1736 files changed, 60567 insertions, 46800 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index a4429bcd609e..8d2ae24b9f4a 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -365,6 +365,9 @@ config HAVE_IRQ_TIME_ACCOUNTING
 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
         bool
 
+config HAVE_ARCH_SOFT_DIRTY
+        bool
+
 config HAVE_MOD_ARCH_SPECIFIC
         bool
         help
diff --git a/arch/alpha/include/asm/mmzone.h b/arch/alpha/include/asm/mmzone.h
index c5b5d6bac9ed..14ce27bccd24 100644
--- a/arch/alpha/include/asm/mmzone.h
+++ b/arch/alpha/include/asm/mmzone.h
@@ -71,8 +71,6 @@ PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
 
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 
-#define VALID_PAGE(page)        (((page) - mem_map) < max_mapnr)
-
 #define pmd_page(pmd)           (pfn_to_page(pmd_val(pmd) >> 32))
 #define pgd_page(pgd)           (pfn_to_page(pgd_val(pgd) >> 32))
 #define pte_pfn(pte)            (pte_val(pte) >> 32)
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 81a4342d5a3f..d8f9b7e89234 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -354,9 +354,6 @@ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 #define kern_addr_valid(addr)   (1)
 #endif
 
-#define io_remap_pfn_range(vma, start, pfn, size, prot) \
-                remap_pfn_range(vma, start, pfn, size, prot)
-
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
diff --git a/arch/alpha/include/uapi/asm/fcntl.h b/arch/alpha/include/uapi/asm/fcntl.h
index 6d9e805f18a7..dfdadb0b4bef 100644
--- a/arch/alpha/include/uapi/asm/fcntl.h
+++ b/arch/alpha/include/uapi/asm/fcntl.h
@@ -32,6 +32,7 @@
 #define O_SYNC          (__O_SYNC|O_DSYNC)
 
 #define O_PATH          040000000
+#define O_TMPFILE       0100000000
 
 #define F_GETLK         7
 #define F_SETLK         8
diff --git a/arch/alpha/kernel/console.c b/arch/alpha/kernel/console.c
index da711e37fc97..6a61deed4a85 100644
--- a/arch/alpha/kernel/console.c
+++ b/arch/alpha/kernel/console.c
@@ -61,7 +61,9 @@ locate_and_init_vga(void *(*sel_func)(void *, void *))
 
         /* Set the VGA hose and init the new console. */
         pci_vga_hose = hose;
-        take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
+        console_lock();
+        do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
+        console_unlock();
 }
 
 void __init
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index b9e37ad6fa19..1402fcc11c2c 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -96,6 +96,7 @@ struct osf_dirent {
 };
 
 struct osf_dirent_callback {
+        struct dir_context ctx;
         struct osf_dirent __user *dirent;
         long __user *basep;
         unsigned int count;
@@ -146,17 +147,17 @@ SYSCALL_DEFINE4(osf_getdirentries, unsigned int, fd,
 {
         int error;
         struct fd arg = fdget(fd);
-        struct osf_dirent_callback buf;
+        struct osf_dirent_callback buf = {
+                .ctx.actor = osf_filldir,
+                .dirent = dirent,
+                .basep = basep,
+                .count = count
+        };
 
         if (!arg.file)
                 return -EBADF;
 
-        buf.dirent = dirent;
-        buf.basep = basep;
-        buf.count = count;
-        buf.error = 0;
-
-        error = vfs_readdir(arg.file, osf_filldir, &buf);
+        error = iterate_dir(arg.file, &buf.ctx);
         if (error >= 0)
                 error = buf.error;
         if (count != buf.count)
diff --git a/arch/alpha/kernel/pci-sysfs.c b/arch/alpha/kernel/pci-sysfs.c
index b51f7b4818cd..2b183b0d3207 100644
--- a/arch/alpha/kernel/pci-sysfs.c
+++ b/arch/alpha/kernel/pci-sysfs.c
@@ -26,7 +26,6 @@ static int hose_mmap_page_range(struct pci_controller *hose,
                 base = sparse ? hose->sparse_io_base : hose->dense_io_base;
 
         vma->vm_pgoff += base >> PAGE_SHIFT;
-        vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
 
         return io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
                                   vma->vm_end - vma->vm_start,
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index ab80a80d38a2..f2360a74e5d5 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -117,7 +117,9 @@ common_shutdown_1(void *generic_ptr)
                 if (in_interrupt())
                         irq_exit();
                 /* This has the effect of resetting the VGA video origin.  */
-                take_over_console(&dummy_con, 0, MAX_NR_CONSOLES-1, 1);
+                console_lock();
+                do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES-1, 1);
+                console_unlock();
 #endif
                 pci_restore_srm_config();
                 set_hae(srm_hae);
diff --git a/arch/alpha/kernel/sys_nautilus.c b/arch/alpha/kernel/sys_nautilus.c
index 1d4aabfcf9a1..837c0fa58317 100644
--- a/arch/alpha/kernel/sys_nautilus.c
+++ b/arch/alpha/kernel/sys_nautilus.c
@@ -238,8 +238,8 @@ nautilus_init_pci(void)
         if (pci_mem < memtop)
                 memtop = pci_mem;
         if (memtop > alpha_mv.min_mem_address) {
-                free_reserved_area((unsigned long)__va(alpha_mv.min_mem_address),
-                                   (unsigned long)__va(memtop), 0, NULL);
+                free_reserved_area(__va(alpha_mv.min_mem_address),
+                                   __va(memtop), -1, NULL);
                 printk("nautilus_init_pci: %ldk freed\n",
                         (memtop - alpha_mv.min_mem_address) >> 10);
         }
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 0ba85ee4a466..a1bea91df56a 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -276,56 +276,25 @@ srm_paging_stop (void)
 }
 #endif
 
-#ifndef CONFIG_DISCONTIGMEM
-static void __init
-printk_memory_info(void)
-{
-        unsigned long codesize, reservedpages, datasize, initsize, tmp;
-        extern int page_is_ram(unsigned long) __init;
-
-        /* printk all informations */
-        reservedpages = 0;
-        for (tmp = 0; tmp < max_low_pfn; tmp++)
-                /*
-                 * Only count reserved RAM pages
-                 */
-                if (page_is_ram(tmp) && PageReserved(mem_map+tmp))
-                        reservedpages++;
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_data;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk("Memory: %luk/%luk available (%luk kernel code, %luk reserved, %luk data, %luk init)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               max_mapnr << (PAGE_SHIFT-10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10);
-}
-
 void __init
 mem_init(void)
 {
-        max_mapnr = num_physpages = max_low_pfn;
-        totalram_pages += free_all_bootmem();
+        set_max_mapnr(max_low_pfn);
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
-
-        printk_memory_info();
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 }
-#endif /* CONFIG_DISCONTIGMEM */
 
 void
 free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void
 free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index 33885048fa36..d543d71c28b4 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -129,8 +129,6 @@ setup_memory_node(int nid, void *kernel_end)
         if (node_max_pfn > max_low_pfn)
                 max_pfn = max_low_pfn = node_max_pfn;
 
-        num_physpages += node_max_pfn - node_min_pfn;
-
 #if 0 /* we'll try this one again in a little while */
         /* Cute trick to make sure our local node data is on local memory */
         node_data[nid] = (pg_data_t *)(__va(node_min_pfn << PAGE_SHIFT));
@@ -321,41 +319,3 @@ void __init paging_init(void)
         /* Initialize the kernel's ZERO_PGE. */
         memset((void *)ZERO_PGE, 0, PAGE_SIZE);
 }
-
-void __init mem_init(void)
-{
-        unsigned long codesize, reservedpages, datasize, initsize, pfn;
-        extern int page_is_ram(unsigned long) __init;
-        unsigned long nid, i;
-        high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
-
-        reservedpages = 0;
-        for_each_online_node(nid) {
-                /*
-                 * This will free up the bootmem, ie, slot 0 memory
-                 */
-                totalram_pages += free_all_bootmem_node(NODE_DATA(nid));
-
-                pfn = NODE_DATA(nid)->node_start_pfn;
-                for (i = 0; i < node_spanned_pages(nid); i++, pfn++)
-                        if (page_is_ram(pfn) &&
-                            PageReserved(nid_page_nr(nid, i)))
-                                reservedpages++;
-        }
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_data;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk("Memory: %luk/%luk available (%luk kernel code, %luk reserved, "
-               "%luk data, %luk init)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               num_physpages << (PAGE_SHIFT-10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10);
-#if 0
-        mem_stress();
-#endif
-}
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 5917099470ea..68fcbb2d59e2 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -34,6 +34,7 @@ config ARC
         select OF
         select OF_EARLY_FLATTREE
         select PERF_USE_VMALLOC
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config SCHED_OMIT_FRAME_POINTER
         def_bool y
@@ -184,6 +185,7 @@ config ARC_CACHE_PAGES
 
 config ARC_CACHE_VIPT_ALIASING
         bool "Support VIPT Aliasing D$"
+        depends on ARC_HAS_DCACHE
         default n
 
 endif   #ARC_CACHE
@@ -361,13 +363,6 @@ config ARC_MISALIGN_ACCESS
           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
           potential bugs in code
 
-config ARC_STACK_NONEXEC
-        bool "Make stack non-executable"
-        default n
-        help
-          To disable the execute permissions of stack/heap of processes
-          which are enabled by default.
-
 config HZ
         int "Timer Frequency"
         default 100
diff --git a/arch/arc/Kconfig.debug b/arch/arc/Kconfig.debug
index 962c6099659e..a7fc0da25650 100644
--- a/arch/arc/Kconfig.debug
+++ b/arch/arc/Kconfig.debug
@@ -15,13 +15,6 @@ config EARLY_PRINTK
           with klogd/syslogd or the X server. You should normally N here,
           unless you want to debug such a crash.
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config 16KSTACKS
         bool "Use 16Kb for kernel stacks instead of 8Kb"
         help
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 183397fd289e..8c0b1aa56f7e 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -9,25 +9,27 @@
 UTS_MACHINE := arc
 
 ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := arc-elf32-
+CROSS_COMPILE := arc-linux-uclibc-
 endif
 
 KBUILD_DEFCONFIG := fpga_defconfig
 
 cflags-y        += -mA7 -fno-common -pipe -fno-builtin -D__linux__
 
-LINUXINCLUDE    +=  -include ${src}/arch/arc/include/asm/defines.h
-
 ifdef CONFIG_ARC_CURR_IN_REG
 # For a global register defintion, make sure it gets passed to every file
 # We had a customer reported bug where some code built in kernel was NOT using
 # any kernel headers, and missing the r25 global register
-# Can't do unconditionally (like above) because of recursive include issues
+# Can't do unconditionally because of recursive include issues
 # due to <linux/thread_info.h>
 LINUXINCLUDE    +=  -include ${src}/arch/arc/include/asm/current.h
 endif
 
-atleast_gcc44 :=  $(call cc-ifversion, -gt, 0402, y)
+upto_gcc42    :=  $(call cc-ifversion, -le, 0402, y)
+upto_gcc44    :=  $(call cc-ifversion, -le, 0404, y)
+atleast_gcc44 :=  $(call cc-ifversion, -ge, 0404, y)
+atleast_gcc48 :=  $(call cc-ifversion, -ge, 0408, y)
+
 cflags-$(atleast_gcc44)                 += -fsection-anchors
 
 cflags-$(CONFIG_ARC_HAS_LLSC)           += -mlock
@@ -35,6 +37,11 @@ cflags-$(CONFIG_ARC_HAS_SWAPE)		+= -mswape
 cflags-$(CONFIG_ARC_HAS_RTSC)           += -mrtsc
 cflags-$(CONFIG_ARC_DW2_UNWIND)         += -fasynchronous-unwind-tables
 
+# By default gcc 4.8 generates dwarf4 which kernel unwinder can't grok
+ifeq ($(atleast_gcc48),y)
+cflags-$(CONFIG_ARC_DW2_UNWIND)         += -gdwarf-2
+endif
+
 ifndef CONFIG_CC_OPTIMIZE_FOR_SIZE
 # Generic build system uses -O2, we want -O3
 cflags-y  += -O3
@@ -48,11 +55,10 @@ cflags-$(disable_small_data)		+= -mno-sdata -fcall-used-gp
 cflags-$(CONFIG_CPU_BIG_ENDIAN)         += -mbig-endian
 ldflags-$(CONFIG_CPU_BIG_ENDIAN)        += -EB
 
-# STAR 9000518362:
+# STAR 9000518362: (fixed with binutils shipping with gcc 4.8)
 # arc-linux-uclibc-ld (buildroot) or arceb-elf32-ld (EZChip) don't accept
-# --build-id w/o "-marclinux".
-# Default arc-elf32-ld is OK
-ldflags-y                               += -marclinux
+# --build-id w/o "-marclinux". Default arc-elf32-ld is OK
+ldflags-$(upto_gcc44)                   += -marclinux
 
 ARC_LIBGCC                              := -mA7
 cflags-$(CONFIG_ARC_HAS_HW_MPY)         += -multcost=16
@@ -66,8 +72,8 @@ ifndef CONFIG_ARC_HAS_HW_MPY
 # With gcc 4.4.7, -mno-mpy is enough to make any other related adjustments,
 # e.g. increased cost of MPY. With gcc 4.2.1 this had to be explicitly hinted
 
-        ARC_LIBGCC              := -marc600
-        ifneq ($(atleast_gcc44),y)
+        ifeq ($(upto_gcc42),y)
+                ARC_LIBGCC      := -marc600
                 cflags-y        += -multcost=30
         endif
 endif
diff --git a/arch/arc/boot/dts/abilis_tb100_dvk.dts b/arch/arc/boot/dts/abilis_tb100_dvk.dts
index 0fa0d4abe795..ebc313a9f5b2 100644
--- a/arch/arc/boot/dts/abilis_tb100_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb100_dvk.dts
@@ -45,19 +45,19 @@
                 };
 
                 i2c0: i2c@FF120000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c1: i2c@FF121000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c2: i2c@FF122000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c3: i2c@FF123000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c4: i2c@FF124000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
 
                 leds {
diff --git a/arch/arc/boot/dts/abilis_tb101_dvk.dts b/arch/arc/boot/dts/abilis_tb101_dvk.dts
index a4d80ce283ae..b204657993aa 100644
--- a/arch/arc/boot/dts/abilis_tb101_dvk.dts
+++ b/arch/arc/boot/dts/abilis_tb101_dvk.dts
@@ -45,19 +45,19 @@
                 };
 
                 i2c0: i2c@FF120000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c1: i2c@FF121000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c2: i2c@FF122000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c3: i2c@FF123000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
                 i2c4: i2c@FF124000 {
-                        sda-hold-time = <432>;
+                        i2c-sda-hold-time-ns = <432>;
                 };
 
                 leds {
diff --git a/arch/arc/configs/fpga_defconfig b/arch/arc/configs/fpga_defconfig
index 95350be6ef6f..c109af320274 100644
--- a/arch/arc/configs/fpga_defconfig
+++ b/arch/arc/configs/fpga_defconfig
@@ -1,4 +1,4 @@
-CONFIG_CROSS_COMPILE="arc-elf32-"
+CONFIG_CROSS_COMPILE="arc-linux-uclibc-"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_DEFAULT_HOSTNAME="ARCLinux"
 # CONFIG_SWAP is not set
diff --git a/arch/arc/configs/nsimosci_defconfig b/arch/arc/configs/nsimosci_defconfig
index 446c96c24eff..451af30914f6 100644
--- a/arch/arc/configs/nsimosci_defconfig
+++ b/arch/arc/configs/nsimosci_defconfig
@@ -1,4 +1,4 @@
-CONFIG_CROSS_COMPILE="arc-elf32-"
+CONFIG_CROSS_COMPILE="arc-linux-uclibc-"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_DEFAULT_HOSTNAME="ARCLinux"
 # CONFIG_SWAP is not set
diff --git a/arch/arc/configs/tb10x_defconfig b/arch/arc/configs/tb10x_defconfig
index 4fa5cd9f2202..6be6492442d6 100644
--- a/arch/arc/configs/tb10x_defconfig
+++ b/arch/arc/configs/tb10x_defconfig
@@ -1,4 +1,4 @@
-CONFIG_CROSS_COMPILE="arc-elf32-"
+CONFIG_CROSS_COMPILE="arc-linux-uclibc-"
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_DEFAULT_HOSTNAME="tb10x"
 CONFIG_SYSVIPC=y
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index 1b907c465666..355cb470c2a4 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -20,7 +20,6 @@
 #define ARC_REG_PERIBASE_BCR    0x69
 #define ARC_REG_FP_BCR          0x6B    /* Single-Precision FPU */
 #define ARC_REG_DPFP_BCR        0x6C    /* Dbl Precision FPU */
-#define ARC_REG_MMU_BCR         0x6f
 #define ARC_REG_DCCM_BCR        0x74    /* DCCM Present + SZ */
 #define ARC_REG_TIMERS_BCR      0x75
 #define ARC_REG_ICCM_BCR        0x78
@@ -34,22 +33,12 @@
 #define ARC_REG_D_UNCACH_BCR    0x6A
 
 /* status32 Bits Positions */
-#define STATUS_H_BIT            0       /* CPU Halted */
-#define STATUS_E1_BIT           1       /* Int 1 enable */
-#define STATUS_E2_BIT           2       /* Int 2 enable */
-#define STATUS_A1_BIT           3       /* Int 1 active */
-#define STATUS_A2_BIT           4       /* Int 2 active */
 #define STATUS_AE_BIT           5       /* Exception active */
 #define STATUS_DE_BIT           6       /* PC is in delay slot */
 #define STATUS_U_BIT            7       /* User/Kernel mode */
 #define STATUS_L_BIT            12      /* Loop inhibit */
 
 /* These masks correspond to the status word(STATUS_32) bits */
-#define STATUS_H_MASK           (1<<STATUS_H_BIT)
-#define STATUS_E1_MASK          (1<<STATUS_E1_BIT)
-#define STATUS_E2_MASK          (1<<STATUS_E2_BIT)
-#define STATUS_A1_MASK          (1<<STATUS_A1_BIT)
-#define STATUS_A2_MASK          (1<<STATUS_A2_BIT)
 #define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
 #define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
 #define STATUS_U_MASK           (1<<STATUS_U_BIT)
@@ -71,6 +60,7 @@
 #define ECR_V_ITLB_MISS                 0x21
 #define ECR_V_DTLB_MISS                 0x22
 #define ECR_V_PROTV                     0x23
+#define ECR_V_TRAP                      0x25
 
 /* Protection Violation Exception Cause Code Values */
 #define ECR_C_PROTV_INST_FETCH          0x00
@@ -79,94 +69,23 @@
 #define ECR_C_PROTV_XCHG                0x03
 #define ECR_C_PROTV_MISALIG_DATA        0x04
 
+#define ECR_C_BIT_PROTV_MISALIG_DATA    10
+
+/* Machine Check Cause Code Values */
+#define ECR_C_MCHK_DUP_TLB              0x01
+
 /* DTLB Miss Exception Cause Code Values */
 #define ECR_C_BIT_DTLB_LD_MISS          8
 #define ECR_C_BIT_DTLB_ST_MISS          9
 
+/* Dummy ECR values for Interrupts */
+#define event_IRQ1              0x0031abcd
+#define event_IRQ2              0x0032abcd
 
 /* Auxiliary registers */
 #define AUX_IDENTITY            4
 #define AUX_INTR_VEC_BASE       0x25
-#define AUX_IRQ_LEV             0x200   /* IRQ Priority: L1 or L2 */
-#define AUX_IRQ_HINT            0x201   /* For generating Soft Interrupts */
-#define AUX_IRQ_LV12            0x43    /* interrupt level register */
-
-#define AUX_IENABLE             0x40c
-#define AUX_ITRIGGER            0x40d
-#define AUX_IPULSE              0x415
-
-/* Timer related Aux registers */
-#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
-#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
-#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
-#define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
-#define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
-#define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
-
-#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
-#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
-
-/* MMU Management regs */
-#define ARC_REG_TLBPD0          0x405
-#define ARC_REG_TLBPD1          0x406
-#define ARC_REG_TLBINDEX        0x407
-#define ARC_REG_TLBCOMMAND      0x408
-#define ARC_REG_PID             0x409
-#define ARC_REG_SCRATCH_DATA0   0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
-
-/* Error code if probe fails */
-#define TLB_LKUP_ERR            0x80000000
-
-/* TLB Commands */
-#define TLBWrite    0x1
-#define TLBRead     0x2
-#define TLBGetIndex 0x3
-#define TLBProbe    0x4
-
-#if (CONFIG_ARC_MMU_VER >= 2)
-#define TLBWriteNI  0x5         /* write JTLB without inv uTLBs */
-#define TLBIVUTLB   0x6         /* explicitly inv uTLBs */
-#else
-#undef TLBWriteNI               /* These cmds don't exist on older MMU */
-#undef TLBIVUTLB
-#endif
 
-/* Instruction cache related Auxiliary registers */
-#define ARC_REG_IC_BCR          0x77    /* Build Config reg */
-#define ARC_REG_IC_IVIC         0x10
-#define ARC_REG_IC_CTRL         0x11
-#define ARC_REG_IC_IVIL         0x19
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_IC_PTAG         0x1E
-#endif
-
-/* Bit val in IC_CTRL */
-#define IC_CTRL_CACHE_DISABLE   0x1
-
-/* Data cache related Auxiliary registers */
-#define ARC_REG_DC_BCR          0x72
-#define ARC_REG_DC_IVDC         0x47
-#define ARC_REG_DC_CTRL         0x48
-#define ARC_REG_DC_IVDL         0x4A
-#define ARC_REG_DC_FLSH         0x4B
-#define ARC_REG_DC_FLDL         0x4C
-#if (CONFIG_ARC_MMU_VER > 2)
-#define ARC_REG_DC_PTAG         0x5C
-#endif
-
-/* Bit val in DC_CTRL */
-#define DC_CTRL_INV_MODE_FLUSH  0x40
-#define DC_CTRL_FLUSH_STATUS    0x100
-
-/* MMU Management regs */
-#define ARC_REG_PID             0x409
-#define ARC_REG_SCRATCH_DATA0   0x418
-
-/* Bits in MMU PID register */
-#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
 
 /*
  * Floating Pt Registers
@@ -293,24 +212,6 @@ struct bcr_identity {
 #endif
 };
 
-struct bcr_mmu_1_2 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
-#else
-        unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
-#endif
-};
-
-struct bcr_mmu_3 {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
-                     u_itlb:4, u_dtlb:4;
-#else
-        unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
-                     ways:4, ver:8;
-#endif
-};
-
 #define EXTN_SWAP_VALID     0x1
 #define EXTN_NORM_VALID     0x2
 #define EXTN_MINMAX_VALID   0x2
@@ -343,14 +244,6 @@ struct bcr_extn_xymem {
 #endif
 };
 
-struct bcr_cache {
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
-#else
-        unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
-#endif
-};
-
 struct bcr_perip {
 #ifdef CONFIG_CPU_BIG_ENDIAN
         unsigned int start:8, pad2:8, sz:8, pad:8;
@@ -403,7 +296,7 @@ struct cpuinfo_arc_mmu {
 };
 
 struct cpuinfo_arc_cache {
-        unsigned int has_aliasing, sz, line_len, assoc, ver;
+        unsigned int sz, line_len, assoc, ver;
 };
 
 struct cpuinfo_arc_ccm {
diff --git a/arch/arc/include/asm/bug.h b/arch/arc/include/asm/bug.h
index 2ad8f9b1c54b..5b18e94c6678 100644
--- a/arch/arc/include/asm/bug.h
+++ b/arch/arc/include/asm/bug.h
@@ -18,9 +18,8 @@ struct task_struct;
 void show_regs(struct pt_regs *regs);
 void show_stacktrace(struct task_struct *tsk, struct pt_regs *regs);
 void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
-                            unsigned long address, unsigned long cause_reg);
-void die(const char *str, struct pt_regs *regs, unsigned long address,
-         unsigned long cause_reg);
+                            unsigned long address);
+void die(const char *str, struct pt_regs *regs, unsigned long address);
 
 #define BUG()   do {                            \
         dump_stack();                                   \
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index d5555fe4742a..5802849a6cae 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -18,21 +18,19 @@
 
 #define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
 
-#define ARC_ICACHE_WAYS 2
-#define ARC_DCACHE_WAYS 4
-
-/* Helpers */
+/* For a rare case where customers have differently config I/D */
 #define ARC_ICACHE_LINE_LEN     L1_CACHE_BYTES
 #define ARC_DCACHE_LINE_LEN     L1_CACHE_BYTES
 
 #define ICACHE_LINE_MASK        (~(ARC_ICACHE_LINE_LEN - 1))
 #define DCACHE_LINE_MASK        (~(ARC_DCACHE_LINE_LEN - 1))
 
-#if ARC_ICACHE_LINE_LEN != ARC_DCACHE_LINE_LEN
-#error "Need to fix some code as I/D cache lines not same"
-#else
-#define is_not_cache_aligned(p) ((unsigned long)p & (~DCACHE_LINE_MASK))
-#endif
+/*
+ * ARC700 doesn't cache any access in top 256M.
+ * Ideal for wiring memory mapped peripherals as we don't need to do
+ * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
+ */
+#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
 
 #ifndef __ASSEMBLY__
 
@@ -57,16 +55,10 @@
 
 #define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
 
-/*
- * ARC700 doesn't cache any access in top 256M.
- * Ideal for wiring memory mapped peripherals as we don't need to do
- * explicit uncached accesses (LD.di/ST.di) hence more portable drivers
- */
-#define ARC_UNCACHED_ADDR_SPACE 0xc0000000
-
 extern void arc_cache_init(void);
 extern char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len);
 extern void __init read_decode_cache_bcr(void);
-#endif
+
+#endif  /* !__ASSEMBLY__ */
 
 #endif /* _ASM_CACHE_H */
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h
index ef62682e8d95..6abc4972bc93 100644
--- a/arch/arc/include/asm/cacheflush.h
+++ b/arch/arc/include/asm/cacheflush.h
@@ -81,16 +81,19 @@ void flush_anon_page(struct vm_area_struct *vma,
 #endif  /* CONFIG_ARC_CACHE_VIPT_ALIASING */
 
 /*
+ * A new pagecache page has PG_arch_1 clear - thus dcache dirty by default
+ * This works around some PIO based drivers which don't call flush_dcache_page
+ * to record that they dirtied the dcache
+ */
+#define PG_dc_clean     PG_arch_1
+
+/*
  * Simple wrapper over config option
  * Bootup code ensures that hardware matches kernel configuration
  */
 static inline int cache_is_vipt_aliasing(void)
 {
-#ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
-        return 1;
-#else
-        return 0;
-#endif
+        return IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING);
 }
 
 #define CACHE_COLOR(addr)       (((unsigned long)(addr) >> (PAGE_SHIFT)) & 1)
diff --git a/arch/arc/include/asm/defines.h b/arch/arc/include/asm/defines.h
deleted file mode 100644
index 6097bb439cc5..000000000000
--- a/arch/arc/include/asm/defines.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARC_ASM_DEFINES_H__
-#define __ARC_ASM_DEFINES_H__
-
-#if defined(CONFIG_ARC_MMU_V1)
-#define CONFIG_ARC_MMU_VER 1
-#elif defined(CONFIG_ARC_MMU_V2)
-#define CONFIG_ARC_MMU_VER 2
-#elif defined(CONFIG_ARC_MMU_V3)
-#define CONFIG_ARC_MMU_VER 3
-#endif
-
-#ifdef CONFIG_ARC_HAS_LLSC
-#define __CONFIG_ARC_HAS_LLSC_VAL 1
-#else
-#define __CONFIG_ARC_HAS_LLSC_VAL 0
-#endif
-
-#ifdef CONFIG_ARC_HAS_SWAPE
-#define __CONFIG_ARC_HAS_SWAPE_VAL 1
-#else
-#define __CONFIG_ARC_HAS_SWAPE_VAL 0
-#endif
-
-#ifdef CONFIG_ARC_HAS_RTSC
-#define __CONFIG_ARC_HAS_RTSC_VAL 1
-#else
-#define __CONFIG_ARC_HAS_RTSC_VAL 0
-#endif
-
-#ifdef CONFIG_ARC_MMU_SASID
-#define __CONFIG_ARC_MMU_SASID_VAL 1
-#else
-#define __CONFIG_ARC_MMU_SASID_VAL 0
-#endif
-
-#ifdef CONFIG_ARC_HAS_ICACHE
-#define __CONFIG_ARC_HAS_ICACHE 1
-#else
-#define __CONFIG_ARC_HAS_ICACHE 0
-#endif
-
-#ifdef CONFIG_ARC_HAS_DCACHE
-#define __CONFIG_ARC_HAS_DCACHE 1
-#else
-#define __CONFIG_ARC_HAS_DCACHE 0
-#endif
-
-#endif /* __ARC_ASM_DEFINES_H__ */
diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h
index eb2ae53187d9..8943c028d4bb 100644
--- a/arch/arc/include/asm/entry.h
+++ b/arch/arc/include/asm/entry.h
@@ -50,194 +50,177 @@
  *      Eff Addr for load = [reg2]
  */
 
+.macro PUSH reg
+        st.a    \reg, [sp, -4]
+.endm
+
+.macro PUSHAX aux
+        lr      r9, [\aux]
+        PUSH    r9
+.endm
+
+.macro POP reg
+        ld.ab   \reg, [sp, 4]
+.endm
+
+.macro POPAX aux
+        POP     r9
+        sr      r9, [\aux]
+.endm
+
 /*--------------------------------------------------------------
- * Save caller saved registers (scratch registers) ( r0 - r12 )
- * Registers are pushed / popped in the order defined in struct ptregs
- * in asm/ptrace.h
+ * Helpers to save/restore Scratch Regs:
+ * used by Interrupt/Exception Prologue/Epilogue
  *-------------------------------------------------------------*/
-.macro  SAVE_CALLER_SAVED
-        st.a    r0, [sp, -4]
-        st.a    r1, [sp, -4]
-        st.a    r2, [sp, -4]
-        st.a    r3, [sp, -4]
-        st.a    r4, [sp, -4]
-        st.a    r5, [sp, -4]
-        st.a    r6, [sp, -4]
-        st.a    r7, [sp, -4]
-        st.a    r8, [sp, -4]
-        st.a    r9, [sp, -4]
-        st.a    r10, [sp, -4]
-        st.a    r11, [sp, -4]
-        st.a    r12, [sp, -4]
+.macro  SAVE_R0_TO_R12
+        PUSH    r0
+        PUSH    r1
+        PUSH    r2
+        PUSH    r3
+        PUSH    r4
+        PUSH    r5
+        PUSH    r6
+        PUSH    r7
+        PUSH    r8
+        PUSH    r9
+        PUSH    r10
+        PUSH    r11
+        PUSH    r12
+.endm
+
+.macro RESTORE_R12_TO_R0
+        POP     r12
+        POP     r11
+        POP     r10
+        POP     r9
+        POP     r8
+        POP     r7
+        POP     r6
+        POP     r5
+        POP     r4
+        POP     r3
+        POP     r2
+        POP     r1
+        POP     r0
+
+#ifdef CONFIG_ARC_CURR_IN_REG
+        ld      r25, [sp, 12]
+#endif
 .endm
 
 /*--------------------------------------------------------------
- * Restore caller saved registers (scratch registers)
+ * Helpers to save/restore callee-saved regs:
+ * used by several macros below
  *-------------------------------------------------------------*/
-.macro RESTORE_CALLER_SAVED
-        ld.ab   r12, [sp, 4]
-        ld.ab   r11, [sp, 4]
-        ld.ab   r10, [sp, 4]
-        ld.ab   r9, [sp, 4]
-        ld.ab   r8, [sp, 4]
-        ld.ab   r7, [sp, 4]
-        ld.ab   r6, [sp, 4]
-        ld.ab   r5, [sp, 4]
-        ld.ab   r4, [sp, 4]
-        ld.ab   r3, [sp, 4]
-        ld.ab   r2, [sp, 4]
-        ld.ab   r1, [sp, 4]
-        ld.ab   r0, [sp, 4]
+.macro SAVE_R13_TO_R24
+        PUSH    r13
+        PUSH    r14
+        PUSH    r15
+        PUSH    r16
+        PUSH    r17
+        PUSH    r18
+        PUSH    r19
+        PUSH    r20
+        PUSH    r21
+        PUSH    r22
+        PUSH    r23
+        PUSH    r24
+.endm
+
+.macro RESTORE_R24_TO_R13
+        POP     r24
+        POP     r23
+        POP     r22
+        POP     r21
+        POP     r20
+        POP     r19
+        POP     r18
+        POP     r17
+        POP     r16
+        POP     r15
+        POP     r14
+        POP     r13
 .endm
 
+#define OFF_USER_R25_FROM_R24   (SZ_CALLEE_REGS + SZ_PT_REGS - 8)/4
 
 /*--------------------------------------------------------------
- * Save callee saved registers (non scratch registers) ( r13 - r25 )
- *  on kernel stack.
- * User mode callee regs need to be saved in case of
- *    -fork and friends for replicating from parent to child
- *    -before going into do_signal( ) for ptrace/core-dump
- * Special case handling is required for r25 in case it is used by kernel
- *  for caching task ptr. Low level exception/ISR save user mode r25
- *  into task->thread.user_r25. So it needs to be retrieved from there and
- *  saved into kernel stack with rest of callee reg-file
+ * Collect User Mode callee regs as struct callee_regs - needed by
+ * fork/do_signal/unaligned-access-emulation.
+ * (By default only scratch regs are saved on entry to kernel)
+ *
+ * Special handling for r25 if used for caching Task Pointer.
+ * It would have been saved in task->thread.user_r25 already, but to keep
+ * the interface same it is copied into regular r25 placeholder in
+ * struct callee_regs.
  *-------------------------------------------------------------*/
 .macro SAVE_CALLEE_SAVED_USER
-        st.a    r13, [sp, -4]
-        st.a    r14, [sp, -4]
-        st.a    r15, [sp, -4]
-        st.a    r16, [sp, -4]
-        st.a    r17, [sp, -4]
-        st.a    r18, [sp, -4]
-        st.a    r19, [sp, -4]
-        st.a    r20, [sp, -4]
-        st.a    r21, [sp, -4]
-        st.a    r22, [sp, -4]
-        st.a    r23, [sp, -4]
-        st.a    r24, [sp, -4]
+
+        SAVE_R13_TO_R24
 
 #ifdef CONFIG_ARC_CURR_IN_REG
         ; Retrieve orig r25 and save it on stack
-        ld      r12, [r25, TASK_THREAD + THREAD_USER_R25]
+        ld.as   r12, [sp, OFF_USER_R25_FROM_R24]
         st.a    r12, [sp, -4]
 #else
-        st.a    r25, [sp, -4]
+        PUSH    r25
 #endif
 
-        /* move up by 1 word to "create" callee_regs->"stack_place_holder" */
-        sub sp, sp, 4
 .endm
 
 /*--------------------------------------------------------------
- * Save callee saved registers (non scratch registers) ( r13 - r25 )
- * kernel mode callee regs needed to be saved in case of context switch
- * If r25 is used for caching task pointer then that need not be saved
- * as it can be re-created from current task global
+ * Save kernel Mode callee regs at the time of Contect Switch.
+ *
+ * Special handling for r25 if used for caching Task Pointer.
+ * Kernel simply skips saving it since it will be loaded with
+ * incoming task pointer anyways
  *-------------------------------------------------------------*/
 .macro SAVE_CALLEE_SAVED_KERNEL
-        st.a    r13, [sp, -4]
-        st.a    r14, [sp, -4]
-        st.a    r15, [sp, -4]
-        st.a    r16, [sp, -4]
-        st.a    r17, [sp, -4]
-        st.a    r18, [sp, -4]
-        st.a    r19, [sp, -4]
-        st.a    r20, [sp, -4]
-        st.a    r21, [sp, -4]
-        st.a    r22, [sp, -4]
-        st.a    r23, [sp, -4]
-        st.a    r24, [sp, -4]
+
+        SAVE_R13_TO_R24
+
 #ifdef CONFIG_ARC_CURR_IN_REG
-        sub     sp, sp, 8
-#else
-        st.a    r25, [sp, -4]
         sub     sp, sp, 4
+#else
+        PUSH    r25
 #endif
 .endm
 
 /*--------------------------------------------------------------
- * RESTORE_CALLEE_SAVED_KERNEL:
- * Loads callee (non scratch) Reg File by popping from Kernel mode stack.
- *  This is reverse of SAVE_CALLEE_SAVED,
- *
- * NOTE:
- * Ideally this shd only be called in switch_to for loading
- *  switched-IN task's CALLEE Reg File.
- *  For all other cases RESTORE_CALLEE_SAVED_FAST must be used
- *  which simply pops the stack w/o touching regs.
+ * Opposite of SAVE_CALLEE_SAVED_KERNEL
  *-------------------------------------------------------------*/
 .macro RESTORE_CALLEE_SAVED_KERNEL
 
-
 #ifdef CONFIG_ARC_CURR_IN_REG
-        add     sp, sp, 8  /* skip callee_reg gutter and user r25 placeholder */
+        add     sp, sp, 4  /* skip usual r25 placeholder */
 #else
-        add     sp, sp, 4   /* skip "callee_regs->stack_place_holder" */
-        ld.ab   r25, [sp, 4]
+        POP     r25
 #endif
-
-        ld.ab   r24, [sp, 4]
-        ld.ab   r23, [sp, 4]
-        ld.ab   r22, [sp, 4]
-        ld.ab   r21, [sp, 4]
-        ld.ab   r20, [sp, 4]
-        ld.ab   r19, [sp, 4]
-        ld.ab   r18, [sp, 4]
-        ld.ab   r17, [sp, 4]
-        ld.ab   r16, [sp, 4]
-        ld.ab   r15, [sp, 4]
-        ld.ab   r14, [sp, 4]
-        ld.ab   r13, [sp, 4]
-
+        RESTORE_R24_TO_R13
 .endm
 
 /*--------------------------------------------------------------
- * RESTORE_CALLEE_SAVED_USER:
- * This is called after do_signal where tracer might have changed callee regs
- * thus we need to restore the reg file.
- * Special case handling is required for r25 in case it is used by kernel
- *  for caching task ptr. Ptrace would have modified on-kernel-stack value of
- *  r25, which needs to be shoved back into task->thread.user_r25 where from
- *  Low level exception/ISR return code will retrieve to populate with rest of
- *  callee reg-file.
+ * Opposite of SAVE_CALLEE_SAVED_USER
+ *
+ * ptrace tracer or unaligned-access fixup might have changed a user mode
+ * callee reg which is saved back to usual r25 storage location
  *-------------------------------------------------------------*/
 .macro RESTORE_CALLEE_SAVED_USER
 
-        add     sp, sp, 4   /* skip "callee_regs->stack_place_holder" */
-
 #ifdef CONFIG_ARC_CURR_IN_REG
         ld.ab   r12, [sp, 4]
-        st      r12, [r25, TASK_THREAD + THREAD_USER_R25]
+        st.as   r12, [sp, OFF_USER_R25_FROM_R24]
 #else
-        ld.ab   r25, [sp, 4]
+        POP     r25
 #endif
-
-        ld.ab   r24, [sp, 4]
-        ld.ab   r23, [sp, 4]
-        ld.ab   r22, [sp, 4]
-        ld.ab   r21, [sp, 4]
-        ld.ab   r20, [sp, 4]
-        ld.ab   r19, [sp, 4]
-        ld.ab   r18, [sp, 4]
-        ld.ab   r17, [sp, 4]
-        ld.ab   r16, [sp, 4]
-        ld.ab   r15, [sp, 4]
-        ld.ab   r14, [sp, 4]
-        ld.ab   r13, [sp, 4]
+        RESTORE_R24_TO_R13
 .endm
 
 /*--------------------------------------------------------------
  * Super FAST Restore callee saved regs by simply re-adjusting SP
  *-------------------------------------------------------------*/
 .macro DISCARD_CALLEE_SAVED_USER
-        add     sp, sp, 14 * 4
-.endm
-
-/*--------------------------------------------------------------
- * Restore User mode r25 saved in task_struct->thread.user_r25
- *-------------------------------------------------------------*/
-.macro RESTORE_USER_R25
-        ld  r25, [r25, TASK_THREAD + THREAD_USER_R25]
+        add     sp, sp, SZ_CALLEE_REGS
 .endm
 
 /*-------------------------------------------------------------
@@ -252,7 +235,7 @@
         ld  \out, [\tsk, TASK_THREAD_INFO]
 
         /* Go to end of page where stack begins (grows upwards) */
-        add2 \out, \out, (THREAD_SIZE - 4)/4   /* one word GUTTER */
+        add2 \out, \out, (THREAD_SIZE)/4
 
 .endm
 
@@ -305,33 +288,28 @@
          * safe-keeping not really needed, but it keeps the epilogue code
          * (SP restore) simpler/uniform.
          */
-        b.d     77f
-
-        st.a    sp, [sp, -12]   ; Make room for orig_r0 and orig_r8
+        b.d     66f
+        mov     r9, sp
 
 88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
 
         GET_CURR_TASK_ON_CPU   r9
 
-#ifdef CONFIG_ARC_CURR_IN_REG
-
-        /* If current task pointer cached in r25, time to
-         *  -safekeep USER r25 in task->thread_struct->user_r25
-         *  -load r25 with current task ptr
-         */
-        st.as   r25, [r9, (TASK_THREAD + THREAD_USER_R25)/4]
-        mov     r25, r9
-#endif
-
         /* With current tsk in r9, get it's kernel mode stack base */
         GET_TSK_STACK_BASE  r9, r9
 
-#ifdef PT_REGS_CANARY
-        st      0xabcdabcd, [r9, 0]
+66:
+#ifdef CONFIG_ARC_CURR_IN_REG
+        /*
+         * Treat r25 as scratch reg, save it on stack first
+         * Load it with current task pointer
+         */
+        st      r25, [r9, -4]
+        GET_CURR_TASK_ON_CPU   r25
 #endif
 
         /* Save Pre Intr/Exception User SP on kernel stack */
-        st.a    sp, [r9, -12]   ; Make room for orig_r0 and orig_r8
+        st.a    sp, [r9, -16]   ; Make room for orig_r0, ECR, user_r25
 
         /* CAUTION:
          * SP should be set at the very end when we are done with everything
@@ -342,7 +320,7 @@
         /* set SP to point to kernel mode stack */
         mov sp, r9
 
-77: /* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */
+        /* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */
 
 .endm
 
@@ -369,7 +347,7 @@
  * @reg [OUT] &thread_info of "current"
  */
 .macro GET_CURR_THR_INFO_FROM_SP  reg
-        and \reg, sp, ~(THREAD_SIZE - 1)
+        bic \reg, sp, (THREAD_SIZE - 1)
 .endm
 
 /*
@@ -413,62 +391,25 @@
  * Note that syscalls are implemented via TRAP which is also a exception
  * from CPU's point of view
  *-------------------------------------------------------------*/
-.macro SAVE_ALL_EXCEPTION   marker
+.macro SAVE_ALL_SYS
 
-        st      \marker, [sp, 8]        /* orig_r8 */
+        lr      r9, [ecr]
+        st      r9, [sp, 8]    /* ECR */
         st      r0, [sp, 4]    /* orig_r0, needed only for sys calls */
 
         /* Restore r9 used to code the early prologue */
         EXCPN_PROLOG_RESTORE_REG  r9
 
-        SAVE_CALLER_SAVED
-        st.a    r26, [sp, -4]   /* gp */
-        st.a    fp, [sp, -4]
-        st.a    blink, [sp, -4]
-        lr      r9, [eret]
-        st.a    r9, [sp, -4]
-        lr      r9, [erstatus]
-        st.a    r9, [sp, -4]
-        st.a    lp_count, [sp, -4]
-        lr      r9, [lp_end]
-        st.a    r9, [sp, -4]
-        lr      r9, [lp_start]
-        st.a    r9, [sp, -4]
-        lr      r9, [erbta]
-        st.a    r9, [sp, -4]
-
-#ifdef PT_REGS_CANARY
-        mov   r9, 0xdeadbeef
-        st    r9, [sp, -4]
-#endif
-
-        /* move up by 1 word to "create" pt_regs->"stack_place_holder" */
-        sub sp, sp, 4
-.endm
-
-/*--------------------------------------------------------------
- * Save scratch regs for exceptions
- *-------------------------------------------------------------*/
-.macro SAVE_ALL_SYS
-        SAVE_ALL_EXCEPTION  orig_r8_IS_EXCPN
-.endm
-
-/*--------------------------------------------------------------
- * Save scratch regs for sys calls
- *-------------------------------------------------------------*/
-.macro SAVE_ALL_TRAP
-        /*
-         * Setup pt_regs->orig_r8.
-         * Encode syscall number (r8) in upper short word of event type (r9)
-         * N.B. #1: This is already endian safe (see ptrace.h)
-         *      #2: Only r9 can be used as scratch as it is already clobbered
-         *          and it's contents are no longer needed by the latter part
-         *          of exception prologue
-         */
-        lsl  r9, r8, 16
-        or   r9, r9, orig_r8_IS_SCALL
-
-        SAVE_ALL_EXCEPTION  r9
+        SAVE_R0_TO_R12
+        PUSH    gp
+        PUSH    fp
+        PUSH    blink
+        PUSHAX  eret
+        PUSHAX  erstatus
+        PUSH    lp_count
+        PUSHAX  lp_end
+        PUSHAX  lp_start
+        PUSHAX  erbta
 .endm
 
 /*--------------------------------------------------------------
@@ -483,28 +424,22 @@
  * by hardware and that is not good.
  *-------------------------------------------------------------*/
 .macro RESTORE_ALL_SYS
+        POPAX   erbta
+        POPAX   lp_start
+        POPAX   lp_end
+
+        POP     r9
+        mov     lp_count, r9    ;LD to lp_count is not allowed
 
-        add sp, sp, 4       /* hop over unused "pt_regs->stack_place_holder" */
-
-        ld.ab   r9, [sp, 4]
-        sr      r9, [erbta]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_start]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_end]
-        ld.ab   r9, [sp, 4]
-        mov     lp_count, r9
-        ld.ab   r9, [sp, 4]
-        sr      r9, [erstatus]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [eret]
-        ld.ab   blink, [sp, 4]
-        ld.ab   fp, [sp, 4]
-        ld.ab   r26, [sp, 4]    /* gp */
-        RESTORE_CALLER_SAVED
+        POPAX   erstatus
+        POPAX   eret
+        POP     blink
+        POP     fp
+        POP     gp
+        RESTORE_R12_TO_R0
 
         ld  sp, [sp] /* restore original sp */
-        /* orig_r0 and orig_r8 skipped automatically */
+        /* orig_r0, ECR, user_r25 skipped automatically */
 .endm
 
 
@@ -513,9 +448,7 @@
  *-------------------------------------------------------------*/
 .macro SAVE_ALL_INT1
 
-        /* restore original r9 , saved in int1_saved_reg
-        * It will be saved on stack in macro: SAVE_CALLER_SAVED
-        */
+        /* restore original r9 to be saved as part of reg-file */
 #ifdef CONFIG_SMP
         lr  r9, [ARC_REG_SCRATCH_DATA0]
 #else
@@ -523,29 +456,19 @@
 #endif
 
         /* now we are ready to save the remaining context :) */
-        st      orig_r8_IS_IRQ1, [sp, 8]    /* Event Type */
+        st      event_IRQ1, [sp, 8]    /* Dummy ECR */
         st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */
-        SAVE_CALLER_SAVED
-        st.a    r26, [sp, -4]   /* gp */
-        st.a    fp, [sp, -4]
-        st.a    blink, [sp, -4]
-        st.a    ilink1, [sp, -4]
-        lr      r9, [status32_l1]
-        st.a    r9, [sp, -4]
-        st.a    lp_count, [sp, -4]
-        lr      r9, [lp_end]
-        st.a    r9, [sp, -4]
-        lr      r9, [lp_start]
-        st.a    r9, [sp, -4]
-        lr      r9, [bta_l1]
-        st.a    r9, [sp, -4]
-
-#ifdef PT_REGS_CANARY
-        mov   r9, 0xdeadbee1
-        st    r9, [sp, -4]
-#endif
-        /* move up by 1 word to "create" pt_regs->"stack_place_holder" */
-        sub sp, sp, 4
+
+        SAVE_R0_TO_R12
+        PUSH    gp
+        PUSH    fp
+        PUSH    blink
+        PUSH    ilink1
+        PUSHAX  status32_l1
+        PUSH    lp_count
+        PUSHAX  lp_end
+        PUSHAX  lp_start
+        PUSHAX  bta_l1
 .endm
 
 .macro SAVE_ALL_INT2
@@ -558,30 +481,19 @@
         ld  r9, [@int2_saved_reg]
 
         /* now we are ready to save the remaining context :) */
-        st      orig_r8_IS_IRQ2, [sp, 8]    /* Event Type */
+        st      event_IRQ2, [sp, 8]    /* Dummy ECR */
         st      0, [sp, 4]    /* orig_r0 , N/A for IRQ */
-        SAVE_CALLER_SAVED
-        st.a    r26, [sp, -4]   /* gp */
-        st.a    fp, [sp, -4]
-        st.a    blink, [sp, -4]
-        st.a    ilink2, [sp, -4]
-        lr      r9, [status32_l2]
-        st.a    r9, [sp, -4]
-        st.a    lp_count, [sp, -4]
-        lr      r9, [lp_end]
-        st.a    r9, [sp, -4]
-        lr      r9, [lp_start]
-        st.a    r9, [sp, -4]
-        lr      r9, [bta_l2]
-        st.a    r9, [sp, -4]
-
-#ifdef PT_REGS_CANARY
-        mov   r9, 0xdeadbee2
-        st    r9, [sp, -4]
-#endif
 
-        /* move up by 1 word to "create" pt_regs->"stack_place_holder" */
-        sub sp, sp, 4
+        SAVE_R0_TO_R12
+        PUSH    gp
+        PUSH    fp
+        PUSH    blink
+        PUSH    ilink2
+        PUSHAX  status32_l2
+        PUSH    lp_count
+        PUSHAX  lp_end
+        PUSHAX  lp_start
+        PUSHAX  bta_l2
 .endm
 
 /*--------------------------------------------------------------
@@ -595,52 +507,41 @@
  *-------------------------------------------------------------*/
 
 .macro RESTORE_ALL_INT1
-        add sp, sp, 4       /* hop over unused "pt_regs->stack_place_holder" */
-
-        ld.ab   r9, [sp, 4] /* Actual reg file */
-        sr      r9, [bta_l1]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_start]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_end]
-        ld.ab   r9, [sp, 4]
-        mov     lp_count, r9
-        ld.ab   r9, [sp, 4]
-        sr      r9, [status32_l1]
-        ld.ab   r9, [sp, 4]
-        mov     ilink1, r9
-        ld.ab   blink, [sp, 4]
-        ld.ab   fp, [sp, 4]
-        ld.ab   r26, [sp, 4]    /* gp */
-        RESTORE_CALLER_SAVED
+        POPAX   bta_l1
+        POPAX   lp_start
+        POPAX   lp_end
+
+        POP     r9
+        mov     lp_count, r9    ;LD to lp_count is not allowed
+
+        POPAX   status32_l1
+        POP     ilink1
+        POP     blink
+        POP     fp
+        POP     gp
+        RESTORE_R12_TO_R0
 
         ld  sp, [sp] /* restore original sp */
-        /* orig_r0 and orig_r8 skipped automatically */
+        /* orig_r0, ECR, user_r25 skipped automatically */
 .endm
 
 .macro RESTORE_ALL_INT2
-        add sp, sp, 4       /* hop over unused "pt_regs->stack_place_holder" */
-
-        ld.ab   r9, [sp, 4]
-        sr      r9, [bta_l2]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_start]
-        ld.ab   r9, [sp, 4]
-        sr      r9, [lp_end]
-        ld.ab   r9, [sp, 4]
-        mov     lp_count, r9
-        ld.ab   r9, [sp, 4]
-        sr      r9, [status32_l2]
-        ld.ab   r9, [sp, 4]
-        mov     ilink2, r9
-        ld.ab   blink, [sp, 4]
-        ld.ab   fp, [sp, 4]
-        ld.ab   r26, [sp, 4]    /* gp */
-        RESTORE_CALLER_SAVED
+        POPAX   bta_l2
+        POPAX   lp_start
+        POPAX   lp_end
 
-        ld  sp, [sp] /* restore original sp */
-        /* orig_r0 and orig_r8 skipped automatically */
+        POP     r9
+        mov     lp_count, r9    ;LD to lp_count is not allowed
 
+        POPAX   status32_l2
+        POP     ilink2
+        POP     blink
+        POP     fp
+        POP     gp
+        RESTORE_R12_TO_R0
+
+        ld  sp, [sp] /* restore original sp */
+        /* orig_r0, ECR, user_r25 skipped automatically */
 .endm
 
 
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 57898a17eb82..c0a72105ee0b 100644
--- a/arch/arc/include/asm/irq.h
+++ b/arch/arc/include/asm/irq.h
@@ -21,6 +21,6 @@
 extern void __init arc_init_IRQ(void);
 extern int __init get_hw_config_num_irq(void);
 
-void __cpuinit arc_local_timer_setup(unsigned int cpu);
+void arc_local_timer_setup(unsigned int cpu);
 
 #endif
diff --git a/arch/arc/include/asm/irqflags.h b/arch/arc/include/asm/irqflags.h
index eac071668201..d99f79bcf865 100644
--- a/arch/arc/include/asm/irqflags.h
+++ b/arch/arc/include/asm/irqflags.h
@@ -19,6 +19,26 @@
 
 #include <asm/arcregs.h>
 
+/* status32 Reg bits related to Interrupt Handling */
+#define STATUS_E1_BIT           1       /* Int 1 enable */
+#define STATUS_E2_BIT           2       /* Int 2 enable */
+#define STATUS_A1_BIT           3       /* Int 1 active */
+#define STATUS_A2_BIT           4       /* Int 2 active */
+
+#define STATUS_E1_MASK          (1<<STATUS_E1_BIT)
+#define STATUS_E2_MASK          (1<<STATUS_E2_BIT)
+#define STATUS_A1_MASK          (1<<STATUS_A1_BIT)
+#define STATUS_A2_MASK          (1<<STATUS_A2_BIT)
+
+/* Other Interrupt Handling related Aux regs */
+#define AUX_IRQ_LEV             0x200   /* IRQ Priority: L1 or L2 */
+#define AUX_IRQ_HINT            0x201   /* For generating Soft Interrupts */
+#define AUX_IRQ_LV12            0x43    /* interrupt level register */
+
+#define AUX_IENABLE             0x40c
+#define AUX_ITRIGGER            0x40d
+#define AUX_IPULSE              0x415
+
 #ifndef __ASSEMBLY__
 
 /******************************************************************
diff --git a/arch/arc/include/asm/kgdb.h b/arch/arc/include/asm/kgdb.h
index 4930957ca3d3..b65fca7ffeb5 100644
--- a/arch/arc/include/asm/kgdb.h
+++ b/arch/arc/include/asm/kgdb.h
@@ -31,7 +31,7 @@ static inline void arch_kgdb_breakpoint(void)
         __asm__ __volatile__ ("trap_s   0x4\n");
 }
 
-extern void kgdb_trap(struct pt_regs *regs, int param);
+extern void kgdb_trap(struct pt_regs *regs);
 
 enum arc700_linux_regnums {
         _R0             = 0,
@@ -53,7 +53,7 @@ enum arc700_linux_regnums {
 };
 
 #else
-#define kgdb_trap(regs, param)
+#define kgdb_trap(regs)
 #endif
 
 #endif  /* __ARC_KGDB_H__ */
diff --git a/arch/arc/include/asm/kprobes.h b/arch/arc/include/asm/kprobes.h
index 4d9c211fce70..944dbedb38b5 100644
--- a/arch/arc/include/asm/kprobes.h
+++ b/arch/arc/include/asm/kprobes.h
@@ -50,11 +50,9 @@ struct kprobe_ctlblk {
 
 int kprobe_fault_handler(struct pt_regs *regs, unsigned long cause);
 void kretprobe_trampoline(void);
-void trap_is_kprobe(unsigned long cause, unsigned long address,
-                           struct pt_regs *regs);
+void trap_is_kprobe(unsigned long address, struct pt_regs *regs);
 #else
-static void trap_is_kprobe(unsigned long cause, unsigned long address,
-                           struct pt_regs *regs)
+static void trap_is_kprobe(unsigned long address, struct pt_regs *regs)
 {
 }
 #endif
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h
index 56b02320f1a9..7c03fe61759c 100644
--- a/arch/arc/include/asm/mmu.h
+++ b/arch/arc/include/asm/mmu.h
@@ -9,6 +9,40 @@
 #ifndef _ASM_ARC_MMU_H
 #define _ASM_ARC_MMU_H
 
+#if defined(CONFIG_ARC_MMU_V1)
+#define CONFIG_ARC_MMU_VER 1
+#elif defined(CONFIG_ARC_MMU_V2)
+#define CONFIG_ARC_MMU_VER 2
+#elif defined(CONFIG_ARC_MMU_V3)
+#define CONFIG_ARC_MMU_VER 3
+#endif
+
+/* MMU Management regs */
+#define ARC_REG_MMU_BCR         0x06f
+#define ARC_REG_TLBPD0          0x405
+#define ARC_REG_TLBPD1          0x406
+#define ARC_REG_TLBINDEX        0x407
+#define ARC_REG_TLBCOMMAND      0x408
+#define ARC_REG_PID             0x409
+#define ARC_REG_SCRATCH_DATA0   0x418
+
+/* Bits in MMU PID register */
+#define MMU_ENABLE              (1 << 31)       /* Enable MMU for process */
+
+/* Error code if probe fails */
+#define TLB_LKUP_ERR            0x80000000
+
+/* TLB Commands */
+#define TLBWrite    0x1
+#define TLBRead     0x2
+#define TLBGetIndex 0x3
+#define TLBProbe    0x4
+
+#if (CONFIG_ARC_MMU_VER >= 2)
+#define TLBWriteNI  0x5         /* write JTLB without inv uTLBs */
+#define TLBIVUTLB   0x6         /* explicitly inv uTLBs */
+#endif
+
 #ifndef __ASSEMBLY__
 
 typedef struct {
@@ -18,6 +52,16 @@ typedef struct {
 #endif
 } mm_context_t;
 
+#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
+void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
+#else
+#define tlb_paranoid_check(a, b)
 #endif
 
+void arc_mmu_init(void);
+extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
+void __init read_decode_mmu_bcr(void);
+
+#endif  /* !__ASSEMBLY__ */
+
 #endif
diff --git a/arch/arc/include/asm/page.h b/arch/arc/include/asm/page.h
index ab84bf131fe1..9c8aa41e45c2 100644
--- a/arch/arc/include/asm/page.h
+++ b/arch/arc/include/asm/page.h
@@ -96,13 +96,8 @@ typedef unsigned long pgtable_t;
 
 #define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
 
-/* Default Permissions for page, used in mmap.c */
-#ifdef CONFIG_ARC_STACK_NONEXEC
+/* Default Permissions for stack/heaps pages (Non Executable) */
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE)
-#else
-#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
-                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-#endif
 
 #define WANT_PAGE_VIRTUAL   1
 
diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index 95b1522212a7..4749a0eee1cf 100644
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -135,6 +135,12 @@
 /* ioremap */
 #define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
 
+/* Masks for actual TLB "PD"s */
+#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
+#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
+                         _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
+                         _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
+
 /**************************************************************************
  * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
  *
@@ -394,9 +400,6 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
  * remap a physical page `pfn' of size `size' with page protection `prot'
  * into virtual address `from'
  */
-#define io_remap_pfn_range(vma, from, pfn, size, prot) \
-                        remap_pfn_range(vma, from, pfn, size, prot)
-
 #include <asm-generic/pgtable.h>
 
 /* to cope with aliasing VIPT cache */
diff --git a/arch/arc/include/asm/processor.h b/arch/arc/include/asm/processor.h
index 5f26b2c1cba0..15334ab66b56 100644
--- a/arch/arc/include/asm/processor.h
+++ b/arch/arc/include/asm/processor.h
@@ -19,6 +19,7 @@
 #ifndef __ASSEMBLY__
 
 #include <asm/arcregs.h>        /* for STATUS_E1_MASK et all */
+#include <asm/ptrace.h>
 
 /* Arch specific stuff which needs to be saved per task.
  * However these items are not so important so as to earn a place in
@@ -28,10 +29,6 @@ struct thread_struct {
         unsigned long ksp;      /* kernel mode stack pointer */
         unsigned long callee_reg;       /* pointer to callee regs */
         unsigned long fault_address;    /* dbls as brkpt holder as well */
-        unsigned long cause_code;       /* Exception Cause Code (ECR) */
-#ifdef CONFIG_ARC_CURR_IN_REG
-        unsigned long user_r25;
-#endif
 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE
         struct arc_fpu fpu;
 #endif
@@ -50,7 +47,7 @@ struct task_struct;
 unsigned long thread_saved_pc(struct task_struct *t);
 
 #define task_pt_regs(p) \
-        ((struct pt_regs *)(THREAD_SIZE - 4 + (void *)task_stack_page(p)) - 1)
+        ((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
 
 /* Free all resources held by a thread. */
 #define release_thread(thread) do { } while (0)
@@ -75,11 +72,15 @@ unsigned long thread_saved_pc(struct task_struct *t);
 
 /*
  * Where abouts of Task's sp, fp, blink when it was last seen in kernel mode.
- * These can't be derived from pt_regs as that would give correp user-mode val
+ * Look in process.c for details of kernel stack layout
  */
 #define KSTK_ESP(tsk)   (tsk->thread.ksp)
-#define KSTK_BLINK(tsk) (*((unsigned int *)((KSTK_ESP(tsk)) + (13+1+1)*4)))
-#define KSTK_FP(tsk)    (*((unsigned int *)((KSTK_ESP(tsk)) + (13+1)*4)))
+
+#define KSTK_REG(tsk, off)      (*((unsigned int *)(KSTK_ESP(tsk) + \
+                                        sizeof(struct callee_regs) + off)))
+
+#define KSTK_BLINK(tsk) KSTK_REG(tsk, 4)
+#define KSTK_FP(tsk)    KSTK_REG(tsk, 0)
 
 /*
  * Do necessary setup to start up a newly executed thread.
diff --git a/arch/arc/include/asm/ptrace.h b/arch/arc/include/asm/ptrace.h
index 6179de7e07c2..c9938e7a7dbd 100644
--- a/arch/arc/include/asm/ptrace.h
+++ b/arch/arc/include/asm/ptrace.h
@@ -17,12 +17,6 @@
 /* THE pt_regs: Defines how regs are saved during entry into kernel */
 
 struct pt_regs {
-        /*
-         * 1 word gutter after reg-file has been saved
-         * Technically not needed, Since SP always points to a "full" location
-         * (vs. "empty"). But pt_regs is shared with tools....
-         */
-        long res;
 
         /* Real registers */
         long bta;       /* bta_l1, bta_l2, erbta */
@@ -50,22 +44,32 @@ struct pt_regs {
         long sp;        /* user/kernel sp depending on where we came from  */
         long orig_r0;
 
-        /*to distinguish bet excp, syscall, irq */
+        /*
+         * To distinguish bet excp, syscall, irq
+         * For traps and exceptions, Exception Cause Register.
+         *      ECR: <00> <VV> <CC> <PP>
+         *      Last word used by Linux for extra state mgmt (syscall-restart)
+         * For interrupts, use artificial ECR values to note current prio-level
+         */
         union {
+                struct {
 #ifdef CONFIG_CPU_BIG_ENDIAN
-                /* so that assembly code is same for LE/BE */
-                unsigned long orig_r8:16, event:16;
+                        unsigned long state:8, ecr_vec:8,
+                                      ecr_cause:8, ecr_param:8;
 #else
-                unsigned long event:16, orig_r8:16;
+                        unsigned long ecr_param:8, ecr_cause:8,
+                                      ecr_vec:8, state:8;
 #endif
-                long orig_r8_word;
+                };
+                unsigned long event;
         };
+
+        long user_r25;
 };
 
 /* Callee saved registers - need to be saved only when you are scheduled out */
 
 struct callee_regs {
-        long res;       /* Again this is not needed */
         long r25;
         long r24;
         long r23;
@@ -99,18 +103,20 @@ struct callee_regs {
 /* return 1 if PC in delay slot */
 #define delay_mode(regs) ((regs->status32 & STATUS_DE_MASK) == STATUS_DE_MASK)
 
-#define in_syscall(regs)    (regs->event & orig_r8_IS_SCALL)
-#define in_brkpt_trap(regs) (regs->event & orig_r8_IS_BRKPT)
+#define in_syscall(regs)    ((regs->ecr_vec == ECR_V_TRAP) && !regs->ecr_param)
+#define in_brkpt_trap(regs) ((regs->ecr_vec == ECR_V_TRAP) && regs->ecr_param)
+
+#define STATE_SCALL_RESTARTED   0x01
 
-#define syscall_wont_restart(regs) (regs->event |= orig_r8_IS_SCALL_RESTARTED)
-#define syscall_restartable(regs) !(regs->event &  orig_r8_IS_SCALL_RESTARTED)
+#define syscall_wont_restart(reg) (reg->state |= STATE_SCALL_RESTARTED)
+#define syscall_restartable(reg) !(reg->state &  STATE_SCALL_RESTARTED)
 
 #define current_pt_regs()                                       \
 ({                                                              \
         /* open-coded current_thread_info() */                  \
         register unsigned long sp asm ("sp");                   \
         unsigned long pg_start = (sp & ~(THREAD_SIZE - 1));     \
-        (struct pt_regs *)(pg_start + THREAD_SIZE - 4) - 1;     \
+        (struct pt_regs *)(pg_start + THREAD_SIZE) - 1; \
 })
 
 static inline long regs_return_value(struct pt_regs *regs)
@@ -120,11 +126,4 @@ static inline long regs_return_value(struct pt_regs *regs)
 
 #endif /* !__ASSEMBLY__ */
 
-#define orig_r8_IS_SCALL                0x0001
-#define orig_r8_IS_SCALL_RESTARTED      0x0002
-#define orig_r8_IS_BRKPT                0x0004
-#define orig_r8_IS_EXCPN                0x0008
-#define orig_r8_IS_IRQ1                 0x0010
-#define orig_r8_IS_IRQ2                 0x0020
-
 #endif /* __ASM_PTRACE_H */
diff --git a/arch/arc/include/asm/syscall.h b/arch/arc/include/asm/syscall.h
index 33ab3048e9b2..29de09804306 100644
--- a/arch/arc/include/asm/syscall.h
+++ b/arch/arc/include/asm/syscall.h
@@ -18,7 +18,7 @@ static inline long
 syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 {
         if (user_mode(regs) && in_syscall(regs))
-                return regs->orig_r8;
+                return regs->r8;
         else
                 return -1;
 }
@@ -26,8 +26,7 @@ syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
 static inline void
 syscall_rollback(struct task_struct *task, struct pt_regs *regs)
 {
-        /* XXX: I can't fathom how pt_regs->r8 will be clobbered ? */
-        regs->r8 = regs->orig_r8;
+        regs->r0 = regs->orig_r0;
 }
 
 static inline long
diff --git a/arch/arc/include/asm/tlb-mmu1.h b/arch/arc/include/asm/tlb-mmu1.h
index a5ff961b1efc..8a1ec96012ae 100644
--- a/arch/arc/include/asm/tlb-mmu1.h
+++ b/arch/arc/include/asm/tlb-mmu1.h
@@ -9,9 +9,9 @@
 #ifndef __ASM_TLB_MMU_V1_H__
 #define __ASM_TLB_MMU_V1_H__
 
-#if defined(__ASSEMBLY__) && defined(CONFIG_ARC_MMU_VER == 1)
+#include <asm/mmu.h>
 
-#include <asm/tlb.h>
+#if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
 
 .macro TLB_WRITE_HEURISTICS
 
diff --git a/arch/arc/include/asm/tlb.h b/arch/arc/include/asm/tlb.h
index cb0c708ca665..a9db5f62aaf3 100644
--- a/arch/arc/include/asm/tlb.h
+++ b/arch/arc/include/asm/tlb.h
@@ -9,18 +9,6 @@
 #ifndef _ASM_ARC_TLB_H
 #define _ASM_ARC_TLB_H
 
-#ifdef __KERNEL__
-
-#include <asm/pgtable.h>
-
-/* Masks for actual TLB "PD"s */
-#define PTE_BITS_IN_PD0 (_PAGE_GLOBAL | _PAGE_PRESENT)
-#define PTE_BITS_IN_PD1 (PAGE_MASK | _PAGE_CACHEABLE | \
-                         _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
-                         _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
-
-#ifndef __ASSEMBLY__
-
 #define tlb_flush(tlb)                          \
 do {                                            \
         if (tlb->fullmm)                        \
@@ -56,18 +44,4 @@ do {									\
 #include <linux/pagemap.h>
 #include <asm-generic/tlb.h>
 
-#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
-void tlb_paranoid_check(unsigned int pid_sw, unsigned long address);
-#else
-#define tlb_paranoid_check(a, b)
-#endif
-
-void arc_mmu_init(void);
-extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
-void __init read_decode_mmu_bcr(void);
-
-#endif  /* __ASSEMBLY__ */
-
-#endif  /* __KERNEL__ */
-
 #endif /* _ASM_ARC_TLB_H */
diff --git a/arch/arc/include/asm/unaligned.h b/arch/arc/include/asm/unaligned.h
index 5dbe63f17b66..60702f3751d2 100644
--- a/arch/arc/include/asm/unaligned.h
+++ b/arch/arc/include/asm/unaligned.h
@@ -16,11 +16,11 @@
 
 #ifdef CONFIG_ARC_MISALIGN_ACCESS
 int misaligned_fixup(unsigned long address, struct pt_regs *regs,
-                     unsigned long cause, struct callee_regs *cregs);
+                     struct callee_regs *cregs);
 #else
 static inline int
 misaligned_fixup(unsigned long address, struct pt_regs *regs,
-                 unsigned long cause, struct callee_regs *cregs)
+                 struct callee_regs *cregs)
 {
         return 0;
 }
diff --git a/arch/arc/include/uapi/asm/ptrace.h b/arch/arc/include/uapi/asm/ptrace.h
index 30333cec0fef..2618cc13ba75 100644
--- a/arch/arc/include/uapi/asm/ptrace.h
+++ b/arch/arc/include/uapi/asm/ptrace.h
@@ -20,28 +20,31 @@
  *
  * This is to decouple pt_regs from user-space ABI, to be able to change it
  * w/o affecting the ABI.
- * Although the layout (initial padding) is similar to pt_regs to have some
- * optimizations when copying pt_regs to/from user_regs_struct.
+ *
+ * The intermediate pad,pad2 are relics of initial layout based on pt_regs
+ * for optimizations when copying pt_regs to/from user_regs_struct.
+ * We no longer need them, but can't be changed as they are part of ABI now.
  *
  * Also, sigcontext only care about the scratch regs as that is what we really
- * save/restore for signal handling.
+ * save/restore for signal handling. However gdb also uses the same struct
+ * hence callee regs need to be in there too.
 */
 struct user_regs_struct {
 
+        long pad;
         struct {
-                long pad;
                 long bta, lp_start, lp_end, lp_count;
                 long status32, ret, blink, fp, gp;
                 long r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0;
                 long sp;
         } scratch;
+        long pad2;
         struct {
-                long pad;
                 long r25, r24, r23, r22, r21, r20;
                 long r19, r18, r17, r16, r15, r14, r13;
         } callee;
         long efa;       /* break pt addr, for break points in delay slots */
-        long stop_pc;   /* give dbg stop_pc directly after checking orig_r8 */
+        long stop_pc;   /* give dbg stop_pc after ensuring brkpt trap */
 };
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c
index 7dcda7025241..6c3aa0edb9b5 100644
--- a/arch/arc/kernel/asm-offsets.c
+++ b/arch/arc/kernel/asm-offsets.c
@@ -24,9 +24,6 @@ int main(void)
 
         DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
         DEFINE(THREAD_CALLEE_REG, offsetof(struct thread_struct, callee_reg));
-#ifdef CONFIG_ARC_CURR_IN_REG
-        DEFINE(THREAD_USER_R25, offsetof(struct thread_struct, user_r25));
-#endif
         DEFINE(THREAD_FAULT_ADDR,
                offsetof(struct thread_struct, fault_address));
 
@@ -49,7 +46,7 @@ int main(void)
         BLANK();
 
         DEFINE(PT_status32, offsetof(struct pt_regs, status32));
-        DEFINE(PT_orig_r8, offsetof(struct pt_regs, orig_r8_word));
+        DEFINE(PT_event, offsetof(struct pt_regs, event));
         DEFINE(PT_sp, offsetof(struct pt_regs, sp));
         DEFINE(PT_r0, offsetof(struct pt_regs, r0));
         DEFINE(PT_r1, offsetof(struct pt_regs, r1));
@@ -60,5 +57,7 @@ int main(void)
         DEFINE(PT_r6, offsetof(struct pt_regs, r6));
         DEFINE(PT_r7, offsetof(struct pt_regs, r7));
 
+        DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs));
+        DEFINE(SZ_PT_REGS, sizeof(struct pt_regs));
         return 0;
 }
diff --git a/arch/arc/kernel/ctx_sw.c b/arch/arc/kernel/ctx_sw.c
index 60844dac6132..34410eb1a308 100644
--- a/arch/arc/kernel/ctx_sw.c
+++ b/arch/arc/kernel/ctx_sw.c
@@ -23,10 +23,6 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
         unsigned int tmp;
         unsigned int prev = (unsigned int)prev_task;
         unsigned int next = (unsigned int)next_task;
-        int num_words_to_skip = 1;
-#ifdef CONFIG_ARC_CURR_IN_REG
-        num_words_to_skip++;
-#endif
 
         __asm__ __volatile__(
                 /* FP/BLINK save generated by gcc (standard function prologue */
@@ -44,8 +40,9 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
                 "st.a    r24, [sp, -4]   \n\t"
 #ifndef CONFIG_ARC_CURR_IN_REG
                 "st.a    r25, [sp, -4]   \n\t"
+#else
+                "sub     sp, sp, 4      \n\t"   /* usual r25 placeholder */
 #endif
-                "sub     sp, sp, %4      \n\t"  /* create gutter at top */
 
                 /* set ksp of outgoing task in tsk->thread.ksp */
                 "st.as   sp, [%3, %1]    \n\t"
@@ -76,10 +73,10 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
 
                 /* start loading it's CALLEE reg file */
 
-                "add    sp, sp, %4     \n\t"    /* skip gutter at top */
-
 #ifndef CONFIG_ARC_CURR_IN_REG
                 "ld.ab   r25, [sp, 4]   \n\t"
+#else
+                "add    sp, sp, 4       \n\t"
 #endif
                 "ld.ab   r24, [sp, 4]   \n\t"
                 "ld.ab   r23, [sp, 4]   \n\t"
@@ -100,8 +97,7 @@ __switch_to(struct task_struct *prev_task, struct task_struct *next_task)
                 /* FP/BLINK restore generated by gcc (standard func epilogue */
 
                 : "=r"(tmp)
-                : "n"((TASK_THREAD + THREAD_KSP) / 4), "r"(next), "r"(prev),
-                  "n"(num_words_to_skip * 4)
+                : "n"((TASK_THREAD + THREAD_KSP) / 4), "r"(next), "r"(prev)
                 : "blink"
         );
 
diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 0c6d664d4a83..1d7165156e17 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -142,7 +142,7 @@ VECTOR   reserved                ; Reserved Exceptions
 .endr
 
 #include <linux/linkage.h>   /* ARC_{EXTRY,EXIT} */
-#include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,TRAP...} */
+#include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,SYS...} */
 #include <asm/errno.h>
 #include <asm/arcregs.h>
 #include <asm/irqflags.h>
@@ -274,10 +274,8 @@ ARC_ENTRY instr_service
         SWITCH_TO_KERNEL_STK
         SAVE_ALL_SYS
 
-        lr  r0, [ecr]
-        lr  r1, [efa]
-
-        mov r2, sp
+        lr  r0, [efa]
+        mov r1, sp
 
         FAKE_RET_FROM_EXCPN r9
 
@@ -298,9 +296,8 @@ ARC_ENTRY mem_service
         SWITCH_TO_KERNEL_STK
         SAVE_ALL_SYS
 
-        lr  r0, [ecr]
-        lr  r1, [efa]
-        mov r2, sp
+        lr  r0, [efa]
+        mov r1, sp
         bl  do_memory_error
         b   ret_from_exception
 ARC_EXIT mem_service
@@ -317,11 +314,14 @@ ARC_ENTRY EV_MachineCheck
         SWITCH_TO_KERNEL_STK
         SAVE_ALL_SYS
 
-        lr  r0, [ecr]
-        lr  r1, [efa]
-        mov r2, sp
+        lr  r2, [ecr]
+        lr  r0, [efa]
+        mov r1, sp
+
+        lsr     r3, r2, 8
+        bmsk    r3, r3, 7
+        brne    r3, ECR_C_MCHK_DUP_TLB, 1f
 
-        brne    r0, 0x200100, 1f
         bl      do_tlb_overlap_fault
         b       ret_from_exception
 
@@ -355,8 +355,8 @@ ARC_ENTRY EV_TLBProtV
         ;  ecr and efa were not saved in case an Intr sneaks in
         ;  after fake rtie
         ;
-        lr  r3, [ecr]
-        lr  r4, [efa]
+        lr  r2, [ecr]
+        lr  r1, [efa]   ; Faulting Data address
 
         ; --------(4) Return from CPU Exception Mode ---------
         ;  Fake a rtie, but rtie to next label
@@ -368,31 +368,25 @@ ARC_ENTRY EV_TLBProtV
         ;------ (5) Type of Protection Violation? ----------
         ;
         ; ProtV Hardware Exception is triggered for Access Faults of 2 types
-        ;   -Access Violaton (WRITE to READ ONLY Page) - for linux COW
-        ;   -Unaligned Access (READ/WRITE on odd boundary)
+        ;   -Access Violaton    : 00_23_(00|01|02|03)_00
+        ;                                x  r  w  r+w
+        ;   -Unaligned Access   : 00_23_04_00
         ;
-        cmp r3, 0x230400    ; Misaligned data access ?
-        beq 4f
+        bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
 
         ;========= (6a) Access Violation Processing ========
-        cmp r3, 0x230100
-        mov r1, 0x0              ; if LD exception ? write = 0
-        mov.ne r1, 0x1           ; else write = 1
-
-        mov r2, r4              ; faulting address
         mov r0, sp              ; pt_regs
         bl  do_page_fault
         b   ret_from_exception
 
         ;========== (6b) Non aligned access ============
 4:
-        mov r0, r3              ; cause code
-        mov r1, r4              ; faulting address
-        mov r2, sp              ; pt_regs
+        mov r0, r1
+        mov r1, sp              ; pt_regs
 
 #ifdef  CONFIG_ARC_MISALIGN_ACCESS
         SAVE_CALLEE_SAVED_USER
-        mov r3, sp              ; callee_regs
+        mov r2, sp              ; callee_regs
 
         bl  do_misaligned_access
 
@@ -419,9 +413,8 @@ ARC_ENTRY EV_PrivilegeV
         SWITCH_TO_KERNEL_STK
         SAVE_ALL_SYS
 
-        lr  r0, [ecr]
-        lr  r1, [efa]
-        mov r2, sp
+        lr  r0, [efa]
+        mov r1, sp
 
         FAKE_RET_FROM_EXCPN r9
 
@@ -440,9 +433,8 @@ ARC_ENTRY EV_Extension
         SWITCH_TO_KERNEL_STK
         SAVE_ALL_SYS
 
-        lr  r0, [ecr]
-        lr  r1, [efa]
-        mov r2, sp
+        lr  r0, [efa]
+        mov r1, sp
         bl  do_extension_fault
         b   ret_from_exception
 ARC_EXIT EV_Extension
@@ -498,11 +490,8 @@ tracesys_exit:
 trap_with_param:
 
         ; stop_pc info by gdb needs this info
-        stw orig_r8_IS_BRKPT, [sp, PT_orig_r8]
-
-        mov r0, r12
-        lr  r1, [efa]
-        mov r2, sp
+        lr  r0, [efa]
+        mov r1, sp
 
         ; Now that we have read EFA, its safe to do "fake" rtie
         ;   and get out of CPU exception mode
@@ -544,11 +533,11 @@ ARC_ENTRY EV_Trap
         lr  r9, [erstatus]
 
         SWITCH_TO_KERNEL_STK
-        SAVE_ALL_TRAP
+        SAVE_ALL_SYS
 
         ;------- (4) What caused the Trap --------------
         lr     r12, [ecr]
-        and.f  0, r12, ECR_PARAM_MASK
+        bmsk.f 0, r12, 7
         bnz    trap_with_param
 
         ; ======= (5a) Trap is due to System Call ========
@@ -589,11 +578,7 @@ ARC_ENTRY ret_from_exception
         ; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
         ld  r8, [sp, PT_status32]   ; returning to User/Kernel Mode
 
-#ifdef CONFIG_PREEMPT
         bbit0  r8, STATUS_U_BIT, resume_kernel_mode
-#else
-        bbit0  r8, STATUS_U_BIT, restore_regs
-#endif
 
         ; Before returning to User mode check-for-and-complete any pending work
         ; such as rescheduling/signal-delivery etc.
@@ -653,10 +638,10 @@ resume_user_mode_begin:
         b      resume_user_mode_begin   ; unconditionally back to U mode ret chks
                                         ; for single exit point from this block
 
-#ifdef CONFIG_PREEMPT
-
 resume_kernel_mode:
 
+#ifdef CONFIG_PREEMPT
+
         ; Can't preempt if preemption disabled
         GET_CURR_THR_INFO_FROM_SP   r10
         ld  r8, [r10, THREAD_INFO_PREEMPT_COUNT]
@@ -687,17 +672,6 @@ restore_regs :
         ; XXX can this be optimised out
         IRQ_DISABLE_SAVE    r9, r10     ;@r10 has prisitine (pre-disable) copy
 
-#ifdef CONFIG_ARC_CURR_IN_REG
-        ; Restore User R25
-        ; Earlier this used to be only for returning to user mode
-        ; However with 2 levels of IRQ this can also happen even if
-        ; in kernel mode
-        ld r9, [sp, PT_sp]
-        brhs r9, VMALLOC_START, 8f
-        RESTORE_USER_R25
-8:
-#endif
-
         ; Restore REG File. In case multiple Events outstanding,
         ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
         ; Note that we use realtime STATUS32 (not pt_regs->status32) to
@@ -714,28 +688,33 @@ not_exception:
 
 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
 
+        ; Level 2 interrupt return Path - from hardware standpoint
         bbit0  r10, STATUS_A2_BIT, not_level2_interrupt
 
         ;------------------------------------------------------------------
+        ; However the context returning might not have taken L2 intr itself
+        ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
+        ; Special considerations needed for the context which took L2 intr
+
+        ld   r9, [sp, PT_event]        ; Ensure this is L2 intr context
+        brne r9, event_IRQ2, 149f
+
+        ;------------------------------------------------------------------
         ; if L2 IRQ interrupted a L1 ISR,  we'd disbaled preemption earlier
         ; so that sched doesnt move to new task, causing L1 to be delayed
         ; undeterministically. Now that we've achieved that, lets reset
         ; things to what they were, before returning from L2 context
         ;----------------------------------------------------------------
 
-        ldw  r9, [sp, PT_orig_r8]      ; get orig_r8 to make sure it is
-        brne r9, orig_r8_IS_IRQ2, 149f ; infact a L2 ISR ret path
-
         ld r9, [sp, PT_status32]       ; get statu32_l2 (saved in pt_regs)
         bbit0 r9, STATUS_A1_BIT, 149f  ; L1 not active when L2 IRQ, so normal
 
-        ; A1 is set in status32_l2
         ; decrement thread_info->preempt_count (re-enable preemption)
         GET_CURR_THR_INFO_FROM_SP   r10
         ld      r9, [r10, THREAD_INFO_PREEMPT_COUNT]
 
         ; paranoid check, given A1 was active when A2 happened, preempt count
-        ; must not be 0 beccause we would have incremented it.
+        ; must not be 0 because we would have incremented it.
         ; If this does happen we simply HALT as it means a BUG !!!
         cmp     r9, 0
         bnz     2f
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 006dec3fc353..2a913f85a747 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -27,6 +27,8 @@ stext:
         ; Don't clobber r0-r4 yet. It might have bootloader provided info
         ;-------------------------------------------------------------------
 
+        sr      @_int_vec_base_lds, [AUX_INTR_VEC_BASE]
+
 #ifdef CONFIG_SMP
         ; Only Boot (Master) proceeds. Others wait in platform dependent way
         ;       IDENTITY Reg [ 3  2  1  0 ]
diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c
index 8115fa531575..305b3f866aa7 100644
--- a/arch/arc/kernel/irq.c
+++ b/arch/arc/kernel/irq.c
@@ -28,25 +28,17 @@
  * -Disable all IRQs (on CPU side)
  * -Optionally, setup the High priority Interrupts as Level 2 IRQs
  */
-void __cpuinit arc_init_IRQ(void)
+void arc_init_IRQ(void)
 {
         int level_mask = 0;
 
-        write_aux_reg(AUX_INTR_VEC_BASE, _int_vec_base_lds);
-
         /* Disable all IRQs: enable them as devices request */
         write_aux_reg(AUX_IENABLE, 0);
 
        /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
-#ifdef CONFIG_ARC_IRQ3_LV2
-        level_mask |= (1 << 3);
-#endif
-#ifdef CONFIG_ARC_IRQ5_LV2
-        level_mask |= (1 << 5);
-#endif
-#ifdef CONFIG_ARC_IRQ6_LV2
-        level_mask |= (1 << 6);
-#endif
+        level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
+        level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
+        level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
 
         if (level_mask) {
                 pr_info("Level-2 interrupts bitset %x\n", level_mask);
diff --git a/arch/arc/kernel/kgdb.c b/arch/arc/kernel/kgdb.c
index 52bdc83c1495..a7698fb14818 100644
--- a/arch/arc/kernel/kgdb.c
+++ b/arch/arc/kernel/kgdb.c
@@ -169,7 +169,7 @@ int kgdb_arch_init(void)
         return 0;
 }
 
-void kgdb_trap(struct pt_regs *regs, int param)
+void kgdb_trap(struct pt_regs *regs)
 {
         /* trap_s 3 is used for breakpoints that overwrite existing
          * instructions, while trap_s 4 is used for compiled breakpoints.
@@ -181,7 +181,7 @@ void kgdb_trap(struct pt_regs *regs, int param)
          * with trap_s 4 (compiled) breakpoints, continuation needs to
          * start after the breakpoint.
          */
-        if (param == 3)
+        if (regs->ecr_param == 3)
                 instruction_pointer(regs) -= BREAK_INSTR_SIZE;
 
         kgdb_handle_exception(1, SIGTRAP, 0, regs);
diff --git a/arch/arc/kernel/kprobes.c b/arch/arc/kernel/kprobes.c
index 5a7b80e2d883..72f97822784a 100644
--- a/arch/arc/kernel/kprobes.c
+++ b/arch/arc/kernel/kprobes.c
@@ -517,8 +517,7 @@ int __kprobes arch_trampoline_kprobe(struct kprobe *p)
         return 0;
 }
 
-void trap_is_kprobe(unsigned long cause, unsigned long address,
-                    struct pt_regs *regs)
+void trap_is_kprobe(unsigned long address, struct pt_regs *regs)
 {
-        notify_die(DIE_TRAP, "kprobe_trap", regs, address, cause, SIGTRAP);
+        notify_die(DIE_TRAP, "kprobe_trap", regs, address, 0, SIGTRAP);
 }
diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c
index cad66851e0c4..07a3a968fe49 100644
--- a/arch/arc/kernel/process.c
+++ b/arch/arc/kernel/process.c
@@ -55,10 +55,8 @@ asmlinkage void ret_from_fork(void);
  * |     ...        |
  * |    unused      |
  * |                |
- * ------------------  <==== top of Stack (thread.ksp)
- * |   UNUSED 1 word|
  * ------------------
- * |     r25        |
+ * |     r25        |   <==== top of Stack (thread.ksp)
  * ~                ~
  * |    --to--      |   (CALLEE Regs of user mode)
  * |     r13        |
@@ -76,7 +74,10 @@ asmlinkage void ret_from_fork(void);
  * |    --to--      |   (scratch Regs of user mode)
  * |     r0         |
  * ------------------
- * |   UNUSED 1 word|
+ * |      SP        |
+ * |    orig_r0     |
+ * |    event/ECR   |
+ * |    user_r25    |
  * ------------------  <===== END of PAGE
  */
 int copy_thread(unsigned long clone_flags,
diff --git a/arch/arc/kernel/ptrace.c b/arch/arc/kernel/ptrace.c
index c6a81c58d0f3..333238564b67 100644
--- a/arch/arc/kernel/ptrace.c
+++ b/arch/arc/kernel/ptrace.c
@@ -40,7 +40,15 @@ static int genregs_get(struct task_struct *target,
                         offsetof(struct user_regs_struct, LOC), \
                         offsetof(struct user_regs_struct, LOC) + 4);
 
+#define REG_O_ZERO(LOC)         \
+        if (!ret)               \
+                ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf, \
+                        offsetof(struct user_regs_struct, LOC), \
+                        offsetof(struct user_regs_struct, LOC) + 4);
+
+        REG_O_ZERO(pad);
         REG_O_CHUNK(scratch, callee, ptregs);
+        REG_O_ZERO(pad2);
         REG_O_CHUNK(callee, efa, cregs);
         REG_O_CHUNK(efa, stop_pc, &target->thread.fault_address);
 
@@ -88,8 +96,10 @@ static int genregs_set(struct task_struct *target,
                         offsetof(struct user_regs_struct, LOC), \
                         offsetof(struct user_regs_struct, LOC) + 4);
 
-        /* TBD: disallow updates to STATUS32, orig_r8 etc*/
-        REG_IN_CHUNK(scratch, callee, ptregs);  /* pt_regs[bta..orig_r8] */
+        REG_IGNORE_ONE(pad);
+        /* TBD: disallow updates to STATUS32 etc*/
+        REG_IN_CHUNK(scratch, pad2, ptregs);    /* pt_regs[bta..sp] */
+        REG_IGNORE_ONE(pad2);
         REG_IN_CHUNK(callee, efa, cregs);       /* callee_regs[r25..r13] */
         REG_IGNORE_ONE(efa);                    /* efa update invalid */
         REG_IN_ONE(stop_pc, &ptregs->ret);      /* stop_pc: PC update */
diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c
index b2b3731dd1e9..6b083454d039 100644
--- a/arch/arc/kernel/setup.c
+++ b/arch/arc/kernel/setup.c
@@ -31,14 +31,14 @@
 int running_on_hw = 1;  /* vs. on ISS */
 
 char __initdata command_line[COMMAND_LINE_SIZE];
-struct machine_desc *machine_desc __cpuinitdata;
+struct machine_desc *machine_desc;
 
 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
 
 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
 
 
-void __cpuinit read_arc_build_cfg_regs(void)
+void read_arc_build_cfg_regs(void)
 {
         struct bcr_perip uncached_space;
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
@@ -182,7 +182,7 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
         FIX_PTR(cpu);
 #define IS_AVAIL1(var, str)     ((var) ? str : "")
 #define IS_AVAIL2(var, str)     ((var == 0x2) ? str : "")
-#define IS_USED(var)            ((var) ? "(in-use)" : "(not used)")
+#define IS_USED(cfg)            (IS_ENABLED(cfg) ? "(in-use)" : "(not used)")
 
         n += scnprintf(buf + n, len - n,
                        "Extn [700-Base]\t: %s %s %s %s %s %s\n",
@@ -202,9 +202,9 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
         if (cpu->core.family == 0x34) {
                 n += scnprintf(buf + n, len - n,
                 "Extn [700-4.10]\t: LLOCK/SCOND %s, SWAPE %s, RTSC %s\n",
-                               IS_USED(__CONFIG_ARC_HAS_LLSC_VAL),
-                               IS_USED(__CONFIG_ARC_HAS_SWAPE_VAL),
-                               IS_USED(__CONFIG_ARC_HAS_RTSC_VAL));
+                               IS_USED(CONFIG_ARC_HAS_LLSC),
+                               IS_USED(CONFIG_ARC_HAS_SWAPE),
+                               IS_USED(CONFIG_ARC_HAS_RTSC));
         }
 
         n += scnprintf(buf + n, len - n, "Extn [CCM]\t: %s",
@@ -237,7 +237,7 @@ char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
         return buf;
 }
 
-void __cpuinit arc_chk_ccms(void)
+void arc_chk_ccms(void)
 {
 #if defined(CONFIG_ARC_HAS_DCCM) || defined(CONFIG_ARC_HAS_ICCM)
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
@@ -272,7 +272,7 @@ void __cpuinit arc_chk_ccms(void)
  * hardware has dedicated regs which need to be saved/restored on ctx-sw
  * (Single Precision uses core regs), thus kernel is kind of oblivious to it
  */
-void __cpuinit arc_chk_fpu(void)
+void arc_chk_fpu(void)
 {
         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 
@@ -293,7 +293,7 @@ void __cpuinit arc_chk_fpu(void)
  *    such as only for boot CPU etc
  */
 
-void __cpuinit setup_processor(void)
+void setup_processor(void)
 {
         char str[512];
         int cpu_id = smp_processor_id();
diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c
index 5c7fd603d216..bca3052c956d 100644
--- a/arch/arc/kernel/smp.c
+++ b/arch/arc/kernel/smp.c
@@ -117,7 +117,7 @@ const char *arc_platform_smp_cpuinfo(void)
  * Called from asm stub in head.S
  * "current"/R25 already setup by low level boot code
  */
-void __cpuinit start_kernel_secondary(void)
+void start_kernel_secondary(void)
 {
         struct mm_struct *mm = &init_mm;
         unsigned int cpu = smp_processor_id();
@@ -154,7 +154,7 @@ void __cpuinit start_kernel_secondary(void)
  *
  * Essential requirements being where to run from (PC) and stack (SP)
 */
-int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
+int __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         unsigned long wait_till;
 
diff --git a/arch/arc/kernel/stacktrace.c b/arch/arc/kernel/stacktrace.c
index ca0207b9d5b6..f8b7d880304d 100644
--- a/arch/arc/kernel/stacktrace.c
+++ b/arch/arc/kernel/stacktrace.c
@@ -79,7 +79,7 @@ static void seed_unwind_frame_info(struct task_struct *tsk,
                  * assembly code
                  */
                 frame_info->regs.r27 = 0;
-                frame_info->regs.r28 += 64;
+                frame_info->regs.r28 += 60;
                 frame_info->call_frame = 0;
 
         } else {
diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c
index 09f4309aa2c0..0e51e69cf30d 100644
--- a/arch/arc/kernel/time.c
+++ b/arch/arc/kernel/time.c
@@ -44,13 +44,24 @@
 #include <asm/clk.h>
 #include <asm/mach_desc.h>
 
+/* Timer related Aux registers */
+#define ARC_REG_TIMER0_LIMIT    0x23    /* timer 0 limit */
+#define ARC_REG_TIMER0_CTRL     0x22    /* timer 0 control */
+#define ARC_REG_TIMER0_CNT      0x21    /* timer 0 count */
+#define ARC_REG_TIMER1_LIMIT    0x102   /* timer 1 limit */
+#define ARC_REG_TIMER1_CTRL     0x101   /* timer 1 control */
+#define ARC_REG_TIMER1_CNT      0x100   /* timer 1 count */
+
+#define TIMER_CTRL_IE           (1 << 0) /* Interupt when Count reachs limit */
+#define TIMER_CTRL_NH           (1 << 1) /* Count only when CPU NOT halted */
+
 #define ARC_TIMER_MAX   0xFFFFFFFF
 
 /********** Clock Source Device *********/
 
 #ifdef CONFIG_ARC_HAS_RTSC
 
-int __cpuinit arc_counter_setup(void)
+int arc_counter_setup(void)
 {
         /* RTSC insn taps into cpu clk, needs no setup */
 
@@ -105,7 +116,7 @@ static bool is_usable_as_clocksource(void)
 /*
  * set 32bit TIMER1 to keep counting monotonically and wraparound
  */
-int __cpuinit arc_counter_setup(void)
+int arc_counter_setup(void)
 {
         write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
         write_aux_reg(ARC_REG_TIMER1_CNT, 0);
@@ -212,7 +223,7 @@ static struct irqaction arc_timer_irq = {
  * Setup the local event timer for @cpu
  * N.B. weak so that some exotic ARC SoCs can completely override it
  */
-void __attribute__((weak)) __cpuinit arc_local_timer_setup(unsigned int cpu)
+void __attribute__((weak)) arc_local_timer_setup(unsigned int cpu)
 {
         struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
 
diff --git a/arch/arc/kernel/traps.c b/arch/arc/kernel/traps.c
index 0471d9c9dd54..e21692d2fdab 100644
--- a/arch/arc/kernel/traps.c
+++ b/arch/arc/kernel/traps.c
@@ -28,10 +28,9 @@ void __init trap_init(void)
         return;
 }
 
-void die(const char *str, struct pt_regs *regs, unsigned long address,
-         unsigned long cause_reg)
+void die(const char *str, struct pt_regs *regs, unsigned long address)
 {
-        show_kernel_fault_diag(str, regs, address, cause_reg);
+        show_kernel_fault_diag(str, regs, address);
 
         /* DEAD END */
         __asm__("flag 1");
@@ -42,14 +41,13 @@ void die(const char *str, struct pt_regs *regs, unsigned long address,
  *  -for user faults enqueues requested signal
  *  -for kernel, chk if due to copy_(to|from)_user, otherwise die()
  */
-static noinline int handle_exception(unsigned long cause, char *str,
-                                     struct pt_regs *regs, siginfo_t *info)
+static noinline int
+handle_exception(const char *str, struct pt_regs *regs, siginfo_t *info)
 {
         if (user_mode(regs)) {
                 struct task_struct *tsk = current;
 
                 tsk->thread.fault_address = (__force unsigned int)info->si_addr;
-                tsk->thread.cause_code = cause;
 
                 force_sig_info(info->si_signo, info, tsk);
 
@@ -58,14 +56,14 @@ static noinline int handle_exception(unsigned long cause, char *str,
                 if (fixup_exception(regs))
                         return 0;
 
-                die(str, regs, (unsigned long)info->si_addr, cause);
+                die(str, regs, (unsigned long)info->si_addr);
         }
 
         return 1;
 }
 
 #define DO_ERROR_INFO(signr, str, name, sicode) \
-int name(unsigned long cause, unsigned long address, struct pt_regs *regs) \
+int name(unsigned long address, struct pt_regs *regs) \
 {                                               \
         siginfo_t info = {                      \
                 .si_signo = signr,              \
@@ -73,7 +71,7 @@ int name(unsigned long cause, unsigned long address, struct pt_regs *regs) \
                 .si_code  = sicode,             \
                 .si_addr = (void __user *)address,      \
         };                                      \
-        return handle_exception(cause, str, regs, &info);\
+        return handle_exception(str, regs, &info);\
 }
 
 /*
@@ -90,11 +88,11 @@ DO_ERROR_INFO(SIGBUS, "Misaligned Access", do_misaligned_error, BUS_ADRALN)
 /*
  * Entry Point for Misaligned Data access Exception, for emulating in software
  */
-int do_misaligned_access(unsigned long cause, unsigned long address,
-                         struct pt_regs *regs, struct callee_regs *cregs)
+int do_misaligned_access(unsigned long address, struct pt_regs *regs,
+                         struct callee_regs *cregs)
 {
-        if (misaligned_fixup(address, regs, cause, cregs) != 0)
-                return do_misaligned_error(cause, address, regs);
+        if (misaligned_fixup(address, regs, cregs) != 0)
+                return do_misaligned_error(address, regs);
 
         return 0;
 }
@@ -104,10 +102,9 @@ int do_misaligned_access(unsigned long cause, unsigned long address,
  * Entry point for miscll errors such as Nested Exceptions
  *  -Duplicate TLB entry is handled seperately though
  */
-void do_machine_check_fault(unsigned long cause, unsigned long address,
-                            struct pt_regs *regs)
+void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
 {
-        die("Machine Check Exception", regs, address, cause);
+        die("Machine Check Exception", regs, address);
 }
 
 
@@ -120,23 +117,22 @@ void do_machine_check_fault(unsigned long cause, unsigned long address,
  *  -1 used for software breakpointing (gdb)
  *  -2 used by kprobes
  */
-void do_non_swi_trap(unsigned long cause, unsigned long address,
-                        struct pt_regs *regs)
+void do_non_swi_trap(unsigned long address, struct pt_regs *regs)
 {
-        unsigned int param = cause & 0xff;
+        unsigned int param = regs->ecr_param;
 
         switch (param) {
         case 1:
-                trap_is_brkpt(cause, address, regs);
+                trap_is_brkpt(address, regs);
                 break;
 
         case 2:
-                trap_is_kprobe(param, address, regs);
+                trap_is_kprobe(address, regs);
                 break;
 
         case 3:
         case 4:
-                kgdb_trap(regs, param);
+                kgdb_trap(regs);
                 break;
 
         default:
@@ -149,14 +145,14 @@ void do_non_swi_trap(unsigned long cause, unsigned long address,
  *  -For a corner case, ARC kprobes implementation resorts to using
  *   this exception, hence the check
  */
-void do_insterror_or_kprobe(unsigned long cause,
-                                       unsigned long address,
-                                       struct pt_regs *regs)
+void do_insterror_or_kprobe(unsigned long address, struct pt_regs *regs)
 {
+        int rc;
+
         /* Check if this exception is caused by kprobes */
-        if (notify_die(DIE_IERR, "kprobe_ierr", regs, address,
-                       cause, SIGILL) == NOTIFY_STOP)
+        rc = notify_die(DIE_IERR, "kprobe_ierr", regs, address, 0, SIGILL);
+        if (rc == NOTIFY_STOP)
                 return;
 
-        insterror_is_error(cause, address, regs);
+        insterror_is_error(address, regs);
 }
diff --git a/arch/arc/kernel/troubleshoot.c b/arch/arc/kernel/troubleshoot.c
index 11c301b81c92..73a7450ee622 100644
--- a/arch/arc/kernel/troubleshoot.c
+++ b/arch/arc/kernel/troubleshoot.c
@@ -101,7 +101,7 @@ static void show_faulting_vma(unsigned long address, char *buf)
                 if (file) {
                         struct path *path = &file->f_path;
                         nm = d_path(path, buf, PAGE_SIZE - 1);
-                        inode = vma->vm_file->f_path.dentry->d_inode;
+                        inode = file_inode(vma->vm_file);
                         dev = inode->i_sb->s_dev;
                         ino = inode->i_ino;
                 }
@@ -117,23 +117,22 @@ static void show_faulting_vma(unsigned long address, char *buf)
 
 static void show_ecr_verbose(struct pt_regs *regs)
 {
-        unsigned int vec, cause_code, cause_reg;
+        unsigned int vec, cause_code;
         unsigned long address;
 
-        cause_reg = current->thread.cause_code;
-        pr_info("\n[ECR   ]: 0x%08x => ", cause_reg);
+        pr_info("\n[ECR   ]: 0x%08lx => ", regs->event);
 
         /* For Data fault, this is data address not instruction addr */
         address = current->thread.fault_address;
 
-        vec = cause_reg >> 16;
-        cause_code = (cause_reg >> 8) & 0xFF;
+        vec = regs->ecr_vec;
+        cause_code = regs->ecr_cause;
 
         /* For DTLB Miss or ProtV, display the memory involved too */
         if (vec == ECR_V_DTLB_MISS) {
-                pr_cont("Invalid %s 0x%08lx by insn @ 0x%08lx\n",
-                       (cause_code == 0x01) ? "Read From" :
-                       ((cause_code == 0x02) ? "Write to" : "EX"),
+                pr_cont("Invalid %s @ 0x%08lx by insn @ 0x%08lx\n",
+                       (cause_code == 0x01) ? "Read" :
+                       ((cause_code == 0x02) ? "Write" : "EX"),
                        address, regs->ret);
         } else if (vec == ECR_V_ITLB_MISS) {
                 pr_cont("Insn could not be fetched\n");
@@ -144,14 +143,12 @@ static void show_ecr_verbose(struct pt_regs *regs)
         } else if (vec == ECR_V_PROTV) {
                 if (cause_code == ECR_C_PROTV_INST_FETCH)
                         pr_cont("Execute from Non-exec Page\n");
-                else if (cause_code == ECR_C_PROTV_LOAD)
-                        pr_cont("Read from Non-readable Page\n");
-                else if (cause_code == ECR_C_PROTV_STORE)
-                        pr_cont("Write to Non-writable Page\n");
-                else if (cause_code == ECR_C_PROTV_XCHG)
-                        pr_cont("Data exchange protection violation\n");
                 else if (cause_code == ECR_C_PROTV_MISALIG_DATA)
                         pr_cont("Misaligned r/w from 0x%08lx\n", address);
+                else
+                        pr_cont("%s access not allowed on page\n",
+                                (cause_code == 0x01) ? "Read" :
+                                ((cause_code == 0x02) ? "Write" : "EX"));
         } else if (vec == ECR_V_INSN_ERR) {
                 pr_cont("Illegal Insn\n");
         } else {
@@ -176,8 +173,7 @@ void show_regs(struct pt_regs *regs)
         print_task_path_n_nm(tsk, buf);
         show_regs_print_info(KERN_INFO);
 
-        if (current->thread.cause_code)
-                show_ecr_verbose(regs);
+        show_ecr_verbose(regs);
 
         pr_info("[EFA   ]: 0x%08lx\n[BLINK ]: %pS\n[ERET  ]: %pS\n",
                 current->thread.fault_address,
@@ -213,10 +209,9 @@ void show_regs(struct pt_regs *regs)
 }
 
 void show_kernel_fault_diag(const char *str, struct pt_regs *regs,
-                            unsigned long address, unsigned long cause_reg)
+                            unsigned long address)
 {
         current->thread.fault_address = address;
-        current->thread.cause_code = cause_reg;
 
         /* Caller and Callee regs */
         show_regs(regs);
diff --git a/arch/arc/kernel/unaligned.c b/arch/arc/kernel/unaligned.c
index 4cd81633febd..c0f832f595d3 100644
--- a/arch/arc/kernel/unaligned.c
+++ b/arch/arc/kernel/unaligned.c
@@ -187,7 +187,7 @@ fault:	state->fault = 1;
  * Returns 0 if successfully handled, 1 if some error happened
  */
 int misaligned_fixup(unsigned long address, struct pt_regs *regs,
-                     unsigned long cause, struct callee_regs *cregs)
+                     struct callee_regs *cregs)
 {
         struct disasm_state state;
         char buf[TASK_COMM_LEN];
diff --git a/arch/arc/kernel/unwind.c b/arch/arc/kernel/unwind.c
index a8d02223da44..e550b117ec4f 100644
--- a/arch/arc/kernel/unwind.c
+++ b/arch/arc/kernel/unwind.c
@@ -289,6 +289,8 @@ static void __init setup_unwind_table(struct unwind_table *table,
                          * instead of the initial loc addr
                          * return;
                          */
+                        WARN(1, "unwinder: FDE->initial_location NULL %p\n",
+                                (const u8 *)(fde + 1) + *fde);
                 }
                 ++n;
         }
diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S
index d3c92f52d444..2555f5886af6 100644
--- a/arch/arc/kernel/vmlinux.lds.S
+++ b/arch/arc/kernel/vmlinux.lds.S
@@ -125,6 +125,11 @@ SECTIONS
                 *(.debug_frame)
                 __end_unwind = .;
         }
+        /*
+         * gcc 4.8 generates this for -fasynchonous-unwind-tables,
+         * while we still use the .debug_frame based unwinder
+         */
+        /DISCARD/ : {   *(.eh_frame) }
 #else
         /DISCARD/ : {   *(.debug_frame) }
 #endif
@@ -142,15 +147,18 @@ SECTIONS
                 *(.arcextmap.*)
         }
 
+#ifndef CONFIG_DEBUG_INFO
         /* open-coded because we need .debug_frame seperately for unwinding */
-        .debug_aranges 0 : { *(.debug_aranges) }
-        .debug_pubnames 0 : { *(.debug_pubnames) }
-        .debug_info 0 : { *(.debug_info) }
-        .debug_abbrev 0 : { *(.debug_abbrev) }
-        .debug_line 0 : { *(.debug_line) }
-        .debug_str 0 : { *(.debug_str) }
-        .debug_loc 0 : { *(.debug_loc) }
-        .debug_macinfo 0 : { *(.debug_macinfo) }
+        /DISCARD/ : { *(.debug_aranges) }
+        /DISCARD/ : { *(.debug_pubnames) }
+        /DISCARD/ : { *(.debug_info) }
+        /DISCARD/ : { *(.debug_abbrev) }
+        /DISCARD/ : { *(.debug_line) }
+        /DISCARD/ : { *(.debug_str) }
+        /DISCARD/ : { *(.debug_loc) }
+        /DISCARD/ : { *(.debug_macinfo) }
+        /DISCARD/ : { *(.debug_ranges) }
+#endif
 
 #ifdef CONFIG_ARC_HAS_DCCM
         . = CONFIG_ARC_DCCM_BASE;
diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index aedce1905441..f415d851b765 100644
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -73,6 +73,33 @@
 #include <asm/cachectl.h>
 #include <asm/setup.h>
 
+/* Instruction cache related Auxiliary registers */
+#define ARC_REG_IC_BCR          0x77    /* Build Config reg */
+#define ARC_REG_IC_IVIC         0x10
+#define ARC_REG_IC_CTRL         0x11
+#define ARC_REG_IC_IVIL         0x19
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_IC_PTAG         0x1E
+#endif
+
+/* Bit val in IC_CTRL */
+#define IC_CTRL_CACHE_DISABLE   0x1
+
+/* Data cache related Auxiliary registers */
+#define ARC_REG_DC_BCR          0x72    /* Build Config reg */
+#define ARC_REG_DC_IVDC         0x47
+#define ARC_REG_DC_CTRL         0x48
+#define ARC_REG_DC_IVDL         0x4A
+#define ARC_REG_DC_FLSH         0x4B
+#define ARC_REG_DC_FLDL         0x4C
+#if (CONFIG_ARC_MMU_VER > 2)
+#define ARC_REG_DC_PTAG         0x5C
+#endif
+
+/* Bit val in DC_CTRL */
+#define DC_CTRL_INV_MODE_FLUSH  0x40
+#define DC_CTRL_FLUSH_STATUS    0x100
+
 char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
 {
         int n = 0;
@@ -89,8 +116,10 @@ char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
                         enb ?  "" : "DISABLED (kernel-build)");         \
 }
 
-        PR_CACHE(&cpuinfo_arc700[c].icache, __CONFIG_ARC_HAS_ICACHE, "I-Cache");
-        PR_CACHE(&cpuinfo_arc700[c].dcache, __CONFIG_ARC_HAS_DCACHE, "D-Cache");
+        PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),
+                        "I-Cache");
+        PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),
+                        "D-Cache");
 
         return buf;
 }
@@ -100,17 +129,23 @@ char *arc_cache_mumbojumbo(int cpu_id, char *buf, int len)
  * the cpuinfo structure for later use.
  * No Validation done here, simply read/convert the BCRs
  */
-void __cpuinit read_decode_cache_bcr(void)
+void read_decode_cache_bcr(void)
 {
-        struct bcr_cache ibcr, dbcr;
         struct cpuinfo_arc_cache *p_ic, *p_dc;
         unsigned int cpu = smp_processor_id();
+        struct bcr_cache {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
+#else
+                unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
+#endif
+        } ibcr, dbcr;
 
         p_ic = &cpuinfo_arc700[cpu].icache;
         READ_BCR(ARC_REG_IC_BCR, ibcr);
 
-        if (ibcr.config == 0x3)
-                p_ic->assoc = 2;
+        BUG_ON(ibcr.config != 3);
+        p_ic->assoc = 2;                /* Fixed to 2w set assoc */
         p_ic->line_len = 8 << ibcr.line_len;
         p_ic->sz = 0x200 << ibcr.sz;
         p_ic->ver = ibcr.ver;
@@ -118,8 +153,8 @@ void __cpuinit read_decode_cache_bcr(void)
         p_dc = &cpuinfo_arc700[cpu].dcache;
         READ_BCR(ARC_REG_DC_BCR, dbcr);
 
-        if (dbcr.config == 0x2)
-                p_dc->assoc = 4;
+        BUG_ON(dbcr.config != 2);
+        p_dc->assoc = 4;                /* Fixed to 4w set assoc */
         p_dc->line_len = 16 << dbcr.line_len;
         p_dc->sz = 0x200 << dbcr.sz;
         p_dc->ver = dbcr.ver;
@@ -132,14 +167,12 @@ void __cpuinit read_decode_cache_bcr(void)
  * 3. Enable the Caches, setup default flush mode for D-Cache
  * 3. Calculate the SHMLBA used by user space
  */
-void __cpuinit arc_cache_init(void)
+void arc_cache_init(void)
 {
-        unsigned int temp;
         unsigned int cpu = smp_processor_id();
         struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
         struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
-        int way_pg_ratio = way_pg_ratio;
-        int dcache_does_alias;
+        unsigned int dcache_does_alias, temp;
         char str[256];
 
         printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
@@ -149,20 +182,11 @@ void __cpuinit arc_cache_init(void)
 
 #ifdef CONFIG_ARC_HAS_ICACHE
         /* 1. Confirm some of I-cache params which Linux assumes */
-        if ((ic->assoc != ARC_ICACHE_WAYS) ||
-            (ic->line_len != ARC_ICACHE_LINE_LEN)) {
+        if (ic->line_len != ARC_ICACHE_LINE_LEN)
                 panic("Cache H/W doesn't match kernel Config");
-        }
-#if (CONFIG_ARC_MMU_VER > 2)
-        if (ic->ver != 3) {
-                if (running_on_hw)
-                        panic("Cache ver doesn't match MMU ver\n");
-
-                /* For ISS - suggest the toggles to use */
-                pr_err("Use -prop=icache_version=3,-prop=dcache_version=3\n");
 
-        }
-#endif
+        if (ic->ver != CONFIG_ARC_MMU_VER)
+                panic("Cache ver doesn't match MMU ver\n");
 #endif
 
         /* Enable/disable I-Cache */
@@ -181,14 +205,12 @@ chk_dc:
                 return;
 
 #ifdef CONFIG_ARC_HAS_DCACHE
-        if ((dc->assoc != ARC_DCACHE_WAYS) ||
-            (dc->line_len != ARC_DCACHE_LINE_LEN)) {
+        if (dc->line_len != ARC_DCACHE_LINE_LEN)
                 panic("Cache H/W doesn't match kernel Config");
-        }
-
-        dcache_does_alias = (dc->sz / ARC_DCACHE_WAYS) > PAGE_SIZE;
 
         /* check for D-Cache aliasing */
+        dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
+
         if (dcache_does_alias && !cache_is_vipt_aliasing())
                 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
         else if (!dcache_does_alias && cache_is_vipt_aliasing())
@@ -239,11 +261,9 @@ static inline void wait_for_flush(void)
  */
 static inline void __dc_entire_op(const int cacheop)
 {
-        unsigned long flags, tmp = tmp;
+        unsigned int tmp = tmp;
         int aux;
 
-        local_irq_save(flags);
-
         if (cacheop == OP_FLUSH_N_INV) {
                 /* Dcache provides 2 cmd: FLUSH or INV
                  * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
@@ -267,8 +287,6 @@ static inline void __dc_entire_op(const int cacheop)
         /* Switch back the DISCARD ONLY Invalidate mode */
         if (cacheop == OP_FLUSH_N_INV)
                 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
-
-        local_irq_restore(flags);
 }
 
 /*
@@ -459,8 +477,15 @@ static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
         local_irq_restore(flags);
 }
 
+static inline void __ic_entire_inv(void)
+{
+        write_aux_reg(ARC_REG_IC_IVIC, 1);
+        read_aux_reg(ARC_REG_IC_CTRL);  /* blocks */
+}
+
 #else
 
+#define __ic_entire_inv()
 #define __ic_line_inv_vaddr(pstart, vstart, sz)
 
 #endif /* CONFIG_ARC_HAS_ICACHE */
@@ -487,7 +512,7 @@ void flush_dcache_page(struct page *page)
         struct address_space *mapping;
 
         if (!cache_is_vipt_aliasing()) {
-                set_bit(PG_arch_1, &page->flags);
+                clear_bit(PG_dc_clean, &page->flags);
                 return;
         }
 
@@ -501,7 +526,7 @@ void flush_dcache_page(struct page *page)
          * Make a note that K-mapping is dirty
          */
         if (!mapping_mapped(mapping)) {
-                set_bit(PG_arch_1, &page->flags);
+                clear_bit(PG_dc_clean, &page->flags);
         } else if (page_mapped(page)) {
 
                 /* kernel reading from page with U-mapping */
@@ -629,26 +654,13 @@ void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
         __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
 }
 
-void flush_icache_all(void)
-{
-        unsigned long flags;
-
-        local_irq_save(flags);
-
-        write_aux_reg(ARC_REG_IC_IVIC, 1);
-
-        /* lr will not complete till the icache inv operation is not over */
-        read_aux_reg(ARC_REG_IC_CTRL);
-        local_irq_restore(flags);
-}
-
 noinline void flush_cache_all(void)
 {
         unsigned long flags;
 
         local_irq_save(flags);
 
-        flush_icache_all();
+        __ic_entire_inv();
         __dc_entire_op(OP_FLUSH_N_INV);
 
         local_irq_restore(flags);
@@ -667,7 +679,12 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
 {
         unsigned int paddr = pfn << PAGE_SHIFT;
 
-        __sync_icache_dcache(paddr, u_vaddr, PAGE_SIZE);
+        u_vaddr &= PAGE_MASK;
+
+        ___flush_dcache_page(paddr, u_vaddr);
+
+        if (vma->vm_flags & VM_EXEC)
+                __inv_icache_page(paddr, u_vaddr);
 }
 
 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
@@ -717,7 +734,7 @@ void copy_user_highpage(struct page *to, struct page *from,
          * non copied user pages (e.g. read faults which wire in pagecache page
          * directly).
          */
-        set_bit(PG_arch_1, &to->flags);
+        clear_bit(PG_dc_clean, &to->flags);
 
         /*
          * if SRC was already usermapped and non-congruent to kernel mapping
@@ -725,15 +742,16 @@ void copy_user_highpage(struct page *to, struct page *from,
          */
         if (clean_src_k_mappings) {
                 __flush_dcache_page(kfrom, kfrom);
+                set_bit(PG_dc_clean, &from->flags);
         } else {
-                set_bit(PG_arch_1, &from->flags);
+                clear_bit(PG_dc_clean, &from->flags);
         }
 }
 
 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
 {
         clear_page(to);
-        set_bit(PG_arch_1, &page->flags);
+        clear_bit(PG_dc_clean, &page->flags);
 }
 
 
diff --git a/arch/arc/mm/fault.c b/arch/arc/mm/fault.c
index 689ffd86d5e9..318164cabdfc 100644
--- a/arch/arc/mm/fault.c
+++ b/arch/arc/mm/fault.c
@@ -15,6 +15,7 @@
 #include <linux/uaccess.h>
 #include <linux/kdebug.h>
 #include <asm/pgalloc.h>
+#include <asm/mmu.h>
 
 static int handle_vmalloc_fault(struct mm_struct *mm, unsigned long address)
 {
@@ -51,14 +52,14 @@ bad_area:
         return 1;
 }
 
-void do_page_fault(struct pt_regs *regs, int write, unsigned long address,
-                   unsigned long cause_code)
+void do_page_fault(struct pt_regs *regs, unsigned long address)
 {
         struct vm_area_struct *vma = NULL;
         struct task_struct *tsk = current;
         struct mm_struct *mm = tsk->mm;
         siginfo_t info;
         int fault, ret;
+        int write = regs->ecr_cause & ECR_C_PROTV_STORE;  /* ST/EX */
         unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
                                 (write ? FAULT_FLAG_WRITE : 0);
 
@@ -109,7 +110,8 @@ good_area:
 
         /* Handle protection violation, execute on heap or stack */
 
-        if (cause_code == ((ECR_V_PROTV << 16) | ECR_C_PROTV_INST_FETCH))
+        if ((regs->ecr_vec == ECR_V_PROTV) &&
+            (regs->ecr_cause == ECR_C_PROTV_INST_FETCH))
                 goto bad_area;
 
         if (write) {
@@ -176,7 +178,6 @@ bad_area_nosemaphore:
         /* User mode accesses just cause a SIGSEGV */
         if (user_mode(regs)) {
                 tsk->thread.fault_address = address;
-                tsk->thread.cause_code = cause_code;
                 info.si_signo = SIGSEGV;
                 info.si_errno = 0;
                 /* info.si_code has been set above */
@@ -197,7 +198,7 @@ no_context:
         if (fixup_exception(regs))
                 return;
 
-        die("Oops", regs, address, cause_code);
+        die("Oops", regs, address);
 
 out_of_memory:
         if (is_global_init(tsk)) {
@@ -218,7 +219,6 @@ do_sigbus:
                 goto no_context;
 
         tsk->thread.fault_address = address;
-        tsk->thread.cause_code = cause_code;
         info.si_signo = SIGBUS;
         info.si_errno = 0;
         info.si_code = BUS_ADRERR;
diff --git a/arch/arc/mm/init.c b/arch/arc/mm/init.c
index 4a177365b2c4..a08ce7185423 100644
--- a/arch/arc/mm/init.c
+++ b/arch/arc/mm/init.c
@@ -74,7 +74,7 @@ void __init setup_arch_memory(void)
         /* Last usable page of low mem (no HIGHMEM yet for ARC port) */
         max_low_pfn = max_pfn = PFN_DOWN(end_mem);
 
-        max_mapnr = num_physpages = max_low_pfn - min_low_pfn;
+        max_mapnr = max_low_pfn - min_low_pfn;
 
         /*------------- reserve kernel image -----------------------*/
         memblock_reserve(CONFIG_LINUX_LINK_BASE,
@@ -84,7 +84,7 @@ void __init setup_arch_memory(void)
 
         /*-------------- node setup --------------------------------*/
         memset(zones_size, 0, sizeof(zones_size));
-        zones_size[ZONE_NORMAL] = num_physpages;
+        zones_size[ZONE_NORMAL] = max_low_pfn - min_low_pfn;
 
         /*
          * We can't use the helper free_area_init(zones[]) because it uses
@@ -106,39 +106,9 @@ void __init setup_arch_memory(void)
  */
 void __init mem_init(void)
 {
-        int codesize, datasize, initsize, reserved_pages, free_pages;
-        int tmp;
-
         high_memory = (void *)(CONFIG_LINUX_LINK_BASE + arc_mem_sz);
-
-        totalram_pages = free_all_bootmem();
-
-        /* count all reserved pages [kernel code/data/mem_map..] */
-        reserved_pages = 0;
-        for (tmp = 0; tmp < max_mapnr; tmp++)
-                if (PageReserved(mem_map + tmp))
-                        reserved_pages++;
-
-        /* XXX: nr_free_pages() is equivalent */
-        free_pages = max_mapnr - reserved_pages;
-
-        /*
-         * For the purpose of display below, split the "reserve mem"
-         * kernel code/data is already shown explicitly,
-         * Show any other reservations (mem_map[ ] et al)
-         */
-        reserved_pages -= (((unsigned int)_end - CONFIG_LINUX_LINK_BASE) >>
-                                                                PAGE_SHIFT);
-
-        codesize = _etext - _text;
-        datasize = _end - _etext;
-        initsize = __init_end - __init_begin;
-
-        pr_info("Memory Available: %dM / %ldM (%dK code, %dK data, %dK init, %dK reserv)\n",
-                PAGES_TO_MB(free_pages),
-                TO_MB(arc_mem_sz),
-                TO_KB(codesize), TO_KB(datasize), TO_KB(initsize),
-                PAGES_TO_KB(reserved_pages));
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 }
 
 /*
@@ -146,13 +116,13 @@ void __init mem_init(void)
  */
 void __init_refok free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index fe1c5a073afe..7957dc4e4d4a 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -55,7 +55,7 @@
 #include <asm/arcregs.h>
 #include <asm/setup.h>
 #include <asm/mmu_context.h>
-#include <asm/tlb.h>
+#include <asm/mmu.h>
 
 /*                      Need for ARC MMU v2
  *
@@ -97,6 +97,7 @@
  * J-TLB entry got evicted/replaced.
  */
 
+
 /* A copy of the ASID from the PID reg is kept in asid_cache */
 int asid_cache = FIRST_ASID;
 
@@ -432,9 +433,14 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
 {
         unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
         unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
+        struct page *page = pfn_to_page(pte_pfn(*ptep));
 
         create_tlb(vma, vaddr, ptep);
 
+        if (page == ZERO_PAGE(0)) {
+                return;
+        }
+
         /*
          * Exec page : Independent of aliasing/page-color considerations,
          *             since icache doesn't snoop dcache on ARC, any dirty
@@ -446,9 +452,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
          */
         if ((vma->vm_flags & VM_EXEC) ||
              addr_not_cache_congruent(paddr, vaddr)) {
-                struct page *page = pfn_to_page(pte_pfn(*ptep));
 
-                int dirty = test_and_clear_bit(PG_arch_1, &page->flags);
+                int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
                 if (dirty) {
                         /* wback + inv dcache lines */
                         __flush_dcache_page(paddr, paddr);
@@ -464,12 +469,27 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
  * the cpuinfo structure for later use.
  * No Validation is done here, simply read/convert the BCRs
  */
-void __cpuinit read_decode_mmu_bcr(void)
+void read_decode_mmu_bcr(void)
 {
-        unsigned int tmp;
-        struct bcr_mmu_1_2 *mmu2;       /* encoded MMU2 attr */
-        struct bcr_mmu_3 *mmu3;         /* encoded MMU3 attr */
         struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
+        unsigned int tmp;
+        struct bcr_mmu_1_2 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+                unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
+#else
+                unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
+#endif
+        } *mmu2;
+
+        struct bcr_mmu_3 {
+#ifdef CONFIG_CPU_BIG_ENDIAN
+        unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
+                     u_itlb:4, u_dtlb:4;
+#else
+        unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
+                     ways:4, ver:8;
+#endif
+        } *mmu3;
 
         tmp = read_aux_reg(ARC_REG_MMU_BCR);
         mmu->ver = (tmp >> 24);
@@ -505,12 +525,12 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
                        "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
                        p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
                        p_mmu->u_dtlb, p_mmu->u_itlb,
-                       __CONFIG_ARC_MMU_SASID_VAL ? "SASID" : "");
+                       IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : "");
 
         return buf;
 }
 
-void __cpuinit arc_mmu_init(void)
+void arc_mmu_init(void)
 {
         char str[256];
         struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S
index 3357d26ffe54..5c5bb23001b0 100644
--- a/arch/arc/mm/tlbex.S
+++ b/arch/arc/mm/tlbex.S
@@ -39,7 +39,7 @@
 
 #include <linux/linkage.h>
 #include <asm/entry.h>
-#include <asm/tlb.h>
+#include <asm/mmu.h>
 #include <asm/pgtable.h>
 #include <asm/arcregs.h>
 #include <asm/cache.h>
@@ -147,9 +147,9 @@ ex_saved_reg1:
 #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
         and.f 0, r0, _PAGE_PRESENT
         bz   1f
-        ld   r2, [num_pte_not_present]
-        add  r2, r2, 1
-        st   r2, [num_pte_not_present]
+        ld   r3, [num_pte_not_present]
+        add  r3, r3, 1
+        st   r3, [num_pte_not_present]
 1:
 #endif
 
@@ -271,22 +271,22 @@ ARC_ENTRY EV_TLBMissI
 #endif
 
         ;----------------------------------------------------------------
-        ; Get the PTE corresponding to V-addr accessed
+        ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
         LOAD_FAULT_PTE
 
         ;----------------------------------------------------------------
         ; VERIFY_PTE: Check if PTE permissions approp for executing code
         cmp_s   r2, VMALLOC_START
-        mov.lo  r2, (_PAGE_PRESENT | _PAGE_U_READ | _PAGE_U_EXECUTE)
-        mov.hs  r2, (_PAGE_PRESENT | _PAGE_K_READ | _PAGE_K_EXECUTE)
+        mov.lo  r2, (_PAGE_PRESENT | _PAGE_U_EXECUTE)
+        mov.hs  r2, (_PAGE_PRESENT | _PAGE_K_EXECUTE)
 
         and     r3, r0, r2  ; Mask out NON Flag bits from PTE
         xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )
         bnz     do_slow_path_pf
 
         ; Let Linux VM know that the page was accessed
-        or      r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED)  ; set Accessed Bit
-        st_s    r0, [r1]                                  ; Write back PTE
+        or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit
+        st_s    r0, [r1]                ; Write back PTE
 
         CONV_PTE_TO_TLB
         COMMIT_ENTRY_TO_MMU
@@ -311,7 +311,7 @@ ARC_ENTRY EV_TLBMissD
 
         ;----------------------------------------------------------------
         ; Get the PTE corresponding to V-addr accessed
-        ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE
+        ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
         LOAD_FAULT_PTE
 
         ;----------------------------------------------------------------
@@ -345,7 +345,7 @@ ARC_ENTRY EV_TLBMissD
         ;----------------------------------------------------------------
         ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
         lr      r3, [ecr]
-        or      r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED) ; Accessed bit always
+        or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
         btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?
         or.nz   r0, r0, _PAGE_MODIFIED        ; if Write, set Dirty bit as well
         st_s    r0, [r1]                      ; Write back PTE
@@ -381,18 +381,7 @@ do_slow_path_pf:
 
         ; ------- setup args for Linux Page fault Hanlder ---------
         mov_s r0, sp
-        lr  r2, [efa]
-        lr  r3, [ecr]
-
-        ; Both st and ex imply WRITE access of some sort, hence do_page_fault( )
-        ; invoked with write=1 for DTLB-st/ex Miss and write=0 for ITLB miss or
-        ; DTLB-ld Miss
-        ; DTLB Miss Cause code is ld = 0x01 , st = 0x02, ex = 0x03
-        ; Following code uses that fact that st/ex have one bit in common
-
-        btst_s r3,  ECR_C_BIT_DTLB_ST_MISS
-        mov.z  r1, 0
-        mov.nz r1, 1
+        lr  r1, [efa]
 
         ; We don't want exceptions to be disabled while the fault is handled.
         ; Now that we have saved the context we return from exception hence
diff --git a/arch/arc/plat-arcfpga/platform.c b/arch/arc/plat-arcfpga/platform.c
index b3700c064c06..d71f3c3bcf24 100644
--- a/arch/arc/plat-arcfpga/platform.c
+++ b/arch/arc/plat-arcfpga/platform.c
@@ -77,6 +77,7 @@ static void __init setup_bvci_lat_unit(void)
 
 /*----------------------- Platform Devices -----------------------------*/
 
+#if IS_ENABLED(CONFIG_SERIAL_ARC)
 static unsigned long arc_uart_info[] = {
         0,      /* uart->is_emulated (runtime @running_on_hw) */
         0,      /* uart->port.uartclk */
@@ -115,7 +116,7 @@ static struct platform_device arc_uart0_dev = {
 static struct platform_device *fpga_early_devs[] __initdata = {
         &arc_uart0_dev,
 };
-#endif
+#endif  /* CONFIG_SERIAL_ARC_CONSOLE */
 
 static void arc_fpga_serial_init(void)
 {
@@ -152,8 +153,13 @@ static void arc_fpga_serial_init(void)
          * otherwise the early console never gets a chance to run.
          */
         add_preferred_console("ttyARC", 0, "115200");
-#endif
+#endif  /* CONFIG_SERIAL_ARC_CONSOLE */
+}
+#else   /* !IS_ENABLED(CONFIG_SERIAL_ARC) */
+static void arc_fpga_serial_init(void)
+{
 }
+#endif
 
 static void __init plat_fpga_early_init(void)
 {
@@ -169,7 +175,7 @@ static void __init plat_fpga_early_init(void)
 }
 
 static struct of_dev_auxdata plat_auxdata_lookup[] __initdata = {
-#if defined(CONFIG_SERIAL_ARC) || defined(CONFIG_SERIAL_ARC_MODULE)
+#if IS_ENABLED(CONFIG_SERIAL_ARC)
         OF_DEV_AUXDATA("snps,arc-uart", UART0_BASE, "arc-uart", arc_uart_info),
 #endif
         {}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 49d993cee512..531cdda016f9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -9,7 +9,7 @@ config ARM
         select BUILDTIME_EXTABLE_SORT if MMU
         select CPU_PM if (SUSPEND || CPU_IDLE)
         select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
-        select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
+        select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
@@ -175,6 +175,9 @@ config ARCH_HAS_CPUFREQ
           and that the relevant menu configurations are displayed for
           it.
 
+config ARCH_HAS_BANDGAP
+        bool
+
 config GENERIC_HWEIGHT
         bool
         default y
@@ -366,11 +369,12 @@ config ARCH_CLPS711X
         select ARCH_REQUIRE_GPIOLIB
         select AUTO_ZRELADDR
         select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
         select COMMON_CLK
         select CPU_ARM720T
         select GENERIC_CLOCKEVENTS
+        select MFD_SYSCON
         select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
         select SPARSE_IRQ
         help
           Support for Cirrus Logic 711x/721x/731x based boards.
@@ -502,6 +506,7 @@ config ARCH_DOVE
 
 config ARCH_KIRKWOOD
         bool "Marvell Kirkwood"
+        select ARCH_HAS_CPUFREQ
         select ARCH_REQUIRE_GPIOLIB
         select CPU_FEROCEON
         select GENERIC_CLOCKEVENTS
@@ -623,8 +628,8 @@ config ARCH_MSM
         bool "Qualcomm MSM"
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
         help
           Support for Qualcomm MSM/QSD based systems.  This runs on the
           apps processor of the MSM/QSD and depends on a shared memory
@@ -634,6 +639,7 @@ config ARCH_MSM
 
 config ARCH_SHMOBILE
         bool "Renesas SH-Mobile / R-Mobile"
+        select ARM_PATCH_PHYS_VIRT
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU if SMP
@@ -643,9 +649,8 @@ config ARCH_SHMOBILE
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
         select MULTI_IRQ_HANDLER
-        select NEED_MACH_MEMORY_H
         select NO_IOPORT
-        select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
+        select PINCTRL
         select PM_GENERIC_DOMAINS if PM
         select SPARSE_IRQ
         help
@@ -695,6 +700,7 @@ config ARCH_S3C24XX
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -702,6 +708,7 @@ config ARCH_S3C24XX
         select MULTI_IRQ_HANDLER
         select NEED_MACH_GPIO_H
         select NEED_MACH_IO_H
+        select SAMSUNG_ATAGS
         help
           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
@@ -717,6 +724,7 @@ config ARCH_S3C64XX
         select CLKSRC_MMIO
         select CPU_V6
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -726,9 +734,11 @@ config ARCH_S3C64XX
         select PLAT_SAMSUNG
         select S3C_DEV_NAND
         select S3C_GPIO_TRACK
+        select SAMSUNG_ATAGS
         select SAMSUNG_CLKSRC
         select SAMSUNG_GPIOLIB_4BIT
         select SAMSUNG_IRQ_VIC_TIMER
+        select SAMSUNG_WDT_RESET
         select USB_ARCH_HAS_OHCI
         help
           Samsung S3C64XX series based systems
@@ -739,11 +749,14 @@ config ARCH_S5P64X0
         select CLKSRC_MMIO
         select CPU_V6
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
+        select SAMSUNG_WDT_RESET
+        select SAMSUNG_ATAGS
         help
           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
           SMDK6450.
@@ -755,11 +768,14 @@ config ARCH_S5PC100
         select CLKSRC_MMIO
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
+        select SAMSUNG_WDT_RESET
+        select SAMSUNG_ATAGS
         help
           Samsung S5PC100 series based systems
 
@@ -772,12 +788,14 @@ config ARCH_S5PV210
         select CLKSRC_MMIO
         select CPU_V7
         select GENERIC_CLOCKEVENTS
+        select GPIO_SAMSUNG
         select HAVE_CLK
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
         select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
+        select SAMSUNG_ATAGS
         help
           Samsung S5PV210/S5PC110 series based systems
 
@@ -785,7 +803,9 @@ config ARCH_EXYNOS
         bool "Samsung EXYNOS"
         select ARCH_HAS_CPUFREQ
         select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_REQUIRE_GPIOLIB
         select ARCH_SPARSEMEM_ENABLE
+        select ARM_GIC
         select CLKDEV_LOOKUP
         select COMMON_CLK
         select CPU_V7
@@ -794,8 +814,9 @@ config ARCH_EXYNOS
         select HAVE_S3C2410_I2C if I2C
         select HAVE_S3C2410_WATCHDOG if WATCHDOG
         select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_GPIO_H
         select NEED_MACH_MEMORY_H
+        select SPARSE_IRQ
+        select USE_OF
         help
           Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 
@@ -813,23 +834,6 @@ config ARCH_SHARK
           Support for the StrongARM based Digital DNARD machine, also known
           as "Shark" (<http://www.shark-linux.de/shark.html>).
 
-config ARCH_U300
-        bool "ST-Ericsson U300 Series"
-        depends on MMU
-        select ARCH_REQUIRE_GPIOLIB
-        select ARM_AMBA
-        select ARM_PATCH_PHYS_VIRT
-        select ARM_VIC
-        select CLKDEV_LOOKUP
-        select CLKSRC_MMIO
-        select COMMON_CLK
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-        select HAVE_TCM
-        select SPARSE_IRQ
-        help
-          Support for ST-Ericsson U300 series mobile platforms.
-
 config ARCH_DAVINCI
         bool "TI DaVinci"
         select ARCH_HAS_HOLES_MEMORYMODEL
@@ -840,6 +844,7 @@ config ARCH_DAVINCI
         select GENERIC_IRQ_CHIP
         select HAVE_IDE
         select NEED_MACH_GPIO_H
+        select TI_PRIV_EDMA
         select USE_OF
         select ZONE_DMA
         help
@@ -871,20 +876,21 @@ menu "Multiple platform selection"
 
 comment "CPU Core family selection"
 
-config ARCH_MULTI_V4
-        bool "ARMv4 based platforms (FA526, StrongARM)"
-        depends on !ARCH_MULTI_V6_V7
-        select ARCH_MULTI_V4_V5
-
 config ARCH_MULTI_V4T
         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
         depends on !ARCH_MULTI_V6_V7
         select ARCH_MULTI_V4_V5
+        select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
+                CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM940T)
 
 config ARCH_MULTI_V5
         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
         depends on !ARCH_MULTI_V6_V7
         select ARCH_MULTI_V4_V5
+        select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
+                CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 
 config ARCH_MULTI_V4_V5
         bool
@@ -948,6 +954,8 @@ source "arch/arm/mach-iop13xx/Kconfig"
 
 source "arch/arm/mach-ixp4xx/Kconfig"
 
+source "arch/arm/mach-keystone/Kconfig"
+
 source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
@@ -964,6 +972,8 @@ source "arch/arm/mach-netx/Kconfig"
 
 source "arch/arm/mach-nomadik/Kconfig"
 
+source "arch/arm/mach-nspire/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
@@ -981,6 +991,8 @@ source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-realview/Kconfig"
 
+source "arch/arm/mach-rockchip/Kconfig"
+
 source "arch/arm/mach-sa1100/Kconfig"
 
 source "arch/arm/plat-samsung/Kconfig"
@@ -989,6 +1001,8 @@ source "arch/arm/mach-socfpga/Kconfig"
 
 source "arch/arm/mach-spear/Kconfig"
 
+source "arch/arm/mach-sti/Kconfig"
+
 source "arch/arm/mach-s3c24xx/Kconfig"
 
 if ARCH_S3C64XX
@@ -1087,6 +1101,20 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config PJ4B_ERRATA_4742
+        bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
+        depends on CPU_PJ4B && MACH_ARMADA_370
+        default y
+        help
+          When coming out of either a Wait for Interrupt (WFI) or a Wait for
+          Event (WFE) IDLE states, a specific timing sensitivity exists between
+          the retiring WFI/WFE instructions and the newly issued subsequent
+          instructions.  This sensitivity can result in a CPU hang scenario.
+          Workaround:
+          The software must insert either a Data Synchronization Barrier (DSB)
+          or Data Memory Barrier (DMB) command immediately after the WFI/WFE
+          instruction
+
 config ARM_ERRATA_326103
         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
         depends on CPU_V6
@@ -1189,6 +1217,16 @@ config PL310_ERRATA_588369
            is not correctly implemented in PL310 as clean lines are not
            invalidated as a result of these operations.
 
+config ARM_ERRATA_643719
+        bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 643719 Cortex-A9 (prior to
+          r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
+          register returns zero when it should return one. The workaround
+          corrects this value, ensuring cache maintenance operations which use
+          it behave as intended and avoiding data corruption.
+
 config ARM_ERRATA_720789
         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
         depends on CPU_V7
@@ -1393,6 +1431,7 @@ config PCI_HOST_ITE8152
         select DMABOUNCE
 
 source "drivers/pci/Kconfig"
+source "drivers/pci/pcie/Kconfig"
 
 source "drivers/pcmcia/Kconfig"
 
@@ -1414,7 +1453,7 @@ config SMP
         depends on CPU_V6K || CPU_V7
         depends on GENERIC_CLOCKEVENTS
         depends on HAVE_SMP
-        depends on MMU
+        depends on MMU || ARM_MPU
         select USE_GENERIC_SMP_HELPERS
         help
           This enables support for systems with more than one CPU. If you have
@@ -1435,7 +1474,7 @@ config SMP
 
 config SMP_ON_UP
         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
-        depends on SMP && !XIP_KERNEL
+        depends on SMP && !XIP_KERNEL && MMU
         default y
         help
           SMP kernels contain instructions which fail on non-SMP processors.
@@ -1528,7 +1567,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
-        depends on SMP && HOTPLUG
+        depends on SMP
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
@@ -1560,6 +1599,7 @@ config ARCH_NR_GPIO
         int
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 512 if SOC_OMAP5
+        default 512 if ARCH_KEYSTONE
         default 392 if ARCH_U8500
         default 352 if ARCH_VT8500
         default 288 if ARCH_SUNXI
@@ -1585,7 +1625,7 @@ config SCHED_HRTICK
 
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
-        depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+        depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
         default y if CPU_THUMBONLY
         select AEABI
         select ARM_ASM_UNIFIED
@@ -1707,6 +1747,14 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+       def_bool y
+       depends on ARM_LPAE
+
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+       def_bool y
+       depends on ARM_LPAE
+
 source "mm/Kconfig"
 
 config FORCE_MAX_ZONEORDER
@@ -2006,7 +2054,7 @@ config XIP_PHYS_ADDR
 
 config KEXEC
         bool "Kexec system call (EXPERIMENTAL)"
-        depends on (!SMP || HOTPLUG_CPU)
+        depends on (!SMP || PM_SLEEP_SMP)
         help
           kexec is a system call that implements the ability to shutdown your
           current kernel, and to start another kernel.  It is like a reboot
@@ -2040,7 +2088,7 @@ config CRASH_DUMP
 
 config AUTO_ZRELADDR
         bool "Auto calculation of the decompressed kernel image address"
-        depends on !ZBOOT_ROM && !ARCH_U300
+        depends on !ZBOOT_ROM
         help
           ZRELADDR is the physical address where the decompressed kernel
           image will be placed. If AUTO_ZRELADDR is selected, the address
@@ -2054,53 +2102,6 @@ menu "CPU Power Management"
 
 if ARCH_HAS_CPUFREQ
 source "drivers/cpufreq/Kconfig"
-
-config CPU_FREQ_S3C
-        bool
-        help
-          Internal configuration node for common cpufreq on Samsung SoC
-
-config CPU_FREQ_S3C24XX
-        bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
-        depends on ARCH_S3C24XX && CPU_FREQ
-        select CPU_FREQ_S3C
-        help
-          This enables the CPUfreq driver for the Samsung S3C24XX family
-          of CPUs.
-
-          For details, take a look at <file:Documentation/cpu-freq>.
-
-          If in doubt, say N.
-
-config CPU_FREQ_S3C24XX_PLL
-        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Compile in support for changing the PLL frequency from the
-          S3C24XX series CPUfreq driver. The PLL takes time to settle
-          after a frequency change, so by default it is not enabled.
-
-          This also means that the PLL tables for the selected CPU(s) will
-          be built which may increase the size of the kernel image.
-
-config CPU_FREQ_S3C24XX_DEBUG
-        bool "Debug CPUfreq Samsung driver core"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
-
-config CPU_FREQ_S3C24XX_IODEBUG
-        bool "Debug CPUfreq Samsung driver IO timing"
-        depends on CPU_FREQ_S3C24XX
-        help
-          Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
-
-config CPU_FREQ_S3C24XX_DEBUGFS
-        bool "Export debugfs for CPUFreq"
-        depends on CPU_FREQ_S3C24XX && DEBUG_FS
-        help
-          Export status information via debugfs.
-
 endif
 
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
index 2cef8e13f9f8..aed66d5df7f1 100644
--- a/arch/arm/Kconfig-nommu
+++ b/arch/arm/Kconfig-nommu
@@ -28,7 +28,7 @@ config FLASH_SIZE
 config PROCESSOR_ID
         hex 'Hard wire the processor ID'
         default 0x00007700
-        depends on !CPU_CP15
+        depends on !(CPU_CP15 || CPU_V7M)
         help
           If processor has no CP15 register, this processor ID is
           used instead of the auto-probing which utilizes the register.
@@ -50,3 +50,15 @@ config REMAP_VECTORS_TO_RAM
           Otherwise, say 'y' here.  In this case, the kernel will require
           external support to redirect the hardware exception vectors to
           the writable versions located at DRAM_BASE.
+
+config ARM_MPU
+       bool 'Use the ARM v7 PMSA Compliant MPU'
+       depends on CPU_V7
+       default y
+       help
+         Some ARM systems without an MMU have instead a Memory Protection
+         Unit (MPU) that defines the type and permissions for regions of
+         memory.
+
+         If your CPU has an MPU then you should choose 'y' here unless you
+         know that you do not want to use the MPU.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 1d41908d5cda..5b7be8d975b5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -251,6 +251,27 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on i.MX6Q/DL.
 
+        config DEBUG_IMX6SL_UART
+                bool "i.MX6SL Debug UART"
+                depends on SOC_IMX6SL
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX6SL.
+
+        config DEBUG_KEYSTONE_UART0
+                bool "Kernel low-level debugging on KEYSTONE2 using UART0"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART0 serial port on KEYSTONE2 devices.
+
+        config DEBUG_KEYSTONE_UART1
+                bool "Kernel low-level debugging on KEYSTONE2 using UART1"
+                depends on ARCH_KEYSTONE
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART1 serial port on KEYSTONE2 devices.
+
         config DEBUG_MMP_UART2
                 bool "Kernel low-level debugging message via MMP UART2"
                 depends on ARCH_MMP
@@ -303,12 +324,37 @@ choice
                   their output to the serial port on MSM 8960 devices.
 
         config DEBUG_MVEBU_UART
-                bool "Kernel low-level debugging messages via MVEBU UART"
+                bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
+                depends on ARCH_MVEBU
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on MVEBU based platforms.
+
+                  This option should be used with the old bootloaders
+                  that left the internal registers mapped at
+                  0xd0000000. As of today, this is the case on
+                  platforms such as the Globalscale Mirabox or the
+                  Plathome OpenBlocks AX3, when using the original
+                  bootloader.
+
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
+
+        config DEBUG_MVEBU_UART_ALTERNATE
+                bool "Kernel low-level debugging messages via MVEBU UART (new bootloaders)"
                 depends on ARCH_MVEBU
                 help
                   Say Y here if you want kernel low-level debugging support
                   on MVEBU based platforms.
 
+                  This option should be used with the new bootloaders
+                  that remap the internal registers at 0xf1000000.
+
+                  If the wrong DEBUG_MVEBU_UART* option is selected,
+                  when u-boot hands over to the kernel, the system
+                  silently crashes, with no serial output at all.
+
         config DEBUG_NOMADIK_UART
                 bool "Kernel low-level debugging messages via NOMADIK UART"
                 depends on ARCH_NOMADIK
@@ -316,6 +362,20 @@ choice
                   Say Y here if you want kernel low-level debugging support
                   on NOMADIK based platforms.
 
+        config DEBUG_NSPIRE_CLASSIC_UART
+                bool "Kernel low-level debugging via TI-NSPIRE 8250 UART"
+                depends on ARCH_NSPIRE
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on TI-NSPIRE classic models.
+
+        config DEBUG_NSPIRE_CX_UART
+                bool "Kernel low-level debugging via TI-NSPIRE PL011 UART"
+                depends on ARCH_NSPIRE
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on TI-NSPIRE CX models.
+
         config DEBUG_OMAP2PLUS_UART
                 bool "Kernel low-level debugging messages via OMAP2PLUS UART"
                 depends on ARCH_OMAP2PLUS
@@ -353,6 +413,13 @@ choice
                   their output to the standard serial port on the RealView
                   PB1176 platform.
 
+        config DEBUG_ROCKCHIP_UART
+                bool "Kernel low-level debugging messages via Rockchip UART"
+                depends on ARCH_ROCKCHIP
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on Rockchip based platforms.
+
         config DEBUG_S3C_UART0
                 depends on PLAT_SAMSUNG
                 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -443,6 +510,13 @@ choice
                   Say Y here if you want the debug print routines to direct
                   their output to the uart1 port on SiRFmarco devices.
 
+        config DEBUG_U300_UART
+                bool "Kernel low-level debugging messages via U300 UART0"
+                depends on ARCH_U300
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the uart port on U300 devices.
+
         config DEBUG_UX500_UART
                 depends on ARCH_U8500
                 bool "Use Ux500 UART for low-level debug"
@@ -476,6 +550,13 @@ choice
                   of the tiles using the RS1 memory map, including all new A-class
                   core tiles, FPGA-based SMMs and software models.
 
+        config DEBUG_VEXPRESS_UART0_CRX
+                bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)"
+                depends on ARCH_VEXPRESS && !MMU
+                help
+                  This option selects UART0 at 0xb0090000. This is appropriate for
+                  Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7
+
         config DEBUG_VT8500_UART0
                 bool "Use UART0 on VIA/Wondermedia SoCs"
                 depends on ARCH_VT8500
@@ -483,6 +564,16 @@ choice
                   This option selects UART0 on VIA/Wondermedia System-on-a-chip
                   devices, including VT8500, WM8505, WM8650 and WM8850.
 
+        config DEBUG_STI_UART
+                depends on ARCH_STI
+                bool "Use StiH415/416 ASC for low-level debug"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on StiH415/416 based platforms like B2000, B2020.
+                  It support UART2 and SBC_UART1.
+
+                  If unsure, say N.
+
         config DEBUG_LL_UART_NONE
                 bool "No low-level debugging UART"
                 depends on !ARCH_MULTIPLATFORM
@@ -532,7 +623,8 @@ config DEBUG_IMX_UART_PORT
                                                 DEBUG_IMX35_UART || \
                                                 DEBUG_IMX51_UART || \
                                                 DEBUG_IMX53_UART || \
-                                                DEBUG_IMX6Q_UART
+                                                DEBUG_IMX6Q_UART || \
+                                                DEBUG_IMX6SL_UART
         default 1
         depends on ARCH_MXC
         help
@@ -589,6 +681,32 @@ endchoice
 
 choice
         prompt "Low-level debug console UART"
+        depends on DEBUG_ROCKCHIP_UART
+
+        config DEBUG_RK29_UART0
+                bool "RK29 UART0"
+
+        config DEBUG_RK29_UART1
+                bool "RK29 UART1"
+
+        config DEBUG_RK29_UART2
+                bool "RK29 UART2"
+
+        config DEBUG_RK3X_UART0
+                bool "RK3X UART0"
+
+        config DEBUG_RK3X_UART1
+                bool "RK3X UART1"
+
+        config DEBUG_RK3X_UART2
+                bool "RK3X UART2"
+
+        config DEBUG_RK3X_UART3
+                bool "RK3X UART3"
+endchoice
+
+choice
+        prompt "Low-level debug console UART"
         depends on DEBUG_LL && DEBUG_TEGRA_UART
 
         config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -617,6 +735,30 @@ choice
 
 endchoice
 
+choice
+        prompt "Low-level debug console UART"
+        depends on DEBUG_LL && DEBUG_STI_UART
+
+        config STIH41X_DEBUG_ASC2
+                bool "ASC2 UART"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on STiH415/416 based platforms like b2000, which has
+                  default UART wired up to ASC2.
+
+                  If unsure, say N.
+
+        config STIH41X_DEBUG_SBC_ASC1
+                bool "SBC ASC1 UART"
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on STiH415/416 based platforms like b2020. which has
+                  default UART wired up to SBC ASC1.
+
+                  If unsure, say N.
+
+endchoice
+
 config DEBUG_LL_INCLUDE
         string
         default "debug/bcm2835.S" if DEBUG_BCM2835
@@ -631,21 +773,31 @@ config DEBUG_LL_INCLUDE
                                  DEBUG_IMX35_UART || \
                                  DEBUG_IMX51_UART || \
                                  DEBUG_IMX53_UART ||\
-                                 DEBUG_IMX6Q_UART
-        default "debug/mvebu.S" if DEBUG_MVEBU_UART
+                                 DEBUG_IMX6Q_UART || \
+                                 DEBUG_IMX6SL_UART
+        default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \
+                                      DEBUG_KEYSTONE_UART1
+        default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
+                                   DEBUG_MVEBU_UART_ALTERNATE
         default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
         default "debug/nomadik.S" if DEBUG_NOMADIK_UART
+        default "debug/nspire.S" if     DEBUG_NSPIRE_CX_UART || \
+                                        DEBUG_NSPIRE_CLASSIC_UART
         default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
         default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
         default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
                                  DEBUG_MMP_UART3
+        default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
         default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
         default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
+        default "debug/sti.S" if DEBUG_STI_UART
         default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
         default "debug/tegra.S" if DEBUG_TEGRA_UART
+        default "debug/u300.S" if DEBUG_U300_UART
         default "debug/ux500.S" if DEBUG_UX500_UART
         default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
-                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
+                DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \
+                DEBUG_VEXPRESS_UART0_CRX
         default "debug/vt8500.S" if DEBUG_VT8500_UART0
         default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
         default "mach/debug-macro.S"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1ba358ba16b8..c0ac0f5e5e5c 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -59,37 +59,44 @@ comma = ,
 # Note that GCC does not numerically define an architecture version
 # macro, but instead defines a whole series of macros which makes
 # testing for a specific architecture or later rather impossible.
-arch-$(CONFIG_CPU_32v7)         :=-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
-arch-$(CONFIG_CPU_32v6)         :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
+arch-$(CONFIG_CPU_32v7M)        =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
+arch-$(CONFIG_CPU_32v7)         =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
+arch-$(CONFIG_CPU_32v6)         =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
 # Only override the compiler option if ARMv6. The ARMv6K extensions are
 # always available in ARMv7
 ifeq ($(CONFIG_CPU_32v6),y)
-arch-$(CONFIG_CPU_32v6K)        :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
+arch-$(CONFIG_CPU_32v6K)        =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
 endif
-arch-$(CONFIG_CPU_32v5)         :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
-arch-$(CONFIG_CPU_32v4T)        :=-D__LINUX_ARM_ARCH__=4 -march=armv4t
-arch-$(CONFIG_CPU_32v4)         :=-D__LINUX_ARM_ARCH__=4 -march=armv4
-arch-$(CONFIG_CPU_32v3)         :=-D__LINUX_ARM_ARCH__=3 -march=armv3
+arch-$(CONFIG_CPU_32v5)         =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
+arch-$(CONFIG_CPU_32v4T)        =-D__LINUX_ARM_ARCH__=4 -march=armv4t
+arch-$(CONFIG_CPU_32v4)         =-D__LINUX_ARM_ARCH__=4 -march=armv4
+arch-$(CONFIG_CPU_32v3)         =-D__LINUX_ARM_ARCH__=3 -march=armv3
+
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
 
 # This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM7TDMI)     :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM720T)      :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM740T)      :=-mtune=arm7tdmi
-tune-$(CONFIG_CPU_ARM9TDMI)     :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM940T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM946E)      :=$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
-tune-$(CONFIG_CPU_ARM920T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM922T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM925T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_ARM926T)      :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_FA526)        :=-mtune=arm9tdmi
-tune-$(CONFIG_CPU_SA110)        :=-mtune=strongarm110
-tune-$(CONFIG_CPU_SA1100)       :=-mtune=strongarm1100
-tune-$(CONFIG_CPU_XSCALE)       :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_XSC3)         :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
-tune-$(CONFIG_CPU_FEROCEON)     :=$(call cc-option,-mtune=marvell-f,-mtune=xscale)
-tune-$(CONFIG_CPU_V6)           :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
-tune-$(CONFIG_CPU_V6K)          :=$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_ARM7TDMI)     =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM720T)      =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM740T)      =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM9TDMI)     =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM940T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM946E)      =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
+tune-$(CONFIG_CPU_ARM920T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM922T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM925T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_ARM926T)      =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_FA526)        =-mtune=arm9tdmi
+tune-$(CONFIG_CPU_SA110)        =-mtune=strongarm110
+tune-$(CONFIG_CPU_SA1100)       =-mtune=strongarm1100
+tune-$(CONFIG_CPU_XSCALE)       =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_XSC3)         =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
+tune-$(CONFIG_CPU_FEROCEON)     =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
+tune-$(CONFIG_CPU_V6)           =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+tune-$(CONFIG_CPU_V6K)          =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
+
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
 
 ifeq ($(CONFIG_AEABI),y)
 CFLAGS_ABI      :=-mabi=aapcs-linux -mno-thumb-interwork
@@ -164,13 +171,15 @@ machine-$(CONFIG_ARCH_MXS)		+= mxs
 machine-$(CONFIG_ARCH_MVEBU)            += mvebu
 machine-$(CONFIG_ARCH_NETX)             += netx
 machine-$(CONFIG_ARCH_NOMADIK)          += nomadik
+machine-$(CONFIG_ARCH_NSPIRE)           += nspire
 machine-$(CONFIG_ARCH_OMAP1)            += omap1
 machine-$(CONFIG_ARCH_OMAP2PLUS)        += omap2
 machine-$(CONFIG_ARCH_ORION5X)          += orion5x
 machine-$(CONFIG_ARCH_PICOXCELL)        += picoxcell
-machine-$(CONFIG_ARCH_PRIMA2)           += prima2
+machine-$(CONFIG_ARCH_SIRF)             += prima2
 machine-$(CONFIG_ARCH_PXA)              += pxa
 machine-$(CONFIG_ARCH_REALVIEW)         += realview
+machine-$(CONFIG_ARCH_ROCKCHIP)         += rockchip
 machine-$(CONFIG_ARCH_RPC)              += rpc
 machine-$(CONFIG_ARCH_S3C24XX)          += s3c24xx
 machine-$(CONFIG_ARCH_S3C64XX)          += s3c64xx
@@ -191,12 +200,15 @@ machine-$(CONFIG_ARCH_W90X900)		+= w90x900
 machine-$(CONFIG_FOOTBRIDGE)            += footbridge
 machine-$(CONFIG_ARCH_SOCFPGA)          += socfpga
 machine-$(CONFIG_PLAT_SPEAR)            += spear
+machine-$(CONFIG_ARCH_STI)              += sti
 machine-$(CONFIG_ARCH_VIRT)             += virt
 machine-$(CONFIG_ARCH_ZYNQ)             += zynq
 machine-$(CONFIG_ARCH_SUNXI)            += sunxi
+machine-$(CONFIG_ARCH_KEYSTONE)         += keystone
 
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
+plat-$(CONFIG_ARCH_EXYNOS)      += samsung
 plat-$(CONFIG_ARCH_OMAP)        += omap
 plat-$(CONFIG_ARCH_S3C64XX)     += samsung
 plat-$(CONFIG_PLAT_IOP)         += iop
@@ -289,9 +301,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-%.dtb: scripts
+%.dtb: | scripts
         $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@
 
+PHONY += dtbs
 dtbs: scripts
         $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) dtbs
 
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3580d57ea218..48d0a44270bd 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -27,7 +27,7 @@ OBJS	+= misc.o decompress.o
 ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
 OBJS    += debug.o
 endif
-FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
+FONTC   = $(srctree)/lib/fonts/font_acorn_8x8.c
 
 # string library code (-Os is enforced to keep it much smaller)
 OBJS            += string.o
@@ -116,7 +116,8 @@ targets       := vmlinux vmlinux.lds \
 
 # Make sure files are removed during clean
 extra-y       += piggy.gzip piggy.lzo piggy.lzma piggy.xzkern \
-                 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs)
+                 lib1funcs.S ashldi3.S $(libfdt) $(libfdt_hdrs) \
+                 hyp-stub.S
 
 ifeq ($(CONFIG_FUNCTION_TRACER),y)
 ORIG_CFLAGS := $(KBUILD_CFLAGS)
@@ -124,7 +125,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
 endif
 
 ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
 
 # Supply kernel BSS size to the decompressor via a linker symbol.
 KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index aabc02a68482..d1153c8a765a 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -53,6 +53,17 @@ static const void *getprop(const void *fdt, const char *node_path,
         return fdt_getprop(fdt, offset, property, len);
 }
 
+static uint32_t get_cell_size(const void *fdt)
+{
+        int len;
+        uint32_t cell_size = 1;
+        const uint32_t *size_len =  getprop(fdt, "/", "#size-cells", &len);
+
+        if (size_len)
+                cell_size = fdt32_to_cpu(*size_len);
+        return cell_size;
+}
+
 static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 {
         char cmdline[COMMAND_LINE_SIZE];
@@ -95,9 +106,11 @@ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
 int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 {
         struct tag *atag = atag_list;
-        uint32_t mem_reg_property[2 * NR_BANKS];
+        /* In the case of 64 bits memory size, need to reserve 2 cells for
+         * address and size for each bank */
+        uint32_t mem_reg_property[2 * 2 * NR_BANKS];
         int memcount = 0;
-        int ret;
+        int ret, memsize;
 
         /* make sure we've got an aligned pointer */
         if ((u32)atag_list & 0x3)
@@ -137,8 +150,25 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                                 continue;
                         if (!atag->u.mem.size)
                                 continue;
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
-                        mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
+                        memsize = get_cell_size(fdt);
+
+                        if (memsize == 2) {
+                                /* if memsize is 2, that means that
+                                 * each data needs 2 cells of 32 bits,
+                                 * so the data are 64 bits */
+                                uint64_t *mem_reg_prop64 =
+                                        (uint64_t *)mem_reg_property;
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.start);
+                                mem_reg_prop64[memcount++] =
+                                        cpu_to_fdt64(atag->u.mem.size);
+                        } else {
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.start);
+                                mem_reg_property[memcount++] =
+                                        cpu_to_fdt32(atag->u.mem.size);
+                        }
+
                 } else if (atag->hdr.tag == ATAG_INITRD2) {
                         uint32_t initrd_start, initrd_size;
                         initrd_start = atag->u.initrd.start;
@@ -150,8 +180,10 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
                 }
         }
 
-        if (memcount)
-                setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
+        if (memcount) {
+                setprop(fdt, "/memory", "reg", mem_reg_property,
+                        4 * memcount * memsize);
+        }
 
         return fdt_pack(fdt);
 }
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6e8382d5b7a4..5392ee63338f 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -1,6 +1,8 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+#ifndef CONFIG_DEBUG_SEMIHOSTING
+
 #include CONFIG_DEBUG_LL_INCLUDE
 
 ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
         busyuart r3, r1
         mov      pc, lr
 ENDPROC(putc)
+
+#else
+
+ENTRY(putc)
+        adr     r1, 1f
+        ldmia   r1, {r2, r3}
+        add     r2, r2, r1
+        ldr     r1, [r2, r3]
+        strb    r0, [r1]
+        mov     r0, #0x03               @ SYS_WRITEC
+   ARM( svc     #0x123456       )
+ THUMB( svc     #0xab           )
+        mov     pc, lr
+        .align  2
+1:      .word   _GLOBAL_OFFSET_TABLE_ - .
+        .word   semi_writec_buf(GOT)
+ENDPROC(putc)
+
+        .bss
+        .global semi_writec_buf
+        .type   semi_writec_buf, %object
+semi_writec_buf:
+        .space  4
+        .size   semi_writec_buf, 4
+
+#endif
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 6179d94dd5c6..3115e313d9f6 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -11,6 +11,7 @@
 #include <asm/mach-types.h>
 
                 .section        ".start", "ax"
+                .arch   armv4
 
 __SA1100_start:
 
diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S
index 089c560e07f1..92b56897ed64 100644
--- a/arch/arm/boot/compressed/head-shark.S
+++ b/arch/arm/boot/compressed/head-shark.S
@@ -18,6 +18,7 @@
         
                 .section        ".start", "ax"
 
+                .arch armv4
                 b       __beginning
         
 __ofw_data:     .long   0                               @ the number of memory blocks
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b516fd..e2d636336b7c 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -46,7 +46,7 @@ __image_start:
 __image_end:
         .long   _got_end
 __load_base:
-        .long   CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
+        .long   MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
 __loaded:
         .long   __continue
         .align
@@ -55,26 +55,9 @@ __tmp_stack:
 __continue:
 #endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
 
-        b       1f
-__atags:@ tag #1
-        .long   12                      @ tag->hdr.size = tag_size(tag_core);
-        .long   0x54410001              @ tag->hdr.tag = ATAG_CORE;
-        .long   0                       @ tag->u.core.flags = 0;
-        .long   0                       @ tag->u.core.pagesize = 0;
-        .long   0                       @ tag->u.core.rootdev = 0;
-        @ tag #2
-        .long   8                       @ tag->hdr.size = tag_size(tag_mem32);
-        .long   0x54410002              @ tag->hdr.tag = ATAG_MEM;
-        .long   CONFIG_MEMORY_SIZE      @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
-        .long   CONFIG_MEMORY_START     @ @ tag->u.mem.start = CONFIG_MEMORY_START;
-        @ tag #3
-        .long   0                       @ tag->hdr.size = 0
-        .long   0                       @ tag->hdr.tag = ATAG_NONE;
-1:
-
         /* Set board ID necessary for boot */
         ldr     r7, 1f                          @ Set machine type register
-        adr     r8, __atags                     @ Set atag register
+        mov     r8, #0                          @ pass null pointer as atag
         b       2f
 
 1 :     .long MACH_TYPE
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3ad761..75189f13cf54 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
+        .arch   armv7-a
 /*
  * Debugging stuff
  *
@@ -141,7 +142,6 @@ start:
                 mov     r7, r1                  @ save architecture ID
                 mov     r8, r2                  @ save atags pointer
 
-#ifndef __ARM_ARCH_2__
                 /*
                  * Booting from Angel - need to enter SVC mode and disable
                  * FIQs/IRQs (numeric definitions from angel arm.h source).
@@ -157,10 +157,6 @@ not_angel:
                 safe_svcmode_maskall r0
                 msr     spsr_cxsf, r9           @ Save the CPU boot mode in
                                                 @ SPSR
-#else
-                teqp    pc, #0x0c000003         @ turn off interrupts
-#endif
-
                 /*
                  * Note that some cache flushing and other stuff may
                  * be needed here - is there an Angel SWI call for this?
@@ -182,7 +178,19 @@ not_angel:
                 ldr     r4, =zreladdr
 #endif
 
-                bl      cache_on
+                /*
+                 * Set up a page table only if it won't overwrite ourself.
+                 * That means r4 < pc && r4 - 16k page directory > &_end.
+                 * Given that r4 > &_end is most unfrequent, we add a rough
+                 * additional 1MB of room for a possible appended DTB.
+                 */
+                mov     r0, pc
+                cmp     r0, r4
+                ldrcc   r0, LC0+32
+                addcc   r0, r0, pc
+                cmpcc   r4, r0
+                orrcc   r4, r4, #1              @ remember we skipped cache_on
+                blcs    cache_on
 
 restart:        adr     r0, LC0
                 ldmia   r0, {r1, r2, r3, r6, r10, r11, r12}
@@ -228,7 +236,7 @@ restart:	adr	r0, LC0
  *   r0  = delta
  *   r2  = BSS start
  *   r3  = BSS end
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
  *   r5  = appended dtb size (still unknown)
  *   r6  = _edata
  *   r7  = architecture ID
@@ -276,6 +284,7 @@ restart:	adr	r0, LC0
                  */
                 cmp     r0, #1
                 sub     r0, r4, #TEXT_OFFSET
+                bic     r0, r0, #1
                 add     r0, r0, #0x100
                 mov     r1, r6
                 sub     r2, sp, r6
@@ -322,12 +331,13 @@ dtb_check_done:
 
 /*
  * Check to see if we will overwrite ourselves.
- *   r4  = final kernel address
+ *   r4  = final kernel address (possibly with LSB set)
  *   r9  = size of decompressed image
  *   r10 = end of this image, including  bss/stack/malloc space if non XIP
  * We basically want:
  *   r4 - 16k page directory >= r10 -> OK
  *   r4 + image length <= address of wont_overwrite -> OK
+ * Note: the possible LSB in r4 is harmless here.
  */
                 add     r10, r10, #16384
                 cmp     r4, r10
@@ -389,7 +399,8 @@ dtb_check_done:
                 add     sp, sp, r6
 #endif
 
-                bl      cache_clean_flush
+                tst     r4, #1
+                bleq    cache_clean_flush
 
                 adr     r0, BSYM(restart)
                 add     r0, r0, r6
@@ -401,7 +412,7 @@ wont_overwrite:
  *   r0  = delta
  *   r2  = BSS start
  *   r3  = BSS end
- *   r4  = kernel execution address
+ *   r4  = kernel execution address (possibly with LSB set)
  *   r5  = appended dtb size (0 if not present)
  *   r7  = architecture ID
  *   r8  = atags pointer
@@ -464,6 +475,15 @@ not_relocated:	mov	r0, #0
                 cmp     r2, r3
                 blo     1b
 
+                /*
+                 * Did we skip the cache setup earlier?
+                 * That is indicated by the LSB in r4.
+                 * Do it now if so.
+                 */
+                tst     r4, #1
+                bic     r4, r4, #1
+                blne    cache_on
+
 /*
  * The C runtime environment should now be setup sufficiently.
  * Set up some pointers, and start decompressing.
@@ -512,6 +532,7 @@ LC0:		.word	LC0			@ r1
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
                 .word   .L_user_stack_end       @ sp
+                .word   _end - restart + 16384 + 1024*1024
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
@@ -805,8 +826,8 @@ call_cache_fn:	adr	r12, proc_types
                 .align  2
                 .type   proc_types,#object
 proc_types:
-                .word   0x00000000              @ old ARM ID
-                .word   0x0000f000
+                .word   0x41000000              @ old ARM ID
+                .word   0xff00f000
                 mov     pc, lr
  THUMB(         nop                             )
                 mov     pc, lr
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f0895c581a89..641b3c9a7028 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -16,11 +16,13 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9263ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9263.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9263.dtb
 # sam9g20
+dtb-$(CONFIG_ARCH_AT91) += at91-foxg20.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += at91sam9g20ek_2mmc.dtb
 dtb-$(CONFIG_ARCH_AT91) += kizbox.dtb
 dtb-$(CONFIG_ARCH_AT91) += tny_a9g20.dtb
 dtb-$(CONFIG_ARCH_AT91) += usb_a9g20.dtb
+dtb-$(CONFIG_ARCH_AT91) += usb_a9g20_lpw.dtb
 # sam9g45
 dtb-$(CONFIG_ARCH_AT91) += at91sam9m10g45ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb
@@ -57,6 +59,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos5440-sd5v1.dtb \
         exynos5250-smdk5250.dtb \
         exynos5250-snow.dtb \
+        exynos5420-smdk5420.dtb \
         exynos5440-ssdk5440.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
         ecx-2000.dtb
@@ -64,6 +67,8 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
         integratorcp.dtb
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
+        kirkwood-db-88f6281.dtb \
+        kirkwood-db-88f6282.dtb \
         kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
         kirkwood-dockstar.dtb \
@@ -84,6 +89,8 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
         kirkwood-ns2max.dtb \
         kirkwood-ns2mini.dtb \
         kirkwood-nsa310.dtb \
+        kirkwood-sheevaplug.dtb \
+        kirkwood-sheevaplug-esata.dtb \
         kirkwood-topkick.dtb \
         kirkwood-ts219-6281.dtb \
         kirkwood-ts219-6282.dtb \
@@ -103,13 +110,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx27-apf27.dtb \
         imx27-apf27dev.dtb \
         imx27-pdk.dtb \
-        imx27-phytec-phycore.dtb \
+        imx27-phytec-phycore-som.dtb \
+        imx27-phytec-phycore-rdk.dtb \
         imx31-bug.dtb \
         imx51-apf51.dtb \
         imx51-apf51dev.dtb \
         imx51-babbage.dtb \
         imx53-ard.dtb \
         imx53-evk.dtb \
+        imx53-m53evk.dtb \
         imx53-mba53.dtb \
         imx53-qsb.dtb \
         imx53-smd.dtb \
@@ -117,10 +126,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
         imx6dl-sabresd.dtb \
         imx6dl-wandboard.dtb \
         imx6q-arm2.dtb \
+        imx6q-phytec-pbab01.dtb \
         imx6q-sabreauto.dtb \
         imx6q-sabrelite.dtb \
         imx6q-sabresd.dtb \
-        imx6q-sbc6x.dtb
+        imx6q-sbc6x.dtb \
+        imx6sl-evk.dtb \
+        vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx23-olinuxino.dtb \
         imx23-stmp378x_devb.dtb \
@@ -130,11 +142,16 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
         imx28-cfa10036.dtb \
         imx28-cfa10037.dtb \
         imx28-cfa10049.dtb \
+        imx28-cfa10055.dtb \
+        imx28-cfa10057.dtb \
         imx28-evk.dtb \
         imx28-m28evk.dtb \
         imx28-sps1.dtb \
         imx28-tx28.dtb
 dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
+dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
+        nspire-tp.dtb \
+        nspire-clp.dtb
 dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
         omap3430-sdp.dtb \
         omap3-beagle.dtb \
@@ -149,19 +166,26 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
         omap4-panda-es.dtb \
         omap4-var-som.dtb \
         omap4-sdp.dtb \
-        omap5-evm.dtb \
+        omap4-sdp-es23plus.dtb \
+        omap5-uevm.dtb \
         am335x-evm.dtb \
         am335x-evmsk.dtb \
-        am335x-bone.dtb
+        am335x-bone.dtb \
+        am3517-evm.dtb \
+        am3517_mt_ventoux.dtb \
+        am43x-epos-evm.dtb
 dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
 dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
         hrefprev60.dtb \
         hrefv60plus.dtb \
+        ccu8540.dtb \
         ccu9540.dtb
+dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a7740-armadillo800eva.dtb \
         r8a7778-bockw.dtb \
+        r8a7740-armadillo800eva-reference.dtb \
         r8a7779-marzen-reference.dtb \
         r8a7790-lager.dtb \
         sh73a0-kzm9g.dtb \
@@ -177,10 +201,15 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
         spear320-evb.dtb \
         spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
+dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
+        stih416-b2000.dtb \
+        stih415-b2020.dtb \
+        stih416-b2020.dtb
 dtb-$(CONFIG_ARCH_SUNXI) += \
         sun4i-a10-cubieboard.dtb \
         sun4i-a10-mini-xplus.dtb \
         sun4i-a10-hackberry.dtb \
+        sun5i-a10s-olinuxino-micro.dtb \
         sun5i-a13-olinuxino.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra20-iris-512.dtb \
@@ -199,6 +228,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
         tegra114-pluto.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
         versatile-pb.dtb
+dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
         vexpress-v2p-ca9.dtb \
         vexpress-v2p-ca15-tc1.dtb \
@@ -207,8 +237,11 @@ dtb-$(CONFIG_ARCH_VIRT) += xenvm-4.2.dtb
 dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
         wm8505-ref.dtb \
         wm8650-mid.dtb \
+        wm8750-apc8750.dtb \
         wm8850-w70v2.dtb
-dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
+        zynq-zc706.dtb \
+        zynq-zed.dtb
 
 targets += dtbs
 targets += $(dtb-y)
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index 29b9f15e7599..54cb5cf8604a 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -9,7 +9,7 @@
 
 /dts-v1/;
 
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 
 / {
         chosen {
@@ -46,7 +46,7 @@
                         };
 
                         usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 15 0>;
+                                atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
                 };
@@ -90,23 +90,23 @@
                 compatible = "gpio-leds";
 
                 red {
-                        gpios = <&pioC 10 0>;
+                        gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "none";
                 };
 
                 green {
-                        gpios = <&pioA 5 1>;
+                        gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                         default-state = "on";
                 };
 
                 yellow {
-                        gpios = <&pioB 20 1>;
+                        gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                 };
 
                 blue {
-                        gpios = <&pioB 21 1>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                 };
         };
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 5302f79c05b7..04feaf8f1420 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x BeagleBone";
@@ -26,24 +26,104 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0>;
+                pinctrl-0 = <&clkout2_pin>;
 
                 user_leds_s0: user_leds_s0 {
                         pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-                                0x58 0x17       /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
-                                0x5c 0x7        /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
-                                0x60 0x17       /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                                0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a6.gpio1_22 */
+                                0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a7.gpio1_23 */
+                                0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_a8.gpio1_24 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxerr.mii1_rxerr */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+                                0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxdv.mii1_rxdv */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+                                0x12c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_txclk.mii1_txclk */
+                                0x130 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxclk.mii1_rxclk */
+                                0x134 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd3.mii1_rxd3 */
+                                0x138 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd2.mii1_rxd2 */
+                                0x13c (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd1.mii1_rxd1 */
+                                0x140 (PIN_INPUT_PULLUP | MUX_MODE0)    /* mii1_rxd0.mii1_rxd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -55,31 +135,34 @@
         };
 
         leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+
                 compatible = "gpio-leds";
 
                 led@2 {
                         label = "beaglebone:green:heartbeat";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                         default-state = "off";
                 };
 
                 led@3 {
                         label = "beaglebone:green:mmc0";
-                        gpios = <&gpio1 22 0>;
+                        gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                         default-state = "off";
                 };
 
                 led@4 {
                         label = "beaglebone:green:usr2";
-                        gpios = <&gpio1 23 0>;
+                        gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@5 {
                         label = "beaglebone:green:usr3";
-                        gpios = <&gpio1 24 0>;
+                        gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
         };
@@ -136,3 +219,16 @@
 &cpsw_emac1 {
         phy_id = <&davinci_mdio>, <1>;
 };
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 0423298a26fe..a16bb9691cc6 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x EVM";
@@ -26,32 +26,143 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+                pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 
                 matrix_keypad_s0: matrix_keypad_s0 {
                         pinctrl-single,pins = <
-                                0x54 0x7        /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
-                                0x58 0x7        /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
-                                0x64 0x27       /* gpmc_a9.gpio1_25, INPUT | MODE7 */
-                                0x68 0x27       /* gpmc_a10.gpio1_26, INPUT | MODE7 */
-                                0x6c 0x27       /* gpmc_a11.gpio1_27, INPUT | MODE7 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio1_21 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a6.gpio1_22 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a9.gpio1_25 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a10.gpio1_26 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_a11.gpio1_27 */
                         >;
                 };
 
                 volume_keys_s0: volume_keys_s0 {
                         pinctrl-single,pins = <
-                                0x150 0x27      /* spi0_sclk.gpio0_2, INPUT | MODE7 */
-                                0x154 0x27      /* spi0_d0.gpio0_3, INPUT | MODE7 */
+                                0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_sclk.gpio0_2 */
+                                0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)  /* spi0_d0.gpio0_3 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                i2c1_pins: pinmux_i2c1_pins {
+                        pinctrl-single,pins = <
+                                0x158 (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_d1.i2c1_sda */
+                                0x15c (PIN_INPUT_PULLUP | MUX_MODE2)    /* spi0_cs0.i2c1_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                nandflash_pins_s0: nandflash_pins_s0 {
+                        pinctrl-single,pins = <
+                                0x0 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad0.gpmc_ad0 */
+                                0x4 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad1.gpmc_ad1 */
+                                0x8 (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad2.gpmc_ad2 */
+                                0xc (PIN_INPUT_PULLUP | MUX_MODE0)      /* gpmc_ad3.gpmc_ad3 */
+                                0x10 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
+                                0x14 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
+                                0x18 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
+                                0x1c (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
+                                0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                                0x74 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_wpn.gpio0_30 */
+                                0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                                0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                                0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                                0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                                0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                        >;
+                };
+
+                ecap0_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x164 0x0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -61,6 +172,9 @@
                 };
 
                 i2c1: i2c@4802a000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins>;
+
                         status = "okay";
                         clock-frequency = <100000>;
 
@@ -102,6 +216,101 @@
                                 reg = <0x48>;
                         };
                 };
+
+                elm: elm@48080000 {
+                        status = "okay";
+                };
+
+                epwmss0: epwmss@48300000 {
+                        status = "okay";
+
+                        ecap0: ecap@48300100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap0_pins>;
+                        };
+                };
+
+                gpmc: gpmc@50000000 {
+                        status = "okay";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&nandflash_pins_s0>;
+                        ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
+                        nand@0,0 {
+                                reg = <0 0 0>; /* CS0, offset 0 */
+                                nand-bus-width = <8>;
+                                ti,nand-ecc-opt = "bch8";
+                                gpmc,device-nand = "true";
+                                gpmc,device-width = <1>;
+                                gpmc,sync-clk-ps = <0>;
+                                gpmc,cs-on-ns = <0>;
+                                gpmc,cs-rd-off-ns = <44>;
+                                gpmc,cs-wr-off-ns = <44>;
+                                gpmc,adv-on-ns = <6>;
+                                gpmc,adv-rd-off-ns = <34>;
+                                gpmc,adv-wr-off-ns = <44>;
+                                gpmc,we-on-ns = <0>;
+                                gpmc,we-off-ns = <40>;
+                                gpmc,oe-on-ns = <0>;
+                                gpmc,oe-off-ns = <54>;
+                                gpmc,access-ns = <64>;
+                                gpmc,rd-cycle-ns = <82>;
+                                gpmc,wr-cycle-ns = <82>;
+                                gpmc,wait-on-read = "true";
+                                gpmc,wait-on-write = "true";
+                                gpmc,bus-turnaround-ns = <0>;
+                                gpmc,cycle2cycle-delay-ns = <0>;
+                                gpmc,clk-activation-ns = <0>;
+                                gpmc,wait-monitoring-ns = <0>;
+                                gpmc,wr-access-ns = <40>;
+                                gpmc,wr-data-mux-bus-ns = <0>;
+
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                elm_id = <&elm>;
+
+                                /* MTD partition table */
+                                partition@0 {
+                                        label = "SPL1";
+                                        reg = <0x00000000 0x000020000>;
+                                };
+
+                                partition@1 {
+                                        label = "SPL2";
+                                        reg = <0x00020000 0x00020000>;
+                                };
+
+                                partition@2 {
+                                        label = "SPL3";
+                                        reg = <0x00040000 0x00020000>;
+                                };
+
+                                partition@3 {
+                                        label = "SPL4";
+                                        reg = <0x00060000 0x00020000>;
+                                };
+
+                                partition@4 {
+                                        label = "U-boot";
+                                        reg = <0x00080000 0x001e0000>;
+                                };
+
+                                partition@5 {
+                                        label = "environment";
+                                        reg = <0x00260000 0x00020000>;
+                                };
+
+                                partition@6 {
+                                        label = "Kernel";
+                                        reg = <0x00280000 0x00500000>;
+                                };
+
+                                partition@7 {
+                                        label = "File-System";
+                                        reg = <0x00780000 0x0F880000>;
+                                };
+                        };
+                };
         };
 
         vbat: fixedregulator@0 {
@@ -123,12 +332,12 @@
                 debounce-delay-ms = <5>;
                 col-scan-delay-us = <2>;
 
-                row-gpios = <&gpio1 25 0        /* Bank1, pin25 */
-                             &gpio1 26 0        /* Bank1, pin26 */
-                             &gpio1 27 0>;      /* Bank1, pin27 */
+                row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
+                             &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
+                             &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
 
-                col-gpios = <&gpio1 21 0        /* Bank1, pin21 */
-                             &gpio1 22 0>;      /* Bank1, pin22 */
+                col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
+                             &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
 
                 linux,keymap = <0x0000008b      /* MENU */
                                 0x0100009e      /* BACK */
@@ -147,20 +356,27 @@
                 switch@9 {
                         label = "volume-up";
                         linux,code = <115>;
-                        gpios = <&gpio0 2 1>;
+                        gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
                         gpio-key,wakeup;
                 };
 
                 switch@10 {
                         label = "volume-down";
                         linux,code = <114>;
-                        gpios = <&gpio0 3 1>;
+                        gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
                         gpio-key,wakeup;
                 };
         };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap0 0 50000 0>;
+                brightness-levels = <0 51 53 56 62 75 101 152 255>;
+                default-brightness-level = <8>;
+        };
 };
 
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 
 &tps {
         vcc1-supply = <&vbat>;
@@ -237,6 +453,18 @@
         };
 };
 
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
+
 &cpsw_emac0 {
         phy_id = <&davinci_mdio>, <0>;
 };
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index f67c360844f4..9e00eef9b74b 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-/include/ "am33xx.dtsi"
+#include "am33xx.dtsi"
 
 / {
         model = "TI AM335x EVM-SK";
@@ -32,33 +32,145 @@
 
         am33xx_pinmux: pinmux@44e10800 {
                 pinctrl-names = "default";
-                pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
+                pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
 
                 user_leds_s0: user_leds_s0 {
                         pinctrl-single,pins = <
-                                0x10 0x7        /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
-                                0x14 0x7        /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
-                                0x18 0x7        /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
-                                0x1c 0x7        /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
+                                0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad4.gpio1_4 */
+                                0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad5.gpio1_5 */
+                                0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad6.gpio1_6 */
+                                0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_ad7.gpio1_7 */
                         >;
                 };
 
                 gpio_keys_s0: gpio_keys_s0 {
                         pinctrl-single,pins = <
-                                0x94 0x27       /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
-                                0x90 0x27       /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
-                                0x70 0x27       /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
-                                0x9c 0x27       /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
+                                0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_oen_ren.gpio2_3 */
+                                0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_advn_ale.gpio2_2 */
+                                0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_wait0.gpio0_30 */
+                                0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)   /* gpmc_ben0_cle.gpio2_5 */
+                        >;
+                };
+
+                i2c0_pins: pinmux_i2c0_pins {
+                        pinctrl-single,pins = <
+                                0x188 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
+                                0x18c (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
+                        >;
+                };
+
+                uart0_pins: pinmux_uart0_pins {
+                        pinctrl-single,pins = <
+                                0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
+                                0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)         /* uart0_txd.uart0_txd */
+                        >;
+                };
+
+                clkout2_pin: pinmux_clkout2_pin {
+                        pinctrl-single,pins = <
+                                0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)         /* xdma_event_intr1.clkout2 */
+                        >;
+                };
+
+                ecap2_pins: backlight_pins {
+                        pinctrl-single,pins = <
+                                0x19c 0x4       /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
+                        >;
+                };
+
+                cpsw_default: cpsw_default {
+                        pinctrl-single,pins = <
+                                /* Slave 1 */
+                                0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rctl */
+                                0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
+                                0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
+                                0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
+                                0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
+                                0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rgmii1_rclk */
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd3.rgmii1_rd3 */
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd2.rgmii1_rd2 */
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rd1 */
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rd0 */
+
+                                /* Slave 2 */
+                                0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a0.rgmii2_tctl */
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a1.rgmii2_rctl */
+                                0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a2.rgmii2_td3 */
+                                0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a3.rgmii2_td2 */
+                                0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a4.rgmii2_td1 */
+                                0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a5.rgmii2_td0 */
+                                0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)  /* gpmc_a6.rgmii2_tclk */
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a7.rgmii2_rclk */
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a8.rgmii2_rd3 */
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a9.rgmii2_rd2 */
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a10.rgmii2_rd1 */
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2)   /* gpmc_a11.rgmii2_rd0 */
+                        >;
+                };
+
+                cpsw_sleep: cpsw_sleep {
+                        pinctrl-single,pins = <
+                                /* Slave 1 reset value */
+                                0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+
+                                /* Slave 2 reset value*/
+                                0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        >;
+                };
+
+                davinci_mdio_default: davinci_mdio_default {
+                        pinctrl-single,pins = <
+                                /* MDIO */
+                                0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                                0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                        >;
+                };
+
+                davinci_mdio_sleep: davinci_mdio_sleep {
+                        pinctrl-single,pins = <
+                                /* MDIO reset value */
+                                0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                                0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
                         >;
                 };
         };
 
         ocp {
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins>;
+
                         status = "okay";
                 };
 
                 i2c0: i2c@44e0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins>;
+
                         status = "okay";
                         clock-frequency = <400000>;
 
@@ -94,6 +206,16 @@
                                 st,max-limit-z = <750>;
                         };
                 };
+
+                epwmss2: epwmss@48304000 {
+                        status = "okay";
+
+                        ecap2: ecap@48304100 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ecap2_pins>;
+                        };
+                };
         };
 
         vbat: fixedregulator@0 {
@@ -111,30 +233,33 @@
         };
 
         leds {
+                pinctrl-names = "default";
+                pinctrl-0 = <&user_leds_s0>;
+
                 compatible = "gpio-leds";
 
                 led@1 {
                         label = "evmsk:green:usr0";
-                        gpios = <&gpio1 4 0>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@2 {
                         label = "evmsk:green:usr1";
-                        gpios = <&gpio1 5 0>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
                         default-state = "off";
                 };
 
                 led@3 {
                         label = "evmsk:green:mmc0";
-                        gpios = <&gpio1 6 0>;
+                        gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                         default-state = "off";
                 };
 
                 led@4 {
                         label = "evmsk:green:heartbeat";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                         default-state = "off";
                 };
@@ -148,31 +273,38 @@
                 switch@1 {
                         label = "button0";
                         linux,code = <0x100>;
-                        gpios = <&gpio2 3 0>;
+                        gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
                 };
 
                 switch@2 {
                         label = "button1";
                         linux,code = <0x101>;
-                        gpios = <&gpio2 2 0>;
+                        gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
                 };
 
                 switch@3 {
                         label = "button2";
                         linux,code = <0x102>;
-                        gpios = <&gpio0 30 0>;
+                        gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
                         gpio-key,wakeup;
                 };
 
                 switch@4 {
                         label = "button3";
                         linux,code = <0x103>;
-                        gpios = <&gpio2 5 0>;
+                        gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
                 };
         };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&ecap2 0 50000 1>;
+                brightness-levels = <0 58 61 66 75 90 125 170 255>;
+                default-brightness-level = <8>;
+        };
 };
 
-/include/ "tps65910.dtsi"
+#include "tps65910.dtsi"
 
 &tps {
         vcc1-supply = <&vbat>;
@@ -248,3 +380,15 @@
                 };
         };
 };
+
+&mac {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+};
+
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b88adf..0d4df90477f7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -8,26 +8,33 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,am33xx";
         interrupt-parent = <&intc>;
 
         aliases {
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
-                serial5 = &uart6;
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
                 d_can0 = &dcan0;
                 d_can1 = &dcan1;
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0>;
 
                         /*
                          * To consider voltage drop between PMIC and SoC,
@@ -133,7 +140,7 @@
                         interrupts = <62>;
                 };
 
-                uart1: serial@44e09000 {
+                uart0: serial@44e09000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
@@ -142,7 +149,7 @@
                         status = "disabled";
                 };
 
-                uart2: serial@48022000 {
+                uart1: serial@48022000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
@@ -151,7 +158,7 @@
                         status = "disabled";
                 };
 
-                uart3: serial@48024000 {
+                uart2: serial@48024000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
@@ -160,7 +167,7 @@
                         status = "disabled";
                 };
 
-                uart4: serial@481a6000 {
+                uart3: serial@481a6000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
@@ -169,7 +176,7 @@
                         status = "disabled";
                 };
 
-                uart5: serial@481a8000 {
+                uart4: serial@481a8000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
@@ -178,7 +185,7 @@
                         status = "disabled";
                 };
 
-                uart6: serial@481aa000 {
+                uart5: serial@481aa000 {
                         compatible = "ti,omap3-uart";
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
@@ -343,6 +350,90 @@
                         ti,hwmods = "usb_otg_hs";
                 };
 
+                epwmss0: epwmss@48300000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48300000 0x10>;
+                        ti,hwmods = "epwmss0";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                                  0x48300180 0x48300180 0x80   /* EQEP */
+                                  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+                        ecap0: ecap@48300100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48300100 0x80>;
+                                ti,hwmods = "ecap0";
+                                status = "disabled";
+                        };
+
+                        ehrpwm0: ehrpwm@48300200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48300200 0x80>;
+                                ti,hwmods = "ehrpwm0";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss1: epwmss@48302000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48302000 0x10>;
+                        ti,hwmods = "epwmss1";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48302100 0x48302100 0x80   /* ECAP */
+                                  0x48302180 0x48302180 0x80   /* EQEP */
+                                  0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+                        ecap1: ecap@48302100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48302100 0x80>;
+                                ti,hwmods = "ecap1";
+                                status = "disabled";
+                        };
+
+                        ehrpwm1: ehrpwm@48302200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48302200 0x80>;
+                                ti,hwmods = "ehrpwm1";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss2: epwmss@48304000 {
+                        compatible = "ti,am33xx-pwmss";
+                        reg = <0x48304000 0x10>;
+                        ti,hwmods = "epwmss2";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges = <0x48304100 0x48304100 0x80   /* ECAP */
+                                  0x48304180 0x48304180 0x80   /* EQEP */
+                                  0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+                        ecap2: ecap@48304100 {
+                                compatible = "ti,am33xx-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48304100 0x80>;
+                                ti,hwmods = "ecap2";
+                                status = "disabled";
+                        };
+
+                        ehrpwm2: ehrpwm@48304200 {
+                                compatible = "ti,am33xx-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48304200 0x80>;
+                                ti,hwmods = "ehrpwm2";
+                                status = "disabled";
+                        };
+                };
+
                 mac: ethernet@4a100000 {
                         compatible = "ti,cpsw";
                         ti,hwmods = "cpgmac0";
@@ -394,7 +485,6 @@
                         compatible = "ti,am3352-ocmcram";
                         reg = <0x40300000 0x10000>;
                         ti,hwmods = "ocmcram";
-                        ti,no_idle_on_suspend;
                 };
 
                 wkup_m3: wkup_m3@44d00000 {
@@ -404,13 +494,21 @@
                         ti,hwmods = "wkup_m3";
                 };
 
+                elm: elm@48080000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48080000 0x2000>;
+                        interrupts = <4>;
+                        ti,hwmods = "elm";
+                        status = "disabled";
+                };
+
                 gpmc: gpmc@50000000 {
                         compatible = "ti,am3352-gpmc";
                         ti,hwmods = "gpmc";
                         reg = <0x50000000 0x2000>;
                         interrupts = <100>;
-                        num-cs = <7>;
-                        num-waitpins = <2>;
+                        gpmc,num-cs = <7>;
+                        gpmc,num-waitpins = <2>;
                         #address-cells = <2>;
                         #size-cells = <1>;
                         status = "disabled";
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
index e9b5bdae4908..e99dfaf70052 100644
--- a/arch/arm/boot/dts/am3517-evm.dts
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI AM3517 EVM (AM3517/05)";
diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts
index 556868388a23..fdf5ce63c8e6 100644
--- a/arch/arm/boot/dts/am3517_mt_ventoux.dts
+++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TeeJet Mt.Ventoux";
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
new file mode 100644
index 000000000000..ddc1df77ac52
--- /dev/null
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Source for AM4372 SoC
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "ti,am4372", "ti,am43";
+        interrupt-parent = <&gic>;
+
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+
+        gic: interrupt-controller@48241000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = <0x48241000 0x1000>,
+                      <0x48240100 0x0100>;
+        };
+
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                uart0: serial@44e09000 {
+                        compatible = "ti,am4372-uart","ti,omap2-uart";
+                        reg = <0x44e09000 0x2000>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                timer1: timer@44e31000 {
+                        compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
+                        reg = <0x44e31000 0x400>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,timer-alwon;
+                };
+
+                timer2: timer@48040000  {
+                        compatible = "ti,am4372-timer","ti,am335x-timer";
+                        reg = <0x48040000  0x400>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                counter32k: counter@44e86000 {
+                        compatible = "ti,am4372-counter32k","ti,omap-counter32k";
+                        reg = <0x44e86000 0x40>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
new file mode 100644
index 000000000000..74174d48f476
--- /dev/null
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* AM43x EPOS EVM */
+
+/dts-v1/;
+
+#include "am4372.dtsi"
+
+/ {
+        model = "TI AM43x EPOS EVM";
+        compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
+};
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 5160210f74da..3a1de9eb5111 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -7,7 +7,7 @@
  */
 
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
         model = "Somfy Animeo IP";
@@ -123,7 +123,7 @@
 
                 usb0: ohci@00500000 {
                         num-ports = <2>;
-                        atmel,vbus-gpio = <&pioB 15 1>;
+                        atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
                         status = "okay";
                 };
         };
@@ -133,23 +133,23 @@
 
                 power_green {
                         label = "power_green";
-                        gpios = <&pioC 17 0>;
+                        gpios = <&pioC 17 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 power_red {
                         label = "power_red";
-                        gpios = <&pioA 2 0>;
+                        gpios = <&pioA 2 GPIO_ACTIVE_HIGH>;
                 };
 
                 tx_green {
                         label = "tx_green";
-                        gpios = <&pioC 19 0>;
+                        gpios = <&pioC 19 GPIO_ACTIVE_HIGH>;
                 };
 
                 tx_red {
                         label = "tx_red";
-                        gpios = <&pioC 18 0>;
+                        gpios = <&pioC 18 GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -160,21 +160,21 @@
 
                 keyswitch_in {
                         label = "keyswitch_in";
-                        gpios = <&pioB 1 0>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_HIGH>;
                         linux,code = <28>;
                         gpio-key,wakeup;
                 };
 
                 error_in {
                         label = "error_in";
-                        gpios = <&pioB 2 0>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_HIGH>;
                         linux,code = <29>;
                         gpio-key,wakeup;
                 };
 
                 btn {
                         label = "btn";
-                        gpios = <&pioC 23 0>;
+                        gpios = <&pioC 23 GPIO_ACTIVE_HIGH>;
                         linux,code = <31>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 2353b1f13704..beee1699d49e 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -74,6 +74,7 @@
                                  */
                                 status = "disabled";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 14e36e19d515..45b107763e3b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -99,6 +99,7 @@
                                  * No CD or WP GPIOs: SDIO interface used for
                                  * Wifi/Bluetooth chip
                                  */
+                                 broken-cd;
                         };
 
                         usb@50000 {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 130f8390a7e4..a3a2fedb8726 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -64,6 +64,7 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
@@ -84,6 +85,22 @@
                                         gpios = <&gpio0 6 1>;
                                 };
                         };
+
+                        pcie-controller {
+                                status = "okay";
+
+                                /* Internal mini-PCIe connector */
+                                pcie@1,0 {
+                                        /* Port 0, Lane 0 */
+                                        status = "okay";
+                                };
+
+                                /* Internal mini-PCIe connector */
+                                pcie@2,0 {
+                                        /* Port 1, Lane 0 */
+                                        status = "okay";
+                                };
+                        };
                 };
         };
  };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 550eb772c30e..90b117624abb 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -22,9 +22,18 @@
         model = "Marvell Armada 370 and XP SoC";
         compatible = "marvell,armada-370-xp";
 
+        aliases {
+                eth0 = &eth0;
+                eth1 = &eth1;
+        };
+
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "marvell,sheeva-v7";
+                        device_type = "cpu";
+                        reg = <0>;
                 };
         };
 
@@ -80,7 +89,7 @@
 
                         sata@a0000 {
                                 compatible = "marvell,orion-sata";
-                                reg = <0xa0000 0x2400>;
+                                reg = <0xa0000 0x5000>;
                                 interrupts = <55>;
                                 clocks = <&gateclk 15>, <&gateclk 30>;
                                 clock-names = "0", "1";
@@ -94,17 +103,17 @@
                                 reg = <0x72004 0x4>;
                         };
 
-                        ethernet@70000 {
+                        eth0: ethernet@70000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x70000 0x2500>;
+                                reg = <0x70000 0x4000>;
                                 interrupts = <8>;
                                 clocks = <&gateclk 4>;
                                 status = "disabled";
                         };
 
-                        ethernet@74000 {
+                        eth1: ethernet@74000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x74000 0x2500>;
+                                reg = <0x74000 0x4000>;
                                 interrupts = <10>;
                                 clocks = <&gateclk 3>;
                                 status = "disabled";
@@ -143,6 +152,10 @@
                                 reg = <0xd4000 0x200>;
                                 interrupts = <54>;
                                 clocks = <&gateclk 17>;
+                                bus-width = <4>;
+                                cap-sdio-irq;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index aee2b1866ce2..fa3dfc6b4c6a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -180,10 +180,6 @@
 
                                 bus-range = <0x00 0xff>;
 
-                                reg = <0x40000 0x2000>, <0x80000 0x2000>;
-
-                                reg-names = "pcie0.0", "pcie1.0";
-
                                 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000   /* Port 0.0 registers */
                                         0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
                                         0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index d6cc8bf8272e..e28e68ff864d 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -30,6 +30,10 @@
         };
 
         soc {
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
+
                 internal-regs {
                         serial@12000 {
                                 clock-frequency = <250000000>;
@@ -97,6 +101,7 @@
                                 pinctrl-names = "default";
                                 status = "okay";
                                 /* No CD or WP GPIOs */
+                                broken-cd;
                         };
 
                         usb@50000 {
@@ -155,6 +160,35 @@
                                         status = "okay";
                                 };
                         };
+
+                        devbus-bootcs@10400 {
+                                status = "okay";
+                                ranges = <0 0xf0000000 0x1000000>;
+
+                                /* Device Bus parameters are required */
+
+                                /* Read parameters */
+                                devbus,bus-width    = <8>;
+                                devbus,turn-off-ps  = <60000>;
+                                devbus,badr-skew-ps = <0>;
+                                devbus,acc-first-ps = <124000>;
+                                devbus,acc-next-ps  = <248000>;
+                                devbus,rd-setup-ps  = <0>;
+                                devbus,rd-hold-ps   = <0>;
+
+                                /* Write parameters */
+                                devbus,sync-enable = <0>;
+                                devbus,wr-high-ps  = <60000>;
+                                devbus,wr-low-ps   = <60000>;
+                                devbus,ale-wr-ps   = <60000>;
+
+                                /* NOR 16 MiB */
+                                nor@0 {
+                                        compatible = "cfi-flash";
+                                        reg = <0 0x1000000>;
+                                        bank-width = <2>;
+                                };
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 3ee63d128e27..c87b2de29c30 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,8 +39,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x1000000>;
+                ranges = <0          0 0xd0000000 0x100000  /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
+                          0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB  */>;
 
                 internal-regs {
                         serial@12000 {
@@ -104,6 +105,16 @@
                                 phy-mode = "rgmii-id";
                         };
 
+                        /* Front-side USB slot */
+                        usb@50000 {
+                                status = "okay";
+                        };
+
+                        /* Back-side USB slot */
+                        usb@51000 {
+                                status = "okay";
+                        };
+
                         spi0: spi@10600 {
                                 status = "okay";
 
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f4029f015aff..2d9335da210c 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -92,7 +92,7 @@
 
                         ethernet@34000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x34000 0x2500>;
+                                reg = <0x34000 0x4000>;
                                 interrupts = <14>;
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6ab56bd35de9..c7b1f4d5c1c7 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -23,6 +23,7 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
+                eth3 = &eth3;
         };
 
 
@@ -105,9 +106,9 @@
                                 interrupts = <91>;
                         };
 
-                        ethernet@34000 {
+                        eth3: ethernet@34000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x34000 0x2500>;
+                                reg = <0x34000 0x4000>;
                                 interrupts = <14>;
                                 clocks = <&gateclk 1>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 46b785064dd8..8f510458ea86 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,8 +27,9 @@
         };
 
         soc {
-                ranges = <0          0 0xd0000000 0x100000
-                          0xf0000000 0 0xf0000000 0x8000000>;
+                ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
+                          0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
+                          0xf0000000 0 0xf0000000 0x8000000     /* Device Bus, NOR 128MiB   */>;
 
                 internal-regs {
                         serial@12000 {
@@ -137,13 +138,22 @@
                                 nr-ports = <2>;
                                 status = "okay";
                         };
+
+                        /* Front side USB 0 */
                         usb@50000 {
                                 status = "okay";
                         };
+
+                        /* Front side USB 1 */
                         usb@51000 {
                                 status = "okay";
                         };
 
+                        /* USB interface in the mini-PCIe connector */
+                        usb@52000 {
+                                status = "okay";
+                        };
+
                         devbus-bootcs@10400 {
                                 status = "okay";
                                 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 5b902f9a3af2..416eb9481844 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -22,6 +22,10 @@
         model = "Marvell Armada XP family SoC";
         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
 
+        aliases {
+                eth2 = &eth2;
+        };
+
         soc {
                 internal-regs {
                         L2: l2-cache {
@@ -86,9 +90,9 @@
                                 reg = <0x18200 0x500>;
                         };
 
-                        ethernet@30000 {
+                        eth2: ethernet@30000 {
                                 compatible = "marvell,armada-370-neta";
-                                reg = <0x30000 0x2500>;
+                                reg = <0x30000 0x4000>;
                                 interrupts = <12>;
                                 clocks = <&gateclk 2>;
                                 status = "disabled";
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index c7aebba4e8e7..cce45f5177f9 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
+#include "at91sam9g25.dtsi"
 
 / {
         model = "Acme Systems Aria G25";
@@ -21,6 +21,7 @@
                 serial3 = &usart2;
                 serial4 = &usart3;
                 serial5 = &uart0;
+                serial6 = &uart1;
         };
 
         chosen {
@@ -112,13 +113,17 @@
                                 status = "okay";
                         };
 
+                        /*
+                         * UART0/1 pins are marked as GPIO on
+                         * Aria documentation.
+                         * Change to "okay" if you need additional serial ports
+                         */
                         uart0: serial@f8040000 {
-                                compatible = "atmel,at91sam9260-usart";
-                                reg = <0xf8040000 0x200>;
-                                interrupts = <15 4 5>;
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pinctrl_uart0>;
-                                status = "okay";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@f8044000 {
+                                status = "disabled";
                         };
 
                         adc0: adc@f804c000 {
@@ -138,6 +143,10 @@
                                         };
                                 };
                         };
+
+                        rtc@fffffeb0 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00600000 {
@@ -156,7 +165,7 @@
                 /* little green LED in middle of Aria G25 module */
                 aria_led {
                         label = "aria_led";
-                        gpios = <&pioB 8 0>; /* PB8 */
+                        gpios = <&pioB 8 GPIO_ACTIVE_HIGH>; /* PB8 */
                         linux,default-trigger = "heartbeat";
                 };
 
@@ -164,7 +173,7 @@
 
         onewire@0 {
                 compatible = "w1-gpio";
-                gpios = <&pioA 21 1>;
+                gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_w1_0>;
         };
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
new file mode 100644
index 000000000000..cbe967343997
--- /dev/null
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -0,0 +1,157 @@
+/*
+ * at91-foxg20.dts - Device Tree file for Acme Systems FoxG20 board
+ *
+ * Based on DT files for at91sam9g20ek evaluation board (AT91SAM9G20 SoC)
+ *
+ * Copyright (C) 2013 Douglas Gilbert <dgilbert@interlog.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "at91sam9g20.dtsi"
+
+/ {
+        model = "Acme Systems FoxG20";
+        compatible = "acme,foxg20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 6 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                };
+                        };
+
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                        >;
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                        };
+
+                        uart0: serial@fffd4000 {
+                                status = "okay";
+                        };
+
+                        uart1: serial@fffd8000 {
+                                status = "okay";
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                board {
+                                        pinctrl_pck0_as_mck: pck0_as_mck {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* CD pin */
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0: i2c0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* TWD (SDA), open drain */
+                                                         AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* TWCK (SCL), open drain */
+                                        };
+                                };
+                        };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c0>;
+                i2c-gpio,delay-us = <5>;        /* ~85 kHz */
+                status = "okay";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                /* red LED marked "PC7" near mini USB (device) receptacle */
+                user_led {
+                        label = "user_led";
+                        gpios = <&pioC 7 GPIO_ACTIVE_HIGH>;     /* PC7 */
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                btn {
+                        label = "Button";
+                        gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 5d3ed5aafc69..92b9e21389db 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -10,7 +10,10 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91RM9200 family SoC";
@@ -35,8 +38,12 @@
                 ssc2 = &ssc2;
         };
         cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
                         compatible = "arm,arm920t";
+                        device_type = "cpu";
                 };
         };
 
@@ -77,25 +84,29 @@
                         st: timer@fffffd00 {
                                 compatible = "atmel,at91rm9200-st";
                                 reg = <0xfffffd00 0x100>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
                         tcb0: timer@fffa0000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 0 18 4 0 19 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                              18 IRQ_TYPE_LEVEL_HIGH 0
+                                              19 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         tcb1: timer@fffa4000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffa4000 0x100>;
-                                interrupts = <20 4 0 21 4 0 22 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
+                                              21 IRQ_TYPE_LEVEL_HIGH 0
+                                              22 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         i2c0: i2c@fffb8000 {
                                 compatible = "atmel,at91rm9200-i2c";
                                 reg = <0xfffb8000 0x4000>;
-                                interrupts = <12 4 6>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_twi>;
                                 #address-cells = <1>;
@@ -106,7 +117,7 @@
                         mmc0: mmc@fffb4000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffb4000 0x4000>;
-                                interrupts = <10 4 0>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -115,7 +126,7 @@
                         ssc0: ssc@fffd0000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfffd0000 0x4000>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disable";
@@ -124,7 +135,7 @@
                         ssc1: ssc@fffd4000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfffd4000 0x4000>;
-                                interrupts = <15 4 5>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                 status = "disable";
@@ -133,7 +144,7 @@
                         ssc2: ssc@fffd8000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfffd8000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
                                 status = "disable";
@@ -142,7 +153,7 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at91rm9200-emac", "cdns,emac";
                                 reg = <0xfffbc000 0x4000>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                 phy-mode = "rmii";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb_rmii>;
@@ -167,234 +178,319 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A */
-                                                         0 31 0x1 0x1>; /* PA31 periph with pullup */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA31 periph with pullup */
                                         };
                                 };
 
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
-                                                         0 18 0x1 0x0>; /* PA18 periph A */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */
                                         };
 
                                         pinctrl_uart0_rts: uart0_rts-0 {
                                                 atmel,pins =
-                                                        <0 20 0x1 0x0>; /* PA20 periph A */
+                                                        <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */
                                         };
 
                                         pinctrl_uart0_cts: uart0_cts-0 {
                                                 atmel,pins =
-                                                        <0 21 0x1 0x0>; /* PA21 periph A */
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <1 20 0x1 0x1   /* PB20 periph A with pullup */
-                                                         1 21 0x1 0x0>; /* PB21 periph A */
+                                                        <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB20 periph A with pullup */
+                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
                                         };
 
                                         pinctrl_uart1_rts: uart1_rts-0 {
                                                 atmel,pins =
-                                                        <1 24 0x1 0x0>; /* PB24 periph A */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */
                                         };
 
                                         pinctrl_uart1_cts: uart1_cts-0 {
                                                 atmel,pins =
-                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                         };
 
                                         pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 {
                                                 atmel,pins =
-                                                        <1 19 0x1 0x0   /* PB19 periph A */
-                                                         1 25 0x1 0x0>; /* PB25 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB19 periph A */
+                                                         AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                         };
 
                                         pinctrl_uart1_dcd: uart1_dcd-0 {
                                                 atmel,pins =
-                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                                        <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                         };
 
                                         pinctrl_uart1_ri: uart1_ri-0 {
                                                 atmel,pins =
-                                                        <1 18 0x1 0x0>; /* PB18 periph A */
+                                                        <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                         };
                                 };
 
                                 uart2 {
                                         pinctrl_uart2: uart2-0 {
                                                 atmel,pins =
-                                                        <0 22 0x1 0x0   /* PA22 periph A */
-                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                                        <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA22 periph A */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
                                         };
 
                                         pinctrl_uart2_rts: uart2_rts-0 {
                                                 atmel,pins =
-                                                        <0 30 0x2 0x0>; /* PA30 periph B */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                         };
 
                                         pinctrl_uart2_cts: uart2_cts-0 {
                                                 atmel,pins =
-                                                        <0 31 0x2 0x0>; /* PA31 periph B */
+                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */
                                         };
                                 };
 
                                 uart3 {
                                         pinctrl_uart3: uart3-0 {
                                                 atmel,pins =
-                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
-                                                         0 6 0x2 0x0>;  /* PA6 periph B */
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
+                                                         AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA6 periph B */
                                         };
 
                                         pinctrl_uart3_rts: uart3_rts-0 {
                                                 atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                         };
 
                                         pinctrl_uart3_cts: uart3_cts-0 {
                                                 atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <2 2 0x0 0x1    /* PC2 gpio RDY pin pull_up */
-                                                         1 1 0x0 0x1>;  /* PB1 gpio CD pin pull_up */
+                                                        <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC2 gpio RDY pin pull_up */
+                                                         AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* PB1 gpio CD pin pull_up */
                                         };
                                 };
 
                                 macb {
                                         pinctrl_macb_rmii: macb_rmii-0 {
                                                 atmel,pins =
-                                                        <0 7 0x1 0x0    /* PA7 periph A */
-                                                         0 8 0x1 0x0    /* PA8 periph A */
-                                                         0 9 0x1 0x0    /* PA9 periph A */
-                                                         0 10 0x1 0x0   /* PA10 periph A */
-                                                         0 11 0x1 0x0   /* PA11 periph A */
-                                                         0 12 0x1 0x0   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
-                                                         0 16 0x1 0x0>; /* PA16 periph A */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */
                                         };
 
                                         pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                 atmel,pins =
-                                                        <1 12 0x2 0x0   /* PB12 periph B */
-                                                         1 13 0x2 0x0   /* PB13 periph B */
-                                                         1 14 0x2 0x0   /* PB14 periph B */
-                                                         1 15 0x2 0x0   /* PB15 periph B */
-                                                         1 16 0x2 0x0   /* PB16 periph B */
-                                                         1 17 0x2 0x0   /* PB17 periph B */
-                                                         1 18 0x2 0x0   /* PB18 periph B */
-                                                         1 19 0x2 0x0>; /* PB19 periph B */
+                                                        <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB12 periph B */
+                                                         AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB13 periph B */
+                                                         AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB14 periph B */
+                                                         AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB15 periph B */
+                                                         AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB16 periph B */
+                                                         AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB17 periph B */
+                                                         AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB18 periph B */
+                                                         AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_clk: mmc0_clk-0 {
                                                 atmel,pins =
-                                                        <0 27 0x1 0x0>; /* PA27 periph A */
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
                                         };
 
                                         pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 28 0x1 0x1   /* PA28 periph A with pullup */
-                                                         0 29 0x1 0x1>; /* PA29 periph A with pullup */
+                                                        <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA29 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <1 3 0x2 0x1    /* PB3 periph B with pullup */
-                                                         1 4 0x2 0x1    /* PB4 periph B with pullup */
-                                                         1 5 0x2 0x1>;  /* PB5 periph B with pullup */
+                                                        <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */
+                                                         AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PB5 periph B with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 8 0x2 0x1    /* PA8 periph B with pullup */
-                                                         0 9 0x2 0x1>;  /* PA9 periph B with pullup */
+                                                        <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */
+                                                         AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA9 periph B with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 10 0x2 0x1   /* PA10 periph B with pullup */
-                                                         0 11 0x2 0x1   /* PA11 periph B with pullup */
-                                                         0 12 0x2 0x1>; /* PA12 periph B with pullup */
+                                                        <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA10 periph B with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA11 periph B with pullup */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA12 periph B with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A */
-                                                         1 1 0x1 0x0    /* PB1 periph A */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <1 3 0x1 0x0    /* PB3 periph A */
-                                                         1 4 0x1 0x0    /* PB4 periph A */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                        <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                         };
                                 };
 
                                 ssc1 {
                                         pinctrl_ssc1_tx: ssc1_tx-0 {
                                                 atmel,pins =
-                                                        <1 6 0x1 0x0    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
-                                                         1 8 0x1 0x0>;  /* PB8 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                         AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                         };
 
                                         pinctrl_ssc1_rx: ssc1_rx-0 {
                                                 atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A */
-                                                         1 10 0x1 0x0   /* PB10 periph A */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                         };
                                 };
 
                                 ssc2 {
                                         pinctrl_ssc2_tx: ssc2_tx-0 {
                                                 atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A */
-                                                         1 13 0x1 0x0   /* PB13 periph A */
-                                                         1 14 0x1 0x0>; /* PB14 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */
                                         };
 
                                         pinctrl_ssc2_rx: ssc2_rx-0 {
                                                 atmel,pins =
-                                                        <1 15 0x1 0x0   /* PB15 periph A */
-                                                         1 16 0x1 0x0   /* PB16 periph A */
-                                                         1 17 0x1 0x0>; /* PB17 periph A */
+                                                        <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
                                         };
                                 };
 
                                 twi {
                                         pinctrl_twi: twi-0 {
                                                 atmel,pins =
-                                                        <0 25 0x1 0x2   /* PA25 periph A with multi drive */
-                                                         0 26 0x1 0x2>; /* PA26 periph A with multi drive */
+                                                        <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE    /* PA25 periph A with multi drive */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>;  /* PA26 periph A with multi drive */
                                         };
 
                                         pinctrl_twi_gpio: twi_gpio-0 {
                                                 atmel,pins =
-                                                        <0 25 0x0 0x2   /* PA25 GPIO with multi drive */
-                                                         0 26 0x0 0x2>; /* PA26 GPIO with multi drive */
+                                                        <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */
+                                                         AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;       /* PA26 GPIO with multi drive */
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -404,7 +500,7 @@
                                 pioB: gpio@fffff600 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -414,7 +510,7 @@
                                 pioC: gpio@fffff800 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -424,7 +520,7 @@
                                 pioD: gpio@fffffa00 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffffa00 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -435,7 +531,7 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91rm9200-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -444,7 +540,7 @@
                         usart0: serial@fffc0000 {
                                 compatible = "atmel,at91rm9200-usart";
                                 reg = <0xfffc0000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -455,7 +551,7 @@
                         usart1: serial@fffc4000 {
                                 compatible = "atmel,at91rm9200-usart";
                                 reg = <0xfffc4000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -466,7 +562,7 @@
                         usart2: serial@fffc8000 {
                                 compatible = "atmel,at91rm9200-usart";
                                 reg = <0xfffc8000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -477,7 +573,7 @@
                         usart3: serial@fffcc000 {
                                 compatible = "atmel,at91rm9200-usart";
                                 reg = <0xfffcc000 0x200>;
-                                interrupts = <23 4 5>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -488,7 +584,18 @@
                         usb1: gadget@fffb0000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfffb0000 0x4000>;
-                                interrupts = <11 4 2>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
+                                status = "disabled";
+                        };
+
+                        spi0: spi@fffe0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91rm9200-spi";
+                                reg = <0xfffe0000 0x200>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
                         };
                 };
@@ -503,9 +610,9 @@
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
                         nand-ecc-mode = "soft";
-                        gpios = <&pioC 2 0
+                        gpios = <&pioC 2 GPIO_ACTIVE_HIGH
                                  0
-                                 &pioB 1 0
+                                 &pioB 1 GPIO_ACTIVE_HIGH
                                 >;
                         status = "disabled";
                 };
@@ -513,15 +620,15 @@
                 usb0: ohci@00300000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00300000 0x100000>;
-                        interrupts = <23 4 2>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioA 25 0 /* sda */
-                         &pioA 26 0 /* scl */
+                gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
+                         &pioA 26 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index e586d85f8e23..d2d72c3b44c4 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 
 / {
         model = "Atmel AT91RM9200 evaluation kit";
@@ -50,9 +50,19 @@
                         };
 
                         usb1: gadget@fffb0000 {
-                                atmel,vbus-gpio = <&pioD 4 0>;
+                                atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
+
+                        spi0: spi@fffe0000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 3 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <15000000>;
+                                        reg = <0>;
+                                };
+                        };
                 };
 
                 usb0: ohci@00300000 {
@@ -66,19 +76,19 @@
 
                 ds2 {
                         label = "green";
-                        gpios = <&pioB 0 0x1>;
+                        gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "mmc0";
                 };
 
                 ds4 {
                         label = "yellow";
-                        gpios = <&pioB 1 0x1>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 ds6 {
                         label = "red";
-                        gpios = <&pioB 2 0x1>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 84c4bef2d726..c7ccbcbffb3e 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -8,7 +8,10 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91SAM9260 family SoC";
@@ -32,8 +35,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -84,19 +91,23 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
                         tcb0: timer@fffa0000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 0 18 4 0 19 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
+                                              18 IRQ_TYPE_LEVEL_HIGH 0
+                                              19 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         tcb1: timer@fffdc000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 0 27 4 0 28 4 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
+                                              27 IRQ_TYPE_LEVEL_HIGH 0
+                                              28 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         pinctrl@fffff400 {
@@ -116,234 +127,318 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <1 14 0x1 0x0   /* PB14 periph A */
-                                                         1 15 0x1 0x1>; /* PB15 periph with pullup */
+                                                        <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB15 periph with pullup */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <1 4 0x1 0x0    /* PB4 periph A */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
                                                 atmel,pins =
-                                                        <1 26 0x1 0x0>; /* PB26 periph A */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */
                                         };
 
                                         pinctrl_usart0_cts: usart0_cts-0 {
                                                 atmel,pins =
-                                                        <1 27 0x1 0x0>; /* PB27 periph A */
+                                                        <AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A */
                                         };
 
                                         pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
                                                 atmel,pins =
-                                                        <1 24 0x1 0x0   /* PB24 periph A */
-                                                         1 22 0x1 0x0>; /* PB22 periph A */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB24 periph A */
+                                                         AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB22 periph A */
                                         };
 
                                         pinctrl_usart0_dcd: usart0_dcd-0 {
                                                 atmel,pins =
-                                                        <1 23 0x1 0x0>; /* PB23 periph A */
+                                                        <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */
                                         };
 
                                         pinctrl_usart0_ri: usart0_ri-0 {
                                                 atmel,pins =
-                                                        <1 25 0x1 0x0>; /* PB25 periph A */
+                                                        <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */
                                         };
                                 };
 
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
                                                 atmel,pins =
-                                                        <1 28 0x1 0x0>; /* PB28 periph A */
+                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB28 periph A */
                                         };
 
                                         pinctrl_usart1_cts: usart1_cts-0 {
                                                 atmel,pins =
-                                                        <1 29 0x1 0x0>; /* PB29 periph A */
+                                                        <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB29 periph A */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <1 8 0x1 0x1    /* PB8 periph A with pullup */
-                                                         1 9 0x1 0x0>;  /* PB9 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB8 periph A with pullup */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB9 periph A */
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
                                                 atmel,pins =
-                                                        <0 4 0x1 0x0>;  /* PA4 periph A */
+                                                        <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA4 periph A */
                                         };
 
                                         pinctrl_usart2_cts: usart2_cts-0 {
                                                 atmel,pins =
-                                                        <0 5 0x1 0x0>;  /* PA5 periph A */
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA5 periph A */
                                         };
                                 };
 
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <1 10 0x1 0x1   /* PB10 periph A with pullup */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                        <AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB10 periph A with pullup */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <2 8 0x2 0x0>;  /* PC8 periph B */
+                                                        <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC8 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <2 10 0x2 0x0>; /* PC10 periph B */
+                                                        <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC10 periph B */
                                         };
                                 };
 
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <0 31 0x2 0x1   /* PA31 periph B with pullup */
-                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                                        <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA31 periph B with pullup */
+                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <1 12 0x1 0x1   /* PB12 periph A with pullup */
-                                                         1 13 0x1 0x0>; /* PB13 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB12 periph A with pullup */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <2 13 0x0 0x1   /* PC13 gpio RDY pin pull_up */
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                        <AT91_PIOC 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP     /* PC13 gpio RDY pin pull_up */
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                         };
                                 };
 
                                 macb {
                                         pinctrl_macb_rmii: macb_rmii-0 {
                                                 atmel,pins =
-                                                        <0 12 0x1 0x0   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
-                                                         0 16 0x1 0x0   /* PA16 periph A */
-                                                         0 17 0x1 0x0   /* PA17 periph A */
-                                                         0 18 0x1 0x0   /* PA18 periph A */
-                                                         0 19 0x1 0x0   /* PA19 periph A */
-                                                         0 20 0x1 0x0   /* PA20 periph A */
-                                                         0 21 0x1 0x0>; /* PA21 periph A */
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA18 periph A */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA19 periph A */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA20 periph A */
+                                                         AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */
                                         };
 
                                         pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                 atmel,pins =
-                                                        <0 22 0x2 0x0   /* PA22 periph B */
-                                                         0 23 0x2 0x0   /* PA23 periph B */
-                                                         0 24 0x2 0x0   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
-                                                         0 26 0x2 0x0   /* PA26 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                        <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA23 periph B */
+                                                         AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA26 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                         };
 
                                         pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
                                                 atmel,pins =
-                                                        <0 10 0x2 0x0   /* PA10 periph B */
-                                                         0 11 0x2 0x0   /* PA11 periph B */
-                                                         0 22 0x2 0x0   /* PA22 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
-                                                         0 26 0x2 0x0   /* PA26 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                        <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA10 periph B */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA11 periph B */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA26 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_clk: mmc0_clk-0 {
                                                 atmel,pins =
-                                                        <0 8 0x1 0x0>;  /* PA8 periph A */
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA8 periph A */
                                         };
 
                                         pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
-                                                         0 6 0x1 0x1>;  /* PA6 periph A with pullup */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA6 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
-                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
-                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA10 periph A with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA11 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 1 0x2 0x1    /* PA1 periph B with pullup */
-                                                         0 0 0x2 0x1>;  /* PA0 periph B with pullup */
+                                                        <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA1 periph B with pullup */
+                                                         AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA0 periph B with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 5 0x2 0x1    /* PA5 periph B with pullup */
-                                                         0 4 0x2 0x1    /* PA4 periph B with pullup */
-                                                         0 3 0x2 0x1>;  /* PA3 periph B with pullup */
+                                                        <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA5 periph B with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA4 periph B with pullup */
+                                                         AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA3 periph B with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <1 16 0x1 0x0   /* PB16 periph A */
-                                                         1 17 0x1 0x0   /* PB17 periph A */
-                                                         1 18 0x1 0x0>; /* PB18 periph A */
+                                                        <AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <1 19 0x1 0x0   /* PB19 periph A */
-                                                         1 20 0x1 0x0   /* PB20 periph A */
-                                                         1 21 0x1 0x0>; /* PB21 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB19 periph A */
+                                                         AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB20 periph A */
+                                                         AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB21 periph A */
                                         };
                                 };
 
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <0 0 0x1 0x0    /* PA0 periph A SPI0_MISO pin */
-                                                         0 1 0x1 0x0    /* PA1 periph A SPI0_MOSI pin */
-                                                         0 2 0x1 0x0>;  /* PA2 periph A SPI0_SPCK pin */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A SPI1_MISO pin */
-                                                         1 1 0x1 0x0    /* PB1 periph A SPI1_MOSI pin */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI1_SPCK pin */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A SPI1_MISO pin */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
+                                i2c_gpio0 {
+                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE
+                                                         AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                         };
                                 };
 
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -353,7 +448,7 @@
                                 pioB: gpio@fffff600 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -363,7 +458,7 @@
                                 pioC: gpio@fffff800 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -374,7 +469,7 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -383,7 +478,7 @@
                         usart0: serial@fffb0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -394,7 +489,7 @@
                         usart1: serial@fffb4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -405,7 +500,7 @@
                         usart2: serial@fffb8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -416,7 +511,7 @@
                         usart3: serial@fffd0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4 5>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -427,7 +522,7 @@
                         uart0: serial@fffd4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4 5>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -438,7 +533,7 @@
                         uart1: serial@fffd8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4 5>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -449,7 +544,7 @@
                         macb0: ethernet@fffc4000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4 3>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb_rmii>;
                                 status = "disabled";
@@ -458,14 +553,14 @@
                         usb1: gadget@fffa4000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4 2>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
                                 status = "disabled";
                         };
 
                         i2c0: i2c@fffac000 {
                                 compatible = "atmel,at91sam9260-i2c";
                                 reg = <0xfffac000 0x100>;
-                                interrupts = <11 4 6>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -474,7 +569,7 @@
                         mmc0: mmc@fffa8000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffa8000 0x600>;
-                                interrupts = <9 4 0>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -483,7 +578,7 @@
                         ssc0: ssc@fffbc000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfffbc000 0x4000>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -494,7 +589,7 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xfffc8000 0x200>;
-                                interrupts = <12 4 3>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -505,7 +600,7 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xfffcc000 0x200>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
@@ -514,7 +609,7 @@
                         adc0: adc@fffe0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffe0000 0x100>;
-                                interrupts = <5 4 0>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xf>;
                                 atmel,adc-vref = <3300>;
@@ -567,8 +662,8 @@
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioC 13 0
-                                 &pioC 14 0
+                        gpios = <&pioC 13 GPIO_ACTIVE_HIGH
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                  0
                                 >;
                         status = "disabled";
@@ -577,21 +672,23 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x100000>;
-                        interrupts = <20 4 2>;
+                        interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioA 23 0 /* sda */
-                         &pioA 24 0 /* scl */
+                gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
+                         &pioA 24 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
                 i2c-gpio,delay-us = <2>;        /* ~100 kHz */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_i2c_gpio0>;
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 94b58ab2cc08..d5bd65f74602 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -6,7 +6,10 @@
  * Licensed under GPLv2 only.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91SAM9263 family SoC";
@@ -29,8 +32,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -72,13 +79,13 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <19 4 0>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         rstc@fffffd00 {
@@ -110,221 +117,259 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <2 30 0x1 0x0   /* PC30 periph A */
-                                                         2 31 0x1 0x1>; /* PC31 periph with pullup */
+                                                        <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC30 periph A */
+                                                         AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC31 periph with pullup */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <0 26 0x1 0x1   /* PA26 periph A with pullup */
-                                                         0 27 0x1 0x0>; /* PA27 periph A */
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA26 periph A with pullup */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
                                                 atmel,pins =
-                                                        <0 28 0x1 0x0>; /* PA28 periph A */
+                                                        <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
                                         };
 
                                         pinctrl_usart0_cts: usart0_cts-0 {
                                                 atmel,pins =
-                                                        <0 29 0x1 0x0>; /* PA29 periph A */
+                                                        <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
                                         };
                                 };
 
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <3 0 0x1 0x1    /* PD0 periph A with pullup */
-                                                         3 1 0x1 0x0>;  /* PD1 periph A */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD1 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
                                                 atmel,pins =
-                                                        <3 7 0x2 0x0>;  /* PD7 periph B */
+                                                        <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD7 periph B */
                                         };
 
                                         pinctrl_usart1_cts: usart1_cts-0 {
                                                 atmel,pins =
-                                                        <3 8 0x2 0x0>;  /* PD8 periph B */
+                                                        <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD8 periph B */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <3 2 0x1 0x1    /* PD2 periph A with pullup */
-                                                         3 3 0x1 0x0>;  /* PD3 periph A */
+                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD3 periph A */
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
                                                 atmel,pins =
-                                                        <3 5 0x2 0x0>;  /* PD5 periph B */
+                                                        <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD5 periph B */
                                         };
 
                                         pinctrl_usart2_cts: usart2_cts-0 {
                                                 atmel,pins =
-                                                        <4 6 0x2 0x0>;  /* PD6 periph B */
+                                                        <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PD6 periph B */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <0 22 0x0 0x1   /* PA22 gpio RDY pin pull_up*/
-                                                         3 15 0x0 0x1>; /* PD15 gpio enable pin pull_up */
+                                                        <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP     /* PA22 gpio RDY pin pull_up*/
+                                                         AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD15 gpio enable pin pull_up */
                                         };
                                 };
 
                                 macb {
                                         pinctrl_macb_rmii: macb_rmii-0 {
                                                 atmel,pins =
-                                                        <2 25 0x2 0x0   /* PC25 periph B */
-                                                         4 21 0x1 0x0   /* PE21 periph A */
-                                                         4 23 0x1 0x0   /* PE23 periph A */
-                                                         4 24 0x1 0x0   /* PE24 periph A */
-                                                         4 25 0x1 0x0   /* PE25 periph A */
-                                                         4 26 0x1 0x0   /* PE26 periph A */
-                                                         4 27 0x1 0x0   /* PE27 periph A */
-                                                         4 28 0x1 0x0   /* PE28 periph A */
-                                                         4 29 0x1 0x0   /* PE29 periph A */
-                                                         4 30 0x1 0x0>; /* PE30 periph A */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC25 periph B */
+                                                         AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE21 periph A */
+                                                         AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE23 periph A */
+                                                         AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE24 periph A */
+                                                         AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE25 periph A */
+                                                         AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE26 periph A */
+                                                         AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE27 periph A */
+                                                         AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE28 periph A */
+                                                         AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PE29 periph A */
+                                                         AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
                                         };
 
                                         pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                 atmel,pins =
-                                                        <2 20 0x2 0x0   /* PC20 periph B */
-                                                         2 21 0x2 0x0   /* PC21 periph B */
-                                                         2 22 0x2 0x0   /* PC22 periph B */
-                                                         2 23 0x2 0x0   /* PC23 periph B */
-                                                         2 24 0x2 0x0   /* PC24 periph B */
-                                                         2 25 0x2 0x0   /* PC25 periph B */
-                                                         2 27 0x2 0x0   /* PC27 periph B */
-                                                         4 22 0x2 0x0>; /* PE22 periph B */
+                                                        <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC22 periph B */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC23 periph B */
+                                                         AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC24 periph B */
+                                                         AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC25 periph B */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
+                                                         AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_clk: mmc0_clk-0 {
                                                 atmel,pins =
-                                                        <0 12 0x1 0x0>; /* PA12 periph A */
+                                                        <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
                                         };
 
                                         pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
-                                                         0 0 0x1 0x1>;  /* PA0 periph A with pullup */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA0 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
-                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
-                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA5 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 16 0x1 0x1   /* PA16 periph A with pullup */
-                                                         0 17 0x1 0x1>; /* PA17 periph A with pullup */
+                                                        <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA17 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_mmc1_clk: mmc1_clk-0 {
                                                 atmel,pins =
-                                                        <0 6 0x1 0x0>;  /* PA6 periph A */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA6 periph A */
                                         };
 
                                         pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x1>;  /* PA8 periph A with pullup */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA8 periph A with pullup */
                                         };
 
                                         pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 9 0x1 0x1    /* PA9 periph A with pullup */
-                                                         0 10 0x1 0x1   /* PA10 periph A with pullup */
-                                                         0 11 0x1 0x1>; /* PA11 periph A with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA10 periph A with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA11 periph A with pullup */
                                         };
 
                                         pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 21 0x1 0x1   /* PA21 periph A with pullup */
-                                                         0 22 0x1 0x1>; /* PA22 periph A with pullup */
+                                                        <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA21 periph A with pullup */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA22 periph A with pullup */
                                         };
 
                                         pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 23 0x1 0x1   /* PA23 periph A with pullup */
-                                                         0 24 0x1 0x1   /* PA24 periph A with pullup */
-                                                         0 25 0x1 0x1>; /* PA25 periph A with pullup */
+                                                        <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA23 periph A with pullup */
+                                                         AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA24 periph A with pullup */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA25 periph A with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <1 0 0x2 0x0    /* PB0 periph B */
-                                                         1 1 0x2 0x0    /* PB1 periph B */
-                                                         1 2 0x2 0x0>;  /* PB2 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB0 periph B */
+                                                         AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB1 periph B */
+                                                         AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB2 periph B */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <1 3 0x2 0x0    /* PB3 periph B */
-                                                         1 4 0x2 0x0    /* PB4 periph B */
-                                                         1 5 0x2 0x0>;  /* PB5 periph B */
+                                                        <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB3 periph B */
+                                                         AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB4 periph B */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB5 periph B */
                                         };
                                 };
 
                                 ssc1 {
                                         pinctrl_ssc1_tx: ssc1_tx-0 {
                                                 atmel,pins =
-                                                        <1 6 0x1 0x0    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
-                                                         1 8 0x1 0x0>;  /* PB8 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                         AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                         };
 
                                         pinctrl_ssc1_rx: ssc1_rx-0 {
                                                 atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A */
-                                                         1 10 0x1 0x0   /* PB10 periph A */
-                                                         1 11 0x1 0x0>; /* PB11 periph A */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
                                         };
                                 };
 
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <0 0 0x2 0x0    /* PA0 periph B SPI0_MISO pin */
-                                                         0 1 0x2 0x0    /* PA1 periph B SPI0_MOSI pin */
-                                                         0 2 0x2 0x0>;  /* PA2 periph B SPI0_SPCK pin */
+                                                        <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA0 periph B SPI0_MISO pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA1 periph B SPI0_MOSI pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PA2 periph B SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A SPI1_MISO pin */
-                                                         1 13 0x1 0x0   /* PB13 periph A SPI1_MOSI pin */
-                                                         1 14 0x1 0x0>; /* PB14 periph A SPI1_SPCK pin */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A SPI1_MISO pin */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                         };
                                 };
 
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -334,7 +379,7 @@
                                 pioB: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -344,7 +389,7 @@
                                 pioC: gpio@fffff600 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -354,7 +399,7 @@
                                 pioD: gpio@fffff800 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -364,7 +409,7 @@
                                 pioE: gpio@fffffa00 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffffa00 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -375,7 +420,7 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -384,7 +429,7 @@
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -395,7 +440,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -406,7 +451,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4 5>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -417,7 +462,7 @@
                         ssc0: ssc@fff98000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfff98000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -426,7 +471,7 @@
                         ssc1: ssc@fff9c000 {
                                 compatible = "atmel,at91rm9200-ssc";
                                 reg = <0xfff9c000 0x4000>;
-                                interrupts = <17 4 5>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                 status = "disabled";
@@ -435,7 +480,7 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <21 4 3>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb_rmii>;
                                 status = "disabled";
@@ -444,14 +489,14 @@
                         usb1: gadget@fff78000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfff78000 0x4000>;
-                                interrupts = <24 4 2>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
                                 status = "disabled";
                         };
 
                         i2c0: i2c@fff88000 {
                                 compatible = "atmel,at91sam9263-i2c";
                                 reg = <0xfff88000 0x100>;
-                                interrupts = <13 4 6>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -460,7 +505,7 @@
                         mmc0: mmc@fff80000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
-                                interrupts = <10 4 0>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -469,7 +514,7 @@
                         mmc1: mmc@fff84000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff84000 0x600>;
-                                interrupts = <11 4 0>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -486,7 +531,7 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xfffa4000 0x200>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -497,7 +542,7 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xfffa8000 0x200>;
-                                interrupts = <15 4 3>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
@@ -515,8 +560,8 @@
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioA 22 0
-                                 &pioD 15 0
+                        gpios = <&pioA 22 GPIO_ACTIVE_HIGH
+                                 &pioD 15 GPIO_ACTIVE_HIGH
                                  0
                                 >;
                         status = "disabled";
@@ -525,15 +570,15 @@
                 usb0: ohci@00a00000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00a00000 0x100000>;
-                        interrupts = <29 4 2>;
+                        interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioB 4 0 /* sda */
-                         &pioB 5 0 /* scl */
+                gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+                         &pioB 5 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 3b82d91e7fcc..70f835b55c0b 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
         model = "Atmel at91sam9263ek";
@@ -51,7 +51,7 @@
                         };
 
                         usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioA 25 0>;
+                                atmel,vbus-gpio = <&pioA 25 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
@@ -65,8 +65,8 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioE 18 0>;
-                                        wp-gpios = <&pioE 19 0>;
+                                        cd-gpios = <&pioE 18 GPIO_ACTIVE_HIGH>;
+                                        wp-gpios = <&pioE 19 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -74,8 +74,8 @@
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
                                                 atmel,pins =
-                                                        <5 18 0x0 0x5   /* PE18 gpio CD pin pull up and deglitch */
-                                                         5 19 0x0 0x1>; /* PE19 gpio WP pin pull up */
+                                                        <AT91_PIOE 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH    /* PE18 gpio CD pin pull up and deglitch */
+                                                         AT91_PIOE 19 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PE19 gpio WP pin pull up */
                                         };
                                 };
                         };
@@ -89,6 +89,10 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -141,8 +145,8 @@
                 usb0: ohci@00a00000 {
                         num-ports = <2>;
                         status = "okay";
-                        atmel,vbus-gpio = <&pioA 24 0
-                                           &pioA 21 0
+                        atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH
+                                           &pioA 21 GPIO_ACTIVE_HIGH
                                           >;
                 };
         };
@@ -152,13 +156,13 @@
 
                 d3 {
                         label = "d3";
-                        gpios = <&pioB 7 0>;
+                        gpios = <&pioB 7 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 d2 {
                         label = "d2";
-                        gpios = <&pioC 29 1>;
+                        gpios = <&pioC 29 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "nand-disk";
                 };
         };
@@ -168,14 +172,14 @@
 
                 left_click {
                         label = "left_click";
-                        gpios = <&pioC 5 1>;
+                        gpios = <&pioC 5 GPIO_ACTIVE_LOW>;
                         linux,code = <272>;
                         gpio-key,wakeup;
                 };
 
                 right_click {
                         label = "right_click";
-                        gpios = <&pioC 4 1>;
+                        gpios = <&pioC 4 GPIO_ACTIVE_LOW>;
                         linux,code = <273>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/at91sam9g15.dtsi b/arch/arm/boot/dts/at91sam9g15.dtsi
index 28467fd6bf96..cfd7044616d7 100644
--- a/arch/arm/boot/dts/at91sam9g15.dtsi
+++ b/arch/arm/boot/dts/at91sam9g15.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
         model = "Atmel AT91SAM9G15 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g15ek.dts b/arch/arm/boot/dts/at91sam9g15ek.dts
index 5427b2dba87e..26b0444b0f96 100644
--- a/arch/arm/boot/dts/at91sam9g15ek.dts
+++ b/arch/arm/boot/dts/at91sam9g15ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g15.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g15.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
         model = "Atmel AT91SAM9G15-EK";
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index 75ce6e760016..b8e79466014f 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
         model = "Atmel AT91SAM9G20 family SoC";
diff --git a/arch/arm/boot/dts/at91sam9g20ek.dts b/arch/arm/boot/dts/at91sam9g20ek.dts
index e5324bf9d529..bbfd753112c9 100644
--- a/arch/arm/boot/dts/at91sam9g20ek.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 
 / {
         model = "Atmel at91sam9g20ek";
@@ -17,13 +17,13 @@
 
                 ds1 {
                         label = "ds1";
-                        gpios = <&pioA 9 0>;
+                        gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 ds5 {
                         label = "ds5";
-                        gpios = <&pioA 6 1>;
+                        gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
index 66467b113126..bdb799bad179 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
+++ b/arch/arm/boot/dts/at91sam9g20ek_2mmc.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20ek_common.dtsi"
+#include "at91sam9g20ek_common.dtsi"
 
 / {
         model = "Atmel at91sam9g20ek 2 mmc";
@@ -23,7 +23,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioC 2 0>;
+                                        cd-gpios = <&pioC 2 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -31,7 +31,7 @@
                                 mmc0_slot0 {
                                         pinctrl_board_mmc0_slot0: mmc0_slot0-board {
                                                 atmel,pins =
-                                                        <2 2 0x0 0x5>;  /* PC2 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PC2 gpio CD pin pull up and deglitch */
                                         };
                                 };
                         };
@@ -43,13 +43,13 @@
 
                 ds1 {
                         label = "ds1";
-                        gpios = <&pioB 9 0>;
+                        gpios = <&pioB 9 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 ds5 {
                         label = "ds5";
-                        gpios = <&pioB 8 1>;
+                        gpios = <&pioB 8 GPIO_ACTIVE_LOW>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index 6a92c5baef8c..137354689ad0 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -5,7 +5,7 @@
  *
  * Licensed under GPLv2.
  */
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 
 / {
 
@@ -34,10 +34,17 @@
                                 board {
                                         pinctrl_pck0_as_mck: pck0_as_mck {
                                                 atmel,pins =
-                                                        <2 1 0x2 0x0>;  /* PC1 periph B */
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC1 periph B */
                                         };
 
                                 };
+
+                                mmc0_slot1 {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PC9 gpio CD pin pull up and deglitch */
+                                        };
+                                };
                         };
 
                         dbgu: serial@fffff200 {
@@ -65,7 +72,7 @@
                         };
 
                         usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
@@ -79,16 +86,7 @@
                                 slot@1 {
                                         reg = <1>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioC 9 0>;
-                                };
-                        };
-
-                        pinctrl@fffff400 {
-                                mmc0_slot1 {
-                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
-                                                atmel,pins =
-                                                        <2 9 0x0 0x5>;  /* PC9 gpio CD pin pull up and deglitch */
-                                        };
+                                        cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -106,6 +104,10 @@
                                         reg = <1>;
                                 };
                         };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -180,14 +182,14 @@
 
                 btn3 {
                         label = "Button 3";
-                        gpios = <&pioA 30 1>;
+                        gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
                         linux,code = <0x103>;
                         gpio-key,wakeup;
                 };
 
                 btn4 {
                         label = "Button 4";
-                        gpios = <&pioA 31 1>;
+                        gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
                         linux,code = <0x104>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/at91sam9g25.dtsi b/arch/arm/boot/dts/at91sam9g25.dtsi
index 5fd32df03f25..b4ec6fe53fc7 100644
--- a/arch/arm/boot/dts/at91sam9g25.dtsi
+++ b/arch/arm/boot/dts/at91sam9g25.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
         model = "Atmel AT91SAM9G25 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index a1c511fecdc1..1e4c49c584d3 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g25.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
         model = "Atmel AT91SAM9G25-EK";
diff --git a/arch/arm/boot/dts/at91sam9g35.dtsi b/arch/arm/boot/dts/at91sam9g35.dtsi
index d6fa8af50724..bebf9f55614b 100644
--- a/arch/arm/boot/dts/at91sam9g35.dtsi
+++ b/arch/arm/boot/dts/at91sam9g35.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
         model = "Atmel AT91SAM9G35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9g35ek.dts b/arch/arm/boot/dts/at91sam9g35ek.dts
index 6f58ab8d21f5..641a9bf89ed1 100644
--- a/arch/arm/boot/dts/at91sam9g35ek.dts
+++ b/arch/arm/boot/dts/at91sam9g35ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9g35.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
         model = "Atmel AT91SAM9G35-EK";
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index bf18a735c37d..c3e514837074 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -9,7 +9,11 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91SAM9G45 family SoC";
@@ -35,8 +39,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -83,7 +91,7 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
 
@@ -95,19 +103,19 @@
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <18 4 0>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         tcb1: timer@fffd4000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffd4000 0x100>;
-                                interrupts = <18 4 0>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <21 4 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
@@ -130,221 +138,297 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <1 12 0x1 0x0   /* PB12 periph A */
-                                                         1 13 0x1 0x0>; /* PB13 periph A */
+                                                        <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <1 19 0x1 0x1   /* PB19 periph A with pullup */
-                                                         1 18 0x1 0x0>; /* PB18 periph A */
+                                                        <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A with pullup */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
                                                 atmel,pins =
-                                                        <1 17 0x2 0x0>; /* PB17 periph B */
+                                                        <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
                                         };
 
                                         pinctrl_usart0_cts: usart0_cts-0 {
                                                 atmel,pins =
-                                                        <1 15 0x2 0x0>; /* PB15 periph B */
+                                                        <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <1 4 0x1 0x1    /* PB4 periph A with pullup */
-                                                         1 5 0x1 0x0>;  /* PB5 periph A */
+                                                        <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB5 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
                                                 atmel,pins =
-                                                        <3 16 0x1 0x0>; /* PD16 periph A */
+                                                        <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
                                         };
 
                                         pinctrl_usart1_cts: usart1_cts-0 {
                                                 atmel,pins =
-                                                        <3 17 0x1 0x0>; /* PD17 periph A */
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <1 6 0x1 0x1    /* PB6 periph A with pullup */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A */
+                                                        <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A */
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
                                                 atmel,pins =
-                                                        <2 9 0x2 0x0>;  /* PC9 periph B */
+                                                        <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PC9 periph B */
                                         };
 
                                         pinctrl_usart2_cts: usart2_cts-0 {
                                                 atmel,pins =
-                                                        <2 11 0x2 0x0>; /* PC11 periph B */
+                                                        <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
                                         };
                                 };
 
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <1 8 0x1 0x1    /* PB9 periph A with pullup */
-                                                         1 9 0x1 0x0>;  /* PB8 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB8 periph A */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <0 23 0x2 0x0>; /* PA23 periph B */
+                                                        <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <0 24 0x2 0x0>; /* PA24 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <2 8 0x0 0x1    /* PC8 gpio RDY pin pull_up*/
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                        <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PC8 gpio RDY pin pull_up*/
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                         };
                                 };
 
                                 macb {
                                         pinctrl_macb_rmii: macb_rmii-0 {
                                                 atmel,pins =
-                                                        <0 10 0x1 0x0   /* PA10 periph A */
-                                                         0 11 0x1 0x0   /* PA11 periph A */
-                                                         0 12 0x1 0x0   /* PA12 periph A */
-                                                         0 13 0x1 0x0   /* PA13 periph A */
-                                                         0 14 0x1 0x0   /* PA14 periph A */
-                                                         0 15 0x1 0x0   /* PA15 periph A */
-                                                         0 16 0x1 0x0   /* PA16 periph A */
-                                                         0 17 0x1 0x0   /* PA17 periph A */
-                                                         0 18 0x1 0x0   /* PA18 periph A */
-                                                         0 19 0x1 0x0>; /* PA19 periph A */
+                                                        <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA16 periph A */
+                                                         AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                         AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA18 periph A */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
                                         };
 
                                         pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
                                                 atmel,pins =
-                                                        <0 6 0x2 0x0    /* PA6 periph B */
-                                                         0 7 0x2 0x0    /* PA7 periph B */
-                                                         0 8 0x2 0x0    /* PA8 periph B */
-                                                         0 9 0x2 0x0    /* PA9 periph B */
-                                                         0 27 0x2 0x0   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
-                                                         0 29 0x2 0x0   /* PA29 periph B */
-                                                         0 30 0x2 0x0>; /* PA30 periph B */
+                                                        <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA6 periph B */
+                                                         AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA7 periph B */
+                                                         AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA8 periph B */
+                                                         AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PA9 periph B */
+                                                         AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA29 periph B */
+                                                         AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 0 0x1 0x0    /* PA0 periph A */
-                                                         0 1 0x1 0x1    /* PA1 periph A with pullup */
-                                                         0 2 0x1 0x1>;  /* PA2 periph A with pullup */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA2 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 3 0x1 0x1    /* PA3 periph A with pullup */
-                                                         0 4 0x1 0x1    /* PA4 periph A with pullup */
-                                                         0 5 0x1 0x1>;  /* PA5 periph A with pullup */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA5 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
                                                 atmel,pins =
-                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
-                                                         0 7 0x1 0x1    /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x1    /* PA8 periph A with pullup */
-                                                         0 9 0x1 0x1>;  /* PA9 periph A with pullup */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PA9 periph A with pullup */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 31 0x1 0x0   /* PA31 periph A */
-                                                         0 22 0x1 0x1   /* PA22 periph A with pullup */
-                                                         0 23 0x1 0x1>; /* PA23 periph A with pullup */
+                                                        <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA31 periph A */
+                                                         AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA22 periph A with pullup */
+                                                         AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA23 periph A with pullup */
                                         };
 
                                         pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 24 0x1 0x1   /* PA24 periph A with pullup */
-                                                         0 25 0x1 0x1   /* PA25 periph A with pullup */
-                                                         0 26 0x1 0x1>; /* PA26 periph A with pullup */
+                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA24 periph A with pullup */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA25 periph A with pullup */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA26 periph A with pullup */
                                         };
 
                                         pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
                                                 atmel,pins =
-                                                        <0 27 0x1 0x1   /* PA27 periph A with pullup */
-                                                         0 28 0x1 0x1   /* PA28 periph A with pullup */
-                                                         0 29 0x1 0x1   /* PA29 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA30 periph A with pullup */
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA27 periph A with pullup */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA28 periph A with pullup */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA29 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA30 periph A with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <3 0 0x1 0x0    /* PD0 periph A */
-                                                         3 1 0x1 0x0    /* PD1 periph A */
-                                                         3 2 0x1 0x0>;  /* PD2 periph A */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD0 periph A */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD1 periph A */
+                                                         AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD2 periph A */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <3 3 0x1 0x0    /* PD3 periph A */
-                                                         3 4 0x1 0x0    /* PD4 periph A */
-                                                         3 5 0x1 0x0>;  /* PD5 periph A */
+                                                        <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD3 periph A */
+                                                         AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD4 periph A */
+                                                         AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PD5 periph A */
                                         };
                                 };
 
                                 ssc1 {
                                         pinctrl_ssc1_tx: ssc1_tx-0 {
                                                 atmel,pins =
-                                                        <3 10 0x1 0x0   /* PD10 periph A */
-                                                         3 11 0x1 0x0   /* PD11 periph A */
-                                                         3 12 0x1 0x0>; /* PD12 periph A */
+                                                        <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
                                         };
 
                                         pinctrl_ssc1_rx: ssc1_rx-0 {
                                                 atmel,pins =
-                                                        <3 13 0x1 0x0   /* PD13 periph A */
-                                                         3 14 0x1 0x0   /* PD14 periph A */
-                                                         3 15 0x1 0x0>; /* PD15 periph A */
+                                                        <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD13 periph A */
+                                                         AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD14 periph A */
+                                                         AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
                                         };
                                 };
 
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A SPI0_MISO pin */
-                                                         1 1 0x1 0x0    /* PB1 periph A SPI0_MOSI pin */
-                                                         1 2 0x1 0x0>;  /* PB2 periph A SPI0_SPCK pin */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A SPI0_MISO pin */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A SPI0_MOSI pin */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB2 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <1 14 0x1 0x0   /* PB14 periph A SPI1_MISO pin */
-                                                         1 15 0x1 0x0   /* PB15 periph A SPI1_MOSI pin */
-                                                         1 16 0x1 0x0>; /* PB16 periph A SPI1_SPCK pin */
+                                                        <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A SPI1_MISO pin */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A SPI1_MOSI pin */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
                                         };
                                 };
 
                                 pioA: gpio@fffff200 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff200 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -354,7 +438,7 @@
                                 pioB: gpio@fffff400 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -364,7 +448,7 @@
                                 pioC: gpio@fffff600 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <4 4 1>;
+                                        interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -374,7 +458,7 @@
                                 pioD: gpio@fffff800 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -384,7 +468,7 @@
                                 pioE: gpio@fffffa00 {
                                         compatible = "atmel,at91rm9200-gpio";
                                         reg = <0xfffffa00 0x200>;
-                                        interrupts = <5 4 1>;
+                                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -395,7 +479,7 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -404,7 +488,7 @@
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -415,7 +499,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -426,7 +510,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4 5>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -437,7 +521,7 @@
                         usart3: serial@fff98000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff98000 0x200>;
-                                interrupts = <10 4 5>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 pinctrl-names = "default";
@@ -448,7 +532,7 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <25 4 3>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb_rmii>;
                                 status = "disabled";
@@ -457,7 +541,7 @@
                         i2c0: i2c@fff84000 {
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff84000 0x100>;
-                                interrupts = <12 4 6>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -466,7 +550,7 @@
                         i2c1: i2c@fff88000 {
                                 compatible = "atmel,at91sam9g10-i2c";
                                 reg = <0xfff88000 0x100>;
-                                interrupts = <13 4 6>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 status = "disabled";
@@ -475,7 +559,7 @@
                         ssc0: ssc@fff9c000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xfff9c000 0x4000>;
-                                interrupts = <16 4 5>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -484,7 +568,7 @@
                         ssc1: ssc@fffa0000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xfffa0000 0x4000>;
-                                interrupts = <17 4 5>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                 status = "disabled";
@@ -493,7 +577,7 @@
                         adc0: adc@fffb0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffb0000 0x100>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xff>;
                                 atmel,adc-vref = <3300>;
@@ -533,8 +617,8 @@
                         mmc0: mmc@fff80000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfff80000 0x600>;
-                                interrupts = <11 4 0>;
-                                dmas = <&dma 1 0>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -544,8 +628,8 @@
                         mmc1: mmc@fffd0000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xfffd0000 0x600>;
-                                interrupts = <29 4 0>;
-                                dmas = <&dma 1 13>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -579,6 +663,68 @@
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        usb2: gadget@fff78000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00600000 0x80000
+                                       0xfff78000 0x400>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -592,8 +738,8 @@
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioC 8 0
-                                 &pioC 14 0
+                        gpios = <&pioC 8 GPIO_ACTIVE_HIGH
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                  0
                                 >;
                         status = "disabled";
@@ -602,22 +748,22 @@
                 usb0: ohci@00700000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00800000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00800000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioA 20 0 /* sda */
-                         &pioA 21 0 /* scl */
+                gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
+                         &pioA 21 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 51d9251b5bbe..a4b00e5c61c0 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 
 / {
         model = "Atmel AT91SAM9M10G45-EK";
@@ -59,6 +59,10 @@
                                 status = "okay";
                         };
 
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+
                         mmc0: mmc@fff80000 {
                                 pinctrl-0 = <
                                         &pinctrl_board_mmc0
@@ -68,7 +72,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 10 0>;
+                                        cd-gpios = <&pioD 10 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -81,8 +85,8 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 11 0>;
-                                        wp-gpios = <&pioD 29 0>;
+                                        cd-gpios = <&pioD 11 GPIO_ACTIVE_HIGH>;
+                                        wp-gpios = <&pioD 29 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -90,15 +94,15 @@
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
                                                 atmel,pins =
-                                                        <3 10 0x0 0x5>; /* PD10 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD10 gpio CD pin pull up and deglitch */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_board_mmc1: mmc1-board {
                                                 atmel,pins =
-                                                        <3 11 0x0 0x5   /* PD11 gpio CD pin pull up and deglitch */
-                                                         3 29 0x0 0x1>; /* PD29 gpio WP pin pull up */
+                                                        <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH    /* PD11 gpio CD pin pull up and deglitch */
+                                                         AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PD29 gpio WP pin pull up */
                                         };
                                 };
                         };
@@ -112,6 +116,11 @@
                                         reg = <0>;
                                 };
                         };
+
+                        usb2: gadget@fff78000 {
+                                atmel,vbus-gpio = <&pioB 19 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -139,8 +148,8 @@
                 usb0: ohci@00700000 {
                         status = "okay";
                         num-ports = <2>;
-                        atmel,vbus-gpio = <&pioD 1 1
-                                           &pioD 3 1>;
+                        atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW
+                                           &pioD 3 GPIO_ACTIVE_LOW>;
                 };
 
                 usb1: ehci@00800000 {
@@ -153,19 +162,19 @@
 
                 d8 {
                         label = "d8";
-                        gpios = <&pioD 30 0>;
+                        gpios = <&pioD 30 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 d6 {
                         label = "d6";
-                        gpios = <&pioD 0 1>;
+                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "nand-disk";
                 };
 
                 d7 {
                         label = "d7";
-                        gpios = <&pioD 31 1>;
+                        gpios = <&pioD 31 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -175,45 +184,45 @@
 
                 left_click {
                         label = "left_click";
-                        gpios = <&pioB 6 1>;
+                        gpios = <&pioB 6 GPIO_ACTIVE_LOW>;
                         linux,code = <272>;
                         gpio-key,wakeup;
                 };
 
                 right_click {
                         label = "right_click";
-                        gpios = <&pioB 7 1>;
+                        gpios = <&pioB 7 GPIO_ACTIVE_LOW>;
                         linux,code = <273>;
                         gpio-key,wakeup;
                 };
 
                 left {
                         label = "Joystick Left";
-                        gpios = <&pioB 14 1>;
+                        gpios = <&pioB 14 GPIO_ACTIVE_LOW>;
                         linux,code = <105>;
                 };
 
                 right {
                         label = "Joystick Right";
-                        gpios = <&pioB 15 1>;
+                        gpios = <&pioB 15 GPIO_ACTIVE_LOW>;
                         linux,code = <106>;
                 };
 
                 up {
                         label = "Joystick Up";
-                        gpios = <&pioB 16 1>;
+                        gpios = <&pioB 16 GPIO_ACTIVE_LOW>;
                         linux,code = <103>;
                 };
 
                 down {
                         label = "Joystick Down";
-                        gpios = <&pioB 17 1>;
+                        gpios = <&pioB 17 GPIO_ACTIVE_LOW>;
                         linux,code = <108>;
                 };
 
                 enter {
                         label = "Joystick Press";
-                        gpios = <&pioB 18 1>;
+                        gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
                         linux,code = <28>;
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 8d25f889928e..bb7f564b3a55 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -7,7 +7,11 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91SAM9N12 SoC";
@@ -31,8 +35,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -78,7 +86,7 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
                         shdwc@fffffe10 {
@@ -89,8 +97,8 @@
                         mmc0: mmc@f0008000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
-                                interrupts = <12 4 0>;
-                                dmas = <&dma 1 0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -100,19 +108,19 @@
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
@@ -134,159 +142,235 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <0 9 0x1 0x0    /* PA9 periph A */
-                                                         0 10 0x1 0x1>; /* PA10 periph with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA10 periph with pullup */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <0 1 0x1 0x1    /* PA1 periph A with pullup */
-                                                         0 0 0x1 0x0>;  /* PA0 periph A */
+                                                        <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA0 periph A */
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
                                                 atmel,pins =
-                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A */
                                         };
 
                                         pinctrl_usart0_cts: usart0_cts-0 {
                                                 atmel,pins =
-                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA3 periph A */
                                         };
                                 };
 
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <0 6 0x1 0x1    /* PA6 periph A with pullup */
-                                                         0 5 0x1 0x0>;  /* PA5 periph A */
+                                                        <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA5 periph A */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <0 8 0x1 0x1    /* PA8 periph A with pullup */
-                                                         0 7 0x1 0x0>;  /* PA7 periph A */
+                                                        <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA7 periph A */
                                         };
 
                                         pinctrl_usart2_rts: usart2_rts-0 {
                                                 atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                         };
 
                                         pinctrl_usart2_cts: usart2_cts-0 {
                                                 atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                         };
                                 };
 
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <2 23 0x2 0x1   /* PC23 periph B with pullup */
-                                                         2 22 0x2 0x0>; /* PC22 periph B */
+                                                        <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC23 periph B with pullup */
+                                                         AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC22 periph B */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <2 24 0x2 0x0>; /* PC24 periph B */
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <2 25 0x2 0x0>; /* PC25 periph B */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
                                         };
                                 };
 
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <2 9 0x3 0x1    /* PC9 periph C with pullup */
-                                                         2 8 0x3 0x0>;  /* PC8 periph C */
+                                                        <AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* PC9 periph C with pullup */
+                                                         AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* PC8 periph C */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <2 16 0x3 0x1   /* PC17 periph C with pullup */
-                                                         2 17 0x3 0x0>; /* PC16 periph C */
+                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* PC17 periph C with pullup */
+                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC16 periph C */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <3 5 0x0 0x1    /* PD5 gpio RDY pin pull_up*/
-                                                         3 4 0x0 0x1>;  /* PD4 gpio enable pin pull_up */
+                                                        <AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD5 gpio RDY pin pull_up*/
+                                                         AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* PD4 gpio enable pin pull_up */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
-                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
-                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA15 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
                                                 atmel,pins =
-                                                        <0 11 0x2 0x1   /* PA11 periph B with pullup */
-                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
-                                                         0 13 0x2 0x1   /* PA13 periph B with pullup */
-                                                         0 14 0x2 0x1>; /* PA14 periph B with pullup */
+                                                        <AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA11 periph B with pullup */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA12 periph B with pullup */
+                                                         AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA13 periph B with pullup */
+                                                         AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA14 periph B with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <0 24 0x2 0x0   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
-                                                         0 26 0x2 0x0>; /* PA26 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <0 27 0x2 0x0   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                        <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                         };
                                 };
 
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
-                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
-                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
-                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA21 periph B SPI1_MISO pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B SPI1_MOSI pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
                                         };
                                 };
 
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -296,7 +380,7 @@
                                 pioB: gpio@fffff600 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -306,7 +390,7 @@
                                 pioC: gpio@fffff800 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -316,7 +400,7 @@
                                 pioD: gpio@fffffa00 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffffa00 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -327,7 +411,7 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -336,7 +420,7 @@
                         ssc0: ssc@f0010000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xf0010000 0x4000>;
-                                interrupts = <28 4 5>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -345,7 +429,7 @@
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x4000>;
-                                interrupts = <5 4 5>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
                                 status = "disabled";
@@ -354,7 +438,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x4000>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
                                 status = "disabled";
@@ -363,7 +447,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x4000>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
                                 status = "disabled";
@@ -372,7 +456,7 @@
                         usart3: serial@f8028000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8028000 0x4000>;
-                                interrupts = <8 4 5>;
+                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart3>;
                                 status = "disabled";
@@ -381,9 +465,9 @@
                         i2c0: i2c@f8010000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
-                                interrupts = <9 4 6>;
-                                dmas = <&dma 1 13>,
-                                       <&dma 1 14>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(14)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -393,9 +477,9 @@
                         i2c1: i2c@f8014000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
-                                interrupts = <10 4 6>;
-                                dmas = <&dma 1 15>,
-                                       <&dma 1 16>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(15)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(16)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -407,7 +491,10 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0000000 0x100>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -418,11 +505,20 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma 1 AT91_DMA_CFG_PER_ID(4)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -439,8 +535,8 @@
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioD 5 0
-                                 &pioD 4 0
+                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
+                                 &pioD 4 GPIO_ACTIVE_HIGH
                                  0
                                 >;
                         status = "disabled";
@@ -449,15 +545,15 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x00100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioA 30 0 /* sda */
-                         &pioA 31 0 /* scl */
+                gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
+                         &pioA 31 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d30e48bd1e9d..d59b70c6a6a0 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9n12.dtsi"
+#include "at91sam9n12.dtsi"
 
 / {
         model = "Atmel AT91SAM9N12-EK";
@@ -55,7 +55,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioA 7 0>;
+                                        cd-gpios = <&pioA 7 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -63,7 +63,7 @@
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
                                                 atmel,pins =
-                                                        <0 7 0x0 0x5>;  /* PA7 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PA7 gpio CD pin pull up and deglitch */
                                         };
                                 };
                         };
@@ -77,6 +77,10 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -95,19 +99,19 @@
 
                 d8 {
                         label = "d8";
-                        gpios = <&pioB 4 1>;
+                        gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "mmc0";
                 };
 
                 d9 {
                         label = "d6";
-                        gpios = <&pioB 5 1>;
+                        gpios = <&pioB 5 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "nand-disk";
                 };
 
                 d10 {
                         label = "d7";
-                        gpios = <&pioB 6 0>;
+                        gpios = <&pioB 6 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
         };
@@ -117,7 +121,7 @@
 
                 enter {
                         label = "Enter";
-                        gpios = <&pioB 4 1>;
+                        gpios = <&pioB 4 GPIO_ACTIVE_LOW>;
                         linux,code = <28>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi
index 9ac2bc2b4f07..49e94aba938f 100644
--- a/arch/arm/boot/dts/at91sam9x25.dtsi
+++ b/arch/arm/boot/dts/at91sam9x25.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
         model = "Atmel AT91SAM9X25 SoC";
@@ -26,16 +26,16 @@
                                 macb1 {
                                         pinctrl_macb1_rmii: macb1_rmii-0 {
                                                 atmel,pins =
-                                                        <2 16 0x2 0x0   /* PC16 periph B */
-                                                         2 18 0x2 0x0   /* PC18 periph B */
-                                                         2 19 0x2 0x0   /* PC19 periph B */
-                                                         2 20 0x2 0x0   /* PC20 periph B */
-                                                         2 21 0x2 0x0   /* PC21 periph B */
-                                                         2 27 0x2 0x0   /* PC27 periph B */
-                                                         2 28 0x2 0x0   /* PC28 periph B */
-                                                         2 29 0x2 0x0   /* PC29 periph B */
-                                                         2 30 0x2 0x0   /* PC30 periph B */
-                                                         2 31 0x2 0x0>; /* PC31 periph B */
+                                                        <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC16 periph B */
+                                                         AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC18 periph B */
+                                                         AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC19 periph B */
+                                                         AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC20 periph B */
+                                                         AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC21 periph B */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC27 periph B */
+                                                         AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC28 periph B */
+                                                         AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC29 periph B */
+                                                         AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC30 periph B */
+                                                         AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC31 periph B */
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/at91sam9x25ek.dts b/arch/arm/boot/dts/at91sam9x25ek.dts
index 315250b4995e..494864836e83 100644
--- a/arch/arm/boot/dts/at91sam9x25ek.dts
+++ b/arch/arm/boot/dts/at91sam9x25ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9x25.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x25.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
         model = "Atmel AT91SAM9X25-EK";
diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi
index ba67d83d17ac..1a3d525a1f5d 100644
--- a/arch/arm/boot/dts/at91sam9x35.dtsi
+++ b/arch/arm/boot/dts/at91sam9x35.dtsi
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 
-/include/ "at91sam9x5.dtsi"
+#include "at91sam9x5.dtsi"
 
 / {
         model = "Atmel AT91SAM9X35 SoC";
diff --git a/arch/arm/boot/dts/at91sam9x35ek.dts b/arch/arm/boot/dts/at91sam9x35ek.dts
index 6ad19a0d5424..343d32818ca3 100644
--- a/arch/arm/boot/dts/at91sam9x35ek.dts
+++ b/arch/arm/boot/dts/at91sam9x35ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9x35.dtsi"
-/include/ "at91sam9x5ek.dtsi"
+#include "at91sam9x35.dtsi"
+#include "at91sam9x5ek.dtsi"
 
 / {
         model = "Atmel AT91SAM9X35-EK";
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 1145ac330fb7..57d45f5bea09 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -9,7 +9,11 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel AT91SAM9x5 family SoC";
@@ -33,8 +37,12 @@
                 ssc0 = &ssc0;
         };
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -85,32 +93,32 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
 
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4 0>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         dma0: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4 0>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
                         dma1: dma-controller@ffffee00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <21 4 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
@@ -124,297 +132,373 @@
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <0 9 0x1 0x0    /* PA9 periph A */
-                                                         0 10 0x1 0x1>; /* PA10 periph A with pullup */
+                                                        <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA10 periph A with pullup */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <0 0 0x1 0x1    /* PA0 periph A with pullup */
-                                                         0 1 0x1 0x0>;  /* PA1 periph A */
+                                                        <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA0 periph A with pullup */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA1 periph A */
                                         };
 
                                         pinctrl_usart0_rts: usart0_rts-0 {
                                                 atmel,pins =
-                                                        <0 2 0x1 0x0>;  /* PA2 periph A */
+                                                        <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA2 periph A */
                                         };
 
                                         pinctrl_usart0_cts: usart0_cts-0 {
                                                 atmel,pins =
-                                                        <0 3 0x1 0x0>;  /* PA3 periph A */
+                                                        <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA3 periph A */
                                         };
 
                                         pinctrl_usart0_sck: usart0_sck-0 {
                                                 atmel,pins =
-                                                        <0 4 0x1 0x0>;  /* PA4 periph A */
+                                                        <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA4 periph A */
                                         };
                                 };
 
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <0 5 0x1 0x1    /* PA5 periph A with pullup */
-                                                         0 6 0x1 0x0>;  /* PA6 periph A */
+                                                        <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA5 periph A with pullup */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA6 periph A */
                                         };
 
                                         pinctrl_usart1_rts: usart1_rts-0 {
                                                 atmel,pins =
-                                                        <2 27 0x3 0x0>; /* PC27 periph C */
+                                                        <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC27 periph C */
                                         };
 
                                         pinctrl_usart1_cts: usart1_cts-0 {
                                                 atmel,pins =
-                                                        <2 28 0x3 0x0>; /* PC28 periph C */
+                                                        <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C */
                                         };
 
                                         pinctrl_usart1_sck: usart1_sck-0 {
                                                 atmel,pins =
-                                                        <2 28 0x3 0x0>; /* PC29 periph C */
+                                                        <AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC29 periph C */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <0 7 0x1 0x1    /* PA7 periph A with pullup */
-                                                         0 8 0x1 0x0>;  /* PA8 periph A */
+                                                        <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PA8 periph A */
                                         };
 
                                         pinctrl_uart2_rts: uart2_rts-0 {
                                                 atmel,pins =
-                                                        <1 0 0x2 0x0>;  /* PB0 periph B */
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB0 periph B */
                                         };
 
                                         pinctrl_uart2_cts: uart2_cts-0 {
                                                 atmel,pins =
-                                                        <1 1 0x2 0x0>;  /* PB1 periph B */
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB1 periph B */
                                         };
 
                                         pinctrl_usart2_sck: usart2_sck-0 {
                                                 atmel,pins =
-                                                        <1 2 0x2 0x0>;  /* PB2 periph B */
+                                                        <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB2 periph B */
                                         };
                                 };
 
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <2 22 0x2 0x1   /* PC22 periph B with pullup */
-                                                         2 23 0x2 0x0>; /* PC23 periph B */
+                                                        <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PC22 periph B with pullup */
+                                                         AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC23 periph B */
                                         };
 
                                         pinctrl_usart3_rts: usart3_rts-0 {
                                                 atmel,pins =
-                                                        <2 24 0x2 0x0>; /* PC24 periph B */
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC24 periph B */
                                         };
 
                                         pinctrl_usart3_cts: usart3_cts-0 {
                                                 atmel,pins =
-                                                        <2 25 0x2 0x0>; /* PC25 periph B */
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC25 periph B */
                                         };
 
                                         pinctrl_usart3_sck: usart3_sck-0 {
                                                 atmel,pins =
-                                                        <2 26 0x2 0x0>; /* PC26 periph B */
+                                                        <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC26 periph B */
                                         };
                                 };
 
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <2 8 0x3 0x0    /* PC8 periph C */
-                                                         2 9 0x3 0x1>;  /* PC9 periph C with pullup */
+                                                        <AT91_PIOC 8 AT91_PERIPH_C AT91_PINCTRL_NONE    /* PC8 periph C */
+                                                         AT91_PIOC 9 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;       /* PC9 periph C with pullup */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <2 16 0x3 0x0   /* PC16 periph C */
-                                                         2 17 0x3 0x1>; /* PC17 periph C with pullup */
+                                                        <AT91_PIOC 16 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC16 periph C */
+                                                         AT91_PIOC 17 AT91_PERIPH_C AT91_PINCTRL_PULL_UP>;      /* PC17 periph C with pullup */
                                         };
                                 };
 
                                 nand {
                                         pinctrl_nand: nand-0 {
                                                 atmel,pins =
-                                                        <3 0 0x1 0x0    /* PD0 periph A Read Enable */
-                                                         3 1 0x1 0x0    /* PD1 periph A Write Enable */
-                                                         3 2 0x1 0x0    /* PD2 periph A Address Latch Enable */
-                                                         3 3 0x1 0x0    /* PD3 periph A Command Latch Enable */
-                                                         3 4 0x0 0x1    /* PD4 gpio Chip Enable pin pull_up */
-                                                         3 5 0x0 0x1    /* PD5 gpio RDY/BUSY pin pull_up */
-                                                         3 6 0x1 0x0    /* PD6 periph A Data bit 0 */
-                                                         3 7 0x1 0x0    /* PD7 periph A Data bit 1 */
-                                                         3 8 0x1 0x0    /* PD8 periph A Data bit 2 */
-                                                         3 9 0x1 0x0    /* PD9 periph A Data bit 3 */
-                                                         3 10 0x1 0x0   /* PD10 periph A Data bit 4 */
-                                                         3 11 0x1 0x0   /* PD11 periph A Data bit 5 */
-                                                         3 12 0x1 0x0   /* PD12 periph A Data bit 6 */
-                                                         3 13 0x1 0x0>; /* PD13 periph A Data bit 7 */
+                                                        <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD0 periph A Read Enable */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD1 periph A Write Enable */
+                                                         AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD2 periph A Address Latch Enable */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD3 periph A Command Latch Enable */
+                                                         AT91_PIOD 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD4 gpio Chip Enable pin pull_up */
+                                                         AT91_PIOD 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD5 gpio RDY/BUSY pin pull_up */
+                                                         AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD6 periph A Data bit 0 */
+                                                         AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD7 periph A Data bit 1 */
+                                                         AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD8 periph A Data bit 2 */
+                                                         AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD9 periph A Data bit 3 */
+                                                         AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A Data bit 4 */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A Data bit 5 */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD12 periph A Data bit 6 */
+                                                         AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD13 periph A Data bit 7 */
                                         };
 
                                         pinctrl_nand_16bits: nand_16bits-0 {
                                                 atmel,pins =
-                                                        <3 14 0x1 0x0   /* PD14 periph A Data bit 8 */
-                                                         3 15 0x1 0x0   /* PD15 periph A Data bit 9 */
-                                                         3 16 0x1 0x0   /* PD16 periph A Data bit 10 */
-                                                         3 17 0x1 0x0   /* PD17 periph A Data bit 11 */
-                                                         3 18 0x1 0x0   /* PD18 periph A Data bit 12 */
-                                                         3 19 0x1 0x0   /* PD19 periph A Data bit 13 */
-                                                         3 20 0x1 0x0   /* PD20 periph A Data bit 14 */
-                                                         3 21 0x1 0x0>; /* PD21 periph A Data bit 15 */
+                                                        <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD14 periph A Data bit 8 */
+                                                         AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD15 periph A Data bit 9 */
+                                                         AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD16 periph A Data bit 10 */
+                                                         AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD17 periph A Data bit 11 */
+                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD18 periph A Data bit 12 */
+                                                         AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD19 periph A Data bit 13 */
+                                                         AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD20 periph A Data bit 14 */
+                                                         AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A Data bit 15 */
                                         };
                                 };
 
                                 macb0 {
                                         pinctrl_macb0_rmii: macb0_rmii-0 {
                                                 atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A */
-                                                         1 1 0x1 0x0    /* PB1 periph A */
-                                                         1 2 0x1 0x0    /* PB2 periph A */
-                                                         1 3 0x1 0x0    /* PB3 periph A */
-                                                         1 4 0x1 0x0    /* PB4 periph A */
-                                                         1 5 0x1 0x0    /* PB5 periph A */
-                                                         1 6 0x1 0x0    /* PB6 periph A */
-                                                         1 7 0x1 0x0    /* PB7 periph A */
-                                                         1 9 0x1 0x0    /* PB9 periph A */
-                                                         1 10 0x1 0x0>; /* PB10 periph A */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A */
+                                                         AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A */
+                                                         AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB7 periph A */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A */
                                         };
 
                                         pinctrl_macb0_rmii_mii: macb0_rmii_mii-0 {
                                                 atmel,pins =
-                                                        <1 8 0x1 0x0    /* PB8 periph A */
-                                                         1 11 0x1 0x0   /* PB11 periph A */
-                                                         1 12 0x1 0x0   /* PB12 periph A */
-                                                         1 13 0x1 0x0   /* PB13 periph A */
-                                                         1 14 0x1 0x0   /* PB14 periph A */
-                                                         1 15 0x1 0x0   /* PB15 periph A */
-                                                         1 16 0x1 0x0   /* PB16 periph A */
-                                                         1 17 0x1 0x0>; /* PB17 periph A */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A */
+                                                         AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 17 0x1 0x0   /* PA17 periph A */
-                                                         0 16 0x1 0x1   /* PA16 periph A with pullup */
-                                                         0 15 0x1 0x1>; /* PA15 periph A with pullup */
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA17 periph A */
+                                                         AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA16 periph A with pullup */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA15 periph A with pullup */
                                         };
 
                                         pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 18 0x1 0x1   /* PA18 periph A with pullup */
-                                                         0 19 0x1 0x1   /* PA19 periph A with pullup */
-                                                         0 20 0x1 0x1>; /* PA20 periph A with pullup */
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA18 periph A with pullup */
+                                                         AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PA19 periph A with pullup */
+                                                         AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PA20 periph A with pullup */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
                                                 atmel,pins =
-                                                        <0 13 0x2 0x0   /* PA13 periph B */
-                                                         0 12 0x2 0x1   /* PA12 periph B with pullup */
-                                                         0 11 0x2 0x1>; /* PA11 periph B with pullup */
+                                                        <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA13 periph B */
+                                                         AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* PA12 periph B with pullup */
+                                                         AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA11 periph B with pullup */
                                         };
 
                                         pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
                                                 atmel,pins =
-                                                        <0 2 0x2 0x1    /* PA2 periph B with pullup */
-                                                         0 3 0x2 0x1    /* PA3 periph B with pullup */
-                                                         0 4 0x2 0x1>;  /* PA4 periph B with pullup */
+                                                        <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA2 periph B with pullup */
+                                                         AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA3 periph B with pullup */
+                                                         AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;       /* PA4 periph B with pullup */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx-0 {
                                                 atmel,pins =
-                                                        <0 24 0x2 0x0   /* PA24 periph B */
-                                                         0 25 0x2 0x0   /* PA25 periph B */
-                                                         0 26 0x2 0x0>; /* PA26 periph B */
+                                                        <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA24 periph B */
+                                                         AT91_PIOA 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA25 periph B */
+                                                         AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA26 periph B */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx-0 {
                                                 atmel,pins =
-                                                        <0 27 0x2 0x0   /* PA27 periph B */
-                                                         0 28 0x2 0x0   /* PA28 periph B */
-                                                         0 29 0x2 0x0>; /* PA29 periph B */
+                                                        <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA27 periph B */
+                                                         AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA28 periph B */
+                                                         AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA29 periph B */
                                         };
                                 };
 
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <0 11 0x1 0x0   /* PA11 periph A SPI0_MISO pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A SPI0_MOSI pin */
-                                                         0 13 0x1 0x0>; /* PA13 periph A SPI0_SPCK pin */
+                                                        <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A SPI0_MISO pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A SPI0_MOSI pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA13 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <0 21 0x2 0x0   /* PA21 periph B SPI1_MISO pin */
-                                                         0 22 0x2 0x0   /* PA22 periph B SPI1_MOSI pin */
-                                                         0 23 0x2 0x0>; /* PA23 periph B SPI1_SPCK pin */
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA21 periph B SPI1_MISO pin */
+                                                         AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA22 periph B SPI1_MOSI pin */
+                                                         AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B SPI1_SPCK pin */
                                         };
                                 };
 
                                 i2c0 {
                                         pinctrl_i2c0: i2c0-0 {
                                                 atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A I2C0 data */
-                                                         0 31 0x1 0x0>; /* PA31 periph A I2C0 clock */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A I2C0 data */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A I2C0 clock */
                                         };
                                 };
 
                                 i2c1 {
                                         pinctrl_i2c1: i2c1-0 {
                                                 atmel,pins =
-                                                        <2 0 0x3 0x0    /* PC0 periph C I2C1 data */
-                                                         2 1 0x3 0x0>;  /* PC1 periph C I2C1 clock */
+                                                        <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* PC0 periph C I2C1 data */
+                                                         AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* PC1 periph C I2C1 clock */
                                         };
                                 };
 
                                 i2c2 {
                                         pinctrl_i2c2: i2c2-0 {
                                                 atmel,pins =
-                                                        <1 4 0x2 0x0    /* PB4 periph B I2C2 data */
-                                                         1 5 0x2 0x0>;  /* PB5 periph B I2C2 clock */
+                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB4 periph B I2C2 data */
+                                                         AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB5 periph B I2C2 clock */
                                         };
                                 };
 
                                 i2c_gpio0 {
                                         pinctrl_i2c_gpio0: i2c_gpio0-0 {
                                                 atmel,pins =
-                                                        <0 30 0x0 0x2   /* PA30 gpio multidrive I2C0 data */
-                                                         0 31 0x0 0x2>; /* PA31 gpio multidrive I2C0 clock */
+                                                        <AT91_PIOA 30 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA30 gpio multidrive I2C0 data */
+                                                         AT91_PIOA 31 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;       /* PA31 gpio multidrive I2C0 clock */
                                         };
                                 };
 
                                 i2c_gpio1 {
                                         pinctrl_i2c_gpio1: i2c_gpio1-0 {
                                                 atmel,pins =
-                                                        <2 0 0x0 0x2    /* PC0 gpio multidrive I2C1 data */
-                                                         2 1 0x0 0x2>;  /* PC1 gpio multidrive I2C1 clock */
+                                                        <AT91_PIOC 0 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE  /* PC0 gpio multidrive I2C1 data */
+                                                         AT91_PIOC 1 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;        /* PC1 gpio multidrive I2C1 clock */
                                         };
                                 };
 
                                 i2c_gpio2 {
                                         pinctrl_i2c_gpio2: i2c_gpio2-0 {
                                                 atmel,pins =
-                                                        <1 4 0x0 0x2    /* PB4 gpio multidrive I2C2 data */
-                                                         1 5 0x0 0x2>;  /* PB5 gpio multidrive I2C2 clock */
+                                                        <AT91_PIOB 4 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE  /* PB4 gpio multidrive I2C2 data */
+                                                         AT91_PIOB 5 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;        /* PB5 gpio multidrive I2C2 clock */
+                                        };
+                                };
+
+                                tcb0 {
+                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
+                                                atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
+                                                atmel,pins = <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
+                                                atmel,pins = <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
+                                                atmel,pins = <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
+                                                atmel,pins = <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
+                                                atmel,pins = <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
+                                                atmel,pins = <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
+                                                atmel,pins = <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
+                                                atmel,pins = <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+
+                                tcb1 {
+                                        pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
+                                                atmel,pins = <AT91_PIOC 4 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
+                                                atmel,pins = <AT91_PIOC 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
+                                                atmel,pins = <AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
+                                                atmel,pins = <AT91_PIOC 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
+                                                atmel,pins = <AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
+                                                atmel,pins = <AT91_PIOC 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;
+                                        };
+
+                                        pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
+                                                atmel,pins = <AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE>;
                                         };
                                 };
 
                                 pioA: gpio@fffff400 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff400 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -424,7 +508,7 @@
                                 pioB: gpio@fffff600 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff600 0x200>;
-                                        interrupts = <2 4 1>;
+                                        interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         #gpio-lines = <19>;
@@ -435,7 +519,7 @@
                                 pioC: gpio@fffff800 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffff800 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         interrupt-controller;
@@ -445,7 +529,7 @@
                                 pioD: gpio@fffffa00 {
                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                         reg = <0xfffffa00 0x200>;
-                                        interrupts = <3 4 1>;
+                                        interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
                                         #gpio-cells = <2>;
                                         gpio-controller;
                                         #gpio-lines = <22>;
@@ -457,7 +541,7 @@
                         ssc0: ssc@f0010000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xf0010000 0x4000>;
-                                interrupts = <28 4 5>;
+                                interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -466,8 +550,8 @@
                         mmc0: mmc@f0008000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0008000 0x600>;
-                                interrupts = <12 4 0>;
-                                dmas = <&dma0 1 0>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -477,8 +561,8 @@
                         mmc1: mmc@f000c000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf000c000 0x600>;
-                                interrupts = <26 4 0>;
-                                dmas = <&dma1 1 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -488,7 +572,7 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -497,7 +581,7 @@
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x200>;
-                                interrupts = <5 4 5>;
+                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
                                 status = "disabled";
@@ -506,7 +590,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x200>;
-                                interrupts = <6 4 5>;
+                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
                                 status = "disabled";
@@ -515,7 +599,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x200>;
-                                interrupts = <7 4 5>;
+                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
                                 status = "disabled";
@@ -524,7 +608,7 @@
                         macb0: ethernet@f802c000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf802c000 0x100>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
                                 status = "disabled";
@@ -533,16 +617,16 @@
                         macb1: ethernet@f8030000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf8030000 0x100>;
-                                interrupts = <27 4 3>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
                                 status = "disabled";
                         };
 
                         i2c0: i2c@f8010000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8010000 0x100>;
-                                interrupts = <9 4 6>;
-                                dmas = <&dma0 1 7>,
-                                       <&dma0 1 8>;
+                                interrupts = <9 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(7)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(8)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -554,9 +638,9 @@
                         i2c1: i2c@f8014000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8014000 0x100>;
-                                interrupts = <10 4 6>;
-                                dmas = <&dma1 1 5>,
-                                       <&dma1 1 6>;
+                                interrupts = <10 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(5)>,
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(6)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -568,9 +652,9 @@
                         i2c2: i2c@f8018000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf8018000 0x100>;
-                                interrupts = <11 4 6>;
-                                dmas = <&dma0 1 9>,
-                                       <&dma0 1 10>;
+                                interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(9)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(10)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -579,10 +663,28 @@
                                 status = "disabled";
                         };
 
+                        uart0: serial@f8040000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8040000 0x200>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart0>;
+                                status = "disabled";
+                        };
+
+                        uart1: serial@f8044000 {
+                                compatible = "atmel,at91sam9260-usart";
+                                reg = <0xf8044000 0x200>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_uart1>;
+                                status = "disabled";
+                        };
+
                         adc0: adc@f804c000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xf804c000 0x100>;
-                                interrupts = <19 4 0>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
                                 atmel,adc-use-external;
                                 atmel,adc-channels-used = <0xffff>;
                                 atmel,adc-vref = <3300>;
@@ -625,7 +727,10 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0000000 0x100>;
-                                interrupts = <13 4 3>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -636,16 +741,87 @@
                                 #size-cells = <0>;
                                 compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
-                                interrupts = <14 4 3>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma1 1 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
                         };
 
+                        usb2: gadget@f803c000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00500000 0x80000
+                                       0xf803c000 0x400>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+                                status = "disabled";
+
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
+
+                        watchdog@fffffe40 {
+                                compatible = "atmel,at91sam9260-wdt";
+                                reg = <0xfffffe40 0x10>;
+                                status = "disabled";
+                        };
+
                         rtc@fffffeb0 {
-                                compatible = "atmel,at91rm9200-rtc";
+                                compatible = "atmel,at91sam9x5-rtc";
                                 reg = <0xfffffeb0 0x40>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                 status = "disabled";
                         };
                 };
@@ -664,8 +840,8 @@
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_nand>;
-                        gpios = <&pioD 5 0
-                                 &pioD 4 0
+                        gpios = <&pioD 5 GPIO_ACTIVE_HIGH
+                                 &pioD 4 GPIO_ACTIVE_HIGH
                                  0
                                 >;
                         status = "disabled";
@@ -674,22 +850,22 @@
                 usb0: ohci@00600000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00700000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4 2>;
+                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
         };
 
         i2c@0 {
                 compatible = "i2c-gpio";
-                gpios = <&pioA 30 0 /* sda */
-                         &pioA 31 0 /* scl */
+                gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
+                         &pioA 31 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
@@ -703,8 +879,8 @@
 
         i2c@1 {
                 compatible = "i2c-gpio";
-                gpios = <&pioC 0 0 /* sda */
-                         &pioC 1 0 /* scl */
+                gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
+                         &pioC 1 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
@@ -718,8 +894,8 @@
 
         i2c@2 {
                 compatible = "i2c-gpio";
-                gpios = <&pioB 4 0 /* sda */
-                         &pioB 5 0 /* scl */
+                gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
+                         &pioB 5 GPIO_ACTIVE_HIGH /* scl */
                         >;
                 i2c-gpio,sda-open-drain;
                 i2c-gpio,scl-open-drain;
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 347a74a857f6..4a5ee5cc115a 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -28,7 +28,7 @@
                         pinctrl@fffff400 {
                                 1wire_cm {
                                         pinctrl_1wire_cm: 1wire_cm-0 {
-                                                atmel,pins = <1 18 0x0 0x2>; /* PB18 multidrive, conflicts with led */
+                                                atmel,pins = <AT91_PIOB 18 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PB18 multidrive, conflicts with led */
                                         };
                                 };
                         };
@@ -75,19 +75,19 @@
 
                 pb18 {
                         label = "pb18";
-                        gpios = <&pioB 18 1>;
+                        gpios = <&pioB 18 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 pd21 {
                         label = "pd21";
-                        gpios = <&pioD 21 0>;
+                        gpios = <&pioD 21 GPIO_ACTIVE_HIGH>;
                 };
         };
 
         1wire_cm {
                 compatible = "w1-gpio";
-                gpios = <&pioB 18 0>;
+                gpios = <&pioB 18 GPIO_ACTIVE_HIGH>;
                 linux,open-drain;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_1wire_cm>;
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 1fa48d2bfd80..b753855b2058 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "at91sam9x5cm.dtsi"
+#include "at91sam9x5cm.dtsi"
 
 / {
         model = "Atmel AT91SAM9X5-EK";
@@ -27,7 +27,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 15 0>;
+                                        cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -40,7 +40,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 14 0>;
+                                        cd-gpios = <&pioD 14 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -52,6 +52,11 @@
                                 status = "okay";
                         };
 
+                        usb2: gadget@f803c000 {
+                                atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
                         i2c0: i2c@f8010000 {
                                 status = "okay";
                         };
@@ -60,14 +65,14 @@
                                 mmc0 {
                                         pinctrl_board_mmc0: mmc0-board {
                                                 atmel,pins =
-                                                        <3 15 0x0 0x5>; /* PD15 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD15 gpio CD pin pull up and deglitch */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_board_mmc1: mmc1-board {
                                                 atmel,pins =
-                                                        <3 14 0x0 0x5>; /* PD14 gpio CD pin pull up and deglitch */
+                                                        <AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;  /* PD14 gpio CD pin pull up and deglitch */
                                         };
                                 };
                         };
@@ -81,13 +86,17 @@
                                         reg = <0>;
                                 };
                         };
+
+                        watchdog@fffffe40 {
+                                status = "okay";
+                        };
                 };
 
                 usb0: ohci@00600000 {
                         status = "okay";
                         num-ports = <2>;
-                        atmel,vbus-gpio = <&pioD 19 1
-                                           &pioD 20 1
+                        atmel,vbus-gpio = <&pioD 19 GPIO_ACTIVE_LOW
+                                           &pioD 20 GPIO_ACTIVE_LOW
                                           >;
                 };
 
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 7d1a27949c13..9866cd736dee 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -613,7 +613,7 @@
                 };
 
                 rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 248067cf7069..67ec524098b5 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -13,7 +13,7 @@
 
 /dts-v1/;
 
-/include/ "bcm11351.dtsi"
+#include "bcm11351.dtsi"
 
 / {
         model = "BCM11351 BRT board";
@@ -27,4 +27,21 @@
                 status = "okay";
         };
 
+        sdio0: sdio@0x3f180000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+        sdio1: sdio@0x3f190000 {
+                non-removable;
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+        sdio3: sdio@0x3f1b0000 {
+                max-frequency = <48000000>;
+                status = "okay";
+        };
+
+
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f09..c0cdf66f8964 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -11,7 +11,10 @@
  * GNU General Public License for more details.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
 
 / {
         model = "BCM11351 SoC";
@@ -33,7 +36,7 @@
 
         smc@0x3404c000 {
                 compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
-                reg = <0x3404c000 0x400>; //1 KiB in SRAM
+                reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
         };
 
         uart@3e000000 {
@@ -41,23 +44,51 @@
                 status = "disabled";
                 reg = <0x3e000000 0x1000>;
                 clock-frequency = <13000000>;
-                interrupts = <0x0 67 0x4>;
+                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                 reg-shift = <2>;
                 reg-io-width = <4>;
         };
 
         L2: l2-cache {
-                    compatible = "arm,pl310-cache";
-                    reg = <0x3ff20000 0x1000>;
-                    cache-unified;
-                    cache-level = <2>;
+                compatible = "bcm,bcm11351-a2-pl310-cache";
+                reg = <0x3ff20000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
         };
 
         timer@35006000 {
                 compatible = "bcm,kona-timer";
                 reg = <0x35006000 0x1000>;
-                interrupts = <0x0 7 0x4>;
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
                 clock-frequency = <32768>;
         };
 
+        sdio0: sdio@0x3f180000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f180000 0x10000>;
+                interrupts = <0x0 77 0x4>;
+                status = "disabled";
+        };
+
+        sdio1: sdio@0x3f190000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f190000 0x10000>;
+                interrupts = <0x0 76 0x4>;
+                status = "disabled";
+        };
+
+        sdio2: sdio@0x3f1a0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1a0000 0x10000>;
+                interrupts = <0x0 74 0x4>;
+                status = "disabled";
+        };
+
+        sdio3: sdio@0x3f1b0000 {
+                compatible = "bcm,kona-sdhci";
+                reg = <0x3f1b0000 0x10000>;
+                interrupts = <0x0 73 0x4>;
+                status = "disabled";
+        };
+
 };
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index aafda174a605..6e9deb786a7d 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -8,6 +8,17 @@
         memory {
                 reg = <0 0x10000000>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                act {
+                        label = "ACT";
+                        gpios = <&gpio 16 1>;
+                        default-state = "keep";
+                        linux,default-trigger = "heartbeat";
+                };
+        };
 };
 
 &gpio {
diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
new file mode 100644
index 000000000000..48ff03441f5a
--- /dev/null
+++ b/arch/arm/boot/dts/ccu8540.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2013 ST-Ericsson AB
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "dbx5x0.dtsi"
+
+/ {
+        model = "ST-Ericsson U8540 platform with Device Tree";
+        compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
+
+        memory@0 {
+                reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
+        };
+
+        soc {
+                prcmu@80157000 {
+                        reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
+                        reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
+                };
+
+                uart@80120000 {
+                        status = "okay";
+                };
+
+                uart@80121000 {
+                        status = "okay";
+                };
+
+                uart@80007000 {
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ccu9540.dts
index 04305463f00d..ed29ec7288e4 100644
--- a/arch/arm/boot/dts/ccu9540.dts
+++ b/arch/arm/boot/dts/ccu9540.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 
 / {
         model = "ST-Ericsson CCU9540 platform with Device Tree";
@@ -20,7 +20,7 @@
                 reg = <0x00000000 0x20000000>;
         };
 
-        soc-u9500 {
+        soc {
                 uart@80120000 {
                         status = "okay";
                 };
@@ -52,7 +52,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts
index 422fdb3fcfc1..e750ab9086d5 100644
--- a/arch/arm/boot/dts/da850-enbw-cmc.dts
+++ b/arch/arm/boot/dts/da850-enbw-cmc.dts
@@ -10,7 +10,7 @@
  * option) any later version.
  */
 /dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
 
 / {
         compatible = "enbw,cmc", "ti,da850";
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index c914357c0d89..5bce7cc55cf3 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -8,7 +8,7 @@
  * Free Software Foundation, version 2.
  */
 /dts-v1/;
-/include/ "da850.dtsi"
+#include "da850.dtsi"
 
 / {
         compatible = "ti,da850-evm", "ti,da850";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 2c88313d2c7a..d70ba5504481 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -7,7 +7,7 @@
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         arm {
@@ -37,7 +37,7 @@
                         #size-cells = <0>;
                         pinctrl-single,bit-per-mux;
                         pinctrl-single,register-width = <32>;
-                        pinctrl-single,function-mask = <0xffffffff>;
+                        pinctrl-single,function-mask = <0xf>;
                         status = "disabled";
 
                         nand_cs3_pins: pinmux_nand_pins {
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/dbx5x0.dtsi
index b6bc4ff17f26..a1529455f081 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/dbx5x0.dtsi
@@ -9,10 +9,11 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "skeleton.dtsi"
 
 / {
-        soc-u9500 {
+        soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
                 compatible = "stericsson,db8500";
@@ -31,33 +32,33 @@
                 L2: l2-cache {
                         compatible = "arm,pl310-cache";
                         reg = <0xa0412000 0x1000>;
-                        interrupts = <0 13 4>;
+                        interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
                         cache-unified;
                         cache-level = <2>;
                 };
 
                 pmu {
                         compatible = "arm,cortex-a9-pmu";
-                        interrupts = <0 7 0x4>;
+                        interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 timer@a0410600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xa0410600 0x20>;
-                        interrupts = <1 13 0x304>;
+                        interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
                 };
 
                 rtc@80154000 {
                         compatible = "arm,rtc-pl031", "arm,primecell";
                         reg = <0x80154000 0x1000>;
-                        interrupts = <0 18 0x4>;
+                        interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 gpio0: gpio@8012e000 {
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8012e000 0x80>;
-                        interrupts = <0 119 0x4>;
+                        interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -70,7 +71,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8012e080 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -83,7 +84,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e000 0x80>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -96,7 +97,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e080 0x80>;
-                        interrupts = <0 122 0x4>;
+                        interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -109,7 +110,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e100 0x80>;
-                        interrupts = <0 123 0x4>;
+                        interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -122,7 +123,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8000e180 0x80>;
-                        interrupts = <0 124 0x4>;
+                        interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -135,7 +136,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8011e000 0x80>;
-                        interrupts = <0 125 0x4>;
+                        interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -148,7 +149,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0x8011e080 0x80>;
-                        interrupts = <0 126 0x4>;
+                        interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -161,7 +162,7 @@
                         compatible = "stericsson,db8500-gpio",
                                 "st,nomadik-gpio";
                         reg =  <0xa03fe000 0x80>;
-                        interrupts = <0 127 0x4>;
+                        interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         st,supports-sleepmode;
@@ -171,29 +172,61 @@
                 };
 
                 pinctrl {
-                        compatible = "stericsson,nmk-pinctrl";
+                        compatible = "stericsson,db8500-pinctrl";
                         prcm = <&prcmu>;
                 };
 
-                usb@a03e0000 {
+                usb_per5@a03e0000 {
                         compatible = "stericsson,db8500-musb",
                                 "mentor,musb";
                         reg = <0xa03e0000 0x10000>;
-                        interrupts = <0 23 0x4>;
-                };
-
-                dma-controller@801C0000 {
-                        compatible = "stericsson,db8500-dma40",
-                                        "stericsson,dma40";
+                        interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "mc";
+
+                        dr_mode = "otg";
+
+                        dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
+                               <&dma 38 0 0x0>, /* Logical - MemToDev */
+                               <&dma 37 0 0x2>, /* Logical - DevToMem */
+                               <&dma 37 0 0x0>, /* Logical - MemToDev */
+                               <&dma 36 0 0x2>, /* Logical - DevToMem */
+                               <&dma 36 0 0x0>, /* Logical - MemToDev */
+                               <&dma 19 0 0x2>, /* Logical - DevToMem */
+                               <&dma 19 0 0x0>, /* Logical - MemToDev */
+                               <&dma 18 0 0x2>, /* Logical - DevToMem */
+                               <&dma 18 0 0x0>, /* Logical - MemToDev */
+                               <&dma 17 0 0x2>, /* Logical - DevToMem */
+                               <&dma 17 0 0x0>, /* Logical - MemToDev */
+                               <&dma 16 0 0x2>, /* Logical - DevToMem */
+                               <&dma 16 0 0x0>, /* Logical - MemToDev */
+                               <&dma 39 0 0x2>, /* Logical - DevToMem */
+                               <&dma 39 0 0x0>; /* Logical - MemToDev */
+
+                        dma-names = "iep_1_9",  "oep_1_9",
+                                    "iep_2_10", "oep_2_10",
+                                    "iep_3_11", "oep_3_11",
+                                    "iep_4_12", "oep_4_12",
+                                    "iep_5_13", "oep_5_13",
+                                    "iep_6_14", "oep_6_14",
+                                    "iep_7_15", "oep_7_15",
+                                    "iep_8",    "oep_8";
+                };
+
+                dma: dma-controller@801C0000 {
+                        compatible = "stericsson,db8500-dma40", "stericsson,dma40";
                         reg = <0x801C0000 0x1000 0x40010000 0x800>;
-                        interrupts = <0 25 0x4>;
+                        reg-names = "base", "lcpa";
+                        interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
+
+                        #dma-cells = <3>;
+                        memcpy-channels = <56 57 58 59 60>;
                 };
 
                 prcmu: prcmu@80157000 {
                         compatible = "stericsson,db8500-prcmu";
                         reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
                         reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
-                        interrupts = <0 47 0x4>;
+                        interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         interrupt-controller;
@@ -208,7 +241,8 @@
                         thermal@801573c0 {
                                 compatible = "stericsson,db8500-thermal";
                                 reg = <0x801573c0 0x40>;
-                                interrupts = <21 0x4>, <22 0x4>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
+                                             <22 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
                                 status = "disabled";
                          };
@@ -322,21 +356,26 @@
                         ab8500 {
                                 compatible = "stericsson,ab8500";
                                 interrupt-parent = <&intc>;
-                                interrupts = <0 40 0x4>;
+                                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
 
+                                ab8500_gpio: ab8500-gpio {
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+
                                 ab8500-rtc {
                                         compatible = "stericsson,ab8500-rtc";
-                                        interrupts = <17 0x4
-                                                      18 0x4>;
+                                        interrupts = <17 IRQ_TYPE_LEVEL_HIGH
+                                                      18 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "60S", "ALARM";
                                 };
 
                                 ab8500-gpadc {
                                         compatible = "stericsson,ab8500-gpadc";
-                                        interrupts = <32 0x4
-                                                      39 0x4>;
+                                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH
+                                                      39 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "HW_CONV_END", "SW_CONV_END";
                                         vddadc-supply = <&ab8500_ldo_tvout_reg>;
                                 };
@@ -369,13 +408,13 @@
 
                                 ab8500_usb {
                                         compatible = "stericsson,ab8500-usb";
-                                        interrupts = < 90 0x4
-                                                       96 0x4
-                                                       14 0x4
-                                                       15 0x4
-                                                       79 0x4
-                                                       74 0x4
-                                                       75 0x4>;
+                                        interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
+                                                       96 IRQ_TYPE_LEVEL_HIGH
+                                                       14 IRQ_TYPE_LEVEL_HIGH
+                                                       15 IRQ_TYPE_LEVEL_HIGH
+                                                       79 IRQ_TYPE_LEVEL_HIGH
+                                                       74 IRQ_TYPE_LEVEL_HIGH
+                                                       75 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "ID_WAKEUP_R",
                                                           "ID_WAKEUP_F",
                                                           "VBUS_DET_F",
@@ -383,15 +422,15 @@
                                                           "USB_LINK_STATUS",
                                                           "USB_ADP_PROBE_PLUG",
                                                           "USB_ADP_PROBE_UNPLUG";
-                                        vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                                        vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
                                         v-ape-supply = <&db8500_vape_reg>;
                                         musb_1v8-supply = <&db8500_vsmps2_reg>;
                                 };
 
                                 ab8500-ponkey {
                                         compatible = "stericsson,ab8500-poweron-key";
-                                        interrupts = <6 0x4
-                                                      7 0x4>;
+                                        interrupts = <6 IRQ_TYPE_LEVEL_HIGH
+                                                      7 IRQ_TYPE_LEVEL_HIGH>;
                                         interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
                                 };
 
@@ -410,6 +449,11 @@
                                 codec: ab8500-codec {
                                         compatible = "stericsson,ab8500-codec";
 
+                                        V-AUD-supply = <&ab8500_ldo_audio_reg>;
+                                        V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
+                                        V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
+                                        V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
+
                                         stericsson,earpeice-cmv = <950>; /* Units in mV. */
                                 };
 
@@ -441,8 +485,8 @@
                                         };
 
                                         // supply for v-intcore12; VINTCORE12 LDO
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
-                                                regulator-compatible = "ab8500_ldo_initcore";
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
+                                                regulator-compatible = "ab8500_ldo_intcore";
                                         };
 
                                         // supply for tvout; gpadc; TVOUT LDO
@@ -460,14 +504,14 @@
                                                 regulator-compatible = "ab8500_ldo_audio";
                                         };
 
-                                        // supply for v-anamic1 VAMic1-LDO
+                                        // supply for v-anamic1 VAMIC1 LDO
                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
                                                 regulator-compatible = "ab8500_ldo_anamic1";
                                         };
 
                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
-                                                regulator-compatible = "ab8500_ldo_amamic2";
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
+                                                regulator-compatible = "ab8500_ldo_anamic2";
                                         };
 
                                         // supply for v-dmic; VDMIC LDO
@@ -486,7 +530,7 @@
                 i2c@80004000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80004000 0x1000>;
-                        interrupts = <0 21 0x4>;
+                        interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -499,7 +543,7 @@
                 i2c@80122000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80122000 0x1000>;
-                        interrupts = <0 22 0x4>;
+                        interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -512,7 +556,7 @@
                 i2c@80128000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80128000 0x1000>;
-                        interrupts = <0 55 0x4>;
+                        interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -525,7 +569,7 @@
                 i2c@80110000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x80110000 0x1000>;
-                        interrupts = <0 12 0x4>;
+                        interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -538,7 +582,7 @@
                 i2c@8012a000 {
                         compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
                         reg = <0x8012a000 0x1000>;
-                        interrupts = <0 51 0x4>;
+                        interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
                         arm,primecell-periphid = <0x180024>;
 
                         #address-cells = <1>;
@@ -551,82 +595,114 @@
                 ssp@80002000 {
                         compatible = "arm,pl022", "arm,primecell";
                         reg = <0x80002000 0x1000>;
-                        interrupts = <0 14 0x4>;
+                        interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         status = "disabled";
-
-                        // Add one of these for each child device
-                        cs-gpios = <&gpio0 31 0x4 &gpio4 14 0x4 &gpio4 16 0x4
-                                    &gpio6 22 0x4 &gpio7 0 0x4>;
-
                 };
 
                 uart@80120000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80120000 0x1000>;
-                        interrupts = <0 11 0x4>;
+                        interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
+                               <&dma 13 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
+
                 uart@80121000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80121000 0x1000>;
-                        interrupts = <0 19 0x4>;
+                        interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
+                               <&dma 12 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
+
                 uart@80007000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0x80007000 0x1000>;
-                        interrupts = <0 26 0x4>;
+                        interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
+                               <&dma 11 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi0_per1@80126000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80126000 0x1000>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
+                               <&dma 29 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi1_per2@80118000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80118000 0x1000>;
-                        interrupts = <0 50 0x4>;
+                        interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
+                               <&dma 32 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi2_per3@80005000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80005000 0x1000>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
+                               <&dma 28 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi3_per2@80119000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80119000 0x1000>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
                 sdi4_per2@80114000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80114000 0x1000>;
-                        interrupts = <0 99 0x4>;
+                        interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
+
+                        dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
+                               <&dma 42 0 0x0>; /* Logical - MemToDev */
+                        dma-names = "rx", "tx";
+
                         status = "disabled";
                 };
 
                 sdi5_per3@80008000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x80008000 0x1000>;
-                        interrupts = <0 100 0x4>;
+                        interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
 
                 msp0: msp@80123000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80123000 0x1000>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -634,7 +710,7 @@
                 msp1: msp@80124000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80124000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -643,7 +719,7 @@
                 msp2: msp@80117000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80117000 0x1000>;
-                        interrupts = <0 98 0x4>;
+                        interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -651,7 +727,7 @@
                 msp3: msp@80125000 {
                         compatible = "stericsson,ux500-msp-i2s";
                         reg = <0x80125000 0x1000>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
                         v-ape-supply = <&db8500_vape_reg>;
                         status = "disabled";
                 };
@@ -686,5 +762,20 @@
 
                         status = "disabled";
                 };
+
+                cryp@a03cb000 {
+                        compatible = "stericsson,ux500-cryp";
+                        reg = <0xa03cb000 0x1000>;
+                        interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
+
+                hash@a03c2000 {
+                        compatible = "stericsson,ux500-hash";
+                        reg = <0xa03c2000 0x1000>;
+
+                        v-ape-supply = <&db8500_vape_reg>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7e3065abd751..5cae2ab69762 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -44,11 +44,60 @@
                         gpio = <&gpio0 1 0>;
                 };
         };
+
+        clocks {
+                /* 25MHz reference crystal */
+                ref25: oscillator {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <25000000>;
+                };
+        };
 };
 
 &uart0 { status = "okay"; };
 &sata0 { status = "okay"; };
-&i2c0 { status = "okay"; };
+
+&i2c0 {
+        status = "okay";
+        clock-frequency = <100000>;
+
+        si5351: clock-generator {
+                compatible = "silabs,si5351a-msop";
+                reg = <0x60>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                #clock-cells = <1>;
+
+                /* connect xtal input to 25MHz reference */
+                clocks = <&ref25>;
+
+                /* connect xtal input as source of pll0 and pll1 */
+                silabs,pll-source = <0 0>, <1 0>;
+
+                clkout0 {
+                        reg = <0>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <0>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+
+                clkout1 {
+                        reg = <1>;
+                        silabs,drive-strength = <8>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                        silabs,pll-master;
+                };
+
+                clkout2 {
+                        reg = <2>;
+                        silabs,multisynth-source = <1>;
+                        silabs,clock-source = <0>;
+                };
+        };
+};
 
 &sdio0 {
         status = "okay";
diff --git a/arch/arm/boot/dts/ecx-common.dtsi b/arch/arm/boot/dts/ecx-common.dtsi
index d61b535f682a..e8559b753c9d 100644
--- a/arch/arm/boot/dts/ecx-common.dtsi
+++ b/arch/arm/boot/dts/ecx-common.dtsi
@@ -33,6 +33,8 @@
                         calxeda,port-phys = <&combophy5 0 &combophy0 0
                                              &combophy0 1 &combophy0 2
                                              &combophy0 3>;
+                        calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+                        calxeda,led-order = <4 0 1 2 3>;
                 };
 
                 sdhci@ffe0e000 {
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 1ea9d34460a4..143b6d25bc80 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
         model = "Ethernut 5";
@@ -40,7 +40,7 @@
                         };
 
                         usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
                 };
@@ -52,7 +52,7 @@
                         status = "okay";
 
                         gpios = <0
-                                 &pioC 14 0
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                  0
                                 >;
 
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index 96e50f569433..4d829685fdfb 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -9,7 +9,7 @@
 
 /dts-v1/;
 
-/include/ "ge863-pro3.dtsi"
+#include "ge863-pro3.dtsi"
 
 / {
         model = "Telit EVK-PRO3 for Telit GE863-PRO3";
@@ -31,7 +31,7 @@
                         };
 
                         usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
@@ -50,4 +50,4 @@
                 status = "okay";
         };
 
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 359694c78918..3f94fe8e3706 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -19,7 +19,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         interrupt-parent = <&gic>;
@@ -160,6 +160,8 @@
                 reg = <0x13400000 0x10000>;
                 interrupts = <0 94 0>;
                 samsung,power-domain = <&pd_mfc>;
+                clocks = <&clock 170>, <&clock 273>;
+                clock-names = "sclk_mfc", "mfc";
                 status = "disabled";
         };
 
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 524b90846df5..382d8c7e2906 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
         model = "Insignal Origen evaluation board based on Exynos4210";
@@ -41,6 +41,10 @@
                 enable-active-high;
         };
 
+        tmu@100C0000 {
+                status = "okay";
+        };
+
         sdhci@12530000 {
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
@@ -83,6 +87,150 @@
                 status = "okay";
         };
 
+        i2c@13860000 {
+                status = "okay";
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+
+                max8997_pmic@66 {
+                        compatible = "maxim,max8997-pmic";
+                        reg = <0x66>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <4 0>, <3 0>;
+
+                        max8997,pmic-buck1-dvs-voltage = <1350000>;
+                        max8997,pmic-buck2-dvs-voltage = <1100000>;
+                        max8997,pmic-buck5-dvs-voltage = <1200000>;
+
+                        regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ABB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDD_ALIVE_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VMIPI_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDD_RTC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VMIPI_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD_AUD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                ldo8_reg: LDO8 {
+                                        regulator-name = "VADC_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo9_reg: LDO9 {
+                                        regulator-name = "DVDD_SWB_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10_reg: LDO10 {
+                                        regulator-name = "VDD_PLL_1.1V";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD_AUD_3V";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "AVDD18_SWB_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo17_reg: LDO17 {
+                                        regulator-name = "VDD_SWB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "VDD_MIF_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "VDD_ARM_1.2V";
+                                        regulator-min-microvolt = <950000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "VDD_INT_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "VDD_G3D_1.1V";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_M1M2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "VDD_LCD_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
+
         gpio_keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
@@ -143,4 +291,25 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        fimd@11c00000 {
+                pinctrl-0 = <&lcd_en &lcd_clk &lcd_data24 &pwm0_out>;
+                pinctrl-names = "default";
+                status = "okay";
+        };
+
+        display-timings {
+                native-mode = <&timing0>;
+                timing0: timing {
+                        clock-frequency = <50000>;
+                        hactive = <1024>;
+                        vactive = <600>;
+                        hfront-porch = <64>;
+                        hback-porch = <16>;
+                        hsync-len = <48>;
+                        vback-porch = <64>;
+                        vfront-porch = <16>;
+                        vsync-len = <3>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 55a2efb763d1..553bceae8967 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -330,6 +330,95 @@
                         samsung,pin-pud = <3>;
                         samsung,pin-drv = <0>;
                 };
+
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpd0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpd0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpd0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpd0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_ctrl: lcd-ctrl {
+                        samsung,pins = "gpd0-0", "gpd0-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_sync: lcd-sync {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_en: lcd-en {
+                        samsung,pins = "gpe3-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_clk: lcd-clk {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data16: lcd-data-width16 {
+                        samsung,pins = "gpf0-7", "gpf1-0", "gpf1-1", "gpf1-2",
+                                        "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0",
+                                        "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data18: lcd-data-width18 {
+                        samsung,pins = "gpf0-6", "gpf0-7", "gpf1-0", "gpf1-1",
+                                        "gpf1-2", "gpf1-3", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1",
+                                        "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                lcd_data24: lcd-data-width24 {
+                        samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7",
+                                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3",
+                                        "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7",
+                                        "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3",
+                                        "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7",
+                                        "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
         };
 
         pinctrl@11000000 {
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 91332b72acf5..9c01b718d29d 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -15,7 +15,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
         model = "Samsung smdkv310 evaluation board based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484c7bb1..94eebffe3044 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
         model = "Samsung Trats based on Exynos4210";
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 345cdb51dcb7..889cdada1ce9 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4210.dtsi"
+#include "exynos4210.dtsi"
 
 / {
         model = "Samsung Universal C210 based on Exynos4210 rev0";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 54710de82908..b7f358a93bcb 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -19,8 +19,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4210-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4210-pinctrl.dtsi"
 
 / {
         compatible = "samsung,exynos4210";
@@ -112,12 +112,17 @@
                 interrupt-parent = <&combiner>;
                 reg = <0x100C0000 0x100>;
                 interrupts = <2 4>;
+                clocks = <&clock 383>;
+                clock-names = "tmu_apbif";
+                status = "disabled";
         };
 
         g2d@12800000 {
                 compatible = "samsung,s5pv210-g2d";
                 reg = <0x12800000 0x1000>;
                 interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index c0f60f49cea6..6f34d7f6ba7e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
         compatible = "samsung,exynos4212";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 53bc8bf77984..46c678ee119c 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -12,7 +12,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
         model = "Hardkernel ODROID-X board based on Exynos4412";
@@ -43,6 +43,7 @@
                 #size-cells = <0>;
                 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
                 pinctrl-names = "default";
+                vmmc-supply = <&ldo20_reg &buck8_reg>;
                 status = "okay";
 
                 num-slots = <1>;
@@ -78,6 +79,7 @@
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
                 pinctrl-names = "default";
+                vmmc-supply = <&ldo4_reg &ldo21_reg>;
                 status = "okay";
         };
 
@@ -108,4 +110,199 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        i2c@13860000 {
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                max77686: pmic@09 {
+                        compatible = "maxim,max77686";
+                        reg = <0x09>;
+
+                        voltage-regulators {
+                                ldo1_reg: LDO1 {
+                                        regulator-name = "VDD_ALIVE_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo2_reg: LDO2 {
+                                        regulator-name = "VDDQ_M1_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo3_reg: LDO3 {
+                                        regulator-name = "VDDQ_EXT_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo4_reg: LDO4 {
+                                        regulator-name = "VDDQ_MMC2_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo5_reg: LDO5 {
+                                        regulator-name = "VDDQ_MMC1_3_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo6_reg: LDO6 {
+                                        regulator-name = "VDD10_MPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo7_reg: LDO7 {
+                                        regulator-name = "VDD10_XPLL_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11_reg: LDO11 {
+                                        regulator-name = "VDD18_ABB1_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo12_reg: LDO12 {
+                                        regulator-name = "VDD33_USB_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo13_reg: LDO13 {
+                                        regulator-name = "VDDQ_C2C_W_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo14_reg: LDO14 {
+                                        regulator-name = "VDD18_ABB0_2_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo15_reg: LDO15 {
+                                        regulator-name = "VDD10_HSIC_1.0V";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo16_reg: LDO16 {
+                                        regulator-name = "VDD18_HSIC_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo20_reg: LDO20 {
+                                        regulator-name = "LDO20_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                };
+
+                                ldo21_reg: LDO21 {
+                                        regulator-name = "LDO21_3.3V";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo25_reg: LDO25 {
+                                        regulator-name = "VDDQ_LCD_1.8V";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck1_reg: BUCK1 {
+                                        regulator-name = "vdd_mif";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck2_reg: BUCK2 {
+                                        regulator-name = "vdd_arm";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck3_reg: BUCK3 {
+                                        regulator-name = "vdd_int";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck4_reg: BUCK4 {
+                                        regulator-name = "vdd_g3d";
+                                        regulator-min-microvolt = <900000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        regulator-microvolt-offset = <50000>;
+                                };
+
+                                buck5_reg: BUCK5 {
+                                        regulator-name = "VDDQ_CKEM1_2_1.2V";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck6_reg: BUCK6 {
+                                        regulator-name = "BUCK6_1.35V";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                buck7_reg: BUCK7 {
+                                        regulator-name = "BUCK7_2.0V";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        regulator-always-on;
+                                };
+
+                                buck8_reg: BUCK8 {
+                                        regulator-name = "BUCK8_2.8V";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 1c21bad32ca9..7993641cb32a 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
         model = "Insignal Origen evaluation board based on Exynos4412";
@@ -36,6 +36,72 @@
                 enable-active-high;
         };
 
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <2>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
+                status = "okay";
+
+                key_home {
+                        keypad,row = <0>;
+                        keypad,column = <0>;
+                        linux,code = <102>;
+                };
+
+                key_down {
+                        keypad,row = <0>;
+                        keypad,column = <1>;
+                        linux,code = <108>;
+                };
+
+                key_up {
+                        keypad,row = <1>;
+                        keypad,column = <0>;
+                        linux,code = <103>;
+                };
+
+                key_menu {
+                        keypad,row = <1>;
+                        keypad,column = <1>;
+                        linux,code = <139>;
+                };
+
+                key_back {
+                        keypad,row = <2>;
+                        keypad,column = <0>;
+                        linux,code = <158>;
+                };
+
+                key_enter {
+                        keypad,row = <2>;
+                        keypad,column = <1>;
+                        linux,code = <28>;
+                };
+        };
+
+        g2d@10800000 {
+                status = "okay";
+        };
+
         sdhci@12530000 {
                 bus-width = <4>;
                 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index dd564310d4a5..ad316a1ee9e0 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -13,7 +13,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos4412.dtsi"
+#include "exynos4412.dtsi"
 
 / {
         model = "Samsung SMDK evaluation board based on Exynos4412";
@@ -31,8 +31,91 @@
                 status = "okay";
         };
 
-        g2d@10800000 {
+        pinctrl@11000000 {
+                keypad_rows: keypad-rows {
+                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                keypad_cols: keypad-cols {
+                        samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3",
+                                       "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <3>;
+                samsung,keypad-num-columns = <8>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                pinctrl-0 = <&keypad_rows &keypad_cols>;
+                pinctrl-names = "default";
                 status = "okay";
+
+                key_1 {
+                        keypad,row = <1>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+
+                key_2 {
+                        keypad,row = <1>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+
+                key_3 {
+                        keypad,row = <1>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+
+                key_4 {
+                        keypad,row = <1>;
+                        keypad,column = <6>;
+                        linux,code = <5>;
+                };
+
+                key_5 {
+                        keypad,row = <1>;
+                        keypad,column = <7>;
+                        linux,code = <6>;
+                };
+
+                key_A {
+                        keypad,row = <2>;
+                        keypad,column = <6>;
+                        linux,code = <30>;
+                };
+
+                key_B {
+                        keypad,row = <2>;
+                        keypad,column = <7>;
+                        linux,code = <48>;
+                };
+
+                key_C {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <46>;
+                };
+
+                key_D {
+                        keypad,row = <2>;
+                        keypad,column = <5>;
+                        linux,code = <32>;
+                };
+
+                key_E {
+                        keypad,row = <0>;
+                        keypad,column = <7>;
+                        linux,code = <18>;
+                };
         };
 
         sdhci@12530000 {
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 270b389e0a1b..e743e677a9e2 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -17,7 +17,7 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4x12.dtsi"
+#include "exynos4x12.dtsi"
 
 / {
         compatible = "samsung,exynos4412";
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 099cec79e2ae..704290f7c5c0 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -778,62 +778,6 @@
                         samsung,pin-drv = <3>;
                 };
 
-                keypad_col0: keypad-col0 {
-                        samsung,pins = "gpl2-0";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col1: keypad-col1 {
-                        samsung,pins = "gpl2-1";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col2: keypad-col2 {
-                        samsung,pins = "gpl2-2";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col3: keypad-col3 {
-                        samsung,pins = "gpl2-3";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col4: keypad-col4 {
-                        samsung,pins = "gpl2-4";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col5: keypad-col5 {
-                        samsung,pins = "gpl2-5";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col6: keypad-col6 {
-                        samsung,pins = "gpl2-6";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
-                keypad_col7: keypad-col7 {
-                        samsung,pins = "gpl2-7";
-                        samsung,pin-function = <3>;
-                        samsung,pin-pud = <0>;
-                        samsung,pin-drv = <0>;
-                };
-
                 cam_port_b: cam-port-b {
                         samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
                                         "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index e3380a7a285c..01da194ba329 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -17,8 +17,8 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "exynos4.dtsi"
-/include/ "exynos4x12-pinctrl.dtsi"
+#include "exynos4.dtsi"
+#include "exynos4x12-pinctrl.dtsi"
 
 / {
         aliases {
@@ -28,14 +28,6 @@
                 pinctrl3 = &pinctrl_3;
         };
 
-        combiner:interrupt-controller@10440000 {
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
-        };
-
         clock: clock-controller@0x10030000 {
                 compatible = "samsung,exynos4412-clock";
                 reg = <0x10030000 0x20000>;
@@ -77,6 +69,8 @@
                 compatible = "samsung,exynos4212-g2d";
                 reg = <0x10800000 0x1000>;
                 interrupts = <0 89 0>;
+                clocks = <&clock 177>, <&clock 277>;
+                clock-names = "sclk_fimg2d", "fimg2d";
                 status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
new file mode 100644
index 000000000000..f65e124c04a6
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -0,0 +1,111 @@
+/*
+ * Samsung's Exynos5 SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
+ * SoCs from Exynos5 series can include this file and provide values for SoCs
+ * specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&gic>;
+
+        chipid@10000000 {
+                compatible = "samsung,exynos4210-chipid";
+                reg = <0x10000000 0x100>;
+        };
+
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                samsung,combiner-nr = <32>;
+                reg = <0x10440000 0x1000>;
+                interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                                <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                                <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                                <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                                <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+        };
+
+        gic:interrupt-controller@10481000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg =   <0x10481000 0x1000>,
+                        <0x10482000 0x1000>,
+                        <0x10484000 0x2000>,
+                        <0x10486000 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        dwmmc_0: dwmmc0@12200000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 75 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        dwmmc_1: dwmmc1@12210000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 76 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        dwmmc_2: dwmmc2@12220000 {
+                compatible = "samsung,exynos5250-dw-mshc";
+                interrupts = <0 77 0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        serial@12C00000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C00000 0x100>;
+                interrupts = <0 51 0>;
+        };
+
+        serial@12C10000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C10000 0x100>;
+                interrupts = <0 52 0>;
+        };
+
+        serial@12C20000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C20000 0x100>;
+                interrupts = <0 53 0>;
+        };
+
+        serial@12C30000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x12C30000 0x100>;
+                interrupts = <0 54 0>;
+        };
+
+        rtc {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x101E0000 0x100>;
+                interrupts = <0 43 0>, <0 44 0>;
+                status = "disabled";
+        };
+
+        watchdog {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x101D0000 0x100>;
+                interrupts = <0 42 0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 02cfc76d002f..abc7272c7afd 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
         model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -449,4 +449,35 @@
                         clock-frequency = <24000000>;
                 };
         };
+
+        dp-controller {
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <4>;
+        };
+
+        fimd: fimd@14400000 {
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing@0 {
+                                /* 2560x1600 DP panel */
+                                clock-frequency = <50000>;
+                                hactive = <2560>;
+                                vactive = <1600>;
+                                hfront-porch = <48>;
+                                hback-porch = <80>;
+                                hsync-len = <32>;
+                                vback-porch = <16>;
+                                vfront-porch = <8>;
+                                vsync-len = <6>;
+                        };
+                };
+        };
+
+        rtc {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index d1650fb34c0a..724a22f9b1c8 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -553,6 +553,13 @@
                         samsung,pin-pud = <0>;
                         samaung,pin-drv = <0>;
                 };
+
+                dp_hpd: dp_hpd {
+                        samsung,pins = "gpx0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samaung,pin-drv = <0>;
+                };
         };
 
         pinctrl@13400000 {
@@ -763,7 +770,7 @@
                 };
         };
 
-        pinctrl@03680000 {
+        pinctrl@03860000 {
                 gpz: gpz {
                         gpio-controller;
                         #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 3e0c792e2767..35a66dee4011 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -10,7 +10,7 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
+#include "exynos5250.dtsi"
 
 / {
         model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
@@ -37,6 +37,30 @@
                 };
         };
 
+        vdd:fixed-regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+        };
+
+        dbvdd:fixed-regulator@1 {
+                compatible = "regulator-fixed";
+                regulator-name = "dbvdd-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        spkvdd:fixed-regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "spkvdd-supply";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
         i2c@12C70000 {
                 samsung,i2c-sda-delay = <100>;
                 samsung,i2c-max-bus-freq = <20000>;
@@ -47,8 +71,17 @@
                 };
 
                 wm8994: wm8994@1a {
-                         compatible = "wlf,wm8994";
-                         reg = <0x1a>;
+                        compatible = "wlf,wm8994";
+                        reg = <0x1a>;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        AVDD2-supply = <&vdd>;
+                        CPVDD-supply = <&vdd>;
+                        DBVDD-supply = <&dbvdd>;
+                        SPKVDD1-supply = <&spkvdd>;
+                        SPKVDD2-supply = <&spkvdd>;
                 };
         };
 
@@ -224,6 +257,9 @@
                 samsung,color-depth = <1>;
                 samsung,link-rate = <0x0a>;
                 samsung,lane-count = <4>;
+
+                pinctrl-names = "default";
+                pinctrl-0 = <&dp_hpd>;
         };
 
         display-timings {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index d449feb7e143..e79331dba12d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -9,8 +9,8 @@
 */
 
 /dts-v1/;
-/include/ "exynos5250.dtsi"
-/include/ "cros5250-common.dtsi"
+#include "exynos5250.dtsi"
+#include "cros5250-common.dtsi"
 
 / {
         model = "Google Snow";
@@ -171,6 +171,10 @@
                 };
         };
 
+        rtc {
+                status = "okay";
+        };
+
         /*
          * On Snow we've got SIP WiFi and so can keep drive strengths low to
          * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 0673524238a6..41cd625b6020 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -17,12 +17,13 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
-/include/ "exynos5250-pinctrl.dtsi"
+#include "exynos5.dtsi"
+#include "exynos5250-pinctrl.dtsi"
+
+#include <dt-bindings/clk/exynos-audss-clk.h>
 
 / {
         compatible = "samsung,exynos5250";
-        interrupt-parent = <&gic>;
 
         aliases {
                 spi0 = &spi_0;
@@ -51,9 +52,20 @@
                 pinctrl3 = &pinctrl_3;
         };
 
-        chipid@10000000 {
-                compatible = "samsung,exynos4210-chipid";
-                reg = <0x10000000 0x100>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
         };
 
         pd_gsc: gsc-power-domain@0x10044000 {
@@ -72,15 +84,10 @@
                 #clock-cells = <1>;
         };
 
-        gic:interrupt-controller@10481000 {
-                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg = <0x10481000 0x1000>,
-                      <0x10482000 0x1000>,
-                      <0x10484000 0x2000>,
-                      <0x10486000 0x2000>;
-                interrupts = <1 9 0xf04>;
+        clock_audss: audss-clock-controller@3810000 {
+                compatible = "samsung,exynos5250-audss-clock";
+                reg = <0x03810000 0x0C>;
+                #clock-cells = <1>;
         };
 
         timer {
@@ -91,22 +98,6 @@
                              <1 10 0xf08>;
         };
 
-        combiner:interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                samsung,combiner-nr = <32>;
-                reg = <0x10440000 0x1000>;
-                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                             <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                             <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                             <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                             <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
-        };
-
         mct@101C0000 {
                 compatible = "samsung,exynos4210-mct";
                 reg = <0x101C0000 0x800>;
@@ -161,16 +152,13 @@
                 interrupts = <0 50 0>;
         };
 
-        pinctrl_3: pinctrl@03680000 {
+        pinctrl_3: pinctrl@03860000 {
                 compatible = "samsung,exynos5250-pinctrl";
-                reg = <0x0368000 0x1000>;
+                reg = <0x03860000 0x1000>;
                 interrupts = <0 47 0>;
         };
 
         watchdog {
-                compatible = "samsung,s3c2410-wdt";
-                reg = <0x101D0000 0x100>;
-                interrupts = <0 42 0>;
                 clocks = <&clock 336>;
                 clock-names = "watchdog";
         };
@@ -183,12 +171,8 @@
         };
 
         rtc {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x101E0000 0x100>;
-                interrupts = <0 43 0>, <0 44 0>;
                 clocks = <&clock 337>;
                 clock-names = "rtc";
-                status = "disabled";
         };
 
         tmu@10060000 {
@@ -200,33 +184,21 @@
         };
 
         serial@12C00000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C00000 0x100>;
-                interrupts = <0 51 0>;
                 clocks = <&clock 289>, <&clock 146>;
                 clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C10000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C10000 0x100>;
-                interrupts = <0 52 0>;
                 clocks = <&clock 290>, <&clock 147>;
                 clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C20000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C20000 0x100>;
-                interrupts = <0 53 0>;
                 clocks = <&clock 291>, <&clock 148>;
                 clock-names = "uart", "clk_uart_baud0";
         };
 
         serial@12C30000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C30000 0x100>;
-                interrupts = <0 54 0>;
                 clocks = <&clock 292>, <&clock 149>;
                 clock-names = "uart", "clk_uart_baud0";
         };
@@ -405,31 +377,19 @@
         };
 
         dwmmc_0: dwmmc0@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                 reg = <0x12200000 0x1000>;
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                 clocks = <&clock 280>, <&clock 139>;
                 clock-names = "biu", "ciu";
         };
 
         dwmmc_1: dwmmc1@12210000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                 reg = <0x12210000 0x1000>;
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                 clocks = <&clock 281>, <&clock 140>;
                 clock-names = "biu", "ciu";
         };
 
         dwmmc_2: dwmmc2@12220000 {
-                compatible = "samsung,exynos5250-dw-mshc";
                 reg = <0x12220000 0x1000>;
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
                 clocks = <&clock 282>, <&clock 141>;
                 clock-names = "biu", "ciu";
         };
@@ -451,6 +411,10 @@
                         &pdma0 9
                         &pdma0 8>;
                 dma-names = "tx", "rx", "tx-sec";
+                clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_I2S_BUS>,
+                        <&clock_audss EXYNOS_SCLK_I2S>;
+                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
                 samsung,supports-6ch;
                 samsung,supports-rstclr;
                 samsung,supports-secdai;
@@ -465,6 +429,8 @@
                 dmas = <&pdma1 12
                         &pdma1 11>;
                 dma-names = "tx", "rx";
+                clocks = <&clock 307>, <&clock 157>;
+                clock-names = "iis", "i2s_opclk0";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2s1_bus>;
         };
@@ -475,10 +441,42 @@
                 dmas = <&pdma0 12
                         &pdma0 11>;
                 dma-names = "tx", "rx";
+                clocks = <&clock 308>, <&clock 158>;
+                clock-names = "iis", "i2s_opclk0";
                 pinctrl-names = "default";
                 pinctrl-0 = <&i2s2_bus>;
         };
 
+        usb@12000000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock 286>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                dwc3 {
+                        compatible = "synopsys,dwc3";
+                        reg = <0x12000000 0x10000>;
+                        interrupts = <0 72 0>;
+                        usb-phy = <&usb2_phy &usb3_phy>;
+                };
+        };
+
+        usb3_phy: usbphy@12100000 {
+                compatible = "samsung,exynos5250-usb3phy";
+                reg = <0x12100000 0x100>;
+                clocks = <&clock 1>, <&clock 286>;
+                clock-names = "ext_xtal", "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                usbphy-sys {
+                        reg = <0x10040704 0x8>;
+                };
+        };
+
         usb@12110000 {
                 compatible = "samsung,exynos4210-ehci";
                 reg = <0x12110000 0x100>;
@@ -497,7 +495,7 @@
                 clock-names = "usbhost";
         };
 
-        usbphy@12130000 {
+        usb2_phy: usbphy@12130000 {
                 compatible = "samsung,exynos5250-usb2phy";
                 reg = <0x12130000 0x100>;
                 clocks = <&clock 1>, <&clock 285>;
@@ -621,6 +619,8 @@
                 reg = <0x145b0000 0x1000>;
                 interrupts = <10 3>;
                 interrupt-parent = <&combiner>;
+                clocks = <&clock 342>;
+                clock-names = "dp";
                 #address-cells = <1>;
                 #size-cells = <0>;
 
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
new file mode 100644
index 000000000000..5848c425ae4d
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -0,0 +1,680 @@
+/*
+ * Samsung's Exynos5420 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5420 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/ {
+        pinctrl@13400000 {
+                gpy7: gpy7 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx0: gpx0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <23 0>, <24 0>, <25 0>, <25 1>,
+                                     <26 0>, <26 1>, <27 0>, <27 1>;
+                };
+
+                gpx1: gpx1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        interrupt-parent = <&combiner>;
+                        #interrupt-cells = <2>;
+                        interrupts = <28 0>, <28 1>, <29 0>, <29 1>,
+                                     <30 0>, <30 1>, <31 0>, <31 1>;
+                };
+
+                gpx2: gpx2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpx3: gpx3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+        };
+
+        pinctrl@13410000 {
+                gpc0: gpc0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc1: gpc1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc2: gpc2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc3: gpc3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpc4: gpc4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpd1: gpd1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpy0: gpy0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy1: gpy1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy2: gpy2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy3: gpy3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy4: gpy4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy5: gpy5 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                gpy6: gpy6 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                sd0_clk: sd0-clk {
+                        samsung,pins = "gpc0-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_cmd: sd0-cmd {
+                        samsung,pins = "gpc0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_cd: sd0-cd {
+                        samsung,pins = "gpc0-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus1: sd0-bus-width1 {
+                        samsung,pins = "gpc0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus4: sd0-bus-width4 {
+                        samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd0_bus8: sd0-bus-width8 {
+                        samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_clk: sd1-clk {
+                        samsung,pins = "gpc1-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_cmd: sd1-cmd {
+                        samsung,pins = "gpc1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_cd: sd1-cd {
+                        samsung,pins = "gpc1-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_int: sd1-int {
+                        samsung,pins = "gpd1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                sd1_bus1: sd1-bus-width1 {
+                        samsung,pins = "gpc1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_bus4: sd1-bus-width4 {
+                        samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd1_bus8: sd1-bus-width8 {
+                        samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_clk: sd2-clk {
+                        samsung,pins = "gpc2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_cmd: sd2-cmd {
+                        samsung,pins = "gpc2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_cd: sd2-cd {
+                        samsung,pins = "gpc2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_bus1: sd2-bus-width1 {
+                        samsung,pins = "gpc2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+
+                sd2_bus4: sd2-bus-width4 {
+                        samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <3>;
+                };
+        };
+
+        pinctrl@14000000 {
+                gpe0: gpe0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpe1: gpe1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf0: gpf0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpf1: gpf1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg0: gpg0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg1: gpg1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpg2: gpg2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpj4: gpj4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                cam_gpio_a: cam-gpio-a {
+                        samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+                                       "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+                                       "gpe1-0", "gpe1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_gpio_b: cam-gpio-b {
+                        samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+                                       "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_i2c2_bus: cam-i2c2-bus {
+                        samsung,pins = "gpf0-4", "gpf0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                cam_spi1_bus: cam-spi1-bus {
+                        samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_i2c1_bus: cam-i2c1-bus {
+                        samsung,pins = "gpf0-2", "gpf0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_i2c0_bus: cam-i2c0-bus {
+                        samsung,pins = "gpf0-0", "gpf0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_spi0_bus: cam-spi0-bus {
+                        samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                cam_bayrgb_bus: cam-bayrgb-bus {
+                        samsung,pins = "gpg0-0", "gpg0-1", "gpg0-2", "gpg0-3",
+                                       "gpg0-4", "gpg0-5", "gpg0-6", "gpg0-7",
+                                       "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3",
+                                       "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7",
+                                       "gpg2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@14010000 {
+                gpa0: gpa0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpa1: gpa1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpa2: gpa2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb0: gpb0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb1: gpb1 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb2: gpb2 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb3: gpb3 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gpb4: gpb4 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                gph0: gph0 {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                uart0_data: uart0-data {
+                        samsung,pins = "gpa0-0", "gpa0-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart0_fctl: uart0-fctl {
+                        samsung,pins = "gpa0-2", "gpa0-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart1_data: uart1-data {
+                        samsung,pins = "gpa0-4", "gpa0-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart1_fctl: uart1-fctl {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c2_bus: i2c2-bus {
+                        samsung,pins = "gpa0-6", "gpa0-7";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart2_data: uart2-data {
+                        samsung,pins = "gpa1-0", "gpa1-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart2_fctl: uart2-fctl {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c3_bus: i2c3-bus {
+                        samsung,pins = "gpa1-2", "gpa1-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                uart3_data: uart3-data {
+                        samsung,pins = "gpa1-4", "gpa1-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi0_bus: spi0-bus {
+                        samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi1_bus: spi1-bus {
+                        samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c4_hs_bus: i2c4-hs-bus {
+                        samsung,pins = "gpa2-0", "gpa2-1";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c5_hs_bus: i2c5-hs-bus {
+                        samsung,pins = "gpa2-2", "gpa2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s1_bus: i2s1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm1_bus: pcm1-bus {
+                        samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                        "gpb0-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2s2_bus: i2s2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                pcm2_bus: pcm2-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3",
+                                        "gpb1-4";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spdif_bus: spdif-bus {
+                        samsung,pins = "gpb1-0", "gpb1-1";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+
+                spi2_bus: spi2-bus {
+                        samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <5>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c6_hs_bus: i2c6-hs-bus {
+                        samsung,pins = "gpb1-3", "gpb1-4";
+                        samsung,pin-function = <4>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c7_hs_bus: i2c7-hs-bus {
+                        samsung,pins = "gpb2-2", "gpb2-3";
+                        samsung,pin-function = <3>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c0_bus: i2c0-bus {
+                        samsung,pins = "gpb3-0", "gpb3-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c1_bus: i2c1-bus {
+                        samsung,pins = "gpb3-2", "gpb3-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c8_hs_bus: i2c8-hs-bus {
+                        samsung,pins = "gpb3-4", "gpb3-5";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c9_hs_bus: i2c9-hs-bus {
+                        samsung,pins = "gpb3-6", "gpb3-7";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+
+                i2c10_hs_bus: i2c10-hs-bus {
+                        samsung,pins = "gpb4-0", "gpb4-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+
+        pinctrl@03860000 {
+                gpz: gpz {
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
+
+                i2s0_bus: i2s0-bus {
+                        samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3",
+                                        "gpz-4", "gpz-5", "gpz-6";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
new file mode 100644
index 000000000000..08607df6a180
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -0,0 +1,33 @@
+/*
+ * SAMSUNG SMDK5420 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5420.dtsi"
+
+/ {
+        model = "Samsung SMDK5420 board based on EXYNOS5420";
+        compatible = "samsung,smdk5420", "samsung,exynos5420";
+
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttySAC2,115200 init=/linuxrc";
+        };
+
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
new file mode 100644
index 000000000000..8c54c4b74f0e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -0,0 +1,148 @@
+/*
+ * SAMSUNG EXYNOS5420 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
+ * EXYNOS5420 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5.dtsi"
+/include/ "exynos5420-pinctrl.dtsi"
+/ {
+        compatible = "samsung,exynos5420";
+
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+                pinctrl3 = &pinctrl_3;
+                pinctrl4 = &pinctrl_4;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                        clock-frequency = <1800000000>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                        clock-frequency = <1800000000>;
+                };
+
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x2>;
+                        clock-frequency = <1800000000>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x3>;
+                        clock-frequency = <1800000000>;
+                };
+        };
+
+        clock: clock-controller@0x10010000 {
+                compatible = "samsung,exynos5420-clock";
+                reg = <0x10010000 0x30000>;
+                #clock-cells = <1>;
+        };
+
+        mct@101C0000 {
+                compatible = "samsung,exynos4210-mct";
+                reg = <0x101C0000 0x800>;
+                interrupt-controller;
+                #interrups-cells = <1>;
+                interrupt-parent = <&mct_map>;
+                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
+                clocks = <&clock 1>, <&clock 315>;
+                clock-names = "fin_pll", "mct";
+
+                mct_map: mct-map {
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &combiner 23 3>,
+                                        <1 &combiner 23 4>,
+                                        <2 &combiner 25 2>,
+                                        <3 &combiner 25 3>,
+                                        <4 &gic 0 120 0>,
+                                        <5 &gic 0 121 0>,
+                                        <6 &gic 0 122 0>,
+                                        <7 &gic 0 123 0>;
+                };
+        };
+
+        pinctrl_0: pinctrl@13400000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x13400000 0x1000>;
+                interrupts = <0 45 0>;
+
+                wakeup-interrupt-controller {
+                        compatible = "samsung,exynos4210-wakeup-eint";
+                        interrupt-parent = <&gic>;
+                        interrupts = <0 32 0>;
+                };
+        };
+
+        pinctrl_1: pinctrl@13410000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x13410000 0x1000>;
+                interrupts = <0 78 0>;
+        };
+
+        pinctrl_2: pinctrl@14000000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x14000000 0x1000>;
+                interrupts = <0 46 0>;
+        };
+
+        pinctrl_3: pinctrl@14010000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x14010000 0x1000>;
+                interrupts = <0 50 0>;
+        };
+
+        pinctrl_4: pinctrl@03860000 {
+                compatible = "samsung,exynos5420-pinctrl";
+                reg = <0x03860000 0x1000>;
+                interrupts = <0 47 0>;
+        };
+
+        serial@12C00000 {
+                clocks = <&clock 257>, <&clock 128>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+
+        serial@12C10000 {
+                clocks = <&clock 258>, <&clock 129>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+
+        serial@12C20000 {
+                clocks = <&clock 259>, <&clock 130>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+
+        serial@12C30000 {
+                clocks = <&clock 260>, <&clock 131>;
+                clock-names = "uart", "clk_uart_baud0";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts
index ef747b52b674..5b22508050da 100644
--- a/arch/arm/boot/dts/exynos5440-sd5v1.dts
+++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts
@@ -10,14 +10,14 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
         model = "SAMSUNG SD5v1 board based on EXYNOS5440";
         compatible = "samsung,sd5v1", "samsung,exynos5440";
 
         chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
         };
 
         fixed-rate-clocks {
diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index d55042beb5c5..ede772741f81 100644
--- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -10,18 +10,53 @@
 */
 
 /dts-v1/;
-/include/ "exynos5440.dtsi"
+#include "exynos5440.dtsi"
 
 / {
         model = "SAMSUNG SSDK5440 board based on EXYNOS5440";
         compatible = "samsung,ssdk5440", "samsung,exynos5440";
 
         chosen {
-                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 console=ttySAC0,115200";
+                bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel early_printk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200";
         };
 
-        spi {
-                status = "disabled";
+        spi_0: spi@D0000 {
+
+                flash: w25q128@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "winbond,w25q128";
+                        spi-max-frequency = <15625000>;
+                        reg = <0>;
+                        controller-data {
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@00000 {
+                                label = "BootLoader";
+                                reg = <0x60000 0x80000>;
+                                read-only;
+                        };
+
+                        partition@e0000 {
+                                label = "Recovery-Kernel";
+                                reg = <0xe0000 0x300000>;
+                                read-only;
+                        };
+
+                        partition@3e0000 {
+                                label = "CRAM-FS";
+                                reg = <0x3e0000 0x700000>;
+                                read-only;
+                        };
+
+                        partition@ae0000 {
+                                label = "User-Data";
+                                reg = <0xae0000 0x520000>;
+                        };
+
+                };
+
         };
 
         fixed-rate-clocks {
@@ -30,4 +65,12 @@
                         clock-frequency = <50000000>;
                 };
         };
+
+        pcie@290000 {
+                reset-gpio = <&pin_ctrl 5 0>;
+        };
+
+        pcie@2a0000 {
+                reset-gpio = <&pin_ctrl 22 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index f6b1c8973845..ff7f5d855845 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -9,13 +9,17 @@
  * published by the Free Software Foundation.
 */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         compatible = "samsung,exynos5440";
 
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+        };
+
         clock: clock-controller@0x160000 {
                 compatible = "samsung,exynos5440-clock";
                 reg = <0x160000 0x1000>;
@@ -38,18 +42,22 @@
                 #size-cells = <0>;
 
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0>;
                 };
                 cpu@1 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
                 };
                 cpu@2 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <2>;
                 };
                 cpu@3 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <3>;
                 };
@@ -79,8 +87,13 @@
                 interrupts = <0 57 0>;
                 operating-points = <
                                 /* KHz    uV */
+                                1500000 1100000
+                                1400000 1075000
+                                1300000 1050000
                                 1200000 1025000
+                                1100000 1000000
                                 1000000 975000
+                                900000  950000
                                 800000  925000
                 >;
         };
@@ -101,19 +114,19 @@
                 clock-names = "uart", "clk_uart_baud0";
         };
 
-        spi {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0xD0000 0x1000>;
+        spi_0: spi@D0000 {
+                compatible = "samsung,exynos5440-spi";
+                reg = <0xD0000 0x100>;
                 interrupts = <0 4 0>;
-                tx-dma-channel = <&pdma0 5>; /* preliminary */
-                rx-dma-channel = <&pdma0 4>; /* preliminary */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                samsung,spi-src-clk = <0>;
+                num-cs = <1>;
                 clocks = <&clock 21>, <&clock 16>;
                 clock-names = "spi", "spi_busclk0";
         };
 
-        pinctrl {
+        pin_ctrl: pinctrl {
                 compatible = "samsung,exynos5440-pinctrl";
                 reg = <0xE0000 0x1000>;
                 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
@@ -184,28 +197,6 @@
                 compatible = "arm,amba-bus";
                 interrupt-parent = <&gic>;
                 ranges;
-
-                pdma0: pdma@00121000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121000 0x1000>;
-                        interrupts = <0 46 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                pdma1: pdma@00120000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x120000 0x1000>;
-                        interrupts = <0 47 0>;
-                        clocks = <&clock 8>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
         };
 
         rtc {
@@ -214,6 +205,67 @@
                 interrupts = <0 17 0>, <0 16 0>;
                 clocks = <&clock 21>;
                 clock-names = "rtc";
-                status = "disabled";
+        };
+
+        sata@210000 {
+                compatible = "snps,exynos5440-ahci";
+                reg = <0x210000 0x10000>;
+                interrupts = <0 30 0>;
+                clocks = <&clock 23>;
+                clock-names = "sata";
+        };
+
+        ohci@220000 {
+                compatible = "samsung,exynos5440-ohci";
+                reg = <0x220000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
+        };
+
+        ehci@221000 {
+                compatible = "samsung,exynos5440-ehci";
+                reg = <0x221000 0x1000>;
+                interrupts = <0 29 0>;
+                clocks = <&clock 24>;
+                clock-names = "usbhost";
+        };
+
+        pcie@290000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x290000 0x1000
+                        0x270000 0x1000
+                        0x271000 0x40>;
+                interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
+                clocks = <&clock 28>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x40001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 53>;
+        };
+
+        pcie@2a0000 {
+                compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
+                reg = <0x2a0000 0x1000
+                        0x272000 0x1000
+                        0x271040 0x40>;
+                interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
+                clocks = <&clock 29>, <&clock 27>;
+                clock-names = "pcie", "pcie_bus";
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000   /* configuration space */
+                          0x81000000 0 0          0x60001000 0 0x00010000   /* downstream I/O */
+                          0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0x0 0 &gic 56>;
         };
 };
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 17136fc7a516..230099bb31c8 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "at91sam9260.dtsi"
+#include "at91sam9260.dtsi"
 
 / {
         clocks {
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/href.dtsi
index c0bc426952ea..9db41b9d8358 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/href.dtsi
@@ -9,7 +9,8 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-/include/ "dbx5x0.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "dbx5x0.dtsi"
 
 / {
         memory {
@@ -27,7 +28,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 uart@80120000 {
                         status = "okay";
                 };
@@ -45,14 +46,14 @@
                                 compatible = "tc3589x";
                                 reg = <0x42>;
                                 interrupt-parent = <&gpio6>;
-                                interrupts = <25 0x1>;
+                                interrupts = <25 IRQ_TYPE_EDGE_RISING>;
 
                                 interrupt-controller;
                                 #interrupt-cells = <2>;
 
                                 tc3589x_gpio: tc3589x_gpio {
                                         compatible = "tc3589x-gpio";
-                                        interrupts = <0 0x1>;
+                                        interrupts = <0 IRQ_TYPE_EDGE_RISING>;
 
                                         interrupt-controller;
                                         #interrupt-cells = <2>;
@@ -63,17 +64,43 @@
                 };
 
                 i2c@80128000 {
-                        lp5521@0x33 {
-                                compatible = "lp5521";
+                        lp5521@33 {
+                                compatible = "national,lp5521";
                                 reg = <0x33>;
+                                label = "lp5521_pri";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                         };
-
-                        lp5521@0x34 {
-                                compatible = "lp5521";
+                        lp5521@34 {
+                                compatible = "national,lp5521";
                                 reg = <0x34>;
+                                label = "lp5521_sec";
+                                clock-mode = /bits/ 8 <2>;
+                                chan0 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan1 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
+                                chan2 {
+                                        led-cur = /bits/ 8 <0x2f>;
+                                        max-cur = /bits/ 8 <0x5f>;
+                                };
                         };
-
-                        bh1780@0x29 {
+                        bh1780@29 {
                                 compatible = "rohm,bh1780gli";
                                 reg = <0x33>;
                         };
@@ -82,7 +109,7 @@
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-sd-highspeed;
                         mmc-cap-mmc-highspeed;
@@ -97,7 +124,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
@@ -106,7 +133,7 @@
                 // PoP:ed eMMC
                 sdi2_per3@80005000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
 
@@ -116,7 +143,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -236,7 +263,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -256,7 +283,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/hrefprev60.dts
index c2d274815923..c6bb07df2d1d 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/hrefprev60.dts
@@ -10,9 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
-/include/ "href.dtsi"
-/include/ "stuib.dtsi"
+#include "dbx5x0.dtsi"
+#include "href.dtsi"
+#include "stuib.dtsi"
 
 / {
         model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
@@ -24,7 +24,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 prcmu@80157000 {
                         ab8500@5 {
                                 ab8500-gpio {
@@ -41,7 +41,7 @@
                 };
 
                 i2c@80110000 {
-                        bu21013_tp@0x5c {
+                        bu21013_tp@5c {
                                 reset-gpio = <&tc3589x_gpio 13 0x4>;
                         };
                 };
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/hrefv60plus.dts
index 2b587a74b813..3d580d6447f9 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/hrefv60plus.dts
@@ -10,9 +10,9 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
-/include/ "href.dtsi"
-/include/ "stuib.dtsi"
+#include "dbx5x0.dtsi"
+#include "href.dtsi"
+#include "stuib.dtsi"
 
 / {
         model = "ST-Ericsson HREF (v60+) platform with Device Tree";
@@ -24,7 +24,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
                 i2c@80110000 {
                         bu21013_tp@0x5c {
                                 reset-gpio = <&gpio4 15 0x4>;
@@ -34,7 +34,7 @@
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-sd-highspeed;
                         mmc-cap-mmc-highspeed;
@@ -48,7 +48,7 @@
                 // WLAN SDIO channel
                 sdi1_per2@80118000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
 
                         status = "okay";
@@ -57,7 +57,7 @@
                 // PoP:ed eMMC
                 sdi2_per3@80005000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
 
@@ -67,7 +67,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -172,7 +172,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -192,7 +192,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 73fd7d0887b5..587ceef81e45 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -23,8 +23,12 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
new file mode 100644
index 000000000000..e7ed9786920a
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -0,0 +1,37 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx27-phytec-phycore-som.dts"
+
+/ {
+        model = "Phytec pcm970";
+        compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
+};
+
+&sdhci2 {
+        bus-width = <4>;
+        cd-gpios = <&gpio3 29 0>;
+        wp-gpios = <&gpio3 28 0>;
+        vmmc-supply = <&vmmc1_reg>;
+        status = "okay";
+};
+
+&uart1 {
+        fsl,uart-has-rtscts;
+};
+
+&uart2 {
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
new file mode 100644
index 000000000000..f0105651869d
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx27.dtsi"
+
+/ {
+        model = "Phytec pcm038";
+        compatible = "phytec,imx27-pcm038", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi1 */
+                        serial@1000a000 {
+                                status = "okay";
+                        };
+
+                        i2c@1001d000 {
+                                clock-frequency = <400000>;
+                                status = "okay";
+                                at24@52 {
+                                        compatible = "at,24c32";
+                                        pagesize = <32>;
+                                        reg = <0x52>;
+                                };
+                                pcf8563@51 {
+                                        compatible = "nxp,pcf8563";
+                                        reg = <0x51>;
+                                };
+                                lm75@4a {
+                                        compatible = "national,lm75";
+                                        reg = <0x4a>;
+                                };
+                        };
+                };
+
+                aipi@10020000 { /* aipi2 */
+                        ethernet@1002b000 {
+                                phy-reset-gpios = <&gpio3 30 0>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        nor_flash@c0000000 {
+                compatible = "cfi-flash";
+                bank-width = <2>;
+                reg = <0xc0000000 0x02000000>;
+                linux,mtd-name = "physmap-flash.0";
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&cspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 28 0>;
+        status = "okay";
+
+        pmic: mc13783@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13783";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <23 0x4>;
+                fsl,mc13xxx-uses-adc;
+                fsl,mc13xxx-uses-rtc;
+
+                regulators {
+                        sw1a_reg: sw1a {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw1b_reg: sw1b {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw2a_reg: sw2a {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw2b_reg: sw2b {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        sw3_reg: sw3 {
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vaudio_reg: vaudio {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        violo_reg: violo {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        viohi_reg: viohi {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vgen_reg: vgen {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vcam_reg: vcam {
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        vrf1_reg: vrf1 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vrf2_reg: vrf2 {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        vmmc1_reg: vmmc1 {
+                                regulator-min-microvolt = <1600000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+
+                        gpo1_reg: gpo1 { };
+
+                        pwgt1spi_reg: pwgt1spi {
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
deleted file mode 100644
index fe64e3a91df0..000000000000
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/dts-v1/;
-#include "imx27.dtsi"
-
-/ {
-        model = "Phytec pcm038";
-        compatible = "phytec,imx27-pcm038", "fsl,imx27";
-
-        memory {
-                reg = <0x0 0x0>;
-        };
-
-        soc {
-                aipi@10000000 { /* aipi1 */
-                        serial@1000a000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        serial@1000b000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        serial@1000c000 {
-                                fsl,uart-has-rtscts;
-                                status = "okay";
-                        };
-
-                        i2c@1001d000 {
-                                clock-frequency = <400000>;
-                                status = "okay";
-                                at24@52 {
-                                        compatible = "at,24c32";
-                                        pagesize = <32>;
-                                        reg = <0x52>;
-                                };
-                                pcf8563@51 {
-                                        compatible = "nxp,pcf8563";
-                                        reg = <0x51>;
-                                };
-                                lm75@4a {
-                                        compatible = "national,lm75";
-                                        reg = <0x4a>;
-                                };
-                        };
-                };
-
-                aipi@10020000 { /* aipi2 */
-                        ethernet@1002b000 {
-                                status = "okay";
-                        };
-                };
-        };
-
-        nor_flash@c0000000 {
-                compatible = "cfi-flash";
-                bank-width = <2>;
-                reg = <0xc0000000 0x02000000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-};
-
-&nfc {
-        nand-bus-width = <8>;
-        nand-ecc-mode = "hw";
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 75bd11386516..0695264ddf1b 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -25,6 +25,9 @@
                 gpio3 = &gpio4;
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
+                spi0 = &cspi1;
+                spi1 = &cspi2;
+                spi2 = &cspi3;
         };
 
         avic: avic-interrupt-controller@e0000000 {
@@ -58,6 +61,16 @@
                         reg = <0x10000000 0x20000>;
                         ranges;
 
+                        dma: dma@10001000 {
+                                compatible = "fsl,imx27-dma";
+                                reg = <0x10001000 0x1000>;
+                                interrupts = <32>;
+                                clocks = <&clks 50>, <&clks 70>;
+                                clock-names = "ipg", "ahb";
+                                #dma-cells = <1>;
+                                #dma-channels = <16>;
+                        };
+
                         wdog: wdog@10002000 {
                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
                                 reg = <0x10002000 0x1000>;
@@ -89,6 +102,14 @@
                                 clock-names = "ipg", "per";
                         };
 
+                        pwm0: pwm@10006000 {
+                                compatible = "fsl,imx27-pwm";
+                                reg = <0x10006000 0x1000>;
+                                interrupts = <23>;
+                                clocks = <&clks 34>, <&clks 61>;
+                                clock-names = "ipg", "per";
+                        };
+
                         uart1: serial@1000a000 {
                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
                                 reg = <0x1000a000 0x1000>;
@@ -157,6 +178,28 @@
                                 status = "disabled";
                         };
 
+                        sdhci1: sdhci@10013000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10013000 0x1000>;
+                                interrupts = <11>;
+                                clocks = <&clks 30>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 7>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
+                        sdhci2: sdhci@10014000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x10014000 0x1000>;
+                                interrupts = <10>;
+                                clocks = <&clks 29>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 6>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
                         gpio1: gpio@10015000 {
                                 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
                                 reg = <0x10015000 0x100>;
@@ -272,6 +315,17 @@
                                 status = "disabled";
                         };
 
+                        sdhci3: sdhci@1001e000 {
+                                compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
+                                reg = <0x1001e000 0x1000>;
+                                interrupts = <9>;
+                                clocks = <&clks 28>, <&clks 60>;
+                                clock-names = "ipg", "per";
+                                dmas = <&dma 36>;
+                                dma-names = "rx-tx";
+                                status = "disabled";
+                        };
+
                         gpt6: timer@1001f000 {
                                 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
                                 reg = <0x1001f000 0x1000>;
@@ -288,6 +342,21 @@
                         reg = <0x10020000 0x20000>;
                         ranges;
 
+                        coda: coda@10023000 {
+                                compatible = "fsl,imx27-vpu";
+                                reg = <0x10023000 0x0200>;
+                                interrupts = <53>;
+                                clocks = <&clks 57>, <&clks 66>;
+                                clock-names = "per", "ahb";
+                                iram = <&iram>;
+                        };
+
+                        clks: ccm@10027000{
+                                compatible = "fsl,imx27-ccm";
+                                reg = <0x10027000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+
                         fec: ethernet@1002b000 {
                                 compatible = "fsl,imx27-fec";
                                 reg = <0x1002b000 0x4000>;
@@ -296,19 +365,16 @@
                                 clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
-
-                        clks: ccm@10027000{
-                                compatible = "fsl,imx27-ccm";
-                                reg = <0x10027000 0x1000>;
-                                #clock-cells = <1>;
-                        };
                 };
 
+                iram: iram@ffff4c00 {
+                        compatible = "mmio-sram";
+                        reg = <0xffff4c00 0xb400>;
+                };
 
                 nfc: nand@d8000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
-
                         compatible = "fsl,imx27-nand";
                         reg = <0xd8000000 0x1000>;
                         interrupts = <29>;
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 3d905d16cbec..b602494c152b 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -103,6 +103,7 @@
 
                 apbx@80040000 {
                         lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
                                 status = "okay";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 1594694532b9..94c4476972c3 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -45,6 +45,17 @@
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
+
+                                usb0_otg_cfa10036: otg-10036@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0142 /* MX28_PAD_GPMI_READY0__USB0_ID */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                         };
 
                         ssp0: ssp@80010000 {
@@ -58,12 +69,6 @@
                 };
 
                 apbx@80040000 {
-                        pwm: pwm@80064000 {
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&pwm4_pins_a>;
-                                status = "okay";
-                        };
-
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_b>;
@@ -73,15 +78,30 @@
                         i2c0: i2c@80058000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&i2c0_pins_b>;
+                                clock-frequency = <400000>;
                                 status = "okay";
 
-                                ssd1307: oled@3c {
-                                        compatible = "solomon,ssd1307fb-i2c";
+                                ssd1306: oled@3c {
+                                        compatible = "solomon,ssd1306fb-i2c";
                                         reg = <0x3c>;
-                                        pwms = <&pwm 4 3000>;
                                         reset-gpios = <&gpio2 7 0>;
+                                        solomon,height = <32>;
+                                        solomon,width = <128>;
+                                        solomon,page-offset = <0>;
                                 };
                         };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&usb0_otg_cfa10036>;
+                        status = "okay";
                 };
         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 063e62059890..04b2f769ffbd 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -33,7 +33,7 @@
                                                 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
                                                 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
                                                 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
-                                                0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
                                         >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
@@ -166,8 +166,8 @@
 
                 apbx@80040000 {
                         pwm: pwm@80064000 {
-                                pinctrl-names = "default", "default";
-                                pinctrl-1 = <&pwm3_pins_b>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
                                 status = "okay";
                         };
 
@@ -265,7 +265,7 @@
                 gpio-sck = <&gpio2 16 0>;
                 gpio-mosi = <&gpio2 17 0>;
                 gpio-miso = <&gpio2 18 0>;
-                cs-gpios = <&gpio3 23 0>;
+                cs-gpios = <&gpio3 5 0>;
                 num-chipselects = <1>;
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
new file mode 100644
index 000000000000..158111244122
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ *                                Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10055 is an expansion board for the CFA-10036 module and
+ * CFA-10037, thus we need to include the CFA-10037 DTS.
+ */
+/include/ "imx28-cfa10037.dts"
+
+/ {
+        model = "Crystalfontz CFA-10055 Board";
+        compatible = "crystalfontz,cfa10055", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10055
+                                        &hog_pins_cfa10055_pullup>;
+
+                                hog_pins_cfa10055: hog-10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                spi2_pins_cfa10055: spi2-cfa10055@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
+                                                0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
+                                                0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                lcdif_18bit_pins_cfa10055: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_cfa10055: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10055
+                                             &lcdif_pins_cfa10055>;
+                                display = <&display>;
+                                status = "okay";
+
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <9216000>;
+                                                        hactive = <320>;
+                                                        vactive = <480>;
+                                                        hback-porch = <2>;
+                                                        hfront-porch = <2>;
+                                                        vback-porch = <2>;
+                                                        vfront-porch = <2>;
+                                                        hsync-len = <15>;
+                                                        vsync-len = <15>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        spi2 {
+                compatible = "spi-gpio";
+                pinctrl-names = "default";
+                pinctrl-0 = <&spi2_pins_cfa10055>;
+                status = "okay";
+                gpio-sck = <&gpio2 16 0>;
+                gpio-mosi = <&gpio2 17 0>;
+                gpio-miso = <&gpio2 18 0>;
+                cs-gpios = <&gpio3 5 0>;
+                num-chipselects = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                hx8357: hx8357@0 {
+                        compatible = "himax,hx8357b", "himax,hx8357";
+                        reg = <0>;
+                        spi-max-frequency = <100000>;
+                        spi-cpol;
+                        spi-cpha;
+                        gpios-reset = <&gpio3 30 0>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
new file mode 100644
index 000000000000..2da713cdb42a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -0,0 +1,191 @@
+/*
+ * Copyright 2013 Crystalfontz America, Inc.
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
+ * need to include the CFA-10036 DTS.
+ */
+/include/ "imx28-cfa10036.dts"
+
+/ {
+        model = "Crystalfontz CFA-10057 Board";
+        compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28";
+
+        apb@80000000 {
+                apbh@80000000 {
+                        pinctrl@80018000 {
+                                pinctrl-names = "default", "default";
+                                pinctrl-1 = <&hog_pins_cfa10057
+                                        &hog_pins_cfa10057_pullup>;
+
+                                hog_pins_cfa10057: hog-10057@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
+                                                0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
+                                                0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
+                                                0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_cfa10057: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_18bit_pins_cfa10057
+                                             &lcdif_pins_cfa10057>;
+                                display = <&display>;
+                                status = "okay";
+
+                                display: display {
+                                        bits-per-pixel = <32>;
+                                        bus-width = <18>;
+
+                                        display-timings {
+                                                native-mode = <&timing0>;
+                                                timing0: timing0 {
+                                                        clock-frequency = <30000000>;
+                                                        hactive = <480>;
+                                                        vactive = <800>;
+                                                        hfront-porch = <12>;
+                                                        hback-porch = <2>;
+                                                        vfront-porch = <5>;
+                                                        vback-porch = <3>;
+                                                        hsync-len = <2>;
+                                                        vsync-len = <2>;
+                                                        hsync-active = <0>;
+                                                        vsync-active = <0>;
+                                                        de-active = <1>;
+                                                        pixelclk-active = <1>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        lradc@80050000 {
+                                fsl,lradc-touchscreen-wires = <4>;
+                                status = "okay";
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm3_pins_b>;
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@8005a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c1_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        pinctrl-0 = <&usbphy1_pins_a>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio0 7 1>;
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio2 21 0>;
+                        phy-reset-duration = <100>;
+                        status = "okay";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 5aa44e05c9f5..880df2f13be8 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -220,7 +220,19 @@
 
                         auart0: serial@8006a000 {
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&auart0_2pins_a>;
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart2: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart2_2pins_b>;
                                 status = "okay";
                         };
                 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 600f7cb51f3e..6a8acb01b1d3 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -32,8 +32,12 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
@@ -330,6 +334,17 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart2_2pins_b: auart2-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3080 /* MX28_PAD_AUART2_RX__AUART2_RX */
+                                                0x3090 /* MX28_PAD_AUART2_TX__AUART2_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 auart3_pins_a: auart3@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -354,6 +369,28 @@
                                         fsl,pull-up = <0>;
                                 };
 
+                                auart3_2pins_b: auart3-2pins@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+                                                0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart4_2pins_a: auart4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2181 /* MX28_PAD_SSP3_SCK__AUART4_TX */
+                                                0x2191 /* MX28_PAD_SSP3_MOSI__AUART4_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
                                 mac0_pins_a: mac0@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -669,7 +706,7 @@
                         };
 
                         digctl@8001c000 {
-                                compatible = "fsl,imx28-digctl";
+                                compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
                                 reg = <0x8001c000 0x2000>;
                                 interrupts = <89>;
                                 status = "disabled";
@@ -699,7 +736,7 @@
                         dcp@80028000 {
                                 reg = <0x80028000 0x2000>;
                                 interrupts = <52 53 54>;
-                                status = "disabled";
+                                compatible = "fsl-dcp";
                         };
 
                         pxp@8002a000 {
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 2bcf6981d490..8f7f9ac0b989 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -45,6 +45,13 @@
         status = "okay";
 };
 
+&nfc {
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
+
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3_2>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 53fdde69bbf4..25764b505a61 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -175,10 +175,20 @@
                                 };
                         };
 
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
                         usbotg: usb@73f80000 {
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80000 0x0200>;
                                 interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                 status = "disabled";
                         };
 
@@ -186,6 +196,8 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80200 0x0200>;
                                 interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
                                 status = "disabled";
                         };
 
@@ -193,6 +205,8 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80400 0x0200>;
                                 interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -200,9 +214,18 @@
                                 compatible = "fsl,imx51-usb", "fsl,imx27-usb";
                                 reg = <0x73f80600 0x0200>;
                                 interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@73f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx51-usbmisc";
+                                reg = <0x73f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
+
                         gpio1: gpio@73f84000 {
                                 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f84000 0x4000>;
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
new file mode 100644
index 000000000000..7d304d02ed38
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -0,0 +1,259 @@
+/*
+ * Copyright (C) 2013 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx53.dtsi"
+
+/ {
+        model = "DENX M53EVK";
+        compatible = "denx,imx53-m53evk", "fsl,imx53";
+
+        memory {
+                reg = <0x70000000 0x20000000>;
+        };
+
+        soc {
+                display@di1 {
+                        compatible = "fsl,imx-parallel-display";
+                        crtcs = <&ipu 1>;
+                        interface-pix-fmt = "bgr666";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_ipu_disp2_1>;
+
+                        display-timings {
+                                800x480p60 {
+                                        native-mode;
+                                        clock-frequency = <31500000>;
+                                        hactive = <800>;
+                                        vactive = <480>;
+                                        hfront-porch = <40>;
+                                        hback-porch = <88>;
+                                        hsync-len = <128>;
+                                        vback-porch = <33>;
+                                        vfront-porch = <9>;
+                                        vsync-len = <3>;
+                                        vsync-active = <1>;
+                                };
+                        };
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 3000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pin_gpio>;
+
+                user1 {
+                        label = "user1";
+                        gpios = <&gpio2 8 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                user2 {
+                        label = "user2";
+                        gpios = <&gpio2 9 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p2v: 3p2v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P2V";
+                        regulator-min-microvolt = <3200000>;
+                        regulator-max-microvolt = <3200000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "fsl,imx53-m53evk-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-m53evk-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "LINE_IN", "Line In Jack",
+                        "Headphone Jack", "HP_OUT",
+                        "Ext Spk", "LINE_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <4>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_3>;
+        status = "okay";
+};
+
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "okay";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_1>;
+        cd-gpios = <&gpio1 1 0>;
+        wp-gpios = <&gpio1 9 0>;
+        status = "okay";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2_2>;
+        clock-frequency = <400000>;
+        status = "okay";
+
+        stmpe610@41 {
+                compatible = "st,stmpe610";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x41>;
+                id = <0>;
+                blocks = <0x5>;
+                interrupts = <6 0x0>;
+                interrupt-parent = <&gpio7>;
+                irq-trigger = <0x1>;
+
+                stmpe_touchscreen {
+                        compatible = "stmpe,ts";
+                        reg = <0>;
+                        ts,sample-time = <4>;
+                        ts,mod-12b = <1>;
+                        ts,ref-sel = <0>;
+                        ts,adc-freq = <1>;
+                        ts,ave-ctrl = <3>;
+                        ts,touch-det-delay = <3>;
+                        ts,settling = <4>;
+                        ts,fraction-z = <7>;
+                        ts,i-drive = <1>;
+                };
+        };
+
+        eeprom: eeprom@50 {
+                compatible = "atmel,24c128";
+                reg = <0x50>;
+                pagesize = <32>;
+        };
+
+        rtc: rtc@68 {
+                compatible = "stm,m41t62";
+                reg = <0x68>;
+        };
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_1>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK       0x80000000
+                                MX53_PAD_EIM_EB3__GPIO2_31              0x80000000
+                                MX53_PAD_PATA_DA_0__GPIO7_6             0x80000000
+                                MX53_PAD_DISP0_DAT8__PWM1_PWMO          0x5
+
+                        >;
+                };
+
+                led_pin_gpio: led_gpio@0 {
+                        fsl,pins = <
+                                MX53_PAD_PATA_DATA8__GPIO2_8            0x80000000
+                                MX53_PAD_PATA_DATA9__GPIO2_9            0x80000000
+                        >;
+                };
+        };
+};
+
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand_1>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        status = "okay";
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1_1>;
+        status = "okay";
+};
+
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>;
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_1>;
+        status = "okay";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 445a01119cc5..aaa33bc99f78 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -16,27 +16,81 @@
 / {
         model = "TQ MBa53 starter kit";
         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
+
+        reg_backlight: fixed@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "lcd-supply";
+                gpio = <&gpio2 5 0>;
+                startup-delay-us = <5000>;
+                enable-active-low;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm2 0 50000 0 0>;
+                brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
+                default-brightness-level = <10>;
+                enable-gpios = <&gpio7 7 0>;
+                power-supply = <&reg_backlight>;
+        };
+
+        disp1: display@disp1 {
+                compatible = "fsl,imx-parallel-display";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_disp1_1>;
+                crtcs = <&ipu 1>;
+                interface-pix-fmt = "rgb24";
+                status = "disabled";
+        };
+
+        reg_3p2v: 3p2v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P2V";
+                regulator-min-microvolt = <3200000>;
+                regulator-max-microvolt = <3200000>;
+                regulator-always-on;
+        };
+
+        sound {
+                compatible = "tq,imx53-mba53-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx53-mba53-sgtl5000";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <2>;
+                mux-ext-port = <5>;
+        };
+};
+
+&ldb {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lvds1_1>;
+        status = "disabled";
 };
 
 &iomuxc {
         lvds1 {
                 pinctrl_lvds1_1: lvds1-grp1 {
                         fsl,pins = <
-                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
-                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
-                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
-                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
-                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
+                                MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
+                                MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
+                                MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
+                                MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
+                                MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
                         >;
                 };
 
                 pinctrl_lvds1_2: lvds1-grp2 {
                         fsl,pins = <
-                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
-                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
-                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
-                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
-                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
+                                MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
+                                MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
+                                MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
+                                MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
+                                MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
                         >;
                 };
         };
@@ -44,33 +98,44 @@
         disp1 {
                 pinctrl_disp1_1: disp1-grp1 {
                         fsl,pins = <
-                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x10000 /* DISP1_DRDY */
-                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x10000 /* DISP1_HSYNC */
-                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x10000 /* DISP1_VSYNC */
-                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
-                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
-                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
-                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
-                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
-                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
-                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
-                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
-                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
-                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
-                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
-                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
-                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
-                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
-                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x10000
-                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x10000
-                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x10000
-                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x10000
-                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x10000
-                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x10000
-                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x10000
-                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x10000
-                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x10000
-                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x10000
+                                MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
+                                MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
+                                MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
+                                MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
+                                MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
+                                MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
+                                MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
+                                MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
+                                MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
+                                MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
+                                MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
+                                MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
+                                MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
+                                MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
+                                MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
+                                MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
+                                MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
+                                MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
+                                MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
+                                MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
+                                MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
+                                MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
+                                MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
+                                MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
+                                MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
+                                MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
+                                MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
+                                MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
+                        >;
+                };
+        };
+
+        tve {
+                pinctrl_vga_sync_1: vgasync-grp1 {
+                        fsl,pins = <
+                                /* VGA_VSYNC, HSYNC with max drive strength */
+                                MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
+                                MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
                         >;
                 };
         };
@@ -80,16 +145,27 @@
         status = "okay";
 };
 
+&audmux {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+};
+
 &i2c2 {
         codec: sgtl5000@a {
                 compatible = "fsl,sgtl5000";
                 reg = <0x0a>;
+                clocks = <&clks 150>;
+                VDDA-supply = <&reg_3p2v>;
+                VDDIO-supply = <&reg_3p2v>;
         };
 
         expander: pca9554@20 {
                 compatible = "pca9554";
                 reg = <0x20>;
                 interrupts = <109>;
+                #gpio-cells = <2>;
+                gpio-controller;
         };
 
         sensor2: lm75@49 {
@@ -99,6 +175,7 @@
 };
 
 &fec {
+        phy-reset-gpios = <&gpio7 6 0>;
         status = "okay";
 };
 
@@ -114,10 +191,24 @@
         status = "okay";
 };
 
+&usbotg {
+        dr_mode = "host";
+        status = "okay";
+};
+
+&usbh1 {
+        status = "okay";
+};
+
 &uart1 {
         status = "okay";
 };
 
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
 &uart2 {
         status = "okay";
 };
@@ -133,3 +224,13 @@
 &i2c3 {
         status = "okay";
 };
+
+&tve {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_vga_sync_1>;
+        ddc = <&i2c3>;
+        fsl,tve-mode = "vga";
+        fsl,hsync-pin = <4>;
+        fsl,vsync-pin = <6>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 8f0e9ae0e3e6..512a1f608253 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -21,6 +21,33 @@
                 reg = <0x70000000 0x40000000>;
         };
 
+        display@di0 {
+                compatible = "fsl,imx-parallel-display";
+                crtcs = <&ipu 0>;
+                interface-pix-fmt = "rgb565";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_ipu_disp0_1>;
+                status = "disabled";
+                display-timings {
+                        claawvga {
+                                native-mode;
+                                clock-frequency = <27000000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <40>;
+                                hfront-porch = <60>;
+                                vback-porch = <10>;
+                                vfront-porch = <10>;
+                                hsync-len = <20>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
@@ -147,6 +174,7 @@
                 reg = <0x0a>;
                 VDDA-supply = <&reg_3p2v>;
                 VDDIO-supply = <&reg_3p2v>;
+                clocks = <&clks 150>;
         };
 };
 
@@ -268,3 +296,11 @@
         phy-reset-gpios = <&gpio7 6 0>;
         status = "okay";
 };
+
+&usbh1 {
+       status = "okay";
+};
+
+&usbotg {
+       status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 38bed3ed7c1a..abd72af545bf 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -35,7 +35,9 @@
 
 &esdhc2 {
         pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        pinctrl-0 = <&pinctrl_esdhc2_1>,
+                    <&pinctrl_tqma53_esdhc2_2>;
+        vmmc-supply = <&reg_3p3v>;
         wp-gpios = <&gpio1 2 0>;
         cd-gpios = <&gpio1 4 0>;
         status = "disabled";
@@ -69,14 +71,22 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
 
+        esdhc2_2 {
+                pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
+                        fsl,pins = <
+                                MX53_PAD_GPIO_4__GPIO1_4        0x80000000 /* SD2_CD */
+                                MX53_PAD_GPIO_2__GPIO1_2        0x80000000 /* SD2_WP */
+                        >;
+                };
+        };
+
         i2s {
                 pinctrl_i2s_1: i2s-grp1 {
                         fsl,pins = <
-                                 MX53_PAD_GPIO_19__GPIO4_5           0x10000 /* I2S_MCLK */
-                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x10000 /* I2S_SCLK */
-                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x10000 /* I2S_DOUT */
-                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
-                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x10000 /* I2S_DIN */
+                                 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC  0x80000000 /* I2S_SCLK */
+                                 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD  0x80000000 /* I2S_DOUT */
+                                 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
+                                 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000 /* I2S_DIN */
                         >;
                 };
         };
@@ -84,16 +94,17 @@
         hog {
                 pinctrl_hog: hoggrp {
                         fsl,pins = <
-                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6  0x10000 /* VSYNC */
-                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
-                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x10000 /* LCD_BLT_EN */
-                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x10000 /* LCD_RESET */
-                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x10000 /* LCD_POWER */
-                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x10000 /* PMIC_INT */
-                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x10000 /* CSI_RST */
-                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x10000 /* CSI_PWDN */
-                                 MX53_PAD_GPIO_0__GPIO1_0        0x10000 /* SYSTEM_DOWN */
-                                 MX53_PAD_GPIO_3__GPIO1_3        0x10000
+                                 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
+                                 MX53_PAD_PATA_DA_1__GPIO7_7     0x80000000 /* LCD_BLT_EN */
+                                 MX53_PAD_PATA_DA_2__GPIO7_8     0x80000000 /* LCD_RESET */
+                                 MX53_PAD_PATA_DATA5__GPIO2_5    0x80000000 /* LCD_POWER */
+                                 MX53_PAD_PATA_DATA6__GPIO2_6    0x80000000 /* PMIC_INT */
+                                 MX53_PAD_PATA_DATA14__GPIO2_14  0x80000000 /* CSI_RST */
+                                 MX53_PAD_PATA_DATA15__GPIO2_15  0x80000000 /* CSI_PWDN */
+                                 MX53_PAD_GPIO_19__GPIO4_5       0x80000000 /* #SYSTEM_DOWN */
+                                 MX53_PAD_GPIO_3__GPIO1_3        0x80000000
+                                 MX53_PAD_PATA_DA_0__GPIO7_6     0x80000000 /* #PHY_RESET */
+                                 MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000 /* LCD_CONTRAST */
                         >;
                 };
         };
@@ -149,7 +160,7 @@
                 reg = <0x8>;
                 fsl,mc13xxx-uses-rtc;
                 interrupt-parent = <&gpio2>;
-                interrupts = <6 8>; /* PDATA_DATA6, low active */
+                interrupts = <6 4>; /* PATA_DATA6, active high */
         };
 
         sensor1: lm75@48 {
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
new file mode 100644
index 000000000000..f494766700a3
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "imx53.dtsi"
+
+/ {
+        model = "Ka-Ro TX53";
+        compatible = "karo,tx53", "fsl,imx53";
+
+        memory {
+                reg = <0x70000000 0x40000000>; /* Up to 1GiB */
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
+
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1_2>;
+        status = "disabled";
+};
+
+&can2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can2_1>;
+        status = "disabled";
+};
+
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_2>;
+        status = "disabled";
+};
+
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1_2>;
+        status = "disabled";
+};
+
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2_1>;
+        status = "disabled";
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "disabled";
+};
+
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3_2>;
+        status = "disabled";
+};
+
+&owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire_1>;
+        status = "disabled";
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2_1>;
+        status = "disabled";
+};
+
+&ssi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_1>;
+        status = "disabled";
+};
+
+&ssi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_2>,
+                    <&pinctrl_uart1_3>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2_2>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3_1>;
+        fsl,uart-has-rtscts;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index eb83aa039b8b..3895fbba8fce 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -27,6 +27,9 @@
                 gpio4 = &gpio5;
                 gpio5 = &gpio6;
                 gpio6 = &gpio7;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -163,10 +166,27 @@
                                 };
                         };
 
+                        usbphy0: usbphy@0 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 124>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@1 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks 125>;
+                                clock-names = "main_clk";
+                                status = "okay";
+                        };
+
                         usbotg: usb@53f80000 {
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80000 0x0200>;
                                 interrupts = <18>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                 status = "disabled";
                         };
 
@@ -174,6 +194,9 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80200 0x0200>;
                                 interrupts = <14>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                fsl,usbphy = <&usbphy1>;
                                 status = "disabled";
                         };
 
@@ -181,6 +204,8 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80400 0x0200>;
                                 interrupts = <16>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 2>;
                                 status = "disabled";
                         };
 
@@ -188,9 +213,18 @@
                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
                                 reg = <0x53f80600 0x0200>;
                                 interrupts = <17>;
+                                clocks = <&clks 108>;
+                                fsl,usbmisc = <&usbmisc 3>;
                                 status = "disabled";
                         };
 
+                        usbmisc: usbmisc@53f80800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx53-usbmisc";
+                                reg = <0x53f80800 0x200>;
+                                clocks = <&clks 108>;
+                        };
+
                         gpio1: gpio@53f84000 {
                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f84000 0x4000>;
@@ -267,6 +301,24 @@
                                                         MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD  0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_audmux_2: audmuxgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC     0x80000000
+                                                        MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD     0x80000000
+                                                        MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS    0x80000000
+                                                        MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD     0x80000000
+                                                >;
+                                        };
+
+                                        pinctrl_audmux_3: audmuxgrp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC     0x80000000
+                                                        MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD     0x80000000
+                                                        MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS    0x80000000
+                                                        MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 fec {
@@ -284,6 +336,29 @@
                                                         MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_fec_2: fecgrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_FEC_MDC__FEC_MDC        0x80000000
+                                                        MX53_PAD_FEC_MDIO__FEC_MDIO      0x80000000
+                                                        MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
+                                                        MX53_PAD_FEC_RX_ER__FEC_RX_ER    0x80000000
+                                                        MX53_PAD_FEC_CRS_DV__FEC_RX_DV   0x80000000
+                                                        MX53_PAD_FEC_RXD1__FEC_RDATA_1   0x80000000
+                                                        MX53_PAD_FEC_RXD0__FEC_RDATA_0   0x80000000
+                                                        MX53_PAD_FEC_TX_EN__FEC_TX_EN    0x80000000
+                                                        MX53_PAD_FEC_TXD1__FEC_TDATA_1   0x80000000
+                                                        MX53_PAD_FEC_TXD0__FEC_TDATA_0   0x80000000
+                                                        MX53_PAD_KEY_ROW1__FEC_COL       0x80000000
+                                                        MX53_PAD_KEY_COL3__FEC_CRS       0x80000000
+                                                        MX53_PAD_KEY_COL2__FEC_RDATA_2   0x80000000
+                                                        MX53_PAD_KEY_COL0__FEC_RDATA_3   0x80000000
+                                                        MX53_PAD_KEY_COL1__FEC_RX_CLK    0x80000000
+                                                        MX53_PAD_KEY_ROW2__FEC_TDATA_2   0x80000000
+                                                        MX53_PAD_GPIO_19__FEC_TDATA_3    0x80000000
+                                                        MX53_PAD_KEY_ROW0__FEC_TX_ER     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 csi {
@@ -312,6 +387,22 @@
                                                         MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
                                                 >;
                                         };
+
+                                        pinctrl_csi_2: csigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC     0x1d5
+                                                        MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC      0x1d5
+                                                        MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK   0x1d5
+                                                        MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19      0x1d5
+                                                        MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18      0x1d5
+                                                        MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17      0x1d5
+                                                        MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16      0x1d5
+                                                        MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15      0x1d5
+                                                        MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14      0x1d5
+                                                        MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13      0x1d5
+                                                        MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12      0x1d5
+                                                >;
+                                        };
                                 };
 
                                 cspi {
@@ -322,6 +413,14 @@
                                                         MX53_PAD_SD1_CLK__CSPI_SCLK   0x1d5
                                                 >;
                                         };
+
+                                        pinctrl_cspi_2: cspigrp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
+                                                        MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
+                                                        MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
+                                                >;
+                                        };
                                 };
 
                                 ecspi1 {
@@ -332,6 +431,27 @@
                                                         MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_ecspi1_2: ecspi1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_19__ECSPI1_RDY    0x80000000
+                                                        MX53_PAD_EIM_EB2__ECSPI1_SS0    0x80000000
+                                                        MX53_PAD_EIM_D16__ECSPI1_SCLK   0x80000000
+                                                        MX53_PAD_EIM_D17__ECSPI1_MISO   0x80000000
+                                                        MX53_PAD_EIM_D18__ECSPI1_MOSI   0x80000000
+                                                        MX53_PAD_EIM_D19__ECSPI1_SS1    0x80000000
+                                                >;
+                                        };
+                                };
+
+                                ecspi2 {
+                                        pinctrl_ecspi2_1: ecspi2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_OE__ECSPI2_MISO  0x80000000
+                                                        MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
+                                                        MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
+                                                >;
+                                        };
                                 };
 
                                 esdhc1 {
@@ -406,6 +526,13 @@
                                                         MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
                                                 >;
                                         };
+
+                                        pinctrl_can1_3: can1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_7__CAN1_TXCAN     0x80000000
+                                                        MX53_PAD_GPIO_8__CAN1_RXCAN     0x80000000
+                                                >;
+                                        };
                                 };
 
                                 can2 {
@@ -424,6 +551,13 @@
                                                         MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
                                                 >;
                                         };
+
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D21__I2C1_SCL      0xc0000000
+                                                        MX53_PAD_EIM_D28__I2C1_SDA      0xc0000000
+                                                >;
+                                        };
                                 };
 
                                 i2c2 {
@@ -433,6 +567,13 @@
                                                         MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
                                                 >;
                                         };
+
+                                        pinctrl_i2c2_2: i2c2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_D16__I2C2_SDA      0xc0000000
+                                                        MX53_PAD_EIM_EB2__I2C2_SCL      0xc0000000
+                                                >;
+                                        };
                                 };
 
                                 i2c3 {
@@ -444,6 +585,119 @@
                                         };
                                 };
 
+                                ipu_disp0 {
+                                        pinctrl_ipu_disp0_1: ipudisp0grp-1 {
+                                                fsl,pins = <
+                                                MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
+                                                MX53_PAD_DI0_PIN15__IPU_DI0_PIN15               0x5
+                                                MX53_PAD_DI0_PIN2__IPU_DI0_PIN2         0x5
+                                                MX53_PAD_DI0_PIN3__IPU_DI0_PIN3                 0x5
+                                                MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0            0x5
+                                                MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1            0x5
+                                                MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2            0x5
+                                                MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3            0x5
+                                                MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4            0x5
+                                                MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5            0x5
+                                                MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6            0x5
+                                                MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7            0x5
+                                                MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8            0x5
+                                                MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9            0x5
+                                                MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10          0x5
+                                                MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11          0x5
+                                                MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12          0x5
+                                                MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13          0x5
+                                                MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14          0x5
+                                                MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15          0x5
+                                                MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16          0x5
+                                                MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17          0x5
+                                                MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18          0x5
+                                                MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19          0x5
+                                                MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20          0x5
+                                                MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21          0x5
+                                                MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22          0x5
+                                                MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23          0x5
+                                                >;
+                                        };
+                                };
+
+                                ipu_disp1 {
+                                        pinctrl_ipu_disp1_1: ipudisp1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0       0x5
+                                                        MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1       0x5
+                                                        MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2       0x5
+                                                        MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3       0x5
+                                                        MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4       0x5
+                                                        MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5       0x5
+                                                        MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6       0x5
+                                                        MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7       0x5
+                                                        MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8       0x5
+                                                        MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9       0x5
+                                                        MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10      0x5
+                                                        MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11      0x5
+                                                        MX53_PAD_EIM_A17__IPU_DISP1_DAT_12      0x5
+                                                        MX53_PAD_EIM_A18__IPU_DISP1_DAT_13      0x5
+                                                        MX53_PAD_EIM_A19__IPU_DISP1_DAT_14      0x5
+                                                        MX53_PAD_EIM_A20__IPU_DISP1_DAT_15      0x5
+                                                        MX53_PAD_EIM_A21__IPU_DISP1_DAT_16      0x5
+                                                        MX53_PAD_EIM_A22__IPU_DISP1_DAT_17      0x5
+                                                        MX53_PAD_EIM_A23__IPU_DISP1_DAT_18      0x5
+                                                        MX53_PAD_EIM_A24__IPU_DISP1_DAT_19      0x5
+                                                        MX53_PAD_EIM_D31__IPU_DISP1_DAT_20      0x5
+                                                        MX53_PAD_EIM_D30__IPU_DISP1_DAT_21      0x5
+                                                        MX53_PAD_EIM_D26__IPU_DISP1_DAT_22      0x5
+                                                        MX53_PAD_EIM_D27__IPU_DISP1_DAT_23      0x5
+                                                        MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK      0x5
+                                                        MX53_PAD_EIM_DA13__IPU_DI1_D0_CS        0x5
+                                                        MX53_PAD_EIM_DA14__IPU_DI1_D1_CS        0x5
+                                                        MX53_PAD_EIM_DA15__IPU_DI1_PIN1         0x5
+                                                        MX53_PAD_EIM_DA11__IPU_DI1_PIN2         0x5
+                                                        MX53_PAD_EIM_DA12__IPU_DI1_PIN3         0x5
+                                                        MX53_PAD_EIM_A25__IPU_DI1_PIN12         0x5
+                                                        MX53_PAD_EIM_DA10__IPU_DI1_PIN15        0x5
+                                                >;
+                                        };
+                                };
+
+                                ipu_disp2 {
+                                        pinctrl_ipu_disp2_1: ipudisp2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0     0x80000000
+                                                        MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1     0x80000000
+                                                        MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2     0x80000000
+                                                        MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3     0x80000000
+                                                        MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK     0x80000000
+                                                        MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0     0x80000000
+                                                        MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1     0x80000000
+                                                        MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2     0x80000000
+                                                        MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3     0x80000000
+                                                        MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK     0x80000000
+                                                >;
+                                        };
+                                };
+
+                                nand {
+                                        pinctrl_nand_1: nandgrp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B     0x4
+                                                        MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B     0x4
+                                                        MX53_PAD_NANDF_CLE__EMI_NANDF_CLE       0x4
+                                                        MX53_PAD_NANDF_ALE__EMI_NANDF_ALE       0x4
+                                                        MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B     0xe0
+                                                        MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0      0xe0
+                                                        MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0      0x4
+                                                        MX53_PAD_PATA_DATA0__EMI_NANDF_D_0      0xa4
+                                                        MX53_PAD_PATA_DATA1__EMI_NANDF_D_1      0xa4
+                                                        MX53_PAD_PATA_DATA2__EMI_NANDF_D_2      0xa4
+                                                        MX53_PAD_PATA_DATA3__EMI_NANDF_D_3      0xa4
+                                                        MX53_PAD_PATA_DATA4__EMI_NANDF_D_4      0xa4
+                                                        MX53_PAD_PATA_DATA5__EMI_NANDF_D_5      0xa4
+                                                        MX53_PAD_PATA_DATA6__EMI_NANDF_D_6      0xa4
+                                                        MX53_PAD_PATA_DATA7__EMI_NANDF_D_7      0xa4
+                                                >;
+                                        };
+                                };
+
                                 owire {
                                         pinctrl_owire_1: owiregrp-1 {
                                                 fsl,pins = <
@@ -452,6 +706,22 @@
                                         };
                                 };
 
+                                pwm1 {
+                                        pinctrl_pwm1_1: pwm1grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_DISP0_DAT8__PWM1_PWMO  0x5
+                                                >;
+                                        };
+                                };
+
+                                pwm2 {
+                                        pinctrl_pwm2_1: pwm2grp-1 {
+                                                fsl,pins = <
+                                                        MX53_PAD_GPIO_1__PWM2_PWMO      0x80000000
+                                                >;
+                                        };
+                                };
+
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
@@ -466,6 +736,13 @@
                                                         MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
                                                 >;
                                         };
+
+                                        pinctrl_uart1_3: uart1grp-3 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
+                                                        MX53_PAD_PATA_IORDY__UART1_RTS   0x1c5
+                                                >;
+                                        };
                                 };
 
                                 uart2 {
@@ -475,6 +752,15 @@
                                                         MX53_PAD_PATA_DMARQ__UART2_TXD_MUX     0x1c5
                                                 >;
                                         };
+
+                                        pinctrl_uart2_2: uart2grp-2 {
+                                                fsl,pins = <
+                                                        MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX  0x1c5
+                                                        MX53_PAD_PATA_DMARQ__UART2_TXD_MUX      0x1c5
+                                                        MX53_PAD_PATA_DIOR__UART2_RTS           0x1c5
+                                                        MX53_PAD_PATA_INTRQ__UART2_CTS          0x1c5
+                                                >;
+                                        };
                                 };
 
                                 uart3 {
@@ -513,7 +799,6 @@
                                                 >;
                                         };
                                 };
-
                         };
 
                         gpr: iomuxc-gpr@53fa8000 {
@@ -781,6 +1066,16 @@
                                 clock-names = "ipg", "ahb", "ptp";
                                 status = "disabled";
                         };
+
+                        tve: tve@63ff0000 {
+                                compatible = "fsl,imx53-tve";
+                                reg = <0x63ff0000 0x1000>;
+                                interrupts = <92>;
+                                clocks = <&clks 69>, <&clks 116>;
+                                clock-names = "tve", "di_sel";
+                                crtcs = <&ipu 1>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 7adcec360213..95da71185a4a 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -28,4 +28,12 @@
                         >;
                 };
         };
+
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6DL_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 7efb05db4783..8989df2b89e5 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -29,6 +29,7 @@
                                 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6DL_PAD_GPIO_0__CCM_CLKO1    0x130b0
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5bcdf3a90bb3..2b3ecd679350 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -18,12 +18,14 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
@@ -35,6 +37,27 @@
                                 compatible = "fsl,imx6dl-iomuxc";
                                 reg = <0x020e0000 0x4000>;
 
+                                audmux {
+                                        pinctrl_audmux_2: audmux-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT7__AUD3_RXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT4__AUD3_TXC  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT5__AUD3_TXD  0x80000000
+                                                        MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+                                                >;
+                                        };
+                                };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                                                        MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                                                        MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                                                >;
+                                        };
+                                };
+
                                 enet {
                                         pinctrl_enet_1: enetgrp-1 {
                                                 fsl,pins = <
@@ -78,6 +101,39 @@
                                         };
                                 };
 
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
+                                                        MX6DL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
+                                                        MX6DL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
+                                                        MX6DL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
+                                                        MX6DL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
+                                                        MX6DL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
+                                                        MX6DL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
+                                                        MX6DL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
+                                                        MX6DL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
+                                                        MX6DL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
+                                                        MX6DL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
+                                                        MX6DL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
+                                                        MX6DL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
+                                                        MX6DL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
+                                                        MX6DL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
+                                                        MX6DL_PAD_SD4_DAT0__NAND_DQS      0x00b1
+                                                >;
+                                        };
+                                };
+
+                                i2c1 {
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
+                                };
+
                                 uart1 {
                                         pinctrl_uart1_1: uart1grp-1 {
                                                 fsl,pins = <
@@ -149,6 +205,64 @@
                                         };
                                 };
 
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+
+                                        pinctrl_weim_nor_1: weim_norgrp-1 {
+                                                fsl,pins = <
+                                                        MX6DL_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6DL_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6DL_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6DL_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6DL_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6DL_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6DL_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6DL_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6DL_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6DL_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6DL_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6DL_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6DL_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6DL_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6DL_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6DL_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6DL_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6DL_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+
+                                };
 
                         };
 
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
new file mode 100644
index 000000000000..7d37ec60d58d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+#include "imx6q-phytec-pfla02.dtsi"
+
+/ {
+        model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
+        compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
+};
+
+&fec {
+        status = "okay";
+};
+
+&uart4 {
+        status = "okay";
+};
+
+&usdhc2 {
+        status = "okay";
+};
+
+&usdhc3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..f5e1981025ed
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include "imx6q.dtsi"
+
+/ {
+        model = "Phytec phyFLEX-i.MX6 Ouad";
+        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D23__GPIO3_IO23    0x80000000
+                        >;
+                };
+        };
+
+        pfla02 {
+                pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
+                        fsl,pins = <
+                                MX6Q_PAD_ENET_RXD0__GPIO1_IO27  0x80000000
+                                MX6Q_PAD_ENET_TXD1__GPIO1_IO29  0x80000000
+                        >;
+                };
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet_3>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 0>;
+        status = "disabled";
+};
+
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4_1>;
+        status = "disabled";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        status = "disabled";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_2
+                     &pinctrl_usdhc3_pfla02>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 49d6f2831ec9..09a75807bc6d 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -32,4 +32,12 @@
                         >;
                 };
         };
+
+        ecspi1 {
+                pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
+                        fsl,pins = <
+                                MX6Q_PAD_EIM_D19__GPIO3_IO19  0x80000000
+                        >;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 442051350225..0038228c508c 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -33,6 +33,7 @@
                                 MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
                                 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
                                 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
+                                MX6Q_PAD_GPIO_0__CCM_CLKO1    0x130b0
                         >;
                 };
         };
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 21e675848bd1..ba09dc32324e 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -18,6 +18,7 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                         operating-points = <
@@ -39,18 +40,21 @@
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@2 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <2>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@3 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <3>;
                         next-level-cache = <&L2>;
                 };
@@ -157,6 +161,27 @@
                                                         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
                                                 >;
                                         };
+
+                                        pinctrl_enet_3: enetgrp-3 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                        MX6Q_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                        MX6Q_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                                                        MX6Q_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
+                                                        MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+                                                        MX6Q_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+                                                >;
+                                        };
                                 };
 
                                 gpmi-nand {
@@ -168,8 +193,6 @@
                                                         MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
                                                         MX6Q_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
                                                         MX6Q_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS2__NAND_CE2_B   0xb0b1
-                                                        MX6Q_PAD_NANDF_CS3__NAND_CE3_B   0xb0b1
                                                         MX6Q_PAD_SD4_CMD__NAND_RE_B      0xb0b1
                                                         MX6Q_PAD_SD4_CLK__NAND_WE_B      0xb0b1
                                                         MX6Q_PAD_NANDF_D0__NAND_DATA00   0xb0b1
@@ -192,6 +215,13 @@
                                                         MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
                                                 >;
                                         };
+
+                                        pinctrl_i2c1_2: i2c1grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+                                                        MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+                                                >;
+                                        };
                                 };
 
                                 i2c2 {
@@ -268,6 +298,17 @@
                                                         MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
                                                 >;
                                         };
+
+                                        pinctrl_usdhc2_2: usdhc2grp-2 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6Q_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
                                 };
 
                                 usdhc3 {
@@ -325,6 +366,65 @@
                                                 >;
                                         };
                                 };
+
+                                weim {
+                                        pinctrl_weim_cs0_1: weim_cs0grp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_CS0__EIM_CS0_B   0xb0b1
+                                                >;
+                                        };
+
+                                        pinctrl_weim_nor_1: weimnorgrp-1 {
+                                                fsl,pins = <
+                                                        MX6Q_PAD_EIM_OE__EIM_OE_B     0xb0b1
+                                                        MX6Q_PAD_EIM_RW__EIM_RW       0xb0b1
+                                                        MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
+                                                        /* data */
+                                                        MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
+                                                        MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
+                                                        MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
+                                                        MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
+                                                        MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
+                                                        MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
+                                                        MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
+                                                        MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
+                                                        MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
+                                                        MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
+                                                        MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
+                                                        MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
+                                                        MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
+                                                        MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
+                                                        MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
+                                                        MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
+                                                        /* address */
+                                                        MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
+                                                        MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
+                                                        MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
+                                                        MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
+                                                        MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
+                                                        MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
+                                                        MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
+                                                        MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
+                                                        MX6Q_PAD_EIM_DA15__EIM_AD15  0xb0b1
+                                                        MX6Q_PAD_EIM_DA14__EIM_AD14  0xb0b1
+                                                        MX6Q_PAD_EIM_DA13__EIM_AD13  0xb0b1
+                                                        MX6Q_PAD_EIM_DA12__EIM_AD12  0xb0b1
+                                                        MX6Q_PAD_EIM_DA11__EIM_AD11  0xb0b1
+                                                        MX6Q_PAD_EIM_DA10__EIM_AD10  0xb0b1
+                                                        MX6Q_PAD_EIM_DA9__EIM_AD09   0xb0b1
+                                                        MX6Q_PAD_EIM_DA8__EIM_AD08   0xb0b1
+                                                        MX6Q_PAD_EIM_DA7__EIM_AD07   0xb0b1
+                                                        MX6Q_PAD_EIM_DA6__EIM_AD06   0xb0b1
+                                                        MX6Q_PAD_EIM_DA5__EIM_AD05   0xb0b1
+                                                        MX6Q_PAD_EIM_DA4__EIM_AD04   0xb0b1
+                                                        MX6Q_PAD_EIM_DA3__EIM_AD03   0xb0b1
+                                                        MX6Q_PAD_EIM_DA2__EIM_AD02   0xb0b1
+                                                        MX6Q_PAD_EIM_DA1__EIM_AD01   0xb0b1
+                                                        MX6Q_PAD_EIM_DA0__EIM_AD00   0xb0b1
+                                                >;
+                                        };
+
+                                };
                         };
                 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 4d237cffcc41..e994011220e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -16,6 +16,22 @@
         };
 };
 
+&ecspi1 {
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio3 19 0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
+        status = "disabled"; /* pin conflict with WEIM NOR */
+
+        flash: m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
 &fec {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet_2>;
@@ -23,6 +39,12 @@
         status = "okay";
 };
 
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+        status = "okay";
+};
+
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4_1>;
@@ -36,3 +58,22 @@
         wp-gpios = <&gpio1 13 0>;
         status = "okay";
 };
+
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x08000000 0x08000000>;
+        status = "disabled"; /* pin conflict with SPI NOR */
+
+        nor@0,0 {
+                compatible = "cfi-flash";
+                reg = <0 0 0x02000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                bank-width = <2>;
+                fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
+                                0x0000c000 0x1404a38e 0x00000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index e21f6a89cf0f..6e5dfdb32416 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -26,6 +26,13 @@
                         gpio = <&gpio3 22 0>;
                         enable-active-high;
                 };
+
+                reg_audio: wm8962_supply {
+                        compatible = "regulator-fixed";
+                        regulator-name = "wm8962-supply";
+                        gpio = <&gpio4 10 0>;
+                        enable-active-high;
+                };
         };
 
         gpio-keys {
@@ -43,6 +50,31 @@
                         linux,code = <114>; /* KEY_VOLUMEDOWN */
                 };
         };
+
+        sound {
+                compatible = "fsl,imx6q-sabresd-wm8962",
+                           "fsl,imx-audio-wm8962";
+                model = "wm8962-audio";
+                ssi-controller = <&ssi2>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "Headphone Jack", "HPOUTL",
+                        "Headphone Jack", "HPOUTR",
+                        "Ext Spk", "SPKOUTL",
+                        "Ext Spk", "SPKOUTR",
+                        "MICBIAS", "AMIC",
+                        "IN3R", "MICBIAS",
+                        "DMIC", "MICBIAS",
+                        "DMICDAT", "DMIC";
+                mux-int-port = <2>;
+                mux-ext-port = <3>;
+        };
+};
+
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux_2>;
+        status = "okay";
 };
 
 &fec {
@@ -52,6 +84,40 @@
         status = "okay";
 };
 
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1_2>;
+        status = "okay";
+
+        codec: wm8962@1a {
+                compatible = "wlf,wm8962";
+                reg = <0x1a>;
+                clocks = <&clks 169>;
+                DCVDD-supply = <&reg_audio>;
+                DBVDD-supply = <&reg_audio>;
+                AVDD-supply = <&reg_audio>;
+                CPVDD-supply = <&reg_audio>;
+                MICVDD-supply = <&reg_audio>;
+                PLLVDD-supply = <&reg_audio>;
+                SPKVDD1-supply = <&reg_audio>;
+                SPKVDD2-supply = <&reg_audio>;
+                gpio-cfg = <
+                        0x0000 /* 0:Default */
+                        0x0000 /* 1:Default */
+                        0x0013 /* 2:FN_DMICCLK */
+                        0x0000 /* 3:Default */
+                        0x8014 /* 4:FN_DMICCDAT */
+                        0x0000 /* 5:Default */
+                >;
+       };
+};
+
+&ssi2 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_1>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 9e8296e4c343..f21d259080fd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -106,6 +106,8 @@
                         interrupts = <0 92 0x04>;
                         cache-unified;
                         cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
                 };
 
                 pmu {
@@ -638,7 +640,7 @@
                                 status = "disabled";
                         };
 
-                        usbmisc: usbmisc: usbmisc@02184800 {
+                        usbmisc: usbmisc@02184800 {
                                 #index-cells = <1>;
                                 compatible = "fsl,imx6q-usbmisc";
                                 reg = <0x02184800 0x200>;
@@ -742,9 +744,11 @@
                                 reg = <0x021b4000 0x4000>;
                         };
 
-                        weim@021b8000 {
+                        weim: weim@021b8000 {
+                                compatible = "fsl,imx6q-weim";
                                 reg = <0x021b8000 0x4000>;
                                 interrupts = <0 14 0x04>;
+                                clocks = <&clks 196>;
                         };
 
                         ocotp@021bc000 {
@@ -752,11 +756,6 @@
                                 reg = <0x021bc000 0x4000>;
                         };
 
-                        ocotp@021c0000 {
-                                reg = <0x021c0000 0x4000>;
-                                interrupts = <0 21 0x04>;
-                        };
-
                         tzasc@021d0000 { /* TZASC1 */
                                 reg = <0x021d0000 0x4000>;
                                 interrupts = <0 108 0x04>;
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
new file mode 100644
index 000000000000..2886a590823d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sl.dtsi"
+
+/ {
+        model = "Freescale i.MX6 SoloLite EVK Board";
+        compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
+
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+};
+
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec_1>;
+        phy-mode = "rmii";
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+
+        hog {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
+                                MX6SL_PAD_KEY_COL7__GPIO4_IO06    0x17059
+                                MX6SL_PAD_SD2_DAT7__GPIO5_IO00    0x17059
+                                MX6SL_PAD_SD2_DAT6__GPIO4_IO29    0x17059
+                                MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
+                        >;
+                };
+        };
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1_1>;
+        bus-width = <8>;
+        cd-gpios = <&gpio4 7 0>;
+        wp-gpios = <&gpio4 6 0>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2_1>;
+        cd-gpios = <&gpio5 0 0>;
+        wp-gpios = <&gpio4 29 0>;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3_1>;
+        cd-gpios = <&gpio3 22 0>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
new file mode 100644
index 000000000000..c5e5da02d7e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -0,0 +1,779 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "skeleton.dtsi"
+#include "imx6sl-pinfunc.h"
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: interrupt-controller@00a01000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-controller;
+                reg = <0x00a01000 0x1000>,
+                      <0x00a00100 0x100>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ckil {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                osc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                L2: l2-cache@00a02000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x00a02000 0x1000>;
+                        interrupts = <0 92 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                        arm,tag-latency = <4 2 3>;
+                        arm,data-latency = <4 2 3>;
+                };
+
+                pmu {
+                        compatible = "arm,cortex-a9-pmu";
+                        interrupts = <0 94 0x04>;
+                };
+
+                aips1: aips-bus@02000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02000000 0x100000>;
+                        ranges;
+
+                        spba: spba-bus@02000000 {
+                                compatible = "fsl,spba-bus", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x02000000 0x40000>;
+                                ranges;
+
+                                spdif: spdif@02004000 {
+                                        reg = <0x02004000 0x4000>;
+                                        interrupts = <0 52 0x04>;
+                                };
+
+                                ecspi1: ecspi@02008000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02008000 0x4000>;
+                                        interrupts = <0 31 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI1>,
+                                                 <&clks IMX6SL_CLK_ECSPI1>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi2: ecspi@0200c000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x0200c000 0x4000>;
+                                        interrupts = <0 32 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI2>,
+                                                 <&clks IMX6SL_CLK_ECSPI2>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi3: ecspi@02010000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02010000 0x4000>;
+                                        interrupts = <0 33 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI3>,
+                                                 <&clks IMX6SL_CLK_ECSPI3>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ecspi4: ecspi@02014000 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
+                                        reg = <0x02014000 0x4000>;
+                                        interrupts = <0 34 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_ECSPI4>,
+                                                 <&clks IMX6SL_CLK_ECSPI4>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart5: serial@02018000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02018000 0x4000>;
+                                        interrupts = <0 30 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart1: serial@02020000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02020000 0x4000>;
+                                        interrupts = <0 26 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart2: serial@02024000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02024000 0x4000>;
+                                        interrupts = <0 27 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                ssi1: ssi@02028000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02028000 0x4000>;
+                                        interrupts = <0 46 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI1>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                ssi2: ssi@0202c000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x0202c000 0x4000>;
+                                        interrupts = <0 47 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI2>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                ssi3: ssi@02030000 {
+                                        compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
+                                        reg = <0x02030000 0x4000>;
+                                        interrupts = <0 48 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_SSI3>;
+                                        fsl,fifo-depth = <15>;
+                                        status = "disabled";
+                                };
+
+                                uart3: serial@02034000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02034000 0x4000>;
+                                        interrupts = <0 28 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+
+                                uart4: serial@02038000 {
+                                        compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+                                        reg = <0x02038000 0x4000>;
+                                        interrupts = <0 29 0x04>;
+                                        clocks = <&clks IMX6SL_CLK_UART>,
+                                                 <&clks IMX6SL_CLK_UART_SERIAL>;
+                                        clock-names = "ipg", "per";
+                                        status = "disabled";
+                                };
+                        };
+
+                        pwm1: pwm@02080000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02080000 0x4000>;
+                                interrupts = <0 83 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM1>,
+                                         <&clks IMX6SL_CLK_PWM1>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm2: pwm@02084000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02084000 0x4000>;
+                                interrupts = <0 84 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM2>,
+                                         <&clks IMX6SL_CLK_PWM2>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm3: pwm@02088000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x02088000 0x4000>;
+                                interrupts = <0 85 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM3>,
+                                         <&clks IMX6SL_CLK_PWM3>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        pwm4: pwm@0208c000 {
+                                #pwm-cells = <2>;
+                                compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
+                                reg = <0x0208c000 0x4000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks IMX6SL_CLK_PWM4>,
+                                         <&clks IMX6SL_CLK_PWM4>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt: gpt@02098000 {
+                                compatible = "fsl,imx6sl-gpt";
+                                reg = <0x02098000 0x4000>;
+                                interrupts = <0 55 0x04>;
+                                clocks = <&clks IMX6SL_CLK_GPT>,
+                                         <&clks IMX6SL_CLK_GPT_SERIAL>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpio1: gpio@0209c000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x0209c000 0x4000>;
+                                interrupts = <0 66 0x04 0 67 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio2: gpio@020a0000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a0000 0x4000>;
+                                interrupts = <0 68 0x04 0 69 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio3: gpio@020a4000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a4000 0x4000>;
+                                interrupts = <0 70 0x04 0 71 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio4: gpio@020a8000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020a8000 0x4000>;
+                                interrupts = <0 72 0x04 0 73 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio5: gpio@020ac000 {
+                                compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
+                                reg = <0x020ac000 0x4000>;
+                                interrupts = <0 74 0x04 0 75 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        kpp: kpp@020b8000 {
+                                reg = <0x020b8000 0x4000>;
+                                interrupts = <0 82 0x04>;
+                        };
+
+                        wdog1: wdog@020bc000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020bc000 0x4000>;
+                                interrupts = <0 80 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                        };
+
+                        wdog2: wdog@020c0000 {
+                                compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
+                                reg = <0x020c0000 0x4000>;
+                                interrupts = <0 81 0x04>;
+                                clocks = <&clks IMX6SL_CLK_DUMMY>;
+                                status = "disabled";
+                        };
+
+                        clks: ccm@020c4000 {
+                                compatible = "fsl,imx6sl-ccm";
+                                reg = <0x020c4000 0x4000>;
+                                interrupts = <0 87 0x04 0 88 0x04>;
+                                #clock-cells = <1>;
+                        };
+
+                        anatop: anatop@020c8000 {
+                                compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
+                                reg = <0x020c8000 0x1000>;
+                                interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+
+                                regulator-1p1@110 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p1";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1375000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x110>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <4>;
+                                        anatop-min-voltage = <800000>;
+                                        anatop-max-voltage = <1375000>;
+                                };
+
+                                regulator-3p0@120 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd3p0";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <3150000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x120>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2625000>;
+                                        anatop-max-voltage = <3400000>;
+                                };
+
+                                regulator-2p5@130 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd2p5";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x130>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <0>;
+                                        anatop-min-voltage = <2100000>;
+                                        anatop-max-voltage = <2850000>;
+                                };
+
+                                reg_arm: regulator-vddcore@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "cpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <0>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <24>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+
+                                reg_pu: regulator-vddpu@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddpu";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <9>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <26>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+
+                                reg_soc: regulator-vddsoc@140 {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vddsoc";
+                                        regulator-min-microvolt = <725000>;
+                                        regulator-max-microvolt = <1450000>;
+                                        regulator-always-on;
+                                        anatop-reg-offset = <0x140>;
+                                        anatop-vol-bit-shift = <18>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-delay-reg-offset = <0x170>;
+                                        anatop-delay-bit-shift = <28>;
+                                        anatop-delay-bit-width = <2>;
+                                        anatop-min-bit-val = <1>;
+                                        anatop-min-voltage = <725000>;
+                                        anatop-max-voltage = <1450000>;
+                                };
+                        };
+
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020c9000 0x1000>;
+                                interrupts = <0 44 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY1>;
+                        };
+
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
+                                reg = <0x020ca000 0x1000>;
+                                interrupts = <0 45 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBPHY2>;
+                        };
+
+                        snvs@020cc000 {
+                                compatible = "fsl,sec-v4.0-mon", "simple-bus";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                ranges = <0 0x020cc000 0x4000>;
+
+                                snvs-rtc-lp@34 {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        reg = <0x34 0x58>;
+                                        interrupts = <0 19 0x04 0 20 0x04>;
+                                };
+                        };
+
+                        epit1: epit@020d0000 {
+                                reg = <0x020d0000 0x4000>;
+                                interrupts = <0 56 0x04>;
+                        };
+
+                        epit2: epit@020d4000 {
+                                reg = <0x020d4000 0x4000>;
+                                interrupts = <0 57 0x04>;
+                        };
+
+                        src: src@020d8000 {
+                                compatible = "fsl,imx6sl-src", "fsl,imx51-src";
+                                reg = <0x020d8000 0x4000>;
+                                interrupts = <0 91 0x04 0 96 0x04>;
+                                #reset-cells = <1>;
+                        };
+
+                        gpc: gpc@020dc000 {
+                                compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
+                                reg = <0x020dc000 0x4000>;
+                                interrupts = <0 89 0x04>;
+                        };
+
+                        iomuxc: iomuxc@020e0000 {
+                                compatible = "fsl,imx6sl-iomuxc";
+                                reg = <0x020e0000 0x4000>;
+
+                                fec {
+                                        pinctrl_fec_1: fecgrp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_FEC_MDC__FEC_MDC         0x1b0b0
+                                                        MX6SL_PAD_FEC_MDIO__FEC_MDIO       0x1b0b0
+                                                        MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV    0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_TX_EN__FEC_TX_EN     0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0   0x1b0b0
+                                                        MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1   0x1b0b0
+                                                        MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+                                                        MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+                                                >;
+                                        };
+                                };
+
+                                usdhc1 {
+                                        pinctrl_usdhc1_1: usdhc1grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD1_CMD__SD1_CMD    0x17059
+                                                        MX6SL_PAD_SD1_CLK__SD1_CLK    0x10059
+                                                        MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+                                                        MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+                                                        MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+                                                        MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+                                                        MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+                                                        MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+                                                        MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+                                                        MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc2 {
+                                        pinctrl_usdhc2_1: usdhc2grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD2_CMD__SD2_CMD    0x17059
+                                                        MX6SL_PAD_SD2_CLK__SD2_CLK    0x10059
+                                                        MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+                                                        MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+                                                        MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+                                                        MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+
+                                usdhc3 {
+                                        pinctrl_usdhc3_1: usdhc3grp-1 {
+                                                fsl,pins = <
+                                                        MX6SL_PAD_SD3_CMD__SD3_CMD    0x17059
+                                                        MX6SL_PAD_SD3_CLK__SD3_CLK    0x10059
+                                                        MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+                                                        MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+                                                        MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+                                                        MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+                                                >;
+                                        };
+                                };
+                        };
+
+                        csi: csi@020e4000 {
+                                reg = <0x020e4000 0x4000>;
+                                interrupts = <0 7 0x04>;
+                        };
+
+                        spdc: spdc@020e8000 {
+                                reg = <0x020e8000 0x4000>;
+                                interrupts = <0 6 0x04>;
+                        };
+
+                        sdma: sdma@020ec000 {
+                                compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
+                                reg = <0x020ec000 0x4000>;
+                                interrupts = <0 2 0x04>;
+                                clocks = <&clks IMX6SL_CLK_SDMA>,
+                                         <&clks IMX6SL_CLK_SDMA>;
+                                clock-names = "ipg", "ahb";
+                                fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
+                        };
+
+                        pxp: pxp@020f0000 {
+                                reg = <0x020f0000 0x4000>;
+                                interrupts = <0 98 0x04>;
+                        };
+
+                        epdc: epdc@020f4000 {
+                                reg = <0x020f4000 0x4000>;
+                                interrupts = <0 97 0x04>;
+                        };
+
+                        lcdif: lcdif@020f8000 {
+                                reg = <0x020f8000 0x4000>;
+                                interrupts = <0 39 0x04>;
+                        };
+
+                        dcp: dcp@020fc000 {
+                                reg = <0x020fc000 0x4000>;
+                                interrupts = <0 99 0x04>;
+                        };
+                };
+
+                aips2: aips-bus@02100000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x02100000 0x100000>;
+                        ranges;
+
+                        usbotg1: usb@02184000 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy1>;
+                                fsl,usbmisc = <&usbmisc 0>;
+                                status = "disabled";
+                        };
+
+                        usbotg2: usb@02184200 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbphy = <&usbphy2>;
+                                fsl,usbmisc = <&usbmisc 1>;
+                                status = "disabled";
+                        };
+
+                        usbh: usb@02184400 {
+                                compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 42 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                                fsl,usbmisc = <&usbmisc 2>;
+                                status = "disabled";
+                        };
+
+                        usbmisc: usbmisc@02184800 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
+                                reg = <0x02184800 0x200>;
+                                clocks = <&clks IMX6SL_CLK_USBOH3>;
+                        };
+
+                        fec: ethernet@02188000 {
+                                compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
+                                reg = <0x02188000 0x4000>;
+                                interrupts = <0 114 0x04>;
+                                clocks = <&clks IMX6SL_CLK_ENET_REF>,
+                                         <&clks IMX6SL_CLK_ENET_REF>;
+                                clock-names = "ipg", "ahb";
+                                status = "disabled";
+                        };
+
+                        usdhc1: usdhc@02190000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02190000 0x4000>;
+                                interrupts = <0 22 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>,
+                                         <&clks IMX6SL_CLK_USDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc2: usdhc@02194000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02194000 0x4000>;
+                                interrupts = <0 23 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>,
+                                         <&clks IMX6SL_CLK_USDHC2>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc3: usdhc@02198000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x02198000 0x4000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>,
+                                         <&clks IMX6SL_CLK_USDHC3>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc4: usdhc@0219c000 {
+                                compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
+                                reg = <0x0219c000 0x4000>;
+                                interrupts = <0 25 0x04>;
+                                clocks = <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>,
+                                         <&clks IMX6SL_CLK_USDHC4>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@021a0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a0000 0x4000>;
+                                interrupts = <0 36 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C1>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@021a4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a4000 0x4000>;
+                                interrupts = <0 37 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C2>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@021a8000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
+                                reg = <0x021a8000 0x4000>;
+                                interrupts = <0 38 0x04>;
+                                clocks = <&clks IMX6SL_CLK_I2C3>;
+                                status = "disabled";
+                        };
+
+                        mmdc: mmdc@021b0000 {
+                                compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
+                                reg = <0x021b0000 0x4000>;
+                        };
+
+                        rngb: rngb@021b4000 {
+                                reg = <0x021b4000 0x4000>;
+                                interrupts = <0 5 0x04>;
+                        };
+
+                        weim: weim@021b8000 {
+                                reg = <0x021b8000 0x4000>;
+                                interrupts = <0 14 0x04>;
+                        };
+
+                        ocotp: ocotp@021bc000 {
+                                compatible = "fsl,imx6sl-ocotp";
+                                reg = <0x021bc000 0x4000>;
+                        };
+
+                        audmux: audmux@021d8000 {
+                                compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
+                                reg = <0x021d8000 0x4000>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index c9c3fa344647..b6b82eca8d1e 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -39,6 +39,47 @@
                 valid-mask = <0x003fffff>;
         };
 
+        pci: pciv3@62000000 {
+                compatible = "v3,v360epc-pci";
+                #interrupt-cells = <1>;
+                #size-cells = <2>;
+                #address-cells = <3>;
+                reg = <0x62000000 0x10000>;
+                interrupt-parent = <&pic>;
+                interrupts = <17>; /* Bus error IRQ */
+                ranges = <0x00000000 0 0x61000000 /* config space */
+                        0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
+                        0x01000000 0 0x0 /* I/O space */
+                        0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
+                        0x02000000 0 0x00000000 /* non-prefectable memory */
+                        0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
+                        0x42000000 0 0x10000000 /* prefetchable memory */
+                        0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
+                interrupt-map-mask = <0xf800 0 0 0x7>;
+                interrupt-map = <
+                /* IDSEL 9 */
+                0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
+                0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
+                0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
+                0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
+                /* IDSEL 10 */
+                0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
+                0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
+                0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
+                0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
+                /* IDSEL 11 */
+                0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
+                0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
+                0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
+                0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
+                /* IDSEL 12 */
+                0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
+                0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
+                0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
+                0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
+                >;
+        };
+
         fpga {
                 /*
                  * The Integator/AP predates the idea to have magic numbers
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
new file mode 100644
index 000000000000..1334b42c6b77
--- /dev/null
+++ b/arch/arm/boot/dts/keystone.dts
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Texas Instruments Keystone 2 SoC";
+        compatible =  "ti,keystone-evm";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        memory {
+                reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                interrupt-parent = <&gic>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <0>;
+                };
+
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <1>;
+                };
+
+                cpu@2 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <2>;
+                };
+
+                cpu@3 {
+                        compatible = "arm,cortex-a15";
+                        device_type = "cpu";
+                        reg = <3>;
+                };
+        };
+
+        gic: interrupt-controller {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #size-cells = <0>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0x0 0x02561000 0x0 0x1000>,
+                      <0x0 0x02562000 0x0 0x2000>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0x308>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <0 20 0xf01>,
+                             <0 21 0xf01>,
+                             <0 22 0xf01>,
+                             <0 23 0xf01>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "ti,keystone","simple-bus";
+                interrupt-parent = <&gic>;
+                ranges = <0x0 0x0 0x0 0xc0000000>;
+
+                rstctrl: reset-controller {
+                        compatible = "ti,keystone-reset";
+                        reg = <0x023100e8 4>;   /* pll reset control reg */
+                };
+
+                uart0: serial@02530c00 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02530c00 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 277 0xf01>;
+                };
+
+                uart1:  serial@02531000 {
+                        compatible = "ns16550a";
+                        current-speed = <115200>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        reg = <0x02531000 0x100>;
+                        clock-frequency = <133120000>;
+                        interrupts = <0 280 0xf01>;
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index d6c9d65cbaeb..1e5bef0bead7 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -40,5 +40,64 @@
                                 marvell,function = "sdio";
                         };
                 };
+
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 23991e45bc55..a63a11137262 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -49,6 +49,34 @@
                         };
                 };
 
+                rtc@10300 {
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
+                        reg = <0x10300 0x20>;
+                        interrupts = <53>;
+                        clocks = <&gate_clk 7>;
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        clocks = <&gate_clk 14>, <&gate_clk 15>;
+                        clock-names = "0", "1";
+                        status = "disabled";
+                };
+
+                mvsdio@90000 {
+                        compatible = "marvell,orion-sdio";
+                        reg = <0x90000 0x200>;
+                        interrupts = <28>;
+                        clocks = <&gate_clk 4>;
+                        bus-width = <4>;
+                        cap-sdio-irq;
+                        cap-sd-highspeed;
+                        cap-mmc-highspeed;
+                        status = "disabled";
+                };
+
                 thermal@10078 {
                         compatible = "marvell,kirkwood-thermal";
                         reg = <0x10078 0x4>;
@@ -65,5 +93,53 @@
                         clocks = <&gate_clk 7>;
                         status = "disabled";
                 };
+
+                pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+
+                        bus-range = <0x00 0xff>;
+
+                        ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */
+                                  0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */
+                                  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
+                                  0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
+
+                        pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+
+                        pcie@2,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
+                                reg = <0x1000 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 10>;
+                                marvell,pcie-port = <1>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 18>;
+                                status = "disabled";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 5f21d4e427b0..00c48d26de68 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -18,10 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_uart0
-                                        &pmx_cloudbox_sata0 >;
-                        pinctrl-names = "default";
-
                         pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
                                 marvell,pins = "mpp15";
                                 marvell,function = "sata0";
@@ -29,16 +25,22 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         clock-frequency = <166666667>;
                         status = "okay";
                 };
 
                 sata@80000 {
+                        pinctrl-0 = <&pmx_cloudbox_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
 
                 spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         flash@0 {
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
new file mode 100644
index 000000000000..9d777edd1f36
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -0,0 +1,30 @@
+/*
+ * Marvell DB-88F6281-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        model = "Marvell DB-88F6281-BP Development Board";
+        compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
new file mode 100644
index 000000000000..f4c852886d23
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -0,0 +1,34 @@
+/*
+ * Marvell DB-88F6282-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-db.dtsi"
+/include/ "kirkwood-6282.dtsi"
+
+/ {
+        model = "Marvell DB-88F6282-BP Development Board";
+        compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
new file mode 100644
index 000000000000..c87cfb816120
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -0,0 +1,89 @@
+/*
+ * Marvell DB-{88F6281,88F6282}-BP Development Board Setup
+ *
+ * Saeed Bishara <saeed@marvell.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the 6281
+ * and 6282 variants of the Marvell Kirkwood Development Board.
+ */
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl@10000 {
+                        pmx_sdio_gpios: pmx-sdio-gpios {
+                                marvell,pins = "mpp37", "mpp38";
+                                marvell,function = "gpio";
+                        };
+                };
+
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        chip-delay = <25>;
+                        status = "okay";
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0 0x100000>;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x500000 0x1fb00000>;
+                        };
+                };
+
+                sata@80000 {
+                        nr-ports = <2>;
+                        status = "okay";
+                };
+
+                ehci@50000 {
+                        status = "okay";
+                };
+
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio_gpios>;
+                        pinctrl-names = "default";
+                        wp-gpios = <&gpio1 5 0>;
+                        cd-gpios = <&gpio1 6 0>;
+                        status = "okay";
+                };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index c9c44b2f62d7..14d4ceea3057 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -17,6 +17,11 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_320
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
+
                 blue-power {
                         label = "dns320:blue:power";
                         gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
@@ -46,6 +51,8 @@
                 };
 
                 serial@12100 {
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index e4e4930dc5cf..63872570e6ce 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -17,6 +17,11 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_power &pmx_led_red_usb_325
+                             &pmx_led_red_left_hdd &pmx_led_red_right_hdd
+                             &pmx_led_white_usb>;
+                pinctrl-names = "default";
+
                 white-power {
                         label = "dns325:white:power";
                         gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 6875ac00c174..0afe1d07c803 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -9,6 +9,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_unmount
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Power button";
                         linux,code = <116>;
@@ -29,6 +33,8 @@
         gpio_fan {
                 /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
                 compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_high_speed &pmx_fan_low_speed>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 14 1
                          &gpio1 13 1>;
                 gpio-fan,speed-map = <0    0
@@ -38,27 +44,17 @@
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 4 0>;
         };
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_nand &pmx_uart1
-                                      &pmx_sata0 &pmx_sata1
-                                      &pmx_led_power
-                                      &pmx_led_red_right_hdd
-                                      &pmx_led_red_left_hdd
-                                      &pmx_led_red_usb_325
-                                      &pmx_button_power
-                                      &pmx_led_red_usb_320
-                                      &pmx_power_off &pmx_power_back_on
-                                      &pmx_power_sata0 &pmx_power_sata1
-                                      &pmx_present_sata0 &pmx_present_sata1
-                                      &pmx_led_white_usb &pmx_fan_tacho
-                                      &pmx_fan_high_speed &pmx_fan_low_speed
-                                      &pmx_button_unmount &pmx_button_reset
-                                      &pmx_temp_alarm >;
+                        pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
+                                     &pmx_present_sata1 &pmx_fan_tacho
+                                     &pmx_temp_alarm>;
                         pinctrl-names = "default";
 
                         pmx_sata0: pmx-sata0 {
@@ -147,11 +143,15 @@
                         };
                 };
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "okay";
                         chip-delay = <35>;
 
@@ -192,6 +192,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_sata0 &pmx_power_sata1>;
+                pinctrl-names = "default";
 
                 sata0_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 0196cf6b0ef2..7714742bb8d8 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -18,11 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_usb_power_enable
-                                      &pmx_led_green &pmx_led_orange >;
-                        pinctrl-names = "default";
-
                         pmx_usb_power_enable: pmx-usb-power-enable {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
@@ -62,6 +57,8 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_green &pmx_led_orange>;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
@@ -77,6 +74,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 289e51d86372..36c7ba38d500 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -18,12 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_spi
-                                      &pmx_led_bluetooth &pmx_led_wifi
-                                      &pmx_led_wifi_ap >;
-                        pinctrl-names = "default";
-
                         pmx_led_bluetooth: pmx-led-bluetooth {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
@@ -43,6 +37,8 @@
 
                 spi@10600 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
 
                         m25p40@0 {
                                 #address-cells = <1>;
@@ -79,11 +75,15 @@
                         pinctrl-names = "default";
                         status = "okay";
                         /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_bluetooth &pmx_led_wifi
+                             &pmx_led_wifi_ap >;
+                pinctrl-names = "default";
 
                 bluetooth {
                         label = "dreamplug:blue:bluetooth";
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index c3573be7b92c..31caa6405065 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -18,15 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_usb_power_enable &pmx_led_orange
-                                      &pmx_led_left_cap_0 &pmx_led_left_cap_1
-                                      &pmx_led_left_cap_2 &pmx_led_left_cap_3
-                                      &pmx_led_right_cap_0 &pmx_led_right_cap_1
-                                      &pmx_led_right_cap_2 &pmx_led_right_cap_3
-                                    >;
-                        pinctrl-names = "default";
-
                         pmx_usb_power_enable: pmx-usb-power-enable {
                                 marvell,pins = "mpp29";
                                 marvell,function = "gpio";
@@ -109,6 +100,13 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_orange
+                              &pmx_led_left_cap_0 &pmx_led_left_cap_1
+                              &pmx_led_left_cap_2 &pmx_led_left_cap_3
+                              &pmx_led_right_cap_0 &pmx_led_right_cap_1
+                              &pmx_led_right_cap_2 &pmx_led_right_cap_3
+                            >;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
@@ -156,6 +154,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 44fd97dfc1f3..1e642f39b154 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -18,11 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
-                                      &pmx_led_wmode_r &pmx_led_wmode_g >;
-                        pinctrl-names = "default";
-
                         pmx_led_health_r: pmx-led-health-r {
                                 marvell,pins = "mpp46";
                                 marvell,function = "gpio";
@@ -72,11 +67,16 @@
 
                 mvsdio@90000 {
                         status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health_r &pmx_led_health_g
+                              &pmx_led_wmode_r &pmx_led_wmode_g >;
+                pinctrl-names = "default";
 
                 health-r {
                         label = "guruplug:red:health";
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 5335b1aa8601..20c4b081f420 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -18,13 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand
-                                      &pmx_led_os_red &pmx_power_off
-                                      &pmx_led_os_green &pmx_led_usb_transfer
-                                      &pmx_button_reset &pmx_button_usb_copy >;
-                        pinctrl-names = "default";
-
                         pmx_led_os_red: pmx-led-os-red {
                                 marvell,pins = "mpp22";
                                 marvell,function = "gpio";
@@ -61,6 +54,8 @@
 
                 nand@3000000 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "u-boot";
@@ -84,6 +79,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
@@ -97,6 +95,9 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_os_red &pmx_led_os_green
+                             &pmx_led_usb_transfer>;
+                pinctrl-names = "default";
 
                 green-os {
                         label = "ib62x0:green:os";
@@ -114,6 +115,8 @@
         };
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_power_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio0 24 0>;
         };
 
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 12ccf74ac3c4..441204e8abc6 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -20,51 +20,43 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_gpio_12 &pmx_gpio_35
-                                      &pmx_gpio_41 &pmx_gpio_42
-                                      &pmx_gpio_43 &pmx_gpio_44
-                                      &pmx_gpio_45 &pmx_gpio_46
-                                      &pmx_gpio_47 &pmx_gpio_48 >;
-                        pinctrl-names = "default";
-
-                        pmx_gpio_12: pmx-gpio-12 {
+                        pmx_button_reset: pmx-button-reset {
                                 marvell,pins = "mpp12";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_35: pmx-gpio-35 {
+                        pmx_button_otb: pmx-button-otb {
                                 marvell,pins = "mpp35";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_41: pmx-gpio-41 {
+                        pmx_led_level: pmx-led-level {
                                 marvell,pins = "mpp41";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_42: pmx-gpio-42 {
+                        pmx_led_power_blue: pmx-led-power-blue {
                                 marvell,pins = "mpp42";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_43: pmx-gpio-43 {
+                        pmx_led_power_red: pmx-power-red {
                                 marvell,pins = "mpp43";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_44: pmx-gpio-44 {
+                        pmx_led_usb1: pmx-led-usb1 {
                                 marvell,pins = "mpp44";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_45: pmx-gpio-45 {
+                        pmx_led_usb2: pmx-led-usb2 {
                                 marvell,pins = "mpp45";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_46: pmx-gpio-46 {
+                        pmx_led_usb3: pmx-led-usb3 {
                                 marvell,pins = "mpp46";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_47: pmx-gpio-47 {
+                        pmx_led_usb4: pmx-led-usb4 {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
                         };
-                        pmx_gpio_48: pmx-gpio-48 {
+                        pmx_led_otb: pmx-led-otb {
                                 marvell,pins = "mpp48";
                                 marvell,function = "gpio";
                         };
@@ -109,10 +101,23 @@
                                 reg = <0x980000 0x1f400000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_level &pmx_led_power_blue
+                              &pmx_led_power_red &pmx_led_usb1
+                              &pmx_led_usb2 &pmx_led_usb3
+                              &pmx_led_usb4 &pmx_led_otb >;
+                pinctrl-names = "default";
 
                 led-level {
                         label = "led_level";
@@ -154,6 +159,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = < &pmx_button_reset &pmx_button_otb >;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "OTB Button";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 3694e94f6e99..00a7bfe5e83b 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -18,12 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_button_reset &pmx_button_power
-                                      &pmx_led_backup &pmx_led_power
-                                      &pmx_button_otb &pmx_led_rebuild
-                                      &pmx_led_health
-                                      &pmx_led_sata_brt_ctrl_1
+                        pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
                                       &pmx_led_sata_brt_ctrl_2
                                       &pmx_led_backup_brt_ctrl_1
                                       &pmx_led_backup_brt_ctrl_2
@@ -151,6 +146,9 @@
         };
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_backup &pmx_led_power
+                              &pmx_led_rebuild &pmx_led_health >;
+                pinctrl-names = "default";
 
                 power_led {
                         label = "status:white:power_led";
@@ -174,6 +172,11 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_reset &pmx_button_power
+                             &pmx_button_otb>;
+                pinctrl-names = "default";
+
+
                 Power {
                         label = "Power Button";
                         linux,code = <116>;
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index 0bdce0ad7277..c3f036b86cca 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5bbd0542cdd3..5d9f5ea78700 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -18,9 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand &pmx_i2c_gpio_sda
-                                &pmx_i2c_gpio_scl >;
+                        pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
                         pinctrl-names = "default";
 
                         pmx_i2c_gpio_sda: pmx-gpio-sda {
@@ -38,8 +36,17 @@
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "ok";
                         chip-delay = <25>;
                 };
         };
+
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = < &gpio0 8 0            /* sda */
+                        &gpio0 9 0 >;           /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 37d45c4f88fb..31b17f5b9d28 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -8,16 +8,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_power_hdd &pmx_usb_vbus
-                                      &pmx_fan_low &pmx_fan_high
-                                      &pmx_led_function_red &pmx_led_alarm
-                                      &pmx_led_info &pmx_led_power
-                                      &pmx_fan_lock &pmx_button_function
-                                      &pmx_power_switch &pmx_power_auto_switch
-                                      &pmx_led_function_blue >;
-                        pinctrl-names = "default";
-
                         pmx_power_hdd: pmx-power-hdd {
                                 marvell,pins = "mpp10";
                                 marvell,function = "gpo";
@@ -112,6 +102,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_function &pmx_power_switch
+                             &pmx_power_auto_switch>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Function Button";
                         linux,code = <357>;
@@ -133,6 +127,10 @@
 
         gpio_leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_function_red &pmx_led_alarm
+                             &pmx_led_info &pmx_led_power
+                             &pmx_led_function_blue>;
+                pinctrl-names = "default";
 
                 led@1 {
                         label = "lsxl:blue:func";
@@ -163,6 +161,8 @@
 
         gpio_fan {
                 compatible = "gpio-fan";
+                pinctrl-0 = <&pmx_fan_low &pmx_fan_high &pmx_fan_lock>;
+                pinctrl-names = "default";
                 gpios = <&gpio0 19 1
                          &gpio0 18 1>;
                 gpio-fan,speed-map = <0    3
@@ -172,10 +172,16 @@
                 alarm-gpios = <&gpio1 8 0>;
         };
 
+        restart_poweroff {
+                compatible = "restart-poweroff";
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_power_hdd &pmx_usb_vbus>;
+                pinctrl-names = "default";
 
                 usb_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 758824118a9a..6179333fd71f 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -18,16 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                      &pmx_led_health
-                                      &pmx_sata0 &pmx_sata1
-                                      &pmx_led_user1o
-                                      &pmx_led_user1g &pmx_led_user0o
-                                      &pmx_led_user0g &pmx_led_misc
-                                    >;
-                        pinctrl-names = "default";
-
                         pmx_led_health: pmx-led-health {
                                 marvell,pins = "mpp7";
                                 marvell,function = "gpo";
@@ -91,9 +81,13 @@
 
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         partition@0 {
@@ -127,22 +121,37 @@
                 };
 
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         nr-ports = <2>;
                         status = "okay";
-
                 };
 
                 mvsdio@90000 {
                         pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
                         pinctrl-names = "default";
                         status = "okay";
-                        cd-gpios = <&gpio1 15 0>;
+                        cd-gpios = <&gpio1 15 1>;
                         /* No WP GPIO */
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_health
+                              &pmx_led_user1o
+                              &pmx_led_user1g &pmx_led_user0o
+                              &pmx_led_user0g &pmx_led_misc
+                            >;
+                pinctrl-names = "default";
 
                 health {
                         label = "status:green:health";
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 1ca66ab83ad6..ad6ade7d9191 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -18,18 +18,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-
-                        pinctrl-0 = < &pmx_uart0
-                                      &pmx_button_power
-                                      &pmx_button_backup
-                                      &pmx_button_reset
-                                      &pmx_led_blue_power
-                                      &pmx_led_blue_activity
-                                      &pmx_led_blue_disk1
-                                      &pmx_led_blue_disk2
-                                      &pmx_led_blue_backup >;
-                        pinctrl-names = "default";
-
                         pmx_button_power: pmx-button-power {
                                 marvell,pins = "mpp47";
                                 marvell,function = "gpio";
@@ -74,6 +62,8 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
 
@@ -111,10 +101,22 @@
                         status = "okay";
                         nr-ports = <2>;
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = < &pmx_led_blue_power &pmx_led_blue_activity
+                              &pmx_led_blue_disk1 &pmx_led_blue_disk2
+                              &pmx_led_blue_backup >;
+                pinctrl-names = "default";
 
                 power_led {
                         label = "status:blue:power_led";
@@ -143,6 +145,10 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_button_power &pmx_button_backup
+                             &pmx_button_reset>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "Power Button";
                         linux,code = <116>;     /* KEY_POWER */
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 6affd924fe11..2afac0405816 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -8,10 +8,6 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_spi &pmx_twsi0 &pmx_uart0
-                                        &pmx_ns2_sata0 &pmx_ns2_sata1>;
-                        pinctrl-names = "default";
-
                         pmx_ns2_sata0: pmx-ns2-sata0 {
                                 marvell,pins = "mpp21";
                                 marvell,function = "sata0";
@@ -23,10 +19,14 @@
                 };
 
                 serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                         status = "okay";
                 };
 
                 spi@10600 {
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         flash@0 {
@@ -45,6 +45,8 @@
                 };
 
                 i2c@11000 {
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                         status = "okay";
 
                         eeprom@50 {
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index f2d36ecf36d8..b50e93d7796c 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index b02eb4ea1bb4..af8259fe8955 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index bcec4d6cada7..85f24d227e17 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -13,6 +13,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0 &pmx_ns2_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab25733..329e530bffe7 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -14,6 +14,8 @@
 
         ocp@f1000000 {
                 sata@80000 {
+                        pinctrl-0 = <&pmx_ns2_sata0>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <1>;
                 };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index a7412b937a8a..69003598f5fa 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 
 /include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
 
 / {
         model = "ZyXEL NSA310";
@@ -17,22 +18,7 @@
 
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_led_esata_green
-                                      &pmx_led_esata_red
-                                      &pmx_led_usb_green
-                                      &pmx_led_usb_red
-                                      &pmx_usb_power_off
-                                      &pmx_led_sys_green
-                                      &pmx_led_sys_red
-                                      &pmx_btn_reset
-                                      &pmx_btn_copy
-                                      &pmx_led_copy_green
-                                      &pmx_led_copy_red
-                                      &pmx_led_hdd_green
-                                      &pmx_led_hdd_red
-                                      &pmx_unknown
-                                      &pmx_btn_power
-                                      &pmx_pwr_off >;
+                        pinctrl-0 = <&pmx_unknown>;
                         pinctrl-names = "default";
 
                         pmx_led_esata_green: pmx-led-esata-green {
@@ -176,12 +162,22 @@
                                 reg = <0x5040000 0x2fc0000>;
                         };
                 };
+
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 
         gpio_keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+                pinctrl-names = "default";
 
                 button@1 {
                         label = "Power Button";
@@ -202,6 +198,12 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
+                             &pmx_led_usb_green &pmx_led_usb_red
+                             &pmx_led_sys_green &pmx_led_sys_red
+                             &pmx_led_copy_green &pmx_led_copy_red
+                             &pmx_led_hdd_green &pmx_led_hdd_red>;
+                pinctrl-names = "default";
 
                 green-sys {
                         label = "nsa310:green:sys";
@@ -247,6 +249,8 @@
 
         gpio_poweroff {
                 compatible = "gpio-poweroff";
+                pinctrl-0 = <&pmx_pwr_off>;
+                pinctrl-names = "default";
                 gpios = <&gpio1 16 0>;
         };
 
@@ -254,6 +258,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_off>;
+                pinctrl-names = "default";
 
                 usb0_power_off: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index d27f7245f8e7..38dc8517d777 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -19,15 +19,21 @@
         ocp@f1000000 {
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 serial@12100 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
                         chip-delay = <25>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "uboot";
@@ -67,6 +73,8 @@
 
                 i2c@11100 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_twsi1>;
+                        pinctrl-names = "default";
 
                         s35390a: s35390a@30 {
                                 compatible = "s35390a";
@@ -75,16 +83,7 @@
                 };
 
                 pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_nand &pmx_uart0
-                                &pmx_uart1 &pmx_twsi1
-                                &pmx_dip_sw0 &pmx_dip_sw1
-                                &pmx_dip_sw2 &pmx_dip_sw3
-                                &pmx_gpio_0 &pmx_gpio_1
-                                &pmx_gpio_2 &pmx_gpio_3
-                                &pmx_gpio_4 &pmx_gpio_5
-                                &pmx_gpio_6 &pmx_gpio_7
-                                &pmx_led_red &pmx_led_green
-                                &pmx_led_yellow >;
+                        pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
                         pinctrl-names = "default";
 
                         pmx_uart0: pmx-uart0 {
@@ -104,63 +103,14 @@
                                 marvell,function = "sysrst";
                         };
 
-                        pmx_dip_sw0: pmx-dip-sw0 {
-                                marvell,pins = "mpp20";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw1: pmx-dip-sw1 {
-                                marvell,pins = "mpp21";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw2: pmx-dip-sw2 {
-                                marvell,pins = "mpp22";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_dip_sw3: pmx-dip-sw3 {
-                                marvell,pins = "mpp23";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_0: pmx-gpio-0 {
-                                marvell,pins = "mpp24";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_1: pmx-gpio-1 {
-                                marvell,pins = "mpp25";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_2: pmx-gpio-2 {
-                                marvell,pins = "mpp26";
+                        pmx_dip_switches: pmx-dip-switches {
+                                marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23";
                                 marvell,function = "gpio";
                         };
 
-                        pmx_gpio_3: pmx-gpio-3 {
-                                marvell,pins = "mpp27";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_4: pmx-gpio-4 {
-                                marvell,pins = "mpp28";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_5: pmx-gpio-5 {
-                                marvell,pins = "mpp29";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_6: pmx-gpio-6 {
-                                marvell,pins = "mpp30";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_gpio_7: pmx-gpio-7 {
-                                marvell,pins = "mpp31";
+                        pmx_gpio_header: pmx-gpio-header {
+                                marvell,pins = "mpp24", "mpp25", "mpp26", "mpp27",
+                                               "mpp28", "mpp29", "mpp30", "mpp31";
                                 marvell,function = "gpio";
                         };
 
@@ -174,18 +124,8 @@
                                 marvell,function = "gpio";
                         };
 
-                        pmx_led_red: pmx-led-red {
-                                marvell,pins = "mpp41";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_led_green: pmx-led-green {
-                                marvell,pins = "mpp42";
-                                marvell,function = "gpio";
-                        };
-
-                        pmx_led_yellow: pmx-led-yellow {
-                                marvell,pins = "mpp43";
+                        pmx_leds: pmx-leds {
+                                marvell,pins = "mpp41", "mpp42", "mpp43";
                                 marvell,function = "gpio";
                         };
                 };
@@ -193,6 +133,8 @@
 
         gpio-leds {
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_leds>;
+                pinctrl-names = "default";
 
                 led-red {
                         label = "obsa6:red:stat";
@@ -209,4 +151,18 @@
                         gpios = <&gpio1 11 1>;
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_gpio_init>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                button@1 {
+                        label = "Init Button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 6 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
new file mode 100644
index 000000000000..f7143f128504
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -0,0 +1,93 @@
+/*
+ * kirkwood-sheevaplug-common.dts - Common parts for Sheevaplugs
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/include/ "kirkwood.dtsi"
+/include/ "kirkwood-6281.dtsi"
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                pinctrl: pinctrl@10000 {
+
+                        pmx_usb_power_enable: pmx-usb-power-enable {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_red: pmx-led-red {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_blue: pmx-led-blue {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_wp: pmx-sdio-wp {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                };
+
+                nand@3000000 {
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "root";
+                                reg = <0x0500000 0x1fb00000>;
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_usb_power_enable>;
+                pinctrl-names = "default";
+
+                usb_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "USB Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 29 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
new file mode 100644
index 000000000000..f620ce48de97
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for eSATA Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+        model = "Globalscale Technologies eSATA SheevaPlug";
+        compatible = "globalscale,sheevaplug-esata-rev13", "globalscale,sheevaplug-esata", "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio &pmx_sdio_cd &pmx_sdio_wp>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        cd-gpios = <&gpio1 12 1>;
+                        wp-gpios = <&gpio1 15 0>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue>;
+                pinctrl-names = "default";
+
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
new file mode 100644
index 000000000000..bf1dff251432
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -0,0 +1,43 @@
+/*
+ * kirkwood-sheevaplug-esata.dts - Device tree file for Sheevaplug
+ *
+ * Copyright (C) 2013 Simon Baatz <gmbnomis@gmail.com>
+ *
+ * Licensed under GPLv2
+ */
+
+/dts-v1/;
+
+/include/ "kirkwood-sheevaplug-common.dtsi"
+
+/ {
+        model = "Globalscale Technologies SheevaPlug";
+        compatible = "globalscale,sheevaplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        ocp@f1000000 {
+                mvsdio@90000 {
+                        pinctrl-0 = <&pmx_sdio>;
+                        pinctrl-names = "default";
+                        status = "okay";
+                        /* No CD or WP GPIOs */
+                        broken-cd;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_blue &pmx_led_red>;
+                pinctrl-names = "default";
+
+                health {
+                        label = "sheevaplug:blue:health";
+                        gpios = <&gpio1 17 1>;
+                        linux,default-trigger = "default-on";
+                };
+
+                misc {
+                        label = "sheevaplug:red:misc";
+                        gpios = <&gpio1 14 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 66eb45b00b25..f2052d7bc10f 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -19,18 +19,6 @@
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
                         /*
-                         * GPIO LED layout
-                         *
-                         *       /-SYS_LED(2)
-                         *       |
-                         *       |   /-DISK_LED
-                         *       |   |
-                         *       |   |   /-WLAN_LED(2)
-                         *       |   |   |
-                         * [SW] [*] [*] [*]
-                         */
-
-                        /*
                          * Switch positions
                          *
                          *     /-SW_LEFT(2)
@@ -41,19 +29,8 @@
                          *     |   |   |
                          * PS [L] [I] [R] LEDS
                          */
-                        pinctrl-0 = < &pmx_led_disk_yellow
-                                      &pmx_sata0_pwr_enable
-                                      &pmx_led_sys_red
-                                      &pmx_led_sys_blue
-                                      &pmx_led_wifi_green
-                                      &pmx_sw_left
-                                      &pmx_sw_right
-                                      &pmx_sw_idle
-                                      &pmx_sw_left2
-                                      &pmx_led_wifi_yellow
-                                      &pmx_uart0
-                                      &pmx_nand
-                                      &pmx_twsi0 >;
+                        pinctrl-0 = <&pmx_sw_left &pmx_sw_right
+                                     &pmx_sw_idle &pmx_sw_left2>;
                         pinctrl-names = "default";
 
                         pmx_led_disk_yellow: pmx-led-disk-yellow {
@@ -109,10 +86,14 @@
 
                 serial@12000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
 
                 nand@3000000 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
 
                         partition@0 {
                                 label = "u-boot";
@@ -147,6 +128,8 @@
 
                 i2c@11000 {
                         status = "ok";
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                 };
 
                 mvsdio@90000 {
@@ -154,11 +137,28 @@
                         pinctrl-names = "default";
                         status = "okay";
                         /* No CD or WP GPIOs */
+                        broken-cd;
                 };
         };
 
         gpio-leds {
+                /*
+                 * GPIO LED layout
+                 *
+                 *       /-SYS_LED(2)
+                 *       |
+                 *       |   /-DISK_LED
+                 *       |   |
+                 *       |   |   /-WLAN_LED(2)
+                 *       |   |   |
+                 * [SW] [*] [*] [*]
+                 */
+
                 compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_disk_yellow &pmx_led_sys_red
+                             &pmx_led_sys_blue &pmx_led_wifi_green
+                             &pmx_led_wifi_yellow>;
+                pinctrl-names = "default";
 
                 disk {
                         label = "topkick:yellow:disk";
@@ -187,6 +187,8 @@
                 compatible = "simple-bus";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_sata0_pwr_enable>;
+                pinctrl-names = "default";
 
                 sata0_power: regulator@1 {
                         compatible = "regulator-fixed";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 8295c833887f..6dd1038e4de4 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,16 +1,14 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6281.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                         pinctrl-names = "default";
 
                         pmx_ram_size: pmx-ram-size {
@@ -38,6 +36,9 @@
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index df3f95dfba33..6fdc5ffcaae5 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,16 +1,14 @@
 /dts-v1/;
 
-/include/ "kirkwood-ts219.dtsi"
+/include/ "kirkwood.dtsi"
 /include/ "kirkwood-6282.dtsi"
+/include/ "kirkwood-ts219.dtsi"
 
 / {
         ocp@f1000000 {
                 pinctrl: pinctrl@10000 {
 
-                        pinctrl-0 = < &pmx_uart0 &pmx_uart1 &pmx_spi
-                                      &pmx_twsi0 &pmx_sata0 &pmx_sata1
-                                      &pmx_ram_size &pmx_reset_button
-                                      &pmx_USB_copy_button &pmx_board_id>;
+                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                         pinctrl-names = "default";
 
                         pmx_ram_size: pmx-ram-size {
@@ -32,12 +30,23 @@
                                 marvell,function = "gpio";
                         };
                 };
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@2,0 {
+                                status = "okay";
+                        };
+                };
+
         };
 
         gpio_keys {
                 compatible = "gpio-keys";
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>;
+                pinctrl-names = "default";
+
                 button@1 {
                         label = "USB Copy";
                         linux,code = <133>;
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 64ea27cb3298..0c9a94cd666c 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -1,5 +1,3 @@
-/include/ "kirkwood.dtsi"
-
 / {
         model = "QNAP TS219 family";
         compatible = "qnap,ts219", "marvell,kirkwood";
@@ -17,6 +15,8 @@
                 i2c@11000 {
                         status = "okay";
                         clock-frequency = <400000>;
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
 
                         s35390a: s35390a@30 {
                                 compatible = "s35390a";
@@ -26,13 +26,24 @@
                 serial@12000 {
                         clock-frequency = <200000000>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                 };
                 serial@12100 {
                         clock-frequency = <200000000>;
                         status = "okay";
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
+                };
+                poweroff@12100 {
+                        compatible = "qnap,power-off";
+                        reg = <0x12000 0x100>;
+                        clocks = <&gate_clk 7>;
                 };
                 spi@10600 {
                         status = "okay";
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
 
                         m25p128@0 {
                                 #address-cells = <1>;
@@ -71,8 +82,17 @@
                         };
                 };
                 sata@80000 {
+                        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+                        pinctrl-names = "default";
                         status = "okay";
                         nr-ports = <2>;
                 };
+                pcie-controller {
+                        status = "okay";
+
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index fada7e6d24d8..9809fc1f105c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -4,6 +4,18 @@
         compatible = "marvell,kirkwood";
         interrupt-parent = <&intc>;
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "marvell,feroceon";
+                        clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>;
+                        clock-names = "cpu_clk", "ddrclk", "powersave";
+                };
+        };
+
         aliases {
                gpio0 = &gpio0;
                gpio1 = &gpio1;
@@ -18,7 +30,9 @@
 
         ocp@f1000000 {
                 compatible = "simple-bus";
-                ranges = <0x00000000 0xf1000000 0x4000000
+                ranges = <0x00000000 0xf1000000 0x0100000
+                          0xe0000000 0xe0000000 0x8100000 /* PCIE */
+                          0xf4000000 0xf4000000 0x0000400
                           0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -71,13 +85,6 @@
                         status = "disabled";
                 };
 
-                rtc@10300 {
-                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
-                        reg = <0x10300 0x20>;
-                        interrupts = <53>;
-                        clocks = <&gate_clk 7>;
-                };
-
                 spi@10600 {
                         compatible = "marvell,orion-spi";
                         #address-cells = <1>;
@@ -151,15 +158,6 @@
                         status = "okay";
                 };
 
-                sata@80000 {
-                        compatible = "marvell,orion-sata";
-                        reg = <0x80000 0x5000>;
-                        interrupts = <21>;
-                        clocks = <&gate_clk 14>, <&gate_clk 15>;
-                        clock-names = "0", "1";
-                        status = "disabled";
-                };
-
                 nand@3000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
@@ -167,7 +165,7 @@
                         ale = <1>;
                         bank-width = <1>;
                         compatible = "marvell,orion-nand";
-                        reg = <0x3000000 0x400>;
+                        reg = <0xf4000000 0x400>;
                         chip-delay = <25>;
                         /* set partition map and/or chip-delay in board dts */
                         clocks = <&gate_clk 7>;
@@ -194,13 +192,5 @@
                         clocks = <&gate_clk 17>;
                         status = "okay";
                 };
-
-                mvsdio@90000 {
-                        compatible = "marvell,orion-sdio";
-                        reg = <0x90000 0x200>;
-                        interrupts = <28>;
-                        clocks = <&gate_clk 4>;
-                        status = "disabled";
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index b4dc3ed9a3ec..02df1914a47c 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
+#include "at91sam9g20.dtsi"
 
 / {
 
@@ -94,26 +94,26 @@
 
                 led1g {
                         label = "led1:green";
-                        gpios = <&pioB 0 1>;
+                        gpios = <&pioB 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                 };
 
                 led1r {
                         label = "led1:red";
-                        gpios = <&pioB 1 1>;
+                        gpios = <&pioB 1 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                 };
 
                 led2g {
                         label = "led2:green";
-                        gpios = <&pioB 2 1>;
+                        gpios = <&pioB 2 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                         default-state = "on";
                 };
 
                 led2r {
                         label = "led2:red";
-                        gpios = <&pioB 3 1>;
+                        gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "none";
                 };
         };
@@ -125,16 +125,16 @@
 
                 reset {
                         label = "reset";
-                        gpios = <&pioB 30 1>;
+                        gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
                         linux,code = <0x100>;
                         gpio-key,wakeup;
                 };
 
                 mode {
                         label = "mode";
-                        gpios = <&pioB 31 1>;
+                        gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
                         linux,code = <0x101>;
                         gpio-key,wakeup;
                 };
         };
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 1582f484a867..3abebb75fc57 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -18,8 +18,12 @@
         interrupt-parent = <&mic>;
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index 317300875f34..ccf9ea242f72 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91rm9200.dtsi"
+#include "at91rm9200.dtsi"
 
 / {
         model = "Phontech MPA 1600";
@@ -62,7 +62,7 @@
 
                 monitor_mute {
                         label = "Monitor mute";
-                        gpios = <&pioC 1 1>;
+                        gpios = <&pioC 1 GPIO_ACTIVE_LOW>;
                         linux,code = <113>;
                 };
         };
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 9bf49b3826ea..cdc010e0f93e 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -15,7 +15,7 @@
                       < 0x02081000 0x1000 >;
         };
 
-        timer@2000004 {
+        timer@2000000 {
                 compatible = "qcom,scss-timer", "qcom,msm-timer";
                 interrupts = <1 0 0x301>,
                              <1 1 0x301>,
@@ -26,7 +26,18 @@
                 cpu-offset = <0x40000>;
         };
 
-        serial@19c400000 {
+        msmgpio: gpio@800000 {
+                compatible = "qcom,msm-gpio";
+                reg = <0x00800000 0x1000>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <173>;
+                interrupts = <0 32 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        serial@19c40000 {
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x19c40000 0x1000>,
                       <0x19c00000 0x1000>;
diff --git a/arch/arm/boot/dts/msm8960-cdp.dts b/arch/arm/boot/dts/msm8960-cdp.dts
index 2e4d87a125d6..db2060c46540 100644
--- a/arch/arm/boot/dts/msm8960-cdp.dts
+++ b/arch/arm/boot/dts/msm8960-cdp.dts
@@ -26,7 +26,18 @@
                 cpu-offset = <0x80000>;
         };
 
-        serial@19c400000 {
+        msmgpio: gpio@fd510000 {
+                compatible = "qcom,msm-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+                ngpio = <150>;
+                interrupts = <0 32 0x4>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                reg = <0xfd510000 0x4000>;
+        };
+
+        serial@16440000 {
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x16440000 0x1000>,
                       <0x16400000 0x1000>;
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
new file mode 100644
index 000000000000..9565199bce7a
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -0,0 +1,74 @@
+/*
+ *  linux/arch/arm/boot/nspire-classic.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "nspire.dtsi"
+
+&lcd {
+        lcd-type = "classic";
+};
+
+&fast_timer {
+        /* compatible = "lsi,zevio-timer"; */
+        reg = <0x90010000 0x1000>, <0x900A0010 0x8>;
+};
+
+&uart {
+        compatible = "ns16550";
+        reg-shift = <2>;
+        reg-io-width = <4>;
+        clocks = <&apb_pclk>;
+        no-loopback-test;
+};
+
+&timer0 {
+        /* compatible = "lsi,zevio-timer"; */
+        reg = <0x900C0000 0x1000>, <0x900A0018 0x8>;
+};
+
+&timer1 {
+        compatible = "lsi,zevio-timer";
+        reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
+};
+
+&keypad {
+        active-low;
+
+};
+
+&base_clk {
+        compatible = "lsi,nspire-classic-clock";
+};
+
+&ahb_clk {
+        compatible = "lsi,nspire-classic-ahb-divider";
+};
+
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x10000000 0x2000000>; /* 32 MB */
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                intc: interrupt-controller@DC000000 {
+                        compatible = "lsi,zevio-intc";
+                        interrupt-controller;
+                        reg = <0xDC000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+        };
+        chosen {
+                bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
+        };
+};
diff --git a/arch/arm/boot/dts/nspire-clp.dts b/arch/arm/boot/dts/nspire-clp.dts
new file mode 100644
index 000000000000..fa5a044656de
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-clp.dts
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/boot/nspire-clp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00020039
+        0x0004002c      0x00050034      0x00060015
+        0x0007000b      0x0008002d      0x01000033
+        0x0101004e      0x01020011      0x01030004
+        0x0104002f      0x01050003      0x01060016
+        0x01070002      0x01080014      0x02000062
+        0x0201000c      0x0202001f      0x02030007
+        0x02040013      0x02050006      0x02060010
+        0x02070005      0x02080019      0x03000027
+        0x03010037      0x03020018      0x0303000a
+        0x03040031      0x03050009      0x03060032
+        0x03070008      0x03080026      0x04000028
+        0x04010035      0x04020025      0x04040024
+        0x04060017      0x04080023      0x05000028
+        0x05020022      0x0503001b      0x05040021
+        0x0505001a      0x05060012      0x0507006f
+        0x05080020      0x0509002a      0x0601001c
+        0x0602002e      0x06030068      0x06040030
+        0x0605006d      0x0606001e      0x06070001
+        0x0608002b      0x0609000f      0x07000067
+        0x0702006a      0x0704006c      0x07060069
+        0x0707000e      0x0708001d      0x070a000d
+        >;
+};
+
+/ {
+        model = "TI-NSPIRE Clickpad";
+        compatible = "ti,nspire-clp";
+};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
new file mode 100644
index 000000000000..375b924f60d8
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -0,0 +1,112 @@
+/*
+ *  linux/arch/arm/boot/nspire-cx.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire.dtsi"
+
+&lcd {
+        lcd-type = "cx";
+};
+
+&fast_timer {
+        /* compatible = "arm,sp804", "arm,primecell"; */
+};
+
+&uart {
+        compatible = "arm,pl011", "arm,primecell";
+
+        clocks = <&uart_clk>, <&apb_pclk>;
+        clock-names = "uart_clk", "apb_pclk";
+};
+
+&timer0 {
+        compatible = "arm,sp804", "arm,primecell";
+};
+
+&timer1 {
+        compatible = "arm,sp804", "arm,primecell";
+};
+
+&base_clk {
+        compatible = "lsi,nspire-cx-clock";
+};
+
+&ahb_clk {
+        compatible = "lsi,nspire-cx-ahb-divider";
+};
+
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00040039
+        0x0005002c      0x00060015      0x0007000b
+        0x0008000f      0x0100002d      0x01010011
+        0x0102002f      0x01030004      0x01040016
+        0x01050014      0x0106001f      0x01070002
+        0x010a006a      0x02000013      0x02010010
+        0x02020019      0x02030007      0x02040018
+        0x02050031      0x02060032      0x02070005
+        0x02080028      0x0209006c      0x03000026
+        0x03010025      0x03020024      0x0303000a
+        0x03040017      0x03050023      0x03060022
+        0x03070008      0x03080035      0x03090069
+        0x04000021      0x04010012      0x04020020
+        0x0404002e      0x04050030      0x0406001e
+        0x0407000d      0x04080037      0x04090067
+        0x05010038      0x0502000c      0x0503001b
+        0x05040034      0x0505001a      0x05060006
+        0x05080027      0x0509000e      0x050a006f
+        0x0600002b      0x0602004e      0x06030068
+        0x06040003      0x0605006d      0x06060009
+        0x06070001      0x0609000f      0x0708002a
+        0x0709001d      0x070a0033      >;
+};
+
+/ {
+        model = "TI-NSPIRE CX";
+        compatible = "ti,nspire-cx";
+
+        memory {
+                device_type = "memory";
+                reg = <0x10000000 0x4000000>; /* 64 MB */
+        };
+
+        uart_clk: uart_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        ahb {
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                intc: interrupt-controller@DC000000 {
+                        compatible = "arm,pl190-vic";
+                        interrupt-controller;
+                        reg = <0xDC000000 0x1000>;
+                        #interrupt-cells = <1>;
+                };
+
+                apb@90000000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        i2c@90050000 {
+                                compatible = "snps,designware-i2c";
+                                reg = <0x90050000 0x1000>;
+                                interrupts = <20>;
+                        };
+                };
+        };
+        chosen {
+                bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
+        };
+};
diff --git a/arch/arm/boot/dts/nspire-tp.dts b/arch/arm/boot/dts/nspire-tp.dts
new file mode 100644
index 000000000000..621391ce6ed6
--- /dev/null
+++ b/arch/arm/boot/dts/nspire-tp.dts
@@ -0,0 +1,44 @@
+/*
+ *  linux/arch/arm/boot/nspire-tp.dts
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+
+/include/ "nspire-classic.dtsi"
+
+&keypad {
+        linux,keymap = <
+        0x0000001c      0x0001001c      0x00040039
+        0x0005002c      0x00060015      0x0007000b
+        0x0008000f      0x0100002d      0x01010011
+        0x0102002f      0x01030004      0x01040016
+        0x01050014      0x0106001f      0x01070002
+        0x010a006a      0x02000013      0x02010010
+        0x02020019      0x02030007      0x02040018
+        0x02050031      0x02060032      0x02070005
+        0x02080028      0x0209006c      0x03000026
+        0x03010025      0x03020024      0x0303000a
+        0x03040017      0x03050023      0x03060022
+        0x03070008      0x03080035      0x03090069
+        0x04000021      0x04010012      0x04020020
+        0x0404002e      0x04050030      0x0406001e
+        0x0407000d      0x04080037      0x04090067
+        0x05010038      0x0502000c      0x0503001b
+        0x05040034      0x0505001a      0x05060006
+        0x05080027      0x0509000e      0x050a006f
+        0x0600002b      0x0602004e      0x06030068
+        0x06040003      0x0605006d      0x06060009
+        0x06070001      0x0609000f      0x0708002a
+        0x0709001d      0x070a0033      >;
+};
+
+/ {
+        model = "TI-NSPIRE Touchpad";
+        compatible = "ti,nspire-tp";
+};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
new file mode 100644
index 000000000000..a22ffe633b49
--- /dev/null
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -0,0 +1,175 @@
+/*
+ *  linux/arch/arm/boot/nspire.dtsi
+ *
+ *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        bootrom: bootrom@00000000 {
+                reg = <0x00000000 0x80000>;
+        };
+
+        sram: sram@A4000000 {
+                device = "memory";
+                reg = <0xA4000000 0x20000>;
+        };
+
+        timer_clk: timer_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        base_clk: base_clk {
+                #clock-cells = <0>;
+                reg = <0x900B0024 0x4>;
+        };
+
+        ahb_clk: ahb_clk {
+                #clock-cells = <0>;
+                reg = <0x900B0024 0x4>;
+                clocks = <&base_clk>;
+        };
+
+        apb_pclk: apb_pclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clock-div = <2>;
+                clock-mult = <1>;
+                clocks = <&ahb_clk>;
+        };
+
+        ahb {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                spi: spi@A9000000 {
+                        reg = <0xA9000000 0x1000>;
+                };
+
+                usb0: usb@B0000000 {
+                        reg = <0xB0000000 0x1000>;
+                        interrupts = <8>;
+                };
+
+                usb1: usb@B4000000 {
+                        reg = <0xB4000000 0x1000>;
+                        interrupts = <9>;
+                        status = "disabled";
+                };
+
+                lcd: lcd@C0000000 {
+                        compatible = "arm,pl111", "arm,primecell";
+                        reg = <0xC0000000 0x1000>;
+                        interrupts = <21>;
+
+                        clocks = <&apb_pclk>;
+                        clock-names = "apb_pclk";
+                };
+
+                adc: adc@C4000000 {
+                        reg = <0xC4000000 0x1000>;
+                        interrupts = <11>;
+                };
+
+                tdes: crypto@C8010000 {
+                        reg = <0xC8010000 0x1000>;
+                };
+
+                sha256: crypto@CC000000 {
+                        reg = <0xCC000000 0x1000>;
+                };
+
+                apb@90000000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        clock-ranges;
+                        ranges;
+
+                        gpio: gpio@90000000 {
+                                reg = <0x90000000 0x1000>;
+                                interrupts = <7>;
+                        };
+
+                        fast_timer: timer@90010000 {
+                                reg = <0x90010000 0x1000>;
+                                interrupts = <17>;
+                        };
+
+                        uart: serial@90020000 {
+                                reg = <0x90020000 0x1000>;
+                                interrupts = <1>;
+                        };
+
+                        timer0: timer@900C0000 {
+                                reg = <0x900C0000 0x1000>;
+
+                                clocks = <&timer_clk>;
+                        };
+
+                        timer1: timer@900D0000 {
+                                reg = <0x900D0000 0x1000>;
+                                interrupts = <19>;
+
+                                clocks = <&timer_clk>;
+                        };
+
+                        watchdog: watchdog@90060000 {
+                                compatible = "arm,amba-primecell";
+                                reg = <0x90060000 0x1000>;
+                                interrupts = <3>;
+                        };
+
+                        rtc: rtc@90090000 {
+                                reg = <0x90090000 0x1000>;
+                                interrupts = <4>;
+                        };
+
+                        misc: misc@900A0000 {
+                                reg = <0x900A0000 0x1000>;
+                        };
+
+                        pwr: pwr@900B0000 {
+                                reg = <0x900B0000 0x1000>;
+                                interrupts = <15>;
+                        };
+
+                        keypad: input@900E0000 {
+                                compatible = "ti,nspire-keypad";
+                                reg = <0x900E0000 0x1000>;
+                                interrupts = <16>;
+
+                                scan-interval = <1000>;
+                                row-delay = <200>;
+
+                                clocks = <&apb_pclk>;
+                        };
+
+                        contrast: contrast@900F0000 {
+                                reg = <0x900F0000 0x1000>;
+                        };
+
+                        led: led@90110000 {
+                                reg = <0x90110000 0x1000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 37aa7487d4d8..a2bfcde858a6 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -8,7 +8,10 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
@@ -21,8 +24,12 @@
         };
 
         cpus {
-                cpu@0 {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
                         compatible = "arm,arm1136jf-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 68282ee13e26..224c08f472f4 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap2420.dtsi"
+#include "omap2420.dtsi"
 
 / {
         model = "TI OMAP2420 H4 board";
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index da5b285b73be..c8f9c55169ea 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
         compatible = "ti,omap2420", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 054bc4439568..c535a5a2b27f 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap2.dtsi"
+#include "omap2.dtsi"
 
 / {
         compatible = "ti,omap2430", "ti,omap2";
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 3046d1f81be0..afdb16417d4e 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap36xx.dtsi"
+#include "omap36xx.dtsi"
 
 / {
         model = "TI OMAP3 BeagleBoard xM";
@@ -29,13 +29,13 @@
 
                 heartbeat {
                         label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -57,6 +57,26 @@
                 ti,mcbsp = <&mcbsp2>;
                 ti,codec = <&twl_audio>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                user {
+                        label = "user";
+                        gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+
+        };
+};
+
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x0e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot2.gpio_4 */
+                >;
+        };
 };
 
 &i2c1 {
@@ -75,7 +95,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
@@ -126,3 +147,22 @@
         mode = <3>;
         power = <50>;
 };
+
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                >;
+        };
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 6eec69997607..dfd83103657a 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3 BeagleBoard";
@@ -28,18 +28,18 @@
                 compatible = "gpio-leds";
                 pmu_stat {
                         label = "beagleboard::pmu_stat";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                 };
 
                 heartbeat {
                         label = "beagleboard::usr0";
-                        gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
+                        gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "beagleboard::usr1";
-                        gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
+                        gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -71,6 +71,26 @@
                 reset-supply = <&hsusb2_reset>;
                 vcc-supply = <&hsusb2_power>;
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                user {
+                        label = "user";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                        linux,code = <0x114>;
+                        gpio-key,wakeup;
+                };
+
+        };
+};
+
+&omap3_pmx_wkup {
+        gpio1_pins: pinmux_gpio1_pins {
+                pinctrl-single,pins = <
+                        0x14 (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE4) /* sys_boot5.gpio_7 */
+                >;
+        };
 };
 
 &omap3_pmx_core {
@@ -81,18 +101,25 @@
 
         hsusbb2_pins: pinmux_hsusbb2_pins {
                 pinctrl-single,pins = <
-                        0x5c0 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
-                        0x5c2 0x3  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
-                        0x5c4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
-                        0x5c6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
-                        0x5c8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
-                        0x5cA 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
-                        0x1a4 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
-                        0x1a6 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
-                        0x1a8 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
-                        0x1aa 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
-                        0x1ac 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
-                        0x1ae 0x10b  /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+                        0x5c0 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x5c2 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */
+                        0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */
+                        0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */
+                        0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */
+                        0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */
+                        0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */
+                        0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */
+                        0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */
+                        0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */
+                        0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */
+                        0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3)  /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
                 >;
         };
 };
@@ -107,7 +134,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
@@ -142,3 +170,13 @@
          */
         ti,pulldowns = <0x03a1c4>;
 };
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&gpio1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gpio1_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 8a5cdcc6debd..7ef282795dd4 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 / {
         model = "TimLL OMAP3 Devkit8000";
         compatible = "timll,omap3-devkit8000", "ti,omap3";
@@ -22,21 +22,21 @@
 
                 heartbeat {
                         label = "devkit8000::led1";
-                        gpios = <&gpio6 26 0>;  /* 186 -> LED1 */
+                        gpios = <&gpio6 26 GPIO_ACTIVE_HIGH>;   /* 186 -> LED1 */
                         default-state = "on";
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "devkit8000::led2";
-                        gpios = <&gpio6 3 0>;   /* 163 -> LED2 */
+                        gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;    /* 163 -> LED2 */
                         default-state = "on";
                         linux,default-trigger = "none";
                 };
 
                 usr {
                         label = "devkit8000::led3";
-                        gpios = <&gpio6 4 0>;   /* 164 -> LED3 */
+                        gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>;    /* 164 -> LED3 */
                         default-state = "on";
                         linux,default-trigger = "usr";
                 };
@@ -80,7 +80,8 @@
         status = "disabled";
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
@@ -123,20 +124,21 @@
                 reg = <0 0 0>; /* CS0, offset 0 */
                 nand-bus-width = <16>;
 
-                gpmc,sync-clk = <0>;
-                gpmc,cs-on = <0>;
-                gpmc,cs-rd-off = <44>;
-                gpmc,cs-wr-off = <44>;
-                gpmc,adv-on = <6>;
-                gpmc,adv-rd-off = <34>;
-                gpmc,adv-wr-off = <44>;
-                gpmc,we-off = <40>;
-                gpmc,oe-off = <54>;
-                gpmc,access = <64>;
-                gpmc,rd-cycle = <82>;
-                gpmc,wr-cycle = <82>;
-                gpmc,wr-access = <40>;
-                gpmc,wr-data-mux-bus = <0>;
+                gpmc,device-nand;
+                gpmc,sync-clki-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 96d1c206a57b..7d4329d179c4 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)";
@@ -28,7 +28,7 @@
                 compatible = "gpio-leds";
                 ledb {
                         label = "omap3evm::ledb";
-                        gpios = <&twl_gpio 19 0>; /* LEDB */
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_HIGH>; /* LEDB */
                         linux,default-trigger = "default-on";
                 };
         };
@@ -44,7 +44,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index f8fe3b748c3e..bc48b114eae6 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         memory {
@@ -29,37 +29,43 @@
 &omap3_pmx_core {
         uart1_pins: pinmux_uart1_pins {
                 pinctrl-single,pins = <
-                        0x152 0x100     /* uart1_rx.uart1_rx INPUT | MODE0 */
-                        0x14c 0         /* uart1_tx.uart1_tx OUTPUT | MODE0 */
+                        0x152 (PIN_INPUT | MUX_MODE0)           /* uart1_rx.uart1_rx */
+                        0x14c (PIN_OUTPUT |MUX_MODE0)           /* uart1_tx.uart1_tx */
                 >;
         };
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0x14a 0x100     /* uart2_rx.uart2_rx INPUT | MODE0 */
-                        0x148 0         /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0x14a (PIN_INPUT | MUX_MODE0)           /* uart2_rx.uart2_rx */
+                        0x148 (PIN_OUTPUT | MUX_MODE0)          /* uart2_tx.uart2_tx */
                 >;
         };
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x16e 0x100     /* uart3_rx.uart3_rx INPUT | MODE0 */
-                        0x170 0         /* uart3_tx.uart3_tx OUTPUT | MODE0 */
+                        0x16e (PIN_INPUT | MUX_MODE0)           /* uart3_rx.uart3_rx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx.uart3_tx */
                 >;
         };
 
         mmc1_pins: pinmux_mmc1_pins {
                 pinctrl-single,pins = <
-                        0x114 0x0118    /* sdmmc1_clk.sdmmc1_clk INPUT PULLUP | MODE 0 */
-                        0x116 0x0118    /* sdmmc1_cmd.sdmmc1_cmd INPUT PULLUP | MODE 0 */
-                        0x118 0x0118    /* sdmmc1_dat0.sdmmc1_dat0 INPUT PULLUP | MODE 0 */
-                        0x11a 0x0118    /* sdmmc1_dat1.sdmmc1_dat1 INPUT PULLUP | MODE 0 */
-                        0x11c 0x0118    /* sdmmc1_dat2.sdmmc1_dat2 INPUT PULLUP | MODE 0 */
-                        0x11e 0x0118    /* sdmmc1_dat3.sdmmc1_dat3 INPUT PULLUP | MODE 0 */
-                        0x120 0x0100    /* sdmmc1_dat4.sdmmc1_dat4 INPUT | MODE 0 */
-                        0x122 0x0100    /* sdmmc1_dat5.sdmmc1_dat5 INPUT | MODE 0 */
-                        0x124 0x0100    /* sdmmc1_dat6.sdmmc1_dat6 INPUT | MODE 0 */
-                        0x126 0x0100    /* sdmmc1_dat7.sdmmc1_dat7 INPUT | MODE 0 */
+                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk.sdmmc1_clk */
+                        0x116 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_cmd.sdmmc1_cmd */
+                        0x118 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat0.sdmmc1_dat0 */
+                        0x11a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat1.sdmmc1_dat1 */
+                        0x11c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat2.sdmmc1_dat2 */
+                        0x11e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_dat3.sdmmc1_dat3 */
+                        0x120 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat4.sdmmc1_dat4 */
+                        0x122 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat5.sdmmc1_dat5 */
+                        0x124 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat6.sdmmc1_dat6 */
+                        0x126 (PIN_INPUT | MUX_MODE0)           /* sdmmc1_dat7.sdmmc1_dat7 */
+                >;
+        };
+
+        smsc911x_pins: pinmux_smsc911x_pins {
+                pinctrl-single,pins = <
+                        0x1a2 (PIN_INPUT | MUX_MODE4)           /* mcspi1_cs2.gpio_176 */
                 >;
         };
 };
@@ -80,7 +86,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e2b98490cc9a..e8c48284587c 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
         model = "IGEPv2";
@@ -19,27 +19,39 @@
                 compatible = "gpio-leds";
                 boot {
                          label = "omap3:green:boot";
-                         gpios = <&gpio1 26 0>;
+                         gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
                          default-state = "on";
                 };
 
                 user0 {
                          label = "omap3:red:user0";
-                         gpios = <&gpio1 27 0>;
+                         gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
                          default-state = "off";
                 };
 
                 user1 {
                          label = "omap3:red:user1";
-                         gpios = <&gpio1 28 0>;
+                         gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
                          default-state = "off";
                 };
 
                 user2 {
                         label = "omap3:green:user1";
-                        gpios = <&twl_gpio 19 1>;
+                        gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>;
                 };
         };
+
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
 };
 
 &i2c3 {
@@ -54,3 +66,92 @@
                 reg = <0x50>;
         };
 };
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>,
+                 <5 0 0x2c000000 0x01000000>;
+
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+
+        ethernet@5,0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&smsc911x_pins>;
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <186>;
+                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <48>;
+                gpmc,adv-wr-off-ns = <48>;
+                gpmc,oe-on-ns = <54>;
+                gpmc,oe-off-ns = <168>;
+                gpmc,we-on-ns = <54>;
+                gpmc,we-off-ns = <168>;
+                gpmc,rd-cycle-ns = <186>;
+                gpmc,wr-cycle-ns = <186>;
+                gpmc,access-ns = <114>;
+                gpmc,page-burst-access-ns = <6>;
+                gpmc,bus-turnaround-ns = <12>;
+                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,wr-data-mux-bus-ns = <90>;
+                gpmc,wr-access-ns = <186>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 8>;
+                vmmc-supply = <&vddvario>;
+                vmmc_aux-supply = <&vdd33a>;
+                reg-io-width = <4>;
+
+                smsc,save-mac-address;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 9dc48d262ffb..644d05383836 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -9,7 +9,7 @@
  * published by the Free Software Foundation.
  */
 
-/include/ "omap3-igep.dtsi"
+#include "omap3-igep.dtsi"
 
 / {
         model = "IGEP COM Module";
@@ -19,26 +19,76 @@
                 compatible = "gpio-leds";
                 boot {
                          label = "omap3:green:boot";
-                         gpios = <&twl_gpio 13 1>;
+                         gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
                          default-state = "on";
                 };
 
                 user0 {
                          label = "omap3:red:user0";
-                         gpios = <&twl_gpio 18 1>; /* LEDA */
+                         gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */
                          default-state = "off";
                 };
 
                 user1 {
                          label = "omap3:green:user1";
-                         gpios = <&twl_gpio 19 1>; /* LEDB */
+                         gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */
                          default-state = "off";
                 };
 
                 user2 {
                          label = "omap3:red:user1";
-                         gpios = <&gpio1 16 1>;
+                         gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
                          default-state = "off";
                 };
         };
 };
+
+&gpmc {
+        ranges = <0 0 0x00000000 0x20000000>;
+
+        nand@0,0 {
+                linux,mtd-name= "micron,mt29c4g96maz";
+                reg = <0 0 0>;
+                nand-bus-width = <16>;
+                ti,nand-ecc-opt = "bch8";
+
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <44>;
+                gpmc,cs-wr-off-ns = <44>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <34>;
+                gpmc,adv-wr-off-ns = <44>;
+                gpmc,we-off-ns = <40>;
+                gpmc,oe-off-ns = <54>;
+                gpmc,access-ns = <64>;
+                gpmc,rd-cycle-ns = <82>;
+                gpmc,wr-cycle-ns = <82>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                partition@0 {
+                        label = "SPL";
+                        reg = <0 0x100000>;
+                };
+                partition@0x80000 {
+                        label = "U-Boot";
+                        reg = <0x100000 0x180000>;
+                };
+                partition@0x1c0000 {
+                        label = "Environment";
+                        reg = <0x280000 0x100000>;
+                };
+                partition@0x280000 {
+                        label = "Kernel";
+                        reg = <0x380000 0x300000>;
+                };
+                partition@0x780000 {
+                        label = "Filesystem";
+                        reg = <0x680000 0x1f980000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-overo.dtsi b/arch/arm/boot/dts/omap3-overo.dtsi
index a626c50041f6..8f1abec78275 100644
--- a/arch/arm/boot/dts/omap3-overo.dtsi
+++ b/arch/arm/boot/dts/omap3-overo.dtsi
@@ -11,7 +11,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         pwmleds {
@@ -21,6 +21,7 @@
                         label = "overo:blue:COM";
                         pwms = <&twl_pwmled 1 7812500>;
                         max-brightness = <127>;
+                        linux,default-trigger = "mmc0";
                 };
         };
 
@@ -49,7 +50,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 /* i2c2 pins are used for gpio */
 &i2c2 {
@@ -77,3 +79,17 @@
         mode = <3>;
         power = <50>;
 };
+
+&omap3_pmx_core {
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
diff --git a/arch/arm/boot/dts/omap3-tobi.dts b/arch/arm/boot/dts/omap3-tobi.dts
index a13d12de77ff..7e4ad2aec37a 100644
--- a/arch/arm/boot/dts/omap3-tobi.dts
+++ b/arch/arm/boot/dts/omap3-tobi.dts
@@ -10,7 +10,7 @@
  * Tobi expansion board is manufactured by Gumstix Inc.
  */
 
-/include/ "omap3-overo.dtsi"
+#include "omap3-overo.dtsi"
 
 / {
         model = "TI OMAP3 Gumstix Overo on Tobi";
@@ -20,10 +20,58 @@
                 compatible = "gpio-leds";
                 heartbeat {
                         label = "overo:red:gpio21";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        vddvario: regulator-vddvario {
+                  compatible = "regulator-fixed";
+                  regulator-name = "vddvario";
+                  regulator-always-on;
+        };
+
+        vdd33a: regulator-vdd33a {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
+};
+
+&gpmc {
+        ranges = <5 0 0x2c000000 0x1000000>;    /* CS5 */
+
+        ethernet@5,0 {
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0 0xff>;
+                bank-width = <2>;
+
+                gpmc,mux-add-data;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <42>;
+                gpmc,cs-wr-off-ns = <36>;
+                gpmc,adv-on-ns = <6>;
+                gpmc,adv-rd-off-ns = <12>;
+                gpmc,adv-wr-off-ns = <12>;
+                gpmc,oe-on-ns = <0>;
+                gpmc,oe-off-ns = <42>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <36>;
+                gpmc,rd-cycle-ns = <60>;
+                gpmc,wr-cycle-ns = <54>;
+                gpmc,access-ns = <36>;
+                gpmc,page-burst-access-ns = <0>;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <18>;
+                gpmc,wr-access-ns = <42>;
+                gpmc,cycle2cycle-samecsen;
+                gpmc,cycle2cycle-diffcsen;
+
+                interrupt-parent = <&gpio6>;
+                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;   /* GPIO 176 */
+                reg-io-width = <4>;
+        };
 };
 
 &i2c3 {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99ba6e14ebf3..7d95cda1fae4 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -8,7 +8,11 @@
  * kind, whether express or implied.
  */
 
-/include/ "skeleton.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/omap.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap3430", "ti,omap3";
@@ -21,8 +25,13 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index 144ae43453c4..e2249bcc3e63 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap34xx.dtsi"
+#include "omap34xx.dtsi"
 
 / {
         model = "TI OMAP3430 SDP";
@@ -28,7 +28,8 @@
         };
 };
 
-/include/ "twl4030.dtsi"
+#include "twl4030.dtsi"
+#include "twl4030_omap3.dtsi"
 
 &mmc1 {
         vmmc-supply = <&vmmc1>;
@@ -105,7 +106,6 @@
                 nand-bus-width = <8>;
 
                 ti,nand-ecc-opt = "sw";
-                gpmc,device-nand;
                 gpmc,cs-on-ns = <0>;
                 gpmc,cs-rd-off-ns = <36>;
                 gpmc,cs-wr-off-ns = <36>;
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 75ed4ae2e631..5355d6173748 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
         cpus {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index f3447bc1b032..f8b3765eb9be 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap3.dtsi"
+#include "omap3.dtsi"
 
 / {
         aliases {
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
index e30cdf0f5ac1..133f1b74e8ae 100644
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -7,14 +7,14 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60deb52b..faa95b5b242e 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -5,7 +5,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "elpida_ecb240abacn.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 PandaBoard";
@@ -16,17 +16,22 @@
                 reg = <0x80000000 0x40000000>; /* 1 GB */
         };
 
-        leds {
+        leds: leds {
                 compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <
+                        &led_wkgpio_pins
+                >;
+
                 heartbeat {
                         label = "pandaboard::status1";
-                        gpios = <&gpio1 7 0>;
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
 
                 mmc {
                         label = "pandaboard::status2";
-                        gpios = <&gpio1 8 0>;
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "mmc0";
                 };
         };
@@ -54,85 +59,180 @@
                         "AFML", "Line In",
                         "AFMR", "Line In";
         };
+
+        /*
+         * Temp hack: Need to be replaced with the proper gpio-controlled
+         * reset driver as soon it will be merged.
+         * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
+         */
+        /* HS USB Port 1 RESET */
+        hsusb1_reset: hsusb1_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 30 0>;   /* gpio_62 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Port 1 Power */
+        hsusb1_power: hsusb1_power_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb1_vbus";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 1 0>;    /* gpio_1 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+                /*
+                 * boot-on is required along with always-on as the
+                 * regulator framework doesn't enable the regulator
+                 * if boot-on is not there.
+                 */
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb1_reset>;
+                vcc-supply = <&hsusb1_power>;
+        /**
+         * FIXME:
+         * put the right clock phandle here when available
+         *      clocks = <&auxclk3>;
+         *      clock-names = "main_clk";
+         */
+                clock-frequency = <19200000>;
+        };
+};
+
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
+                >;
+        };
 };
 
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &mcbsp1_pins
                         &dss_hdmi_pins
                         &tpd12s015_pins
+                        &hsusbb1_pins
         >;
 
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
+                >;
+        };
+
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)   /* hdq_sio.gpio_127 */
+                        0x160 (PIN_INPUT | MUX_MODE0)   /* sys_nirq2.sys_nirq2 */
                 >;
         };
 
         mcpdm_pins: pinmux_mcpdm_pins {
                 pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        0xca (PIN_INPUT_PULLUP   | MUX_MODE0)   /* abe_pdm_frame.abe_pdm_frame */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                 >;
         };
 
         mcbsp1_pins: pinmux_mcbsp1_pins {
                 pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-                        0xc2 0x8                /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                 >;
         };
 
         dss_hdmi_pins: pinmux_dss_hdmi_pins {
                 pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                 >;
         };
 
         tpd12s015_pins: pinmux_tpd12s015_pins {
                 pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
+                >;
+        };
+
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        0x84 (PIN_OUTPUT | MUX_MODE4)           /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
                 >;
         };
 
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                 >;
         };
 
         i2c2_pins: pinmux_i2c2_pins {
                 pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                 >;
         };
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                 >;
         };
 
         i2c4_pins: pinmux_i2c4_pins {
                 pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
+                >;
+        };
+};
+
+&omap4_pmx_wkup {
+        led_wkgpio_pins: pinmux_leds_wkpins {
+                pinctrl-single,pins = <
+                        0x1a (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk7 */
+                        0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
                 >;
         };
 };
@@ -145,18 +245,18 @@
 
         twl: twl@48 {
                 reg = <0x48>;
-                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                /* IRQ# = 7 */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
                 reg = <0x4b>;
-                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                /* IRQ# = 119 */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                 interrupt-parent = <&gic>;
-                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+                ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>;  /* gpio line 127 */
 
                 vio-supply = <&v1v8>;
                 v2v1-supply = <&v2v1>;
@@ -164,7 +264,7 @@
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         pinctrl-names = "default";
@@ -249,3 +349,11 @@
         mode = <3>;
         power = <50>;
 };
+
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index f1d8c217ce12..56c435468e94 100644
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap4460.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap4460.dtsi"
+#include "omap4-panda-common.dtsi"
 
 /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
 &sound {
@@ -29,8 +29,36 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
+
+&omap4_pmx_core {
+        led_gpio_pins: gpio_led_pmx {
+                pinctrl-single,pins = <
+                        0xb6 (PIN_OUTPUT | MUX_MODE3)   /* gpio_110 */
+                >;
+        };
+};
+
+&led_wkgpio_pins {
+        pinctrl-single,pins = <
+                0x1c (PIN_OUTPUT | MUX_MODE3)   /* gpio_wk8 */
+        >;
+};
+
+&leds {
+        pinctrl-0 = <
+                &led_gpio_pins
+                &led_wkgpio_pins
+        >;
+
+        heartbeat {
+                gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
+        };
+        mmc {
+                gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index f8b221f0168e..6189a8b77d7f 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -7,5 +7,5 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "omap4-panda-common.dtsi"
+#include "omap443x.dtsi"
+#include "omap4-panda-common.dtsi"
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
index b4a40ffbce31..aad5dda0f469 100644
--- a/arch/arm/boot/dts/omap4-sdp-es23plus.dts
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -5,13 +5,13 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-/include/ "omap4-sdp.dts"
+#include "omap4-sdp.dts"
 
 /* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
 &dss_hdmi_pins {
         pinctrl-single,pins = <
-                0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                0x5c 0x100      /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
-                0x5e 0x100      /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+                0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                0x5c (PIN_INPUT | MUX_MODE0)            /* hdmi_scl.hdmi_scl */
+                0x5e (PIN_INPUT | MUX_MODE0)            /* hdmi_sda.hdmi_sda */
                 >;
 };
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd58063..7951b4ea500a 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -7,8 +7,8 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
-/include/ "elpida_ecb240abacn.dtsi"
+#include "omap443x.dtsi"
+#include "elpida_ecb240abacn.dtsi"
 
 / {
         model = "TI OMAP4 SDP board";
@@ -41,42 +41,42 @@
                 compatible = "gpio-leds";
                 debug0 {
                         label = "omap4:green:debug0";
-                        gpios = <&gpio2 29 0>; /* 61 */
+                        gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
                 };
 
                 debug1 {
                         label = "omap4:green:debug1";
-                        gpios = <&gpio1 30 0>; /* 30 */
+                        gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
                 };
 
                 debug2 {
                         label = "omap4:green:debug2";
-                        gpios = <&gpio1 7 0>; /* 7 */
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
                 };
 
                 debug3 {
                         label = "omap4:green:debug3";
-                        gpios = <&gpio1 8 0>; /* 8 */
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
                 };
 
                 debug4 {
                         label = "omap4:green:debug4";
-                        gpios = <&gpio2 18 0>; /* 50 */
+                        gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
                 };
 
                 user1 {
                         label = "omap4:blue:user";
-                        gpios = <&gpio6 9 0>; /* 169 */
+                        gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
                 };
 
                 user2 {
                         label = "omap4:red:user";
-                        gpios = <&gpio6 10 0>; /* 170 */
+                        gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
                 };
 
                 user3 {
                         label = "omap4:green:user";
-                        gpios = <&gpio5 11 0>; /* 139 */
+                        gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
                 };
         };
 
@@ -142,9 +142,23 @@
         };
 };
 
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6030_wkup_pins
+        >;
+
+        twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
+                pinctrl-single,pins = <
+                        0x14 (PIN_OUTPUT | MUX_MODE2)           /* fref_clk0_out.sys_drm_msecure */
+                >;
+        };
+};
+
 &omap4_pmx_core {
         pinctrl-names = "default";
         pinctrl-0 = <
+                        &twl6030_pins
                         &twl6040_pins
                         &mcpdm_pins
                         &dmic_pins
@@ -156,123 +170,129 @@
 
         uart2_pins: pinmux_uart2_pins {
                 pinctrl-single,pins = <
-                        0xd8 0x118      /* uart2_cts.uart2_cts INPUT_PULLUP | MODE0 */
-                        0xda 0          /* uart2_rts.uart2_rts OUTPUT | MODE0 */
-                        0xdc 0x118      /* uart2_rx.uart2_rx INPUT_PULLUP | MODE0 */
-                        0xde 0          /* uart2_tx.uart2_tx OUTPUT | MODE0 */
+                        0xd8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_cts.uart2_cts */
+                        0xda (PIN_OUTPUT | MUX_MODE0)           /* uart2_rts.uart2_rts */
+                        0xdc (PIN_INPUT_PULLUP | MUX_MODE0)     /* uart2_rx.uart2_rx */
+                        0xde (PIN_OUTPUT | MUX_MODE0)           /* uart2_tx.uart2_tx */
                 >;
         };
 
         uart3_pins: pinmux_uart3_pins {
                 pinctrl-single,pins = <
-                        0x100 0x118     /* uart3_cts_rctx.uart3_cts_rctx INPUT_PULLUP | MODE0 */
-                        0x102 0         /* uart3_rts_sd.uart3_rts_sd OUTPUT | MODE0 */
-                        0x104 0x100     /* uart3_rx_irrx.uart3_rx_irrx INPUT | MODE0 */
-                        0x106 0         /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
+                        0x100 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart3_cts_rctx.uart3_cts_rctx */
+                        0x102 (PIN_OUTPUT | MUX_MODE0)          /* uart3_rts_sd.uart3_rts_sd */
+                        0x104 (PIN_INPUT | MUX_MODE0)           /* uart3_rx_irrx.uart3_rx_irrx */
+                        0x106 (PIN_OUTPUT | MUX_MODE0)          /* uart3_tx_irtx.uart3_tx_irtx */
                 >;
         };
 
         uart4_pins: pinmux_uart4_pins {
                 pinctrl-single,pins = <
-                        0x11c 0x100     /* uart4_rx.uart4_rx INPUT | MODE0 */
-                        0x11e 0         /* uart4_tx.uart4_tx OUTPUT | MODE0 */
+                        0x11c (PIN_INPUT | MUX_MODE0)           /* uart4_rx.uart4_rx */
+                        0x11e (PIN_OUTPUT | MUX_MODE0)          /* uart4_tx.uart4_tx */
+                >;
+        };
+
+        twl6030_pins: pinmux_twl6030_pins {
+                pinctrl-single,pins = <
+                        0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0)        /* sys_nirq1.sys_nirq1 */
                 >;
         };
 
         twl6040_pins: pinmux_twl6040_pins {
                 pinctrl-single,pins = <
-                        0xe0 0x3        /* hdq_sio.gpio_127 OUTPUT | MODE3 */
-                        0x160 0x100     /* sys_nirq2.sys_nirq2 INPUT | MODE0 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE3)           /* hdq_sio.gpio_127 */
+                        0x160 (PIN_INPUT | MUX_MODE0)           /* sys_nirq2.sys_nirq2 */
                 >;
         };
 
         mcpdm_pins: pinmux_mcpdm_pins {
                 pinctrl-single,pins = <
-                        0xc6 0x108      /* abe_pdm_ul_data.abe_pdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0xc8 0x108      /* abe_pdm_dl_data.abe_pdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0xca 0x118      /* abe_pdm_frame.abe_pdm_frame INPUT PULLUP | MODE0 */
-                        0xcc 0x108      /* abe_pdm_lb_clk.abe_pdm_lb_clk INPUT PULLDOWN | MODE0 */
-                        0xce 0x108      /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
+                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        0xca (PIN_INPUT_PULLUP | MUX_MODE0)     /* abe_pdm_frame.abe_pdm_frame */
+                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
                 >;
         };
 
         dmic_pins: pinmux_dmic_pins {
                 pinctrl-single,pins = <
-                        0xd0 0          /* abe_dmic_clk1.abe_dmic_clk1 OUTPUT | MODE0 */
-                        0xd2 0x100      /* abe_dmic_din1.abe_dmic_din1 INPUT | MODE0 */
-                        0xd4 0x100      /* abe_dmic_din2.abe_dmic_din2 INPUT | MODE0 */
-                        0xd6 0x100      /* abe_dmic_din3.abe_dmic_din3 INPUT | MODE0 */
+                        0xd0 (PIN_OUTPUT | MUX_MODE0)           /* abe_dmic_clk1.abe_dmic_clk1 */
+                        0xd2 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din1.abe_dmic_din1 */
+                        0xd4 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din2.abe_dmic_din2 */
+                        0xd6 (PIN_INPUT | MUX_MODE0)            /* abe_dmic_din3.abe_dmic_din3 */
                 >;
         };
 
         mcbsp1_pins: pinmux_mcbsp1_pins {
                 pinctrl-single,pins = <
-                        0xbe 0x100      /* abe_mcbsp1_clkx.abe_mcbsp1_clkx INPUT | MODE0 */
-                        0xc0 0x108      /* abe_mcbsp1_dr.abe_mcbsp1_dr INPUT PULLDOWN | MODE0 */
-                        0xc2 0x8        /* abe_mcbsp1_dx.abe_mcbsp1_dx OUTPUT PULLDOWN | MODE0 */
-                        0xc4 0x100      /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                 >;
         };
 
         mcbsp2_pins: pinmux_mcbsp2_pins {
                 pinctrl-single,pins = <
-                        0xb6 0x100      /* abe_mcbsp2_clkx.abe_mcbsp2_clkx INPUT | MODE0 */
-                        0xb8 0x108      /* abe_mcbsp2_dr.abe_mcbsp2_dr INPUT PULLDOWN | MODE0 */
-                        0xba 0x8        /* abe_mcbsp2_dx.abe_mcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-                        0xbc 0x100      /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
+                        0xb6 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
+                        0xb8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp2_dr.abe_mcbsp2_dr */
+                        0xba (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp2_dx.abe_mcbsp2_dx */
+                        0xbc (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
                 >;
         };
 
         mcspi1_pins: pinmux_mcspi1_pins {
                 pinctrl-single,pins = <
-                        0xf2 0x100      /*  mcspi1_clk.mcspi1_clk INPUT | MODE0 */
-                        0xf4 0x100      /*  mcspi1_somi.mcspi1_somi INPUT | MODE0 */
-                        0xf6 0x100      /*  mcspi1_simo.mcspi1_simo INPUT | MODE0 */
-                        0xf8 0x100      /*  mcspi1_cs0.mcspi1_cs0 INPUT | MODE0*/
+                        0xf2 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_clk.mcspi1_clk */
+                        0xf4 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_somi.mcspi1_somi */
+                        0xf6 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_simo.mcspi1_simo */
+                        0xf8 (PIN_INPUT | MUX_MODE0)            /*  mcspi1_cs0.mcspi1_cs0 */
                 >;
         };
 
         dss_hdmi_pins: pinmux_dss_hdmi_pins {
                 pinctrl-single,pins = <
-                        0x5a 0x118      /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
-                        0x5c 0x118      /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
-                        0x5e 0x118      /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
+                        0x5a (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_cec.hdmi_cec */
+                        0x5c (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_scl.hdmi_scl */
+                        0x5e (PIN_INPUT_PULLUP | MUX_MODE0)     /* hdmi_sda.hdmi_sda */
                 >;
         };
 
         tpd12s015_pins: pinmux_tpd12s015_pins {
                 pinctrl-single,pins = <
-                        0x22 0x3        /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
-                        0x48 0x3        /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
-                        0x58 0x10b      /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
+                        0x22 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a17.gpio_41 */
+                        0x48 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_nbe1.gpio_60 */
+                        0x58 (PIN_INPUT_PULLDOWN | MUX_MODE3)   /* hdmi_hpd.gpio_63 */
                 >;
         };
 
         i2c1_pins: pinmux_i2c1_pins {
                 pinctrl-single,pins = <
-                        0xe2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe4 0x118       /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
                 >;
         };
 
         i2c2_pins: pinmux_i2c2_pins {
                 pinctrl-single,pins = <
-                        0xe6 0x118        /* i2c2_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xe8 0x118        /* i2c2_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
                 >;
         };
 
         i2c3_pins: pinmux_i2c3_pins {
                 pinctrl-single,pins = <
-                        0xea 0x118        /* i2c3_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xec 0x118     /* i2c3_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
                 >;
         };
 
         i2c4_pins: pinmux_i2c4_pins {
                 pinctrl-single,pins = <
-                        0xee 0x118        /* i2c4_scl PULLUP | INPUTENABLE | MODE0 */
-                        0xf0 0x118     /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
+                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
                 >;
         };
 };
@@ -286,7 +306,7 @@
         twl: twl@48 {
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 
@@ -294,7 +314,7 @@
                 compatible = "ti,twl6040";
                 reg = <0x4b>;
                 /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
-                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
                 interrupt-parent = <&gic>;
                 ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
 
@@ -316,7 +336,7 @@
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         pinctrl-names = "default";
@@ -375,7 +395,7 @@
                 spi-max-frequency = <24000000>;
                 reg = <0>;
                 interrupt-parent = <&gpio2>;
-                interrupts = <2 8>; /* gpio line 34, low triggered */
+                interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
                 vdd-supply = <&vdd_eth>;
         };
 };
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 7e04103779c4..b41269e871dd 100644
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
@@ -7,7 +7,7 @@
  */
 /dts-v1/;
 
-/include/ "omap443x.dtsi"
+#include "omap443x.dtsi"
 
 / {
         model = "Variscite OMAP4 SOM";
@@ -34,12 +34,12 @@
         twl: twl@48 {
                 reg = <0x48>;
                 /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
 };
 
-/include/ "twl6030.dtsi"
+#include "twl6030.dtsi"
 
 &i2c2 {
         clock-frequency = <400000>;
@@ -68,7 +68,7 @@
                 spi-max-frequency = <24000000>;
                 reg = <0>;
                 interrupt-parent = <&gpio6>;
-                interrupts = <11 8>; /* gpio line 171, low triggered */
+                interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */
                 vdd-supply = <&vdd_eth>;
         };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 2a5642882c8a..22d9f2b593d4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -6,15 +6,11 @@
  * published by the Free Software Foundation.
  */
 
-/*
- * Carveout for multimedia usecases
- * It should be the last 48MB of the first 512MB memory part
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         compatible = "ti,omap4430", "ti,omap4";
@@ -28,13 +24,20 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         next-level-cache = <&L2>;
+                        reg = <0x0>;
                 };
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         next-level-cache = <&L2>;
+                        reg = <0x1>;
                 };
         };
 
@@ -56,7 +59,7 @@
         local-timer@0x48240600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x48240600 0x20>;
-                interrupts = <1 13 0x304>;
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         /*
@@ -97,8 +100,8 @@
                 reg = <0x44000000 0x1000>,
                       <0x44800000 0x2000>,
                       <0x45000000 0x1000>;
-                interrupts = <0 9 0x4>,
-                             <0 10 0x4>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
                 counter32k: counter@4a304000 {
                         compatible = "ti,omap-counter32k";
@@ -126,10 +129,10 @@
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
-                                     <0 13 0x4>,
-                                     <0 14 0x4>,
-                                     <0 15 0x4>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
                         #dma-channels = <32>;
                         #dma-requests = <127>;
@@ -138,7 +141,7 @@
                 gpio1: gpio@4a310000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4a310000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio1";
                         ti,gpio-always-on;
                         gpio-controller;
@@ -150,7 +153,7 @@
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -161,7 +164,7 @@
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -172,7 +175,7 @@
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -183,7 +186,7 @@
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -194,7 +197,7 @@
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -207,7 +210,7 @@
                         reg = <0x50000000 0x1000>;
                         #address-cells = <2>;
                         #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                         gpmc,num-cs = <8>;
                         gpmc,num-waitpins = <4>;
                         ti,hwmods = "gpmc";
@@ -216,7 +219,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -224,7 +227,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -232,7 +235,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -240,7 +243,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -248,7 +251,7 @@
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -257,7 +260,7 @@
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -266,7 +269,7 @@
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -275,7 +278,7 @@
                 i2c4: i2c@48350000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48350000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -284,7 +287,7 @@
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -304,7 +307,7 @@
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -319,7 +322,7 @@
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -331,7 +334,7 @@
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -343,7 +346,7 @@
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -354,7 +357,7 @@
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                         dmas = <&sdma 47>, <&sdma 48>;
@@ -364,7 +367,7 @@
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                         dmas = <&sdma 77>, <&sdma 78>;
@@ -374,7 +377,7 @@
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                         dmas = <&sdma 57>, <&sdma 58>;
@@ -384,7 +387,7 @@
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                         dmas = <&sdma 59>, <&sdma 60>;
@@ -394,7 +397,7 @@
                 wdt2: wdt@4a314000 {
                         compatible = "ti,omap4-wdt", "ti,omap3-wdt";
                         reg = <0x4a314000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -403,7 +406,7 @@
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mcpdm";
                         dmas = <&sdma 65>,
                                <&sdma 66>;
@@ -415,7 +418,7 @@
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "dmic";
                         dmas = <&sdma 67>;
                         dma-names = "up_link";
@@ -426,7 +429,7 @@
                         reg = <0x40122000 0xff>, /* MPU private access */
                               <0x49022000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp1";
@@ -440,7 +443,7 @@
                         reg = <0x40124000 0xff>, /* MPU private access */
                               <0x49024000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp2";
@@ -454,7 +457,7 @@
                         reg = <0x40126000 0xff>, /* MPU private access */
                               <0x49026000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp3";
@@ -467,7 +470,7 @@
                         compatible = "ti,omap4-mcbsp";
                         reg = <0x48096000 0xff>; /* L4 Interconnect */
                         reg-names = "mpu";
-                        interrupts = <0 16 0x4>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp4";
@@ -479,7 +482,7 @@
                 keypad: keypad@4a31c000 {
                         compatible = "ti,omap4-keypad";
                         reg = <0x4a31c000 0x80>;
-                        interrupts = <0 120 0x4>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                         reg-names = "mpu";
                         ti,hwmods = "kbd";
                 };
@@ -487,7 +490,7 @@
                 emif1: emif@4c000000 {
                         compatible = "ti,emif-4d";
                         reg = <0x4c000000 0x100>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "emif1";
                         phy-type = <1>;
                         hw-caps-read-idle-ctrl;
@@ -498,7 +501,7 @@
                 emif2: emif@4d000000 {
                         compatible = "ti,emif-4d";
                         reg = <0x4d000000 0x100>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "emif2";
                         phy-type = <1>;
                         hw-caps-read-idle-ctrl;
@@ -523,7 +526,7 @@
                 timer1: timer@4a318000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x4a318000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer1";
                         ti,timer-alwon;
                 };
@@ -531,21 +534,21 @@
                 timer2: timer@48032000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer2";
                 };
 
                 timer3: timer@48034000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer3";
                 };
 
                 timer4: timer@48036000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer4";
                 };
 
@@ -553,7 +556,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x40138000 0x80>,
                               <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
                 };
@@ -562,7 +565,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013a000 0x80>,
                               <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
                         ti,timer-dsp;
                 };
@@ -571,7 +574,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013c000 0x80>,
                               <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
                         ti,timer-dsp;
                 };
@@ -580,7 +583,7 @@
                         compatible = "ti,omap4430-timer";
                         reg = <0x4013e000 0x80>,
                               <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
                         ti,timer-pwm;
                         ti,timer-dsp;
@@ -589,7 +592,7 @@
                 timer9: timer@4803e000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer9";
                         ti,timer-pwm;
                 };
@@ -597,7 +600,7 @@
                 timer10: timer@48086000 {
                         compatible = "ti,omap3430-timer";
                         reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer10";
                         ti,timer-pwm;
                 };
@@ -605,7 +608,7 @@
                 timer11: timer@48088000 {
                         compatible = "ti,omap4430-timer";
                         reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
@@ -613,7 +616,7 @@
                 usbhstll: usbhstll@4a062000 {
                         compatible = "ti,usbhs-tll";
                         reg = <0x4a062000 0x1000>;
-                        interrupts = <0 78 0x4>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "usb_tll_hs";
                 };
 
@@ -629,14 +632,14 @@
                                 compatible = "ti,ohci-omap3", "usb-ohci";
                                 reg = <0x4a064800 0x400>;
                                 interrupt-parent = <&gic>;
-                                interrupts = <0 76 0x4>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
                         usbhsehci: ehci@4a064c00 {
                                 compatible = "ti,ehci-omap", "usb-ehci";
                                 reg = <0x4a064c00 0x400>;
                                 interrupt-parent = <&gic>;
-                                interrupts = <0 77 0x4>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
                         };
                 };
 
@@ -651,7 +654,7 @@
                 usb_otg_hs: usb_otg_hs@4a0ab000 {
                         compatible = "ti,omap4-musb";
                         reg = <0x4a0ab000 0x7ff>;
-                        interrupts = <0 92 0x4>, <0 93 0x4>;
+                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "mc", "dma";
                         ti,hwmods = "usb_otg_hs";
                         usb-phy = <&usb2_phy>;
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index cccf39af4925..bcf455efe18d 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -8,7 +8,7 @@
  * kind, whether express or implied.
  */
 
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
         cpus {
@@ -24,4 +24,10 @@
                         clock-latency = <300000>; /* From legacy driver */
                 };
         };
+
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4>;
+                compatible = "ti,omap4430-bandgap";
+        };
 };
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 2cf227c86099..c2f0f39b5a24 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -7,7 +7,7 @@
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
  */
-/include/ "omap4.dtsi"
+#include "omap4.dtsi"
 
 / {
         cpus {
@@ -25,8 +25,17 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 54 0x4>,
-                             <0 55 0x4>;
+                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                 ti,hwmods = "debugss";
         };
+
+        bandgap {
+                reg = <0x4a002260 0x4
+                       0x4a00232C 0x4
+                       0x4a002378 0x18>;
+                compatible = "ti,omap4460-bandgap";
+                interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
+                gpios = <&gpio3 22 0>; /* tshut */
+        };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
deleted file mode 100644
index 982acd19477d..000000000000
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-
-/include/ "omap5.dtsi"
-/include/ "samsung_k3pe0e000b.dtsi"
-
-/ {
-        model = "TI OMAP5 EVM board";
-        compatible = "ti,omap5-evm", "ti,omap5";
-
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x7F000000>; /* 2032 MB */
-        };
-
-        vmmcsd_fixed: fixedregulator-mmcsd {
-                compatible = "regulator-fixed";
-                regulator-name = "vmmcsd_fixed";
-                regulator-min-microvolt = <3000000>;
-                regulator-max-microvolt = <3000000>;
-        };
-
-};
-
-&omap5_pmx_core {
-        pinctrl-names = "default";
-        pinctrl-0 = <
-                        &twl6040_pins
-                        &mcpdm_pins
-                        &dmic_pins
-                        &mcbsp1_pins
-                        &mcbsp2_pins
-        >;
-
-        twl6040_pins: pinmux_twl6040_pins {
-                pinctrl-single,pins = <
-                        0x18a 0x6       /* perslimbus2_clock.gpio5_145 OUTPUT | MODE6 */
-                >;
-        };
-
-        mcpdm_pins: pinmux_mcpdm_pins {
-                pinctrl-single,pins = <
-                        0x142 0x108     /* abe_clks.abe_clks INPUT PULLDOWN | MODE0 */
-                        0x15c 0x108     /* abemcpdm_ul_data.abemcpdm_ul_data INPUT PULLDOWN | MODE0 */
-                        0x15e 0x108     /* abemcpdm_dl_data.abemcpdm_dl_data INPUT PULLDOWN | MODE0 */
-                        0x160 0x118     /* abemcpdm_frame.abemcpdm_frame INPUT PULLUP | MODE0 */
-                        0x162 0x108     /* abemcpdm_lb_clk.abemcpdm_lb_clk INPUT PULLDOWN | MODE0 */
-                >;
-        };
-
-        dmic_pins: pinmux_dmic_pins {
-                pinctrl-single,pins = <
-                        0x144 0x100     /* abedmic_din1.abedmic_din1 INPUT | MODE0 */
-                        0x146 0x100     /* abedmic_din2.abedmic_din2 INPUT | MODE0 */
-                        0x148 0x100     /* abedmic_din3.abedmic_din3 INPUT | MODE0 */
-                        0x14a 0         /* abedmic_clk1.abedmic_clk1 OUTPUT | MODE0 */
-                >;
-        };
-
-        mcbsp1_pins: pinmux_mcbsp1_pins {
-                pinctrl-single,pins = <
-                        0x14c 0x101     /* abedmic_clk2.abemcbsp1_fsx INPUT | MODE1 */
-                        0x14e 0x9       /* abedmic_clk3.abemcbsp1_dx OUTPUT PULLDOWN | MODE1 */
-                        0x150 0x101     /* abeslimbus1_clock.abemcbsp1_clkx INPUT | MODE0 */
-                        0x152 0x109     /* abeslimbus1_data.abemcbsp1_dr INPUT PULLDOWN | MODE1 */
-                >;
-        };
-
-        mcbsp2_pins: pinmux_mcbsp2_pins {
-                pinctrl-single,pins = <
-                        0x154 0x108     /* abemcbsp2_dr.abemcbsp2_dr INPUT PULLDOWN | MODE0 */
-                        0x156 0x8       /* abemcbsp2_dx.abemcbsp2_dx OUTPUT PULLDOWN | MODE0 */
-                        0x158 0x100     /* abemcbsp2_fsx.abemcbsp2_fsx INPUT | MODE0 */
-                        0x15a 0x100     /* abemcbsp2_clkx.abemcbsp2_clkx INPUT | MODE0 */
-                >;
-        };
-
-        i2c1_pins: pinmux_i2c1_pins {
-                pinctrl-single,pins = <
-                        0x1b2 0x118        /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
-                        0x1b4 0x118        /* i2c1_sda PULLUP | INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c2_pins: pinmux_i2c2_pins {
-                pinctrl-single,pins = <
-                        0x178 0x100        /* i2c2_scl INPUTENABLE | MODE0 */
-                        0x17a 0x100        /* i2c2_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c3_pins: pinmux_i2c3_pins {
-                pinctrl-single,pins = <
-                        0x13a 0x100        /* i2c3_scl INPUTENABLE | MODE0 */
-                        0x13c 0x100     /* i2c3_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c4_pins: pinmux_i2c4_pins {
-                pinctrl-single,pins = <
-                        0xb8 0x100        /* i2c4_scl INPUTENABLE | MODE0 */
-                        0xba 0x100     /* i2c4_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        i2c5_pins: pinmux_i2c5_pins {
-                pinctrl-single,pins = <
-                        0x184 0x100        /* i2c5_scl INPUTENABLE | MODE0 */
-                        0x186 0x100     /* i2c5_sda INPUTENABLE | MODE0 */
-                >;
-        };
-
-        mcspi2_pins: pinmux_mcspi2_pins {
-                pinctrl-single,pins = <
-                        0xbc 0x100      /*  MCSPI2_CLK INPUTENABLE | MODE0 */
-                        0xbe 0x100      /*  MCSPI2_SIMO INPUTENABLE | MODE0 */
-                        0xc0 0x118      /*  MCSPI2_SOMI PULLUP | INPUTENABLE | MODE0*/
-                        0xc2 0x0        /*  MCSPI2_CS MODE0*/
-                >;
-        };
-
-        mcspi3_pins: pinmux_mcspi3_pins {
-                pinctrl-single,pins = <
-                        0x78 0x101      /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x7a 0x101      /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                        0x7c 0x101      /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x7e 0x101      /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                >;
-        };
-
-        mcspi4_pins: pinmux_mcspi4_pins {
-                pinctrl-single,pins = <
-                        0x164 0x101     /*  MCSPI2_CLK INPUTENABLE | MODE1 */
-                        0x168 0x101     /*  MCSPI2_SIMO INPUTENABLE | MODE1 */
-                        0x16a 0x101     /*  MCSPI2_SOMI INPUTENABLE | MODE1 */
-                        0x16c 0x101     /*  MCSPI2_CS INPUTENABLE | MODE1 */
-                >;
-        };
-};
-
-&mmc1 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <4>;
-};
-
-&mmc2 {
-        vmmc-supply = <&vmmcsd_fixed>;
-        bus-width = <8>;
-        ti,non-removable;
-};
-
-&mmc3 {
-        bus-width = <4>;
-        ti,non-removable;
-};
-
-&mmc4 {
-        status = "disabled";
-};
-
-&mmc5 {
-        status = "disabled";
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&i2c2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c2_pins>;
-
-        clock-frequency = <400000>;
-
-        /* Pressure Sensor */
-        bmp085@77 {
-                compatible = "bosch,bmp085";
-                reg = <0x77>;
-        };
-};
-
-&i2c3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c3_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&i2c4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c4_pins>;
-
-        clock-frequency = <400000>;
-
-        /* Temperature Sensor */
-        tmp102@48{
-                compatible = "ti,tmp102";
-                reg = <0x48>;
-        };
-};
-
-&i2c5 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c5_pins>;
-
-        clock-frequency = <400000>;
-};
-
-&keypad {
-        keypad,num-rows = <8>;
-        keypad,num-columns = <8>;
-        linux,keymap = <0x02020073      /* VOLUP */
-                        0x02030072      /* VOLDOWM */
-                        0x020400e7      /* SEND */
-                        0x02050066      /* HOME */
-                        0x0206006b      /* END */
-                        0x020700d9>;    /* SEARCH */
-        linux,input-no-autorepeat;
-};
-
-&mcbsp3 {
-        status = "disabled";
-};
-
-&emif1 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-
-&emif2 {
-        cs1-used;
-        device-handle = <&samsung_K3PE0E000B>;
-};
-
-&mcspi1 {
-
-};
-
-&mcspi2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi2_pins>;
-};
-
-&mcspi3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi3_pins>;
-};
-
-&mcspi4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mcspi4_pins>;
-};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
new file mode 100644
index 000000000000..08b72678abff
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -0,0 +1,485 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "TI OMAP5 uEVM board";
+        compatible = "ti,omap5-uevm", "ti,omap5";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x7F000000>; /* 2032 MB */
+        };
+
+        vmmcsd_fixed: fixedregulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+
+        /* HS USB Port 2 RESET */
+        hsusb2_reset: hsusb2_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb2_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb2_reset>;
+        /**
+          * FIXME
+          * Put the right clock phandle here when available
+          *     clocks = <&auxclk1>;
+          *     clock-names = "main_clk";
+          */
+                clock-frequency = <19200000>;
+        };
+
+        /* HS USB Port 3 RESET */
+        hsusb3_reset: hsusb3_reset_reg {
+                compatible = "regulator-fixed";
+                regulator-name = "hsusb3_reset";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+
+        /* HS USB Host PHY on PORT 3 */
+        hsusb3_phy: hsusb3_phy {
+                compatible = "usb-nop-xceiv";
+                reset-supply = <&hsusb3_reset>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "omap5:blue:usr1";
+                        gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+        };
+};
+
+&omap5_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &twl6040_pins
+                        &mcpdm_pins
+                        &dmic_pins
+                        &mcbsp1_pins
+                        &mcbsp2_pins
+                        &usbhost_pins
+                        &led_gpio_pins
+        >;
+
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        0x18a (PIN_OUTPUT | MUX_MODE6)  /* perslimbus2_clock.gpio5_145 */
+                >;
+        };
+
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        0x142 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abe_clks.abe_clks */
+                        0x15c (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_ul_data.abemcpdm_ul_data */
+                        0x15e (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_dl_data.abemcpdm_dl_data */
+                        0x160 (PIN_INPUT_PULLUP | MUX_MODE0)    /* abemcpdm_frame.abemcpdm_frame */
+                        0x162 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcpdm_lb_clk.abemcpdm_lb_clk */
+                >;
+        };
+
+        dmic_pins: pinmux_dmic_pins {
+                pinctrl-single,pins = <
+                        0x144 (PIN_INPUT | MUX_MODE0)           /* abedmic_din1.abedmic_din1 */
+                        0x146 (PIN_INPUT | MUX_MODE0)           /* abedmic_din2.abedmic_din2 */
+                        0x148 (PIN_INPUT | MUX_MODE0)           /* abedmic_din3.abedmic_din3 */
+                        0x14a (PIN_OUTPUT | MUX_MODE0)          /* abedmic_clk1.abedmic_clk1 */
+                >;
+        };
+
+        mcbsp1_pins: pinmux_mcbsp1_pins {
+                pinctrl-single,pins = <
+                        0x14c (PIN_INPUT | MUX_MODE1)           /* abedmic_clk2.abemcbsp1_fsx */
+                        0x14e (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
+                        0x150 (PIN_INPUT | MUX_MODE1)           /* abeslimbus1_clock.abemcbsp1_clkx */
+                        0x152 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* abeslimbus1_data.abemcbsp1_dr */
+                >;
+        };
+
+        mcbsp2_pins: pinmux_mcbsp2_pins {
+                pinctrl-single,pins = <
+                        0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* abemcbsp2_dr.abemcbsp2_dr */
+                        0x156 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
+                        0x158 (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_fsx.abemcbsp2_fsx */
+                        0x15a (PIN_INPUT | MUX_MODE0)           /* abemcbsp2_clkx.abemcbsp2_clkx */
+                >;
+        };
+
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        0x1b2 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_scl */
+                        0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0)    /* i2c1_sda */
+                >;
+        };
+
+        i2c5_pins: pinmux_i2c5_pins {
+                pinctrl-single,pins = <
+                        0x184 (PIN_INPUT | MUX_MODE0)           /* i2c5_scl */
+                        0x186 (PIN_INPUT | MUX_MODE0)           /* i2c5_sda */
+                >;
+        };
+
+        mcspi2_pins: pinmux_mcspi2_pins {
+                pinctrl-single,pins = <
+                        0xbc (PIN_INPUT | MUX_MODE0)            /*  mcspi2_clk */
+                        0xbe (PIN_INPUT | MUX_MODE0)            /*  mcspi2_simo */
+                        0xc0 (PIN_INPUT_PULLUP | MUX_MODE0)     /*  mcspi2_somi */
+                        0xc2 (PIN_OUTPUT | MUX_MODE0)           /*  mcspi2_cs */
+                >;
+        };
+
+        mcspi3_pins: pinmux_mcspi3_pins {
+                pinctrl-single,pins = <
+                        0x78 (PIN_INPUT | MUX_MODE1)            /*  mcspi2_somi */
+                        0x7a (PIN_INPUT | MUX_MODE1)            /*  mcspi2_cs */
+                        0x7c (PIN_INPUT | MUX_MODE1)            /*  mcspi2_simo */
+                        0x7e (PIN_INPUT | MUX_MODE1)            /*  mcspi2_clk */
+                >;
+        };
+
+        mcspi4_pins: pinmux_mcspi4_pins {
+                pinctrl-single,pins = <
+                        0x164 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_clk */
+                        0x168 (PIN_INPUT | MUX_MODE1)           /*  mcspi2_simo */
+                        0x16a (PIN_INPUT | MUX_MODE1)           /*  mcspi2_somi */
+                        0x16c (PIN_INPUT | MUX_MODE1)           /*  mcspi2_cs */
+                >;
+        };
+
+        usbhost_pins: pinmux_usbhost_pins {
+                pinctrl-single,pins = <
+                        0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
+                        0x86 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
+
+                        0x19e (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
+                        0x1a0 (PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
+
+                        0x70 (PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
+                        0x6e (PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
+                >;
+        };
+
+        led_gpio_pins: pinmux_led_gpio_pins {
+                pinctrl-single,pins = <
+                        0x196 (PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
+                >;
+        };
+
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        0x60 (PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x62 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
+                        0x64 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
+                        0x66 (PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
+                >;
+        };
+
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        0x19a (PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
+                        0x19c (PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
+                >;
+        };
+
+        uart5_pins: pinmux_uart5_pins {
+                pinctrl-single,pins = <
+                        0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
+                        0x172 (PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
+                        0x174 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
+                        0x176 (PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
+                >;
+        };
+
+};
+
+&omap5_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &usbhost_wkup_pins
+        >;
+
+        usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
+                pinctrl-single,pins = <
+                        0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
+                >;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <4>;
+};
+
+&mmc2 {
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc3 {
+        bus-width = <4>;
+        ti,non-removable;
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        status = "disabled";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+
+        clock-frequency = <400000>;
+
+        palmas: palmas@48 {
+                compatible = "ti,palmas";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                interrupt-parent = <&gic>;
+                reg = <0x48>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+
+                palmas_pmic {
+                        compatible = "ti,palmas-pmic";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <14 IRQ_TYPE_NONE>;
+                        interrupt-name = "short-irq";
+
+                        ti,ldo6-vibrator;
+
+                        regulators {
+                                smps123_reg: smps123 {
+                                        regulator-name = "smps123";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps45_reg: smps45 {
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps6_reg: smps6 {
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps7_reg: smps7 {
+                                        regulator-name = "smps7";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps8_reg: smps8 {
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                smps9_reg: smps9 {
+                                        regulator-name = "smps9";
+                                        regulator-min-microvolt = <2100000>;
+                                        regulator-max-microvolt = <2100000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ti,smps-range = <0x80>;
+                                };
+
+                                smps10_reg: smps10 {
+                                        regulator-name = "smps10";
+                                        regulator-min-microvolt = <5000000>;
+                                        regulator-max-microvolt = <5000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo1_reg: ldo1 {
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo2_reg: ldo2 {
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <2900000>;
+                                        regulator-max-microvolt = <2900000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo3_reg: ldo3 {
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo4_reg: ldo4 {
+                                        regulator-name = "ldo4";
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo5_reg: ldo5 {
+                                        regulator-name = "ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo6_reg: ldo6 {
+                                        regulator-name = "ldo6";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo7_reg: ldo7 {
+                                        regulator-name = "ldo7";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo8_reg: ldo8 {
+                                        regulator-name = "ldo8";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldo9_reg: ldo9 {
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldoln_reg: ldoln {
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                ldousb_reg: ldousb {
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3250000>;
+                                        regulator-max-microvolt = <3250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
+
+&i2c5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c5_pins>;
+
+        clock-frequency = <400000>;
+};
+
+&mcbsp3 {
+        status = "disabled";
+};
+
+&usbhshost {
+        port2-mode = "ehci-hsic";
+        port3-mode = "ehci-hsic";
+};
+
+&usbhsehci {
+        phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+
+&mcspi1 {
+
+};
+
+&mcspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi2_pins>;
+};
+
+&mcspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi3_pins>;
+};
+
+&mcspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi4_pins>;
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+};
+
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart5_pins>;
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff825828..e643620417a9 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -7,15 +7,11 @@
  * Based on "omap4.dtsi"
  */
 
-/*
- * Carveout for multimedia usecases
- * It should be the last 48MB of the first 512MB memory part
- * In theory, it should not even exist. That zone should be reserved
- * dynamically during the .reserve callback.
- */
-/memreserve/ 0x9d000000 0x03000000;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/omap.h>
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
 
 / {
         #address-cells = <1>;
@@ -34,21 +30,28 @@
         };
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
+                        reg = <0x0>;
                 };
                 cpu@1 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a15";
+                        reg = <0x1>;
                 };
         };
 
         timer {
                 compatible = "arm,armv7-timer";
-                /* PPI secure/nonsecure IRQ, active low level-sensitive */
-                interrupts = <1 13 0x308>,
-                             <1 14 0x308>,
-                             <1 11 0x308>,
-                             <1 10 0x308>;
+                /* PPI secure/nonsecure IRQ */
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
                 clock-frequency = <6144000>;
         };
 
@@ -90,8 +93,8 @@
                 reg = <0x44000000 0x2000>,
                       <0x44800000 0x3000>,
                       <0x45000000 0x4000>;
-                interrupts = <0 9 0x4>,
-                             <0 10 0x4>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
@@ -119,10 +122,10 @@
                 sdma: dma-controller@4a056000 {
                         compatible = "ti,omap4430-sdma";
                         reg = <0x4a056000 0x1000>;
-                        interrupts = <0 12 0x4>,
-                                     <0 13 0x4>,
-                                     <0 14 0x4>,
-                                     <0 15 0x4>;
+                        interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                         #dma-cells = <1>;
                         #dma-channels = <32>;
                         #dma-requests = <127>;
@@ -131,7 +134,7 @@
                 gpio1: gpio@4ae10000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4ae10000 0x200>;
-                        interrupts = <0 29 0x4>;
+                        interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio1";
                         ti,gpio-always-on;
                         gpio-controller;
@@ -143,7 +146,7 @@
                 gpio2: gpio@48055000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48055000 0x200>;
-                        interrupts = <0 30 0x4>;
+                        interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio2";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -154,7 +157,7 @@
                 gpio3: gpio@48057000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48057000 0x200>;
-                        interrupts = <0 31 0x4>;
+                        interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio3";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -165,7 +168,7 @@
                 gpio4: gpio@48059000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48059000 0x200>;
-                        interrupts = <0 32 0x4>;
+                        interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio4";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -176,7 +179,7 @@
                 gpio5: gpio@4805b000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805b000 0x200>;
-                        interrupts = <0 33 0x4>;
+                        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio5";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -187,7 +190,7 @@
                 gpio6: gpio@4805d000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x4805d000 0x200>;
-                        interrupts = <0 34 0x4>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio6";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -198,7 +201,7 @@
                 gpio7: gpio@48051000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48051000 0x200>;
-                        interrupts = <0 35 0x4>;
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio7";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -209,7 +212,7 @@
                 gpio8: gpio@48053000 {
                         compatible = "ti,omap4-gpio";
                         reg = <0x48053000 0x200>;
-                        interrupts = <0 121 0x4>;
+                        interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "gpio8";
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -222,7 +225,7 @@
                         reg = <0x50000000 0x1000>;
                         #address-cells = <2>;
                         #size-cells = <1>;
-                        interrupts = <0 20 0x4>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                         gpmc,num-cs = <8>;
                         gpmc,num-waitpins = <4>;
                         ti,hwmods = "gpmc";
@@ -231,7 +234,7 @@
                 i2c1: i2c@48070000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48070000 0x100>;
-                        interrupts = <0 56 0x4>;
+                        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c1";
@@ -240,7 +243,7 @@
                 i2c2: i2c@48072000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48072000 0x100>;
-                        interrupts = <0 57 0x4>;
+                        interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c2";
@@ -249,7 +252,7 @@
                 i2c3: i2c@48060000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x48060000 0x100>;
-                        interrupts = <0 61 0x4>;
+                        interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c3";
@@ -258,7 +261,7 @@
                 i2c4: i2c@4807a000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x4807a000 0x100>;
-                        interrupts = <0 62 0x4>;
+                        interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c4";
@@ -267,7 +270,7 @@
                 i2c5: i2c@4807c000 {
                         compatible = "ti,omap4-i2c";
                         reg = <0x4807c000 0x100>;
-                        interrupts = <0 60 0x4>;
+                        interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "i2c5";
@@ -276,7 +279,7 @@
                 mcspi1: spi@48098000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x48098000 0x200>;
-                        interrupts = <0 65 0x4>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi1";
@@ -296,7 +299,7 @@
                 mcspi2: spi@4809a000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x4809a000 0x200>;
-                        interrupts = <0 66 0x4>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi2";
@@ -311,7 +314,7 @@
                 mcspi3: spi@480b8000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480b8000 0x200>;
-                        interrupts = <0 91 0x4>;
+                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi3";
@@ -323,7 +326,7 @@
                 mcspi4: spi@480ba000 {
                         compatible = "ti,omap4-mcspi";
                         reg = <0x480ba000 0x200>;
-                        interrupts = <0 48 0x4>;
+                        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         ti,hwmods = "mcspi4";
@@ -335,7 +338,7 @@
                 uart1: serial@4806a000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806a000 0x100>;
-                        interrupts = <0 72 0x4>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart1";
                         clock-frequency = <48000000>;
                 };
@@ -343,7 +346,7 @@
                 uart2: serial@4806c000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806c000 0x100>;
-                        interrupts = <0 73 0x4>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart2";
                         clock-frequency = <48000000>;
                 };
@@ -351,7 +354,7 @@
                 uart3: serial@48020000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48020000 0x100>;
-                        interrupts = <0 74 0x4>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart3";
                         clock-frequency = <48000000>;
                 };
@@ -359,7 +362,7 @@
                 uart4: serial@4806e000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x4806e000 0x100>;
-                        interrupts = <0 70 0x4>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart4";
                         clock-frequency = <48000000>;
                 };
@@ -367,7 +370,7 @@
                 uart5: serial@48066000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48066000 0x100>;
-                        interrupts = <0 105 0x4>;
+                        interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart5";
                         clock-frequency = <48000000>;
                 };
@@ -375,7 +378,7 @@
                 uart6: serial@48068000 {
                         compatible = "ti,omap4-uart";
                         reg = <0x48068000 0x100>;
-                        interrupts = <0 106 0x4>;
+                        interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "uart6";
                         clock-frequency = <48000000>;
                 };
@@ -383,7 +386,7 @@
                 mmc1: mmc@4809c000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x4809c000 0x400>;
-                        interrupts = <0 83 0x4>;
+                        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc1";
                         ti,dual-volt;
                         ti,needs-special-reset;
@@ -394,7 +397,7 @@
                 mmc2: mmc@480b4000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480b4000 0x400>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc2";
                         ti,needs-special-reset;
                         dmas = <&sdma 47>, <&sdma 48>;
@@ -404,7 +407,7 @@
                 mmc3: mmc@480ad000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480ad000 0x400>;
-                        interrupts = <0 94 0x4>;
+                        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc3";
                         ti,needs-special-reset;
                         dmas = <&sdma 77>, <&sdma 78>;
@@ -414,7 +417,7 @@
                 mmc4: mmc@480d1000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d1000 0x400>;
-                        interrupts = <0 96 0x4>;
+                        interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc4";
                         ti,needs-special-reset;
                         dmas = <&sdma 57>, <&sdma 58>;
@@ -424,7 +427,7 @@
                 mmc5: mmc@480d5000 {
                         compatible = "ti,omap4-hsmmc";
                         reg = <0x480d5000 0x400>;
-                        interrupts = <0 59 0x4>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                         dmas = <&sdma 59>, <&sdma 60>;
@@ -442,7 +445,7 @@
                         reg = <0x40132000 0x7f>, /* MPU private access */
                               <0x49032000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 112 0x4>;
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "mcpdm";
                         dmas = <&sdma 65>,
                                <&sdma 66>;
@@ -454,7 +457,7 @@
                         reg = <0x4012e000 0x7f>, /* MPU private access */
                               <0x4902e000 0x7f>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 114 0x4>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "dmic";
                         dmas = <&sdma 67>;
                         dma-names = "up_link";
@@ -465,7 +468,7 @@
                         reg = <0x40122000 0xff>, /* MPU private access */
                               <0x49022000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 17 0x4>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp1";
@@ -479,7 +482,7 @@
                         reg = <0x40124000 0xff>, /* MPU private access */
                               <0x49024000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 22 0x4>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp2";
@@ -493,7 +496,7 @@
                         reg = <0x40126000 0xff>, /* MPU private access */
                               <0x49026000 0xff>; /* L3 Interconnect */
                         reg-names = "mpu", "dma";
-                        interrupts = <0 23 0x4>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
                         interrupt-names = "common";
                         ti,buffer-size = <128>;
                         ti,hwmods = "mcbsp3";
@@ -505,7 +508,7 @@
                 timer1: timer@4ae18000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4ae18000 0x80>;
-                        interrupts = <0 37 0x4>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer1";
                         ti,timer-alwon;
                 };
@@ -513,21 +516,21 @@
                 timer2: timer@48032000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48032000 0x80>;
-                        interrupts = <0 38 0x4>;
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer2";
                 };
 
                 timer3: timer@48034000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48034000 0x80>;
-                        interrupts = <0 39 0x4>;
+                        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer3";
                 };
 
                 timer4: timer@48036000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48036000 0x80>;
-                        interrupts = <0 40 0x4>;
+                        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer4";
                 };
 
@@ -535,16 +538,17 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x40138000 0x80>,
                               <0x49038000 0x80>;
-                        interrupts = <0 41 0x4>;
+                        interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer5";
                         ti,timer-dsp;
+                        ti,timer-pwm;
                 };
 
                 timer6: timer@4013a000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013a000 0x80>,
                               <0x4903a000 0x80>;
-                        interrupts = <0 42 0x4>;
+                        interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer6";
                         ti,timer-dsp;
                         ti,timer-pwm;
@@ -554,7 +558,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013c000 0x80>,
                               <0x4903c000 0x80>;
-                        interrupts = <0 43 0x4>;
+                        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer7";
                         ti,timer-dsp;
                 };
@@ -563,7 +567,7 @@
                         compatible = "ti,omap5430-timer";
                         reg = <0x4013e000 0x80>,
                               <0x4903e000 0x80>;
-                        interrupts = <0 44 0x4>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer8";
                         ti,timer-dsp;
                         ti,timer-pwm;
@@ -572,21 +576,23 @@
                 timer9: timer@4803e000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x4803e000 0x80>;
-                        interrupts = <0 45 0x4>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer9";
+                        ti,timer-pwm;
                 };
 
                 timer10: timer@48086000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48086000 0x80>;
-                        interrupts = <0 46 0x4>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer10";
+                        ti,timer-pwm;
                 };
 
                 timer11: timer@48088000 {
                         compatible = "ti,omap5430-timer";
                         reg = <0x48088000 0x80>;
-                        interrupts = <0 47 0x4>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "timer11";
                         ti,timer-pwm;
                 };
@@ -594,7 +600,7 @@
                 wdt2: wdt@4ae14000 {
                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
                         reg = <0x4ae14000 0x80>;
-                        interrupts = <0 80 0x4>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
                         ti,hwmods = "wd_timer2";
                 };
 
@@ -603,7 +609,7 @@
                         ti,hwmods       = "emif1";
                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                         reg = <0x4c000000 0x400>;
-                        interrupts = <0 110 0x4>;
+                        interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
                         hw-caps-read-idle-ctrl;
                         hw-caps-ll-interface;
                         hw-caps-temp-alert;
@@ -614,7 +620,7 @@
                         ti,hwmods       = "emif2";
                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
                         reg = <0x4d000000 0x400>;
-                        interrupts = <0 111 0x4>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                         hw-caps-read-idle-ctrl;
                         hw-caps-ll-interface;
                         hw-caps-temp-alert;
@@ -632,7 +638,7 @@
                         compatible = "ti,dwc3";
                         ti,hwmods = "usb_otg_ss";
                         reg = <0x4a020000 0x1000>;
-                        interrupts = <0 93 4>;
+                        interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                         #address-cells = <1>;
                         #size-cells = <1>;
                         utmi-mode = <2>;
@@ -640,7 +646,7 @@
                         dwc3@4a030000 {
                                 compatible = "synopsys,dwc3";
                                 reg = <0x4a030000 0x1000>;
-                                interrupts = <0 92 4>;
+                                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                                 usb-phy = <&usb2_phy>, <&usb3_phy>;
                                 tx-fifo-resize;
                         };
@@ -667,5 +673,44 @@
                                 ctrl-module = <&omap_control_usb>;
                         };
                 };
+
+                usbhstll: usbhstll@4a062000 {
+                        compatible = "ti,usbhs-tll";
+                        reg = <0x4a062000 0x1000>;
+                        interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "usb_tll_hs";
+                };
+
+                usbhshost: usbhshost@4a064000 {
+                        compatible = "ti,usbhs-host";
+                        reg = <0x4a064000 0x800>;
+                        ti,hwmods = "usb_host_hs";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbhsohci: ohci@4a064800 {
+                                compatible = "ti,ohci-omap3", "usb-ohci";
+                                reg = <0x4a064800 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
+                        usbhsehci: ehci@4a064c00 {
+                                compatible = "ti,ehci-omap", "usb-ehci";
+                                reg = <0x4a064c00 0x400>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+
+                bandgap@4a0021e0 {
+                        reg = <0x4a0021e0 0xc
+                               0x4a00232c 0xc
+                               0x4a002380 0x2c
+                               0x4a0023C0 0x3c>;
+                        interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                        compatible = "ti,omap5430-bandgap";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
index f0a8c2068ea7..533919e96eae 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x2.dtsi
@@ -18,13 +18,13 @@
         #size-cells = <1>;
 
         cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                 #size-cells = <0>;
 
-                cpu@0 {
-                        compatible = "arm,1176jz-s";
+                cpu {
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                         clock-frequency = <400000000>;
-                        reg = <0>;
                         d-cache-line-size = <32>;
                         d-cache-size = <32768>;
                         i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
index daa962d191e6..ab3e80085511 100644
--- a/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
+++ b/arch/arm/boot/dts/picoxcell-pc3x3.dtsi
@@ -18,13 +18,13 @@
         #size-cells = <1>;
 
         cpus {
-                #address-cells = <1>;
+                #address-cells = <0>;
                 #size-cells = <0>;
 
-                cpu@0 {
-                        compatible = "arm,1176jz-s";
+                cpu {
+                        compatible = "arm,arm1176jz-s";
+                        device_type = "cpu";
                         cpu-clock = <&arm_clk>, "cpu";
-                        reg = <0>;
                         d-cache-line-size = <32>;
                         d-cache-size = <32768>;
                         i-cache-line-size = <32>;
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 387fedb58988..33ffabe9c4c8 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g45.dtsi"
+#include "at91sam9g45.dtsi"
 
 / {
         model = "Ronetix pm9g45";
@@ -42,15 +42,15 @@
                                 board {
                                         pinctrl_board_nand: nand0-board {
                                                 atmel,pins =
-                                                        <3 3 0x0 0x1    /* PD3 gpio RDY pin pull_up*/
-                                                         2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
+                                                        <AT91_PIOD 3 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP      /* PD3 gpio RDY pin pull_up*/
+                                                         AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;   /* PC14 gpio enable pin pull_up */
                                         };
                                 };
 
                                 mmc {
                                         pinctrl_board_mmc: mmc0-board {
                                                 atmel,pins =
-                                                        <3 6 0x0 0x5>;  /* PD6 gpio CD pin pull_up and deglitch */
+                                                        <AT91_PIOD 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;   /* PD6 gpio CD pin pull_up and deglitch */
                                         };
                                 };
                         };
@@ -64,7 +64,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 6 0>;
+                                        cd-gpios = <&pioD 6 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -81,8 +81,8 @@
                         nand-on-flash-bbt;
                         pinctrl-0 = <&pinctrl_board_nand>;
 
-                        gpios = <&pioD 3 0
-                                 &pioC 14 0
+                        gpios = <&pioD 3 GPIO_ACTIVE_HIGH
+                                 &pioC 14 GPIO_ACTIVE_HIGH
                                  0
                                 >;
 
@@ -134,13 +134,13 @@
 
                 led0 {
                         label = "led0";
-                        gpios = <&pioD 0 1>;
+                        gpios = <&pioD 0 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "nand-disk";
                 };
 
                 led1 {
                         label = "led1";
-                        gpios = <&pioD 31 0>;
+                        gpios = <&pioD 31 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
         };
@@ -152,13 +152,13 @@
 
                 right {
                         label = "SW4";
-                        gpios = <&pioE 7 1>;
+                        gpios = <&pioE 7 GPIO_ACTIVE_LOW>;
                         linux,code = <106>;
                 };
 
                 up {
                         label = "SW3";
-                        gpios = <&pioE 8 1>;
+                        gpios = <&pioE 8 GPIO_ACTIVE_LOW>;
                         linux,code = <103>;
                 };
         };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 3329719a9412..05e9489cf95c 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -18,6 +18,8 @@
                 #size-cells = <0>;
 
                 cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0x0>;
                         d-cache-line-size = <32>;
                         i-cache-line-size = <32>;
@@ -608,7 +610,7 @@
                 };
 
                 rtc-iobg {
-                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus";
+                        compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
                         #address-cells = <1>;
                         #size-cells = <1>;
                         reg = <0x80030000 0x10000>;
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index f18aad35e8b3..a5e90f078aa9 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -23,8 +23,11 @@
         };
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,xscale";
+                #address-cells = <0>;
+                #size-cells = <0>;
+                cpu {
+                        compatible = "marvell,xscale";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index fde2a337d1ff..4ff2019c0e30 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -37,12 +37,6 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
-
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
         };
 
         timer {
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
new file mode 100644
index 000000000000..09ea22c26359
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -0,0 +1,45 @@
+/*
+ * Reference Device Tree Source for the armadillo 800 eva board
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7740.dtsi"
+
+/ {
+        model = "armadillo 800 eva reference";
+        compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
+
+        chosen {
+                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x20000000>;
+        };
+
+        reg_3p3v: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+};
+
+&i2c0 {
+        touchscreen: st1232@55 {
+                compatible = "sitronix,st1232";
+                reg = <0x55>;
+                interrupt-parent = <&irqpin1>;
+                interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 798fa35c0005..24e930643821 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,8 +14,129 @@
         compatible = "renesas,r8a7740";
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
+
+        gic: interrupt-controller@c2800000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <1>;
+                interrupt-controller;
+                reg = <0xc2800000 0x1000>,
+                      <0xc2000000 0x1000>;
+        };
+
+        /* irqpin0: IRQ0 - IRQ7 */
+        irqpin0: irqpin@e6900000 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900000 4>,
+                        <0xe6900010 4>,
+                        <0xe6900020 1>,
+                        <0xe6900040 1>,
+                        <0xe6900060 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin1: IRQ8 - IRQ15 */
+        irqpin1: irqpin@e6900004 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900004 4>,
+                        <0xe6900014 4>,
+                        <0xe6900024 1>,
+                        <0xe6900044 1>,
+                        <0xe6900064 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin2: IRQ16 - IRQ23 */
+        irqpin2: irqpin@e6900008 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe6900008 4>,
+                        <0xe6900018 4>,
+                        <0xe6900028 1>,
+                        <0xe6900048 1>,
+                        <0xe6900068 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        /* irqpin3: IRQ24 - IRQ31 */
+        irqpin3: irqpin@e690000c {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xe690000c 4>,
+                        <0xe690001c 4>,
+                        <0xe690002c 1>,
+                        <0xe690004c 1>,
+                        <0xe690006c 1>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4
+                              0 149 0x4>;
+        };
+
+        i2c0: i2c@fff20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xfff20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 201 0x4
+                              0 202 0x4
+                              0 203 0x4
+                              0 204 0x4>;
+        };
+
+        i2c1: i2c@e6c20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,rmobile-iic";
+                reg = <0xe6c20000 0x425>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 70 0x4
+                              0 71 0x4
+                              0 72 0x4
+                              0 73 0x4>;
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index fe5c6f213271..7f146c6bf756 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,23 @@
                       <0xf0000100 0x100>;
         };
 
+        irqpin0: irqpin@fe780010 {
+                compatible = "renesas,intc-irqpin";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0xfe78001c 4>,
+                        <0xfe780010 4>,
+                        <0xfe780024 4>,
+                        <0xfe780044 4>,
+                        <0xfe780064 4>;
+                interrupt-parent = <&gic>;
+                interrupts = <0 27 0x4
+                                0 28 0x4
+                                0 29 0x4
+                                0 30 0x4>;
+                sense-bitfield-width = <2>;
+        };
+
         i2c0: i2c@0xffc70000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7a1711027e41..339d9b11721c 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -36,12 +36,6 @@
                         <0 0xf1004000 0 0x2000>,
                         <0 0xf1006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
-
-                gic-cpuif@4 {
-                        compatible = "arm,gic-cpuif";
-                        cpuif-id = <4>;
-                        cpu = <&cpu0>;
-                };
         };
 
         timer {
diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi
new file mode 100644
index 000000000000..6e307fc4c451
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                        #clock-cells = <0>;
+                };
+
+                xin24m: xin24m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                        #clock-cells = <0>;
+                };
+
+                dummy48m: dummy48m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <48000000>;
+                        #clock-cells = <0>;
+                };
+
+                dummy150m: dummy150m {
+                        compatible = "fixed-clock";
+                        clock-frequency = <150000000>;
+                        #clock-cells = <0>;
+                };
+
+                clk_gates0: gate-clk@200000d0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d0 0x4>;
+                        clocks = <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_core_periph", "gate_cpu_gpll",
+                                "gate_ddrphy", "gate_aclk_cpu",
+                                "gate_hclk_cpu", "gate_pclk_cpu",
+                                "gate_atclk_cpu", "gate_i2s0",
+                                "gate_i2s0_frac", "gate_i2s1",
+                                "gate_i2s1_frac", "gate_i2s2",
+                                "gate_i2s2_frac", "gate_spdif",
+                                "gate_spdif_frac", "gate_testclk";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates1: gate-clk@200000d4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d4 0x4>;
+                        clocks = <&xin24m>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&dummy>, <&xin24m>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>,
+                                 <&xin24m>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_timer0", "gate_timer1",
+                                "gate_timer2", "gate_jtag",
+                                "gate_aclk_lcdc1_src", "gate_otgphy0",
+                                "gate_otgphy1", "gate_ddr_gpll",
+                                "gate_uart0", "gate_frac_uart0",
+                                "gate_uart1", "gate_frac_uart1",
+                                "gate_uart2", "gate_frac_uart2",
+                                "gate_uart3", "gate_frac_uart3";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates2: gate-clk@200000d8 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000d8 0x4>;
+                        clocks = <&clk_gates2 1>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&clk_gates2 3>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy48m>,
+                                 <&dummy>, <&dummy48m>,
+                                 <&dummy>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_periph_src", "gate_aclk_periph",
+                                "gate_hclk_periph", "gate_pclk_periph",
+                                "gate_smc", "gate_mac",
+                                "gate_hsadc", "gate_hsadc_frac",
+                                "gate_saradc", "gate_spi0",
+                                "gate_spi1", "gate_mmc0",
+                                "gate_mac_lbtest", "gate_mmc1",
+                                "gate_emmc", "gate_tsadc";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates3: gate-clk@200000dc {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000dc 0x4>;
+                        clocks = <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
+                                "gate_dclk_lcdc1", "gate_pclkin_cif0",
+                                "gate_pclkin_cif1", "reserved",
+                                "reserved", "gate_cif0_out",
+                                "gate_cif1_out", "gate_aclk_vepu",
+                                "gate_hclk_vepu", "gate_aclk_vdpu",
+                                "gate_hclk_vdpu", "gate_gpu_src",
+                                "reserved", "gate_xin27m";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates4: gate-clk@200000e0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e0 0x4>;
+                        clocks = <&clk_gates2 2>, <&clk_gates2 3>,
+                                 <&clk_gates2 1>, <&clk_gates2 1>,
+                                 <&clk_gates2 1>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates2 2>,
+                                 <&clk_gates0 4>, <&clk_gates0 4>,
+                                 <&clk_gates0 3>, <&clk_gates0 3>,
+                                 <&clk_gates0 3>, <&clk_gates2 3>,
+                                 <&clk_gates0 4>;
+
+                        clock-output-names =
+                                "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
+                                "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
+                                "gate_aclk_pei_niu", "gate_hclk_usb_peri",
+                                "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
+                                "gate_hclk_cpubus", "gate_hclk_ahb2apb",
+                                "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
+                                "gate_aclk_intmem", "gate_pclk_tsadc",
+                                "gate_hclk_hdmi";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates5: gate-clk@200000e4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e4 0x4>;
+                        clocks = <&clk_gates0 3>, <&clk_gates2 1>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 4>, <&clk_gates0 5>,
+                                 <&clk_gates2 1>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates4 5>,
+                                 <&clk_gates4 5>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_aclk_dmac1", "gate_aclk_dmac2",
+                                "gate_pclk_efuse", "gate_pclk_tzpc",
+                                "gate_pclk_grf", "gate_pclk_pmu",
+                                "gate_hclk_rom", "gate_pclk_ddrupctl",
+                                "gate_aclk_smc", "gate_hclk_nandc",
+                                "gate_hclk_mmc0", "gate_hclk_mmc1",
+                                "gate_hclk_emmc", "gate_hclk_otg0",
+                                "gate_hclk_otg1", "gate_aclk_gpu";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates6: gate-clk@200000e8 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000e8 0x4>;
+                        clocks = <&clk_gates3 0>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates0 4>, <&clk_gates3 0>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates3 0>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates1 4>,
+                                 <&clk_gates0 4>, <&clk_gates3 0>,
+                                 <&dummy>, <&dummy>;
+
+                        clock-output-names =
+                                "gate_aclk_lcdc0", "gate_hclk_lcdc0",
+                                "gate_hclk_lcdc1", "gate_aclk_lcdc1",
+                                "gate_hclk_cif0", "gate_aclk_cif0",
+                                "gate_hclk_cif1", "gate_aclk_cif1",
+                                "gate_aclk_ipp", "gate_hclk_ipp",
+                                "gate_hclk_rga", "gate_aclk_rga",
+                                "gate_hclk_vio_bus", "gate_aclk_vio0",
+                                "gate_aclk_vcodec", "gate_shclk_vio_h2h";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates7: gate-clk@200000ec {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000ec 0x4>;
+                        clocks = <&clk_gates2 2>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates0 4>,
+                                 <&clk_gates0 4>, <&clk_gates2 2>,
+                                 <&clk_gates2 2>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>;
+
+                        clock-output-names =
+                                "gate_hclk_emac", "gate_hclk_spdif",
+                                "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
+                                "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
+                                "gate_hclk_pidf", "gate_pclk_timer0",
+                                "gate_pclk_timer1", "gate_pclk_timer2",
+                                "gate_pclk_pwm01", "gate_pclk_pwm23",
+                                "gate_pclk_spi0", "gate_pclk_spi1",
+                                "gate_pclk_saradc", "gate_pclk_wdt";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates8: gate-clk@200000f0 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000f0 0x4>;
+                        clocks = <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&clk_gates2 3>, <&clk_gates0 5>,
+                                 <&clk_gates0 5>, <&clk_gates0 5>,
+                                 <&clk_gates2 3>, <&clk_gates2 3>,
+                                 <&dummy>, <&clk_gates0 5>;
+
+                        clock-output-names =
+                                "gate_pclk_uart0", "gate_pclk_uart1",
+                                "gate_pclk_uart2", "gate_pclk_uart3",
+                                "gate_pclk_i2c0", "gate_pclk_i2c1",
+                                "gate_pclk_i2c2", "gate_pclk_i2c3",
+                                "gate_pclk_i2c4", "gate_pclk_gpio0",
+                                "gate_pclk_gpio1", "gate_pclk_gpio2",
+                                "gate_pclk_gpio3", "gate_pclk_gpio4",
+                                "reserved", "gate_pclk_gpio6";
+
+                        #clock-cells = <1>;
+                };
+
+                clk_gates9: gate-clk@200000f4 {
+                        compatible = "rockchip,rk2928-gate-clk";
+                        reg = <0x200000f4 0x4>;
+                        clocks = <&dummy>, <&clk_gates0 5>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>, <&clk_gates1 4>,
+                                 <&clk_gates0 5>, <&dummy>,
+                                 <&dummy>, <&dummy>,
+                                 <&dummy>;
+
+                        clock-output-names =
+                                "gate_clk_core_dbg", "gate_pclk_dbg",
+                                "gate_clk_trace", "gate_atclk",
+                                "gate_clk_l2c", "gate_aclk_vio1",
+                                "gate_pclk_publ", "gate_aclk_intmem0",
+                                "gate_aclk_intmem1", "gate_aclk_intmem2",
+                                "gate_aclk_intmem3";
+
+                        #clock-cells = <1>;
+                };
+        };
+
+};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
new file mode 100644
index 000000000000..56bfac93d3f6
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "skeleton.dtsi"
+#include "rk3066a-clocks.dtsi"
+
+/ {
+        compatible = "rockchip,rk3066a";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        next-level-cache = <&L2>;
+                        reg = <0x1>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+
+                gic: interrupt-controller@1013d000 {
+                        compatible = "arm,cortex-a9-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x1013d000 0x1000>,
+                              <0x1013c100 0x0100>;
+                };
+
+                L2: l2-cache-controller@10138000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0x10138000 0x1000>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                local-timer@1013c600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0x1013c600 0x20>;
+                        interrupts = <GIC_PPI 13 0x304>;
+                        clocks = <&dummy150m>;
+                };
+
+                timer@20038000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x20038000 0x100>;
+                        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 0>, <&clk_gates7 7>;
+                        clock-names = "timer", "pclk";
+                };
+
+                timer@2003a000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x2003a000 0x100>;
+                        interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 1>, <&clk_gates7 8>;
+                        clock-names = "timer", "pclk";
+                };
+
+                timer@2000e000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        reg = <0x2000e000 0x100>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_gates1 2>, <&clk_gates7 9>;
+                        clock-names = "timer", "pclk";
+                };
+
+                pinctrl@20008000 {
+                        compatible = "rockchip,rk3066a-pinctrl";
+                        reg = <0x20008000 0x150>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        gpio0: gpio0@20034000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20034000 0x100>;
+                                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 9>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio1: gpio1@2003c000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2003c000 0x100>;
+                                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 10>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio2: gpio2@2003e000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2003e000 0x100>;
+                                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 11>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio3: gpio3@20080000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20080000 0x100>;
+                                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 12>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio4: gpio4@20084000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x20084000 0x100>;
+                                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 13>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio6: gpio6@2000a000 {
+                                compatible = "rockchip,gpio-bank";
+                                reg = <0x2000a000 0x100>;
+                                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clk_gates8 15>;
+
+                                gpio-controller;
+                                #gpio-cells = <2>;
+
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        pcfg_pull_default: pcfg_pull_default {
+                                bias-pull-pin-default;
+                        };
+
+                        pcfg_pull_none: pcfg_pull_none {
+                                bias-disable;
+                        };
+
+                        uart0 {
+                                uart0_xfer: uart0-xfer {
+                                        rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart0_cts: uart0-cts {
+                                        rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart0_rts: uart0-rts {
+                                        rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+
+                        uart1 {
+                                uart1_xfer: uart1-xfer {
+                                        rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart1_cts: uart1-cts {
+                                        rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart1_rts: uart1-rts {
+                                        rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+
+                        uart2 {
+                                uart2_xfer: uart2-xfer {
+                                        rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                                /* no rts / cts for uart2 */
+                        };
+
+                        uart3 {
+                                uart3_xfer: uart3-xfer {
+                                        rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart3_cts: uart3-cts {
+                                        rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                uart3_rts: uart3-rts {
+                                        rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+
+                        sd0 {
+                                sd0_clk: sd0-clk {
+                                        rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd0_cmd: sd0-cmd {
+                                        rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd0_cd: sd0-cd {
+                                        rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd0_wp: sd0-wp {
+                                        rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd0_bus1: sd0-bus-width1 {
+                                        rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd0_bus4: sd0-bus-width4 {
+                                        rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+
+                        sd1 {
+                                sd1_clk: sd1-clk {
+                                        rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd1_cmd: sd1-cmd {
+                                        rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd1_cd: sd1-cd {
+                                        rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd1_wp: sd1-wp {
+                                        rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd1_bus1: sd1-bus-width1 {
+                                        rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+
+                                sd1_bus4: sd1-bus-width4 {
+                                        rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
+                                                        <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
+                                        rockchip,config = <&pcfg_pull_default>;
+                                };
+                        };
+                };
+
+                uart0: serial@10124000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x10124000 0x400>;
+                        interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 8>;
+                        status = "disabled";
+                };
+
+                uart1: serial@10126000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x10126000 0x400>;
+                        interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 10>;
+                        status = "disabled";
+                };
+
+                uart2: serial@20064000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x20064000 0x400>;
+                        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 12>;
+                        status = "disabled";
+                };
+
+                uart3: serial@20068000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x20068000 0x400>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <1>;
+                        clocks = <&clk_gates1 14>;
+                        status = "disabled";
+                };
+
+                dwmmc@10214000 {
+                        compatible = "rockchip,rk2928-dw-mshc";
+                        reg = <0x10214000 0x1000>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        clocks = <&clk_gates5 10>, <&clk_gates2 11>;
+                        clock-names = "biu", "ciu";
+
+                        status = "disabled";
+                };
+
+                dwmmc@10218000 {
+                        compatible = "rockchip,rk2928-dw-mshc";
+                        reg = <0x10218000 0x1000>;
+                        interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        clocks = <&clk_gates5 11>, <&clk_gates2 13>;
+                        clock-names = "biu", "ciu";
+
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
new file mode 100644
index 000000000000..527e3193817f
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Samsung S3C2416 pinctrl settings
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&pinctrl_0 {
+        /*
+         * Pin banks
+         */
+
+        gpa: gpa {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpc: gpc {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpd: gpd {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpe: gpe {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpf: gpf {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gpg: gpg {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+
+        gph: gph {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpj: gpj {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpk: gpk {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpl: gpl {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        gpm: gpm {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        /*
+         * Pin groups
+         */
+
+        uart0_data: uart0-data {
+                samsung,pins = "gph-0", "gph-1";
+                samsung,pin-function = <2>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gph-8", "gph-9";
+                samsung,pin-function = <2>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gph-2", "gph-3";
+                samsung,pin-function = <2>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gph-10", "gph-11";
+                samsung,pin-function = <2>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gph-4", "gph-5";
+                samsung,pin-function = <2>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gph-6", "gph-7";
+                samsung,pin-function = <2>;
+        };
+
+        extuart_clk: extuart-clk {
+                samsung,pins = "gph-12";
+                samsung,pin-function = <2>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpe-14", "gpe-15";
+                samsung,pin-function = <2>;
+        };
+
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpe-11", "gpe-12", "gpe-13";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpe-5";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpe-6";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_bus1: sd0-bus1 {
+                samsung,pins = "gpe-7";
+                samsung,pin-function = <2>;
+        };
+
+        sd0_bus4: sd0-bus4 {
+                samsung,pins = "gpe-8", "gpe-9", "gpe-10";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpl-8";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpl-9";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_bus1: sd1-bus1 {
+                samsung,pins = "gpl-0";
+                samsung,pin-function = <2>;
+        };
+
+        sd1_bus4: sd1-bus4 {
+                samsung,pins = "gpl-1", "gpl-2", "gpl-3";
+                samsung,pin-function = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
new file mode 100644
index 000000000000..59594cf15998
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK2416 board device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "s3c2416.dtsi"
+
+/ {
+        model = "SMDK2416";
+        compatible = "samsung,s3c2416";
+
+        memory {
+                reg =  <0x30000000 0x4000000>;
+        };
+
+        serial@50000000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart0_data>, <&uart0_fctl>;
+        };
+
+        serial@50004000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart1_data>, <&uart1_fctl>;
+        };
+
+        serial@50008000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart2_data>;
+        };
+
+        serial@5000C000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&uart3_data>;
+        };
+
+        watchdog@53000000 {
+                status = "okay";
+        };
+
+        rtc@57000000 {
+                status = "okay";
+        };
+
+        sdhci@4AC00000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd0_clk>, <&sd0_cmd>,
+                                <&sd0_bus1>, <&sd0_bus4>;
+                bus-width = <4>;
+                cd-gpios = <&gpf 1 0>;
+                cd-inverted;
+                status = "okay";
+        };
+
+        sdhci@4A800000 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&sd1_clk>, <&sd1_cmd>,
+                                <&sd1_bus1>, <&sd1_bus4>;
+                bus-width = <4>;
+                broken-cd;
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
new file mode 100644
index 000000000000..e6555bdd81b8
--- /dev/null
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -0,0 +1,79 @@
+/*
+ * Samsung's S3C2416 SoC device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "s3c24xx.dtsi"
+#include "s3c2416-pinctrl.dtsi"
+
+/ {
+        model = "Samsung S3C2416 SoC";
+        compatible = "samsung,s3c2416";
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ejs";
+                };
+        };
+
+        interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2416-irq";
+        };
+
+        pinctrl@56000000 {
+                compatible = "samsung,s3c2416-pinctrl";
+        };
+
+        serial@50000000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@50004000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@50008000 {
+                compatible = "samsung,s3c2440-uart";
+        };
+
+        serial@5000C000 {
+                compatible = "samsung,s3c2440-uart";
+                reg = <0x5000C000 0x4000>;
+                interrupts = <1 18 24 4>, <1 18 25 4>;
+                status = "disabled";
+        };
+
+        sdhci@4AC00000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4AC00000 0x100>;
+                interrupts = <0 0 21 3>;
+                status = "disabled";
+        };
+
+        sdhci@4A800000 {
+                compatible = "samsung,s3c6410-sdhci";
+                reg = <0x4A800000 0x100>;
+                interrupts = <0 0 20 3>;
+                status = "disabled";
+        };
+
+        watchdog@53000000 {
+                interrupts = <1 9 27 3>;
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2416-rtc";
+        };
+
+        i2c@54000000 {
+                compatible = "samsung,s3c2440-i2c";
+        };
+};
diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi
new file mode 100644
index 000000000000..2d1d7dc9418a
--- /dev/null
+++ b/arch/arm/boot/dts/s3c24xx.dtsi
@@ -0,0 +1,92 @@
+/*
+ * Samsung's S3C24XX family device tree source
+ *
+ * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+        compatible = "samsung,s3c24xx";
+        interrupt-parent = <&intc>;
+
+        aliases {
+                pinctrl0 = &pinctrl_0;
+        };
+
+        intc:interrupt-controller@4a000000 {
+                compatible = "samsung,s3c2410-irq";
+                reg = <0x4a000000 0x100>;
+                interrupt-controller;
+                #interrupt-cells = <4>;
+        };
+
+        pinctrl_0: pinctrl@56000000 {
+                reg = <0x56000000 0x1000>;
+
+                wakeup-interrupt-controller {
+                        compatible = "samsung,s3c2410-wakeup-eint";
+                        interrupts = <0 0 0 3>,
+                                     <0 0 1 3>,
+                                     <0 0 2 3>,
+                                     <0 0 3 3>,
+                                     <0 0 4 4>,
+                                     <0 0 5 4>;
+                };
+        };
+
+        timer@51000000 {
+                compatible = "samsung,s3c2410-pwm";
+                reg = <0x51000000 0x1000>;
+                interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
+                #pwm-cells = <4>;
+        };
+
+        serial@50000000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50000000 0x4000>;
+                interrupts = <1 28 0 4>, <1 28 1 4>;
+                status = "disabled";
+        };
+
+        serial@50004000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50004000 0x4000>;
+                interrupts = <1 23 3 4>, <1 23 4 4>;
+                status = "disabled";
+        };
+
+        serial@50008000 {
+                compatible = "samsung,s3c2410-uart";
+                reg = <0x50008000 0x4000>;
+                interrupts = <1 15 6 4>, <1 15 7 4>;
+                status = "disabled";
+        };
+
+        watchdog@53000000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x53000000 0x100>;
+                interrupts = <0 0 9 3>;
+                status = "disabled";
+        };
+
+        rtc@57000000 {
+                compatible = "samsung,s3c2410-rtc";
+                reg = <0x57000000 0x100>;
+                interrupts = <0 0 30 3>, <0 0 8 3>;
+                status = "disabled";
+        };
+
+        i2c@54000000 {
+                compatible = "samsung,s3c2410-i2c";
+                reg = <0x54000000 0x100>;
+                interrupts = <0 0 27 3>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 5000e0d42849..a1d5e25a6698 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -8,7 +8,11 @@
  * Licensed under GPLv2 or later.
  */
 
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
         model = "Atmel SAMA5D3 family SoC";
@@ -35,8 +39,12 @@
                 ssc1 = &ssc1;
         };
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a5";
+                        reg = <0x0>;
                 };
         };
 
@@ -59,8 +67,8 @@
                         mmc0: mmc@f0000000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf0000000 0x600>;
-                                interrupts = <21 4 0>;
-                                dmas = <&dma0 2 0>;
+                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
@@ -72,9 +80,12 @@
                         spi0: spi@f0004000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf0004000 0x100>;
-                                interrupts = <24 4 3>;
+                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi0>;
                                 status = "disabled";
@@ -83,7 +94,7 @@
                         ssc0: ssc@f0008000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xf0008000 0x4000>;
-                                interrupts = <38 4 4>;
+                                interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                 status = "disabled";
@@ -92,7 +103,7 @@
                         can0: can@f000c000 {
                                 compatible = "atmel,at91sam9x5-can";
                                 reg = <0xf000c000 0x300>;
-                                interrupts = <40 4 3>;
+                                interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can0_rx_tx>;
                                 status = "disabled";
@@ -101,15 +112,15 @@
                         tcb0: timer@f0010000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf0010000 0x100>;
-                                interrupts = <26 4 0>;
+                                interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         i2c0: i2c@f0014000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf0014000 0x4000>;
-                                interrupts = <18 4 6>;
-                                dmas = <&dma0 2 7>,
-                                       <&dma0 2 8>;
+                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_i2c0>;
@@ -121,9 +132,9 @@
                         i2c1: i2c@f0018000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf0018000 0x4000>;
-                                interrupts = <19 4 6>;
-                                dmas = <&dma0 2 9>,
-                                       <&dma0 2 10>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
                                 dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_i2c1>;
@@ -135,7 +146,7 @@
                         usart0: serial@f001c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf001c000 0x100>;
-                                interrupts = <12 4 5>;
+                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart0>;
                                 status = "disabled";
@@ -144,7 +155,7 @@
                         usart1: serial@f0020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf0020000 0x100>;
-                                interrupts = <13 4 5>;
+                                interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart1>;
                                 status = "disabled";
@@ -153,7 +164,7 @@
                         macb0: ethernet@f0028000 {
                                 compatible = "cdns,pc302-gem", "cdns,gem";
                                 reg = <0xf0028000 0x100>;
-                                interrupts = <34 4 3>;
+                                interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>;
                                 status = "disabled";
@@ -162,15 +173,15 @@
                         isi: isi@f0034000 {
                                 compatible = "atmel,at91sam9g45-isi";
                                 reg = <0xf0034000 0x4000>;
-                                interrupts = <37 4 5>;
+                                interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
                                 status = "disabled";
                         };
 
                         mmc1: mmc@f8000000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf8000000 0x600>;
-                                interrupts = <22 4 0>;
-                                dmas = <&dma1 2 0>;
+                                interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
@@ -182,8 +193,8 @@
                         mmc2: mmc@f8004000 {
                                 compatible = "atmel,hsmci";
                                 reg = <0xf8004000 0x600>;
-                                interrupts = <23 4 0>;
-                                dmas = <&dma1 2 1>;
+                                interrupts = <23 IRQ_TYPE_LEVEL_HIGH 0>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(1)>;
                                 dma-names = "rxtx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>;
@@ -195,9 +206,12 @@
                         spi1: spi@f8008000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
-                                compatible = "atmel,at91sam9x5-spi";
+                                compatible = "atmel,at91rm9200-spi";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <25 4 3>;
+                                interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
+                                dma-names = "tx", "rx";
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_spi1>;
                                 status = "disabled";
@@ -206,7 +220,7 @@
                         ssc1: ssc@f800c000 {
                                 compatible = "atmel,at91sam9g45-ssc";
                                 reg = <0xf800c000 0x4000>;
-                                interrupts = <39 4 4>;
+                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                 status = "disabled";
@@ -215,7 +229,7 @@
                         can1: can@f8010000 {
                                 compatible = "atmel,at91sam9x5-can";
                                 reg = <0xf8010000 0x300>;
-                                interrupts = <41 4 3>;
+                                interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_can1_rx_tx>;
                         };
@@ -223,13 +237,13 @@
                         tcb1: timer@f8014000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8014000 0x100>;
-                                interrupts = <27 4 0>;
+                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         adc0: adc@f8018000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xf8018000 0x100>;
-                                interrupts = <29 4 5>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <
                                         &pinctrl_adc0_adtrg
@@ -283,7 +297,7 @@
                         tsadcc: tsadcc@f8018000 {
                                 compatible = "atmel,at91sam9x5-tsadcc";
                                 reg = <0xf8018000 0x4000>;
-                                interrupts = <29 4 5>;
+                                interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
                                 atmel,tsadcc_clock = <300000>;
                                 atmel,filtering_average = <0x03>;
                                 atmel,pendet_debounce = <0x08>;
@@ -295,9 +309,9 @@
                         i2c2: i2c@f801c000 {
                                 compatible = "atmel,at91sam9x5-i2c";
                                 reg = <0xf801c000 0x4000>;
-                                interrupts = <20 4 6>;
-                                dmas = <&dma1 2 11>,
-                                       <&dma1 2 12>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
                                 dma-names = "tx", "rx";
                                 #address-cells = <1>;
                                 #size-cells = <0>;
@@ -307,7 +321,7 @@
                         usart2: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x100>;
-                                interrupts = <14 4 5>;
+                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart2>;
                                 status = "disabled";
@@ -316,7 +330,7 @@
                         usart3: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x100>;
-                                interrupts = <15 4 5>;
+                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_usart3>;
                                 status = "disabled";
@@ -325,7 +339,7 @@
                         macb1: ethernet@f802c000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf802c000 0x100>;
-                                interrupts = <35 4 3>;
+                                interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_macb1_rmii>;
                                 status = "disabled";
@@ -334,7 +348,7 @@
                         sha@f8034000 {
                                 compatible = "atmel,sam9g46-sha";
                                 reg = <0xf8034000 0x100>;
-                                interrupts = <42 4 0>;
+                                interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         aes@f8038000 {
@@ -346,20 +360,20 @@
                         tdes@f803c000 {
                                 compatible = "atmel,sam9g46-tdes";
                                 reg = <0xf803c000 0x100>;
-                                interrupts = <44 4 0>;
+                                interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
                         };
 
                         dma0: dma-controller@ffffe600 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffe600 0x200>;
-                                interrupts = <30 4 0>;
+                                interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
                         dma1: dma-controller@ffffe800 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffe800 0x200>;
-                                interrupts = <31 4 0>;
+                                interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
                                 #dma-cells = <2>;
                         };
 
@@ -371,7 +385,7 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <2 4 7>;
+                                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&pinctrl_dbgu>;
                                 status = "disabled";
@@ -403,202 +417,202 @@
                                 adc0 {
                                         pinctrl_adc0_adtrg: adc0_adtrg {
                                                 atmel,pins =
-                                                        <3 19 0x1 0x0>; /* PD19 periph A ADTRG */
+                                                        <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
                                         };
                                         pinctrl_adc0_ad0: adc0_ad0 {
                                                 atmel,pins =
-                                                        <3 20 0x1 0x0>; /* PD20 periph A AD0 */
+                                                        <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
                                         };
                                         pinctrl_adc0_ad1: adc0_ad1 {
                                                 atmel,pins =
-                                                        <3 21 0x1 0x0>; /* PD21 periph A AD1 */
+                                                        <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
                                         };
                                         pinctrl_adc0_ad2: adc0_ad2 {
                                                 atmel,pins =
-                                                        <3 22 0x1 0x0>; /* PD22 periph A AD2 */
+                                                        <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
                                         };
                                         pinctrl_adc0_ad3: adc0_ad3 {
                                                 atmel,pins =
-                                                        <3 23 0x1 0x0>; /* PD23 periph A AD3 */
+                                                        <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
                                         };
                                         pinctrl_adc0_ad4: adc0_ad4 {
                                                 atmel,pins =
-                                                        <3 24 0x1 0x0>; /* PD24 periph A AD4 */
+                                                        <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
                                         };
                                         pinctrl_adc0_ad5: adc0_ad5 {
                                                 atmel,pins =
-                                                        <3 25 0x1 0x0>; /* PD25 periph A AD5 */
+                                                        <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
                                         };
                                         pinctrl_adc0_ad6: adc0_ad6 {
                                                 atmel,pins =
-                                                        <3 26 0x1 0x0>; /* PD26 periph A AD6 */
+                                                        <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
                                         };
                                         pinctrl_adc0_ad7: adc0_ad7 {
                                                 atmel,pins =
-                                                        <3 27 0x1 0x0>; /* PD27 periph A AD7 */
+                                                        <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
                                         };
                                         pinctrl_adc0_ad8: adc0_ad8 {
                                                 atmel,pins =
-                                                        <3 28 0x1 0x0>; /* PD28 periph A AD8 */
+                                                        <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
                                         };
                                         pinctrl_adc0_ad9: adc0_ad9 {
                                                 atmel,pins =
-                                                        <3 29 0x1 0x0>; /* PD29 periph A AD9 */
+                                                        <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
                                         };
                                         pinctrl_adc0_ad10: adc0_ad10 {
                                                 atmel,pins =
-                                                        <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */
+                                                        <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
                                         };
                                         pinctrl_adc0_ad11: adc0_ad11 {
                                                 atmel,pins =
-                                                        <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */
+                                                        <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
                                         };
                                 };
 
                                 can0 {
                                         pinctrl_can0_rx_tx: can0_rx_tx {
                                                 atmel,pins =
-                                                        <3 14 0x3 0x0   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
-                                                         3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
+                                                        <AT91_PIOD 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */
+                                                         AT91_PIOD 15 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */
                                         };
                                 };
 
                                 can1 {
                                         pinctrl_can1_rx_tx: can1_rx_tx {
                                                 atmel,pins =
-                                                        <1 14 0x2 0x0   /* PB14 periph B RX, conflicts with GCRS */
-                                                         1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */
+                                                        <AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB14 periph B RX, conflicts with GCRS */
+                                                         AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B TX, conflicts with GCOL */
                                         };
                                 };
 
                                 dbgu {
                                         pinctrl_dbgu: dbgu-0 {
                                                 atmel,pins =
-                                                        <1 30 0x1 0x0   /* PB30 periph A */
-                                                         1 31 0x1 0x1>; /* PB31 periph A with pullup */
+                                                        <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB30 periph A */
+                                                         AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB31 periph A with pullup */
                                         };
                                 };
 
                                 i2c0 {
                                         pinctrl_i2c0: i2c0-0 {
                                                 atmel,pins =
-                                                        <0 30 0x1 0x0   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
-                                                         0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
                                         };
                                 };
 
                                 i2c1 {
                                         pinctrl_i2c1: i2c1-0 {
                                                 atmel,pins =
-                                                        <2 26 0x2 0x0   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
-                                                         2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
+                                                        <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
+                                                         AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
                                         };
                                 };
 
                                 isi {
                                         pinctrl_isi: isi-0 {
                                                 atmel,pins =
-                                                        <0 16 0x3 0x0   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
-                                                         0 17 0x3 0x0   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
-                                                         0 18 0x3 0x0   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
-                                                         0 19 0x3 0x0   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
-                                                         0 20 0x3 0x0   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
-                                                         0 21 0x3 0x0   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
-                                                         0 22 0x3 0x0   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
-                                                         0 23 0x3 0x0   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
-                                                         2 30 0x3 0x0   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
-                                                         0 31 0x3 0x0   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
-                                                         0 30 0x3 0x0   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
-                                                         2 29 0x3 0x0   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
-                                                         2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
+                                                        <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
+                                                         AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
+                                                         AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
+                                                         AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
+                                                         AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
+                                                         AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
+                                                         AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
+                                                         AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
+                                                         AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
+                                                         AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
+                                                         AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
+                                                         AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
+                                                         AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
                                         };
                                         pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
                                                 atmel,pins =
-                                                        <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */
+                                                        <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
                                         };
                                 };
 
                                 lcd {
                                         pinctrl_lcd: lcd-0 {
                                                 atmel,pins =
-                                                        <0 24 0x1 0x0   /* PA24 periph A LCDPWM */
-                                                         0 26 0x1 0x0   /* PA26 periph A LCDVSYNC */
-                                                         0 27 0x1 0x0   /* PA27 periph A LCDHSYNC */
-                                                         0 25 0x1 0x0   /* PA25 periph A LCDDISP */
-                                                         0 29 0x1 0x0   /* PA29 periph A LCDDEN */
-                                                         0 28 0x1 0x0   /* PA28 periph A LCDPCK */
-                                                         0 0 0x1 0x0    /* PA0 periph A LCDD0 pin */
-                                                         0 1 0x1 0x0    /* PA1 periph A LCDD1 pin */
-                                                         0 2 0x1 0x0    /* PA2 periph A LCDD2 pin */
-                                                         0 3 0x1 0x0    /* PA3 periph A LCDD3 pin */
-                                                         0 4 0x1 0x0    /* PA4 periph A LCDD4 pin */
-                                                         0 5 0x1 0x0    /* PA5 periph A LCDD5 pin */
-                                                         0 6 0x1 0x0    /* PA6 periph A LCDD6 pin */
-                                                         0 7 0x1 0x0    /* PA7 periph A LCDD7 pin */
-                                                         0 8 0x1 0x0    /* PA8 periph A LCDD8 pin */
-                                                         0 9 0x1 0x0    /* PA9 periph A LCDD9 pin */
-                                                         0 10 0x1 0x0   /* PA10 periph A LCDD10 pin */
-                                                         0 11 0x1 0x0   /* PA11 periph A LCDD11 pin */
-                                                         0 12 0x1 0x0   /* PA12 periph A LCDD12 pin */
-                                                         0 13 0x1 0x0   /* PA13 periph A LCDD13 pin */
-                                                         0 14 0x1 0x0   /* PA14 periph A LCDD14 pin */
-                                                         0 15 0x1 0x0   /* PA15 periph A LCDD15 pin */
-                                                         2 14 0x3 0x0   /* PC14 periph C LCDD16 pin */
-                                                         2 13 0x3 0x0   /* PC13 periph C LCDD17 pin */
-                                                         2 12 0x3 0x0   /* PC12 periph C LCDD18 pin */
-                                                         2 11 0x3 0x0   /* PC11 periph C LCDD19 pin */
-                                                         2 10 0x3 0x0   /* PC10 periph C LCDD20 pin */
-                                                         2 15 0x3 0x0   /* PC15 periph C LCDD21 pin */
-                                                         4 27 0x3 0x0   /* PE27 periph C LCDD22 pin */
-                                                         4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */
+                                                        <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA24 periph A LCDPWM */
+                                                         AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA26 periph A LCDVSYNC */
+                                                         AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA27 periph A LCDHSYNC */
+                                                         AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA25 periph A LCDDISP */
+                                                         AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA29 periph A LCDDEN */
+                                                         AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA28 periph A LCDPCK */
+                                                         AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA0 periph A LCDD0 pin */
+                                                         AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA1 periph A LCDD1 pin */
+                                                         AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA2 periph A LCDD2 pin */
+                                                         AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA3 periph A LCDD3 pin */
+                                                         AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA4 periph A LCDD4 pin */
+                                                         AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA5 periph A LCDD5 pin */
+                                                         AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA6 periph A LCDD6 pin */
+                                                         AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA7 periph A LCDD7 pin */
+                                                         AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA8 periph A LCDD8 pin */
+                                                         AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PA9 periph A LCDD9 pin */
+                                                         AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA10 periph A LCDD10 pin */
+                                                         AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA11 periph A LCDD11 pin */
+                                                         AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA12 periph A LCDD12 pin */
+                                                         AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA13 periph A LCDD13 pin */
+                                                         AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA14 periph A LCDD14 pin */
+                                                         AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PA15 periph A LCDD15 pin */
+                                                         AT91_PIOC 14 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC14 periph C LCDD16 pin */
+                                                         AT91_PIOC 13 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC13 periph C LCDD17 pin */
+                                                         AT91_PIOC 12 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC12 periph C LCDD18 pin */
+                                                         AT91_PIOC 11 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC11 periph C LCDD19 pin */
+                                                         AT91_PIOC 10 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC10 periph C LCDD20 pin */
+                                                         AT91_PIOC 15 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PC15 periph C LCDD21 pin */
+                                                         AT91_PIOE 27 AT91_PERIPH_C AT91_PINCTRL_NONE   /* PE27 periph C LCDD22 pin */
+                                                         AT91_PIOE 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PE28 periph C LCDD23 pin */
                                         };
                                 };
 
                                 macb0 {
                                         pinctrl_macb0_data_rgmii: macb0_data_rgmii {
                                                 atmel,pins =
-                                                        <1 0 0x1 0x0    /* PB0 periph A GTX0, conflicts with PWMH0 */
-                                                         1 1 0x1 0x0    /* PB1 periph A GTX1, conflicts with PWML0 */
-                                                         1 2 0x1 0x0    /* PB2 periph A GTX2, conflicts with TK1 */
-                                                         1 3 0x1 0x0    /* PB3 periph A GTX3, conflicts with TF1 */
-                                                         1 4 0x1 0x0    /* PB4 periph A GRX0, conflicts with PWMH1 */
-                                                         1 5 0x1 0x0    /* PB5 periph A GRX1, conflicts with PWML1 */
-                                                         1 6 0x1 0x0    /* PB6 periph A GRX2, conflicts with TD1 */
-                                                         1 7 0x1 0x0>;  /* PB7 periph A GRX3, conflicts with RK1 */
+                                                        <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB0 periph A GTX0, conflicts with PWMH0 */
+                                                         AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB1 periph A GTX1, conflicts with PWML0 */
+                                                         AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB2 periph A GTX2, conflicts with TK1 */
+                                                         AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB3 periph A GTX3, conflicts with TF1 */
+                                                         AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB4 periph A GRX0, conflicts with PWMH1 */
+                                                         AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB5 periph A GRX1, conflicts with PWML1 */
+                                                         AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB6 periph A GRX2, conflicts with TD1 */
+                                                         AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PB7 periph A GRX3, conflicts with RK1 */
                                         };
                                         pinctrl_macb0_data_gmii: macb0_data_gmii {
                                                 atmel,pins =
-                                                        <1 19 0x2 0x0   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
-                                                         1 20 0x2 0x0   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
-                                                         1 21 0x2 0x0   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
-                                                         1 22 0x2 0x0   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
-                                                         1 23 0x2 0x0   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
-                                                         1 24 0x2 0x0   /* PB24 periph B GRX5, conflicts with MCI1_CK */
-                                                         1 25 0x2 0x0   /* PB25 periph B GRX6, conflicts with SCK1 */
-                                                         1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */
+                                                        <AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB19 periph B GTX4, conflicts with MCI1_CDA */
+                                                         AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB20 periph B GTX5, conflicts with MCI1_DA0 */
+                                                         AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB21 periph B GTX6, conflicts with MCI1_DA1 */
+                                                         AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB22 periph B GTX7, conflicts with MCI1_DA2 */
+                                                         AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB23 periph B GRX4, conflicts with MCI1_DA3 */
+                                                         AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB24 periph B GRX5, conflicts with MCI1_CK */
+                                                         AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB25 periph B GRX6, conflicts with SCK1 */
+                                                         AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB26 periph B GRX7, conflicts with CTS1 */
                                         };
                                         pinctrl_macb0_signal_rgmii: macb0_signal_rgmii {
                                                 atmel,pins =
-                                                        <1 8 0x1 0x0    /* PB8 periph A GTXCK, conflicts with PWMH2 */
-                                                         1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
-                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
-                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
-                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
-                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
-                                                         1 18 0x1 0x0>; /* PB18 periph A G125CK */
+                                                        <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB8 periph A GTXCK, conflicts with PWMH2 */
+                                                         AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A GMDC */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A GMDIO */
+                                                         AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A G125CK */
                                         };
                                         pinctrl_macb0_signal_gmii: macb0_signal_gmii {
                                                 atmel,pins =
-                                                        <1 9 0x1 0x0    /* PB9 periph A GTXEN, conflicts with PWML2 */
-                                                         1 10 0x1 0x0   /* PB10 periph A GTXER, conflicts with RF1 */
-                                                         1 11 0x1 0x0   /* PB11 periph A GRXCK, conflicts with RD1 */
-                                                         1 12 0x1 0x0   /* PB12 periph A GRXDV, conflicts with PWMH3 */
-                                                         1 13 0x1 0x0   /* PB13 periph A GRXER, conflicts with PWML3 */
-                                                         1 14 0x1 0x0   /* PB14 periph A GCRS, conflicts with CANRX1 */
-                                                         1 15 0x1 0x0   /* PB15 periph A GCOL, conflicts with CANTX1 */
-                                                         1 16 0x1 0x0   /* PB16 periph A GMDC */
-                                                         1 17 0x1 0x0   /* PB17 periph A GMDIO */
-                                                         1 27 0x2 0x0>; /* PB27 periph B G125CKO */
+                                                        <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PB9 periph A GTXEN, conflicts with PWML2 */
+                                                         AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB10 periph A GTXER, conflicts with RF1 */
+                                                         AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB11 periph A GRXCK, conflicts with RD1 */
+                                                         AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB12 periph A GRXDV, conflicts with PWMH3 */
+                                                         AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB13 periph A GRXER, conflicts with PWML3 */
+                                                         AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB14 periph A GCRS, conflicts with CANRX1 */
+                                                         AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB15 periph A GCOL, conflicts with CANTX1 */
+                                                         AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB16 periph A GMDC */
+                                                         AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB17 periph A GMDIO */
+                                                         AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB27 periph B G125CKO */
                                         };
 
                                 };
@@ -606,252 +620,251 @@
                                 macb1 {
                                         pinctrl_macb1_rmii: macb1_rmii-0 {
                                                 atmel,pins =
-                                                        <2 0 0x1 0x0    /* PC0 periph A ETX0, conflicts with TIOA3 */
-                                                         2 1 0x1 0x0    /* PC1 periph A ETX1, conflicts with TIOB3 */
-                                                         2 2 0x1 0x0    /* PC2 periph A ERX0, conflicts with TCLK3 */
-                                                         2 3 0x1 0x0    /* PC3 periph A ERX1, conflicts with TIOA4 */
-                                                         2 4 0x1 0x0    /* PC4 periph A ETXEN, conflicts with TIOB4 */
-                                                         2 5 0x1 0x0    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
-                                                         2 6 0x1 0x0    /* PC6 periph A ERXER, conflicts with TIOA5 */
-                                                         2 7 0x1 0x0    /* PC7 periph A EREFCK, conflicts with TIOB5 */
-                                                         2 8 0x1 0x0    /* PC8 periph A EMDC, conflicts with TCLK5 */
-                                                         2 9 0x1 0x0>;  /* PC9 periph A EMDIO  */
+                                                        <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC0 periph A ETX0, conflicts with TIOA3 */
+                                                         AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC1 periph A ETX1, conflicts with TIOB3 */
+                                                         AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC2 periph A ERX0, conflicts with TCLK3 */
+                                                         AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC3 periph A ERX1, conflicts with TIOA4 */
+                                                         AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC4 periph A ETXEN, conflicts with TIOB4 */
+                                                         AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 periph A ECRSDV,conflicts with TCLK4 */
+                                                         AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 periph A ERXER, conflicts with TIOA5 */
+                                                         AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 periph A EREFCK, conflicts with TIOB5 */
+                                                         AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 periph A EMDC, conflicts with TCLK5 */
+                                                         AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;  /* PC9 periph A EMDIO  */
                                         };
                                 };
 
                                 mmc0 {
                                         pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
                                                 atmel,pins =
-                                                        <3 9 0x1 0x0    /* PD9 periph A MCI0_CK */
-                                                         3 0 0x1 0x1    /* PD0 periph A MCI0_CDA with pullup */
-                                                         3 1 0x1 0x1>;  /* PD1 periph A MCI0_DA0 with pullup */
+                                                        <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PD9 periph A MCI0_CK */
+                                                         AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
+                                                         AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD1 periph A MCI0_DA0 with pullup */
                                         };
                                         pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
                                                 atmel,pins =
-                                                        <3 2 0x1 0x1    /* PD2 periph A MCI0_DA1 with pullup */
-                                                         3 3 0x1 0x1    /* PD3 periph A MCI0_DA2 with pullup */
-                                                         3 4 0x1 0x1>;  /* PD4 periph A MCI0_DA3 with pullup */
+                                                        <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
+                                                         AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
+                                                         AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD4 periph A MCI0_DA3 with pullup */
                                         };
                                         pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
                                                 atmel,pins =
-                                                        <3 5 0x1 0x1    /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
-                                                         3 6 0x1 0x1    /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
-                                                         3 7 0x1 0x1    /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
-                                                         3 8 0x1 0x1>;  /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
+                                                        <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
+                                                         AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
+                                                         AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
+                                                         AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;       /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
                                         };
                                 };
 
                                 mmc1 {
                                         pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
                                                 atmel,pins =
-                                                        <1 24 0x1 0x0   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
-                                                         1 19 0x1 0x1   /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
-                                                         1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
+                                                        <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB24 periph A MCI1_CK, conflicts with GRX5 */
+                                                         AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
+                                                         AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
                                         };
                                         pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
                                                 atmel,pins =
-                                                        <1 21 0x1 0x1   /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
-                                                         1 22 0x1 0x1   /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
-                                                         1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
+                                                        <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
+                                                         AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
+                                                         AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
                                         };
                                 };
 
                                 mmc2 {
                                         pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 {
                                                 atmel,pins =
-                                                        <2 15 0x1 0x0   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
-                                                         2 10 0x1 0x1   /* PC10 periph A MCI2_CDA with pullup */
-                                                         2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */
+                                                        <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC15 periph A MCI2_CK, conflicts with PCK2 */
+                                                         AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC10 periph A MCI2_CDA with pullup */
+                                                         AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC11 periph A MCI2_DA0 with pullup */
                                         };
                                         pinctrl_mmc2_dat1_3: mmc2_dat1_3 {
                                                 atmel,pins =
-                                                        <2 12 0x1 0x0   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
-                                                         2 13 0x1 0x0   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
-                                                         2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
+                                                        <AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */
+                                                         AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */
+                                                         AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */
                                         };
                                 };
 
                                 nand0 {
                                         pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
                                                 atmel,pins =
-                                                        <4 21 0x1 0x1   /* PE21 periph A with pullup */
-                                                         4 22 0x1 0x1>; /* PE22 periph A with pullup */
+                                                        <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PE21 periph A with pullup */
+                                                         AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PE22 periph A with pullup */
                                         };
                                 };
 
-                                pioA: gpio@fffff200 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff200 0x100>;
-                                        interrupts = <6 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-
-                                pioB: gpio@fffff400 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff400 0x100>;
-                                        interrupts = <7 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-
-                                pioC: gpio@fffff600 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff600 0x100>;
-                                        interrupts = <8 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-
-                                pioD: gpio@fffff800 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffff800 0x100>;
-                                        interrupts = <9 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-
-                                pioE: gpio@fffffa00 {
-                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
-                                        reg = <0xfffffa00 0x100>;
-                                        interrupts = <10 4 1>;
-                                        #gpio-cells = <2>;
-                                        gpio-controller;
-                                        interrupt-controller;
-                                        #interrupt-cells = <2>;
-                                };
-
                                 spi0 {
                                         pinctrl_spi0: spi0-0 {
                                                 atmel,pins =
-                                                        <3 10 0x1 0x0   /* PD10 periph A SPI0_MISO pin */
-                                                         3 11 0x1 0x0   /* PD11 periph A SPI0_MOSI pin */
-                                                         3 12 0x1 0x0   /* PD12 periph A SPI0_SPCK pin */
-                                                         3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */
+                                                        <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD10 periph A SPI0_MISO pin */
+                                                         AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD11 periph A SPI0_MOSI pin */
+                                                         AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
                                         };
                                 };
 
                                 spi1 {
                                         pinctrl_spi1: spi1-0 {
                                                 atmel,pins =
-                                                        <2 22 0x1 0x0   /* PC22 periph A SPI1_MISO pin */
-                                                         2 23 0x1 0x0   /* PC23 periph A SPI1_MOSI pin */
-                                                         2 24 0x1 0x0   /* PC24 periph A SPI1_SPCK pin */
-                                                         2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */
+                                                        <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC22 periph A SPI1_MISO pin */
+                                                         AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC23 periph A SPI1_MOSI pin */
+                                                         AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
                                         };
                                 };
 
                                 ssc0 {
                                         pinctrl_ssc0_tx: ssc0_tx {
                                                 atmel,pins =
-                                                        <2 16 0x1 0x0   /* PC16 periph A TK0 */
-                                                         2 17 0x1 0x0   /* PC17 periph A TF0 */
-                                                         2 18 0x1 0x0>; /* PC18 periph A TD0 */
+                                                        <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC16 periph A TK0 */
+                                                         AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC17 periph A TF0 */
+                                                         AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
                                         };
 
                                         pinctrl_ssc0_rx: ssc0_rx {
                                                 atmel,pins =
-                                                        <2 19 0x1 0x0   /* PC19 periph A RK0 */
-                                                         2 20 0x1 0x0   /* PC20 periph A RF0 */
-                                                         2 21 0x1 0x0>; /* PC21 periph A RD0 */
+                                                        <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC19 periph A RK0 */
+                                                         AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC20 periph A RF0 */
+                                                         AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
                                         };
                                 };
 
                                 ssc1 {
                                         pinctrl_ssc1_tx: ssc1_tx {
                                                 atmel,pins =
-                                                        <1 2 0x2 0x0    /* PB2 periph B TK1, conflicts with GTX2 */
-                                                         1 3 0x2 0x0    /* PB3 periph B TF1, conflicts with GTX3 */
-                                                         1 6 0x2 0x0>;  /* PB6 periph B TD1, conflicts with TD1 */
+                                                        <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB2 periph B TK1, conflicts with GTX2 */
+                                                         AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB3 periph B TF1, conflicts with GTX3 */
+                                                         AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* PB6 periph B TD1, conflicts with TD1 */
                                         };
 
                                         pinctrl_ssc1_rx: ssc1_rx {
                                                 atmel,pins =
-                                                        <1 7 0x2 0x0    /* PB7 periph B RK1, conflicts with EREFCK */
-                                                         1 10 0x2 0x0   /* PB10 periph B RF1, conflicts with GTXER */
-                                                         1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */
+                                                        <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE    /* PB7 periph B RK1, conflicts with EREFCK */
+                                                         AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PB10 periph B RF1, conflicts with GTXER */
+                                                         AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
                                         };
                                 };
 
                                 uart0 {
                                         pinctrl_uart0: uart0-0 {
                                                 atmel,pins =
-                                                        <2 29 0x1 0x0   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
-                                                         2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */
+                                                        <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */
+                                                         AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PC30 periph A with pullup, conflicts with ISI_PCK */
                                         };
                                 };
 
                                 uart1 {
                                         pinctrl_uart1: uart1-0 {
                                                 atmel,pins =
-                                                        <0 30 0x2 0x0   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
-                                                         0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
+                                                        <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */
+                                                         AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */
                                         };
                                 };
 
                                 usart0 {
                                         pinctrl_usart0: usart0-0 {
                                                 atmel,pins =
-                                                        <3 17 0x1 0x0   /* PD17 periph A */
-                                                         3 18 0x1 0x1>; /* PD18 periph A with pullup */
+                                                        <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD17 periph A */
+                                                         AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PD18 periph A with pullup */
                                         };
 
                                         pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
                                                 atmel,pins =
-                                                        <3 15 0x1 0x0   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
-                                                         3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
+                                                        <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
+                                                         AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
                                         };
                                 };
 
                                 usart1 {
                                         pinctrl_usart1: usart1-0 {
                                                 atmel,pins =
-                                                        <1 28 0x1 0x0   /* PB28 periph A */
-                                                         1 29 0x1 0x1>; /* PB29 periph A with pullup */
+                                                        <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB28 periph A */
+                                                         AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;      /* PB29 periph A with pullup */
                                         };
 
                                         pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
                                                 atmel,pins =
-                                                        <1 26 0x1 0x0   /* PB26 periph A, conflicts with GRX7 */
-                                                         1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */
+                                                        <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PB26 periph A, conflicts with GRX7 */
+                                                         AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
                                         };
                                 };
 
                                 usart2 {
                                         pinctrl_usart2: usart2-0 {
                                                 atmel,pins =
-                                                        <4 25 0x2 0x0   /* PE25 periph B, conflicts with A25 */
-                                                         4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */
+                                                        <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE25 periph B, conflicts with A25 */
+                                                         AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE26 periph B with pullup, conflicts NCS0 */
                                         };
 
                                         pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
                                                 atmel,pins =
-                                                        <4 23 0x2 0x0   /* PE23 periph B, conflicts with A23 */
-                                                         4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */
+                                                        <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE23 periph B, conflicts with A23 */
+                                                         AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
                                         };
                                 };
 
                                 usart3 {
                                         pinctrl_usart3: usart3-0 {
                                                 atmel,pins =
-                                                        <4 18 0x2 0x0   /* PE18 periph B, conflicts with A18 */
-                                                         4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */
+                                                        <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE18 periph B, conflicts with A18 */
+                                                         AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;      /* PE19 periph B with pullup, conflicts with A19 */
                                         };
 
                                         pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
                                                 atmel,pins =
-                                                        <4 16 0x2 0x0   /* PE16 periph B, conflicts with A16 */
-                                                         4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */
+                                                        <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE   /* PE16 periph B, conflicts with A16 */
+                                                         AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
                                         };
                                 };
+
+
+                                pioA: gpio@fffff200 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff200 0x100>;
+                                        interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioB: gpio@fffff400 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff400 0x100>;
+                                        interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioC: gpio@fffff600 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff600 0x100>;
+                                        interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioD: gpio@fffff800 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffff800 0x100>;
+                                        interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
+
+                                pioE: gpio@fffffa00 {
+                                        compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
+                                        reg = <0xfffffa00 0x100>;
+                                        interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
+                                        #gpio-cells = <2>;
+                                        gpio-controller;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                };
                         };
 
                         pmc: pmc@fffffc00 {
@@ -867,7 +880,7 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <3 4 5>;
+                                interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
                         };
 
                         watchdog@fffffe40 {
@@ -879,7 +892,7 @@
                         rtc@fffffeb0 {
                                 compatible = "atmel,at91rm9200-rtc";
                                 reg = <0xfffffeb0 0x30>;
-                                interrupts = <1 4 7>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                         };
                 };
 
@@ -889,7 +902,7 @@
                         compatible = "atmel,at91sam9rl-udc";
                         reg = <0x00500000 0x100000
                                0xf8030000 0x4000>;
-                        interrupts = <33 4 2>;
+                        interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
 
                         ep0 {
@@ -1001,14 +1014,14 @@
                 usb1: ohci@00600000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
-                        interrupts = <32 4 2>;
+                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
 
                 usb2: ehci@00700000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <32 4 2>;
+                        interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
                         status = "disabled";
                 };
 
@@ -1024,7 +1037,7 @@
                                 0xffffc000 0x00000070   /* NFC HSMC regs */
                                 0x00200000 0x00100000   /* NFC SRAM banks */
                                 >;
-                        interrupts = <5 4 6>;
+                        interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
                         atmel,nand-addr-offset = <21>;
                         atmel,nand-cmd-offset = <22>;
                         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index fa5d216f1db7..027bac7510b6 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
         model = "Atmel SAMA5D31-EK";
@@ -41,7 +41,7 @@
         leds {
                 d3 {
                         label = "d3";
-                        gpios = <&pioE 24 0>;
+                        gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index c38c9433d7a5..99bd0c8e0471 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
         model = "Atmel SAMA5D33-EK";
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index 6bebfcdcb1d1..fb8ee11cf282 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -7,8 +7,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
-/include/ "sama5d3xdm.dtsi"
+#include "sama5d3xmb.dtsi"
+#include "sama5d3xdm.dtsi"
 
 / {
         model = "Atmel SAMA5D34-EK";
@@ -51,7 +51,7 @@
         leds {
                 d3 {
                         label = "d3";
-                        gpios = <&pioE 24 0>;
+                        gpios = <&pioE 24 GPIO_ACTIVE_HIGH>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index a488fc4e9777..509a53d9cc7b 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -7,7 +7,7 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "sama5d3xmb.dtsi"
+#include "sama5d3xmb.dtsi"
 
 / {
         model = "Atmel SAMA5D35-EK";
@@ -48,7 +48,7 @@
 
                 pb_user1 {
                         label = "pb_user1";
-                        gpios = <&pioE 27 0>;
+                        gpios = <&pioE 27 GPIO_ACTIVE_HIGH>;
                         linux,code = <0x100>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b336e7787cb3..1f8050813a54 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "sama5d3.dtsi"
+#include "sama5d3.dtsi"
 
 / {
         compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5";
@@ -89,7 +89,7 @@
 
                 d2 {
                         label = "d2";
-                        gpios = <&pioE 25 1>;   /* PE25, conflicts with A25, RXD2 */
+                        gpios = <&pioE 25 GPIO_ACTIVE_LOW>;     /* PE25, conflicts with A25, RXD2 */
                 };
         };
 };
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi
index 4b8830eb2060..1c296d6b2f2a 100644
--- a/arch/arm/boot/dts/sama5d3xdm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xdm.dtsi
@@ -33,7 +33,7 @@
                                 board {
                                         pinctrl_qt1070_irq: qt1070_irq {
                                                 atmel,pins =
-                                                        <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */
+                                                        <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE31 GPIO with pull up deglith */
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 661d7ca9c309..8a9e05d8a4b8 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -6,7 +6,7 @@
  *
  * Licensed under GPLv2 or later.
  */
-/include/ "sama5d3xcm.dtsi"
+#include "sama5d3xcm.dtsi"
 
 / {
         compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5";
@@ -20,7 +20,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 17 0>;
+                                        cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -62,7 +62,7 @@
                                 slot@0 {
                                         reg = <0>;
                                         bus-width = <4>;
-                                        cd-gpios = <&pioD 18 0>;
+                                        cd-gpios = <&pioD 18 GPIO_ACTIVE_HIGH>;
                                 };
                         };
 
@@ -87,32 +87,32 @@
                                 board {
                                         pinctrl_mmc0_cd: mmc0_cd {
                                                 atmel,pins =
-                                                        <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */
+                                                        <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD17 GPIO with pullup deglitch */
                                         };
 
                                         pinctrl_mmc1_cd: mmc1_cd {
                                                 atmel,pins =
-                                                        <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */
+                                                        <AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD18 GPIO with pullup deglitch */
                                         };
 
                                         pinctrl_pck0_as_audio_mck: pck0_as_audio_mck {
                                                 atmel,pins =
-                                                        <3 30 0x2 0x0>; /* PD30 periph B */
+                                                        <AT91_PIOD 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD30 periph B */
                                         };
 
                                         pinctrl_isi_reset: isi_reset-0 {
                                                 atmel,pins =
-                                                        <4 24 0x0 0x0>;   /* PE24 gpio */
+                                                        <AT91_PIOE 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;   /* PE24 gpio */
                                         };
 
                                         pinctrl_isi_power: isi_power-0 {
                                                 atmel,pins =
-                                                        <4 29 0x0 0x0>; /* PE29 gpio */
+                                                        <AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>; /* PE29 gpio */
                                         };
 
                                         pinctrl_usba_vbus: usba_vbus {
                                                 atmel,pins =
-                                                        <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */
+                                                        <AT91_PIOD 29 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PD29 GPIO with deglitch */
                                         };
                                 };
                         };
@@ -127,7 +127,7 @@
                 };
 
                 usb0: gadget@00500000 {
-                        atmel,vbus-gpio = <&pioD 29 0>;
+                        atmel,vbus-gpio = <&pioD 29 GPIO_ACTIVE_HIGH>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&pinctrl_usba_vbus>;
                         status = "okay";
@@ -135,9 +135,9 @@
 
                 usb1: ohci@00600000 {
                         num-ports = <3>;
-                        atmel,vbus-gpio = <&pioD 25 0
-                                           &pioD 26 1
-                                           &pioD 27 1
+                        atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH
+                                           &pioD 26 GPIO_ACTIVE_LOW
+                                           &pioD 27 GPIO_ACTIVE_LOW
                                           >;
                         status = "okay";
                 };
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 677fc603f8b3..7bf020ecadf5 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -14,8 +14,13 @@
         compatible = "renesas,sh7372";
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 cpu@0 {
                         compatible = "arm,cortex-a8";
+                        device_type = "cpu";
+                        reg = <0x0>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index 5972abb55f9c..b6f759e830ed 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -18,6 +18,19 @@
         model = "KZM-A9-GT";
         compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
 
+        cpus {
+                cpu@0 {
+                        cpu0-supply = <&vdd_dvfs>;
+                        operating-points = <
+                                /* kHz  uV */
+                                1196000 1315000
+                                 598000 1175000
+                                 398667 1065000
+                        >;
+                        voltage-tolerance = <1>; /* 1% */
+                };
+        };
+
         chosen {
                 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
         };
@@ -59,6 +72,79 @@
         };
 };
 
+&i2c0 {
+        as3711@40 {
+                compatible = "ams,as3711";
+                reg = <0x40>;
+
+                regulators {
+                        vdd_dvfs: sd1 {
+                                regulator-name = "1.315V CPU";
+                                regulator-min-microvolt = <1050000>;
+                                regulator-max-microvolt = <1350000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd2 {
+                                regulator-name = "1.8V";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        sd4 {
+                                regulator-name = "1.215V";
+                                regulator-min-microvolt = <1215000>;
+                                regulator-max-microvolt = <1235000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo2 {
+                                regulator-name = "2.8V CPU";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo3 {
+                                regulator-name = "3.0V CPU";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo4 {
+                                regulator-name = "2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo5 {
+                                regulator-name = "2.8V #2";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo7 {
+                                regulator-name = "1.15V CPU";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        ldo8 {
+                                regulator-name = "1.15V CPU #2";
+                                regulator-min-microvolt = <1150000>;
+                                regulator-max-microvolt = <1150000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
+};
+
 &mmcif {
         bus-width = <8>;
         vmmc-supply = <&reg_1p8v>;
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index ec40bf78289e..b97750256003 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -119,7 +119,7 @@
                               0 32 0x4>;
         };
 
-        i2c0: i2c@0xe6820000 {
+        i2c0: i2c@e6820000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -131,7 +131,7 @@
                               0 170 0x4>;
         };
 
-        i2c1: i2c@0xe6822000 {
+        i2c1: i2c@e6822000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -143,7 +143,7 @@
                               0 54 0x4>;
         };
 
-        i2c2: i2c@0xe6824000 {
+        i2c2: i2c@e6824000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -155,7 +155,7 @@
                               0 174 0x4>;
         };
 
-        i2c3: i2c@0xe6826000 {
+        i2c3: i2c@e6826000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -167,7 +167,7 @@
                               0 186 0x4>;
         };
 
-        i2c4: i2c@0xe6828000 {
+        i2c4: i2c@e6828000 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "renesas,rmobile-iic";
@@ -179,7 +179,7 @@
                               0 190 0x4>;
         };
 
-        mmcif: mmcif@0x10010000 {
+        mmcif: mmcif@e6bd0000 {
                 compatible = "renesas,sh-mmcif";
                 reg = <0xe6bd0000 0x100>;
                 interrupt-parent = <&gic>;
@@ -189,7 +189,7 @@
                 status = "disabled";
         };
 
-        sdhi0: sdhi@0xee100000 {
+        sdhi0: sdhi@ee100000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee100000 0x100>;
                 interrupt-parent = <&gic>;
@@ -201,7 +201,7 @@
         };
 
         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
-        sdhi1: sdhi@0xee120000 {
+        sdhi1: sdhi@ee120000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee120000 0x100>;
                 interrupt-parent = <&gic>;
@@ -212,7 +212,7 @@
                 status = "disabled";
         };
 
-        sdhi2: sdhi@0xee140000 {
+        sdhi2: sdhi@ee140000 {
                 compatible = "renesas,r8a7740-sdhi";
                 reg = <0xee140000 0x100>;
                 interrupt-parent = <&gic>;
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index db5db24fd544..49824be66845 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -10,7 +10,7 @@
  */
 
 /dts-v1/;
-/include/ "dbx5x0.dtsi"
+#include "dbx5x0.dtsi"
 
 / {
         model = "Calao Systems Snowball platform with device tree";
@@ -22,12 +22,13 @@
 
         en_3v3_reg: en_3v3 {
                 compatible = "regulator-fixed";
-                regulator-name = "en-3v3-fixed-supply";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                gpios = <&gpio0 26  0x4>; // 26
-                startup-delay-us = <5000>;
-                enable-active-high;
+                regulator-name = "en-3v3-fixed-supply";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                /* AB8500 GPIOs start from 1 - offset 25 is GPIO26. */
+                gpio = <&ab8500_gpio 25 0x4>;
+                startup-delay-us = <5000>;
+                enable-active-high;
         };
 
         gpio_keys {
@@ -82,7 +83,7 @@
                 };
         };
 
-        soc-u9500 {
+        soc {
 
                 sound {
                         compatible = "stericsson,snd-soc-mop500";
@@ -99,40 +100,13 @@
                         status = "okay";
                 };
 
-                prcmu@80157000 {
-                        thermal@801573c0 {
-                                num-trips = <4>;
-
-                                trip0-temp = <70000>;
-                                trip0-type = "active";
-                                trip0-cdev-num = <1>;
-                                trip0-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip1-temp = <75000>;
-                                trip1-type = "active";
-                                trip1-cdev-num = <1>;
-                                trip1-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip2-temp = <80000>;
-                                trip2-type = "active";
-                                trip2-cdev-num = <1>;
-                                trip2-cdev-name0 = "thermal-cpufreq-0";
-
-                                trip3-temp = <85000>;
-                                trip3-type = "critical";
-                                trip3-cdev-num = <0>;
-
-                                status = "okay";
-                         };
-                };
-
                 external-bus@50000000 {
                         status = "okay";
 
                         ethernet@0 {
                                 compatible = "smsc,lan9115";
                                 reg = <0 0x10000>;
-                                interrupts = <12 0x1>;
+                                interrupts = <12 IRQ_TYPE_EDGE_RISING>;
                                 interrupt-parent = <&gpio4>;
                                 vdd33a-supply = <&en_3v3_reg>;
                                 vddvario-supply = <&db8500_vape_reg>;
@@ -146,13 +120,21 @@
                         };
                 };
 
+                vmmci: regulator-gpio {
+                        gpios = <&gpio6 25 0x4>;
+                        enable-gpio = <&gpio7 4 0x4>;
+
+                        status = "okay";
+                };
+
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <4>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
+                        vqmmc-supply = <&vmmci>;
 
                         cd-gpios  = <&gpio6 26 0x4>; // 218
                         cd-inverted;
@@ -163,7 +145,7 @@
                 // On-board eMMC
                 sdi4_per2@80114000 {
                         arm,primecell-periphid = <0x10480180>;
-                        max-frequency = <50000000>;
+                        max-frequency = <100000000>;
                         bus-width = <8>;
                         mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
@@ -197,15 +179,15 @@
                 };
 
                 i2c@80128000 {
-                        lp5521@0x33 {
+                        lp5521@33 {
                                 // compatible = "lp5521";
                                 reg = <0x33>;
                         };
-                        lp5521@0x34 {
+                        lp5521@34 {
                                 // compatible = "lp5521";
                                 reg = <0x34>;
                         };
-                        bh1780@0x29 {
+                        bh1780@29 {
                                 // compatible = "rohm,bh1780gli";
                                 reg = <0x33>;
                         };
@@ -298,6 +280,31 @@
                                 };
                         };
 
+                        thermal@801573c0 {
+                                num-trips = <4>;
+
+                                trip0-temp = <70000>;
+                                trip0-type = "active";
+                                trip0-cdev-num = <1>;
+                                trip0-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip1-temp = <75000>;
+                                trip1-type = "active";
+                                trip1-cdev-num = <1>;
+                                trip1-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip2-temp = <80000>;
+                                trip2-type = "active";
+                                trip2-cdev-num = <1>;
+                                trip2-cdev-name0 = "thermal-cpufreq-0";
+
+                                trip3-temp = <85000>;
+                                trip3-type = "critical";
+                                trip3-cdev-num = <0>;
+
+                                status = "okay";
+                        };
+
                         ab8500 {
                                 ab8500-gpio {
                                         compatible = "stericsson,ab8500-gpio";
@@ -316,7 +323,7 @@
                                                 regulator-name = "V-MMC-SD";
                                         };
 
-                                        ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                        ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
                                                 regulator-name = "V-INTCORE";
                                         };
 
@@ -336,7 +343,7 @@
                                                 regulator-name = "V-AMIC1";
                                         };
 
-                                        ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                        ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
                                                 regulator-name = "V-AMIC2";
                                         };
 
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 16a6e13e08b4..bee62a2cf6d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -23,6 +23,7 @@
 
         aliases {
                 ethernet0 = &gmac0;
+                ethernet1 = &gmac1;
                 serial0 = &uart0;
                 serial1 = &uart1;
                 timer0 = &timer0;
@@ -94,6 +95,12 @@
                                                 compatible = "fixed-clock";
                                         };
 
+                                        f2s_periph_ref_clk: f2s_periph_ref_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "fixed-clock";
+                                                clock-frequency = <10000000>;
+                                        };
+
                                         main_pll: main_pll {
                                                 #address-cells = <1>;
                                                 #size-cells = <0>;
@@ -235,16 +242,222 @@
                                                         reg = <0xD4>;
                                                 };
                                         };
+
+                                mpu_periph_clk: mpu_periph_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <4>;
+                                        };
+
+                                mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mpuclk>;
+                                        fixed-divider = <2>;
+                                        };
+
+                                l4_main_clk: l4_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        clk-gate = <0x60 0>;
+                                        };
+
+                                l3_main_clk: l3_main_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        };
+
+                                l3_mp_clk: l3_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 0 2>;
+                                        clk-gate = <0x60 1>;
+                                        };
+
+                                l3_sp_clk: l3_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>;
+                                        div-reg = <0x64 2 2>;
+                                };
+
+                                l4_mp_clk: l4_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 4 3>;
+                                        clk-gate = <0x60 2>;
+                                        };
+
+                                l4_sp_clk: l4_sp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&mainclk>, <&per_base_clk>;
+                                        div-reg = <0x64 7 3>;
+                                        clk-gate = <0x60 3>;
+                                        };
+
+                                dbg_at_clk: dbg_at_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 0 2>;
+                                        clk-gate = <0x60 4>;
+                                        };
+
+                                dbg_clk: dbg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x68 2 2>;
+                                        clk-gate = <0x60 5>;
+                                        };
+
+                                dbg_trace_clk: dbg_trace_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        div-reg = <0x6C 0 3>;
+                                        clk-gate = <0x60 6>;
+                                        };
+
+                                dbg_timer_clk: dbg_timer_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&dbg_base_clk>;
+                                        clk-gate = <0x60 7>;
+                                        };
+
+                                cfg_clk: cfg_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 8>;
+                                        };
+
+                                s2f_user0_clk: s2f_user0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&cfg_s2f_usr0_clk>;
+                                        clk-gate = <0x60 9>;
+                                        };
+
+                                emac_0_clk: emac_0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac0_clk>;
+                                        clk-gate = <0xa0 0>;
+                                        };
+
+                                emac_1_clk: emac_1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&emac1_clk>;
+                                        clk-gate = <0xa0 1>;
+                                        };
+
+                                usb_mp_clk: usb_mp_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 2>;
+                                        div-reg = <0xa4 0 3>;
+                                        };
+
+                                spi_m_clk: spi_m_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 3>;
+                                        div-reg = <0xa4 3 3>;
+                                        };
+
+                                can0_clk: can0_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 4>;
+                                        div-reg = <0xa4 6 3>;
+                                        };
+
+                                can1_clk: can1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 5>;
+                                        div-reg = <0xa4 9 3>;
+                                        };
+
+                                gpio_db_clk: gpio_db_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&per_base_clk>;
+                                        clk-gate = <0xa0 6>;
+                                        div-reg = <0xa8 0 24>;
+                                        };
+
+                                s2f_user1_clk: s2f_user1_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&s2f_usr1_clk>;
+                                        clk-gate = <0xa0 7>;
+                                        };
+
+                                sdmmc_clk: sdmmc_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 8>;
+                                        };
+
+                                nand_x_clk: nand_x_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 9>;
+                                        };
+
+                                nand_clk: nand_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                        clk-gate = <0xa0 10>;
+                                        fixed-divider = <4>;
+                                        };
+
+                                qspi_clk: qspi_clk {
+                                        #clock-cells = <0>;
+                                        compatible = "altr,socfpga-gate-clk";
+                                        clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+                                        clk-gate = <0xa0 11>;
+                                        };
                                 };
                         };
 
-                gmac0: stmmac@ff700000 {
+                gmac0: ethernet@ff700000 {
                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
                         reg = <0xff700000 0x2000>;
                         interrupts = <0 115 4>;
                         interrupt-names = "macirq";
                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
-                        phy-mode = "gmii";
+                        clocks = <&emac0_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
+                };
+
+                gmac1: ethernet@ff702000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff702000 0x2000>;
+                        interrupts = <0 120 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        clocks = <&emac1_clk>;
+                        clock-names = "stmmaceth";
+                        status = "disabled";
                 };
 
                 L2: l2-cache@fffef000 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
index 2495958f1016..973999d2c697 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -32,6 +32,13 @@
                 reg = <0x0 0x40000000>; /* 1GB */
         };
 
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
+
         soc {
                 clkmgr@ffd04000 {
                         clocks {
@@ -41,6 +48,12 @@
                         };
                 };
 
+                ethernet@ff702000 {
+                        phy-mode = "rgmii";
+                        phy-addr = <0xffffffff>; /* probe for phy addr */
+                        status = "okay";
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <100000000>;
                 };
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 0bf035d607f0..d1ec0cab2dee 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -41,6 +41,11 @@
                         };
                 };
 
+                ethernet@ff700000 {
+                        phy-mode = "gmii";
+                        status = "okay";
+                };
+
                 timer0@ffc08000 {
                         clock-frequency = <7000000>;
                 };
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 45597fd91050..4382547df58a 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -22,12 +22,14 @@
 
                 cpu@0 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <0>;
                         next-level-cache = <&L2>;
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
+                        device_type = "cpu";
                         reg = <1>;
                         next-level-cache = <&L2>;
                 };
diff --git a/arch/arm/boot/dts/spear3xx.dtsi b/arch/arm/boot/dts/spear3xx.dtsi
index c2a852d43c48..f0e3fcf8e323 100644
--- a/arch/arm/boot/dts/spear3xx.dtsi
+++ b/arch/arm/boot/dts/spear3xx.dtsi
@@ -17,8 +17,12 @@
         interrupt-parent = <&vic>;
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 19f99dc4115e..9f60a7b6a42b 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -15,8 +15,12 @@
         compatible = "st,spear600";
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        compatible = "arm,arm926ej-s";
+                        device_type = "cpu";
                 };
         };
 
diff --git a/arch/arm/boot/dts/st-pincfg.h b/arch/arm/boot/dts/st-pincfg.h
new file mode 100644
index 000000000000..8c45d85ac13e
--- /dev/null
+++ b/arch/arm/boot/dts/st-pincfg.h
@@ -0,0 +1,71 @@
+#ifndef _ST_PINCFG_H_
+#define _ST_PINCFG_H_
+
+/* Alternate functions */
+#define ALT1    1
+#define ALT2    2
+#define ALT3    3
+#define ALT4    4
+#define ALT5    5
+#define ALT6    6
+#define ALT7    7
+
+/* Output enable */
+#define OE                      (1 << 27)
+/* Pull Up */
+#define PU                      (1 << 26)
+/* Open Drain */
+#define OD                      (1 << 26)
+#define RT                      (1 << 23)
+#define INVERTCLK               (1 << 22)
+#define CLKNOTDATA              (1 << 21)
+#define DOUBLE_EDGE             (1 << 20)
+#define CLK_A                   (0 << 18)
+#define CLK_B                   (1 << 18)
+#define CLK_C                   (2 << 18)
+#define CLK_D                   (3 << 18)
+
+/* User-frendly defines for Pin Direction */
+                /* oe = 0, pu = 0, od = 0 */
+#define IN                      (0)
+                /* oe = 0, pu = 1, od = 0 */
+#define IN_PU                   (PU)
+                /* oe = 1, pu = 0, od = 0 */
+#define OUT                     (OE)
+                /* oe = 1, pu = 0, od = 1 */
+#define BIDIR                   (OE | OD)
+                /* oe = 1, pu = 1, od = 1 */
+#define BIDIR_PU                (OE | PU | OD)
+
+/* RETIME_TYPE */
+/*
+ * B Mode
+ * Bypass retime with optional delay parameter
+ */
+#define BYPASS          (0)
+/*
+ * R0, R1, R0D, R1D modes
+ * single-edge data non inverted clock, retime data with clk
+ */
+#define SE_NICLK_IO     (RT)
+/*
+ * RIV0, RIV1, RIV0D, RIV1D modes
+ * single-edge data inverted clock, retime data with clk
+ */
+#define SE_ICLK_IO      (RT | INVERTCLK)
+/*
+ * R0E, R1E, R0ED, R1ED modes
+ * double-edge data, retime data with clk
+ */
+#define DE_IO           (RT | DOUBLE_EDGE)
+/*
+ * CIV0, CIV1 modes with inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define ICLK            (RT | CLKNOTDATA | INVERTCLK)
+/*
+ * CLK0, CLK1 modes with non-inverted clock
+ * Retiming the clk pins will park clock & reduce the noise within the core.
+ */
+#define NICLK           (RT | CLKNOTDATA)
+#endif /* _ST_PINCFG_H_ */
diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts
index 6f82d9368948..16c3888b7b15 100644
--- a/arch/arm/boot/dts/ste-nomadik-s8815.dts
+++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts
@@ -22,6 +22,49 @@
                 };
         };
 
+        src@101e0000 {
+                /* These chrystal drivers are not used on this board */
+                disable-sxtalo;
+                disable-mxtalo;
+        };
+
+        pinctrl {
+                /* Hog CD pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&cd_default_mode>;
+
+                mmcsd-cd {
+                        cd_default_mode: cd_default {
+                                cd_default_cfg1 {
+                                        /* CD input GPIO */
+                                        ste,pins = "GPIO111_H21";
+                                        ste,input = <0>;
+                                };
+                                cd_default_cfg2 {
+                                        /* CD GPIO biasing */
+                                        ste,pins = "GPIO112_J21";
+                                        ste,output = <0>;
+                                };
+                        };
+                };
+                user-led {
+                        user_led_default_mode: user_led_default {
+                                user_led_default_cfg {
+                                        ste,pins = "GPIO2_C5";
+                                        ste,output = <1>;
+                                };
+                        };
+                };
+                user-button {
+                        user_button_default_mode: user_button_default {
+                                user_button_default_cfg {
+                                        ste,pins = "GPIO3_A4";
+                                        ste,input = <0>;
+                                };
+                        };
+                };
+        };
+
         /* Custom board node with GPIO pins to active etc */
         usb-s8815 {
                 /* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
@@ -33,4 +76,30 @@
                         gpios = <&gpio3 16 0x1>;
                 };
         };
+
+        /* The user LED on the board is set up to be used for heartbeat */
+        leds {
+                compatible = "gpio-leds";
+                user-led {
+                        label = "user_led";
+                        gpios = <&gpio0 2 0x1>;
+                        default-state = "off";
+                        linux,default-trigger = "heartbeat";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_led_default_mode>;
+                };
+        };
+
+        /* User key mapped in as "escape" */
+        gpio-keys {
+                compatible = "gpio-keys";
+                user-button {
+                        label = "user_button";
+                        gpios = <&gpio0 3 0x1>;
+                        linux,code = <1>; /* KEY_ESC */
+                        gpio-key,wakeup;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&user_button_default_mode>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 4a4aab395141..a3acfa7b3dc9 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -21,18 +21,23 @@
                 cache-level = <2>;
         };
 
-        mtu0 {
+        mtu0: mtu@101e2000 {
                 /* Nomadik system timer */
+                compatible = "st,nomadik-mtu";
                 reg = <0x101e2000 0x1000>;
                 interrupt-parent = <&vica>;
                 interrupts = <4>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
         };
 
-        mtu1 {
+        mtu1: mtu@101e3000 {
                 /* Secondary timer */
                 reg = <0x101e3000 0x1000>;
                 interrupt-parent = <&vica>;
                 interrupts = <5>;
+                clocks = <&timclk>, <&pclk>;
+                clock-names = "timclk", "apb_pclk";
         };
 
         gpio0: gpio@101e4000 {
@@ -45,6 +50,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <0>;
+                clocks = <&pclk>;
         };
 
         gpio1: gpio@101e5000 {
@@ -57,6 +63,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <1>;
+                clocks = <&pclk>;
         };
 
         gpio2: gpio@101e6000 {
@@ -69,6 +76,7 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <2>;
+                clocks = <&pclk>;
         };
 
         gpio3: gpio@101e7000 {
@@ -81,10 +89,544 @@
                 gpio-controller;
                 #gpio-cells = <2>;
                 gpio-bank = <3>;
+                clocks = <&pclk>;
         };
 
         pinctrl {
-                compatible = "stericsson,nmk-pinctrl-stn8815";
+                compatible = "stericsson,stn8815-pinctrl";
+                /* Pin configurations */
+                uart0 {
+                        uart0_default_mux: uart0_mux {
+                                u0_default_mux {
+                                        ste,function = "u0";
+                                        ste,pins = "u0_a_1";
+                                };
+                        };
+                };
+                uart1 {
+                        uart1_default_mux: uart1_mux {
+                                u1_default_mux {
+                                        ste,function = "u1";
+                                        ste,pins = "u1_a_1";
+                                };
+                        };
+                };
+                mmcsd {
+                        mmcsd_default_mux: mmcsd_mux {
+                                mmcsd_default_mux {
+                                        ste,function = "mmcsd";
+                                        ste,pins = "mmcsd_a_1";
+                                };
+                        };
+                        mmcsd_default_mode: mmcsd_default {
+                                mmcsd_default_cfg1 {
+                                        /* MCCLK */
+                                        ste,pins = "GPIO8_B10";
+                                        ste,output = <0>;
+                                };
+                                mmcsd_default_cfg2 {
+                                        /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */
+                                        ste,pins = "GPIO10_C11", "GPIO15_A12",
+                                        "GPIO16_C13";
+                                        ste,output = <1>;
+                                };
+                                mmcsd_default_cfg3 {
+                                        /* MCCMD, MCDAT3-0, MCMSFBCLK */
+                                        ste,pins = "GPIO9_A10", "GPIO11_B11",
+                                        "GPIO12_A11", "GPIO13_C12",
+                                        "GPIO14_B12", "GPIO24_C15";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c0 {
+                        i2c0_default_mode: i2c0_default {
+                                i2c0_default_cfg {
+                                        ste,pins = "GPIO62_D3", "GPIO63_D2";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c1 {
+                        i2c1_default_mode: i2c1_default {
+                                i2c1_default_cfg {
+                                        ste,pins = "GPIO53_L4", "GPIO54_L3";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+                i2c2 {
+                        i2c2_default_mode: i2c2_default {
+                                i2c2_default_cfg {
+                                        ste,pins = "GPIO73_C21", "GPIO74_C20";
+                                        ste,input = <1>;
+                                };
+                        };
+                };
+        };
+
+        src: src@101e0000 {
+                compatible = "stericsson,nomadik-src";
+                reg = <0x101e0000 0x1000>;
+                disable-sxtalo;
+                disable-mxtalo;
+
+                /*
+                 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz
+                 * that is parent of TIMCLK, PLL1 and PLL2
+                 */
+                mxtal: mxtal@19.2M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19200000>;
+                };
+
+                /*
+                 * The 2.4 MHz TIMCLK reference clock is active at
+                 * boot time, this is actually the MXTALCLK @19.2 MHz
+                 * divided by 8. This clock is used by the timers and
+                 * watchdog. See page 105 ff.
+                 */
+                timclk: timclk@2.4M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                        clocks = <&mxtal>;
+                };
+
+                /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
+                pll1: pll1@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <1>;
+                        clocks = <&mxtal>;
+                };
+
+                /* HCLK divides the PLL1 with 1,2,3 or 4 */
+                hclk: hclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-hclk-clock";
+                        clocks = <&pll1>;
+                };
+                /* The PCLK domain uses HCLK right off */
+                pclk: pclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&hclk>;
+                };
+
+                /* PLL2 is usually 864 MHz and divided into a few fixed rates */
+                pll2: pll2@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-pll-clock";
+                        pll-id = <2>;
+                        clocks = <&mxtal>;
+                };
+                clk216: clk216@216M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk108: clk108@108M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&clk216>;
+                };
+                clk72: clk72@72M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <12>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk48: clk48@48M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        /* The data sheet does not say how this is derived */
+                        clock-div = <18>;
+                        clock-mult = <1>;
+                        clocks = <&pll2>;
+                };
+                clk27: clk27@27M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&clk108>;
+                };
+
+                /* This apparently exists as well */
+                ulpiclk: ulpiclk@60M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <60000000>;
+                };
+
+                /*
+                 * IP AMBA bus clocks, driving the bus side of the
+                 * peripheral clocking, clock gates.
+                 */
+
+                hclkdma0: hclkdma0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <0>;
+                        clocks = <&hclk>;
+                };
+                hclksmc: hclksmc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <1>;
+                        clocks = <&hclk>;
+                };
+                hclksdram: hclksdram@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <2>;
+                        clocks = <&hclk>;
+                };
+                hclkdma1: hclkdma1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <3>;
+                        clocks = <&hclk>;
+                };
+                hclkclcd: hclkclcd@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <4>;
+                        clocks = <&hclk>;
+                };
+                pclkirda: pclkirda@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <5>;
+                        clocks = <&pclk>;
+                };
+                pclkssp: pclkssp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <6>;
+                        clocks = <&pclk>;
+                };
+                pclkuart0: pclkuart0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <7>;
+                        clocks = <&pclk>;
+                };
+                pclksdi: pclksdi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <8>;
+                        clocks = <&pclk>;
+                };
+                pclki2c0: pclki2c0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <9>;
+                        clocks = <&pclk>;
+                };
+                pclki2c1: pclki2c1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <10>;
+                        clocks = <&pclk>;
+                };
+                pclkuart1: pclkuart1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <11>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp0: pclkmsp0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <12>;
+                        clocks = <&pclk>;
+                };
+                hclkusb: hclkusb@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <13>;
+                        clocks = <&hclk>;
+                };
+                hclkdif: hclkdif@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <14>;
+                        clocks = <&hclk>;
+                };
+                hclksaa: hclksaa@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <15>;
+                        clocks = <&hclk>;
+                };
+                hclksva: hclksva@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <16>;
+                        clocks = <&hclk>;
+                };
+                pclkhsi: pclkhsi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <17>;
+                        clocks = <&pclk>;
+                };
+                pclkxti: pclkxti@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <18>;
+                        clocks = <&pclk>;
+                };
+                pclkuart2: pclkuart2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <19>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp1: pclkmsp1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <20>;
+                        clocks = <&pclk>;
+                };
+                pclkmsp2: pclkmsp2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <21>;
+                        clocks = <&pclk>;
+                };
+                pclkowm: pclkowm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <22>;
+                        clocks = <&pclk>;
+                };
+                hclkhpi: hclkhpi@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <23>;
+                        clocks = <&hclk>;
+                };
+                pclkske: pclkske@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <24>;
+                        clocks = <&pclk>;
+                };
+                pclkhsem: pclkhsem@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <25>;
+                        clocks = <&pclk>;
+                };
+                hclk3d: hclk3d@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <26>;
+                        clocks = <&hclk>;
+                };
+                hclkhash: hclkhash@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <27>;
+                        clocks = <&hclk>;
+                };
+                hclkcryp: hclkcryp@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <28>;
+                        clocks = <&hclk>;
+                };
+                pclkmshc: pclkmshc@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <29>;
+                        clocks = <&pclk>;
+                };
+                hclkusbm: hclkusbm@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <30>;
+                        clocks = <&hclk>;
+                };
+                hclkrng: hclkrng@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <31>;
+                        clocks = <&hclk>;
+                };
+
+                /* IP kernel clocks */
+                clcdclk: clcdclk@0 {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <36>;
+                        clocks = <&clk72 &clk48>;
+                };
+                irdaclk: irdaclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <37>;
+                        clocks = <&clk48>;
+                };
+                sspiclk: sspiclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <38>;
+                        clocks = <&clk48>;
+                };
+                uart0clk: uart0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <39>;
+                        clocks = <&clk48>;
+                };
+                sdiclk: sdiclk@48M {
+                        /* Also called MCCLK in some documents */
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <40>;
+                        clocks = <&clk48>;
+                };
+                i2c0clk: i2c0clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <41>;
+                        clocks = <&clk48>;
+                };
+                i2c1clk: i2c1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <42>;
+                        clocks = <&clk48>;
+                };
+                uart1clk: uart1clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <43>;
+                        clocks = <&clk48>;
+                };
+                mspclk0: mspclk0@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <44>;
+                        clocks = <&clk48>;
+                };
+                usbclk: usbclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <45>;
+                        clocks = <&clk48>; /* 48 MHz not ULPI */
+                };
+                difclk: difclk@72M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <46>;
+                        clocks = <&clk72>;
+                };
+                ipi2cclk: ipi2cclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <47>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                ipbmcclk: ipbmcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <48>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                hsiclkrx: hsiclkrx@216M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <49>;
+                        clocks = <&clk216>;
+                };
+                hsiclktx: hsiclktx@108M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <50>;
+                        clocks = <&clk108>;
+                };
+                uart2clk: uart2clk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <51>;
+                        clocks = <&clk48>;
+                };
+                mspclk1: mspclk1@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <52>;
+                        clocks = <&clk48>;
+                };
+                mspclk2: mspclk2@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <53>;
+                        clocks = <&clk48>;
+                };
+                owmclk: owmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <54>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                skeclk: skeclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <56>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                x3dclk: x3dclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <58>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                pclkmsp3: pclkmsp3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <59>;
+                        clocks = <&pclk>;
+                };
+                mspclk3: mspclk3@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <60>;
+                        clocks = <&clk48>;
+                };
+                mshcclk: mshcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <61>;
+                        clocks = <&clk48>; /* Guess */
+                };
+                usbmclk: usbmclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <62>;
+                        /* Stated as "48 MHz not ULPI clock" */
+                        clocks = <&clk48>;
+                };
+                rngcclk: rngcclk@48M {
+                        #clock-cells = <0>;
+                        compatible = "st,nomadik-src-clock";
+                        clock-id = <63>;
+                        clocks = <&clk48>; /* Guess */
+                };
         };
 
         /* A NAND flash of 128 MiB */
@@ -97,6 +639,7 @@
                         <0x41000000 0x2000>,    /* NAND Base ADDR */
                         <0x40800000 0x2000>;    /* NAND Base CMD */
                 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                clocks = <&hclksmc>;
                 status = "okay";
 
                 partition@0 {
@@ -144,6 +687,8 @@
                         <&gpio1 30 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c0_default_mode>;
 
                 stw4811@2d {
                            compatible = "st,stw4811";
@@ -158,6 +703,8 @@
                         <&gpio1 21 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c1_default_mode>;
 
                 camera@2d {
                            compatible = "st,camera";
@@ -180,6 +727,9 @@
                         <&gpio2 9 0>; /* scl */
                 #address-cells = <1>;
                 #size-cells = <0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_default_mode>;
+
                 stw4811@2d {
                            compatible = "st,stw4811-usb";
                            reg = <0x2d>;
@@ -211,6 +761,10 @@
                         reg = <0x101fd000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <12>;
+                        clocks = <&uart0clk>, <&pclkuart0>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_default_mux>;
                 };
 
                 uart1: uart@101fb000 {
@@ -218,6 +772,10 @@
                         reg = <0x101fb000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <17>;
+                        clocks = <&uart1clk>, <&pclkuart1>;
+                        clock-names = "uartclk", "apb_pclk";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart1_default_mux>;
                 };
 
                 uart2: uart@101f2000 {
@@ -225,17 +783,23 @@
                         reg = <0x101f2000 0x1000>;
                         interrupt-parent = <&vica>;
                         interrupts = <28>;
+                        clocks = <&uart2clk>, <&pclkuart2>;
+                        clock-names = "uartclk", "apb_pclk";
                         status = "disabled";
                 };
 
                 rng: rng@101b0000 {
                         compatible = "arm,primecell";
                         reg = <0x101b0000 0x1000>;
+                        clocks = <&rngcclk>, <&hclkrng>;
+                        clock-names = "rng", "apb_pclk";
                 };
 
                 rtc: rtc@101e8000 {
                         compatible = "arm,pl031", "arm,primecell";
                         reg = <0x101e8000 0x1000>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                         interrupt-parent = <&vica>;
                         interrupts = <10>;
                 };
@@ -243,6 +807,8 @@
                 mmcsd: sdi@101f6000 {
                         compatible = "arm,pl18x", "arm,primecell";
                         reg = <0x101f6000 0x1000>;
+                        clocks = <&sdiclk>, <&pclksdi>;
+                        clock-names = "mclk", "apb_pclk";
                         interrupt-parent = <&vica>;
                         interrupts = <22>;
                         max-frequency = <48000000>;
@@ -251,6 +817,8 @@
                         mmc-cap-sd-highspeed;
                         cd-gpios = <&gpio3 15 0x1>;
                         cd-inverted;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
new file mode 100644
index 000000000000..8a1032c1ffc9
--- /dev/null
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -0,0 +1,473 @@
+/*
+ * Device Tree for the ST-Ericsson U300 Machine and SoC
+ */
+
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "ST-Ericsson U300";
+        compatible = "stericsson,u300";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        chosen {
+                bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        memory {
+                reg = <0x48000000 0x03c00000>;
+        };
+
+        s365 {
+                compatible = "stericsson,s365";
+                vana15-supply = <&ab3100_ldo_d_reg>;
+                syscon = <&syscon>;
+        };
+
+        syscon: syscon@c0011000 {
+                compatible = "stericsson,u300-syscon", "syscon";
+                reg = <0xc0011000 0x1000>;
+                clk32: app_32_clk@32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+                pll13: pll13@13M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                };
+                /* Slow bridge clocks under PLL13 */
+                slow_clk: slow_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <0>;
+                        clocks = <&pll13>;
+                };
+                uart0_clk: uart0_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <1>;
+                        clocks = <&slow_clk>;
+                };
+                gpio_clk: gpio_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <4>;
+                        clocks = <&slow_clk>;
+                };
+                rtc_clk: rtc_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <6>;
+                        clocks = <&slow_clk>;
+                };
+                apptimer_clk: app_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <7>;
+                        clocks = <&slow_clk>;
+                };
+                acc_tmr_clk@13M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <0>; /* Slow */
+                        clock-id = <8>;
+                        clocks = <&slow_clk>;
+                };
+                pll208: pll208@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <208000000>;
+                };
+                app208: app_208_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <1>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                cpu_clk@208M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <3>;
+                        clocks = <&app208>;
+                };
+                app104: app_104_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                semi_clk@104M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <9>;
+                        clocks = <&app104>;
+                };
+                app52: app_52_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <4>;
+                        clock-mult = <1>;
+                        clocks = <&pll208>;
+                };
+                /* AHB subsystem clocks */
+                ahb_clk: ahb_subsys_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <10>;
+                        clocks = <&app52>;
+                };
+                intcon_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <12>;
+                        clocks = <&ahb_clk>;
+                };
+                emif_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <5>;
+                        clocks = <&ahb_clk>;
+                };
+                dmac_clk: dmac_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <4>;
+                        clocks = <&app52>;
+                };
+                fsmc_clk: fsmc_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <6>;
+                        clocks = <&app52>;
+                };
+                xgam_clk: xgam_clk@52M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <2>; /* Rest */
+                        clock-id = <8>;
+                        clocks = <&app52>;
+                };
+                app26: app_26_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                        clocks = <&app52>;
+                };
+                /* Fast bridge  clocks */
+                fast_clk: fast_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <0>;
+                        clocks = <&app26>;
+                };
+                i2c0_clk: i2c0_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <1>;
+                        clocks = <&fast_clk>;
+                };
+                i2c1_clk: i2c1_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <2>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_pclk: mmc_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <5>;
+                        clocks = <&fast_clk>;
+                };
+                mmc_mclk: mmc_mclk {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-mclk";
+                        clocks = <&mmc_pclk>;
+                };
+                spi_clk: spi_p_clk@26M {
+                        #clock-cells = <0>;
+                        compatible = "stericsson,u300-syscon-clk";
+                        clock-type = <1>; /* Fast */
+                        clock-id = <6>;
+                        clocks = <&fast_clk>;
+                };
+        };
+
+        timer: timer@c0014000 {
+                compatible = "stericsson,u300-apptimer";
+                reg = <0xc0014000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <24 25 26 27>;
+                clocks = <&apptimer_clk>;
+        };
+
+        gpio: gpio@c0016000 {
+                compatible = "stericsson,gpio-coh901";
+                reg = <0xc0016000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <0 1 2 18 21 22 23>;
+                clocks = <&gpio_clk>;
+                interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
+                                "gpio4", "gpio5", "gpio6";
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+
+        pinctrl: pinctrl@c0011000 {
+                compatible = "stericsson,pinctrl-u300";
+                reg = <0xc0011000 0x1000>;
+        };
+
+        watchdog: watchdog@c0012000 {
+                compatible = "stericsson,coh901327";
+                reg = <0xc0012000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <3>;
+                clocks = <&clk32>;
+        };
+
+        rtc: rtc@c0017000 {
+                compatible = "stericsson,coh901331";
+                reg = <0xc0017000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <10>;
+                clocks = <&rtc_clk>;
+        };
+
+        dmac: dma-controller@c00020000 {
+                compatible = "stericsson,coh901318";
+                reg = <0xc0020000 0x1000>;
+                interrupt-parent = <&vica>;
+                interrupts = <2>;
+                #dma-cells = <1>;
+                dma-channels = <40>;
+                clocks = <&dmac_clk>;
+        };
+
+        /* A NAND flash of 128 MiB */
+        fsmc: flash@40000000 {
+                compatible = "stericsson,fsmc-nand";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x9f800000 0x1000>,      /* FSMC Register*/
+                        <0x80000000 0x4000>,    /* NAND Base DATA */
+                        <0x80020000 0x4000>,    /* NAND Base ADDR */
+                        <0x80010000 0x4000>;    /* NAND Base CMD */
+                reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
+                nand-skip-bbtscan;
+                clocks = <&fsmc_clk>;
+
+                partition@0 {
+                label = "boot records";
+                        reg = <0x0 0x20000>;
+                };
+                partition@20000 {
+                        label = "free";
+                        reg = <0x20000 0x7e0000>;
+                };
+                partition@800000 {
+                        label = "platform";
+                        reg = <0x800000 0xf800000>;
+                };
+        };
+
+        i2c0: i2c@c0004000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0004000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <8>;
+                clocks = <&i2c0_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                ab3100: ab3100@0x48 {
+                        compatible = "stericsson,ab3100";
+                        reg = <0x48>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <0>; /* EXT0 IRQ */
+                        ab3100-regulators {
+                                compatible = "stericsson,ab3100-regulators";
+                                ab3100_ldo_a_reg: ab3100_ldo_a {
+                                        regulator-compatible = "ab3100_ldo_a";
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_c_reg: ab3100_ldo_c {
+                                        regulator-compatible = "ab3100_ldo_c";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_d_reg: ab3100_ldo_d {
+                                        regulator-compatible = "ab3100_ldo_d";
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_e_reg: ab3100_ldo_e {
+                                        regulator-compatible = "ab3100_ldo_e";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <200>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_f_reg: ab3100_ldo_f {
+                                        regulator-compatible = "ab3100_ldo_f";
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        startup-delay-us = <600>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ab3100_ldo_g_reg: ab3100_ldo_g {
+                                        regulator-compatible = "ab3100_ldo_g";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        startup-delay-us = <400>;
+                                };
+                                ab3100_ldo_h_reg: ab3100_ldo_h {
+                                        regulator-compatible = "ab3100_ldo_h";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ldo_k_reg: ab3100_ldo_k {
+                                        regulator-compatible = "ab3100_ldo_k";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <2750000>;
+                                        startup-delay-us = <200>;
+                                };
+                                ab3100_ext_reg: ab3100_ext {
+                                        regulator-compatible = "ab3100_ext";
+                                };
+                                ab3100_buck_reg: ab3100_buck {
+                                        regulator-compatible = "ab3100_buck";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        startup-delay-us = <1000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+
+        i2c1: i2c@c0005000 {
+                compatible = "st,ddci2c";
+                reg = <0xc0005000 0x1000>;
+                interrupt-parent = <&vicb>;
+                interrupts = <9>;
+                clocks = <&i2c1_clk>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                fwcam0: fwcam@0x10 {
+                        reg = <0x10>;
+                };
+                fwcam1: fwcam@0x5d {
+                        reg = <0x5d>;
+                };
+        };
+
+        amba {
+                compatible = "arm,amba-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                vica: interrupt-controller@a0001000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0001000 0x20>;
+                };
+
+                vicb: interrupt-controller@a0002000 {
+                        compatible = "arm,versatile-vic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xa0002000 0x20>;
+                };
+
+                uart0: serial@c0013000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0013000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <22>;
+                        clocks = <&uart0_clk>, <&uart0_clk>;
+                        clock-names = "apb_pclk", "uart0_clk";
+                        dmas = <&dmac 17 &dmac 18>;
+                        dma-names = "tx", "rx";
+                };
+
+                uart1: serial@c0007000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0xc0007000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <20>;
+                        dmas = <&dmac 38 &dmac 39>;
+                        dma-names = "tx", "rx";
+                };
+
+                mmcsd: mmcsd@c0001000 {
+                        compatible = "arm,pl18x", "arm,primecell";
+                        reg = <0xc0001000 0x1000>;
+                        interrupt-parent = <&vicb>;
+                        interrupts = <6 7>;
+                        clocks = <&mmc_pclk>, <&mmc_mclk>;
+                        clock-names = "apb_pclk", "mclk";
+                        max-frequency = <24000000>;
+                        bus-width = <4>; // SD-card slot
+                        mmc-cap-mmc-highspeed;
+                        mmc-cap-sd-highspeed;
+                        cd-gpios = <&gpio 12 0x4>;
+                        cd-inverted;
+                        vmmc-supply = <&ab3100_ldo_g_reg>;
+                        dmas = <&dmac 14>;
+                        dma-names = "rx";
+                };
+
+                spi: ssp@c0006000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0xc0006000 0x1000>;
+                        interrupt-parent = <&vica>;
+                        interrupts = <23>;
+                        clocks = <&spi_clk>, <&spi_clk>;
+                        clock-names = "apb_pclk", "spi_clk";
+                        dmas = <&dmac 27 &dmac 28>;
+                        dma-names = "tx", "rx";
+                        num-cs = <3>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        spi-dummy@1 {
+                                compatible = "arm,pl022-dummy";
+                                reg = <1>;
+                                spi-max-frequency = <20000000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
new file mode 100644
index 000000000000..d4af53160435
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2000.dtsi"
+/ {
+        model = "STiH415 B2000 Board";
+        compatible = "st,stih415", "st,stih415-b2000";
+};
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
new file mode 100644
index 000000000000..442b019e9a3a
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih415.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+        model = "STiH415 B2020 Board";
+        compatible = "st,stih415", "st,stih415-b2020";
+};
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
new file mode 100644
index 000000000000..174c799df741
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        clocks {
+                /*
+                 * Fixed 30MHz oscillator input to SoC
+                 */
+                CLK_SYSIN: CLK_SYSIN {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                };
+
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: arm_periph_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <500000000>;
+                };
+
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <100000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
new file mode 100644
index 000000000000..1d322b24d1e4
--- /dev/null
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+        aliases {
+                gpio0   = &PIO0;
+                gpio1   = &PIO1;
+                gpio2   = &PIO2;
+                gpio3   = &PIO3;
+                gpio4   = &PIO4;
+                gpio5   = &PIO5;
+                gpio6   = &PIO6;
+                gpio7   = &PIO7;
+                gpio8   = &PIO8;
+                gpio9   = &PIO9;
+                gpio10  = &PIO10;
+                gpio11  = &PIO11;
+                gpio12  = &PIO12;
+                gpio13  = &PIO13;
+                gpio14  = &PIO14;
+                gpio15  = &PIO15;
+                gpio16  = &PIO16;
+                gpio17  = &PIO17;
+                gpio18  = &PIO18;
+                gpio19  = &PIO100;
+                gpio20  = &PIO101;
+                gpio21  = &PIO102;
+                gpio22  = &PIO103;
+                gpio23  = &PIO104;
+                gpio24  = &PIO105;
+                gpio25  = &PIO106;
+                gpio26  = &PIO107;
+        };
+
+        soc {
+                pin-controller-sbc {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-sbc-pinctrl";
+                        st,syscfg       = <&syscfg_sbc>;
+                        ranges          = <0 0xfe610000 0x5000>;
+
+                        PIO0: gpio@fe610000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO0";
+                        };
+                        PIO1: gpio@fe611000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO1";
+                        };
+                        PIO2: gpio@fe612000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO2";
+                        };
+                        PIO3: gpio@fe613000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO3";
+                        };
+                        PIO4: gpio@fe614000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO4";
+                        };
+
+                        sbc_serial1 {
+                                pinctrl_sbc_serial1:sbc_serial1 {
+                                        st,pins {
+                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                rx      = <&PIO2 7 ALT3 IN>;
+                                        };
+                                };
+                        };
+                };
+
+                pin-controller-front {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-front-pinctrl";
+                        st,syscfg       = <&syscfg_front>;
+                        ranges          = <0 0xfee00000 0x8000>;
+
+                        PIO5: gpio@fee00000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO5";
+                        };
+                        PIO6: gpio@fee01000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO6";
+                        };
+                        PIO7: gpio@fee02000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO7";
+                        };
+                        PIO8: gpio@fee03000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO8";
+                        };
+                        PIO9: gpio@fee04000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO9";
+                        };
+                        PIO10: gpio@fee05000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO10";
+                        };
+                        PIO11: gpio@fee06000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x6000 0x100>;
+                                st,bank-name    = "PIO11";
+                        };
+                        PIO12: gpio@fee07000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x7000 0x100>;
+                                st,bank-name    = "PIO12";
+                        };
+                };
+
+                pin-controller-rear {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-rear-pinctrl";
+                        st,syscfg       = <&syscfg_rear>;
+                        ranges          = <0 0xfe820000 0x8000>;
+
+                        PIO13: gpio@fe820000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO13";
+                        };
+                        PIO14: gpio@fe821000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO14";
+                        };
+                        PIO15: gpio@fe822000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO15";
+                        };
+                        PIO16: gpio@fe823000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO16";
+                        };
+                        PIO17: gpio@fe824000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO17";
+                        };
+                        PIO18: gpio@fe825000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO18";
+                        };
+
+                        serial2 {
+                                pinctrl_serial2: serial2-0 {
+                                        st,pins {
+                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                rx      = <&PIO17 5 ALT2 IN>;
+                                        };
+                                };
+                        };
+                };
+
+                pin-controller-left {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-left-pinctrl";
+                        st,syscfg       = <&syscfg_left>;
+                        ranges          = <0 0xfd6b0000 0x3000>;
+
+                        PIO100: gpio@fd6b0000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO100";
+                        };
+                        PIO101: gpio@fd6b1000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO101";
+                        };
+                        PIO102: gpio@fd6b2000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO102";
+                        };
+                };
+
+                pin-controller-right {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih415-right-pinctrl";
+                        st,syscfg       = <&syscfg_right>;
+                        ranges          = <0 0xfd330000 0x5000>;
+
+                        PIO103: gpio@fd330000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO103";
+                        };
+                        PIO104: gpio@fd331000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO104";
+                        };
+                        PIO105: gpio@fd332000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO105";
+                        };
+                        PIO106: gpio@fd333000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO106";
+                        };
+                        PIO107: gpio@fd334000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO107";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
new file mode 100644
index 000000000000..74ab8ded4b49
--- /dev/null
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih415-clock.dtsi"
+#include "stih415-pinctrl.dtsi"
+/ {
+
+        L2: cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0xfffe2000 0x1000>;
+                arm,data-latency = <3 2 2>;
+                arm,tag-latency = <1 1 1>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                compatible      = "simple-bus";
+
+                syscfg_sbc: sbc-syscfg@fe600000{
+                        compatible      = "st,stih415-sbc-syscfg", "syscon";
+                        reg             = <0xfe600000 0xb4>;
+                };
+
+                syscfg_front: front-syscfg@fee10000{
+                        compatible      = "st,stih415-front-syscfg", "syscon";
+                        reg             = <0xfee10000 0x194>;
+                };
+
+                syscfg_rear: rear-syscfg@fe830000{
+                        compatible      = "st,stih415-rear-syscfg", "syscon";
+                        reg             = <0xfe830000 0x190>;
+                };
+
+                /* MPE syscfgs */
+                syscfg_left: left-syscfg@fd690000{
+                        compatible      = "st,stih415-left-syscfg", "syscon";
+                        reg             = <0xfd690000 0x78>;
+                };
+
+                syscfg_right: right-syscfg@fd320000{
+                        compatible      = "st,stih415-right-syscfg", "syscon";
+                        reg             = <0xfd320000 0x180>;
+                };
+
+                syscfg_system: system-syscfg@fdde0000  {
+                        compatible      = "st,stih415-system-syscfg", "syscon";
+                        reg             = <0xfdde0000 0x15c>;
+                };
+
+                syscfg_lpm: lpm-syscfg@fe4b5100{
+                        compatible      = "st,stih415-lpm-syscfg", "syscon";
+                        reg             = <0xfe4b5100 0x08>;
+                };
+
+                serial2: serial@fed32000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfed32000 0x2c>;
+                        interrupts      = <0 197 0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_serial2>;
+                        clocks          = <&CLKS_ICN_REG_0>;
+                };
+
+                /* SBC comms block ASCs in SASG1 */
+                sbc_serial1: serial@fe531000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfe531000 0x2c>;
+                        interrupts      = <0 210 0>;
+                        clocks          = <&CLK_SYSIN>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_serial1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
new file mode 100644
index 000000000000..a5eb6eee10bf
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2000.dtsi"
+
+/ {
+        compatible = "st,stih416", "st,stih416-b2000";
+        model = "STiH416 B2000";
+};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
new file mode 100644
index 000000000000..276f28da573a
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+        model = "STiH416 B2020";
+        compatible = "st,stih416", "st,stih416-b2020";
+
+};
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
new file mode 100644
index 000000000000..7026bf1158d8
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics R&D Limited
+ * <stlinux-devel@stlinux.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        clocks {
+                /*
+                 * Fixed 30MHz oscillator inputs to SoC
+                 */
+                CLK_SYSIN: CLK_SYSIN {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                        clock-output-names = "CLK_SYSIN";
+                };
+
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: arm_periph_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <600000000>;
+                };
+
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                CLK_S_ICN_REG_0: clockgenA0@4 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <100000000>;
+                        clock-output-names = "CLK_S_ICN_REG_0";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
new file mode 100644
index 000000000000..957b21a71b4b
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -0,0 +1,295 @@
+
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+
+        aliases {
+                gpio0   = &PIO0;
+                gpio1   = &PIO1;
+                gpio2   = &PIO2;
+                gpio3   = &PIO3;
+                gpio4   = &PIO4;
+                gpio5   = &PIO40;
+                gpio6   = &PIO5;
+                gpio7   = &PIO6;
+                gpio8   = &PIO7;
+                gpio9   = &PIO8;
+                gpio10  = &PIO9;
+                gpio11  = &PIO10;
+                gpio12  = &PIO11;
+                gpio13  = &PIO12;
+                gpio14  = &PIO30;
+                gpio15  = &PIO31;
+                gpio16  = &PIO13;
+                gpio17  = &PIO14;
+                gpio18  = &PIO15;
+                gpio19  = &PIO16;
+                gpio20  = &PIO17;
+                gpio21  = &PIO18;
+                gpio22  = &PIO100;
+                gpio23  = &PIO101;
+                gpio24  = &PIO102;
+                gpio25  = &PIO103;
+                gpio26  = &PIO104;
+                gpio27  = &PIO105;
+                gpio28  = &PIO106;
+                gpio29  = &PIO107;
+        };
+
+        soc {
+                pin-controller-sbc {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-sbc-pinctrl";
+                        st,syscfg       = <&syscfg_sbc>;
+                        ranges          = <0 0xfe610000 0x6000>;
+
+                        PIO0: gpio@fe610000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO0";
+                        };
+                        PIO1: gpio@fe611000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO1";
+                        };
+                        PIO2: gpio@fe612000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO2";
+                        };
+                        PIO3: gpio@fe613000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO3";
+                        };
+                        PIO4: gpio@fe614000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO4";
+                        };
+                        PIO40: gpio@fe615000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO40";
+                                st,retime-pin-mask = <0x7f>;
+                        };
+
+                        sbc_serial1 {
+                                pinctrl_sbc_serial1: sbc_serial1 {
+                                        st,pins {
+                                                tx      = <&PIO2 6 ALT3 OUT>;
+                                                rx      = <&PIO2 7 ALT3 IN>;
+                                        };
+                                };
+                        };
+                };
+
+                pin-controller-front {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-front-pinctrl";
+                        st,syscfg       = <&syscfg_front>;
+                        ranges          = <0 0xfee00000 0x10000>;
+
+                        PIO5: gpio@fee00000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO5";
+                        };
+                        PIO6: gpio@fee01000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO6";
+                        };
+                        PIO7: gpio@fee02000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO7";
+                        };
+                        PIO8: gpio@fee03000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO8";
+                        };
+                        PIO9: gpio@fee04000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO9";
+                        };
+                        PIO10: gpio@fee05000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO10";
+                        };
+                        PIO11: gpio@fee06000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x6000 0x100>;
+                                st,bank-name    = "PIO11";
+                        };
+                        PIO12: gpio@fee07000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x7000 0x100>;
+                                st,bank-name    = "PIO12";
+                        };
+                        PIO30: gpio@fee08000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x8000 0x100>;
+                                st,bank-name    = "PIO30";
+                        };
+                        PIO31: gpio@fee09000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x9000 0x100>;
+                                st,bank-name    = "PIO31";
+                        };
+                };
+
+                pin-controller-rear {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-rear-pinctrl";
+                        st,syscfg       = <&syscfg_rear>;
+                        ranges          = <0 0xfe820000 0x6000>;
+
+                        PIO13: gpio@fe820000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO13";
+                        };
+                        PIO14: gpio@fe821000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO14";
+                        };
+                        PIO15: gpio@fe822000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO15";
+                        };
+                        PIO16: gpio@fe823000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO16";
+                        };
+                        PIO17: gpio@fe824000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO17";
+                        };
+                        PIO18: gpio@fe825000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x5000 0x100>;
+                                st,bank-name    = "PIO18";
+                                st,retime-pin-mask = <0xf>;
+                        };
+
+                        serial2 {
+                                pinctrl_serial2: serial2-0 {
+                                        st,pins {
+                                                tx      = <&PIO17 4 ALT2 OUT>;
+                                                rx      = <&PIO17 5 ALT2 IN>;
+                                                output-enable   = <&PIO11 3 ALT2 OUT>;
+                                        };
+                                };
+                        };
+                };
+
+                pin-controller-fvdp-fe {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-fvdp-fe-pinctrl";
+                        st,syscfg       = <&syscfg_fvdp_fe>;
+                        ranges          = <0 0xfd6b0000 0x3000>;
+
+                        PIO100: gpio@fd6b0000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO100";
+                        };
+                        PIO101: gpio@fd6b1000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO101";
+                        };
+                        PIO102: gpio@fd6b2000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO102";
+                        };
+                };
+
+                pin-controller-fvdp-lite {
+                        #address-cells  = <1>;
+                        #size-cells     = <1>;
+                        compatible      = "st,stih416-fvdp-lite-pinctrl";
+                        st,syscfg               = <&syscfg_fvdp_lite>;
+                        ranges                  = <0 0xfd330000 0x5000>;
+
+                        PIO103: gpio@fd330000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0 0x100>;
+                                st,bank-name    = "PIO103";
+                        };
+                        PIO104: gpio@fd331000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x1000 0x100>;
+                                st,bank-name    = "PIO104";
+                        };
+                        PIO105: gpio@fd332000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x2000 0x100>;
+                                st,bank-name    = "PIO105";
+                        };
+                        PIO106: gpio@fd333000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x3000 0x100>;
+                                st,bank-name    = "PIO106";
+                        };
+
+                        PIO107: gpio@fd334000 {
+                                gpio-controller;
+                                #gpio-cells     = <1>;
+                                reg             = <0x4000 0x100>;
+                                st,bank-name    = "PIO107";
+                                st,retime-pin-mask = <0xf>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
new file mode 100644
index 000000000000..3cecd9689a49
--- /dev/null
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih41x.dtsi"
+#include "stih416-clock.dtsi"
+#include "stih416-pinctrl.dtsi"
+/ {
+        L2: cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0xfffe2000 0x1000>;
+                arm,data-latency = <3 3 3>;
+                arm,tag-latency = <2 2 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                compatible      = "simple-bus";
+
+                syscfg_sbc:sbc-syscfg@fe600000{
+                        compatible      = "st,stih416-sbc-syscfg", "syscon";
+                        reg             = <0xfe600000 0x1000>;
+                };
+
+                syscfg_front:front-syscfg@fee10000{
+                        compatible      = "st,stih416-front-syscfg", "syscon";
+                        reg             = <0xfee10000 0x1000>;
+                };
+
+                syscfg_rear:rear-syscfg@fe830000{
+                        compatible      = "st,stih416-rear-syscfg", "syscon";
+                        reg             = <0xfe830000 0x1000>;
+                };
+
+                /* MPE */
+                syscfg_fvdp_fe:fvdp-fe-syscfg@fddf0000{
+                        compatible      = "st,stih416-fvdp-fe-syscfg", "syscon";
+                        reg             = <0xfddf0000 0x1000>;
+                };
+
+                syscfg_fvdp_lite:fvdp-lite-syscfg@fd6a0000{
+                        compatible      = "st,stih416-fvdp-lite-syscfg", "syscon";
+                        reg             = <0xfd6a0000 0x1000>;
+                };
+
+                syscfg_cpu:cpu-syscfg@fdde0000{
+                        compatible      = "st,stih416-cpu-syscfg", "syscon";
+                        reg             = <0xfdde0000 0x1000>;
+                };
+
+                syscfg_compo:compo-syscfg@fd320000{
+                        compatible      = "st,stih416-compo-syscfg", "syscon";
+                        reg             = <0xfd320000 0x1000>;
+                };
+
+                syscfg_transport:transport-syscfg@fd690000{
+                        compatible      = "st,stih416-transport-syscfg", "syscon";
+                        reg             = <0xfd690000 0x1000>;
+                };
+
+                syscfg_lpm:lpm-syscfg@fe4b5100{
+                        compatible      = "st,stih416-lpm-syscfg", "syscon";
+                        reg             = <0xfe4b5100 0x8>;
+                };
+
+                serial2: serial@fed32000{
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfed32000 0x2c>;
+                        interrupts      = <0 197 0>;
+                        clocks          = <&CLK_S_ICN_REG_0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_serial2>;
+                };
+
+                /* SBC_UART1 */
+                sbc_serial1: serial@fe531000 {
+                        compatible      = "st,asc";
+                        status          = "disabled";
+                        reg             = <0xfe531000 0x2c>;
+                        interrupts      = <0 210 0>;
+                        pinctrl-names   = "default";
+                        pinctrl-0       = <&pinctrl_sbc_serial1>;
+                        clocks          = <&CLK_SYSIN>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
new file mode 100644
index 000000000000..8e694d2b8f5b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+
+        memory{
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyAS0,115200";
+                linux,stdout-path = &serial2;
+        };
+
+        aliases {
+                ttyAS0 = &serial2;
+        };
+
+        soc {
+                serial2: serial@fed32000 {
+                        status = "okay";
+                };
+
+                leds {
+                        compatible      = "gpio-leds";
+                        fp_led {
+                                #gpio-cells = <1>;
+                                label   = "Front Panel LED";
+                                gpios   = <&PIO105 7>;
+                                linux,default-trigger   = "heartbeat";
+                        };
+                };
+
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
new file mode 100644
index 000000000000..133e18143b1b
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/ {
+        memory{
+                device_type = "memory";
+                reg = <0x40000000 0x80000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyAS0,115200";
+                linux,stdout-path = &sbc_serial1;
+        };
+
+        aliases {
+                ttyAS0 = &sbc_serial1;
+        };
+        soc {
+                sbc_serial1: serial@fe531000 {
+                        status = "okay";
+                };
+
+                leds {
+                        compatible      = "gpio-leds";
+                        red {
+                                #gpio-cells = <1>;
+                                label   = "Front Panel LED";
+                                gpios   = <&PIO4 1>;
+                                linux,default-trigger   = "heartbeat";
+                        };
+                        green {
+                                gpios   = <&PIO4 7>;
+                                default-state = "off";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
new file mode 100644
index 000000000000..7321403cab8a
--- /dev/null
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -0,0 +1,38 @@
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+
+        intc: interrupt-controller@fffe1000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xfffe1000 0x1000>,
+                      <0xfffe0100 0x100>;
+        };
+
+        scu@fffe0000 {
+                compatible = "arm,cortex-a9-scu";
+                reg = <0xfffe0000 0x1000>;
+        };
+
+        timer@fffe0200 {
+                interrupt-parent = <&intc>;
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0xfffe0200 0x100>;
+                interrupts = <1 11 0x04>;
+                clocks = <&arm_periph_clk>;
+        };
+};
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/stuib.dtsi
index 615392a75676..524e33240ad4 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/stuib.dtsi
@@ -9,13 +9,15 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
+#include <dt-bindings/interrupt-controller/irq.h>
+
 / {
-        soc-u9500 {
+        soc {
                 i2c@80004000 {
                         stmpe1601: stmpe1601@40 {
                                 compatible = "st,stmpe1601";
                                 reg = <0x40>;
-                                interrupts = <26 0x2>;
+                                interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
                                 interrupt-parent = <&gpio6>;
                                 interrupt-controller;
 
@@ -52,26 +54,26 @@
                 };
 
                 i2c@80110000 {
-                        bu21013_tp@0x5c {
-                                compatible = "rhom,bu21013_tp";
+                        bu21013_tp@5c {
+                                compatible = "rohm,bu21013_tp";
                                 reg = <0x5c>;
                                 touch-gpio = <&gpio2 20 0x4>;
                                 avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-                                rhom,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,touch-max-x = <384>;
+                                rohm,touch-max-y = <704>;
+                                rohm,flip-y;
                         };
 
-                        bu21013_tp@0x5d {
-                                compatible = "rhom,bu21013_tp";
+                        bu21013_tp@5d {
+                                compatible = "rohm,bu21013_tp";
                                 reg = <0x5d>;
                                 touch-gpio = <&gpio2 20 0x4>;
                                 avdd-supply = <&ab8500_ldo_aux1_reg>;
 
-                                rhom,touch-max-x = <384>;
-                                rhom,touch-max-y = <704>;
-                                rhom,flip-y;
+                                rohm,touch-max-x = <384>;
+                                rohm,touch-max-y = <704>;
+                                rohm,flip-y;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b70fe0db6bb7..0e22a285dfe0 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -41,6 +41,18 @@
                         pinctrl-0 = <&uart0_pins_a>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e7ef619a70a2..82e03d22f913 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -16,8 +16,12 @@
         interrupt-parent = <&intc>;
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                 };
         };
 
@@ -173,8 +177,10 @@
                 pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun4i-a10-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                         clocks = <&apb0_gates 5>;
                         gpio-controller;
+                        interrupt-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         #gpio-cells = <3>;
@@ -199,6 +205,27 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB18", "PB19";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB20", "PB21";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -292,5 +319,32 @@
                         clocks = <&apb1_gates 23>;
                         status = "disabled";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
new file mode 100644
index 000000000000..64dc0c42c43a
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "sun5i-a10s.dtsi"
+
+/ {
+        model = "Olimex A10s-Olinuxino Micro";
+        compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
+
+        soc@01c20000 {
+                emac: ethernet@01c0b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&emac_pins_a>;
+                        phy = <&phy1>;
+                        status = "okay";
+                };
+
+                mdio@01c0b080 {
+                        status = "okay";
+
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+
+                pinctrl@01c20800 {
+                        led_pins_olinuxino: led_pins@0 {
+                                allwinner,pins = "PE3";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+
+                uart2: serial@01c28800 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart2_pins_a>;
+                        status = "okay";
+                };
+
+                uart3: serial@01c28c00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart3_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_olinuxino>;
+
+                green {
+                        label = "a10s-olinuxino-micro:green:usr";
+                        gpios = <&pio 4 3 0>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
new file mode 100644
index 000000000000..2307ce827ae0
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2013 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        interrupt-parent = <&intc>;
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
+        memory {
+                reg = <0x40000000 0x20000000>;
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * This is a dummy clock, to be used as placeholder on
+                 * other mux clocks when a specific parent clock is not
+                 * yet implemented. It should be dropped when the driver
+                 * is complete.
+                 */
+                dummy: dummy {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <0>;
+                };
+
+                osc24M: osc24M@01c20050 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-osc-clk";
+                        reg = <0x01c20050 0x4>;
+                        clock-frequency = <24000000>;
+                };
+
+                osc32k: osc32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                pll1: pll1@01c20000 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-pll1-clk";
+                        reg = <0x01c20000 0x4>;
+                        clocks = <&osc24M>;
+                };
+
+                /* dummy is 200M */
+                cpu: cpu@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-cpu-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
+                };
+
+                axi: axi@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-axi-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&cpu>;
+                };
+
+                axi_gates: axi_gates@01c2005c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-axi-gates-clk";
+                        reg = <0x01c2005c 0x4>;
+                        clocks = <&axi>;
+                        clock-output-names = "axi_dram";
+                };
+
+                ahb: ahb@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-ahb-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&axi>;
+                };
+
+                ahb_gates: ahb_gates@01c20060 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        reg = <0x01c20060 0x8>;
+                        clocks = <&ahb>;
+                        clock-output-names = "ahb_usb0", "ahb_ehci0",
+                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
+                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
+                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
+                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
+                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
+                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
+                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
+                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
+                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                };
+
+                apb0: apb0@01c20054 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb0-clk";
+                        reg = <0x01c20054 0x4>;
+                        clocks = <&ahb>;
+                };
+
+                apb0_gates: apb0_gates@01c20068 {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        reg = <0x01c20068 0x4>;
+                        clocks = <&apb0>;
+                        clock-output-names = "apb0_codec", "apb0_spdif",
+                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
+                                "apb0_ir1", "apb0_keypad";
+                };
+
+                /* dummy is pll62 */
+                apb1_mux: apb1_mux@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-mux-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&osc24M>, <&dummy>, <&osc32k>;
+                };
+
+                apb1: apb1@01c20058 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-apb1-clk";
+                        reg = <0x01c20058 0x4>;
+                        clocks = <&apb1_mux>;
+                };
+
+                apb1_gates: apb1_gates@01c2006c {
+                        #clock-cells = <1>;
+                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        reg = <0x01c2006c 0x4>;
+                        clocks = <&apb1>;
+                        clock-output-names = "apb1_i2c0", "apb1_i2c1",
+                                "apb1_i2c2", "apb1_can", "apb1_scr",
+                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
+                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
+                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
+                                "apb1_uart7";
+                };
+        };
+
+        soc@01c20000 {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x01c20000 0x300000>;
+                ranges;
+
+                emac: ethernet@01c0b000 {
+                        compatible = "allwinner,sun4i-emac";
+                        reg = <0x01c0b000 0x1000>;
+                        interrupts = <55>;
+                        clocks = <&ahb_gates 17>;
+                        status = "disabled";
+                };
+
+                mdio@01c0b080 {
+                        compatible = "allwinner,sun4i-mdio";
+                        reg = <0x01c0b080 0x14>;
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                intc: interrupt-controller@01c20400 {
+                        compatible = "allwinner,sun4i-ic";
+                        reg = <0x01c20400 0x400>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                pio: pinctrl@01c20800 {
+                        compatible = "allwinner,sun5i-a10s-pinctrl";
+                        reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
+                        clocks = <&apb0_gates 5>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB19", "PB20";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart2_pins_a: uart2@0 {
+                                allwinner,pins = "PC18", "PC19";
+                                allwinner,function = "uart2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        uart3_pins_a: uart3@0 {
+                                allwinner,pins = "PG9", "PG10";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+
+                timer@01c20c00 {
+                        compatible = "allwinner,sun4i-timer";
+                        reg = <0x01c20c00 0x90>;
+                        interrupts = <22>;
+                        clocks = <&osc24M>;
+                };
+
+                wdt: watchdog@01c20c90 {
+                        compatible = "allwinner,sun4i-wdt";
+                        reg = <0x01c20c90 0x10>;
+                };
+
+                uart0: serial@01c28000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28000 0x400>;
+                        interrupts = <1>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 16>;
+                        status = "disabled";
+                };
+
+                uart1: serial@01c28400 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28400 0x400>;
+                        interrupts = <2>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 17>;
+                        status = "disabled";
+                };
+
+                uart2: serial@01c28800 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28800 0x400>;
+                        interrupts = <3>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 18>;
+                        status = "disabled";
+                };
+
+                uart3: serial@01c28c00 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0x01c28c00 0x400>;
+                        interrupts = <4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                        clocks = <&apb1_gates 19>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 3ca55067f868..80497e376706 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -37,6 +37,24 @@
                         pinctrl-0 = <&uart1_pins_b>;
                         status = "okay";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_pins_a>;
+                        status = "okay";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_pins_a>;
+                        status = "okay";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_pins_a>;
+                        status = "okay";
+                };
         };
 
         leds {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 31fa38f8cc98..7363211daf84 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -17,8 +17,12 @@
         interrupt-parent = <&intc>;
 
         cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
                 cpu@0 {
+                        device_type = "cpu";
                         compatible = "arm,cortex-a8";
+                        reg = <0x0>;
                 };
         };
 
@@ -95,20 +99,15 @@
 
                 ahb_gates: ahb_gates@01c20060 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-ahb-gates-clk";
+                        compatible = "allwinner,sun5i-a13-ahb-gates-clk";
                         reg = <0x01c20060 0x8>;
                         clocks = <&ahb>;
-                        clock-output-names = "ahb_usb0", "ahb_ehci0",
-                                "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
-                                "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
-                                "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
-                                "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
-                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
-                                "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
-                                "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
-                                "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
-                                "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
-                                "ahb_de_fe1", "ahb_mp", "ahb_mali400";
+                        clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
+                                "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
+                                "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
+                                "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
+                                "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
+                                "ahb_de_fe", "ahb_iep", "ahb_mali400";
                 };
 
                 apb0: apb0@01c20054 {
@@ -120,15 +119,13 @@
 
                 apb0_gates: apb0_gates@01c20068 {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb0-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb0-gates-clk";
                         reg = <0x01c20068 0x4>;
                         clocks = <&apb0>;
-                        clock-output-names = "apb0_codec", "apb0_spdif",
-                                "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
-                                "apb0_ir1", "apb0_keypad";
+                        clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
                 };
 
-                /* dummy is pll62 */
+                /* dummy is pll6 */
                 apb1_mux: apb1_mux@01c20058 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-apb1-mux-clk";
@@ -145,15 +142,11 @@
 
                 apb1_gates: apb1_gates@01c2006c {
                         #clock-cells = <1>;
-                        compatible = "allwinner,sun4i-apb1-gates-clk";
+                        compatible = "allwinner,sun5i-a13-apb1-gates-clk";
                         reg = <0x01c2006c 0x4>;
                         clocks = <&apb1>;
                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
-                                "apb1_i2c2", "apb1_can", "apb1_scr",
-                                "apb1_ps20", "apb1_ps21", "apb1_uart0",
-                                "apb1_uart1", "apb1_uart2", "apb1_uart3",
-                                "apb1_uart4", "apb1_uart5", "apb1_uart6",
-                                "apb1_uart7";
+                                "apb1_i2c2", "apb1_uart1", "apb1_uart3";
                 };
         };
 
@@ -174,8 +167,10 @@
                 pio: pinctrl@01c20800 {
                         compatible = "allwinner,sun5i-a13-pinctrl";
                         reg = <0x01c20800 0x400>;
+                        interrupts = <28>;
                         clocks = <&apb0_gates 5>;
                         gpio-controller;
+                        interrupt-controller;
                         #address-cells = <1>;
                         #size-cells = <0>;
                         #gpio-cells = <3>;
@@ -193,6 +188,27 @@
                                 allwinner,drive = <0>;
                                 allwinner,pull = <0>;
                         };
+
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB15", "PB16";
+                                allwinner,function = "i2c1";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB17", "PB18";
+                                allwinner,function = "i2c2";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                 };
 
                 timer@01c20c00 {
@@ -226,5 +242,32 @@
                         clocks = <&apb1_gates 19>;
                         status = "disabled";
                 };
+
+                i2c0: i2c@01c2ac00 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2ac00 0x400>;
+                        interrupts = <7>;
+                        clocks = <&apb1_gates 0>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c1: i2c@01c2b000 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b000 0x400>;
+                        interrupts = <8>;
+                        clocks = <&apb1_gates 1>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
+
+                i2c2: i2c@01c2b400 {
+                        compatible = "allwinner,sun4i-i2c";
+                        reg = <0x01c2b400 0x400>;
+                        interrupts = <9>;
+                        clocks = <&apb1_gates 2>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index 72c1f27af7f3..cb640eb6c932 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
         model = "NVIDIA Tegra114 Dalmore evaluation board";
@@ -727,6 +727,16 @@
                         battery-name = "battery";
                         sbs,i2c-retry-count = <2>;
                         sbs,poll-retry-count = <100>;
+                        power-supplies = <&charger>;
+                };
+
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -748,7 +758,7 @@
                         compatible = "ti,tps65090";
                         reg = <0x48>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <72 0x04>; /* gpio PJ0 */
+                        interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_LEVEL_HIGH>;
 
                         vsys1-supply = <&vdd_ac_bat_reg>;
                         vsys2-supply = <&vdd_ac_bat_reg>;
@@ -763,6 +773,11 @@
                         vsys-l1-supply = <&vdd_ac_bat_reg>;
                         vsys-l2-supply = <&vdd_ac_bat_reg>;
 
+                        charger: charger {
+                                compatible = "ti,tps65090-charger";
+                                ti,enable-low-current-chrg;
+                        };
+
                         regulators {
                                 tps65090_dcdc1_reg: dcdc1 {
                                         regulator-name = "vdd-sys-5v0";
@@ -823,12 +838,28 @@
                 };
         };
 
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
+
         pmc {
                 nvidia,invert-interrupt;
         };
 
+        ahub {
+                i2s@70080400 {
+                        status = "okay";
+                };
+        };
+
         sdhci@78000400 {
-                cd-gpios = <&gpio 170 1>; /* gpio PV2 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                 bus-width = <4>;
                 status = "okay";
         };
@@ -873,7 +904,7 @@
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <1800000>;
                         enable-active-high;
-                        gpio = <&gpio 61 0>; /* GPIO PH5 */
+                        gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
                 };
 
                 lcd_bl_en_reg: regulator@2 {
@@ -883,7 +914,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 58 0>; /* GPIO PH2 */
+                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@3 {
@@ -893,7 +924,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 108 0>; /* GPIO PN4 */
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
@@ -905,7 +936,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 86 0>; /* GPIO PK6 */
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
@@ -917,8 +948,32 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 81 0>; /* GPIO PK1 */
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&tps65090_dcdc1_reg>;
                 };
         };
+
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-dalmore",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Dalmore";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL",
+                        "Speakers", "SPORP",
+                        "Speakers", "SPORN",
+                        "Speakers", "SPOLP",
+                        "Speakers", "SPOLN";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA114_CLK_PLL_A>,
+                         <&tegra_car TEGRA114_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA114_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8efae9c0..d5f8d3e0bde2 100644
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/arch/arm/boot/dts/tegra114-pluto.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra114.dtsi"
+#include "tegra114.dtsi"
 
 / {
         model = "NVIDIA Tegra114 Pluto evaluation board";
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 629415ffd8dc..abf6c40d28c6 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra114-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra114";
@@ -19,19 +23,20 @@
                       <0x50042000 0x1000>,
                       <0x50044000 0x2000>,
                       <0x50046000 0x2000>;
-                interrupts = <1 9 0xf04>;
+                interrupts = <GIC_PPI 9
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
         };
 
         timer@60005000 {
                 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
                 reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04
-                              0 121 0x04
-                              0 122 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -43,39 +48,39 @@
         apbdma: dma {
                 compatible = "nvidia,tegra114-apbdma";
                 reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04
-                              0 128 0x04
-                              0 129 0x04
-                              0 130 0x04
-                              0 131 0x04
-                              0 132 0x04
-                              0 133 0x04
-                              0 134 0x04
-                              0 135 0x04
-                              0 136 0x04
-                              0 137 0x04
-                              0 138 0x04
-                              0 139 0x04
-                              0 140 0x04
-                              0 141 0x04
-                              0 142 0x04
-                              0 143 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
         };
 
         ahb: ahb {
@@ -86,14 +91,14 @@
         gpio: gpio {
                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04
-                              0 125 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -118,57 +123,57 @@
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
                 status = "disabled";
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTA>;
         };
 
         uartb: serial@70006040 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
                 status = "disabled";
-                clocks = <&tegra_car 192>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTB>;
         };
 
         uartc: serial@70006200 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
                 status = "disabled";
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTC>;
         };
 
         uartd: serial@70006300 {
                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
                 status = "disabled";
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA114_CLK_UARTD>;
         };
 
         pwm: pwm {
                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA114_CLK_PWM>;
                 status = "disabled";
         };
 
         i2c@7000c000 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C1>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -176,10 +181,10 @@
         i2c@7000c400 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C2>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -187,10 +192,10 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C3>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -198,10 +203,10 @@
         i2c@7000c700 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 103>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C4>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -209,10 +214,10 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra114-i2c";
                 reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>;
+                clocks = <&tegra_car TEGRA114_CLK_I2C5>;
                 clock-names = "div-clk";
                 status = "disabled";
         };
@@ -220,11 +225,11 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC1>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -232,11 +237,11 @@
         spi@7000d600 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC2>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -244,11 +249,11 @@
         spi@7000d800 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC3>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -256,11 +261,11 @@
         spi@7000da00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC4>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -268,11 +273,11 @@
         spi@7000dc00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC5>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -280,11 +285,11 @@
         spi@7000de00 {
                 compatible = "nvidia,tegra114-spi";
                 reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA114_CLK_SBC6>;
                 clock-names = "spi";
                 status = "disabled";
         };
@@ -292,22 +297,22 @@
         rtc {
                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_RTC>;
         };
 
         kbc {
                 compatible = "nvidia,tegra114-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 261>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -322,35 +327,106 @@
                 nvidia,ahb = <&ahb>;
         };
 
+        ahub {
+                compatible = "nvidia,tegra114-ahub";
+                reg = <0x70080000 0x200>,
+                      <0x70080200 0x100>,
+                      <0x70081000 0x200>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
+                        <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
+                        <&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
+                        <&apbdma 29>;
+                clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA114_CLK_APBIF>,
+                         <&tegra_car TEGRA114_CLK_I2S0>,
+                         <&tegra_car TEGRA114_CLK_I2S1>,
+                         <&tegra_car TEGRA114_CLK_I2S2>,
+                         <&tegra_car TEGRA114_CLK_I2S3>,
+                         <&tegra_car TEGRA114_CLK_I2S4>,
+                         <&tegra_car TEGRA114_CLK_DAM0>,
+                         <&tegra_car TEGRA114_CLK_DAM1>,
+                         <&tegra_car TEGRA114_CLK_DAM2>,
+                         <&tegra_car TEGRA114_CLK_SPDIF_IN>,
+                         <&tegra_car TEGRA114_CLK_AMX>,
+                         <&tegra_car TEGRA114_CLK_ADX>;
+                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                              "spdif_in", "amx", "adx";
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                tegra_i2s0: i2s@70080300 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080300 0x100>;
+                        nvidia,ahub-cif-ids = <4 4>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+                        status = "disabled";
+                };
+
+                tegra_i2s1: i2s@70080400 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080400 0x100>;
+                        nvidia,ahub-cif-ids = <5 5>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+                        status = "disabled";
+                };
+
+                tegra_i2s2: i2s@70080500 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080500 0x100>;
+                        nvidia,ahub-cif-ids = <6 6>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+                        status = "disabled";
+                };
+
+                tegra_i2s3: i2s@70080600 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080600 0x100>;
+                        nvidia,ahub-cif-ids = <7 7>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+                        status = "disabled";
+                };
+
+                tegra_i2s4: i2s@70080700 {
+                        compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
+                        reg = <0x70080700 0x100>;
+                        nvidia,ahub-cif-ids = <8 8>;
+                        clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+                        status = "disabled";
+                };
+        };
+
         sdhci@78000000 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
                 status = "disable";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
                 status = "disable";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
                 status = "disable";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
                 reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
                 status = "disable";
         };
 
@@ -385,9 +461,14 @@
 
         timer {
                 compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                             <1 14 0xf08>,
-                             <1 11 0xf08>,
-                             <1 10 0xf08>;
+                interrupts =
+                        <GIC_PPI 13
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index a573b94b7c93..2fcb3f2ca160 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Toradex Colibri T20 512MB";
@@ -14,7 +14,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&i2c_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -217,7 +218,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -443,17 +444,25 @@
 
         ac97: ac97 {
                 status = "okay";
-                nvidia,codec-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
-                nvidia,codec-sync-gpio = <&gpio 120 0>; /* gpio PP0 */
+                nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,codec-sync-gpio = <&gpio TEGRA_GPIO(P, 0)
+                        GPIO_ACTIVE_HIGH>;
         };
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         sdhci@c8000600 {
-                cd-gpios = <&gpio 23 1>; /* gpio PC7 */
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
         };
 
         clocks {
@@ -483,7 +492,9 @@
 
                 nvidia,ac97-controller = <&ac97>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 
@@ -510,7 +521,7 @@
                         enable-active-high;
                         regulator-boot-on;
                         regulator-always-on;
-                        gpio = <&gpio 217 0>;
+                        gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e7d5de4e00b9..d9f89cd879a7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Harmony evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -262,7 +263,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -290,7 +291,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -428,32 +429,43 @@
                 status = "okay";
         };
 
+        usb-phy@c5000000 {
+                status = "okay";
+        };
+
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
-        usb-phy@c5004400 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        usb-phy@c5008000 {
+                status = "okay";
         };
 
         sdhci@c8000200 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <8>;
         };
 
@@ -475,7 +487,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -618,7 +630,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -627,7 +639,7 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -637,7 +649,7 @@
                         regulator-name = "vdd_1v05";
                         regulator-min-microvolt = <1050000>;
                         regulator-max-microvolt = <1050000>;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                         /* Hack until board-harmony-pcie.c is removed */
                         status = "disabled";
@@ -649,7 +661,7 @@
                         regulator-name = "vdd_pnl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -659,7 +671,7 @@
                         regulator-name = "vdd_bl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -682,12 +694,17 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
-
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index 52f1103907d7..f2222bd74eab 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-colibri-512.dtsi"
+#include "tegra20-colibri-512.dtsi"
 
 / {
         model = "Toradex Colibri T20 512MB on Iris";
@@ -38,13 +38,20 @@
 
         usb@c5000000 {
                 status = "okay";
-                dr_mode = "otg";
+        };
+
+        usb-phy@c5000000 {
+                status = "okay";
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
+        usb-phy@c5008000 {
+                status = "okay";
+        };
+
         serial@70006000 {
                 status = "okay";
         };
@@ -73,7 +80,7 @@
                         regulator-max-microvolt = <5000000>;
                         regulator-boot-on;
                         regulator-always-on;
-                        gpio = <&gpio 178 0>;
+                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 vcc_sd_reg: regulator@1 {
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index ace23437da89..7580578903cf 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Medcom-Wide board";
@@ -15,7 +15,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -56,10 +56,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e3e0c9977df4..cfd12763b1b2 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Toshiba AC100 / Dynabook AZ";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -270,13 +271,14 @@
         nvec {
                 compatible = "nvidia,nvec";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
                 clock-frequency = <80000>;
-                request-gpios = <&gpio 170 0>; /* gpio PV2 */
+                request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                 slave-addr = <138>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
         };
 
@@ -287,7 +289,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         #gpio-cells = <2>;
                         gpio-controller;
@@ -427,24 +429,35 @@
                 status = "okay";
         };
 
+        usb-phy@c5000000 {
+                status = "okay";
+        };
+
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
-        usb-phy@c5004400 {
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        usb-phy@c5008000 {
+                status = "okay";
         };
 
         sdhci@c8000000 {
                 status = "okay";
-                cd-gpios = <&gpio 173 1>; /* gpio PV5 */
-                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
-                power-gpios = <&gpio 169 0>; /* gpio PV1 */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -472,7 +485,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 79 1>; /* gpio PJ7, active low */
+                        gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -483,7 +496,7 @@
 
                 wifi {
                         label = "wifi-led";
-                        gpios = <&gpio 24 0>; /* gpio PD0 */
+                        gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "rfkill0";
                 };
         };
@@ -520,9 +533,12 @@
 
                 nvidia,audio-codec = <&alc5632>;
                 nvidia,i2s-controller = <&tegra_i2s1>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 1a17cc30bb9d..d7a358a6a647 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Plutux board";
@@ -17,7 +17,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -50,10 +50,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index cee4c34010fe..ab177b406b78 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Seaboard";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -313,7 +314,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -328,14 +329,14 @@
                         compatible = "isil,isl29018";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /* GPIO PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                 };
 
                 gyrometer@68 {
                         compatible = "invn,mpu3050";
                         reg = <0x68>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <204 0x04>; /* gpio PZ4 */
+                        interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -388,7 +389,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -511,7 +512,7 @@
                         compatible = "ak,ak8975";
                         reg = <0xc>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <109 0x04>; /* gpio PN5 */
+                        interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -565,35 +566,48 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
+                dr_mode = "otg";
+        };
+
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus_reg>;
                 dr_mode = "otg";
         };
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
-        usb-phy@c5004400 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        usb-phy@c5008000 {
+                status = "okay";
         };
 
         sdhci@c8000000 {
                 status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -621,14 +635,14 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
 
                 lid {
                         label = "Lid";
-                        gpios = <&gpio 23 0>; /* gpio PC7 */
+                        gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
                         linux,input-type = <5>; /* EV_SW */
                         linux,code = <0>; /* SW_LID */
                         debounce-interval = <1>;
@@ -795,7 +809,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -804,9 +818,18 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
+
+                vbus_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_vbus_wup1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio 24 0>; /* PD0 */
+                };
         };
 
         sound {
@@ -827,10 +850,12 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 50b3ec16b93a..c54faae7cfb3 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Avionic Design Tamonten SOM";
@@ -14,7 +14,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -321,7 +322,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -470,9 +471,13 @@
                 status = "okay";
         };
 
+        usb-phy@c5008000 {
+                status = "okay";
+        };
+
         sdhci@c8000600 {
-                cd-gpios = <&gpio 58 1>; /* gpio PH2 */
-                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
+                cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 status = "okay";
         };
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 742f0b38d21d..c572c43751b1 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20-tamonten.dtsi"
+#include "tegra20-tamonten.dtsi"
 
 / {
         model = "Avionic Design Tamonten Evaluation Carrier";
@@ -17,7 +17,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -50,10 +50,13 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9cc78a15d739..170159910455 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "Compulab TrimSlice board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -311,20 +312,32 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
+                nvidia,vbus-gpio = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+        };
+
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus_reg>;
         };
 
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
-        usb-phy@c5004400 {
-                nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
+        usb-phy@c5008000 {
+                status = "okay";
         };
 
         sdhci@c8000000 {
@@ -334,8 +347,8 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                cd-gpios = <&gpio 121 1>; /* gpio PP1 */
-                wp-gpios = <&gpio 122 0>; /* gpio PP2 */
+                cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -357,7 +370,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 190 1>; /* gpio PX6, active low */
+                        gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -365,7 +378,7 @@
 
         poweroff {
                 compatible = "gpio-poweroff";
-                gpios = <&gpio 191 1>; /* gpio PX7, active low */
+                gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
         };
 
         regulators {
@@ -390,6 +403,15 @@
                         regulator-max-microvolt = <1800000>;
                         regulator-always-on;
                 };
+
+                vbus_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio 170 0>; /* PV2 */
+                };
         };
 
         sound {
@@ -397,7 +419,9 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&codec>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index dd38f1f03834..7f8c28d1121f 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Ventana evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -310,7 +311,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <187 0x04>;
+                        interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -325,7 +326,7 @@
                         compatible = "isil,isl29018";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <202 0x04>; /*gpio PZ2 */
+                        interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -371,7 +372,7 @@
                 pmic: tps6586x@34 {
                         compatible = "ti,tps6586x";
                         reg = <0x34>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         ti,system-power-controller;
 
@@ -505,31 +506,42 @@
                 status = "okay";
         };
 
+        usb-phy@c5000000 {
+                status = "okay";
+        };
+
         usb@c5004000 {
                 status = "okay";
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
+        };
+
+        usb-phy@c5004000 {
+                status = "okay";
+                nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
+                        GPIO_ACTIVE_LOW>;
         };
 
         usb@c5008000 {
                 status = "okay";
         };
 
-        usb-phy@c5004400 {
-                nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
+        usb-phy@c5008000 {
+                status = "okay";
         };
 
         sdhci@c8000000 {
                 status = "okay";
-                power-gpios = <&gpio 86 0>; /* gpio PK6 */
+                power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
-                power-gpios = <&gpio 70 0>; /* gpio PI6 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -557,7 +569,7 @@
 
                 power {
                         label = "Power";
-                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                         linux,code = <116>; /* KEY_POWER */
                         gpio-key,wakeup;
                 };
@@ -583,7 +595,7 @@
                         regulator-name = "vdd_1v5";
                         regulator-min-microvolt = <1500000>;
                         regulator-max-microvolt = <1500000>;
-                        gpio = <&pmic 0 0>;
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 regulator@2 {
@@ -592,7 +604,7 @@
                         regulator-name = "vdd_1v2";
                         regulator-min-microvolt = <1200000>;
                         regulator-max-microvolt = <1200000>;
-                        gpio = <&pmic 1 0>;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -602,7 +614,7 @@
                         regulator-name = "vdd_pnl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 22 0>; /* gpio PC6 */
+                        gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
 
@@ -612,7 +624,7 @@
                         regulator-name = "vdd_bl";
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
-                        gpio = <&gpio 176 0>; /* gpio PW0 */
+                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                         enable-active-high;
                 };
         };
@@ -635,12 +647,16 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
-                nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
-                nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+                nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
+                        GPIO_ACTIVE_HIGH>;
+                nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d2567f83aaff..ea078ab8edeb 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra20.dtsi"
+#include "tegra20.dtsi"
 
 / {
         model = "NVIDIA Tegra20 Whistler evaluation board";
@@ -18,7 +18,8 @@
                         pll-supply = <&hdmi_pll_reg>;
 
                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
-                        nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
+                        nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
+                                GPIO_ACTIVE_HIGH>;
                 };
         };
 
@@ -281,7 +282,7 @@
                 max8907@3c {
                         compatible = "maxim,max8907";
                         reg = <0x3c>;
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 
                         maxim,system-power-controller;
 
@@ -508,18 +509,28 @@
 
         usb@c5000000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+                nvidia,vbus-gpio = <&tca6416 0 GPIO_ACTIVE_HIGH>;
+        };
+
+        usb-phy@c5000000 {
+                status = "okay";
+                vbus-supply = <&vbus1_reg>;
         };
 
         usb@c5008000 {
                 status = "okay";
-                nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+                nvidia,vbus-gpio = <&tca6416 1 GPIO_ACTIVE_HIGH>;
+        };
+
+        usb-phy@c5008000 {
+                status = "okay";
+                vbus-supply = <&vbus3_reg>;
         };
 
         sdhci@c8000400 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
                 bus-width = <8>;
         };
 
@@ -568,6 +579,24 @@
                         regulator-max-microvolt = <5000000>;
                         regulator-always-on;
                 };
+
+                vbus1_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vbus1";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+                };
+
+                vbus3_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vbus3";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+                };
         };
 
         sound {
@@ -584,7 +613,9 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&codec>;
 
-                clocks = <&tegra_car 112>, <&tegra_car 113>, <&tegra_car 94>;
+                clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
+                         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA20_CLK_CDEV1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 56a91106041b..9653fd8288d2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra20-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra20";
@@ -15,9 +19,9 @@
         host1x {
                 compatible = "nvidia,tegra20-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-                clocks = <&tegra_car 28>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -27,49 +31,50 @@
                 mpe {
                         compatible = "nvidia,tegra20-mpe";
                         reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                        clocks = <&tegra_car 60>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_MPE>;
                 };
 
                 vi {
                         compatible = "nvidia,tegra20-vi";
                         reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                        clocks = <&tegra_car 100>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_VI>;
                 };
 
                 epp {
                         compatible = "nvidia,tegra20-epp";
                         reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                        clocks = <&tegra_car 19>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_EPP>;
                 };
 
                 isp {
                         compatible = "nvidia,tegra20-isp";
                         reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                        clocks = <&tegra_car 23>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_ISP>;
                 };
 
                 gr2d {
                         compatible = "nvidia,tegra20-gr2d";
                         reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                        clocks = <&tegra_car 21>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
                 };
 
                 gr3d {
                         compatible = "nvidia,tegra20-gr3d";
                         reg = <0x54180000 0x00040000>;
-                        clocks = <&tegra_car 24>;
+                        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
                 };
 
                 dc@54200000 {
                         compatible = "nvidia,tegra20-dc";
                         reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-                        clocks = <&tegra_car 27>, <&tegra_car 121>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP1>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                         clock-names = "disp1", "parent";
 
                         rgb {
@@ -80,8 +85,9 @@
                 dc@54240000 {
                         compatible = "nvidia,tegra20-dc";
                         reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-                        clocks = <&tegra_car 26>, <&tegra_car 121>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_DISP2>,
+                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                         clock-names = "disp2", "parent";
 
                         rgb {
@@ -92,8 +98,9 @@
                 hdmi {
                         compatible = "nvidia,tegra20-hdmi";
                         reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        clocks = <&tegra_car 51>, <&tegra_car 117>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_HDMI>,
+                                 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
                         clock-names = "hdmi", "parent";
                         status = "disabled";
                 };
@@ -101,15 +108,15 @@
                 tvo {
                         compatible = "nvidia,tegra20-tvo";
                         reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        clocks = <&tegra_car 102>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA20_CLK_TVO>;
                         status = "disabled";
                 };
 
                 dsi {
                         compatible = "nvidia,tegra20-dsi";
                         reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA20_CLK_DSI>;
                         status = "disabled";
                 };
         };
@@ -117,8 +124,9 @@
         timer@50004600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x50040600 0x20>;
-                interrupts = <1 13 0x304>;
-                clocks = <&tegra_car 132>;
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA20_CLK_TWD>;
         };
 
         intc: interrupt-controller {
@@ -141,11 +149,11 @@
         timer@60005000 {
                 compatible = "nvidia,tegra20-timer";
                 reg = <0x60005000 0x60>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -157,23 +165,23 @@
         apbdma: dma {
                 compatible = "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1200>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
         };
 
         ahb {
@@ -184,13 +192,13 @@
         gpio: gpio {
                 compatible = "nvidia,tegra20-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -213,27 +221,27 @@
         tegra_ac97: ac97 {
                 compatible = "nvidia,tegra20-ac97";
                 reg = <0x70002000 0x200>;
-                interrupts = <0 81 0x04>;
+                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 12>;
-                clocks = <&tegra_car 3>;
+                clocks = <&tegra_car TEGRA20_CLK_AC97>;
                 status = "disabled";
         };
 
         tegra_i2s1: i2s@70002800 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002800 0x200>;
-                interrupts = <0 13 0x04>;
+                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 2>;
-                clocks = <&tegra_car 11>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S1>;
                 status = "disabled";
         };
 
         tegra_i2s2: i2s@70002a00 {
                 compatible = "nvidia,tegra20-i2s";
                 reg = <0x70002a00 0x200>;
-                interrupts = <0 3 0x04>;
+                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 18>;
+                clocks = <&tegra_car TEGRA20_CLK_I2S2>;
                 status = "disabled";
         };
 
@@ -248,9 +256,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTA>;
                 status = "disabled";
         };
 
@@ -258,9 +266,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 96>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTB>;
                 status = "disabled";
         };
 
@@ -268,9 +276,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTC>;
                 status = "disabled";
         };
 
@@ -278,9 +286,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTD>;
                 status = "disabled";
         };
 
@@ -288,9 +296,9 @@
                 compatible = "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA20_CLK_UARTE>;
                 status = "disabled";
         };
 
@@ -298,24 +306,25 @@
                 compatible = "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA20_CLK_PWM>;
                 status = "disabled";
         };
 
         rtc {
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_RTC>;
         };
 
         i2c@7000c000 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C1>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -323,21 +332,22 @@
         spi@7000c380 {
                 compatible = "nvidia,tegra20-sflash";
                 reg = <0x7000c380 0x80>;
-                interrupts = <0 39 0x04>;
+                interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 11>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 43>;
+                clocks = <&tegra_car TEGRA20_CLK_SPI>;
                 status = "disabled";
         };
 
         i2c@7000c400 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C2>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -345,10 +355,11 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra20-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -356,10 +367,11 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra20-i2c-dvc";
                 reg = <0x7000d000 0x200>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 124>;
+                clocks = <&tegra_car TEGRA20_CLK_DVC>,
+                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -367,59 +379,59 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC1>;
                 status = "disabled";
         };
 
         spi@7000d600 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC2>;
                 status = "disabled";
         };
 
         spi@7000d800 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC3>;
                 status = "disabled";
         };
 
         spi@7000da00 {
                 compatible = "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA20_CLK_SBC4>;
                 status = "disabled";
         };
 
         kbc {
                 compatible = "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra20-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 110>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -427,7 +439,7 @@
                 compatible = "nvidia,tegra20-mc";
                 reg = <0x7000f000 0x024
                        0x7000f03c 0x3c4>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         iommu {
@@ -446,89 +458,114 @@
         usb@c5000000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5000000 0x4000>;
-                interrupts = <0 20 0x04>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
-                clocks = <&tegra_car 22>;
+                clocks = <&tegra_car TEGRA20_CLK_USBD>;
                 nvidia,needs-double-reset;
                 nvidia,phy = <&phy1>;
                 status = "disabled";
         };
 
-        phy1: usb-phy@c5000400 {
+        phy1: usb-phy@c5000000 {
                 compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5000400 0x3c00>;
+                reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
                 phy_type = "utmi";
+                clocks = <&tegra_car TEGRA20_CLK_USBD>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
+                clock-names = "reg", "pll_u", "timer", "utmi-pads";
                 nvidia,has-legacy-mode;
-                clocks = <&tegra_car 22>, <&tegra_car 127>;
-                clock-names = "phy", "pll_u";
+                hssync_start_delay = <9>;
+                idle_wait_delay = <17>;
+                elastic_limit = <16>;
+                term_range_adj = <6>;
+                xcvr_setup = <9>;
+                xcvr_lsfslew = <1>;
+                xcvr_lsrslew = <1>;
+                status = "disabled";
         };
 
         usb@c5004000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5004000 0x4000>;
-                interrupts = <0 21 0x04>;
+                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "ulpi";
-                clocks = <&tegra_car 58>;
+                clocks = <&tegra_car TEGRA20_CLK_USB2>;
                 nvidia,phy = <&phy2>;
                 status = "disabled";
         };
 
-        phy2: usb-phy@c5004400 {
+        phy2: usb-phy@c5004000 {
                 compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5004400 0x3c00>;
+                reg = <0xc5004000 0x4000>;
                 phy_type = "ulpi";
-                clocks = <&tegra_car 93>, <&tegra_car 127>;
-                clock-names = "phy", "pll_u";
+                clocks = <&tegra_car TEGRA20_CLK_USB2>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CDEV2>;
+                clock-names = "reg", "pll_u", "ulpi-link";
+                status = "disabled";
         };
 
         usb@c5008000 {
                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
                 reg = <0xc5008000 0x4000>;
-                interrupts = <0 97 0x04>;
+                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                 phy_type = "utmi";
-                clocks = <&tegra_car 59>;
+                clocks = <&tegra_car TEGRA20_CLK_USB3>;
                 nvidia,phy = <&phy3>;
                 status = "disabled";
         };
 
-        phy3: usb-phy@c5008400 {
+        phy3: usb-phy@c5008000 {
                 compatible = "nvidia,tegra20-usb-phy";
-                reg = <0xc5008400 0x3c00>;
+                reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
                 phy_type = "utmi";
-                clocks = <&tegra_car 22>, <&tegra_car 127>;
-                clock-names = "phy", "pll_u";
+                clocks = <&tegra_car TEGRA20_CLK_USB3>,
+                         <&tegra_car TEGRA20_CLK_PLL_U>,
+                         <&tegra_car TEGRA20_CLK_CLK_M>,
+                         <&tegra_car TEGRA20_CLK_USBD>;
+                clock-names = "reg", "pll_u", "timer", "utmi-pads";
+                hssync_start_delay = <9>;
+                idle_wait_delay = <17>;
+                elastic_limit = <16>;
+                term_range_adj = <6>;
+                xcvr_setup = <9>;
+                xcvr_lsfslew = <2>;
+                xcvr_lsrslew = <2>;
+                status = "disabled";
         };
 
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
                 status = "disabled";
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
                 status = "disabled";
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
                 status = "disabled";
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
                 status = "disabled";
         };
 
@@ -551,7 +588,7 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 56 0x04
-                              0 57 0x04>;
+                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
         };
 };
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b732f7c13a66..87c5f7b7c271 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1,13 +1,13 @@
 /dts-v1/;
 
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 / {
         model = "NVIDIA Tegra30 Beaver evaluation board";
         compatible = "nvidia,beaver", "nvidia,tegra30";
 
         memory {
-                reg = <0x80000000 0x80000000>;
+                reg = <0x80000000 0x7ff00000>;
         };
 
         pinmux {
@@ -116,6 +116,15 @@
                 status = "okay";
                 clock-frequency = <100000>;
 
+                rt5640: rt5640 {
+                        compatible = "realtek,rt5640";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(X, 3) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
+                };
+
                 tps62361 {
                         compatible = "ti,tps62361";
                         reg = <0x60>;
@@ -133,7 +142,7 @@
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         #interrupt-cells = <2>;
                         interrupt-controller;
 
@@ -264,9 +273,9 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -312,7 +321,7 @@
                         regulator-boot-on;
                         regulator-always-on;
                         enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 ddr_reg: regulator@2 {
@@ -324,7 +333,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -337,7 +346,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -348,7 +357,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
@@ -360,7 +369,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
@@ -374,7 +383,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vdd_5v_in_reg>;
                 };
 
@@ -387,8 +396,41 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
         };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                gpled1 {
+                        label = "LED1"; /* CR5A1 (blue) */
+                        gpios = <&gpio TEGRA_GPIO(L, 1) GPIO_ACTIVE_HIGH>;
+                };
+                gpled2 {
+                        label = "LED2"; /* CR4A2 (green) */
+                        gpios = <&gpio TEGRA_GPIO(L, 0) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-beaver",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Beaver";
+
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5640>;
+
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a02.dts b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
index e392bd2dab9b..1082c5ed90d1 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a02.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a02.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A02 version of board */
 
@@ -22,7 +22,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                 };
 
                 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 68 0>; /* GPIO PI4 */
+                        gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -56,7 +56,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 63 0>; /* GPIO PH7 */
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -68,7 +68,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&pmic 2 0>;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl_reg: regulator@105 {
@@ -80,13 +80,13 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 83 0>; /* GPIO PK3 */
+                        gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_HIGH>;
                 };
         };
 
         sdhci@78000400 {
                 status = "okay";
-                power-gpios = <&gpio 28 0>; /* gpio PD4 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
diff --git a/arch/arm/boot/dts/tegra30-cardhu-a04.dts b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
index d0db6c7e774f..bf012bddaafb 100644
--- a/arch/arm/boot/dts/tegra30-cardhu-a04.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu-a04.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-/include/ "tegra30-cardhu.dtsi"
+#include "tegra30-cardhu.dtsi"
 
 /* This dts file support the cardhu A04 and later versions of board */
 
@@ -22,7 +22,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 7 0>;
+                        gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
                 };
 
                 sys_3v3_reg: regulator@101 {
@@ -34,7 +34,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&pmic 6 0>;
+                        gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
                 };
 
                 usb1_vbus_reg: regulator@102 {
@@ -44,7 +44,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 238 0>; /* GPIO PDD6 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -56,7 +56,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 236 0>; /* GPIO PDD4 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -68,7 +68,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&pmic 8 0>;
+                        gpio = <&pmic 8 GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl_reg: regulator@105 {
@@ -80,7 +80,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 234 0>; /* GPIO PDD2 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 2) GPIO_ACTIVE_HIGH>;
                 };
 
                 vdd_bl2_reg: regulator@106 {
@@ -92,13 +92,13 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 232 0>; /* GPIO PDD0 */
+                        gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
                 };
         };
 
         sdhci@78000400 {
                 status = "okay";
-                power-gpios = <&gpio 27 0>; /* gpio PD3 */
+                power-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
                 keep-power-in-suspend;
         };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 01b4c26fad96..f65b53d32416 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -1,4 +1,4 @@
-/include/ "tegra30.dtsi"
+#include "tegra30.dtsi"
 
 /**
  * This file contains common DT entry for all fab version of Cardhu.
@@ -146,7 +146,7 @@
                         compatible = "isil,isl29028";
                         reg = <0x44>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <88 0x04>; /*gpio PL0 */
+                        interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
                 };
         };
 
@@ -163,7 +163,7 @@
                         compatible = "wlf,wm8903";
                         reg = <0x1a>;
                         interrupt-parent = <&gpio>;
-                        interrupts = <179 0x04>; /* gpio PW3 */
+                        interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
 
                         gpio-controller;
                         #gpio-cells = <2>;
@@ -190,7 +190,7 @@
                         compatible = "ti,tps65911";
                         reg = <0x2d>;
 
-                        interrupts = <0 86 0x4>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                         #interrupt-cells = <2>;
                         interrupt-controller;
 
@@ -318,9 +318,9 @@
 
         sdhci@78000000 {
                 status = "okay";
-                cd-gpios = <&gpio 69 1>; /* gpio PI5 */
-                wp-gpios = <&gpio 155 0>; /* gpio PT3 */
-                power-gpios = <&gpio 31 0>; /* gpio PD7 */
+                cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
+                power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
                 bus-width = <4>;
         };
 
@@ -364,7 +364,7 @@
                         regulator-min-microvolt = <1800000>;
                         regulator-max-microvolt = <1800000>;
                         enable-active-high;
-                        gpio = <&gpio 220 0>; /* gpio PBB4 */
+                        gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&vio_reg>;
                 };
 
@@ -377,7 +377,7 @@
                         regulator-boot-on;
                         regulator-always-on;
                         enable-active-high;
-                        gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
+                        gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
                 };
 
                 emmc_3v3_reg: regulator@3 {
@@ -389,7 +389,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 25 0>; /* gpio PD1 */
+                        gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -400,7 +400,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 30 0>; /* gpio PD6 */
+                        gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
                 };
 
                 pex_hvdd_3v3_reg: regulator@5 {
@@ -410,7 +410,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 95 0>; /* gpio PL7 */
+                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -421,7 +421,7 @@
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
                         enable-active-high;
-                        gpio = <&gpio 142 0>; /* gpio PR6 */
+                        gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -432,7 +432,7 @@
                         regulator-min-microvolt = <2800000>;
                         regulator-max-microvolt = <2800000>;
                         enable-active-high;
-                        gpio = <&gpio 143 0>; /* gpio PR7 */
+                        gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -443,7 +443,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 144 0>; /* gpio PS0 */
+                        gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -456,7 +456,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 24 0>; /* gpio PD0 */
+                        gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -467,7 +467,7 @@
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
                         enable-active-high;
-                        gpio = <&gpio 94 0>; /* gpio PL6 */
+                        gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -480,7 +480,7 @@
                         regulator-always-on;
                         regulator-boot-on;
                         enable-active-high;
-                        gpio = <&gpio 92 0>; /* gpio PL4 */
+                        gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
                         vin-supply = <&sys_3v3_reg>;
                 };
 
@@ -491,7 +491,7 @@
                         regulator-min-microvolt = <5000000>;
                         regulator-max-microvolt = <5000000>;
                         enable-active-high;
-                        gpio = <&gpio 152 0>; /* GPIO PT0 */
+                        gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
                         gpio-open-drain;
                         vin-supply = <&vdd_5v0_reg>;
                 };
@@ -515,10 +515,13 @@
                 nvidia,i2s-controller = <&tegra_i2s1>;
                 nvidia,audio-codec = <&wm8903>;
 
-                nvidia,spkr-en-gpios = <&wm8903 2 0>;
-                nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+                nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
+                        GPIO_ACTIVE_HIGH>;
 
-                clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
+                clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
+                         <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA30_CLK_EXTERN1>;
                 clock-names = "pll_a", "pll_a_out0", "mclk";
         };
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 15ded605142a..d8783f0fae63 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -1,4 +1,8 @@
-/include/ "skeleton.dtsi"
+#include <dt-bindings/clock/tegra30-car.h>
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
 
 / {
         compatible = "nvidia,tegra30";
@@ -15,9 +19,9 @@
         host1x {
                 compatible = "nvidia,tegra30-host1x", "simple-bus";
                 reg = <0x50000000 0x00024000>;
-                interrupts = <0 65 0x04   /* mpcore syncpt */
-                              0 67 0x04>; /* mpcore general */
-                clocks = <&tegra_car 28>;
+                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
+                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
+                clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -27,36 +31,36 @@
                 mpe {
                         compatible = "nvidia,tegra30-mpe";
                         reg = <0x54040000 0x00040000>;
-                        interrupts = <0 68 0x04>;
-                        clocks = <&tegra_car 60>;
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_MPE>;
                 };
 
                 vi {
                         compatible = "nvidia,tegra30-vi";
                         reg = <0x54080000 0x00040000>;
-                        interrupts = <0 69 0x04>;
-                        clocks = <&tegra_car 164>;
+                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_VI>;
                 };
 
                 epp {
                         compatible = "nvidia,tegra30-epp";
                         reg = <0x540c0000 0x00040000>;
-                        interrupts = <0 70 0x04>;
-                        clocks = <&tegra_car 19>;
+                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_EPP>;
                 };
 
                 isp {
                         compatible = "nvidia,tegra30-isp";
                         reg = <0x54100000 0x00040000>;
-                        interrupts = <0 71 0x04>;
-                        clocks = <&tegra_car 23>;
+                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_ISP>;
                 };
 
                 gr2d {
                         compatible = "nvidia,tegra30-gr2d";
                         reg = <0x54140000 0x00040000>;
-                        interrupts = <0 72 0x04>;
-                        clocks = <&tegra_car 21>;
+                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                 };
 
                 gr3d {
@@ -69,8 +73,9 @@
                 dc@54200000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54200000 0x00040000>;
-                        interrupts = <0 73 0x04>;
-                        clocks = <&tegra_car 27>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp1", "parent";
 
                         rgb {
@@ -81,8 +86,9 @@
                 dc@54240000 {
                         compatible = "nvidia,tegra30-dc";
                         reg = <0x54240000 0x00040000>;
-                        interrupts = <0 74 0x04>;
-                        clocks = <&tegra_car 26>, <&tegra_car 179>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_DISP2>,
+                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                         clock-names = "disp2", "parent";
 
                         rgb {
@@ -93,8 +99,9 @@
                 hdmi {
                         compatible = "nvidia,tegra30-hdmi";
                         reg = <0x54280000 0x00040000>;
-                        interrupts = <0 75 0x04>;
-                        clocks = <&tegra_car 51>, <&tegra_car 189>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_HDMI>,
+                                 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                         clock-names = "hdmi", "parent";
                         status = "disabled";
                 };
@@ -102,15 +109,15 @@
                 tvo {
                         compatible = "nvidia,tegra30-tvo";
                         reg = <0x542c0000 0x00040000>;
-                        interrupts = <0 76 0x04>;
-                        clocks = <&tegra_car 169>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA30_CLK_TVO>;
                         status = "disabled";
                 };
 
                 dsi {
                         compatible = "nvidia,tegra30-dsi";
                         reg = <0x54300000 0x00040000>;
-                        clocks = <&tegra_car 48>;
+                        clocks = <&tegra_car TEGRA30_CLK_DSIA>;
                         status = "disabled";
                 };
         };
@@ -118,8 +125,9 @@
         timer@50004600 {
                 compatible = "arm,cortex-a9-twd-timer";
                 reg = <0x50040600 0x20>;
-                interrupts = <1 13 0xf04>;
-                clocks = <&tegra_car 214>;
+                interrupts = <GIC_PPI 13
+                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+                clocks = <&tegra_car TEGRA30_CLK_TWD>;
         };
 
         intc: interrupt-controller {
@@ -142,13 +150,13 @@
         timer@60005000 {
                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                 reg = <0x60005000 0x400>;
-                interrupts = <0 0 0x04
-                              0 1 0x04
-                              0 41 0x04
-                              0 42 0x04
-                              0 121 0x04
-                              0 122 0x04>;
-                clocks = <&tegra_car 5>;
+                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_TIMER>;
         };
 
         tegra_car: clock {
@@ -160,39 +168,39 @@
         apbdma: dma {
                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
                 reg = <0x6000a000 0x1400>;
-                interrupts = <0 104 0x04
-                              0 105 0x04
-                              0 106 0x04
-                              0 107 0x04
-                              0 108 0x04
-                              0 109 0x04
-                              0 110 0x04
-                              0 111 0x04
-                              0 112 0x04
-                              0 113 0x04
-                              0 114 0x04
-                              0 115 0x04
-                              0 116 0x04
-                              0 117 0x04
-                              0 118 0x04
-                              0 119 0x04
-                              0 128 0x04
-                              0 129 0x04
-                              0 130 0x04
-                              0 131 0x04
-                              0 132 0x04
-                              0 133 0x04
-                              0 134 0x04
-                              0 135 0x04
-                              0 136 0x04
-                              0 137 0x04
-                              0 138 0x04
-                              0 139 0x04
-                              0 140 0x04
-                              0 141 0x04
-                              0 142 0x04
-                              0 143 0x04>;
-                clocks = <&tegra_car 34>;
+                interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
         };
 
         ahb: ahb {
@@ -203,14 +211,14 @@
         gpio: gpio {
                 compatible = "nvidia,tegra30-gpio";
                 reg = <0x6000d000 0x1000>;
-                interrupts = <0 32 0x04
-                              0 33 0x04
-                              0 34 0x04
-                              0 35 0x04
-                              0 55 0x04
-                              0 87 0x04
-                              0 89 0x04
-                              0 125 0x04>;
+                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
                 #gpio-cells = <2>;
                 gpio-controller;
                 #interrupt-cells = <2>;
@@ -235,9 +243,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 36 0x04>;
+                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 8>;
-                clocks = <&tegra_car 6>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTA>;
                 status = "disabled";
         };
 
@@ -245,9 +253,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
-                interrupts = <0 37 0x04>;
+                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 9>;
-                clocks = <&tegra_car 160>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTB>;
                 status = "disabled";
         };
 
@@ -255,9 +263,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 46 0x04>;
+                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 10>;
-                clocks = <&tegra_car 55>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTC>;
                 status = "disabled";
         };
 
@@ -265,9 +273,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 90 0x04>;
+                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 19>;
-                clocks = <&tegra_car 65>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTD>;
                 status = "disabled";
         };
 
@@ -275,9 +283,9 @@
                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
-                interrupts = <0 91 0x04>;
+                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 20>;
-                clocks = <&tegra_car 66>;
+                clocks = <&tegra_car TEGRA30_CLK_UARTE>;
                 status = "disabled";
         };
 
@@ -285,24 +293,25 @@
                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
                 reg = <0x7000a000 0x100>;
                 #pwm-cells = <2>;
-                clocks = <&tegra_car 17>;
+                clocks = <&tegra_car TEGRA30_CLK_PWM>;
                 status = "disabled";
         };
 
         rtc {
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
-                interrupts = <0 2 0x04>;
-                clocks = <&tegra_car 4>;
+                interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_RTC>;
         };
 
         i2c@7000c000 {
                 compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c000 0x100>;
-                interrupts = <0 38 0x04>;
+                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 12>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C1>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -310,10 +319,11 @@
         i2c@7000c400 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c400 0x100>;
-                interrupts = <0 84 0x04>;
+                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 54>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C2>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -321,10 +331,11 @@
         i2c@7000c500 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c500 0x100>;
-                interrupts = <0 92 0x04>;
+                interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 67>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C3>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -332,10 +343,11 @@
         i2c@7000c700 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000c700 0x100>;
-                interrupts = <0 120 0x04>;
+                interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 103>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C4>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -343,10 +355,11 @@
         i2c@7000d000 {
                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
                 reg = <0x7000d000 0x100>;
-                interrupts = <0 53 0x04>;
+                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 47>, <&tegra_car 182>;
+                clocks = <&tegra_car TEGRA30_CLK_I2C5>,
+                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                 clock-names = "div-clk", "fast-clk";
                 status = "disabled";
         };
@@ -354,81 +367,81 @@
         spi@7000d400 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d400 0x200>;
-                interrupts = <0 59 0x04>;
+                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 15>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 41>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC1>;
                 status = "disabled";
         };
 
         spi@7000d600 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d600 0x200>;
-                interrupts = <0 82 0x04>;
+                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 16>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 44>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC2>;
                 status = "disabled";
         };
 
         spi@7000d800 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000d800 0x200>;
-                interrupts = <0 83 0x04>;
+                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 17>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 46>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC3>;
                 status = "disabled";
         };
 
         spi@7000da00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000da00 0x200>;
-                interrupts = <0 93 0x04>;
+                interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 18>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 68>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC4>;
                 status = "disabled";
         };
 
         spi@7000dc00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000dc00 0x200>;
-                interrupts = <0 94 0x04>;
+                interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 27>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 104>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC5>;
                 status = "disabled";
         };
 
         spi@7000de00 {
                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
                 reg = <0x7000de00 0x200>;
-                interrupts = <0 79 0x04>;
+                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 28>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                clocks = <&tegra_car 105>;
+                clocks = <&tegra_car TEGRA30_CLK_SBC6>;
                 status = "disabled";
         };
 
         kbc {
                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
                 reg = <0x7000e200 0x100>;
-                interrupts = <0 85 0x04>;
-                clocks = <&tegra_car 36>;
+                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_KBC>;
                 status = "disabled";
         };
 
         pmc {
                 compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
-                clocks = <&tegra_car 218>, <&clk32k_in>;
+                clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
@@ -438,7 +451,7 @@
                        0x7000f03c 0x1b4
                        0x7000f200 0x028
                        0x7000f284 0x17c>;
-                interrupts = <0 77 0x04>;
+                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
         };
 
         iommu {
@@ -455,12 +468,19 @@
                 compatible = "nvidia,tegra30-ahub";
                 reg = <0x70080000 0x200
                        0x70080200 0x100>;
-                interrupts = <0 103 0x04>;
+                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
-                         <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
-                         <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
-                         <&tegra_car 110>, <&tegra_car 162>;
+                clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
+                         <&tegra_car TEGRA30_CLK_APBIF>,
+                         <&tegra_car TEGRA30_CLK_I2S0>,
+                         <&tegra_car TEGRA30_CLK_I2S1>,
+                         <&tegra_car TEGRA30_CLK_I2S2>,
+                         <&tegra_car TEGRA30_CLK_I2S3>,
+                         <&tegra_car TEGRA30_CLK_I2S4>,
+                         <&tegra_car TEGRA30_CLK_DAM0>,
+                         <&tegra_car TEGRA30_CLK_DAM1>,
+                         <&tegra_car TEGRA30_CLK_DAM2>,
+                         <&tegra_car TEGRA30_CLK_SPDIF_IN>;
                 clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
                               "spdif_in";
@@ -472,7 +492,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
-                        clocks = <&tegra_car 30>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S0>;
                         status = "disabled";
                 };
 
@@ -480,7 +500,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
-                        clocks = <&tegra_car 11>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S1>;
                         status = "disabled";
                 };
 
@@ -488,7 +508,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
-                        clocks = <&tegra_car 18>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S2>;
                         status = "disabled";
                 };
 
@@ -496,7 +516,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
-                        clocks = <&tegra_car 101>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S3>;
                         status = "disabled";
                 };
 
@@ -504,7 +524,7 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
-                        clocks = <&tegra_car 102>;
+                        clocks = <&tegra_car TEGRA30_CLK_I2S4>;
                         status = "disabled";
                 };
         };
@@ -512,32 +532,32 @@
         sdhci@78000000 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000000 0x200>;
-                interrupts = <0 14 0x04>;
-                clocks = <&tegra_car 14>;
+                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
                 status = "disabled";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000200 0x200>;
-                interrupts = <0 15 0x04>;
-                clocks = <&tegra_car 9>;
+                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
                 status = "disabled";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000400 0x200>;
-                interrupts = <0 19 0x04>;
-                clocks = <&tegra_car 69>;
+                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
                 status = "disabled";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000600 0x200>;
-                interrupts = <0 31 0x04>;
-                clocks = <&tegra_car 15>;
+                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
                 status = "disabled";
         };
 
@@ -572,9 +592,9 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 144 0x04
-                              0 145 0x04
-                              0 146 0x04
-                              0 147 0x04>;
+                interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
         };
 };
diff --git a/arch/arm/boot/dts/tny_a9260.dts b/arch/arm/boot/dts/tny_a9260.dts
index 367a16dcd5ef..dabe232216b4 100644
--- a/arch/arm/boot/dts/tny_a9260.dts
+++ b/arch/arm/boot/dts/tny_a9260.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "at91sam9260.dtsi"
+#include "tny_a9260_common.dtsi"
 
 / {
         model = "Calao TNY A9260";
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index dee9c571306b..0751a6a979a8 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
         model = "Calao TNY A9263";
@@ -38,7 +38,7 @@
                         };
 
                         usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioB 11 0>;
+                                atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
                 };
diff --git a/arch/arm/boot/dts/tny_a9g20.dts b/arch/arm/boot/dts/tny_a9g20.dts
index e1ab64c72dba..8456d70bb42b 100644
--- a/arch/arm/boot/dts/tny_a9g20.dts
+++ b/arch/arm/boot/dts/tny_a9g20.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
-/include/ "tny_a9260_common.dtsi"
+#include "at91sam9g20.dtsi"
+#include "tny_a9260_common.dtsi"
 
 / {
         model = "Calao TNY A9G20";
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi
new file mode 100644
index 000000000000..c353ef0a6ac7
--- /dev/null
+++ b/arch/arm/boot/dts/twl4030_omap3.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2013 Linaro, Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&twl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&twl4030_pins>;
+};
+
+&omap3_pmx_core {
+        /*
+         * On most OMAP3 platforms, the twl4030 IRQ line is connected
+         * to the SYS_NIRQ line on OMAP.  Therefore, configure the
+         * defaults for the SYS_NIRQ pin here.
+         */
+        twl4030_pins: pinmux_twl4030_pins {
+                pinctrl-single,pins = <
+                        0x1b0 (PIN_INPUT_PULLUP | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* sys_nirq.sys_nirq */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9260.dts b/arch/arm/boot/dts/usb_a9260.dts
index 296216058c11..de0c24f5210a 100644
--- a/arch/arm/boot/dts/usb_a9260.dts
+++ b/arch/arm/boot/dts/usb_a9260.dts
@@ -6,8 +6,8 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9260.dtsi"
-/include/ "usb_a9260_common.dtsi"
+#include "at91sam9260.dtsi"
+#include "usb_a9260_common.dtsi"
 
 / {
         model = "Calao USB A9260";
@@ -20,4 +20,13 @@
         memory {
                 reg = <0x20000000 0x4000000>;
         };
+
+        ahb {
+                apb {
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index e70d229baef5..285977682cf3 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -30,7 +30,7 @@
                         };
 
                         usb1: gadget@fffa4000 {
-                                atmel,vbus-gpio = <&pioC 5 0>;
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
                 };
@@ -93,7 +93,7 @@
 
                 user_led {
                         label = "user_led";
-                        gpios = <&pioB 21 1>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
                         linux,default-trigger = "heartbeat";
                 };
         };
@@ -105,7 +105,7 @@
 
                 user_pb {
                         label = "user_pb";
-                        gpios = <&pioB 10 1>;
+                        gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
                         linux,code = <28>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 6fe05ccb6203..290e60383baf 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -6,7 +6,7 @@
  * Licensed under GPLv2 only
  */
 /dts-v1/;
-/include/ "at91sam9263.dtsi"
+#include "at91sam9263.dtsi"
 
 / {
         model = "Calao USB A9263";
@@ -43,10 +43,24 @@
                         };
 
                         usb1: gadget@fff78000 {
-                                atmel,vbus-gpio = <&pioB 11 0>;
+                                atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>;
                                 status = "okay";
                         };
 
+                        spi0: spi@fffa4000 {
+                                cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        reg = <0>;
+                                        spi-max-frequency = <15000000>;
+                                };
+                        };
+
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
                 };
 
                 nand0: nand@40000000 {
@@ -107,7 +121,7 @@
 
                 user_led {
                         label = "user_led";
-                        gpios = <&pioB 21 0>;
+                        gpios = <&pioB 21 GPIO_ACTIVE_HIGH>;
                         linux,default-trigger = "heartbeat";
                 };
         };
@@ -119,7 +133,7 @@
 
                 user_pb {
                         label = "user_pb";
-                        gpios = <&pioB 10 1>;
+                        gpios = <&pioB 10 GPIO_ACTIVE_LOW>;
                         linux,code = <28>;
                         gpio-key,wakeup;
                 };
diff --git a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
index ad3eca17c436..5b0ffc1a0b24 100644
--- a/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
+++ b/arch/arm/boot/dts/usb_a9g20-dab-mmx.dtsi
@@ -28,39 +28,39 @@
 
                 user_led1 {
                         label = "user_led1";
-                        gpios = <&pioB 20 1>;
+                        gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
                 };
 
 /*
 * led already used by mother board but active as high
 *               user_led2 {
 *                       label = "user_led2";
-*                       gpios = <&pioB 21 1>;
+*                       gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
 *               };
 */
                 user_led3 {
                         label = "user_led3";
-                        gpios = <&pioB 22 1>;
+                        gpios = <&pioB 22 GPIO_ACTIVE_LOW>;
                 };
 
                 user_led4 {
                         label = "user_led4";
-                        gpios = <&pioB 23 1>;
+                        gpios = <&pioB 23 GPIO_ACTIVE_LOW>;
                 };
 
                 red {
                         label = "red";
-                        gpios = <&pioB 24 1>;
+                        gpios = <&pioB 24 GPIO_ACTIVE_LOW>;
                 };
 
                 orange {
                         label = "orange";
-                        gpios = <&pioB 30 1>;
+                        gpios = <&pioB 30 GPIO_ACTIVE_LOW>;
                 };
 
                 green {
                         label = "green";
-                        gpios = <&pioB 31 1>;
+                        gpios = <&pioB 31 GPIO_ACTIVE_LOW>;
                 };
         };
 
@@ -71,25 +71,25 @@
 
                 user_pb1 {
                         label = "user_pb1";
-                        gpios = <&pioB 25 1>;
+                        gpios = <&pioB 25 GPIO_ACTIVE_LOW>;
                         linux,code = <0x100>;
                 };
 
                 user_pb2 {
                         label = "user_pb2";
-                        gpios = <&pioB 13 1>;
+                        gpios = <&pioB 13 GPIO_ACTIVE_LOW>;
                         linux,code = <0x101>;
                 };
 
                 user_pb3 {
                         label = "user_pb3";
-                        gpios = <&pioA 26 1>;
+                        gpios = <&pioA 26 GPIO_ACTIVE_LOW>;
                         linux,code = <0x102>;
                 };
 
                 user_pb4 {
                         label = "user_pb4";
-                        gpios = <&pioC 9 1>;
+                        gpios = <&pioC 9 GPIO_ACTIVE_LOW>;
                         linux,code = <0x103>;
                 };
         };
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index 2dacb16ce4ae..ec77cf8f9695 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -6,25 +6,9 @@
  * Licensed under GPLv2 or later.
  */
 /dts-v1/;
-/include/ "at91sam9g20.dtsi"
-/include/ "usb_a9260_common.dtsi"
+#include "usb_a9g20_common.dtsi"
 
 / {
         model = "Calao USB A9G20";
         compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
-
-        chosen {
-                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
-        };
-
-        memory {
-                reg = <0x20000000 0x4000000>;
-        };
-
-        i2c@0 {
-                rv3029c2@56 {
-                        compatible = "rv3029c2";
-                        reg = <0x56>;
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi
new file mode 100644
index 000000000000..0b3b36182fe5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -0,0 +1,27 @@
+/*
+ * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
+ *
+ *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "at91sam9g20.dtsi"
+#include "usb_a9260_common.dtsi"
+
+/ {
+        chosen {
+                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        i2c@0 {
+                rv3029c2@56 {
+                        compatible = "rv3029c2";
+                        reg = <0x56>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/usb_a9g20_lpw.dts b/arch/arm/boot/dts/usb_a9g20_lpw.dts
new file mode 100644
index 000000000000..f8cb1b9a01c5
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20_lpw.dts
@@ -0,0 +1,31 @@
+/*
+ * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board
+ *
+ *  Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "usb_a9g20_common.dtsi"
+
+/ {
+        model = "Calao USB A9G20 Low Power";
+        compatible = "calao,usb-a9g20-lpw", "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        spi1: spi@fffcc000 {
+                                cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                                mmc-slot@0 {
+                                        compatible = "mmc-spi-slot";
+                                        reg = <0>;
+                                        voltage-ranges = <3200 3400>;
+                                        spi-max-frequency = <25000000>;
+                                        interrupt-parent = <&pioC>;
+                                        interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf610-pinfunc.h b/arch/arm/boot/dts/vf610-pinfunc.h
new file mode 100644
index 000000000000..1ee681f7ce2f
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-pinfunc.h
@@ -0,0 +1,810 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DTS_VF610_PINFUNC_H
+#define __DTS_VF610_PINFUNC_H
+
+/*
+ * The pin function ID for VF610 is a tuple of:
+ * <mux_reg input_reg mux_mode input_val>
+ */
+
+#define ALT0    0x0
+#define ALT1    0x1
+#define ALT2    0x2
+#define ALT3    0x3
+#define ALT4    0x4
+#define ALT5    0x5
+#define ALT6    0x6
+#define ALT7    0x7
+
+
+#define VF610_PAD_PTA6__GPIO_0                  0x000 0x000 ALT0 0x0
+#define VF610_PAD_PTA6__RMII_CLKOUT             0x000 0x000 ALT1 0x0
+#define VF610_PAD_PTA6__RMII_CLKIN              0x000 0x2F0 ALT2 0x0
+#define VF610_PAD_PTA6__DCU1_TCON11             0x000 0x000 ALT4 0x0
+#define VF610_PAD_PTA6__DCU1_R2                 0x000 0x000 ALT7 0x0
+#define VF610_PAD_PTA8__GPIO_1                  0x004 0x000 ALT0 0x0
+#define VF610_PAD_PTA8__TCLK                    0x004 0x000 ALT1 0x0
+#define VF610_PAD_PTA8__DCU0_R0                 0x004 0x000 ALT4 0x0
+#define VF610_PAD_PTA8__MLB_CLK                 0x004 0x354 ALT7 0x0
+#define VF610_PAD_PTA9__GPIO_2                  0x008 0x000 ALT0 0x0
+#define VF610_PAD_PTA9__TDI                     0x008 0x000 ALT1 0x0
+#define VF610_PAD_PTA9__RMII_CLKOUT             0x008 0x000 ALT2 0x0
+#define VF610_PAD_PTA9__RMII_CLKIN              0x008 0x2F0 ALT3 0x1
+#define VF610_PAD_PTA9__DCU0_R1                 0x008 0x000 ALT4 0x0
+#define VF610_PAD_PTA9__WDOG_B                  0x008 0x000 ALT6 0x0
+#define VF610_PAD_PTA10__GPIO_3                 0x00C 0x000 ALT0 0x0
+#define VF610_PAD_PTA10__TDO                    0x00C 0x000 ALT1 0x0
+#define VF610_PAD_PTA10__EXT_AUDIO_MCLK         0x00C 0x2EC ALT2 0x0
+#define VF610_PAD_PTA10__DCU0_G0                0x00C 0x000 ALT4 0x0
+#define VF610_PAD_PTA10__ENET_TS_CLKIN          0x00C 0x2F4 ALT6 0x0
+#define VF610_PAD_PTA10__MLB_SIGNAL             0x00C 0x35C ALT7 0x0
+#define VF610_PAD_PTA11__GPIO_4                 0x010 0x000 ALT0 0x0
+#define VF610_PAD_PTA11__TMS                    0x010 0x000 ALT1 0x0
+#define VF610_PAD_PTA11__DCU0_G1                0x010 0x000 ALT4 0x0
+#define VF610_PAD_PTA11__MLB_DATA               0x010 0x358 ALT7 0x0
+#define VF610_PAD_PTA12__GPIO_5                 0x014 0x000 ALT0 0x0
+#define VF610_PAD_PTA12__TRACECK                0x014 0x000 ALT1 0x0
+#define VF610_PAD_PTA12__EXT_AUDIO_MCLK         0x014 0x2EC ALT2 0x1
+#define VF610_PAD_PTA12__VIU_DATA13             0x014 0x000 ALT6 0x0
+#define VF610_PAD_PTA12__I2C0_SCL               0x014 0x33C ALT7 0x0
+#define VF610_PAD_PTA16__GPIO_6                 0x018 0x000 ALT0 0x0
+#define VF610_PAD_PTA16__TRACED0                0x018 0x000 ALT1 0x0
+#define VF610_PAD_PTA16__USB0_VBUS_EN           0x018 0x000 ALT2 0x0
+#define VF610_PAD_PTA16__ADC1_SE0               0x018 0x000 ALT3 0x0
+#define VF610_PAD_PTA16__LCD29                  0x018 0x000 ALT4 0x0
+#define VF610_PAD_PTA16__SAI2_TX_BCLK           0x018 0x370 ALT5 0x0
+#define VF610_PAD_PTA16__VIU_DATA14             0x018 0x000 ALT6 0x0
+#define VF610_PAD_PTA16__I2C0_SDA               0x018 0x340 ALT7 0x0
+#define VF610_PAD_PTA17__GPIO_7                 0x01C 0x000 ALT0 0x0
+#define VF610_PAD_PTA17__TRACED1                0x01C 0x000 ALT1 0x0
+#define VF610_PAD_PTA17__USB0_VBUS_OC           0x01C 0x000 ALT2 0x0
+#define VF610_PAD_PTA17__ADC1_SE1               0x01C 0x000 ALT3 0x0
+#define VF610_PAD_PTA17__LCD30                  0x01C 0x000 ALT4 0x0
+#define VF610_PAD_PTA17__USB0_SOF_PULSE         0x01C 0x000 ALT5 0x0
+#define VF610_PAD_PTA17__VIU_DATA15             0x01C 0x000 ALT6 0x0
+#define VF610_PAD_PTA17__I2C1_SCL               0x01C 0x344 ALT7 0x0
+#define VF610_PAD_PTA18__GPIO_8                 0x020 0x000 ALT0 0x0
+#define VF610_PAD_PTA18__TRACED2                0x020 0x000 ALT1 0x0
+#define VF610_PAD_PTA18__ADC0_SE0               0x020 0x000 ALT2 0x0
+#define VF610_PAD_PTA18__FTM1_QD_PHA            0x020 0x334 ALT3 0x0
+#define VF610_PAD_PTA18__LCD31                  0x020 0x000 ALT4 0x0
+#define VF610_PAD_PTA18__SAI2_TX_DATA           0x020 0x000 ALT5 0x0
+#define VF610_PAD_PTA18__VIU_DATA16             0x020 0x000 ALT6 0x0
+#define VF610_PAD_PTA18__I2C1_SDA               0x020 0x348 ALT7 0x0
+#define VF610_PAD_PTA19__GPIO_9                 0x024 0x000 ALT0 0x0
+#define VF610_PAD_PTA19__TRACED3                0x024 0x000 ALT1 0x0
+#define VF610_PAD_PTA19__ADC0_SE1               0x024 0x000 ALT2 0x0
+#define VF610_PAD_PTA19__FTM1_QD_PHB            0x024 0x338 ALT3 0x0
+#define VF610_PAD_PTA19__LCD32                  0x024 0x000 ALT4 0x0
+#define VF610_PAD_PTA19__SAI2_TX_SYNC           0x024 0x000 ALT5 0x0
+#define VF610_PAD_PTA19__VIU_DATA17             0x024 0x000 ALT6 0x0
+#define VF610_PAD_PTA19__QSPI1_A_QSCK           0x024 0x374 ALT7 0x0
+#define VF610_PAD_PTA20__GPIO_10                0x028 0x000 ALT0 0x0
+#define VF610_PAD_PTA20__TRACED4                0x028 0x000 ALT1 0x0
+#define VF610_PAD_PTA20__LCD33                  0x028 0x000 ALT4 0x0
+#define VF610_PAD_PTA20__UART3_TX               0x028 0x394 ALT6 0x0
+#define VF610_PAD_PTA20__DCU1_HSYNC             0x028 0x000 ALT7 0x0
+#define VF610_PAD_PTA21__GPIO_11                0x02C 0x000 ALT0 0x0
+#define VF610_PAD_PTA21__TRACED5                0x02C 0x000 ALT1 0x0
+#define VF610_PAD_PTA21__SAI2_RX_BCLK           0x02C 0x364 ALT5 0x0
+#define VF610_PAD_PTA21__UART3_RX               0x02C 0x390 ALT6 0x0
+#define VF610_PAD_PTA21__DCU1_VSYNC             0x02C 0x000 ALT7 0x0
+#define VF610_PAD_PTA22__GPIO_12                0x030 0x000 ALT0 0x0
+#define VF610_PAD_PTA22__TRACED6                0x030 0x000 ALT1 0x0
+#define VF610_PAD_PTA22__SAI2_RX_DATA           0x030 0x368 ALT5 0x0
+#define VF610_PAD_PTA22__I2C2_SCL               0x030 0x34C ALT6 0x0
+#define VF610_PAD_PTA22__DCU1_TAG               0x030 0x000 ALT7 0x0
+#define VF610_PAD_PTA23__GPIO_13                0x034 0x000 ALT0 0x0
+#define VF610_PAD_PTA23__TRACED7                0x034 0x000 ALT1 0x0
+#define VF610_PAD_PTA23__SAI2_RX_SYNC           0x034 0x36C ALT5 0x0
+#define VF610_PAD_PTA23__I2C2_SDA               0x034 0x350 ALT6 0x0
+#define VF610_PAD_PTA23__DCU1_DE                0x034 0x000 ALT7 0x0
+#define VF610_PAD_PTA24__GPIO_14                0x038 0x000 ALT0 0x0
+#define VF610_PAD_PTA24__TRACED8                0x038 0x000 ALT1 0x0
+#define VF610_PAD_PTA24__USB1_VBUS_EN           0x038 0x000 ALT2 0x0
+#define VF610_PAD_PTA24__ESDHC1_CLK             0x038 0x000 ALT5 0x0
+#define VF610_PAD_PTA24__DCU1_TCON4             0x038 0x000 ALT6 0x0
+#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL      0x038 0x000 ALT7 0x0
+#define VF610_PAD_PTA25__GPIO_15                0x03C 0x000 ALT0 0x0
+#define VF610_PAD_PTA25__TRACED9                0x03C 0x000 ALT1 0x0
+#define VF610_PAD_PTA25__USB1_VBUS_OC           0x03C 0x000 ALT2 0x0
+#define VF610_PAD_PTA25__ESDHC1_CMD             0x03C 0x000 ALT5 0x0
+#define VF610_PAD_PTA25__DCU1_TCON5             0x03C 0x000 ALT6 0x0
+#define VF610_PAD_PTA26__GPIO_16                0x040 0x000 ALT0 0x0
+#define VF610_PAD_PTA26__TRACED10               0x040 0x000 ALT1 0x0
+#define VF610_PAD_PTA26__SAI3_TX_BCLK           0x040 0x000 ALT2 0x0
+#define VF610_PAD_PTA26__ESDHC1_DAT0            0x040 0x000 ALT5 0x0
+#define VF610_PAD_PTA26__DCU1_TCON6             0x040 0x000 ALT6 0x0
+#define VF610_PAD_PTA27__GPIO_17                0x044 0x000 ALT0 0x0
+#define VF610_PAD_PTA27__TRACED11               0x044 0x000 ALT1 0x0
+#define VF610_PAD_PTA27__SAI3_RX_BCLK           0x044 0x000 ALT2 0x0
+#define VF610_PAD_PTA27__ESDHC1_DAT1            0x044 0x000 ALT5 0x0
+#define VF610_PAD_PTA27__DCU1_TCON7             0x044 0x000 ALT6 0x0
+#define VF610_PAD_PTA28__GPIO_18                0x048 0x000 ALT0 0x0
+#define VF610_PAD_PTA28__TRACED12               0x048 0x000 ALT1 0x0
+#define VF610_PAD_PTA28__SAI3_RX_DATA           0x048 0x000 ALT2 0x0
+#define VF610_PAD_PTA28__ENET1_1588_TMR0        0x048 0x000 ALT3 0x0
+#define VF610_PAD_PTA28__UART4_TX               0x048 0x000 ALT4 0x0
+#define VF610_PAD_PTA28__ESDHC1_DATA2           0x048 0x000 ALT5 0x0
+#define VF610_PAD_PTA28__DCU1_TCON8             0x048 0x000 ALT6 0x0
+#define VF610_PAD_PTA29__GPIO_19                0x04C 0x000 ALT0 0x0
+#define VF610_PAD_PTA29__TRACED13               0x04C 0x000 ALT1 0x0
+#define VF610_PAD_PTA29__SAI3_TX_DATA           0x04C 0x000 ALT2 0x0
+#define VF610_PAD_PTA29__ENET1_1588_TMR1        0x04C 0x000 ALT3 0x0
+#define VF610_PAD_PTA29__UART4_RX               0x04C 0x000 ALT4 0x0
+#define VF610_PAD_PTA29__ESDHC1_DAT3            0x04C 0x000 ALT5 0x0
+#define VF610_PAD_PTA29__DCU1_TCON9             0x04C 0x000 ALT6 0x0
+#define VF610_PAD_PTA30__GPIO_20                0x050 0x000 ALT0 0x0
+#define VF610_PAD_PTA30__TRACED14               0x050 0x000 ALT1 0x0
+#define VF610_PAD_PTA30__SAI3_RX_SYNC           0x050 0x000 ALT2 0x0
+#define VF610_PAD_PTA30__ENET1_1588_TMR2        0x050 0x000 ALT3 0x0
+#define VF610_PAD_PTA30__UART4_RTS              0x050 0x000 ALT4 0x0
+#define VF610_PAD_PTA30__I2C3_SCL               0x050 0x000 ALT5 0x0
+#define VF610_PAD_PTA30__UART3_TX               0x050 0x394 ALT7 0x1
+#define VF610_PAD_PTA31__GPIO_21                0x054 0x000 ALT0 0x0
+#define VF610_PAD_PTA31__TRACED15               0x054 0x000 ALT1 0x0
+#define VF610_PAD_PTA31__SAI3_TX_SYNC           0x054 0x000 ALT2 0x0
+#define VF610_PAD_PTA31__ENET1_1588_TMR3        0x054 0x000 ALT3 0x0
+#define VF610_PAD_PTA31__UART4_CTS              0x054 0x000 ALT4 0x0
+#define VF610_PAD_PTA31__I2C3_SDA               0x054 0x000 ALT5 0x0
+#define VF610_PAD_PTA31__UART3_RX               0x054 0x390 ALT7 0x1
+#define VF610_PAD_PTB0__GPIO_22                 0x058 0x000 ALT0 0x0
+#define VF610_PAD_PTB0__FTM0_CH0                0x058 0x000 ALT1 0x0
+#define VF610_PAD_PTB0__ADC0_SE2                0x058 0x000 ALT2 0x0
+#define VF610_PAD_PTB0__TRACE_CTL               0x058 0x000 ALT3 0x0
+#define VF610_PAD_PTB0__LCD34                   0x058 0x000 ALT4 0x0
+#define VF610_PAD_PTB0__SAI2_RX_BCLK            0x058 0x364 ALT5 0x1
+#define VF610_PAD_PTB0__VIU_DATA18              0x058 0x000 ALT6 0x0
+#define VF610_PAD_PTB0__QSPI1_A_QPCS0           0x058 0x000 ALT7 0x0
+#define VF610_PAD_PTB1__GPIO_23                 0x05C 0x000 ALT0 0x0
+#define VF610_PAD_PTB1__FTM0_CH1                0x05C 0x000 ALT1 0x0
+#define VF610_PAD_PTB1__ADC0_SE3                0x05C 0x000 ALT2 0x0
+#define VF610_PAD_PTB1__SRC_RCON30              0x05C 0x000 ALT3 0x0
+#define VF610_PAD_PTB1__LCD35                   0x05C 0x000 ALT4 0x0
+#define VF610_PAD_PTB1__SAI2_RX_DATA            0x05C 0x368 ALT5 0x1
+#define VF610_PAD_PTB1__VIU_DATA19              0x05C 0x000 ALT6 0x0
+#define VF610_PAD_PTB1__QSPI1_A_DATA3           0x05C 0x000 ALT7 0x0
+#define VF610_PAD_PTB2__GPIO_24                 0x060 0x000 ALT0 0x0
+#define VF610_PAD_PTB2__FTM0_CH2                0x060 0x000 ALT1 0x0
+#define VF610_PAD_PTB2__ADC1_SE2                0x060 0x000 ALT2 0x0
+#define VF610_PAD_PTB2__SRC_RCON31              0x060 0x000 ALT3 0x0
+#define VF610_PAD_PTB2__LCD36                   0x060 0x000 ALT4 0x0
+#define VF610_PAD_PTB2__SAI2_RX_SYNC            0x060 0x36C ALT5 0x1
+#define VF610_PAD_PTB2__VIDEO_IN0_DATA20        0x060 0x000 ALT6 0x0
+#define VF610_PAD_PTB2__QSPI1_A_DATA2           0x060 0x000 ALT7 0x0
+#define VF610_PAD_PTB3__GPIO_25                 0x064 0x000 ALT0 0x0
+#define VF610_PAD_PTB3__FTM0_CH3                0x064 0x000 ALT1 0x0
+#define VF610_PAD_PTB3__ADC1_SE3                0x064 0x000 ALT2 0x0
+#define VF610_PAD_PTB3__PDB_EXTRIG              0x064 0x000 ALT3 0x0
+#define VF610_PAD_PTB3__LCD37                   0x064 0x000 ALT4 0x0
+#define VF610_PAD_PTB3__VIU_DATA21              0x064 0x000 ALT6 0x0
+#define VF610_PAD_PTB3__QSPI1_A_DATA1           0x064 0x000 ALT7 0x0
+#define VF610_PAD_PTB4__GPIO_26                 0x068 0x000 ALT0 0x0
+#define VF610_PAD_PTB4__FTM0_CH4                0x068 0x000 ALT1 0x0
+#define VF610_PAD_PTB4__UART1_TX                0x068 0x380 ALT2 0x0
+#define VF610_PAD_PTB4__ADC0_SE4                0x068 0x000 ALT3 0x0
+#define VF610_PAD_PTB4__LCD38                   0x068 0x000 ALT4 0x0
+#define VF610_PAD_PTB4__VIU_FID                 0x068 0x3A8 ALT5 0x0
+#define VF610_PAD_PTB4__VIU_DATA22              0x068 0x000 ALT6 0x0
+#define VF610_PAD_PTB4__QSPI1_A_DATA0           0x068 0x000 ALT7 0x0
+#define VF610_PAD_PTB5__GPIO_27                 0x06C 0x000 ALT0 0x0
+#define VF610_PAD_PTB5__FTM0_CH5                0x06C 0x000 ALT1 0x0
+#define VF610_PAD_PTB5__UART1_RX                0x06C 0x37C ALT2 0x0
+#define VF610_PAD_PTB5__ADC1_SE4                0x06C 0x000 ALT3 0x0
+#define VF610_PAD_PTB5__LCD39                   0x06C 0x000 ALT4 0x0
+#define VF610_PAD_PTB5__VIU_DE                  0x06C 0x3A4 ALT5 0x0
+#define VF610_PAD_PTB5__QSPI1_A_DQS             0x06C 0x000 ALT7 0x0
+#define VF610_PAD_PTB6__GPIO_28                 0x070 0x000 ALT0 0x0
+#define VF610_PAD_PTB6__FTM0_CH6                0x070 0x000 ALT1 0x0
+#define VF610_PAD_PTB6__UART1_RTS               0x070 0x000 ALT2 0x0
+#define VF610_PAD_PTB6__QSPI0_QPCS1_A           0x070 0x000 ALT3 0x0
+#define VF610_PAD_PTB6__LCD_LCD40               0x070 0x000 ALT4 0x0
+#define VF610_PAD_PTB6__FB_CLKOUT               0x070 0x000 ALT5 0x0
+#define VF610_PAD_PTB6__VIU_HSYNC               0x070 0x000 ALT6 0x0
+#define VF610_PAD_PTB6__UART2_TX                0x070 0x38C ALT7 0x0
+#define VF610_PAD_PTB7__GPIO_29                 0x074 0x000 ALT0 0x0
+#define VF610_PAD_PTB7__FTM0_CH7                0x074 0x000 ALT1 0x0
+#define VF610_PAD_PTB7__UART1_CTS               0x074 0x378 ALT2 0x0
+#define VF610_PAD_PTB7__QSPI0_B_QPCS1           0x074 0x000 ALT3 0x0
+#define VF610_PAD_PTB7__LCD41                   0x074 0x000 ALT4 0x0
+#define VF610_PAD_PTB7__VIU_VSYNC               0x074 0x000 ALT6 0x0
+#define VF610_PAD_PTB7__UART2_RX                0x074 0x388 ALT7 0x0
+#define VF610_PAD_PTB8__GPIO_30                 0x078 0x000 ALT0 0x0
+#define VF610_PAD_PTB8__FTM1_CH0                0x078 0x32C ALT1 0x0
+#define VF610_PAD_PTB8__FTM1_QD_PHA             0x078 0x334 ALT3 0x1
+#define VF610_PAD_PTB8__VIU_DE                  0x078 0x3A4 ALT5 0x1
+#define VF610_PAD_PTB8__DCU1_R6                 0x078 0x000 ALT7 0x0
+#define VF610_PAD_PTB9__GPIO_31                 0x07C 0x000 ALT0 0x0
+#define VF610_PAD_PTB9__FTM1_CH1                0x07C 0x330 ALT1 0x0
+#define VF610_PAD_PTB9__FTM1_QD_PHB             0x07C 0x338 ALT3 0x1
+#define VF610_PAD_PTB9__DCU1_R7                 0x07C 0x000 ALT7 0x0
+#define VF610_PAD_PTB10__GPIO_32                0x080 0x000 ALT0 0x0
+#define VF610_PAD_PTB10__UART0_TX               0x080 0x000 ALT1 0x0
+#define VF610_PAD_PTB10__DCU0_TCON4             0x080 0x000 ALT4 0x0
+#define VF610_PAD_PTB10__VIU_DE                 0x080 0x3A4 ALT5 0x2
+#define VF610_PAD_PTB10__CKO1                   0x080 0x000 ALT6 0x0
+#define VF610_PAD_PTB10__ENET_TS_CLKIN          0x080 0x2F4 ALT7 0x1
+#define VF610_PAD_PTB11__GPIO_33                0x084 0x000 ALT0 0x0
+#define VF610_PAD_PTB11__UART0_RX               0x084 0x000 ALT1 0x0
+#define VF610_PAD_PTB11__DCU0_TCON5             0x084 0x000 ALT4 0x0
+#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B       0x084 0x000 ALT5 0x0
+#define VF610_PAD_PTB11__CKO2                   0x084 0x000 ALT6 0x0
+#define VF610_PAD_PTB11_ENET0_1588_TMR0         0x084 0x304 ALT7 0x0
+#define VF610_PAD_PTB12__GPIO_34                0x088 0x000 ALT0 0x0
+#define VF610_PAD_PTB12__UART0_RTS              0x088 0x000 ALT1 0x0
+#define VF610_PAD_PTB12__DSPI0_CS5              0x088 0x000 ALT3 0x0
+#define VF610_PAD_PTB12__DCU0_TCON6             0x088 0x000 ALT4 0x0
+#define VF610_PAD_PTB12__FB_AD1                 0x088 0x000 ALT5 0x0
+#define VF610_PAD_PTB12__NMI                    0x088 0x000 ALT6 0x0
+#define VF610_PAD_PTB12__ENET0_1588_TMR1        0x088 0x308 ALT7 0x0
+#define VF610_PAD_PTB13__GPIO_35                0x08C 0x000 ALT0 0x0
+#define VF610_PAD_PTB13__UART0_CTS              0x08C 0x000 ALT1 0x0
+#define VF610_PAD_PTB13__DSPI0_CS4              0x08C 0x000 ALT3 0x0
+#define VF610_PAD_PTB13__DCU0_TCON7             0x08C 0x000 ALT4 0x0
+#define VF610_PAD_PTB13__FB_AD0                 0x08C 0x000 ALT5 0x0
+#define VF610_PAD_PTB13__TRACE_CTL              0x08C 0x000 ALT6 0x0
+#define VF610_PAD_PTB14__GPIO_36                0x090 0x000 ALT0 0x0
+#define VF610_PAD_PTB14__CAN0_RX                0x090 0x000 ALT1 0x0
+#define VF610_PAD_PTB14__I2C0_SCL               0x090 0x33C ALT2 0x1
+#define VF610_PAD_PTB14__DCU0_TCON8             0x090 0x000 ALT4 0x0
+#define VF610_PAD_PTB14__DCU1_PCLK              0x090 0x000 ALT7 0x0
+#define VF610_PAD_PTB15__GPIO_37                0x094 0x000 ALT0 0x0
+#define VF610_PAD_PTB15__CAN0_TX                0x094 0x000 ALT1 0x0
+#define VF610_PAD_PTB15__I2C0_SDA               0x094 0x340 ALT2 0x1
+#define VF610_PAD_PTB15__DCU0_TCON9             0x094 0x000 ALT4 0x0
+#define VF610_PAD_PTB15__VIU_PIX_CLK            0x094 0x3AC ALT7 0x0
+#define VF610_PAD_PTB16__GPIO_38                0x098 0x000 ALT0 0x0
+#define VF610_PAD_PTB16__CAN1_RX                0x098 0x000 ALT1 0x0
+#define VF610_PAD_PTB16__I2C1_SCL               0x098 0x344 ALT2 0x1
+#define VF610_PAD_PTB16__DCU0_TCON10            0x098 0x000 ALT4 0x0
+#define VF610_PAD_PTB17__GPIO_39                0x09C 0x000 ALT0 0x0
+#define VF610_PAD_PTB17__CAN1_TX                0x09C 0x000 ALT1 0x0
+#define VF610_PAD_PTB17__I2C1_SDA               0x09C 0x348 ALT2 0x1
+#define VF610_PAD_PTB17__DCU0_TCON11            0x09C 0x000 ALT4 0x0
+#define VF610_PAD_PTB18__GPIO_40                0x0A0 0x000 ALT0 0x0
+#define VF610_PAD_PTB18__DSPI0_CS1              0x0A0 0x000 ALT1 0x0
+#define VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x0A0 0x2EC ALT2 0x2
+#define VF610_PAD_PTB18__VIU_DATA9              0x0A0 0x000 ALT6 0x0
+#define VF610_PAD_PTB19__GPIO_41                0x0A4 0x000 ALT0 0x0
+#define VF610_PAD_PTB19__DSPI0_CS0              0x0A4 0x000 ALT1 0x0
+#define VF610_PAD_PTB19__VIU_DATA10             0x0A4 0x000 ALT6 0x0
+#define VF610_PAD_PTB20__GPIO_42                0x0A8 0x000 ALT0 0x0
+#define VF610_PAD_PTB20__DSPI0_SIN              0x0A8 0x000 ALT1 0x0
+#define VF610_PAD_PTB20__LCD42                  0x0A8 0x000 ALT4 0x0
+#define VF610_PAD_PTB20__VIU_DATA11             0x0A8 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__GPIO_43                0x0AC 0x000 ALT0 0x0
+#define VF610_PAD_PTB21__DSPI0_SOUT             0x0AC 0x000 ALT1 0x0
+#define VF610_PAD_PTB21__LCD43                  0x0AC 0x000 ALT4 0x0
+#define VF610_PAD_PTB21__VIU_DATA12             0x0AC 0x000 ALT6 0x0
+#define VF610_PAD_PTB21__DCU1_PCLK              0x0AC 0x000 ALT7 0x0
+#define VF610_PAD_PTB22__GPIO_44                0x0B0 0x000 ALT0 0x0
+#define VF610_PAD_PTB22__DSPI0_SCK              0x0B0 0x000 ALT1 0x0
+#define VF610_PAD_PTB22__VLCD                   0x0B0 0x000 ALT4 0x0
+#define VF610_PAD_PTB22__VIU_FID                0x0B0 0x3A8 ALT5 0x1
+#define VF610_PAD_PTC0__GPIO_45                 0x0B4 0x000 ALT0 0x0
+#define VF610_PAD_PTC0__ENET_RMII0_MDC          0x0B4 0x000 ALT1 0x0
+#define VF610_PAD_PTC0__FTM1_CH0                0x0B4 0x32C ALT2 0x1
+#define VF610_PAD_PTC0__DSPI0_CS3               0x0B4 0x000 ALT3 0x0
+#define VF610_PAD_PTC0__ESAI_SCKT               0x0B4 0x310 ALT4 0x0
+#define VF610_PAD_PTC0__ESDHC0_CLK              0x0B4 0x000 ALT5 0x0
+#define VF610_PAD_PTC0__VIU_DATA0               0x0B4 0x000 ALT6 0x0
+#define VF610_PAD_PTC0__SRC_RCON18              0x0B4 0x398 ALT7 0x0
+#define VF610_PAD_PTC1__GPIO_46                 0x0B8 0x000 ALT0 0x0
+#define VF610_PAD_PTC1__ENET_RMII0_MDIO         0x0B8 0x000 ALT1 0x0
+#define VF610_PAD_PTC1__FTM1_CH1                0x0B8 0x330 ALT2 0x1
+#define VF610_PAD_PTC1__DSPI0_CS2               0x0B8 0x000 ALT3 0x0
+#define VF610_PAD_PTC1__ESAI_FST                0x0B8 0x30C ALT4 0x0
+#define VF610_PAD_PTC1__ESDHC0_CMD              0x0B8 0x000 ALT5 0x0
+#define VF610_PAD_PTC1__VIU_DATA1               0x0B8 0x000 ALT6 0x0
+#define VF610_PAD_PTC1__SRC_RCON19              0x0B8 0x39C ALT7 0x0
+#define VF610_PAD_PTC2__GPIO_47                 0x0BC 0x000 ALT0 0x0
+#define VF610_PAD_PTC2__ENET_RMII0_CRS          0x0BC 0x000 ALT1 0x0
+#define VF610_PAD_PTC2__UART1_TX                0x0BC 0x380 ALT2 0x1
+#define VF610_PAD_PTC2__ESAI_SDO0               0x0BC 0x314 ALT4 0x0
+#define VF610_PAD_PTC2__ESDHC0_DAT0             0x0BC 0x000 ALT5 0x0
+#define VF610_PAD_PTC2__VIU_DATA2               0x0BC 0x000 ALT6 0x0
+#define VF610_PAD_PTC2__SRC_RCON20              0x0BC 0x3A0 ALT7 0x0
+#define VF610_PAD_PTC3__GPIO_48                 0x0C0 0x000 ALT0 0x0
+#define VF610_PAD_PTC3__ENET_RMII0_RXD1         0x0C0 0x000 ALT1 0x0
+#define VF610_PAD_PTC3__UART1_RX                0x0C0 0x37C ALT2 0x1
+#define VF610_PAD_PTC3__ESAI_SDO1               0x0C0 0x318 ALT4 0x0
+#define VF610_PAD_PTC3__ESDHC0_DAT1             0x0C0 0x000 ALT5 0x0
+#define VF610_PAD_PTC3__VIU_DATA3               0x0C0 0x000 ALT6 0x0
+#define VF610_PAD_PTC3__DCU0_R0                 0x0C0 0x000 ALT7 0x0
+#define VF610_PAD_PTC4__GPIO_49                 0x0C4 0x000 ALT0 0x0
+#define VF610_PAD_PTC4__ENET_RMII0_RXD0         0x0C4 0x000 ALT1 0x0
+#define VF610_PAD_PTC4__UART1_RTS               0x0C4 0x000 ALT2 0x0
+#define VF610_PAD_PTC4__DSPI1_CS1               0x0C4 0x000 ALT3 0x0
+#define VF610_PAD_PTC4__ESAI_SDO2               0x0C4 0x31C ALT4 0x0
+#define VF610_PAD_PTC4__ESDHC0_DAT2             0x0C4 0x000 ALT5 0x0
+#define VF610_PAD_PTC4__VIU_DATA4               0x0C4 0x000 ALT6 0x0
+#define VF610_PAD_PTC4__DCU0_R1                 0x0C4 0x000 ALT7 0x0
+#define VF610_PAD_PTC5__GPIO_50                 0x0C8 0x000 ALT0 0x0
+#define VF610_PAD_PTC5__ENET_RMII0_RXER         0x0C8 0x000 ALT1 0x0
+#define VF610_PAD_PTC5__UART1_CTS               0x0C8 0x378 ALT2 0x1
+#define VF610_PAD_PTC5__DSPI1_CS0               0x0C8 0x300 ALT3 0x0
+#define VF610_PAD_PTC5__ESAI_SDO3               0x0C8 0x320 ALT4 0x0
+#define VF610_PAD_PTC5__ESDHC0_DAT3             0x0C8 0x000 ALT5 0x0
+#define VF610_PAD_PTC5__VIU_DATA5               0x0C8 0x000 ALT6 0x0
+#define VF610_PAD_PTC5__DCU0_G0                 0x0C8 0x000 ALT7 0x0
+#define VF610_PAD_PTC6__GPIO_51                 0x0CC 0x000 ALT0 0x0
+#define VF610_PAD_PTC6__ENET_RMII0_TXD1         0x0CC 0x000 ALT1 0x0
+#define VF610_PAD_PTC6__DSPI1_SIN               0x0CC 0x2FC ALT3 0x0
+#define VF610_PAD_PTC6__ESAI_SDI0               0x0CC 0x328 ALT4 0x0
+#define VF610_PAD_PTC6__ESDHC0_WP               0x0CC 0x000 ALT5 0x0
+#define VF610_PAD_PTC6__VIU_DATA6               0x0CC 0x000 ALT6 0x0
+#define VF610_PAD_PTC6__DCU0_G1                 0x0CC 0x000 ALT7 0x0
+#define VF610_PAD_PTC7__GPIO_52                 0x0D0 0x000 ALT0 0x0
+#define VF610_PAD_PTC7__ENET_RMII0_TXD0         0x0D0 0x000 ALT1 0x0
+#define VF610_PAD_PTC7__DSPI1_SOUT              0x0D0 0x000 ALT3 0x0
+#define VF610_PAD_PTC7__ESAI_SDI1               0x0D0 0x324 ALT4 0x0
+#define VF610_PAD_PTC7__VIU_DATA7               0x0D0 0x000 ALT6 0x0
+#define VF610_PAD_PTC7__DCU0_B0                 0x0D0 0x000 ALT7 0x0
+#define VF610_PAD_PTC8__GPIO_53                 0x0D4 0x000 ALT0 0x0
+#define VF610_PAD_PTC8__ENET_RMII0_TXEN         0x0D4 0x000 ALT1 0x0
+#define VF610_PAD_PTC8__DSPI1_SCK               0x0D4 0x2F8 ALT3 0x0
+#define VF610_PAD_PTC8__VIU_DATA8               0x0D4 0x000 ALT6 0x0
+#define VF610_PAD_PTC8__DCU0_B1                 0x0D4 0x000 ALT7 0x0
+#define VF610_PAD_PTC9__GPIO_54                 0x0D8 0x000 ALT0 0x0
+#define VF610_PAD_PTC9__ENET_RMII1_MDC          0x0D8 0x000 ALT1 0x0
+#define VF610_PAD_PTC9__ESAI_SCKT               0x0D8 0x310 ALT3 0x1
+#define VF610_PAD_PTC9__MLB_CLK                 0x0D8 0x354 ALT6 0x1
+#define VF610_PAD_PTC9__DEBUG_OUT0              0x0D8 0x000 ALT7 0x0
+#define VF610_PAD_PTC10__GPIO_55                0x0DC 0x000 ALT0 0x0
+#define VF610_PAD_PTC10__ENET_RMII1_MDIO        0x0DC 0x000 ALT1 0x0
+#define VF610_PAD_PTC10__ESAI_FST               0x0DC 0x30C ALT3 0x1
+#define VF610_PAD_PTC10__MLB_SIGNAL             0x0DC 0x35C ALT6 0x1
+#define VF610_PAD_PTC10__DEBUG_OUT1             0x0DC 0x000 ALT7 0x0
+#define VF610_PAD_PTC11__GPIO_56                0x0E0 0x000 ALT0 0x0
+#define VF610_PAD_PTC11__ENET_RMII1_CRS         0x0E0 0x000 ALT1 0x0
+#define VF610_PAD_PTC11__ESAI_SDO0              0x0E0 0x314 ALT3 0x1
+#define VF610_PAD_PTC11__MLB_DATA               0x0E0 0x358 ALT6 0x1
+#define VF610_PAD_PTC11__DEBUG_OUT              0x0E0 0x000 ALT7 0x0
+#define VF610_PAD_PTC12__GPIO_57                0x0E4 0x000 ALT0 0x0
+#define VF610_PAD_PTC12__ENET_RMII_RXD1         0x0E4 0x000 ALT1 0x0
+#define VF610_PAD_PTC12__ESAI_SDO1              0x0E4 0x318 ALT3 0x1
+#define VF610_PAD_PTC12__SAI2_TX_BCLK           0x0E4 0x370 ALT5 0x1
+#define VF610_PAD_PTC12__DEBUG_OUT3             0x0E4 0x000 ALT7 0x0
+#define VF610_PAD_PTC13__GPIO_58                0x0E8 0x000 ALT0 0x0
+#define VF610_PAD_PTC13__ENET_RMII1_RXD0        0x0E8 0x000 ALT1 0x0
+#define VF610_PAD_PTC13__ESAI_SDO2              0x0E8 0x31C ALT3 0x1
+#define VF610_PAD_PTC13__SAI2_RX_BCLK           0x0E8 0x364 ALT5 0x2
+#define VF610_PAD_PTC13__DEBUG_OUT4             0x0E8 0x000 ALT7 0x0
+#define VF610_PAD_PTC14__GPIO_59                0x0EC 0x000 ALT0 0x0
+#define VF610_PAD_PTC14__ENET_RMII1_RXER        0x0EC 0x000 ALT1 0x0
+#define VF610_PAD_PTC14__ESAI_SDO3              0x0EC 0x320 ALT3 0x1
+#define VF610_PAD_PTC14__UART5_TX               0x0EC 0x000 ALT4 0x0
+#define VF610_PAD_PTC14__SAI2_RX_DATA           0x0EC 0x368 ALT5 0x2
+#define VF610_PAD_PTC14__ADC0_SE6               0x0EC 0x000 ALT6 0x0
+#define VF610_PAD_PTC14__DEBUG_OUT5             0x0EC 0x000 ALT7 0x0
+#define VF610_PAD_PTC15__GPIO_60                0x0F0 0x000 ALT0 0x0
+#define VF610_PAD_PTC15__ENET_RMII1_TXD1        0x0F0 0x000 ALT1 0x0
+#define VF610_PAD_PTC15__ESAI_SDI0              0x0F0 0x328 ALT3 0x1
+#define VF610_PAD_PTC15__UART5_RX               0x0F0 0x000 ALT4 0x0
+#define VF610_PAD_PTC15__SAI2_TX_DATA           0x0F0 0x000 ALT5 0x0
+#define VF610_PAD_PTC15__ADC0_SE7               0x0F0 0x000 ALT6 0x0
+#define VF610_PAD_PTC15__DEBUG_OUT6             0x0F0 0x000 ALT7 0x0
+#define VF610_PAD_PTC16__GPIO_61                0x0F4 0x000 ALT0 0x0
+#define VF610_PAD_PTC16__ENET_RMII1_TXD0        0x0F4 0x000 ALT1 0x0
+#define VF610_PAD_PTC16__ESAI_SDI1              0x0F4 0x324 ALT3 0x1
+#define VF610_PAD_PTC16__UART5_RTS              0x0F4 0x000 ALT4 0x0
+#define VF610_PAD_PTC16__SAI2_RX_SYNC           0x0F4 0x36C ALT5 0x2
+#define VF610_PAD_PTC16__ADC1_SE6               0x0F4 0x000 ALT6 0x0
+#define VF610_PAD_PTC16__DEBUG_OUT7             0x0F4 0x000 ALT7 0x0
+#define VF610_PAD_PTC17__GPIO_62                0x0F8 0x000 ALT0 0x0
+#define VF610_PAD_PTC17__ENET_RMII1_TXEN        0x0F8 0x000 ALT1 0x0
+#define VF610_PAD_PTC17__ADC1_SE7               0x0F8 0x000 ALT3 0x0
+#define VF610_PAD_PTC17__UART5_CTS              0x0F8 0x000 ALT4 0x0
+#define VF610_PAD_PTC17__SAI2_TX_SYNC           0x0F8 0x374 ALT5 0x1
+#define VF610_PAD_PTC17__USB1_SOF_PULSE         0x0F8 0x000 ALT6 0x0
+#define VF610_PAD_PTC17__DEBUG_OUT8             0x0F8 0x000 ALT7 0x0
+#define VF610_PAD_PTD31__GPIO_63                0x0FC 0x000 ALT0 0x0
+#define VF610_PAD_PTD31__FB_AD31                0x0FC 0x000 ALT1 0x0
+#define VF610_PAD_PTD31__NF_IO15                0x0FC 0x000 ALT2 0x0
+#define VF610_PAD_PTD31__FTM3_CH0               0x0FC 0x000 ALT4 0x0
+#define VF610_PAD_PTD31__DSPI2_CS1              0x0FC 0x000 ALT5 0x0
+#define VF610_PAD_PTD31__DEBUG_OUT9             0x0FC 0x000 ALT7 0x0
+#define VF610_PAD_PTD30__GPIO_64                0x100 0x000 ALT0 0x0
+#define VF610_PAD_PTD30__FB_AD30                0x100 0x000 ALT1 0x0
+#define VF610_PAD_PTD30__NF_IO14                0x100 0x000 ALT2 0x0
+#define VF610_PAD_PTD30__FTM3_CH1               0x100 0x000 ALT4 0x0
+#define VF610_PAD_PTD30__DSPI2_CS0              0x100 0x000 ALT5 0x0
+#define VF610_PAD_PTD30__DEBUG_OUT10            0x100 0x000 ALT7 0x0
+#define VF610_PAD_PTD29__GPIO_65                0x104 0x000 ALT0 0x0
+#define VF610_PAD_PTD29__FB_AD29                0x104 0x000 ALT1 0x0
+#define VF610_PAD_PTD29__NF_IO13                0x104 0x000 ALT2 0x0
+#define VF610_PAD_PTD29__FTM3_CH2               0x104 0x000 ALT4 0x0
+#define VF610_PAD_PTD29__DSPI2_SIN              0x104 0x000 ALT5 0x0
+#define VF610_PAD_PTD29__DEBUG_OUT11            0x104 0x000 ALT7 0x0
+#define VF610_PAD_PTD28__GPIO_66                0x108 0x000 ALT0 0x0
+#define VF610_PAD_PTD28__FB_AD28                0x108 0x000 ALT1 0x0
+#define VF610_PAD_PTD28__NF_IO12                0x108 0x000 ALT2 0x0
+#define VF610_PAD_PTD28__I2C2_SCL               0x108 0x34C ALT3 0x1
+#define VF610_PAD_PTD28__FTM3_CH3               0x108 0x000 ALT4 0x0
+#define VF610_PAD_PTD28__DSPI2_SOUT             0x108 0x000 ALT5 0x0
+#define VF610_PAD_PTD28__DEBUG_OUT12            0x108 0x000 ALT7 0x0
+#define VF610_PAD_PTD27__GPIO_67                0x10C 0x000 ALT0 0x0
+#define VF610_PAD_PTD27__FB_AD27                0x10C 0x000 ALT1 0x0
+#define VF610_PAD_PTD27__NF_IO11                0x10C 0x000 ALT2 0x0
+#define VF610_PAD_PTD27__I2C2_SDA               0x10C 0x350 ALT3 0x1
+#define VF610_PAD_PTD27__FTM3_CH4               0x10C 0x000 ALT4 0x0
+#define VF610_PAD_PTD27__DSPI2_SCK              0x10C 0x000 ALT5 0x0
+#define VF610_PAD_PTD27__DEBUG_OUT13            0x10C 0x000 ALT7 0x0
+#define VF610_PAD_PTD26__GPIO_68                0x110 0x000 ALT0 0x0
+#define VF610_PAD_PTD26__FB_AD26                0x110 0x000 ALT1 0x0
+#define VF610_PAD_PTD26__NF_IO10                0x110 0x000 ALT2 0x0
+#define VF610_PAD_PTD26__FTM3_CH5               0x110 0x000 ALT4 0x0
+#define VF610_PAD_PTD26__ESDHC1_WP              0x110 0x000 ALT5 0x0
+#define VF610_PAD_PTD26__DEBUG_OUT14            0x110 0x000 ALT7 0x0
+#define VF610_PAD_PTD25__GPIO_69                0x114 0x000 ALT0 0x0
+#define VF610_PAD_PTD25__FB_AD25                0x114 0x000 ALT1 0x0
+#define VF610_PAD_PTD25__NF_IO9                 0x114 0x000 ALT2 0x0
+#define VF610_PAD_PTD25__FTM3_CH6               0x114 0x000 ALT4 0x0
+#define VF610_PAD_PTD25__DEBUG_OUT15            0x114 0x000 ALT7 0x0
+#define VF610_PAD_PTD24__GPIO_70                0x118 0x000 ALT0 0x0
+#define VF610_PAD_PTD24__FB_AD24                0x118 0x000 ALT1 0x0
+#define VF610_PAD_PTD24__NF_IO8                 0x118 0x000 ALT2 0x0
+#define VF610_PAD_PTD24__FTM3_CH7               0x118 0x000 ALT4 0x0
+#define VF610_PAD_PTD24__DEBUG_OUT16            0x118 0x000 ALT7 0x0
+#define VF610_PAD_PTD23__GPIO_71                0x11C 0x000 ALT0 0x0
+#define VF610_PAD_PTD23__FB_AD23                0x11C 0x000 ALT1 0x0
+#define VF610_PAD_PTD23__NF_IO7                 0x11C 0x000 ALT2 0x0
+#define VF610_PAD_PTD23__FTM2_CH0               0x11C 0x000 ALT3 0x0
+#define VF610_PAD_PTD23__ENET0_1588_TMR0        0x11C 0x304 ALT4 0x1
+#define VF610_PAD_PTD23__ESDHC0_DAT4            0x11C 0x000 ALT5 0x0
+#define VF610_PAD_PTD23__UART2_TX               0x11C 0x38C ALT6 0x1
+#define VF610_PAD_PTD23__DCU1_R3                0x11C 0x000 ALT7 0x0
+#define VF610_PAD_PTD22__GPIO_72                0x120 0x000 ALT0 0x0
+#define VF610_PAD_PTD22__FB_AD22                0x120 0x000 ALT1 0x0
+#define VF610_PAD_PTD22__NF_IO6                 0x120 0x000 ALT2 0x0
+#define VF610_PAD_PTD22__FTM2_CH1               0x120 0x000 ALT3 0x0
+#define VF610_PAD_PTD22__ENET0_1588_TMR1        0x120 0x308 ALT4 0x1
+#define VF610_PAD_PTD22__ESDHC0_DAT5            0x120 0x000 ALT5 0x0
+#define VF610_PAD_PTD22__UART2_RX               0x120 0x388 ALT6 0x1
+#define VF610_PAD_PTD22__DCU1_R4                0x120 0x000 ALT7 0x0
+#define VF610_PAD_PTD21__GPIO_73                0x124 0x000 ALT0 0x0
+#define VF610_PAD_PTD21__FB_AD21                0x124 0x000 ALT1 0x0
+#define VF610_PAD_PTD21__NF_IO5                 0x124 0x000 ALT2 0x0
+#define VF610_PAD_PTD21__ENET0_1588_TMR2        0x124 0x000 ALT4 0x0
+#define VF610_PAD_PTD21__ESDHC0_DAT6            0x124 0x000 ALT5 0x0
+#define VF610_PAD_PTD21__UART2_RTS              0x124 0x000 ALT6 0x0
+#define VF610_PAD_PTD21__DCU1_R5                0x124 0x000 ALT7 0x0
+#define VF610_PAD_PTD20__GPIO_74                0x128 0x000 ALT0 0x0
+#define VF610_PAD_PTD20__FB_AD20                0x128 0x000 ALT1 0x0
+#define VF610_PAD_PTD20__NF_IO4                 0x128 0x000 ALT2 0x0
+#define VF610_PAD_PTD20__ENET0_1588_TMR3        0x128 0x000 ALT4 0x0
+#define VF610_PAD_PTD20__ESDHC0_DAT7            0x128 0x000 ALT5 0x0
+#define VF610_PAD_PTD20__UART2_CTS              0x128 0x384 ALT6 0x0
+#define VF610_PAD_PTD20__DCU1_R0                0x128 0x000 ALT7 0x0
+#define VF610_PAD_PTD19__GPIO_75                0x12C 0x000 ALT0 0x0
+#define VF610_PAD_PTD19__FB_AD19                0x12C 0x000 ALT1 0x0
+#define VF610_PAD_PTD19__NF_IO3                 0x12C 0x000 ALT2 0x0
+#define VF610_PAD_PTD19__ESAI_SCKR              0x12C 0x000 ALT3 0x0
+#define VF610_PAD_PTD19__I2C0_SCL               0x12C 0x33C ALT4 0x2
+#define VF610_PAD_PTD19__FTM2_QD_PHA            0x12C 0x000 ALT5 0x0
+#define VF610_PAD_PTD19__DCU1_R1                0x12C 0x000 ALT7 0x0
+#define VF610_PAD_PTD18__GPIO_76                0x130 0x000 ALT0 0x0
+#define VF610_PAD_PTD18__FB_AD18                0x130 0x000 ALT1 0x0
+#define VF610_PAD_PTD18__NF_IO2                 0x130 0x000 ALT2 0x0
+#define VF610_PAD_PTD18__ESAI_FSR               0x130 0x000 ALT3 0x0
+#define VF610_PAD_PTD18__I2C0_SDA               0x130 0x340 ALT4 0x2
+#define VF610_PAD_PTD18__FTM2_QD_PHB            0x130 0x000 ALT5 0x0
+#define VF610_PAD_PTD18__DCU1_G0                0x130 0x000 ALT7 0x0
+#define VF610_PAD_PTD17__GPIO_77                0x134 0x000 ALT0 0x0
+#define VF610_PAD_PTD17__FB_AD17                0x134 0x000 ALT1 0x0
+#define VF610_PAD_PTD17__NF_IO1                 0x134 0x000 ALT2 0x0
+#define VF610_PAD_PTD17__ESAI_HCKR              0x134 0x000 ALT3 0x0
+#define VF610_PAD_PTD17__I2C1_SCL               0x134 0x344 ALT4 0x2
+#define VF610_PAD_PTD17__DCU1_G1                0x134 0x000 ALT7 0x0
+#define VF610_PAD_PTD16__GPIO_78                0x138 0x000 ALT0 0x0
+#define VF610_PAD_PTD16__FB_AD16                0x138 0x000 ALT1 0x0
+#define VF610_PAD_PTD16__NF_IO0                 0x138 0x000 ALT2 0x0
+#define VF610_PAD_PTD16__ESAI_HCKT              0x138 0x000 ALT3 0x0
+#define VF610_PAD_PTD16__I2C1_SDA               0x138 0x348 ALT4 0x2
+#define VF610_PAD_PTD16__DCU1_G2                0x138 0x000 ALT7 0x0
+#define VF610_PAD_PTD0__GPIO_79                 0x13C 0x000 ALT0 0x0
+#define VF610_PAD_PTD0__QSPI0_A_QSCK            0x13C 0x000 ALT1 0x0
+#define VF610_PAD_PTD0__UART2_TX                0x13C 0x38C ALT2 0x2
+#define VF610_PAD_PTD0__FB_AD15                 0x13C 0x000 ALT4 0x0
+#define VF610_PAD_PTD0__SPDIF_EXTCLK            0x13C 0x000 ALT5 0x0
+#define VF610_PAD_PTD0__DEBUG_OUT17             0x13C 0x000 ALT7 0x0
+#define VF610_PAD_PTD1__GPIO_80                 0x140 0x000 ALT0 0x0
+#define VF610_PAD_PTD1__QSPI0_A_CS0             0x140 0x000 ALT1 0x0
+#define VF610_PAD_PTD1__UART2_RX                0x140 0x388 ALT2 0x2
+#define VF610_PAD_PTD1__FB_AD14                 0x140 0x000 ALT4 0x0
+#define VF610_PAD_PTD1__SPDIF_IN1               0x140 0x000 ALT5 0x0
+#define VF610_PAD_PTD1__DEBUG_OUT18             0x140 0x000 ALT7 0x0
+#define VF610_PAD_PTD2__GPIO_81                 0x144 0x000 ALT0 0x0
+#define VF610_PAD_PTD2__QSPI0_A_DATA3           0x144 0x000 ALT1 0x0
+#define VF610_PAD_PTD2__UART2_RTS               0x144 0x000 ALT2 0x0
+#define VF610_PAD_PTD2__DSPI1_CS3               0x144 0x000 ALT3 0x0
+#define VF610_PAD_PTD2__FB_AD13                 0x144 0x000 ALT4 0x0
+#define VF610_PAD_PTD2__SPDIF_OUT1              0x144 0x000 ALT5 0x0
+#define VF610_PAD_PTD2__DEBUG_OUT19             0x144 0x000 ALT7 0x0
+#define VF610_PAD_PTD3__GPIO_82                 0x148 0x000 ALT0 0x0
+#define VF610_PAD_PTD3__QSPI0_A_DATA2           0x148 0x000 ALT1 0x0
+#define VF610_PAD_PTD3__UART2_CTS               0x148 0x384 ALT2 0x1
+#define VF610_PAD_PTD3__DSPI1_CS2               0x148 0x000 ALT3 0x0
+#define VF610_PAD_PTD3__FB_AD12                 0x148 0x000 ALT4 0x0
+#define VF610_PAD_PTD3__SPDIF_PLOCK             0x148 0x000 ALT5 0x0
+#define VF610_PAD_PTD3__DEBUG_OUT20             0x148 0x000 ALT7 0x0
+#define VF610_PAD_PTD4__GPIO_83                 0x14C 0x000 ALT0 0x0
+#define VF610_PAD_PTD4__QSPI0_A_DATA1           0x14C 0x000 ALT1 0x0
+#define VF610_PAD_PTD4__DSPI1_CS1               0x14C 0x000 ALT3 0x0
+#define VF610_PAD_PTD4__FB_AD11                 0x14C 0x000 ALT4 0x0
+#define VF610_PAD_PTD4__SPDIF_SRCLK             0x14C 0x000 ALT5 0x0
+#define VF610_PAD_PTD4__DEBUG_OUT21             0x14C 0x000 ALT7 0x0
+#define VF610_PAD_PTD5__GPIO_84                 0x150 0x000 ALT0 0x0
+#define VF610_PAD_PTD5__QSPI0_A_DATA0           0x150 0x000 ALT1 0x0
+#define VF610_PAD_PTD5__DSPI1_CS0               0x150 0x300 ALT3 0x1
+#define VF610_PAD_PTD5__FB_AD10                 0x150 0x000 ALT4 0x0
+#define VF610_PAD_PTD5__DEBUG_OUT22             0x150 0x000 ALT7 0x0
+#define VF610_PAD_PTD6__GPIO_85                 0x154 0x000 ALT0 0x0
+#define VF610_PAD_PTD6__QSPI1_A_DQS             0x154 0x000 ALT1 0x0
+#define VF610_PAD_PTD6__DSPI1_SIN               0x154 0x2FC ALT3 0x1
+#define VF610_PAD_PTD6__FB_AD9                  0x154 0x000 ALT4 0x0
+#define VF610_PAD_PTD6__DEBUG_OUT23             0x154 0x000 ALT7 0x0
+#define VF610_PAD_PTD7__GPIO_86                 0x158 0x000 ALT0 0x0
+#define VF610_PAD_PTD7__QSPI0_B_QSCK            0x158 0x000 ALT1 0x0
+#define VF610_PAD_PTD7__DSPI1_SOUT              0x158 0x000 ALT3 0x0
+#define VF610_PAD_PTD7__FB_AD8                  0x158 0x000 ALT4 0x0
+#define VF610_PAD_PTD7__DEBUG_OUT24             0x158 0x000 ALT7 0x0
+#define VF610_PAD_PTD8__GPIO_87                 0x15C 0x000 ALT0 0x0
+#define VF610_PAD_PTD8__QSPI0_B_CS0             0x15C 0x000 ALT1 0x0
+#define VF610_PAD_PTD8__FB_CLKOUT               0x15C 0x000 ALT2 0x0
+#define VF610_PAD_PTD8__DSPI1_SCK               0x15C 0x2F8 ALT3 0x1
+#define VF610_PAD_PTD8__FB_AD7                  0x15C 0x000 ALT4 0x0
+#define VF610_PAD_PTD8__DEBUG_OUT25             0x15C 0x000 ALT7 0x0
+#define VF610_PAD_PTD9__GPIO_88                 0x160 0x000 ALT0 0x0
+#define VF610_PAD_PTD9__QSPI0_B_DATA3           0x160 0x000 ALT1 0x0
+#define VF610_PAD_PTD9__DSPI3_CS1               0x160 0x000 ALT2 0x0
+#define VF610_PAD_PTD9__FB_AD6                  0x160 0x000 ALT4 0x0
+#define VF610_PAD_PTD9__SAI1_TX_SYNC            0x160 0x360 ALT6 0x0
+#define VF610_PAD_PTD9__DCU1_B0                 0x160 0x000 ALT7 0x0
+#define VF610_PAD_PTD10__GPIO_89                0x164 0x000 ALT0 0x0
+#define VF610_PAD_PTD10__QSPI0_B_DATA2          0x164 0x000 ALT1 0x0
+#define VF610_PAD_PTD10__DSPI3_CS0              0x164 0x000 ALT2 0x0
+#define VF610_PAD_PTD10__FB_AD5                 0x164 0x000 ALT4 0x0
+#define VF610_PAD_PTD10__DCU1_B1                0x164 0x000 ALT7 0x0
+#define VF610_PAD_PTD11__GPIO_90                0x168 0x000 ALT0 0x0
+#define VF610_PAD_PTD11__QSPI0_B_DATA1          0x168 0x000 ALT1 0x0
+#define VF610_PAD_PTD11__DSPI3_SIN              0x168 0x000 ALT2 0x0
+#define VF610_PAD_PTD11__FB_AD4                 0x168 0x000 ALT4 0x0
+#define VF610_PAD_PTD11__DEBUG_OUT26            0x168 0x000 ALT7 0x0
+#define VF610_PAD_PTD12__GPIO_91                0x16C 0x000 ALT0 0x0
+#define VF610_PAD_PTD12__QSPI0_B_DATA0          0x16C 0x000 ALT1 0x0
+#define VF610_PAD_PTD12__DSPI3_SOUT             0x16C 0x000 ALT2 0x0
+#define VF610_PAD_PTD12__FB_AD3                 0x16C 0x000 ALT4 0x0
+#define VF610_PAD_PTD12__DEBUG_OUT27            0x16C 0x000 ALT7 0x0
+#define VF610_PAD_PTD13__GPIO_92                0x170 0x000 ALT0 0x0
+#define VF610_PAD_PTD13__QSPI0_B_DQS            0x170 0x000 ALT1 0x0
+#define VF610_PAD_PTD13__DSPI3_SCK              0x170 0x000 ALT2 0x0
+#define VF610_PAD_PTD13__FB_AD2                 0x170 0x000 ALT4 0x0
+#define VF610_PAD_PTD13__DEBUG_OUT28            0x170 0x000 ALT7 0x0
+#define VF610_PAD_PTB23__GPIO_93                0x174 0x000 ALT0 0x0
+#define VF610_PAD_PTB23__SAI0_TX_BCLK           0x174 0x000 ALT1 0x0
+#define VF610_PAD_PTB23__UART1_TX               0x174 0x380 ALT2 0x2
+#define VF610_PAD_PTB23__SRC_RCON18             0x174 0x398 ALT3 0x1
+#define VF610_PAD_PTB23__FB_MUXED_ALE           0x174 0x000 ALT4 0x0
+#define VF610_PAD_PTB23__FB_TS_B                0x174 0x000 ALT5 0x0
+#define VF610_PAD_PTB23__UART3_RTS              0x174 0x000 ALT6 0x0
+#define VF610_PAD_PTB23__DCU1_G3                0x174 0x000 ALT7 0x0
+#define VF610_PAD_PTB24__GPIO_94                0x178 0x000 ALT0 0x0
+#define VF610_PAD_PTB24__SAI0_RX_BCLK           0x178 0x000 ALT1 0x0
+#define VF610_PAD_PTB24__UART1_RX               0x178 0x37C ALT2 0x2
+#define VF610_PAD_PTB24__SRC_RCON19             0x178 0x39C ALT3 0x1
+#define VF610_PAD_PTB24__FB_MUXED_TSIZ0         0x178 0x000 ALT4 0x0
+#define VF610_PAD_PTB24__NF_WE_B                0x178 0x000 ALT5 0x0
+#define VF610_PAD_PTB24__UART3_CTS              0x178 0x000 ALT6 0x0
+#define VF610_PAD_PTB24__DCU1_G4                0x178 0x000 ALT7 0x0
+#define VF610_PAD_PTB25__GPIO_95                0x17C 0x000 ALT0 0x0
+#define VF610_PAD_PTB25__SAI0_RX_DATA           0x17C 0x000 ALT1 0x0
+#define VF610_PAD_PTB25__UART1_RTS              0x17C 0x000 ALT2 0x0
+#define VF610_PAD_PTB25__SRC_RCON20             0x17C 0x3A0 ALT3 0x1
+#define VF610_PAD_PTB25__FB_CS1_B               0x17C 0x000 ALT4 0x0
+#define VF610_PAD_PTB25__NF_CE0_B               0x17C 0x000 ALT5 0x0
+#define VF610_PAD_PTB25__DCU1_G5                0x17C 0x000 ALT7 0x0
+#define VF610_PAD_PTB26__GPIO_96                0x180 0x000 ALT0 0x0
+#define VF610_PAD_PTB26__SAI0_TX_DATA           0x180 0x000 ALT1 0x0
+#define VF610_PAD_PTB26__UART1_CTS              0x180 0x378 ALT2 0x2
+#define VF610_PAD_PTB26__SRC_RCON21             0x180 0x000 ALT3 0x0
+#define VF610_PAD_PTB26__FB_CS0_B               0x180 0x000 ALT4 0x0
+#define VF610_PAD_PTB26__NF_CE1_B               0x180 0x000 ALT5 0x0
+#define VF610_PAD_PTB26__DCU1_G6                0x180 0x000 ALT7 0x0
+#define VF610_PAD_PTB27__GPIO_97                0x184 0x000 ALT0 0x0
+#define VF610_PAD_PTB27__SAI0_RX_SYNC           0x184 0x000 ALT1 0x0
+#define VF610_PAD_PTB27__SRC_RCON22             0x184 0x000 ALT3 0x0
+#define VF610_PAD_PTB27__FB_OE_B                0x184 0x000 ALT4 0x0
+#define VF610_PAD_PTB27__FB_MUXED_TBST_B        0x184 0x000 ALT5 0x0
+#define VF610_PAD_PTB27__NF_RE_B                0x184 0x000 ALT6 0x0
+#define VF610_PAD_PTB27__DCU1_G7                0x184 0x000 ALT7 0x0
+#define VF610_PAD_PTB28__GPIO_98                0x188 0x000 ALT0 0x0
+#define VF610_PAD_PTB28__SAI0_TX_SYNC           0x188 0x000 ALT1 0x0
+#define VF610_PAD_PTB28__SRC_RCON23             0x188 0x000 ALT3 0x0
+#define VF610_PAD_PTB28__FB_RW_B                0x188 0x000 ALT4 0x0
+#define VF610_PAD_PTB28__DCU1_B6                0x188 0x000 ALT7 0x0
+#define VF610_PAD_PTC26__GPIO_99                0x18C 0x000 ALT0 0x0
+#define VF610_PAD_PTC26__SAI1_TX_BCLK           0x18C 0x000 ALT1 0x0
+#define VF610_PAD_PTC26__DSPI0_CS5              0x18C 0x000 ALT2 0x0
+#define VF610_PAD_PTC26__SRC_RCON24             0x18C 0x000 ALT3 0x0
+#define VF610_PAD_PTC26__FB_TA_B                0x18C 0x000 ALT4 0x0
+#define VF610_PAD_PTC26__NF_RB_B                0x18C 0x000 ALT5 0x0
+#define VF610_PAD_PTC26__DCU1_B7                0x18C 0x000 ALT7 0x0
+#define VF610_PAD_PTC27__GPIO_100               0x190 0x000 ALT0 0x0
+#define VF610_PAD_PTC27__SAI1_RX_BCLK           0x190 0x000 ALT1 0x0
+#define VF610_PAD_PTC27__DSPI0_CS4              0x190 0x000 ALT2 0x0
+#define VF610_PAD_PTC27__SRC_RCON25             0x190 0x000 ALT3 0x0
+#define VF610_PAD_PTC27__FB_BE3_B               0x190 0x000 ALT4 0x0
+#define VF610_PAD_PTC27__FB_CS3_B               0x190 0x000 ALT5 0x0
+#define VF610_PAD_PTC27__NF_ALE                 0x190 0x000 ALT6 0x0
+#define VF610_PAD_PTC27__DCU1_B2                0x190 0x000 ALT7 0x0
+#define VF610_PAD_PTC28__GPIO_101               0x194 0x000 ALT0 0x0
+#define VF610_PAD_PTC28__SAI1_RX_DATA           0x194 0x000 ALT1 0x0
+#define VF610_PAD_PTC28__DSPI0_CS3              0x194 0x000 ALT2 0x0
+#define VF610_PAD_PTC28__SRC_RCON26             0x194 0x000 ALT3 0x0
+#define VF610_PAD_PTC28__FB_BE2_B               0x194 0x000 ALT4 0x0
+#define VF610_PAD_PTC28__FB_CS2_B               0x194 0x000 ALT5 0x0
+#define VF610_PAD_PTC28__NF_CLE                 0x194 0x000 ALT6 0x0
+#define VF610_PAD_PTC28__DCU1_B3                0x194 0x000 ALT7 0x0
+#define VF610_PAD_PTC29__GPIO_102               0x198 0x000 ALT0 0x0
+#define VF610_PAD_PTC29__SAI1_TX_DATA           0x198 0x000 ALT1 0x0
+#define VF610_PAD_PTC29__DSPI0_CS2              0x198 0x000 ALT2 0x0
+#define VF610_PAD_PTC29__SRC_RCON27             0x198 0x000 ALT3 0x0
+#define VF610_PAD_PTC29__FB_BE1_B               0x198 0x000 ALT4 0x0
+#define VF610_PAD_PTC29__FB_MUXED_TSIZE1        0x198 0x000 ALT5 0x0
+#define VF610_PAD_PTC29__DCU1_B4                0x198 0x000 ALT7 0x0
+#define VF610_PAD_PTC30__GPIO_103               0x19C 0x000 ALT0 0x0
+#define VF610_PAD_PTC30__SAI1_RX_SYNC           0x19C 0x000 ALT1 0x0
+#define VF610_PAD_PTC30__DSPI1_CS2              0x19C 0x000 ALT2 0x0
+#define VF610_PAD_PTC30__SRC_RCON28             0x19C 0x000 ALT3 0x0
+#define VF610_PAD_PTC30__FB_MUXED_BE0_B         0x19C 0x000 ALT4 0x0
+#define VF610_PAD_PTC30__FB_TSIZ0               0x19C 0x000 ALT5 0x0
+#define VF610_PAD_PTC30__ADC0_SE5               0x19C 0x000 ALT6 0x0
+#define VF610_PAD_PTC30__DCU1_B5                0x19C 0x000 ALT7 0x0
+#define VF610_PAD_PTC31__GPIO_104               0x1A0 0x000 ALT0 0x0
+#define VF610_PAD_PTC31__SAI1_TX_SYNC           0x1A0 0x360 ALT1 0x1
+#define VF610_PAD_PTC31__SRC_RCON29             0x1A0 0x000 ALT3 0x0
+#define VF610_PAD_PTC31__ADC1_SE5               0x1A0 0x000 ALT6 0x0
+#define VF610_PAD_PTC31__DCU1_B6                0x1A0 0x000 ALT7 0x0
+#define VF610_PAD_PTE0__GPIO_105                0x1A4 0x000 ALT0 0x0
+#define VF610_PAD_PTE0__DCU0_HSYNC              0x1A4 0x000 ALT1 0x0
+#define VF610_PAD_PTE0__SRC_BMODE1              0x1A4 0x000 ALT2 0x0
+#define VF610_PAD_PTE0__LCD0                    0x1A4 0x000 ALT4 0x0
+#define VF610_PAD_PTE0__DEBUG_OUT29             0x1A4 0x000 ALT7 0x0
+#define VF610_PAD_PTE1__GPIO_106                0x1A8 0x000 ALT0 0x0
+#define VF610_PAD_PTE1__DCU0_VSYNC              0x1A8 0x000 ALT1 0x0
+#define VF610_PAD_PTE1__SRC_BMODE0              0x1A8 0x000 ALT2 0x0
+#define VF610_PAD_PTE1__LCD1                    0x1A8 0x000 ALT4 0x0
+#define VF610_PAD_PTE1__DEBUG_OUT30             0x1A8 0x000 ALT7 0x0
+#define VF610_PAD_PTE2__GPIO_107                0x1AC 0x000 ALT0 0x0
+#define VF610_PAD_PTE2__DCU0_PCLK               0x1AC 0x000 ALT1 0x0
+#define VF610_PAD_PTE2__LCD2                    0x1AC 0x000 ALT4 0x0
+#define VF610_PAD_PTE2__DEBUG_OUT31             0x1AC 0x000 ALT7 0x0
+#define VF610_PAD_PTE3__GPIO_108                0x1B0 0x000 ALT0 0x0
+#define VF610_PAD_PTE3__DCU0_TAG                0x1B0 0x000 ALT1 0x0
+#define VF610_PAD_PTE3__LCD3                    0x1B0 0x000 ALT4 0x0
+#define VF610_PAD_PTE3__DEBUG_OUT32             0x1B0 0x000 ALT7 0x0
+#define VF610_PAD_PTE4__GPIO_109                0x1B4 0x000 ALT0 0x0
+#define VF610_PAD_PTE4__DCU0_DE                 0x1B4 0x000 ALT1 0x0
+#define VF610_PAD_PTE4__LCD4                    0x1B4 0x000 ALT4 0x0
+#define VF610_PAD_PTE4__DEBUG_OUT33             0x1B4 0x000 ALT7 0x0
+#define VF610_PAD_PTE5__GPIO_110                0x1B8 0x000 ALT0 0x0
+#define VF610_PAD_PTE5__DCU0_R0                 0x1B8 0x000 ALT1 0x0
+#define VF610_PAD_PTE5__LCD5                    0x1B8 0x000 ALT4 0x0
+#define VF610_PAD_PTE5__DEBUG_OUT34             0x1B8 0x000 ALT7 0x0
+#define VF610_PAD_PTE6__GPIO_111                0x1BC 0x000 ALT0 0x0
+#define VF610_PAD_PTE6__DCU0_R1                 0x1BC 0x000 ALT1 0x0
+#define VF610_PAD_PTE6__LCD6                    0x1BC 0x000 ALT4 0x0
+#define VF610_PAD_PTE6__DEBUG_OUT35             0x1BC 0x000 ALT7 0x0
+#define VF610_PAD_PTE7__GPIO_112                0x1C0 0x000 ALT0 0x0
+#define VF610_PAD_PTE7__DCU0_R2                 0x1C0 0x000 ALT1 0x0
+#define VF610_PAD_PTE7__SRC_RCON0               0x1C0 0x000 ALT3 0x0
+#define VF610_PAD_PTE7__LCD7                    0x1C0 0x000 ALT4 0x0
+#define VF610_PAD_PTE7__DEBUG_OUT36             0x1C0 0x000 ALT7 0x0
+#define VF610_PAD_PTE8__GPIO_113                0x1C4 0x000 ALT0 0x0
+#define VF610_PAD_PTE8__DCU0_R3                 0x1C4 0x000 ALT1 0x0
+#define VF610_PAD_PTE8__SRC_RCON1               0x1C4 0x000 ALT3 0x0
+#define VF610_PAD_PTE8__LCD8                    0x1C4 0x000 ALT4 0x0
+#define VF610_PAD_PTE8__DEBUG_OUT37             0x1C4 0x000 ALT7 0x0
+#define VF610_PAD_PTE9__GPIO_114                0x1C8 0x000 ALT0 0x0
+#define VF610_PAD_PTE9__DCU0_R4                 0x1C8 0x000 ALT1 0x0
+#define VF610_PAD_PTE9__SRC_RCON2               0x1C8 0x000 ALT3 0x0
+#define VF610_PAD_PTE9__LCD9                    0x1C8 0x000 ALT4 0x0
+#define VF610_PAD_PTE9__DEBUG_OUT38             0x1C8 0x000 ALT7 0x0
+#define VF610_PAD_PTE10__GPIO_115               0x1CC 0x000 ALT0 0x0
+#define VF610_PAD_PTE10__DCU0_R5                0x1CC 0x000 ALT1 0x0
+#define VF610_PAD_PTE10__SRC_RCON3              0x1CC 0x000 ALT3 0x0
+#define VF610_PAD_PTE10__LCD10                  0x1CC 0x000 ALT4 0x0
+#define VF610_PAD_PTE10__DEBUG_OUT39            0x1CC 0x000 ALT7 0x0
+#define VF610_PAD_PTE11__GPIO_116               0x1D0 0x000 ALT0 0x0
+#define VF610_PAD_PTE11__DCU0_R6                0x1D0 0x000 ALT1 0x0
+#define VF610_PAD_PTE11__SRC_RCON4              0x1D0 0x000 ALT3 0x0
+#define VF610_PAD_PTE11__LCD11                  0x1D0 0x000 ALT4 0x0
+#define VF610_PAD_PTE11__DEBUG_OUT40            0x1D0 0x000 ALT7 0x0
+#define VF610_PAD_PTE12__GPIO_117               0x1D4 0x000 ALT0 0x0
+#define VF610_PAD_PTE12__DCU0_R7                0x1D4 0x000 ALT1 0x0
+#define VF610_PAD_PTE12__DSPI1_CS3              0x1D4 0x000 ALT2 0x0
+#define VF610_PAD_PTE12__SRC_RCON5              0x1D4 0x000 ALT3 0x0
+#define VF610_PAD_PTE12__LCD12                  0x1D4 0x000 ALT4 0x0
+#define VF610_PAD_PTE12__LPT_ALT0               0x1D4 0x000 ALT7 0x0
+#define VF610_PAD_PTE13__GPIO_118               0x1D8 0x000 ALT0 0x0
+#define VF610_PAD_PTE13__DCU0_G0                0x1D8 0x000 ALT1 0x0
+#define VF610_PAD_PTE13__LCD13                  0x1D8 0x000 ALT4 0x0
+#define VF610_PAD_PTE13__DEBUG_OUT41            0x1D8 0x000 ALT7 0x0
+#define VF610_PAD_PTE14__GPIO_119               0x1DC 0x000 ALT0 0x0
+#define VF610_PAD_PTE14__DCU0_G1                0x1DC 0x000 ALT1 0x0
+#define VF610_PAD_PTE14__LCD14                  0x1DC 0x000 ALT4 0x0
+#define VF610_PAD_PTE14__DEBUG_OUT42            0x1DC 0x000 ALT7 0x0
+#define VF610_PAD_PTE15__GPIO_120               0x1E0 0x000 ALT0 0x0
+#define VF610_PAD_PTE15__DCU0_G2                0x1E0 0x000 ALT1 0x0
+#define VF610_PAD_PTE15__SRC_RCON6              0x1E0 0x000 ALT3 0x0
+#define VF610_PAD_PTE15__LCD15                  0x1E0 0x000 ALT4 0x0
+#define VF610_PAD_PTE15__DEBUG_OUT43            0x1E0 0x000 ALT7 0x0
+#define VF610_PAD_PTE16__GPIO_121               0x1E4 0x000 ALT0 0x0
+#define VF610_PAD_PTE16__DCU0_G3                0x1E4 0x000 ALT1 0x0
+#define VF610_PAD_PTE16__SRC_RCON7              0x1E4 0x000 ALT3 0x0
+#define VF610_PAD_PTE16__LCD16                  0x1E4 0x000 ALT4 0x0
+#define VF610_PAD_PTE17__GPIO_122               0x1E8 0x000 ALT0 0x0
+#define VF610_PAD_PTE17__DCU0_G4                0x1E8 0x000 ALT1 0x0
+#define VF610_PAD_PTE17__SRC_RCON8              0x1E8 0x000 ALT3 0x0
+#define VF610_PAD_PTE17__LCD17                  0x1E8 0x000 ALT4 0x0
+#define VF610_PAD_PTE18__GPIO_123               0x1EC 0x000 ALT0 0x0
+#define VF610_PAD_PTE18__DCU0_G5                0x1EC 0x000 ALT1 0x0
+#define VF610_PAD_PTE18__SRC_RCON9              0x1EC 0x000 ALT3 0x0
+#define VF610_PAD_PTE18__LCD18                  0x1EC 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__GPIO_124               0x1F0 0x000 ALT0 0x0
+#define VF610_PAD_PTE19__DCU0_G6                0x1F0 0x000 ALT1 0x0
+#define VF610_PAD_PTE19__SRC_RCON10             0x1F0 0x000 ALT3 0x0
+#define VF610_PAD_PTE19__LCD19                  0x1F0 0x000 ALT4 0x0
+#define VF610_PAD_PTE19__I2C0_SCL               0x1F0 0x33C ALT5 0x3
+#define VF610_PAD_PTE20__GPIO_125               0x1F4 0x000 ALT0 0x0
+#define VF610_PAD_PTE20__DCU0_G7                0x1F4 0x000 ALT1 0x0
+#define VF610_PAD_PTE20__SRC_RCON11             0x1F4 0x000 ALT3 0x0
+#define VF610_PAD_PTE20__LCD20                  0x1F4 0x000 ALT4 0x0
+#define VF610_PAD_PTE20__I2C0_SDA               0x1F4 0x340 ALT5 0x3
+#define VF610_PAD_PTE20__EWM_IN                 0x1F4 0x000 ALT7 0x0
+#define VF610_PAD_PTE21__GPIO_126               0x1F8 0x000 ALT0 0x0
+#define VF610_PAD_PTE21__DCU0_B0                0x1F8 0x000 ALT1 0x0
+#define VF610_PAD_PTE21__LCD21                  0x1F8 0x000 ALT4 0x0
+#define VF610_PAD_PTE22__GPIO_127               0x1FC 0x000 ALT0 0x0
+#define VF610_PAD_PTE22__DCU0_B1                0x1FC 0x000 ALT1 0x0
+#define VF610_PAD_PTE22__LCD22                  0x1FC 0x000 ALT4 0x0
+#define VF610_PAD_PTE23__GPIO_128               0x200 0x000 ALT0 0x0
+#define VF610_PAD_PTE23__DCU0_B2                0x200 0x000 ALT1 0x0
+#define VF610_PAD_PTE23__SRC_RCON12             0x200 0x000 ALT3 0x0
+#define VF610_PAD_PTE23__LCD23                  0x200 0x000 ALT4 0x0
+#define VF610_PAD_PTE24__GPIO_129               0x204 0x000 ALT0 0x0
+#define VF610_PAD_PTE24__DCU0_B3                0x204 0x000 ALT1 0x0
+#define VF610_PAD_PTE24__SRC_RCON13             0x204 0x000 ALT3 0x0
+#define VF610_PAD_PTE24__LCD24                  0x204 0x000 ALT4 0x0
+#define VF610_PAD_PTE25__GPIO_130               0x208 0x000 ALT0 0x0
+#define VF610_PAD_PTE25__DCU0_B4                0x208 0x000 ALT1 0x0
+#define VF610_PAD_PTE25__SRC_RCON14             0x208 0x000 ALT3 0x0
+#define VF610_PAD_PTE25__LCD25                  0x208 0x000 ALT4 0x0
+#define VF610_PAD_PTE26__GPIO_131               0x20C 0x000 ALT0 0x0
+#define VF610_PAD_PTE26__DCU0_B5                0x20C 0x000 ALT1 0x0
+#define VF610_PAD_PTE26__SRC_RCON15             0x20C 0x000 ALT3 0x0
+#define VF610_PAD_PTE26__LCD26                  0x20C 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__GPIO_132               0x210 0x000 ALT0 0x0
+#define VF610_PAD_PTE27__DCU0_B6                0x210 0x000 ALT1 0x0
+#define VF610_PAD_PTE27__SRC_RCON16             0x210 0x000 ALT3 0x0
+#define VF610_PAD_PTE27__LCD27                  0x210 0x000 ALT4 0x0
+#define VF610_PAD_PTE27__I2C1_SCL               0x210 0x344 ALT5 0x3
+#define VF610_PAD_PTE28__GPIO_133               0x214 0x000 ALT0 0x0
+#define VF610_PAD_PTE28__DCU0_B7                0x214 0x000 ALT1 0x0
+#define VF610_PAD_PTE28__SRC_RCON17             0x214 0x000 ALT3 0x0
+#define VF610_PAD_PTE28__LCD28                  0x214 0x000 ALT4 0x0
+#define VF610_PAD_PTE28__I2C1_SDA               0x214 0x348 ALT5 0x3
+#define VF610_PAD_PTE28__EWM_OUT                0x214 0x000 ALT7 0x0
+#define VF610_PAD_PTA7__GPIO_134                0x218 0x000 ALT0 0x0
+#define VF610_PAD_PTA7__VIU_PIX_CLK             0x218 0x3AC ALT1 0x1
+
+#endif
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
new file mode 100644
index 000000000000..b3905f5bcaf9
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "vf610.dtsi"
+
+/ {
+        model = "VF610 Tower Board";
+        compatible = "fsl,vf610-twr", "fsl,vf610";
+
+        chosen {
+                bootargs = "console=ttyLP1,115200";
+        };
+
+        memory {
+                reg = <0x80000000 0x8000000>;
+        };
+
+        clocks {
+                audio_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24576000>;
+                };
+
+                enet_ext {
+                        compatible = "fixed-clock";
+                        clock-frequency = <50000000>;
+                };
+        };
+
+};
+
+&fec0 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec0_1>;
+        status = "okay";
+};
+
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1_1>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1_1>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
new file mode 100644
index 000000000000..e1eb7dadda80
--- /dev/null
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -0,0 +1,464 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include "skeleton.dtsi"
+#include "vf610-pinfunc.h"
+#include <dt-bindings/clock/vf610-clock.h>
+
+/ {
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a5";
+                        device_type = "cpu";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                sxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                fxosc {
+                        compatible = "fixed-clock";
+                        clock-frequency = <24000000>;
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                aips0: aips-bus@40000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&intc>;
+                        reg = <0x40000000 0x70000>;
+                        ranges;
+
+                        intc: interrupt-controller@40002000 {
+                                compatible = "arm,cortex-a9-gic";
+                                #interrupt-cells = <3>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                interrupt-controller;
+                                reg = <0x40003000 0x1000>,
+                                      <0x40002100 0x100>;
+                        };
+
+                        L2: l2-cache@40006000 {
+                                compatible = "arm,pl310-cache";
+                                reg = <0x40006000 0x1000>;
+                                cache-unified;
+                                cache-level = <2>;
+                                arm,data-latency = <1 1 1>;
+                                arm,tag-latency = <2 2 2>;
+                        };
+
+                        uart0: serial@40027000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40027000 0x1000>;
+                                interrupts = <0 61 0x00>;
+                                clocks = <&clks VF610_CLK_UART0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@40028000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40028000 0x1000>;
+                                interrupts = <0 62 0x04>;
+                                clocks = <&clks VF610_CLK_UART1>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart2: serial@40029000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x40029000 0x1000>;
+                                interrupts = <0 63 0x04>;
+                                clocks = <&clks VF610_CLK_UART2>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart3: serial@4002a000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x4002a000 0x1000>;
+                                interrupts = <0 64 0x04>;
+                                clocks = <&clks VF610_CLK_UART3>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        sai2: sai@40031000 {
+                                compatible = "fsl,vf610-sai";
+                                reg = <0x40031000 0x1000>;
+                                interrupts = <0 86 0x04>;
+                                clocks = <&clks VF610_CLK_SAI2>;
+                                clock-names = "sai";
+                                status = "disabled";
+                        };
+
+                        pit: pit@40037000 {
+                                compatible = "fsl,vf610-pit";
+                                reg = <0x40037000 0x1000>;
+                                interrupts = <0 39 0x04>;
+                                clocks = <&clks VF610_CLK_PIT>;
+                                clock-names = "pit";
+                        };
+
+                        wdog@4003e000 {
+                                compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
+                                reg = <0x4003e000 0x1000>;
+                                clocks = <&clks VF610_CLK_WDT>;
+                                clock-names = "wdog";
+                        };
+
+                        qspi0: quadspi@40044000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-qspi";
+                                reg = <0x40044000 0x1000>;
+                                interrupts = <0 24 0x04>;
+                                clocks = <&clks VF610_CLK_QSPI0_EN>,
+                                        <&clks VF610_CLK_QSPI0>;
+                                clock-names = "qspi_en", "qspi";
+                                status = "disabled";
+                        };
+
+                        iomuxc: iomuxc@40048000 {
+                                compatible = "fsl,vf610-iomuxc";
+                                reg = <0x40048000 0x1000>;
+                                #gpio-range-cells = <3>;
+
+                                /* functions and groups pins */
+
+                                dcu0 {
+                                        pinctrl_dcu0_1: dcu0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB8__GPIO_30         0x42
+                                                VF610_PAD_PTE0__DCU0_HSYNC      0x42
+                                                VF610_PAD_PTE1__DCU0_VSYNC      0x42
+                                                VF610_PAD_PTE2__DCU0_PCLK       0x42
+                                                VF610_PAD_PTE4__DCU0_DE         0x42
+                                                VF610_PAD_PTE5__DCU0_R0         0x42
+                                                VF610_PAD_PTE6__DCU0_R1         0x42
+                                                VF610_PAD_PTE7__DCU0_R2         0x42
+                                                VF610_PAD_PTE8__DCU0_R3         0x42
+                                                VF610_PAD_PTE9__DCU0_R4         0x42
+                                                VF610_PAD_PTE10__DCU0_R5        0x42
+                                                VF610_PAD_PTE11__DCU0_R6        0x42
+                                                VF610_PAD_PTE12__DCU0_R7        0x42
+                                                VF610_PAD_PTE13__DCU0_G0        0x42
+                                                VF610_PAD_PTE14__DCU0_G1        0x42
+                                                VF610_PAD_PTE15__DCU0_G2        0x42
+                                                VF610_PAD_PTE16__DCU0_G3        0x42
+                                                VF610_PAD_PTE17__DCU0_G4        0x42
+                                                VF610_PAD_PTE18__DCU0_G5        0x42
+                                                VF610_PAD_PTE19__DCU0_G6        0x42
+                                                VF610_PAD_PTE20__DCU0_G7        0x42
+                                                VF610_PAD_PTE21__DCU0_B0        0x42
+                                                VF610_PAD_PTE22__DCU0_B1        0x42
+                                                VF610_PAD_PTE23__DCU0_B2        0x42
+                                                VF610_PAD_PTE24__DCU0_B3        0x42
+                                                VF610_PAD_PTE25__DCU0_B4        0x42
+                                                VF610_PAD_PTE26__DCU0_B5        0x42
+                                                VF610_PAD_PTE27__DCU0_B6        0x42
+                                                VF610_PAD_PTE28__DCU0_B7        0x42
+                                                >;
+                                        };
+                                };
+
+                                dspi0 {
+                                        pinctrl_dspi0_1: dspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB19__DSPI0_CS0      0x1182
+                                                VF610_PAD_PTB20__DSPI0_SIN      0x1181
+                                                VF610_PAD_PTB21__DSPI0_SOUT     0x1182
+                                                VF610_PAD_PTB22__DSPI0_SCK      0x1182
+                                                >;
+                                        };
+                                };
+
+                                esdhc1 {
+                                        pinctrl_esdhc1_1: esdhc1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                                VF610_PAD_PTA7__GPIO_134        0x219d
+                                                >;
+                                        };
+                                };
+
+                                fec0 {
+                                        pinctrl_fec0_1: fec0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA6__RMII_CLKIN      0x30d1
+                                                VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d3
+                                                VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
+                                                VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
+                                                VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
+                                                VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
+                                                VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
+                                                VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
+                                                VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
+                                                VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
+                                                >;
+                                        };
+                                };
+
+                                fec1 {
+                                        pinctrl_fec1_1: fec1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                                                >;
+                                        };
+                                };
+
+                                i2c0 {
+                                        pinctrl_i2c0_1: i2c0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB14__I2C0_SCL       0x30d3
+                                                VF610_PAD_PTB15__I2C0_SDA       0x30d3
+                                                >;
+                                        };
+                                };
+
+                                pwm0 {
+                                        pinctrl_pwm0_1: pwm0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB0__FTM0_CH0        0x1582
+                                                VF610_PAD_PTB1__FTM0_CH1        0x1582
+                                                VF610_PAD_PTB2__FTM0_CH2        0x1582
+                                                VF610_PAD_PTB3__FTM0_CH3        0x1582
+                                                VF610_PAD_PTB6__FTM0_CH6        0x1582
+                                                VF610_PAD_PTB7__FTM0_CH7        0x1582
+                                                >;
+                                        };
+                                };
+
+                                qspi0 {
+                                        pinctrl_qspi0_1: qspi0grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTD0__QSPI0_A_QSCK    0x307b
+                                                VF610_PAD_PTD1__QSPI0_A_CS0     0x307f
+                                                VF610_PAD_PTD2__QSPI0_A_DATA3   0x3073
+                                                VF610_PAD_PTD3__QSPI0_A_DATA2   0x3073
+                                                VF610_PAD_PTD4__QSPI0_A_DATA1   0x3073
+                                                VF610_PAD_PTD5__QSPI0_A_DATA0   0x307b
+                                                VF610_PAD_PTD7__QSPI0_B_QSCK    0x307b
+                                                VF610_PAD_PTD8__QSPI0_B_CS0     0x307f
+                                                VF610_PAD_PTD9__QSPI0_B_DATA3   0x3073
+                                                VF610_PAD_PTD10__QSPI0_B_DATA2  0x3073
+                                                VF610_PAD_PTD11__QSPI0_B_DATA1  0x3073
+                                                VF610_PAD_PTD12__QSPI0_B_DATA0  0x307b
+                                                >;
+                                        };
+                                };
+
+                                sai2 {
+                                        pinctrl_sai2_1: sai2grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA16__SAI2_TX_BCLK   0x02ed
+                                                VF610_PAD_PTA18__SAI2_TX_DATA   0x02ee
+                                                VF610_PAD_PTA19__SAI2_TX_SYNC   0x02ed
+                                                VF610_PAD_PTA21__SAI2_RX_BCLK   0x02ed
+                                                VF610_PAD_PTA22__SAI2_RX_DATA   0x02ed
+                                                VF610_PAD_PTA23__SAI2_RX_SYNC   0x02ed
+                                                VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
+                                                >;
+                                        };
+                                };
+
+                                uart1 {
+                                        pinctrl_uart1_1: uart1grp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTB4__UART1_TX        0x21a2
+                                                VF610_PAD_PTB5__UART1_RX        0x21a1
+                                                >;
+                                        };
+                                };
+
+                                usbvbus {
+                                        pinctrl_usbvbus_1: usbvbusgrp_1 {
+                                                fsl,pins = <
+                                                VF610_PAD_PTA24__USB1_VBUS_EN   0x219c
+                                                VF610_PAD_PTA16__USB0_VBUS_EN   0x219c
+                                                >;
+                                        };
+                                };
+
+                        };
+
+                        gpio1: gpio@40049000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x40049000 0x1000 0x400ff000 0x40>;
+                                interrupts = <0 107 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 0 32>;
+                        };
+
+                        gpio2: gpio@4004a000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004a000 0x1000 0x400ff040 0x40>;
+                                interrupts = <0 108 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 32 32>;
+                        };
+
+                        gpio3: gpio@4004b000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004b000 0x1000 0x400ff080 0x40>;
+                                interrupts = <0 109 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 64 32>;
+                        };
+
+                        gpio4: gpio@4004c000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
+                                interrupts = <0 110 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 96 32>;
+                        };
+
+                        gpio5: gpio@4004d000 {
+                                compatible = "fsl,vf610-gpio";
+                                reg = <0x4004d000 0x1000 0x400ff100 0x40>;
+                                interrupts = <0 111 0x04>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                gpio-ranges = <&iomuxc 0 128 7>;
+                        };
+
+                        anatop@40050000 {
+                                compatible = "fsl,vf610-anatop";
+                                reg = <0x40050000 0x1000>;
+                        };
+
+                        i2c0: i2c@40066000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,vf610-i2c";
+                                reg = <0x40066000 0x1000>;
+                                interrupts =<0 71 0x04>;
+                                clocks = <&clks VF610_CLK_I2C0>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        clks: ccm@4006b000 {
+                                compatible = "fsl,vf610-ccm";
+                                reg = <0x4006b000 0x1000>;
+                                #clock-cells = <1>;
+                        };
+                };
+
+                aips1: aips-bus@40080000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x40080000 0x80000>;
+                        ranges;
+
+                        uart4: serial@400a9000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400a9000 0x1000>;
+                                interrupts = <0 65 0x04>;
+                                clocks = <&clks VF610_CLK_UART4>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        uart5: serial@400aa000 {
+                                compatible = "fsl,vf610-lpuart";
+                                reg = <0x400aa000 0x1000>;
+                                interrupts = <0 66 0x04>;
+                                clocks = <&clks VF610_CLK_UART5>;
+                                clock-names = "ipg";
+                                status = "disabled";
+                        };
+
+                        fec0: ethernet@400d0000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d0000 0x1000>;
+                                interrupts = <0 78 0x04>;
+                                clocks = <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+
+                        fec1: ethernet@400d1000 {
+                                compatible = "fsl,mvf600-fec";
+                                reg = <0x400d1000 0x1000>;
+                                interrupts = <0 79 0x04>;
+                                clocks = <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>,
+                                        <&clks VF610_CLK_ENET>;
+                                clock-names = "ipg", "ahb", "ptp";
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500-bv07.dts
index 877b33afa7ed..87f33310e2bc 100644
--- a/arch/arm/boot/dts/vt8500-bv07.dts
+++ b/arch/arm/boot/dts/vt8500-bv07.dts
@@ -30,3 +30,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/vt8500.dtsi b/arch/arm/boot/dts/vt8500.dtsi
index 4a4b96f6827e..51d0e912c8f5 100644
--- a/arch/arm/boot/dts/vt8500.dtsi
+++ b/arch/arm/boot/dts/vt8500.dtsi
@@ -11,6 +11,23 @@
 / {
         compatible = "via,vt8500";
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -111,32 +128,36 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8505-ref.dts b/arch/arm/boot/dts/wm8505-ref.dts
index edd2cec3d37f..e3e6b9eb09d0 100644
--- a/arch/arm/boot/dts/wm8505-ref.dts
+++ b/arch/arm/boot/dts/wm8505-ref.dts
@@ -30,3 +30,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index b2bf359e852f..a1a854b8a454 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -12,11 +12,24 @@
         compatible = "wm,wm8505";
 
         cpus {
-                cpu@0 {
-                        compatible = "arm,arm926ejs";
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
                 };
         };
 
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -68,6 +81,13 @@
                                         clock-frequency = <25000000>;
                                 };
 
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
                                 pllb: pllb {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-pll-clock";
@@ -75,6 +95,48 @@
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -163,46 +225,52 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
-                uart@d8370000 {
+                uart4: serial@d8370000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8370000 0x1040>;
                         interrupts = <31>;
                         clocks = <&clkuart4>;
+                        status = "disabled";
                 };
 
-                uart@d8380000 {
+                uart5: serial@d8380000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8380000 0x1040>;
                         interrupts = <30>;
                         clocks = <&clkuart5>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8650-mid.dts b/arch/arm/boot/dts/wm8650-mid.dts
index 61671a0d9ede..dd0d1b602388 100644
--- a/arch/arm/boot/dts/wm8650-mid.dts
+++ b/arch/arm/boot/dts/wm8650-mid.dts
@@ -32,3 +32,6 @@
         };
 };
 
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8650.dtsi b/arch/arm/boot/dts/wm8650.dtsi
index dd8464eeb40d..7525982262ac 100644
--- a/arch/arm/boot/dts/wm8650.dtsi
+++ b/arch/arm/boot/dts/wm8650.dtsi
@@ -11,6 +11,21 @@
 / {
         compatible = "wm,wm8650";
 
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm926ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
         soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -77,6 +92,55 @@
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20c>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8650-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -93,14 +157,7 @@
                                         enable-bit = <2>;
                                 };
 
-                                arm: arm {
-                                        #clock-cells = <0>;
-                                        compatible = "via,vt8500-device-clock";
-                                        clocks = <&plla>;
-                                        divisor-reg = <0x300>;
-                                };
-
-                                sdhc: sdhc {
+                                clksdhc: sdhc {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
                                         clocks = <&pllb>;
@@ -140,18 +197,20 @@
                         reg = <0xd8050400 0x100>;
                 };
 
-                uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/wm8750-apc8750.dts b/arch/arm/boot/dts/wm8750-apc8750.dts
new file mode 100644
index 000000000000..37e4a408bf39
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750-apc8750.dts
@@ -0,0 +1,30 @@
+/*
+ * wm8750-apc8750.dts
+ *  - Device tree file for VIA APC8750
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/dts-v1/;
+/include/ "wm8750.dtsi"
+
+/ {
+        model = "VIA APC8750";
+};
+
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c>;
+
+        i2c: i2c {
+                wm,pins = <168 169 170 171>;
+                wm,function = <2>;      /* alt */
+                wm,pull = <2>;  /* pull-up */
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8750.dtsi b/arch/arm/boot/dts/wm8750.dtsi
new file mode 100644
index 000000000000..557a9c2ace49
--- /dev/null
+++ b/arch/arm/boot/dts/wm8750.dtsi
@@ -0,0 +1,347 @@
+/*
+ * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * Licensed under GPLv2 or later
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "wm,wm8750";
+
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm1176ej-s";
+                };
+        };
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+                serial2 = &uart2;
+                serial3 = &uart3;
+                serial4 = &uart4;
+                serial5 = &uart5;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                ranges;
+                interrupt-parent = <&intc0>;
+
+                intc0: interrupt-controller@d8140000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        reg = <0xd8140000 0x10000>;
+                        #interrupt-cells = <1>;
+                };
+
+                /* Secondary IC cascaded to intc0 */
+                intc1: interrupt-controller@d8150000 {
+                        compatible = "via,vt8500-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        reg = <0xD8150000 0x10000>;
+                        interrupts = <56 57 58 59 60 61 62 63>;
+                };
+
+                pinctrl: pinctrl@d8110000 {
+                        compatible = "wm,wm8750-pinctrl";
+                        reg = <0xd8110000 0x10000>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                pmc@d8130000 {
+                        compatible = "via,vt8500-pmc";
+                        reg = <0xd8130000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ref24: ref24M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <24000000>;
+                                };
+
+                                ref25: ref25M {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <25000000>;
+                                };
+
+                                plla: plla {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x200>;
+                                };
+
+                                pllb: pllb {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x204>;
+                                };
+
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x20C>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8750-pll-clock";
+                                        clocks = <&ref25>;
+                                        reg = <0x210>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
+                                clkuart0: uart0 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <24>;
+                                };
+
+                                clkuart1: uart1 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <25>;
+                                };
+
+                                clkuart2: uart2 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <26>;
+                                };
+
+                                clkuart3: uart3 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <27>;
+                                };
+
+                                clkuart4: uart4 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <28>;
+                                };
+
+                                clkuart5: uart5 {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&ref24>;
+                                        enable-reg = <0x254>;
+                                        enable-bit = <29>;
+                                };
+
+                                clkpwm: pwm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x350>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <17>;
+                                };
+
+                                clksdhc: sdhc {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x330>;
+                                        divisor-mask = <0x3f>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <0>;
+                                };
+
+                                clki2c0: i2c0clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A0>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <8>;
+                                };
+
+                                clki2c1: i2c1clk {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x3A4>;
+                                        enable-reg = <0x250>;
+                                        enable-bit = <9>;
+                                };
+                        };
+                };
+
+                pwm: pwm@d8220000 {
+                        #pwm-cells = <3>;
+                        compatible = "via,vt8500-pwm";
+                        reg = <0xd8220000 0x100>;
+                        clocks = <&clkpwm>;
+                };
+
+                timer@d8130100 {
+                        compatible = "via,vt8500-timer";
+                        reg = <0xd8130100 0x28>;
+                        interrupts = <36>;
+                };
+
+                ehci@d8007900 {
+                        compatible = "via,vt8500-ehci";
+                        reg = <0xd8007900 0x200>;
+                        interrupts = <26>;
+                };
+
+                uhci@d8007b00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8007b00 0x200>;
+                        interrupts = <26>;
+                };
+
+                uhci@d8008d00 {
+                        compatible = "platform-uhci";
+                        reg = <0xd8008d00 0x200>;
+                        interrupts = <26>;
+                };
+
+                uart0: serial@d8200000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8200000 0x1040>;
+                        interrupts = <32>;
+                        clocks = <&clkuart0>;
+                        status = "disabled";
+                };
+
+                uart1: serial@d82b0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82b0000 0x1040>;
+                        interrupts = <33>;
+                        clocks = <&clkuart1>;
+                        status = "disabled";
+                };
+
+                uart2: serial@d8210000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8210000 0x1040>;
+                        interrupts = <47>;
+                        clocks = <&clkuart2>;
+                        status = "disabled";
+                };
+
+                uart3: serial@d82c0000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd82c0000 0x1040>;
+                        interrupts = <50>;
+                        clocks = <&clkuart3>;
+                        status = "disabled";
+                };
+
+                uart4: serial@d8370000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8370000 0x1040>;
+                        interrupts = <30>;
+                        clocks = <&clkuart4>;
+                        status = "disabled";
+                };
+
+                uart5: serial@d8380000 {
+                        compatible = "via,vt8500-uart";
+                        reg = <0xd8380000 0x1040>;
+                        interrupts = <43>;
+                        clocks = <&clkuart5>;
+                        status = "disabled";
+                };
+
+                rtc@d8100000 {
+                        compatible = "via,vt8500-rtc";
+                        reg = <0xd8100000 0x10000>;
+                        interrupts = <48>;
+                };
+
+                sdhc@d800a000 {
+                        compatible = "wm,wm8505-sdhc";
+                        reg = <0xd800a000 0x1000>;
+                        interrupts = <20 21>;
+                        clocks = <&clksdhc>;
+                        bus-width = <4>;
+                        sdon-inverted;
+                };
+
+                i2c_0: i2c@d8280000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8280000 0x1000>;
+                        interrupts = <19>;
+                        clocks = <&clki2c0>;
+                        clock-frequency = <400000>;
+                };
+
+                i2c_1: i2c@d8320000 {
+                        compatible = "wm,wm8505-i2c";
+                        reg = <0xd8320000 0x1000>;
+                        interrupts = <18>;
+                        clocks = <&clki2c1>;
+                        clock-frequency = <400000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/wm8850-w70v2.dts b/arch/arm/boot/dts/wm8850-w70v2.dts
index 32d22532cd6c..90e913fb64be 100644
--- a/arch/arm/boot/dts/wm8850-w70v2.dts
+++ b/arch/arm/boot/dts/wm8850-w70v2.dts
@@ -41,3 +41,7 @@
                 };
         };
 };
+
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/wm8850.dtsi b/arch/arm/boot/dts/wm8850.dtsi
index fc790d0aee66..d98386dd2882 100644
--- a/arch/arm/boot/dts/wm8850.dtsi
+++ b/arch/arm/boot/dts/wm8850.dtsi
@@ -11,6 +11,17 @@
 / {
         compatible = "wm,wm8850";
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0x0>;
+                };
+        };
+
         aliases {
                 serial0 = &uart0;
                 serial1 = &uart1;
@@ -72,18 +83,81 @@
 
                                 plla: plla {
                                         #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
-                                        clocks = <&ref25>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
                                         reg = <0x200>;
                                 };
 
                                 pllb: pllb {
                                         #clock-cells = <0>;
-                                        compatible = "wm,wm8750-pll-clock";
-                                        clocks = <&ref25>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
                                         reg = <0x204>;
                                 };
 
+                                pllc: pllc {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x208>;
+                                };
+
+                                plld: plld {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x20c>;
+                                };
+
+                                plle: plle {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x210>;
+                                };
+
+                                pllf: pllf {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x214>;
+                                };
+
+                                pllg: pllg {
+                                        #clock-cells = <0>;
+                                        compatible = "wm,wm8850-pll-clock";
+                                        clocks = <&ref24>;
+                                        reg = <0x218>;
+                                };
+
+                                clkarm: arm {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plla>;
+                                        divisor-reg = <0x300>;
+                                };
+
+                                clkahb: ahb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x304>;
+                                };
+
+                                clkapb: apb {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&pllb>;
+                                        divisor-reg = <0x320>;
+                                };
+
+                                clkddr: ddr {
+                                        #clock-cells = <0>;
+                                        compatible = "via,vt8500-device-clock";
+                                        clocks = <&plld>;
+                                        divisor-reg = <0x310>;
+                                };
+
                                 clkuart0: uart0 {
                                         #clock-cells = <0>;
                                         compatible = "via,vt8500-device-clock";
@@ -178,32 +252,36 @@
                         interrupts = <26>;
                 };
 
-                uart0: uart@d8200000 {
+                uart0: serial@d8200000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8200000 0x1040>;
                         interrupts = <32>;
                         clocks = <&clkuart0>;
+                        status = "disabled";
                 };
 
-                uart1: uart@d82b0000 {
+                uart1: serial@d82b0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82b0000 0x1040>;
                         interrupts = <33>;
                         clocks = <&clkuart1>;
+                        status = "disabled";
                 };
 
-                uart2: uart@d8210000 {
+                uart2: serial@d8210000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd8210000 0x1040>;
                         interrupts = <47>;
                         clocks = <&clkuart2>;
+                        status = "disabled";
                 };
 
-                uart3: uart@d82c0000 {
+                uart3: serial@d82c0000 {
                         compatible = "via,vt8500-uart";
                         reg = <0xd82c0000 0x1040>;
                         interrupts = <50>;
                         clocks = <&clkuart3>;
+                        status = "disabled";
                 };
 
                 rtc@d8100000 {
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 14fb2e609bab..6f54a64850eb 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -49,16 +49,20 @@
 
                 uart0: uart@e0000000 {
                         compatible = "xlnx,xuartps";
+                        status = "disabled";
+                        clocks = <&clkc 23>, <&clkc 40>;
+                        clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0000000 0x1000>;
                         interrupts = <0 27 4>;
-                        clocks = <&uart_clk 0>;
                 };
 
                 uart1: uart@e0001000 {
                         compatible = "xlnx,xuartps";
+                        status = "disabled";
+                        clocks = <&clkc 24>, <&clkc 41>;
+                        clock-names = "ref_clk", "aper_clk";
                         reg = <0xE0001000 0x1000>;
                         interrupts = <0 50 4>;
-                        clocks = <&uart_clk 1>;
                 };
 
                 slcr: slcr@f8000000 {
@@ -69,50 +73,21 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
-                                ps_clk: ps_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "fixed-clock";
-                                        /* clock-frequency set in board-specific file */
-                                        clock-output-names = "ps_clk";
-                                };
-                                armpll: armpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x100 0x110>;
-                                        clock-output-names = "armpll";
-                                };
-                                ddrpll: ddrpll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x104 0x114>;
-                                        clock-output-names = "ddrpll";
-                                };
-                                iopll: iopll {
-                                        #clock-cells = <0>;
-                                        compatible = "xlnx,zynq-pll";
-                                        clocks = <&ps_clk>;
-                                        reg = <0x108 0x118>;
-                                        clock-output-names = "iopll";
-                                };
-                                uart_clk: uart_clk {
-                                        #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-periph-clock";
-                                        clocks = <&iopll &armpll &ddrpll>;
-                                        reg = <0x154>;
-                                        clock-output-names = "uart0_ref_clk",
-                                                             "uart1_ref_clk";
-                                };
-                                cpu_clk: cpu_clk {
+                                clkc: clkc {
                                         #clock-cells = <1>;
-                                        compatible = "xlnx,zynq-cpu-clock";
-                                        clocks = <&iopll &armpll &ddrpll>;
-                                        reg = <0x120 0x1C4>;
-                                        clock-output-names = "cpu_6x4x",
-                                                             "cpu_3x2x",
-                                                             "cpu_2x",
-                                                             "cpu_1x";
+                                        compatible = "xlnx,ps7-clkc";
+                                        ps-clk-frequency = <33333333>;
+                                        clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
+                                                        "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
+                                                        "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
+                                                        "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
+                                                        "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
+                                                        "dma", "usb0_aper", "usb1_aper", "gem0_aper",
+                                                        "gem1_aper", "sdio0_aper", "sdio1_aper",
+                                                        "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
+                                                        "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
+                                                        "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
+                                                        "dbg_trc", "dbg_apb";
                                 };
                         };
                 };
@@ -121,9 +96,8 @@
                         interrupt-parent = <&intc>;
                         interrupts = < 0 10 4 0 11 4 0 12 4 >;
                         compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                         reg = <0xF8001000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                         clock-ranges;
                 };
 
@@ -131,9 +105,8 @@
                         interrupt-parent = <&intc>;
                         interrupts = < 0 37 4 0 38 4 0 39 4 >;
                         compatible = "cdns,ttc";
+                        clocks = <&clkc 6>;
                         reg = <0xF8002000 0x1000>;
-                        clocks = <&cpu_clk 3>;
-                        clock-names = "cpu_1x";
                         clock-ranges;
                 };
                 scutimer: scutimer@f8f00600 {
@@ -141,7 +114,7 @@
                         interrupts = < 1 13 0x301 >;
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = < 0xf8f00600 0x20 >;
-                        clocks = <&cpu_clk 1>;
+                        clocks = <&clkc 4>;
                 } ;
         };
 };
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5b0265..21aea99a067b 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -24,11 +24,11 @@
         };
 
         chosen {
-                bootargs = "console=ttyPS1,115200 earlyprintk";
+                bootargs = "console=ttyPS0,115200 earlyprintk";
         };
 
 };
 
-&ps_clk {
-        clock-frequency = <33333330>;
+&uart1 {
+        status = "okay";
 };
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
new file mode 100644
index 000000000000..79009e0b74b9
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq ZC706 Development Board";
+        compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts
new file mode 100644
index 000000000000..d6acf2b1cdf4
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-zed.dts
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2012 National Instruments Corp.
+ *  Copyright (C) 2013 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+        model = "Zynq Zed Development Board";
+        compatible = "xlnx,zynq-7000";
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyPS0,115200 earlyprintk";
+        };
+
+};
+
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 9353184d730d..c3a4e9ceba34 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -17,3 +17,6 @@ config SHARP_PARAM
 
 config SHARP_SCOOP
         bool
+
+config TI_PRIV_EDMA
+        bool
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 48434cbe3e89..8c60f473e976 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_ARM_TIMER_SP804)	+= timer-sp.o
 obj-$(CONFIG_MCPM)              += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
 AFLAGS_mcpm_head.o              := -march=armv7-a
 AFLAGS_vlock.o                  := -march=armv7-a
+obj-$(CONFIG_TI_PRIV_EDMA)      += edma.o
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/common/edma.c
index 45b7c71d9cc1..a432e6c1dac1 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/common/edma.c
@@ -17,6 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
+#include <linux/err.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -24,8 +25,15 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/edma.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_dma.h>
+#include <linux/of_irq.h>
+#include <linux/pm_runtime.h>
 
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 /* Offsets matching "struct edmacc_param" */
 #define PARM_OPT                0x00
@@ -494,26 +502,6 @@ static irqreturn_t dma_ccerr_handler(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-/******************************************************************************
- *
- * Transfer controller error interrupt handlers
- *
- *****************************************************************************/
-
-#define tc_errs_handled false   /* disabled as long as they're NOPs */
-
-static irqreturn_t dma_tc0err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc0err_handler\n");
-        return IRQ_HANDLED;
-}
-
-static irqreturn_t dma_tc1err_handler(int irq, void *data)
-{
-        dev_dbg(data, "dma_tc1err_handler\n");
-        return IRQ_HANDLED;
-}
-
 static int reserve_contiguous_slots(int ctlr, unsigned int id,
                                      unsigned int num_slots,
                                      unsigned int start_slot)
@@ -1388,32 +1376,236 @@ void edma_clear_event(unsigned channel)
 }
 EXPORT_SYMBOL(edma_clear_event);
 
-/*-----------------------------------------------------------------------*/
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
+
+static int edma_of_read_u32_to_s16_array(const struct device_node *np,
+                                         const char *propname, s16 *out_values,
+                                         size_t sz)
+{
+        int ret;
+
+        ret = of_property_read_u16_array(np, propname, out_values, sz);
+        if (ret)
+                return ret;
+
+        /* Terminate it */
+        *out_values++ = -1;
+        *out_values++ = -1;
+
+        return 0;
+}
+
+static int edma_xbar_event_map(struct device *dev,
+                               struct device_node *node,
+                               struct edma_soc_info *pdata, int len)
+{
+        int ret, i;
+        struct resource res;
+        void __iomem *xbar;
+        const s16 (*xbar_chans)[2];
+        u32 shift, offset, mux;
+
+        xbar_chans = devm_kzalloc(dev,
+                                  len/sizeof(s16) + 2*sizeof(s16),
+                                  GFP_KERNEL);
+        if (!xbar_chans)
+                return -ENOMEM;
+
+        ret = of_address_to_resource(node, 1, &res);
+        if (ret)
+                return -EIO;
+
+        xbar = devm_ioremap(dev, res.start, resource_size(&res));
+        if (!xbar)
+                return -ENOMEM;
+
+        ret = edma_of_read_u32_to_s16_array(node,
+                                            "ti,edma-xbar-event-map",
+                                            (s16 *)xbar_chans,
+                                            len/sizeof(u32));
+        if (ret)
+                return -EIO;
+
+        for (i = 0; xbar_chans[i][0] != -1; i++) {
+                shift = (xbar_chans[i][1] & 0x03) << 3;
+                offset = xbar_chans[i][1] & 0xfffffffc;
+                mux = readl(xbar + offset);
+                mux &= ~(0xff << shift);
+                mux |= xbar_chans[i][0] << shift;
+                writel(mux, (xbar + offset));
+        }
+
+        pdata->xbar_chans = xbar_chans;
+
+        return 0;
+}
+
+static int edma_of_parse_dt(struct device *dev,
+                            struct device_node *node,
+                            struct edma_soc_info *pdata)
+{
+        int ret = 0, i;
+        u32 value;
+        struct property *prop;
+        size_t sz;
+        struct edma_rsv_info *rsv_info;
+        s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
+
+        memset(pdata, 0, sizeof(struct edma_soc_info));
+
+        ret = of_property_read_u32(node, "dma-channels", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_channel = value;
+
+        ret = of_property_read_u32(node, "ti,edma-regions", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_region = value;
+
+        ret = of_property_read_u32(node, "ti,edma-slots", &value);
+        if (ret < 0)
+                return ret;
+        pdata->n_slot = value;
+
+        pdata->n_cc = 1;
+
+        rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
+        if (!rsv_info)
+                return -ENOMEM;
+        pdata->rsv = rsv_info;
+
+        queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
+        if (!queue_tc_map)
+                return -ENOMEM;
+
+        for (i = 0; i < 3; i++) {
+                queue_tc_map[i][0] = i;
+                queue_tc_map[i][1] = i;
+        }
+        queue_tc_map[i][0] = -1;
+        queue_tc_map[i][1] = -1;
+
+        pdata->queue_tc_mapping = queue_tc_map;
+
+        queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
+        if (!queue_priority_map)
+                return -ENOMEM;
+
+        for (i = 0; i < 3; i++) {
+                queue_priority_map[i][0] = i;
+                queue_priority_map[i][1] = i;
+        }
+        queue_priority_map[i][0] = -1;
+        queue_priority_map[i][1] = -1;
+
+        pdata->queue_priority_mapping = queue_priority_map;
+
+        pdata->default_queue = 0;
+
+        prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
+        if (prop)
+                ret = edma_xbar_event_map(dev, node, pdata, sz);
+
+        return ret;
+}
+
+static struct of_dma_filter_info edma_filter_info = {
+        .filter_fn = edma_filter_fn,
+};
+
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
+                                                      struct device_node *node)
+{
+        struct edma_soc_info *info;
+        int ret;
+
+        info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
+        if (!info)
+                return ERR_PTR(-ENOMEM);
 
-static int __init edma_probe(struct platform_device *pdev)
+        ret = edma_of_parse_dt(dev, node, info);
+        if (ret)
+                return ERR_PTR(ret);
+
+        dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+        of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
+                                   &edma_filter_info);
+
+        return info;
+}
+#else
+static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
+                                                      struct device_node *node)
+{
+        return ERR_PTR(-ENOSYS);
+}
+#endif
+
+static int edma_probe(struct platform_device *pdev)
 {
         struct edma_soc_info    **info = pdev->dev.platform_data;
-        const s8                (*queue_priority_mapping)[2];
-        const s8                (*queue_tc_mapping)[2];
+        struct edma_soc_info    *ninfo[EDMA_MAX_CC] = {NULL};
+        s8              (*queue_priority_mapping)[2];
+        s8              (*queue_tc_mapping)[2];
         int                     i, j, off, ln, found = 0;
         int                     status = -1;
         const s16               (*rsv_chans)[2];
         const s16               (*rsv_slots)[2];
+        const s16               (*xbar_chans)[2];
         int                     irq[EDMA_MAX_CC] = {0, 0};
         int                     err_irq[EDMA_MAX_CC] = {0, 0};
         struct resource         *r[EDMA_MAX_CC] = {NULL};
-        resource_size_t         len[EDMA_MAX_CC];
+        struct resource         res[EDMA_MAX_CC];
         char                    res_name[10];
         char                    irq_name[10];
+        struct device_node      *node = pdev->dev.of_node;
+        struct device           *dev = &pdev->dev;
+        int                     ret;
+
+        if (node) {
+                /* Check if this is a second instance registered */
+                if (arch_num_cc) {
+                        dev_err(dev, "only one EDMA instance is supported via DT\n");
+                        return -ENODEV;
+                }
+
+                ninfo[0] = edma_setup_info_from_dt(dev, node);
+                if (IS_ERR(ninfo[0])) {
+                        dev_err(dev, "failed to get DT data\n");
+                        return PTR_ERR(ninfo[0]);
+                }
+
+                info = ninfo;
+        }
 
         if (!info)
                 return -ENODEV;
 
+        pm_runtime_enable(dev);
+        ret = pm_runtime_get_sync(dev);
+        if (ret < 0) {
+                dev_err(dev, "pm_runtime_get_sync() failed\n");
+                return ret;
+        }
+
         for (j = 0; j < EDMA_MAX_CC; j++) {
-                sprintf(res_name, "edma_cc%d", j);
-                r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+                if (!info[j]) {
+                        if (!found)
+                                return -ENODEV;
+                        break;
+                }
+                if (node) {
+                        ret = of_address_to_resource(node, j, &res[j]);
+                        if (!ret)
+                                r[j] = &res[j];
+                } else {
+                        sprintf(res_name, "edma_cc%d", j);
+                        r[j] = platform_get_resource_byname(pdev,
+                                                IORESOURCE_MEM,
                                                 res_name);
-                if (!r[j] || !info[j]) {
+                }
+                if (!r[j]) {
                         if (found)
                                 break;
                         else
@@ -1422,26 +1614,14 @@ static int __init edma_probe(struct platform_device *pdev)
                         found = 1;
                 }
 
-                len[j] = resource_size(r[j]);
-
-                r[j] = request_mem_region(r[j]->start, len[j],
-                        dev_name(&pdev->dev));
-                if (!r[j]) {
-                        status = -EBUSY;
-                        goto fail1;
-                }
-
-                edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
-                if (!edmacc_regs_base[j]) {
-                        status = -EBUSY;
-                        goto fail1;
-                }
+                edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]);
+                if (IS_ERR(edmacc_regs_base[j]))
+                        return PTR_ERR(edmacc_regs_base[j]);
 
-                edma_cc[j] = kzalloc(sizeof(struct edma), GFP_KERNEL);
-                if (!edma_cc[j]) {
-                        status = -ENOMEM;
-                        goto fail1;
-                }
+                edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma),
+                                          GFP_KERNEL);
+                if (!edma_cc[j])
+                        return -ENOMEM;
 
                 edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
                                                         EDMA_MAX_DMACH);
@@ -1472,7 +1652,7 @@ static int __init edma_probe(struct platform_device *pdev)
                                         off = rsv_chans[i][0];
                                         ln = rsv_chans[i][1];
                                         clear_bits(off, ln,
-                                                edma_cc[j]->edma_unused);
+                                                  edma_cc[j]->edma_unused);
                                 }
                         }
 
@@ -1488,26 +1668,48 @@ static int __init edma_probe(struct platform_device *pdev)
                         }
                 }
 
-                sprintf(irq_name, "edma%d", j);
-                irq[j] = platform_get_irq_byname(pdev, irq_name);
+                /* Clear the xbar mapped channels in unused list */
+                xbar_chans = info[j]->xbar_chans;
+                if (xbar_chans) {
+                        for (i = 0; xbar_chans[i][1] != -1; i++) {
+                                off = xbar_chans[i][1];
+                                clear_bits(off, 1,
+                                           edma_cc[j]->edma_unused);
+                        }
+                }
+
+                if (node) {
+                        irq[j] = irq_of_parse_and_map(node, 0);
+                } else {
+                        sprintf(irq_name, "edma%d", j);
+                        irq[j] = platform_get_irq_byname(pdev, irq_name);
+                }
                 edma_cc[j]->irq_res_start = irq[j];
-                status = request_irq(irq[j], dma_irq_handler, 0, "edma",
-                                        &pdev->dev);
+                status = devm_request_irq(&pdev->dev, irq[j],
+                                          dma_irq_handler, 0, "edma",
+                                          &pdev->dev);
                 if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        dev_dbg(&pdev->dev,
+                                "devm_request_irq %d failed --> %d\n",
                                 irq[j], status);
-                        goto fail;
+                        return status;
                 }
 
-                sprintf(irq_name, "edma%d_err", j);
-                err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+                if (node) {
+                        err_irq[j] = irq_of_parse_and_map(node, 2);
+                } else {
+                        sprintf(irq_name, "edma%d_err", j);
+                        err_irq[j] = platform_get_irq_byname(pdev, irq_name);
+                }
                 edma_cc[j]->irq_res_end = err_irq[j];
-                status = request_irq(err_irq[j], dma_ccerr_handler, 0,
-                                        "edma_error", &pdev->dev);
+                status = devm_request_irq(&pdev->dev, err_irq[j],
+                                          dma_ccerr_handler, 0,
+                                          "edma_error", &pdev->dev);
                 if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
+                        dev_dbg(&pdev->dev,
+                                "devm_request_irq %d failed --> %d\n",
                                 err_irq[j], status);
-                        goto fail;
+                        return status;
                 }
 
                 for (i = 0; i < edma_cc[j]->num_channels; i++)
@@ -1541,46 +1743,20 @@ static int __init edma_probe(struct platform_device *pdev)
                 arch_num_cc++;
         }
 
-        if (tc_errs_handled) {
-                status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
-                                        "edma_tc0", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
-                                IRQ_TCERRINT0, status);
-                        return status;
-                }
-                status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
-                                        "edma_tc1", &pdev->dev);
-                if (status < 0) {
-                        dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
-                                IRQ_TCERRINT, status);
-                        return status;
-                }
-        }
-
         return 0;
-
-fail:
-        for (i = 0; i < EDMA_MAX_CC; i++) {
-                if (err_irq[i])
-                        free_irq(err_irq[i], &pdev->dev);
-                if (irq[i])
-                        free_irq(irq[i], &pdev->dev);
-        }
-fail1:
-        for (i = 0; i < EDMA_MAX_CC; i++) {
-                if (r[i])
-                        release_mem_region(r[i]->start, len[i]);
-                if (edmacc_regs_base[i])
-                        iounmap(edmacc_regs_base[i]);
-                kfree(edma_cc[i]);
-        }
-        return status;
 }
 
+static const struct of_device_id edma_of_ids[] = {
+        { .compatible = "ti,edma3", },
+        {}
+};
 
 static struct platform_driver edma_driver = {
-        .driver.name    = "edma",
+        .driver = {
+                .name   = "edma",
+                .of_match_table = edma_of_ids,
+        },
+        .probe = edma_probe,
 };
 
 static int __init edma_init(void)
diff --git a/arch/arm/common/mcpm_head.S b/arch/arm/common/mcpm_head.S
index 8178705c4b24..80f033614a1f 100644
--- a/arch/arm/common/mcpm_head.S
+++ b/arch/arm/common/mcpm_head.S
@@ -32,11 +32,11 @@
 1901:   adr     r0, 1902b
         bl      printascii
         mov     r0, r9
-        bl      printhex8
+        bl      printhex2
         adr     r0, 1903b
         bl      printascii
         mov     r0, r10
-        bl      printhex8
+        bl      printhex2
         adr     r0, 1904b
         bl      printascii
 #endif
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
index 3caed0db6986..510e5b13aa2e 100644
--- a/arch/arm/common/mcpm_platsmp.c
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -19,10 +19,6 @@
 #include <asm/smp.h>
 #include <asm/smp_plat.h>
 
-static void __init simple_smp_init_cpus(void)
-{
-}
-
 static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         unsigned int mpidr, pcpu, pcluster, ret;
@@ -74,7 +70,6 @@ static void mcpm_cpu_die(unsigned int cpu)
 #endif
 
 static struct smp_operations __initdata mcpm_smp_ops = {
-        .smp_init_cpus          = simple_smp_init_cpus,
         .smp_boot_secondary     = mcpm_boot_secondary,
         .smp_secondary_init     = mcpm_secondary_init,
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
deleted file mode 100644
index 66894f736d04..000000000000
--- a/arch/arm/configs/ap4evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_SH7372=y
-CONFIG_MACH_AP4EVB=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200"
-CONFIG_KEXEC=y
-CONFIG_PM=y
-# CONFIG_SUSPEND is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_FTRACE is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index 0f2d80da7378..fae939d3d7f0 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -86,7 +86,7 @@ CONFIG_TOUCHSCREEN_ST1232=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 047f2a415309..75fd842d4071 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -25,8 +24,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -42,6 +39,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -51,7 +51,8 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-# CONFIG_WIRELESS is not set
+CONFIG_CFG80211=y
+CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -72,7 +73,6 @@ CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_93CX6=m
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -81,7 +81,6 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 # CONFIG_NET_VENDOR_FARADAY is not set
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
@@ -92,7 +91,23 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_DAVICOM_PHY=y
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_RTLWIFI=m
+# CONFIG_RTLWIFI_DEBUG is not set
+CONFIG_RTL8192CU=m
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
@@ -112,13 +127,11 @@ CONFIG_I2C=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_PINCTRL_AT91=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SSB=m
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
@@ -132,11 +145,8 @@ CONFIG_FONT_8x8=y
 CONFIG_FONT_ACORN_8x8=y
 CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
@@ -146,16 +156,12 @@ CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_FTDI_SIO=y
 CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=m
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_ACM_MS=m
-CONFIG_USB_G_MULTI=m
-CONFIG_USB_G_MULTI_CDC=y
+CONFIG_USB_AT91=y
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -164,20 +170,23 @@ CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91RM9200=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
@@ -192,7 +201,7 @@ CONFIG_CRYPTO_ARC4=y
 CONFIG_CRYPTO_USER_API_HASH=m
 CONFIG_CRYPTO_USER_API_SKCIPHER=m
 # CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC_ITU_T=m
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=m
 CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig
index 4ae57a34a582..75502c4d222c 100644
--- a/arch/arm/configs/at91rm9200_defconfig
+++ b/arch/arm/configs/at91rm9200_defconfig
@@ -1,10 +1,12 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_USER_NS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -16,7 +18,6 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91RM9200=y
 CONFIG_MACH_ONEARM=y
-CONFIG_ARCH_AT91RM9200DK=y
 CONFIG_MACH_AT91RM9200EK=y
 CONFIG_MACH_CSB337=y
 CONFIG_MACH_CSB637=y
@@ -35,49 +36,37 @@ CONFIG_AT91_TIMER_HZ=100
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_AT91_CF=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
 CONFIG_AEABI=y
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
+# CONFIG_COMPACTION is not set
 CONFIG_ZBOOT_ROM_TEXT=0x10000000
 CONFIG_ZBOOT_ROM_BSS=0x20040000
 CONFIG_KEXEC=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
-CONFIG_XFRM_USER=m
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-CONFIG_NET_IPIP=m
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
 CONFIG_IPV6_PRIVACY=y
 CONFIG_IPV6_ROUTER_PREF=y
 CONFIG_IPV6_ROUTE_INFO=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_BT=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -94,55 +83,21 @@ CONFIG_MTD_NAND_PLATFORM=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_BLK_DEV_SR_VENDOR=y
-CONFIG_CHR_DEV_SG=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
-CONFIG_TUN=m
+CONFIG_MII=y
 CONFIG_ARM_AT91_ETHER=y
-CONFIG_PHYLIB=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_MICREL_PHY=y
-CONFIG_PPP=y
-CONFIG_PPP_BSDCOMP=y
-CONFIG_PPP_DEFLATE=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_MPPE=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPPOE=m
-CONFIG_PPP_ASYNC=y
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -151,38 +106,8 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
-CONFIG_SPI_BITBANG=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_HWMON=m
-CONFIG_SENSORS_ADM1021=m
-CONFIG_SENSORS_ADM1025=m
-CONFIG_SENSORS_ADM1026=m
-CONFIG_SENSORS_ADM1029=m
-CONFIG_SENSORS_ADM1031=m
-CONFIG_SENSORS_ADM9240=m
-CONFIG_SENSORS_DS1621=m
-CONFIG_SENSORS_GL518SM=m
-CONFIG_SENSORS_GL520SM=m
-CONFIG_SENSORS_IT87=m
-CONFIG_SENSORS_LM63=m
-CONFIG_SENSORS_LM73=m
-CONFIG_SENSORS_LM75=m
-CONFIG_SENSORS_LM77=m
-CONFIG_SENSORS_LM78=m
-CONFIG_SENSORS_LM80=m
-CONFIG_SENSORS_LM83=m
-CONFIG_SENSORS_LM85=m
-CONFIG_SENSORS_LM87=m
-CONFIG_SENSORS_LM90=m
-CONFIG_SENSORS_LM92=m
-CONFIG_SENSORS_MAX1619=m
-CONFIG_SENSORS_PCF8591=m
-CONFIG_SENSORS_SMSC47B397=m
-CONFIG_SENSORS_W83781D=m
-CONFIG_SENSORS_W83791D=m
-CONFIG_SENSORS_W83792D=m
-CONFIG_SENSORS_W83793=m
-CONFIG_SENSORS_W83L785TS=m
+# CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91RM9200_WATCHDOG=y
@@ -194,43 +119,14 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_DISPLAY_SUPPORT=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
-CONFIG_FONT_MINI_4x6=y
 CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_SERIAL_CONSOLE=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_KEYSPAN=y
-CONFIG_USB_SERIAL_KEYSPAN_MPR=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
-CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19=y
-CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
-CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
-CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
-CONFIG_USB_SERIAL_MCT_U232=y
-CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=y
 CONFIG_NEW_LEDS=y
@@ -240,84 +136,27 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-CONFIG_RTC_DRV_DS1307=y
-CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_REISERFS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
-CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=y
-CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
 CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RUBIN=y
-CONFIG_CRAMFS=y
-CONFIG_MINIX_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_CIFS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
+CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_PCBC=y
 CONFIG_CRYPTO_SHA1=y
+CONFIG_XZ_DEC_ARMTHUMB=y
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig
index 892e8287ed73..69b6928d3d9d 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9260_9g20_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -11,7 +10,14 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
+CONFIG_ARCH_AT91SAM9260=y
+CONFIG_MACH_AT91SAM9260EK=y
+CONFIG_MACH_CAM60=y
+CONFIG_MACH_SAM9_L9260=y
+CONFIG_MACH_AFEB9260=y
+CONFIG_MACH_QIL_A9260=y
+CONFIG_MACH_CPU9260=y
+CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_AT91SAM9G20EK=y
 CONFIG_MACH_AT91SAM9G20EK_2MMC=y
 CONFIG_MACH_CPU9G20=y
@@ -20,10 +26,10 @@ CONFIG_MACH_PORTUXG20=y
 CONFIG_MACH_STAMP9G20=y
 CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
-CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
 CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_SLOW_CLOCK=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
@@ -33,12 +39,14 @@ CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
@@ -46,8 +54,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
@@ -56,6 +67,8 @@ CONFIG_MTD_NAND_ATMEL=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -63,23 +76,36 @@ CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
-CONFIG_LEGACY_PTY_COUNT=16
+# CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -94,12 +120,11 @@ CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=m
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_SPI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
@@ -109,15 +134,12 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_RV3029C2=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_MSDOS_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -125,3 +147,9 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_AT91_DEBUG_LL_DBGU0=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
deleted file mode 100644
index 05618eb694f8..000000000000
--- a/arch/arm/configs/at91sam9260_defconfig
+++ /dev/null
@@ -1,91 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9260=y
-CONFIG_ARCH_AT91SAM9260_SAM9XE=y
-CONFIG_MACH_AT91SAM9260EK=y
-CONFIG_MACH_CAM60=y
-CONFIG_MACH_SAM9_L9260=y
-CONFIG_MACH_AFEB9260=y
-CONFIG_MACH_USB_A9260=y
-CONFIG_MACH_QIL_A9260=y
-CONFIG_MACH_CPU9260=y
-CONFIG_MACH_FLEXIBITY=y
-CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM9_DT=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/at91sam9261_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig
index c87beb973b37..9d35cd81c611 100644
--- a/arch/arm/configs/at91sam9261_defconfig
+++ b/arch/arm/configs/at91sam9261_9g10_defconfig
@@ -17,6 +17,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
+CONFIG_MACH_AT91SAM9G10EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -38,11 +39,11 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_CFG80211=y
-CONFIG_LIB80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
@@ -51,17 +52,13 @@ CONFIG_MTD_UBI=y
 CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 CONFIG_USB_ZD1201=m
 CONFIG_RTL8187=m
 CONFIG_LIBERTAS=m
@@ -118,15 +115,11 @@ CONFIG_SND_AT73C213=y
 CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_AT91=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
 CONFIG_NEW_LEDS=y
@@ -147,12 +140,10 @@ CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=y
 CONFIG_NLS_UTF8=y
-CONFIG_FTRACE=y
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 36fed66bd4b5..e40026364e57 100644
--- a/arch/arm/configs/at91sam9263_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -1,6 +1,4 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_IKCONFIG=y
@@ -17,7 +15,6 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
-CONFIG_MACH_USB_A9263=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
@@ -48,9 +45,11 @@ CONFIG_IP_PIMSM_V2=y
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
 CONFIG_IPV6=y
+# CONFIG_WIRELESS is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -65,7 +64,6 @@ CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
@@ -73,23 +71,18 @@ CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
 CONFIG_MII=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_USB_ZD1201=m
+CONFIG_SMSC_PHY=y
+# CONFIG_WLAN is not set
 CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -98,6 +91,7 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
+CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_NOWAYOUT=y
@@ -107,9 +101,9 @@ CONFIG_FB_ATMEL=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -124,16 +118,12 @@ CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
 CONFIG_SND_USB_AUDIO=m
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=m
@@ -145,22 +135,18 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_FUSE_FS=m
+CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_FTRACE=y
+CONFIG_NLS_UTF8=y
 CONFIG_DEBUG_USER=y
 CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 18964cdacd68..08166cd4e7d6 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
@@ -23,8 +22,6 @@ CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_CPU=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
@@ -36,6 +33,9 @@ CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -45,9 +45,6 @@ CONFIG_IPV6=y
 # CONFIG_INET6_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET6_XFRM_MODE_BEET is not set
 CONFIG_IPV6_SIT_6RD=y
-CONFIG_CFG80211=y
-CONFIG_LIB80211=y
-CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -61,13 +58,14 @@ CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_MISC_DEVICES=y
 CONFIG_ATMEL_PWM=y
 CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -76,67 +74,40 @@ CONFIG_NETDEVICES=y
 CONFIG_MII=y
 CONFIG_MACB=y
 CONFIG_DAVICOM_PHY=y
-CONFIG_LIBERTAS_THINFIRM=m
-CONFIG_LIBERTAS_THINFIRM_USB=m
-CONFIG_AT76C50X_USB=m
-CONFIG_USB_ZD1201=m
-CONFIG_RTL8187=m
-CONFIG_ATH_COMMON=m
-CONFIG_ATH9K=m
-CONFIG_CARL9170=m
-CONFIG_B43=m
-CONFIG_B43_PHY_N=y
-CONFIG_LIBERTAS=m
-CONFIG_LIBERTAS_USB=m
-CONFIG_LIBERTAS_SDIO=m
-CONFIG_LIBERTAS_SPI=m
-CONFIG_RT2X00=m
-CONFIG_RT2500USB=m
-CONFIG_RT73USB=m
-CONFIG_RT2800USB=m
-CONFIG_RT2800USB_RT53XX=y
-CONFIG_RT2800USB_UNKNOWN=y
-CONFIG_RTL8192CU=m
-CONFIG_WL1251=m
-CONFIG_WL1251_SDIO=m
-CONFIG_WL12XX_MENU=m
-CONFIG_WL12XX=m
-CONFIG_WL12XX_SDIO=m
-CONFIG_ZD1211RW=m
-CONFIG_MWIFIEX=m
-CONFIG_MWIFIEX_SDIO=m
-CONFIG_INPUT_POLLDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=480
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=272
+# CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_QT1070=m
-CONFIG_KEYBOARD_QT2160=m
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_KEYBOARD_QT2160=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
 CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
-CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
 CONFIG_SPI_ATMEL=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-CONFIG_FB_UDL=m
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_ATMEL_LCDC=y
+CONFIG_BACKLIGHT_ATMEL_PWM=y
 # CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SEQUENCER=y
@@ -148,33 +119,25 @@ CONFIG_SND_PCM_OSS=y
 # CONFIG_SND_ARM is not set
 CONFIG_SND_ATMEL_AC97C=y
 # CONFIG_SND_SPI is not set
-CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB is not set
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_ATMEL_USBA=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_AUDIO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_EEM=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_USB_G_MULTI=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_MULTI=y
 CONFIG_USB_G_MULTI_CDC=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_SDIO_UART=m
 CONFIG_MMC_ATMELMCI=y
-CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
@@ -184,17 +147,14 @@ CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
@@ -203,6 +163,8 @@ CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
 CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_USER_API_HASH=m
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index ce987211a609..34e9780e63ba 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -55,14 +55,11 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_SERIO is not set
-# CONFIG_VT is not set
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_TTY_PRINTK=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_BCM2835=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_BCM2835=y
@@ -70,11 +67,27 @@ CONFIG_SPI=y
 CONFIG_SPI_BCM2835=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_BCM2835=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
index 6524cdf3b08d..845f5cdf62b5 100644
--- a/arch/arm/configs/bockw_defconfig
+++ b/arch/arm/configs/bockw_defconfig
@@ -31,6 +31,7 @@ CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"
 CONFIG_CMDLINE_FORCE=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -48,6 +49,14 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
 # CONFIG_PREVENT_FIRMWARE_BUILD is not set
 # CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_M25P80=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
@@ -71,7 +80,23 @@ CONFIG_SERIAL_SH_SCI_NR_UARTS=6
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_SPI=y
+CONFIG_SPI_SH_HSPI=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_RCAR_PHY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RX8581=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_IOMMU_SUPPORT is not set
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
deleted file mode 100644
index 54571082d920..000000000000
--- a/arch/arm/configs/bonito_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_SHMOBILE=y
-CONFIG_ARCH_R8A7740=y
-CONFIG_MACH_BONITO=y
-# CONFIG_SH_TIMER_TMU is not set
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
-CONFIG_KEXEC=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-# CONFIG_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_ARM_INTEGRATOR=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_SH_SCI=y
-CONFIG_SERIAL_SH_SCI_NR_UARTS=9
-CONFIG_SERIAL_SH_SCI_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_SH_MOBILE=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_UIO=y
-CONFIG_UIO_PDRV=y
-CONFIG_UIO_PDRV_GENIRQ=y
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_TMPFS=y
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
index 1cd94c36321f..9e8c8316d6b0 100644
--- a/arch/arm/configs/clps711x_defconfig
+++ b/arch/arm/configs/clps711x_defconfig
@@ -31,21 +31,18 @@ CONFIG_EP7211_DONGLE=y
 # CONFIG_WIRELESS is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_AUTCPU12=y
 CONFIG_MTD_PLATRAM=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPIO=y
 CONFIG_NETDEVICES=y
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CHELSIO is not set
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 # CONFIG_NET_VENDOR_FARADAY is not set
@@ -63,7 +60,11 @@ CONFIG_CS89x0_PLATFORM=y
 # CONFIG_VT is not set
 CONFIG_SERIAL_CLPS711X_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_GPIO=y
 CONFIG_SPI=y
+CONFIG_SPI_CLPS711X=y
+CONFIG_GPIO_CLPS711X=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
 CONFIG_FB=y
@@ -87,4 +88,3 @@ CONFIG_DEBUG_LL=y
 CONFIG_EARLY_PRINTK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 227abf9cc601..ad7dfbbafa45 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -50,6 +50,7 @@ CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
 CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_CROS_EC=y
 # CONFIG_MOUSE_PS2 is not set
 CONFIG_MOUSE_CYAPA=y
@@ -104,6 +105,8 @@ CONFIG_MMC_SDHCI_S3C=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_IDMAC=y
 CONFIG_MMC_DW_EXYNOS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S3C=y
 CONFIG_COMMON_CLK_MAX77686=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f248b5..06686e7303a9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_SOC_VF610=y
 CONFIG_MXC_PWM=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
@@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
+CONFIG_PM_RUNTIME=y
 CONFIG_PM_DEBUG=y
 CONFIG_PM_TEST_SUSPEND=y
 CONFIG_NET=y
@@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FONTS=y
@@ -182,6 +186,7 @@ CONFIG_SND_SOC=y
 CONFIG_SND_IMX_SOC=y
 CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_WM8962=y
 CONFIG_SND_SOC_IMX_SGTL5000=y
 CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
@@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_DRM_IMX=y
+CONFIG_DRM_IMX_TVE=y
+CONFIG_DRM_IMX_FB_HELPER=y
+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
 CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
new file mode 100644
index 000000000000..62e968cac9dc
--- /dev/null
+++ b/arch/arm/configs/keystone_defconfig
@@ -0,0 +1,157 @@
+# CONFIG_SWAP is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_ELF_CORE is not set
+# CONFIG_BASE_FULL is not set
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_ARCH_KEYSTONE=y
+CONFIG_ARM_LPAE=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IPGRE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_INET_AH=y
+CONFIG_INET_IPCOMP=y
+CONFIG_IPV6=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP_SCTP=y
+CONFIG_VLAN_8021Q=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_CMA=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_PLATRAM=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+CONFIG_NETDEVICES=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_SPIDEV=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_MEMORY=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_USER_API_HASH=y
+CONFIG_CRYPTO_USER_API_SKCIPHER=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index a1d8252e9ec7..0f2aa61911a3 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,4 +1,3 @@
-CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
@@ -31,6 +30,7 @@ CONFIG_MACH_T5325=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_CLOUDBOX_DT=y
+CONFIG_MACH_DB88F628X_BP_DT=y
 CONFIG_MACH_DLINK_KIRKWOOD_DT=y
 CONFIG_MACH_DOCKSTAR_DT=y
 CONFIG_MACH_DREAMPLUG_DT=y
@@ -50,14 +50,19 @@ CONFIG_MACH_NETSPACE_V2_DT=y
 CONFIG_MACH_NSA310_DT=y
 CONFIG_MACH_OPENBLOCKS_A6_DT=y
 CONFIG_MACH_READYNAS_DT=y
+CONFIG_MACH_SHEEVAPLUG_DT=y
 CONFIG_MACH_TOPKICK_DT=y
 CONFIG_MACH_TS219_DT=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
+CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -68,14 +73,12 @@ CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
-CONFIG_NET_DSA=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
@@ -140,6 +143,7 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_PRINTER=m
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index f6e585b353a4..1ad028023a64 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -84,9 +84,12 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_SH_MOBILE=y
 CONFIG_GPIO_PCF857X=y
 # CONFIG_HWMON is not set
+CONFIG_MFD_AS3711=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AS3711=y
 CONFIG_FB=y
 CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_BACKLIGHT_AS3711=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 CONFIG_FB_SH_MOBILE_MERAM=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2e67a272df70..340d550c12b0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -1,6 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_ARCH_SIRF=y
@@ -31,10 +32,12 @@ CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_NETDEVICES=y
+CONFIG_SUN4I_EMAC=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=y
 CONFIG_SERIO_AMBAKMI=y
+CONFIG_MDIO_SUN4I=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
@@ -46,6 +49,8 @@ CONFIG_SERIAL_SIRFSOC=y
 CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_SERIAL_VT8500=y
 CONFIG_SERIAL_VT8500_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
 CONFIG_IPMI_HANDLER=y
 CONFIG_IPMI_SI=y
 CONFIG_I2C=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index f3e8ae001ff1..731814e2c189 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -13,6 +13,8 @@ CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_XP=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
@@ -60,6 +62,8 @@ CONFIG_USB_SUPPORT=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_HCD=y
 CONFIG_MMC=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
@@ -96,5 +100,3 @@ CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
index b01e7632ed2e..35f8cf299fa2 100644
--- a/arch/arm/configs/nhk8815_defconfig
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -81,6 +81,7 @@ CONFIG_PPP_SYNC_TTY=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
 # CONFIG_MOUSE_PS2 is not set
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
@@ -96,6 +97,11 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_MMC=y
 CONFIG_MMC_CLKGATE=y
 CONFIG_MMC_ARMMMCI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 9940f7b4e438..d74edbad18fc 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -26,7 +26,8 @@ CONFIG_ARCH_OMAP=y
 CONFIG_ARCH_OMAP1=y
 CONFIG_OMAP_RESET_CLOCKS=y
 # CONFIG_OMAP_MUX is not set
-CONFIG_OMAP_MBOX_FWK=y
+CONFIG_MAILBOX=y
+CONFIG_OMAP1_MBOX=y
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_DM_TIMER=y
 CONFIG_ARCH_OMAP730=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index abbe31937c65..2ac0ffb12f03 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -210,6 +210,8 @@ CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
 CONFIG_USB_TEST=y
+CONFIG_USB_PHY=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index 4d0dc3c16063..f6e78f83c3c3 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -26,7 +26,9 @@ CONFIG_AEABI=y
 CONFIG_UACCESS_WITH_MEMCPY=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
 CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_KEXEC=y
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
@@ -39,6 +41,9 @@ CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
@@ -68,6 +73,8 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
 CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=4
@@ -95,7 +102,19 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 CONFIG_MICREL_PHY=y
-# CONFIG_WLAN is not set
+CONFIG_LIBERTAS_THINFIRM=m
+CONFIG_LIBERTAS_THINFIRM_USB=m
+CONFIG_RTL8187=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RT2800USB_RT55XX=y
+CONFIG_RT2800USB_UNKNOWN=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_MWIFIEX_USB=m
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
@@ -133,9 +152,13 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_AT91=y
-CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_ATMEL_USBA=y
+CONFIG_USB_G_SERIAL=y
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ATMELMCI=y
@@ -151,18 +174,18 @@ CONFIG_DMADEVICES=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_IIO=y
 CONFIG_AT91_ADC=y
-CONFIG_EXT2_FS=y
+CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
 CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_NFS_FS=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_STRIP_ASM_SYMS=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index f7ba316164d4..1effb43dab80 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -21,8 +21,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_TEGRA=y
 CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_ARCH_TEGRA_114_SOC=y
@@ -36,7 +36,6 @@ CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_KEXEC=y
-CONFIG_AUTO_ZRELADDR=y
 CONFIG_CPU_FREQ=y
 CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPU_IDLE=y
@@ -81,7 +80,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_CMA=y
 CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
@@ -105,8 +103,8 @@ CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
 CONFIG_INPUT_EVDEV=y
-CONFIG_KEYBOARD_TEGRA=y
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MPU3050=y
 # CONFIG_LEGACY_PTYS is not set
@@ -121,6 +119,7 @@ CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
+CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_GPIO_PCA953X_IRQ=y
@@ -129,14 +128,15 @@ CONFIG_GPIO_TPS6586X=y
 CONFIG_GPIO_TPS65910=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
+CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET=y
 CONFIG_POWER_RESET_GPIO=y
 CONFIG_SENSORS_LM90=y
-CONFIG_MFD_TPS6586X=y
-CONFIG_MFD_TPS65910=y
 CONFIG_MFD_MAX8907=y
-CONFIG_MFD_TPS65090=y
 CONFIG_MFD_PALMAS=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
@@ -171,6 +171,7 @@ CONFIG_SND=y
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_RT5640=y
 CONFIG_SND_SOC_TEGRA_WM8753=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
@@ -190,7 +191,13 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
@@ -203,7 +210,6 @@ CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
-CONFIG_AK8975=y
 CONFIG_MFD_NVEC=y
 CONFIG_KEYBOARD_NVEC=y
 CONFIG_SERIO_NVEC_PS2=y
@@ -213,6 +219,7 @@ CONFIG_TEGRA_IOMMU_GART=y
 CONFIG_TEGRA_IOMMU_SMMU=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
+CONFIG_AK8975=y
 CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000ec4e4e..fd81a1b99cce 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
 # CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_CFQ is not set
+# CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_U300=y
-CONFIG_MACH_U300=y
-CONFIG_MACH_U300_BS335=y
 CONFIG_MACH_U300_SPIDUMMY=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,14 +42,15 @@ CONFIG_I2C=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
-CONFIG_MMC_CLKGATE=y
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_ARMMMCI=y
 CONFIG_RTC_CLASS=y
 # CONFIG_RTC_HCTOSYS is not set
@@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index 7c1bfc0aea0c..accefe099182 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -80,15 +80,6 @@ static inline u32 arch_timer_get_cntfrq(void)
         return val;
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-        u64 cval;
-
-        isb();
-        asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (cval));
-        return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 05ee9eebad6b..a5fef710af32 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -136,7 +136,11 @@
  * assumes FIQs are enabled, and that the processor is in SVC mode.
  */
         .macro  save_and_disable_irqs, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        mrs     \oldcpsr, primask
+#else
         mrs     \oldcpsr, cpsr
+#endif
         disable_irq
         .endm
 
@@ -150,7 +154,11 @@
  * guarantee that this will preserve the flags.
  */
         .macro  restore_irqs_notrace, oldcpsr
+#ifdef CONFIG_CPU_V7M
+        msr     primask, \oldcpsr
+#else
         msr     cpsr_c, \oldcpsr
+#endif
         .endm
 
         .macro restore_irqs, oldcpsr
@@ -229,7 +237,14 @@
 #endif
         .endm
 
-#ifdef CONFIG_THUMB2_KERNEL
+#if defined(CONFIG_CPU_V7M)
+        /*
+         * setmode is used to assert to be in svc mode during boot. For v7-M
+         * this is done in __v7m_setup, so setmode can be empty here.
+         */
+        .macro  setmode, mode, reg
+        .endm
+#elif defined(CONFIG_THUMB2_KERNEL)
         .macro  setmode, mode, reg
         mov     \reg, #\mode
         msr     cpsr_c, \reg
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index bff71388e72a..17d0ae8672fa 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -320,9 +320,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 }
 
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
-static inline void flush_kernel_dcache_page(struct page *page)
-{
-}
+extern void flush_kernel_dcache_page(struct page *);
 
 #define flush_dcache_mmap_lock(mapping) \
         spin_lock_irq(&(mapping)->tree_lock)
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 1f3262e99d81..6493802f880a 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -23,6 +23,11 @@
 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
 #define CR_DT   (1 << 16)
+#ifdef CONFIG_MMU
+#define CR_HA   (1 << 17)       /* Hardware management of Access Flag   */
+#else
+#define CR_BR   (1 << 17)       /* MPU Background region enable (PMSA)  */
+#endif
 #define CR_IT   (1 << 18)
 #define CR_ST   (1 << 19)
 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
@@ -61,6 +66,20 @@ static inline void set_cr(unsigned int val)
         isb();
 }
 
+static inline unsigned int get_auxcr(void)
+{
+        unsigned int val;
+        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val));
+        return val;
+}
+
+static inline void set_auxcr(unsigned int val)
+{
+        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
+          : : "r" (val));
+        isb();
+}
+
 #ifndef CONFIG_SMP
 extern void adjust_cr(unsigned long mask, unsigned long set);
 #endif
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 7652712d1d14..8c25dc4e9851 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -8,8 +8,25 @@
 #define CPUID_CACHETYPE 1
 #define CPUID_TCM       2
 #define CPUID_TLBTYPE   3
+#define CPUID_MPUIR     4
 #define CPUID_MPIDR     5
 
+#ifdef CONFIG_CPU_V7M
+#define CPUID_EXT_PFR0  0x40
+#define CPUID_EXT_PFR1  0x44
+#define CPUID_EXT_DFR0  0x48
+#define CPUID_EXT_AFR0  0x4c
+#define CPUID_EXT_MMFR0 0x50
+#define CPUID_EXT_MMFR1 0x54
+#define CPUID_EXT_MMFR2 0x58
+#define CPUID_EXT_MMFR3 0x5c
+#define CPUID_EXT_ISAR0 0x60
+#define CPUID_EXT_ISAR1 0x64
+#define CPUID_EXT_ISAR2 0x68
+#define CPUID_EXT_ISAR3 0x6c
+#define CPUID_EXT_ISAR4 0x70
+#define CPUID_EXT_ISAR5 0x74
+#else
 #define CPUID_EXT_PFR0  "c1, 0"
 #define CPUID_EXT_PFR1  "c1, 1"
 #define CPUID_EXT_DFR0  "c1, 2"
@@ -24,6 +41,7 @@
 #define CPUID_EXT_ISAR3 "c2, 3"
 #define CPUID_EXT_ISAR4 "c2, 4"
 #define CPUID_EXT_ISAR5 "c2, 5"
+#endif
 
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
@@ -32,6 +50,8 @@
 
 #define MPIDR_HWID_BITMASK 0xFFFFFF
 
+#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
+
 #define MPIDR_LEVEL_BITS 8
 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
 
@@ -79,7 +99,23 @@ extern unsigned int processor_id;
                 __val;                                                  \
         })
 
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+
+#include <asm/io.h>
+#include <asm/v7m.h>
+
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                WARN_ON_ONCE(1);                                        \
+                0;                                                      \
+        })
+
+static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
+{
+        return readl(BASEADDR_V7M_SCB + offset);
+}
+
+#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 
 /*
  * read_cpuid and read_cpuid_ext should only ever be called on machines that
@@ -106,7 +142,14 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
         return read_cpuid(CPUID_ID);
 }
 
-#else /* ifdef CONFIG_CPU_CP15 */
+#elif defined(CONFIG_CPU_V7M)
+
+static inline unsigned int __attribute_const__ read_cpuid_id(void)
+{
+        return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
+}
+
+#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 
 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 {
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h
index fe92ccf1d0b0..191ada6e4d2d 100644
--- a/arch/arm/include/asm/div64.h
+++ b/arch/arm/include/asm/div64.h
@@ -46,7 +46,7 @@
         __rem;                                                  \
 })
 
-#if __GNUC__ < 4
+#if __GNUC__ < 4 || !defined(CONFIG_AEABI)
 
 /*
  * gcc versions earlier than 4.0 are simply too problematic for the
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index ea289e1435e7..c81adc08b3fb 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,10 +117,37 @@
 # endif
 #endif
 
+#if defined(CONFIG_CPU_V7M)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE nop
+# endif
+#endif
+
 #if !defined(_CACHE) && !defined(MULTI_CACHE)
 #error Unknown cache maintenance model
 #endif
 
+#ifndef __ASSEMBLER__
+extern inline void nop_flush_icache_all(void) { }
+extern inline void nop_flush_kern_cache_all(void) { }
+extern inline void nop_flush_kern_cache_louis(void) { }
+extern inline void nop_flush_user_cache_all(void) { }
+extern inline void nop_flush_user_cache_range(unsigned long a,
+                unsigned long b, unsigned int c) { }
+
+extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+extern inline int nop_coherent_user_range(unsigned long a,
+                unsigned long b) { return 0; }
+extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+
+extern inline void nop_dma_flush_range(const void *a, const void *b) { }
+
+extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+#endif
+
 #ifndef MULTI_CACHE
 #define __cpuc_flush_icache_all         __glue(_CACHE,_flush_icache_all)
 #define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..6b70f1b46a6e 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -95,6 +95,14 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_ABRT_NOMMU
+# ifdef CPU_DABORT_HANDLER
+#  define MULTI_DABORT 1
+# else
+#  define CPU_DABORT_HANDLER nommu_early_abort
+# endif
+#endif
+
 #ifndef CPU_DABORT_HANDLER
 #error Unknown data abort handler type
 #endif
diff --git a/arch/arm/include/asm/glue-proc.h b/arch/arm/include/asm/glue-proc.h
index ac1dd54724b6..74a8b84f3cb1 100644
--- a/arch/arm/include/asm/glue-proc.h
+++ b/arch/arm/include/asm/glue-proc.h
@@ -230,6 +230,24 @@
 # endif
 #endif
 
+#ifdef CONFIG_CPU_V7M
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_v7m
+# endif
+#endif
+
+#ifdef CONFIG_CPU_PJ4B
+# ifdef CPU_NAME
+#  undef  MULTI_CPU
+#  define MULTI_CPU
+# else
+#  define CPU_NAME cpu_pj4b
+# endif
+#endif
+
 #ifndef MULTI_CPU
 #define cpu_proc_init                   __glue(CPU_NAME,_proc_init)
 #define cpu_proc_fin                    __glue(CPU_NAME,_proc_fin)
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- *  arch/arm/include/asm/hardware/pci_v3.h
- *
- *  Internal header file PCI V3 chip
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_PCI_V3_H
-#define ASM_ARM_HARDWARE_PCI_V3_H
-
-/* -------------------------------------------------------------------------------
- *  V3 Local Bus to PCI Bridge definitions
- * -------------------------------------------------------------------------------
- *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
- *  All V3 register names are prefaced by V3_ to avoid clashing with any other
- *  PCI definitions.  Their names match the user's manual.
- * 
- *  I'm assuming that I20 is disabled.
- * 
- */
-#define V3_PCI_VENDOR                   0x00000000
-#define V3_PCI_DEVICE                   0x00000002
-#define V3_PCI_CMD                      0x00000004
-#define V3_PCI_STAT                     0x00000006
-#define V3_PCI_CC_REV                   0x00000008
-#define V3_PCI_HDR_CFG                  0x0000000C
-#define V3_PCI_IO_BASE                  0x00000010
-#define V3_PCI_BASE0                    0x00000014
-#define V3_PCI_BASE1                    0x00000018
-#define V3_PCI_SUB_VENDOR               0x0000002C
-#define V3_PCI_SUB_ID                   0x0000002E
-#define V3_PCI_ROM                      0x00000030
-#define V3_PCI_BPARAM                   0x0000003C
-#define V3_PCI_MAP0                     0x00000040
-#define V3_PCI_MAP1                     0x00000044
-#define V3_PCI_INT_STAT                 0x00000048
-#define V3_PCI_INT_CFG                  0x0000004C 
-#define V3_LB_BASE0                     0x00000054
-#define V3_LB_BASE1                     0x00000058
-#define V3_LB_MAP0                      0x0000005E
-#define V3_LB_MAP1                      0x00000062
-#define V3_LB_BASE2                     0x00000064
-#define V3_LB_MAP2                      0x00000066
-#define V3_LB_SIZE                      0x00000068
-#define V3_LB_IO_BASE                   0x0000006E
-#define V3_FIFO_CFG                     0x00000070
-#define V3_FIFO_PRIORITY                0x00000072
-#define V3_FIFO_STAT                    0x00000074
-#define V3_LB_ISTAT                     0x00000076
-#define V3_LB_IMASK                     0x00000077
-#define V3_SYSTEM                       0x00000078
-#define V3_LB_CFG                       0x0000007A
-#define V3_PCI_CFG                      0x0000007C
-#define V3_DMA_PCI_ADR0                 0x00000080
-#define V3_DMA_PCI_ADR1                 0x00000090
-#define V3_DMA_LOCAL_ADR0               0x00000084
-#define V3_DMA_LOCAL_ADR1               0x00000094
-#define V3_DMA_LENGTH0                  0x00000088
-#define V3_DMA_LENGTH1                  0x00000098
-#define V3_DMA_CSR0                     0x0000008B
-#define V3_DMA_CSR1                     0x0000009B
-#define V3_DMA_CTLB_ADR0                0x0000008C
-#define V3_DMA_CTLB_ADR1                0x0000009C
-#define V3_DMA_DELAY                    0x000000E0
-#define V3_MAIL_DATA                    0x000000C0
-#define V3_PCI_MAIL_IEWR                0x000000D0
-#define V3_PCI_MAIL_IERD                0x000000D2
-#define V3_LB_MAIL_IEWR                 0x000000D4
-#define V3_LB_MAIL_IERD                 0x000000D6
-#define V3_MAIL_WR_STAT                 0x000000D8
-#define V3_MAIL_RD_STAT                 0x000000DA
-#define V3_QBA_MAP                      0x000000DC
-
-/*  PCI COMMAND REGISTER bits
- */
-#define V3_COMMAND_M_FBB_EN             (1 << 9)
-#define V3_COMMAND_M_SERR_EN            (1 << 8)
-#define V3_COMMAND_M_PAR_EN             (1 << 6)
-#define V3_COMMAND_M_MASTER_EN          (1 << 2)
-#define V3_COMMAND_M_MEM_EN             (1 << 1)
-#define V3_COMMAND_M_IO_EN              (1 << 0)
-
-/*  SYSTEM REGISTER bits
- */
-#define V3_SYSTEM_M_RST_OUT             (1 << 15)
-#define V3_SYSTEM_M_LOCK                (1 << 14)
-
-/*  PCI_CFG bits
- */
-#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
-#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
-#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
-#define V3_PCI_CFG_M_EN3V               (1 << 12)
-#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
-#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
-#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
-
-/*  PCI_BASE register bits (PCI -> Local Bus)
- */
-#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
-#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
-#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
-#define V3_PCI_BASE_M_TYPE              (3 << 1)
-#define V3_PCI_BASE_M_IO                (1 << 0)
-
-/*  PCI MAP register bits (PCI -> Local bus)
- */
-#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
-#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
-#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
-#define V3_PCI_MAP_M_SWAP               (3 << 8)
-#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
-#define V3_PCI_MAP_M_REG_EN             (1 << 1)
-#define V3_PCI_MAP_M_ENABLE             (1 << 0)
-
-/*
- *  LB_BASE0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_BASE_ADR_BASE             0xfff00000
-#define V3_LB_BASE_SWAP                 (3 << 8)
-#define V3_LB_BASE_ADR_SIZE             (15 << 4)
-#define V3_LB_BASE_PREFETCH             (1 << 3)
-#define V3_LB_BASE_ENABLE               (1 << 0)
-
-#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
-#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
-#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
-#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
-#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
-#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
-#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
-#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
-#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
-#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
-#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
-#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
-
-#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
-
-/*
- *  LB_MAP0,1 register bits (Local bus -> PCI)
- */
-#define V3_LB_MAP_MAP_ADR               0xfff0
-#define V3_LB_MAP_TYPE                  (7 << 1)
-#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
-
-#define V3_LB_MAP_TYPE_IACK             (0 << 1)
-#define V3_LB_MAP_TYPE_IO               (1 << 1)
-#define V3_LB_MAP_TYPE_MEM              (3 << 1)
-#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
-#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
-
-#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
-
-/*
- *  LB_BASE2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_BASE2_ADR_BASE            0xff00
-#define V3_LB_BASE2_SWAP                (3 << 6)
-#define V3_LB_BASE2_ENABLE              (1 << 0)
-
-#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
-
-/*
- *  LB_MAP2 register bits (Local bus -> PCI IO)
- */
-#define V3_LB_MAP2_MAP_ADR              0xff00
-
-#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
-
-#endif
diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h
new file mode 100644
index 000000000000..d4014fbe5ea3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb-3level.h
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/include/asm/hugetlb-3level.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_3LEVEL_H
+#define _ASM_ARM_HUGETLB_3LEVEL_H
+
+
+/*
+ * If our huge pte is non-zero then mark the valid bit.
+ * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero
+ * ptes.
+ * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes).
+ */
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        pte_t retval = *ptep;
+        if (pte_val(retval))
+                pte_val(retval) |= L_PTE_VALID;
+        return retval;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+        ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+#endif /* _ASM_ARM_HUGETLB_3LEVEL_H */
diff --git a/arch/arm/include/asm/hugetlb.h b/arch/arm/include/asm/hugetlb.h
new file mode 100644
index 000000000000..1f1b1cd112f3
--- /dev/null
+++ b/arch/arm/include/asm/hugetlb.h
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef _ASM_ARM_HUGETLB_H
+#define _ASM_ARM_HUGETLB_H
+
+#include <asm/page.h>
+#include <asm-generic/hugetlb.h>
+
+#include <asm/hugetlb-3level.h>
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr, unsigned long len)
+{
+        return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr, unsigned long len)
+{
+        struct hstate *h = hstate_file(file);
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+        clear_bit(PG_dcache_clean, &page->flags);
+}
+
+#endif /* _ASM_ARM_HUGETLB_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 652b56086de7..d070741b2b37 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
  */
 extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
         size_t, unsigned int, void *);
-extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
         void *);
 
 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
-extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached);
+extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
+extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 extern void __iounmap(volatile void __iomem *addr);
 extern void __arm_iounmap(volatile void __iomem *addr);
 
-extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
         unsigned int, void *);
 extern void (*arch_iounmap)(volatile void __iomem *);
 
diff --git a/arch/arm/include/asm/irqflags.h b/arch/arm/include/asm/irqflags.h
index 1e6cca55c750..3b763d6652a0 100644
--- a/arch/arm/include/asm/irqflags.h
+++ b/arch/arm/include/asm/irqflags.h
@@ -8,6 +8,16 @@
 /*
  * CPU interrupt mask handling.
  */
+#ifdef CONFIG_CPU_V7M
+#define IRQMASK_REG_NAME_R "primask"
+#define IRQMASK_REG_NAME_W "primask"
+#define IRQMASK_I_BIT   1
+#else
+#define IRQMASK_REG_NAME_R "cpsr"
+#define IRQMASK_REG_NAME_W "cpsr_c"
+#define IRQMASK_I_BIT   PSR_I_BIT
+#endif
+
 #if __LINUX_ARM_ARCH__ >= 6
 
 static inline unsigned long arch_local_irq_save(void)
@@ -15,7 +25,7 @@ static inline unsigned long arch_local_irq_save(void)
         unsigned long flags;
 
         asm volatile(
-                "       mrs     %0, cpsr        @ arch_local_irq_save\n"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ arch_local_irq_save\n"
                 "       cpsid   i"
                 : "=r" (flags) : : "memory", "cc");
         return flags;
@@ -129,7 +139,7 @@ static inline unsigned long arch_local_save_flags(void)
 {
         unsigned long flags;
         asm volatile(
-                "       mrs     %0, cpsr        @ local_save_flags"
+                "       mrs     %0, " IRQMASK_REG_NAME_R "      @ local_save_flags"
                 : "=r" (flags) : : "memory", "cc");
         return flags;
 }
@@ -140,7 +150,7 @@ static inline unsigned long arch_local_save_flags(void)
 static inline void arch_local_irq_restore(unsigned long flags)
 {
         asm volatile(
-                "       msr     cpsr_c, %0      @ local_irq_restore"
+                "       msr     " IRQMASK_REG_NAME_W ", %0      @ local_irq_restore"
                 :
                 : "r" (flags)
                 : "memory", "cc");
@@ -148,8 +158,8 @@ static inline void arch_local_irq_restore(unsigned long flags)
 
 static inline int arch_irqs_disabled_flags(unsigned long flags)
 {
-        return flags & PSR_I_BIT;
+        return flags & IRQMASK_I_BIT;
 }
 
-#endif
-#endif
+#endif /* ifdef __KERNEL__ */
+#endif /* ifndef __ASM_ARM_IRQFLAGS_H */
diff --git a/arch/arm/include/asm/kvm_arch_timer.h b/arch/arm/include/asm/kvm_arch_timer.h
deleted file mode 100644
index 68cb9e1dfb81..000000000000
--- a/arch/arm/include/asm/kvm_arch_timer.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_KVM_ARCH_TIMER_H
-#define __ASM_ARM_KVM_ARCH_TIMER_H
-
-#include <linux/clocksource.h>
-#include <linux/hrtimer.h>
-#include <linux/workqueue.h>
-
-struct arch_timer_kvm {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Is the timer enabled */
-        bool                    enabled;
-
-        /* Virtual offset */
-        cycle_t                 cntvoff;
-#endif
-};
-
-struct arch_timer_cpu {
-#ifdef CONFIG_KVM_ARM_TIMER
-        /* Registers: control register, timer value */
-        u32                             cntv_ctl;       /* Saved/restored */
-        cycle_t                         cntv_cval;      /* Saved/restored */
-
-        /*
-         * Anything that is not used directly from assembly code goes
-         * here.
-         */
-
-        /* Background timer used when the guest is not running */
-        struct hrtimer                  timer;
-
-        /* Work queued with the above timer expires */
-        struct work_struct              expired;
-
-        /* Background timer active */
-        bool                            armed;
-
-        /* Timer IRQ */
-        const struct kvm_irq_level      *irq;
-#endif
-};
-
-#ifdef CONFIG_KVM_ARM_TIMER
-int kvm_timer_hyp_init(void);
-int kvm_timer_init(struct kvm *kvm);
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu);
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu);
-#else
-static inline int kvm_timer_hyp_init(void)
-{
-        return 0;
-};
-
-static inline int kvm_timer_init(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu) {}
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index 124623e5ef14..64e96960de29 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -135,7 +135,6 @@
 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1ULL)
 #define PTRS_PER_S2_PGD (1ULL << (KVM_PHYS_SHIFT - 30))
 #define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
-#define S2_PGD_SIZE     (1 << S2_PGD_ORDER)
 
 /* Virtualization Translation Control Register (VTCR) bits */
 #define VTCR_SH0        (3 << 12)
diff --git a/arch/arm/include/asm/kvm_asm.h b/arch/arm/include/asm/kvm_asm.h
index 18d50322a9e2..a2f43ddcc300 100644
--- a/arch/arm/include/asm/kvm_asm.h
+++ b/arch/arm/include/asm/kvm_asm.h
@@ -37,16 +37,18 @@
 #define c5_AIFSR        15      /* Auxilary Instrunction Fault Status R */
 #define c6_DFAR         16      /* Data Fault Address Register */
 #define c6_IFAR         17      /* Instruction Fault Address Register */
-#define c9_L2CTLR       18      /* Cortex A15 L2 Control Register */
-#define c10_PRRR        19      /* Primary Region Remap Register */
-#define c10_NMRR        20      /* Normal Memory Remap Register */
-#define c12_VBAR        21      /* Vector Base Address Register */
-#define c13_CID         22      /* Context ID Register */
-#define c13_TID_URW     23      /* Thread ID, User R/W */
-#define c13_TID_URO     24      /* Thread ID, User R/O */
-#define c13_TID_PRIV    25      /* Thread ID, Privileged */
-#define c14_CNTKCTL     26      /* Timer Control Register (PL1) */
-#define NR_CP15_REGS    27      /* Number of regs (incl. invalid) */
+#define c7_PAR          18      /* Physical Address Register */
+#define c7_PAR_high     19      /* PAR top 32 bits */
+#define c9_L2CTLR       20      /* Cortex A15 L2 Control Register */
+#define c10_PRRR        21      /* Primary Region Remap Register */
+#define c10_NMRR        22      /* Normal Memory Remap Register */
+#define c12_VBAR        23      /* Vector Base Address Register */
+#define c13_CID         24      /* Context ID Register */
+#define c13_TID_URW     25      /* Thread ID, User R/W */
+#define c13_TID_URO     26      /* Thread ID, User R/O */
+#define c13_TID_PRIV    27      /* Thread ID, Privileged */
+#define c14_CNTKCTL     28      /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    29      /* Number of regs (incl. invalid) */
 
 #define ARM_EXCEPTION_RESET       0
 #define ARM_EXCEPTION_UNDEFINED   1
@@ -72,8 +74,6 @@ extern char __kvm_hyp_vector[];
 extern char __kvm_hyp_code_start[];
 extern char __kvm_hyp_code_end[];
 
-extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
-
 extern void __kvm_flush_vm_context(void);
 extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
 
diff --git a/arch/arm/include/asm/kvm_emulate.h b/arch/arm/include/asm/kvm_emulate.h
index 82b4babead2c..a464e8d7b6c5 100644
--- a/arch/arm/include/asm/kvm_emulate.h
+++ b/arch/arm/include/asm/kvm_emulate.h
@@ -65,11 +65,6 @@ static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
         return cpsr_mode > USR_MODE;;
 }
 
-static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
-{
-        return reg == 15;
-}
-
 static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
 {
         return vcpu->arch.fault.hsr;
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 57cb786a6203..7d22517d8071 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -23,9 +23,14 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
 #include <asm/fpstate.h>
-#include <asm/kvm_arch_timer.h>
+#include <kvm/arm_arch_timer.h>
 
+#if defined(CONFIG_KVM_ARM_MAX_VCPUS)
 #define KVM_MAX_VCPUS CONFIG_KVM_ARM_MAX_VCPUS
+#else
+#define KVM_MAX_VCPUS 0
+#endif
+
 #define KVM_USER_MEM_SLOTS 32
 #define KVM_PRIVATE_MEM_SLOTS 4
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
@@ -38,7 +43,7 @@
 #define KVM_NR_PAGE_SIZES       1
 #define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
 
-#include <asm/kvm_vgic.h>
+#include <kvm/arm_vgic.h>
 
 struct kvm_vcpu;
 u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);
@@ -190,8 +195,8 @@ int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
                 int exception_index);
 
-static inline void __cpu_init_hyp_mode(unsigned long long boot_pgd_ptr,
-                                       unsigned long long pgd_ptr,
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+                                       phys_addr_t pgd_ptr,
                                        unsigned long hyp_stack_ptr,
                                        unsigned long vector_ptr)
 {
diff --git a/arch/arm/include/asm/kvm_vgic.h b/arch/arm/include/asm/kvm_vgic.h
deleted file mode 100644
index 343744e4809c..000000000000
--- a/arch/arm/include/asm/kvm_vgic.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_KVM_VGIC_H
-#define __ASM_ARM_KVM_VGIC_H
-
-#include <linux/kernel.h>
-#include <linux/kvm.h>
-#include <linux/irqreturn.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <linux/irqchip/arm-gic.h>
-
-#define VGIC_NR_IRQS            128
-#define VGIC_NR_SGIS            16
-#define VGIC_NR_PPIS            16
-#define VGIC_NR_PRIVATE_IRQS    (VGIC_NR_SGIS + VGIC_NR_PPIS)
-#define VGIC_NR_SHARED_IRQS     (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
-#define VGIC_MAX_CPUS           KVM_MAX_VCPUS
-#define VGIC_MAX_LRS            (1 << 6)
-
-/* Sanity checks... */
-#if (VGIC_MAX_CPUS > 8)
-#error  Invalid number of CPU interfaces
-#endif
-
-#if (VGIC_NR_IRQS & 31)
-#error "VGIC_NR_IRQS must be a multiple of 32"
-#endif
-
-#if (VGIC_NR_IRQS > 1024)
-#error "VGIC_NR_IRQS must be <= 1024"
-#endif
-
-/*
- * The GIC distributor registers describing interrupts have two parts:
- * - 32 per-CPU interrupts (SGI + PPI)
- * - a bunch of shared interrupts (SPI)
- */
-struct vgic_bitmap {
-        union {
-                u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
-        } percpu[VGIC_MAX_CPUS];
-        union {
-                u32 reg[VGIC_NR_SHARED_IRQS / 32];
-                DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
-        } shared;
-};
-
-struct vgic_bytemap {
-        u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
-        u32 shared[VGIC_NR_SHARED_IRQS  / 4];
-};
-
-struct vgic_dist {
-#ifdef CONFIG_KVM_ARM_VGIC
-        spinlock_t              lock;
-        bool                    ready;
-
-        /* Virtual control interface mapping */
-        void __iomem            *vctrl_base;
-
-        /* Distributor and vcpu interface mapping in the guest */
-        phys_addr_t             vgic_dist_base;
-        phys_addr_t             vgic_cpu_base;
-
-        /* Distributor enabled */
-        u32                     enabled;
-
-        /* Interrupt enabled (one bit per IRQ) */
-        struct vgic_bitmap      irq_enabled;
-
-        /* Interrupt 'pin' level */
-        struct vgic_bitmap      irq_state;
-
-        /* Level-triggered interrupt in progress */
-        struct vgic_bitmap      irq_active;
-
-        /* Interrupt priority. Not used yet. */
-        struct vgic_bytemap     irq_priority;
-
-        /* Level/edge triggered */
-        struct vgic_bitmap      irq_cfg;
-
-        /* Source CPU per SGI and target CPU */
-        u8                      irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
-
-        /* Target CPU for each IRQ */
-        u8                      irq_spi_cpu[VGIC_NR_SHARED_IRQS];
-        struct vgic_bitmap      irq_spi_target[VGIC_MAX_CPUS];
-
-        /* Bitmap indicating which CPU has something pending */
-        unsigned long           irq_pending_on_cpu;
-#endif
-};
-
-struct vgic_cpu {
-#ifdef CONFIG_KVM_ARM_VGIC
-        /* per IRQ to LR mapping */
-        u8              vgic_irq_lr_map[VGIC_NR_IRQS];
-
-        /* Pending interrupts on this VCPU */
-        DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
-        DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
-
-        /* Bitmap of used/free list registers */
-        DECLARE_BITMAP( lr_used, VGIC_MAX_LRS);
-
-        /* Number of list registers on this CPU */
-        int             nr_lr;
-
-        /* CPU vif control registers for world switch */
-        u32             vgic_hcr;
-        u32             vgic_vmcr;
-        u32             vgic_misr;      /* Saved only */
-        u32             vgic_eisr[2];   /* Saved only */
-        u32             vgic_elrsr[2];  /* Saved only */
-        u32             vgic_apr;
-        u32             vgic_lr[VGIC_MAX_LRS];
-#endif
-};
-
-#define LR_EMPTY        0xff
-
-struct kvm;
-struct kvm_vcpu;
-struct kvm_run;
-struct kvm_exit_mmio;
-
-#ifdef CONFIG_KVM_ARM_VGIC
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr);
-int kvm_vgic_hyp_init(void);
-int kvm_vgic_init(struct kvm *kvm);
-int kvm_vgic_create(struct kvm *kvm);
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level);
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio);
-
-#define irqchip_in_kernel(k)    (!!((k)->arch.vgic.vctrl_base))
-#define vgic_initialized(k)     ((k)->arch.vgic.ready)
-
-#else
-static inline int kvm_vgic_hyp_init(void)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_init(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_create(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-
-static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
-static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
-
-static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
-                                      unsigned int irq_num, bool level)
-{
-        return 0;
-}
-
-static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        return 0;
-}
-
-static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                                    struct kvm_exit_mmio *mmio)
-{
-        return false;
-}
-
-static inline int irqchip_in_kernel(struct kvm *kvm)
-{
-        return 0;
-}
-
-static inline bool vgic_initialized(struct kvm *kvm)
-{
-        return true;
-}
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 308ad7d6f98b..75bf07910b81 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -8,6 +8,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/types.h>
+
 #ifndef __ASSEMBLY__
 
 struct tag;
@@ -16,8 +18,10 @@ struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
 #define smp_ops(ops) (&(ops))
+#define smp_init_ops(ops) (&(ops))
 #else
 #define smp_ops(ops) (struct smp_operations *)NULL
+#define smp_init_ops(ops) (bool (*)(void))NULL
 #endif
 
 struct machine_desc {
@@ -41,6 +45,7 @@ struct machine_desc {
         unsigned char           reserve_lp2 :1; /* never has lp2        */
         char                    restart_mode;   /* default restart mode */
         struct smp_operations   *smp;           /* SMP operations       */
+        bool                    (*smp_init)(void);
         void                    (*fixup)(struct tag *, char **,
                                          struct meminfo *);
         void                    (*reserve)(void);/* reserve mem blocks  */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
 struct pci_sys_data;
 struct pci_ops;
 struct pci_bus;
+struct device;
 
 struct hw_pci {
 #ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
 /*
  * Call this with your hw_pci struct to initialise the PCI system.
  */
-void pci_common_init(struct hw_pci *);
+void pci_common_init_dev(struct device *, struct hw_pci *);
+
+/*
+ * Compatibility wrapper for older platforms that do not care about
+ * passing the parent device.
+ */
+static inline void pci_common_init(struct hw_pci *hw)
+{
+        pci_common_init_dev(NULL, hw);
+}
 
 /*
  * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
 extern int via82c505_setup(int nr, struct pci_sys_data *);
 extern void via82c505_init(void *sysdata);
 
-extern struct pci_ops pci_v3_ops;
-extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern void pci_v3_preinit(void);
-extern void pci_v3_postinit(void);
-
 #endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 57870ab313c5..e750a938fd3c 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -18,6 +18,8 @@
 #include <linux/types.h>
 #include <linux/sizes.h>
 
+#include <asm/cache.h>
+
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
 #endif
@@ -141,6 +143,20 @@
 #define page_to_phys(page)      (__pfn_to_phys(page_to_pfn(page)))
 #define phys_to_page(phys)      (pfn_to_page(__phys_to_pfn(phys)))
 
+/*
+ * Minimum guaranted alignment in pgd_alloc().  The page table pointers passed
+ * around in head.S and proc-*.S are shifted by this amount, in order to
+ * leave spare high bits for systems with physical address extension.  This
+ * does not fully accomodate the 40-bit addressing capability of ARM LPAE, but
+ * gives us about 38-bits or so.
+ */
+#ifdef CONFIG_ARM_LPAE
+#define ARCH_PGD_SHIFT          L1_CACHE_SHIFT
+#else
+#define ARCH_PGD_SHIFT          0
+#endif
+#define ARCH_PGD_MASK           ((1 << ARCH_PGD_SHIFT) - 1)
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -207,7 +223,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
  * direct-mapped view.  We assume this is the first page
  * of RAM in the mem_map as well.
  */
-#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+#define PHYS_PFN_OFFSET ((unsigned long)(PHYS_OFFSET >> PAGE_SHIFT))
 
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
@@ -260,12 +276,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 /*
  * Conversion between a struct page and a physical address.
  *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
  *  page_to_pfn(page)   convert a struct page * to a PFN number
  *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
  *
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a7b85e0d0cc1..b5792b7fd8d3 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,6 +18,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/proc-fns.h>
+#include <asm/smp_plat.h>
 #include <asm-generic/mm_hooks.h>
 
 void __check_vmalloc_seq(struct mm_struct *mm);
@@ -27,7 +28,15 @@ void __check_vmalloc_seq(struct mm_struct *mm);
 void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk);
 #define init_new_context(tsk,mm)        ({ atomic64_set(&mm->context.id, 0); 0; })
 
-DECLARE_PER_CPU(atomic64_t, active_asids);
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask);
+#else  /* !CONFIG_ARM_ERRATA_798181 */
+static inline void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                                           cpumask_t *mask)
+{
+}
+#endif /* CONFIG_ARM_ERRATA_798181 */
 
 #else   /* !CONFIG_CPU_HAS_ASID */
 
@@ -98,12 +107,16 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 #ifdef CONFIG_MMU
         unsigned int cpu = smp_processor_id();
 
-#ifdef CONFIG_SMP
-        /* check for possible thread migration */
-        if (!cpumask_empty(mm_cpumask(next)) &&
+        /*
+         * __sync_icache_dcache doesn't broadcast the I-cache invalidation,
+         * so check for possible thread migration and invalidate the I-cache
+         * if we're new to this CPU.
+         */
+        if (cache_ops_need_broadcast() &&
+            !cpumask_empty(mm_cpumask(next)) &&
             !cpumask_test_cpu(cpu, mm_cpumask(next)))
                 __flush_icache_all();
-#endif
+
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
                 check_and_switch_context(next, tsk);
                 if (cache_is_vivt())
diff --git a/arch/arm/include/asm/mpu.h b/arch/arm/include/asm/mpu.h
new file mode 100644
index 000000000000..c3247cc2fe08
--- /dev/null
+++ b/arch/arm/include/asm/mpu.h
@@ -0,0 +1,76 @@
+#ifndef __ARM_MPU_H
+#define __ARM_MPU_H
+
+#ifdef CONFIG_ARM_MPU
+
+/* MPUIR layout */
+#define MPUIR_nU                1
+#define MPUIR_DREGION           8
+#define MPUIR_IREGION           16
+#define MPUIR_DREGION_SZMASK    (0xFF << MPUIR_DREGION)
+#define MPUIR_IREGION_SZMASK    (0xFF << MPUIR_IREGION)
+
+/* ID_MMFR0 data relevant to MPU */
+#define MMFR0_PMSA              (0xF << 4)
+#define MMFR0_PMSAv7            (3 << 4)
+
+/* MPU D/I Size Register fields */
+#define MPU_RSR_SZ              1
+#define MPU_RSR_EN              0
+
+/* The D/I RSR value for an enabled region spanning the whole of memory */
+#define MPU_RSR_ALL_MEM         63
+
+/* Individual bits in the DR/IR ACR */
+#define MPU_ACR_XN              (1 << 12)
+#define MPU_ACR_SHARED          (1 << 2)
+
+/* C, B and TEX[2:0] bits only have semantic meanings when grouped */
+#define MPU_RGN_CACHEABLE       0xB
+#define MPU_RGN_SHARED_CACHEABLE (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#define MPU_RGN_STRONGLY_ORDERED 0
+
+/* Main region should only be shared for SMP */
+#ifdef CONFIG_SMP
+#define MPU_RGN_NORMAL          (MPU_RGN_CACHEABLE | MPU_ACR_SHARED)
+#else
+#define MPU_RGN_NORMAL          MPU_RGN_CACHEABLE
+#endif
+
+/* Access permission bits of ACR (only define those that we use)*/
+#define MPU_AP_PL1RW_PL0RW      (0x3 << 8)
+#define MPU_AP_PL1RW_PL0R0      (0x2 << 8)
+#define MPU_AP_PL1RW_PL0NA      (0x1 << 8)
+
+/* For minimal static MPU region configurations */
+#define MPU_PROBE_REGION        0
+#define MPU_BG_REGION           1
+#define MPU_RAM_REGION          2
+#define MPU_VECTORS_REGION      3
+
+/* Maximum number of regions Linux is interested in */
+#define MPU_MAX_REGIONS         16
+
+#define MPU_DATA_SIDE           0
+#define MPU_INSTR_SIDE          1
+
+#ifndef __ASSEMBLY__
+
+struct mpu_rgn {
+        /* Assume same attributes for d/i-side  */
+        u32 drbar;
+        u32 drsr;
+        u32 dracr;
+};
+
+struct mpu_rgn_info {
+        u32 mpuir;
+        struct mpu_rgn rgns[MPU_MAX_REGIONS];
+};
+extern struct mpu_rgn_info mpu_rgn_info;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* CONFIG_ARM_MPU */
+
+#endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 812a4944e783..6363f3d1d505 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -13,7 +13,7 @@
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT              12
 #define PAGE_SIZE               (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK               (~(PAGE_SIZE-1))
+#define PAGE_MASK               (~((1 << PAGE_SHIFT) - 1))
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
index 968c0a14e0a3..209e6504922e 100644
--- a/arch/arm/include/asm/percpu.h
+++ b/arch/arm/include/asm/percpu.h
@@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off)
 static inline unsigned long __my_cpu_offset(void)
 {
         unsigned long off;
-        /* Read TPIDRPRW */
-        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory");
+        register unsigned long *sp asm ("sp");
+
+        /*
+         * Read TPIDRPRW.
+         * We want to allow caching the value, so avoid using volatile and
+         * instead use a fake stack read to hazard against barrier().
+         */
+        asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
+
         return off;
 }
 #define __my_cpu_offset __my_cpu_offset()
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
index 18f5cef82ad5..626989fec4d3 100644
--- a/arch/arm/include/asm/pgtable-3level-hwdef.h
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -30,6 +30,7 @@
 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
 #define PMD_BIT4                (_AT(pmdval_t, 0))
 #define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
 #define PMD_APTABLE_SHIFT       (61)
@@ -41,6 +42,8 @@
  */
 #define PMD_SECT_BUFFERABLE     (_AT(pmdval_t, 1) << 2)
 #define PMD_SECT_CACHEABLE      (_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
+#define PMD_SECT_RDONLY         (_AT(pmdval_t, 1) << 7)         /* AP[2] */
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
@@ -66,6 +69,7 @@
 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
 #define PTE_BUFFERABLE          (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
 #define PTE_CACHEABLE           (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
 #define PTE_EXT_SHARED          (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
@@ -79,4 +83,24 @@
 #define PHYS_MASK_SHIFT         (40)
 #define PHYS_MASK               ((1ULL << PHYS_MASK_SHIFT) - 1)
 
+/*
+ * TTBR0/TTBR1 split (PAGE_OFFSET):
+ *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
+ *   0x80000000: T0SZ = 0, T1SZ = 1
+ *   0xc0000000: T0SZ = 0, T1SZ = 2
+ *
+ * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
+ * booting secondary CPUs would end up using TTBR1 for the identity
+ * mapping set up in TTBR0.
+ */
+#if defined CONFIG_VMSPLIT_2G
+#define TTBR1_OFFSET    16                      /* skip two L1 entries */
+#elif defined CONFIG_VMSPLIT_3G
+#define TTBR1_OFFSET    (4096 * (1 + 3))        /* only L2, skip pgd + 3*pmd */
+#else
+#define TTBR1_OFFSET    0
+#endif
+
+#define TTBR1_SIZE      (((PAGE_OFFSET >> 30) - 1) << 16)
+
 #endif
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
index 86b8fe398b95..5689c18c85f5 100644
--- a/arch/arm/include/asm/pgtable-3level.h
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -33,7 +33,7 @@
 #define PTRS_PER_PMD            512
 #define PTRS_PER_PGD            4
 
-#define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
+#define PTE_HWTABLE_PTRS        (0)
 #define PTE_HWTABLE_OFF         (0)
 #define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u64))
 
@@ -48,20 +48,28 @@
 #define PMD_SHIFT               21
 
 #define PMD_SIZE                (1UL << PMD_SHIFT)
-#define PMD_MASK                (~(PMD_SIZE-1))
+#define PMD_MASK                (~((1 << PMD_SHIFT) - 1))
 #define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+#define PGDIR_MASK              (~((1 << PGDIR_SHIFT) - 1))
 
 /*
  * section address mask and size definitions.
  */
 #define SECTION_SHIFT           21
 #define SECTION_SIZE            (1UL << SECTION_SHIFT)
-#define SECTION_MASK            (~(SECTION_SIZE-1))
+#define SECTION_MASK            (~((1 << SECTION_SHIFT) - 1))
 
 #define USER_PTRS_PER_PGD       (PAGE_OFFSET / PGDIR_SIZE)
 
 /*
+ * Hugetlb definitions.
+ */
+#define HPAGE_SHIFT             PMD_SHIFT
+#define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
+
+/*
  * "Linux" PTE definitions for LPAE.
  *
  * These bits overlap with the hardware bits but the naming is preserved for
@@ -79,6 +87,11 @@
 #define L_PTE_SPECIAL           (_AT(pteval_t, 1) << 56)        /* unused */
 #define L_PTE_NONE              (_AT(pteval_t, 1) << 57)        /* PROT_NONE */
 
+#define PMD_SECT_VALID          (_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_DIRTY          (_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING      (_AT(pmdval_t, 1) << 56)
+#define PMD_SECT_NONE           (_AT(pmdval_t, 1) << 57)
+
 /*
  * To be used in assembly code with the upper page attributes.
  */
@@ -166,8 +179,83 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
                 clean_pmd_entry(pmdp);  \
         } while (0)
 
+/*
+ * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
+ * that are written to a page table but not for ptes created with mk_pte.
+ *
+ * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
+ * hugetlb_cow, where it is compared with an entry in a page table.
+ * This comparison test fails erroneously leading ultimately to a memory leak.
+ *
+ * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
+ * present before running the comparison.
+ */
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(pte_a,pte_b)   ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG     \
+                                        : pte_val(pte_a))                               \
+                                == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG   \
+                                        : pte_val(pte_b)))
+
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
 
+#define pte_huge(pte)           (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
+#define pmd_young(pmd)          (pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)          (!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,     &= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+
+#define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
+
+/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
+#define pmd_mknotpresent(pmd)   (__pmd(0))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
+                                PMD_SECT_VALID | PMD_SECT_NONE;
+        pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+        return pmd;
+}
+
+static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                              pmd_t *pmdp, pmd_t pmd)
+{
+        BUG_ON(addr >= TASK_SIZE);
+
+        /* create a faulting entry if PROT_NONE protected */
+        if (pmd_val(pmd) & PMD_SECT_NONE)
+                pmd_val(pmd) &= ~PMD_SECT_VALID;
+
+        *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
+        flush_pmd_entry(pmdp);
+}
+
+static inline int has_transparent_hugepage(void)
+{
+        return 1;
+}
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index 7ec60d6075bf..0642228ff785 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -79,8 +79,6 @@ extern unsigned int kobjsize(const void *objp);
  * No page table caches to initialise.
  */
 #define pgtable_cache_init()    do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
-
 
 /*
  * All 32bit addresses are effectively valid for vmalloc...
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9bcd262a9008..04aeb02d2e11 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -24,6 +24,9 @@
 #include <asm/memory.h>
 #include <asm/pgtable-hwdef.h>
 
+
+#include <asm/tlbflush.h>
+
 #ifdef CONFIG_ARM_LPAE
 #include <asm/pgtable-3level.h>
 #else
@@ -318,13 +321,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define HAVE_ARCH_UNMAPPED_AREA
 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 
-/*
- * remap a physical page `pfn' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_pfn_range(vma,from,pfn,size,prot) \
-                remap_pfn_range(vma, from, pfn, size, prot)
-
 #define pgtable_cache_init() do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index f3628fb3d2b3..5324c1112f3a 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -60,7 +60,7 @@ extern struct processor {
         /*
          * Set the page table
          */
-        void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+        void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
         /*
          * Set a possibly extended PTE.  Non-extended PTEs should
          * ignore 'ext'.
@@ -82,7 +82,7 @@ extern void cpu_proc_init(void);
 extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
-extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
 #ifdef CONFIG_ARM_LPAE
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
 #else
@@ -116,13 +116,25 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
 
 #ifdef CONFIG_ARM_LPAE
+
+#define cpu_get_ttbr(nr)                                        \
+        ({                                                      \
+                u64 ttbr;                                       \
+                __asm__("mrrc   p15, " #nr ", %Q0, %R0, c2"     \
+                        : "=r" (ttbr));                         \
+                ttbr;                                           \
+        })
+
+#define cpu_set_ttbr(nr, val)                                   \
+        do {                                                    \
+                u64 ttbr = val;                                 \
+                __asm__("mcrr   p15, " #nr ", %Q0, %R0, c2"     \
+                        : : "r" (ttbr));                        \
+        } while (0)
+
 #define cpu_get_pgd()   \
         ({                                              \
-                unsigned long pg, pg2;                  \
-                __asm__("mrrc   p15, 0, %0, %1, c2"     \
-                        : "=r" (pg), "=r" (pg2)         \
-                        :                               \
-                        : "cc");                        \
+                u64 pg = cpu_get_ttbr(0);               \
                 pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
                 (pgd_t *)phys_to_virt(pg);              \
         })
@@ -137,6 +149,10 @@ extern void cpu_resume(void);
         })
 #endif
 
+#else   /*!CONFIG_MMU */
+
+#define cpu_switch_mm(pgd,mm)   { }
+
 #endif
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index ce0dbe7c1625..c4ae171850f8 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -32,5 +32,14 @@ struct psci_operations {
 };
 
 extern struct psci_operations psci_ops;
+extern struct smp_operations psci_smp_ops;
+
+#ifdef CONFIG_ARM_PSCI
+void psci_init(void);
+bool psci_smp_available(void);
+#else
+static inline void psci_init(void) { }
+static inline bool psci_smp_available(void) { return false; }
+#endif
 
 #endif /* __ASM_ARM_PSCI_H */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 3d52ee1bfb31..04c99f36ff7f 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -45,6 +45,7 @@ struct pt_regs {
  */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned long mode = regs->ARM_cpsr & MODE_MASK;
 
         /*
@@ -67,6 +68,9 @@ static inline int valid_user_regs(struct pt_regs *regs)
                 regs->ARM_cpsr |= USR_MODE;
 
         return 0;
+#else /* ifndef CONFIG_CPU_V7M */
+        return 1;
+#endif
 }
 
 static inline long regs_return_value(struct pt_regs *regs)
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index d3a22bebe6ce..a8cae71caceb 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -65,7 +65,10 @@ asmlinkage void secondary_start_kernel(void);
  * Initial data for bringing up a secondary CPU.
  */
 struct secondary_data {
-        unsigned long pgdir;
+        union {
+                unsigned long mpu_rgn_szr;
+                unsigned long pgdir;
+        };
         unsigned long swapper_pg_dir;
         void *stack;
 };
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index aaa61b6f50ff..6462a721ebd4 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -26,6 +26,9 @@ static inline bool is_smp(void)
 }
 
 /* all SMP configurations have the extended CPUID registers */
+#ifndef CONFIG_MMU
+#define tlb_ops_need_broadcast()        0
+#else
 static inline int tlb_ops_need_broadcast(void)
 {
         if (!is_smp())
@@ -33,6 +36,7 @@ static inline int tlb_ops_need_broadcast(void)
 
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
+#endif
 
 #if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
 #define cache_ops_need_broadcast()      0
@@ -49,7 +53,7 @@ static inline int cache_ops_need_broadcast(void)
 /*
  * Logical CPU mapping.
  */
-extern int __cpu_logical_map[];
+extern u32 __cpu_logical_map[];
 #define cpu_logical_map(cpu)    __cpu_logical_map[cpu]
 /*
  * Retrieve logical cpu index corresponding to a given MPIDR[23:0]
@@ -66,4 +70,22 @@ static inline int get_logical_index(u32 mpidr)
         return -EINVAL;
 }
 
+/*
+ * NOTE ! Assembly code relies on the following
+ * structure memory layout in order to carry out load
+ * multiple from its base address. For more
+ * information check arch/arm/kernel/sleep.S
+ */
+struct mpidr_hash {
+        u32     mask; /* used by sleep.S */
+        u32     shift_aff[3]; /* used by sleep.S */
+        u32     bits;
+};
+
+extern struct mpidr_hash mpidr_hash;
+
+static inline u32 mpidr_hash_size(void)
+{
+        return 1 << mpidr_hash.bits;
+}
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 6220e9fdf4c7..f8b8965666e9 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -97,19 +97,22 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
-        unsigned long tmp;
+        unsigned long contended, res;
         u32 slock;
 
-        __asm__ __volatile__(
-"       ldrex   %0, [%2]\n"
-"       subs    %1, %0, %0, ror #16\n"
-"       addeq   %0, %0, %3\n"
-"       strexeq %1, %0, [%2]"
-        : "=&r" (slock), "=&r" (tmp)
-        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
-        : "cc");
-
-        if (tmp == 0) {
+        do {
+                __asm__ __volatile__(
+                "       ldrex   %0, [%3]\n"
+                "       mov     %2, #0\n"
+                "       subs    %1, %0, %0, ror #16\n"
+                "       addeq   %0, %0, %4\n"
+                "       strexeq %2, %0, [%3]"
+                : "=&r" (slock), "=&r" (contended), "=r" (res)
+                : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
+                : "cc");
+        } while (res);
+
+        if (!contended) {
                 smp_mb();
                 return 1;
         } else {
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index 1c0a551ae375..cd20029bcd94 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,6 +1,11 @@
 #ifndef __ASM_ARM_SUSPEND_H
 #define __ASM_ARM_SUSPEND_H
 
+struct sleep_save_sp {
+        u32 *save_ptr_stash;
+        u32 save_ptr_stash_phys;
+};
+
 extern void cpu_resume(void);
 extern int cpu_suspend(unsigned long, int (*)(unsigned long));
 
diff --git a/arch/arm/include/asm/system_info.h b/arch/arm/include/asm/system_info.h
index dfd386d0c022..720ea0320a6d 100644
--- a/arch/arm/include/asm/system_info.h
+++ b/arch/arm/include/asm/system_info.h
@@ -11,6 +11,7 @@
 #define CPU_ARCH_ARMv5TEJ       7
 #define CPU_ARCH_ARMv6          8
 #define CPU_ARCH_ARMv7          9
+#define CPU_ARCH_ARMv7M         10
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 1995d1a84060..214d4158089a 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -58,7 +58,7 @@ struct thread_info {
         struct cpu_context_save cpu_context;    /* cpu context */
         __u32                   syscall;        /* syscall number */
         __u8                    used_cp[16];    /* thread used copro */
-        unsigned long           tp_value;
+        unsigned long           tp_value[2];    /* TLS registers */
 #ifdef CONFIG_CRUNCH
         struct crunch_state     crunchstate;
 #endif
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index bdf2b8458ec1..46e7cfb3e721 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -204,6 +204,12 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 #endif
 }
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+        tlb_add_flush(tlb, addr);
+}
+
 #define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)   __pmd_free_tlb(tlb, pmdp, addr)
 #define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index a3625d141c1d..fdbb9e369745 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -535,8 +535,33 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 }
 #endif
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
-#endif /* CONFIG_MMU */
+#elif defined(CONFIG_SMP)       /* !CONFIG_MMU */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/mm_types.h>
+
+static inline void local_flush_tlb_all(void)                                                                    { }
+static inline void local_flush_tlb_mm(struct mm_struct *mm)                                                     { }
+static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)                        { }
+static inline void local_flush_tlb_kernel_page(unsigned long kaddr)                                             { }
+static inline void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)    { }
+static inline void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)                         { }
+static inline void local_flush_bp_all(void)                                                                     { }
+
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
+extern void flush_tlb_kernel_page(unsigned long kaddr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void flush_bp_all(void);
+#endif  /* __ASSEMBLY__ */
+
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 73409e6c0251..83259b873333 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -2,27 +2,30 @@
 #define __ASMARM_TLS_H
 
 #ifdef __ASSEMBLY__
-        .macro set_tls_none, tp, tmp1, tmp2
+#include <asm/asm-offsets.h>
+        .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
         .endm
 
-        .macro set_tls_v6k, tp, tmp1, tmp2
+        .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
+        mrc     p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
         mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
-        mov     \tmp1, #0
-        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
+        mcr     p15, 0, \tpuser, c13, c0, 2     @ and the user r/w register
+        str     \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
         .endm
 
-        .macro set_tls_v6, tp, tmp1, tmp2
+        .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
         ldr     \tmp1, =elf_hwcap
         ldr     \tmp1, [\tmp1, #0]
         mov     \tmp2, #0xffff0fff
         tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
-        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
-        movne   \tmp1, #0
-        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
+        mrcne   p15, 0, \tmp2, c13, c0, 2       @ get the user r/w register
+        mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        mcrne   p15, 0, \tpuser, c13, c0, 2     @ set user r/w register
+        strne   \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
         .endm
 
-        .macro set_tls_software, tp, tmp1, tmp2
+        .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
         mov     \tmp1, #0xffff0fff
         str     \tp, [\tmp1, #-15]              @ set TLS value at 0xffff0ff0
         .endm
@@ -31,19 +34,30 @@
 #ifdef CONFIG_TLS_REG_EMUL
 #define tls_emu         1
 #define has_tls_reg             1
-#define set_tls         set_tls_none
+#define switch_tls      switch_tls_none
 #elif defined(CONFIG_CPU_V6)
 #define tls_emu         0
 #define has_tls_reg             (elf_hwcap & HWCAP_TLS)
-#define set_tls         set_tls_v6
+#define switch_tls      switch_tls_v6
 #elif defined(CONFIG_CPU_32v6K)
 #define tls_emu         0
 #define has_tls_reg             1
-#define set_tls         set_tls_v6k
+#define switch_tls      switch_tls_v6k
 #else
 #define tls_emu         0
 #define has_tls_reg             0
-#define set_tls         set_tls_software
+#define switch_tls      switch_tls_software
 #endif
 
+#ifndef __ASSEMBLY__
+static inline unsigned long get_tpuser(void)
+{
+        unsigned long reg = 0;
+
+        if (has_tls_reg && !tls_emu)
+                __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
+
+        return reg;
+}
+#endif
 #endif  /* __ASMARM_TLS_H */
diff --git a/arch/arm/include/asm/v7m.h b/arch/arm/include/asm/v7m.h
new file mode 100644
index 000000000000..fa88d09fa3d9
--- /dev/null
+++ b/arch/arm/include/asm/v7m.h
@@ -0,0 +1,44 @@
+/*
+ * Common defines for v7m cpus
+ */
+#define V7M_SCS_ICTR                    IOMEM(0xe000e004)
+#define V7M_SCS_ICTR_INTLINESNUM_MASK           0x0000000f
+
+#define BASEADDR_V7M_SCB                IOMEM(0xe000ed00)
+
+#define V7M_SCB_CPUID                   0x00
+
+#define V7M_SCB_ICSR                    0x04
+#define V7M_SCB_ICSR_PENDSVSET                  (1 << 28)
+#define V7M_SCB_ICSR_PENDSVCLR                  (1 << 27)
+#define V7M_SCB_ICSR_RETTOBASE                  (1 << 11)
+
+#define V7M_SCB_VTOR                    0x08
+
+#define V7M_SCB_SCR                     0x10
+#define V7M_SCB_SCR_SLEEPDEEP                   (1 << 2)
+
+#define V7M_SCB_CCR                     0x14
+#define V7M_SCB_CCR_STKALIGN                    (1 << 9)
+
+#define V7M_SCB_SHPR2                   0x1c
+#define V7M_SCB_SHPR3                   0x20
+
+#define V7M_SCB_SHCSR                   0x24
+#define V7M_SCB_SHCSR_USGFAULTENA               (1 << 18)
+#define V7M_SCB_SHCSR_BUSFAULTENA               (1 << 17)
+#define V7M_SCB_SHCSR_MEMFAULTENA               (1 << 16)
+
+#define V7M_xPSR_FRAMEPTRALIGN                  0x00000200
+#define V7M_xPSR_EXCEPTIONNO                    0x000001ff
+
+/*
+ * When branching to an address that has bits [31:28] == 0xf an exception return
+ * occurs. Bits [27:5] are reserved (SBOP). If the processor implements the FP
+ * extension Bit [4] defines if the exception frame has space allocated for FP
+ * state information, SBOP otherwise. Bit [3] defines the mode that is returned
+ * to (0 -> handler mode; 1 -> thread mode). Bit [2] defines which sp is used
+ * (0 -> msp; 1 -> psp). Bits [1:0] are fixed to 0b01.
+ */
+#define EXC_RET_STACK_MASK                      0x00000004
+#define EXC_RET_THREADMODE_PROCESSSTACK         0xfffffffd
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index 30cdacb675af..359a7b50b158 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -1,7 +1,6 @@
 #ifndef _ASM_ARM_XEN_PAGE_H
 #define _ASM_ARM_XEN_PAGE_H
 
-#include <asm/mach/map.h>
 #include <asm/page.h>
 #include <asm/pgtable.h>
 
@@ -88,6 +87,6 @@ static inline bool set_phys_to_machine(unsigned long pfn, unsigned long mfn)
         return __set_phys_to_machine(pfn, mfn);
 }
 
-#define xen_remap(cookie, size) __arm_ioremap((cookie), (size), MT_MEMORY);
+#define xen_remap(cookie, size) ioremap_cached((cookie), (size));
 
 #endif /* _ASM_ARM_XEN_PAGE_H */
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
 #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
 #define IMX6Q_UART_BASE(n)      IMX6Q_UART_BASE_ADDR(n)
 
+#define IMX6SL_UART1_BASE_ADDR  0x02020000
+#define IMX6SL_UART2_BASE_ADDR  0x02024000
+#define IMX6SL_UART3_BASE_ADDR  0x02034000
+#define IMX6SL_UART4_BASE_ADDR  0x02038000
+#define IMX6SL_UART5_BASE_ADDR  0x02018000
+#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
+#define IMX6SL_UART_BASE(n)     IMX6SL_UART_BASE_ADDR(n)
+
 #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
 
 #ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX53)
 #elif defined(CONFIG_DEBUG_IMX6Q_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6Q)
+#elif defined(CONFIG_DEBUG_IMX6SL_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6SL)
 #endif
 
 #endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/keystone.S b/arch/arm/include/debug/keystone.S
new file mode 100644
index 000000000000..9aef9ba3f4f0
--- /dev/null
+++ b/arch/arm/include/debug/keystone.S
@@ -0,0 +1,43 @@
+/*
+ * Early serial debug output macro for Keystone SOCs
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * Based on RMKs low level debug code.
+ *  Copyright (C) 1994-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+
+#define UART_SHIFT 2
+#if defined(CONFIG_DEBUG_KEYSTONE_UART0)
+#define UART_PHYS               0x02530c00
+#define UART_VIRT               0xfeb30c00
+#elif defined(CONFIG_DEBUG_KEYSTONE_UART1)
+#define UART_PHYS               0x02531000
+#define UART_VIRT               0xfeb31000
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rv, =UART_VIRT                 @ physical base address
+        ldr     \rp, =UART_PHYS                 @ virtual base address
+        .endm
+
+        .macro  senduart,rd,rx
+        str     \rd, [\rx, #UART_TX << UART_SHIFT]
+        .endm
+
+        .macro  busyuart,rd,rx
+1002:   ldr     \rd, [\rx, #UART_LSR << UART_SHIFT]
+        and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
+        bne     1002b
+        .endm
+
+        .macro  waituart,rd,rx
+        .endm
diff --git a/arch/arm/include/debug/mvebu.S b/arch/arm/include/debug/mvebu.S
index df191afa3be1..6517311a1c91 100644
--- a/arch/arm/include/debug/mvebu.S
+++ b/arch/arm/include/debug/mvebu.S
@@ -11,7 +11,12 @@
  * published by the Free Software Foundation.
 */
 
+#ifdef CONFIG_DEBUG_MVEBU_UART_ALTERNATE
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xf1000000
+#else
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#endif
+
 #define ARMADA_370_XP_REGS_VIRT_BASE    0xfec00000
 
         .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/include/debug/nspire.S b/arch/arm/include/debug/nspire.S
new file mode 100644
index 000000000000..886fd276fcbc
--- /dev/null
+++ b/arch/arm/include/debug/nspire.S
@@ -0,0 +1,28 @@
+/*
+ *      linux/arch/arm/include/debug/nspire.S
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_EARLY_UART_PHYS_BASE        0x90020000
+#define NSPIRE_EARLY_UART_VIRT_BASE        0xfee20000
+
+.macro  addruart, rp, rv, tmp
+        ldr \rp, =(NSPIRE_EARLY_UART_PHYS_BASE)         @ physical base address
+        ldr \rv, =(NSPIRE_EARLY_UART_VIRT_BASE)         @ virtual base address
+.endm
+
+
+#ifdef CONFIG_DEBUG_NSPIRE_CX_UART
+#include <asm/hardware/debug-pl01x.S>
+#endif
+
+#ifdef CONFIG_DEBUG_NSPIRE_CLASSIC_UART
+#define UART_SHIFT 2
+#include <asm/hardware/debug-8250.S>
+#endif
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
new file mode 100644
index 000000000000..cfd883e69588
--- /dev/null
+++ b/arch/arm/include/debug/rockchip.S
@@ -0,0 +1,42 @@
+/*
+ * Early serial output macro for Rockchip SoCs
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#if defined(CONFIG_DEBUG_RK29_UART0)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
+#elif defined(CONFIG_DEBUG_RK29_UART1)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
+#elif defined(CONFIG_DEBUG_RK29_UART2)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
+#elif defined(CONFIG_DEBUG_RK3X_UART0)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
+#elif defined(CONFIG_DEBUG_RK3X_UART1)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
+#elif defined(CONFIG_DEBUG_RK3X_UART2)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
+#elif defined(CONFIG_DEBUG_RK3X_UART3)
+#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
+#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
+#endif
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
+        ldr     \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
new file mode 100644
index 000000000000..e3aa58ff1776
--- /dev/null
+++ b/arch/arm/include/debug/sti.S
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/include/debug/sti.S
+ *
+ * Debugging macro include header
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define STIH41X_COMMS_BASE              0xfed00000
+#define STIH41X_ASC2_BASE               (STIH41X_COMMS_BASE+0x32000)
+
+#define STIH41X_SBC_LPM_BASE            0xfe400000
+#define STIH41X_SBC_COMMS_BASE          (STIH41X_SBC_LPM_BASE + 0x100000)
+#define STIH41X_SBC_ASC1_BASE           (STIH41X_SBC_COMMS_BASE + 0x31000)
+
+
+#define VIRT_ADDRESS(x)         (x - 0x1000000)
+
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_ASC2)
+#define DEBUG_LL_UART_BASE      STIH41X_ASC2_BASE
+#endif
+
+#if IS_ENABLED(CONFIG_STIH41X_DEBUG_SBC_ASC1)
+#define DEBUG_LL_UART_BASE      STIH41X_SBC_ASC1_BASE
+#endif
+
+#ifndef DEBUG_LL_UART_BASE
+#error "DEBUG UART is not Configured"
+#endif
+
+#define ASC_TX_BUF_OFF  0x04
+#define ASC_CTRL_OFF    0x0c
+#define ASC_STA_OFF     0x14
+
+#define ASC_STA_TX_FULL         (1<<9)
+#define ASC_STA_TX_EMPTY        (1<<1)
+
+
+                .macro  addruart, rp, rv, tmp
+                ldr     \rp,      =DEBUG_LL_UART_BASE   @ physical base
+                ldr     \rv,      =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #ASC_TX_BUF_OFF]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #ASC_STA_OFF]
+                tst     \rd, #ASC_STA_TX_FULL
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #ASC_STA_OFF]
+                tst     \rd, #ASC_STA_TX_EMPTY
+                beq     1001b
+                .endm
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
index 8ae8e4ab34b0..6f04f08a203c 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
 /*
- *
- * arch-arm/mach-u300/include/mach/debug-macro.S
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2013 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Debugging macro include header.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
-#include <mach/hardware.h>
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
 
         .macro  addruart, rp, rv, tmp
         /* If we move the address using MMU, use this. */
diff --git a/arch/arm/include/debug/vexpress.S b/arch/arm/include/debug/vexpress.S
index dc8e882a6257..acafb229e2b6 100644
--- a/arch/arm/include/debug/vexpress.S
+++ b/arch/arm/include/debug/vexpress.S
@@ -16,6 +16,8 @@
 #define DEBUG_LL_PHYS_BASE_RS1          0x1c000000
 #define DEBUG_LL_UART_OFFSET_RS1        0x00090000
 
+#define DEBUG_LL_UART_PHYS_CRX          0xb0090000
+
 #define DEBUG_LL_VIRT_BASE              0xf8000000
 
 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
@@ -67,6 +69,14 @@
 
 #include <asm/hardware/debug-pl01x.S>
 
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX)
+
+                .macro  addruart,rp,tmp,tmp2
+                ldr     \rp, =DEBUG_LL_UART_PHYS_CRX
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
 #else /* CONFIG_DEBUG_LL_UART_NONE */
 
                 .macro  addruart, rp, rv, tmp
diff --git a/arch/arm/include/uapi/asm/hwcap.h b/arch/arm/include/uapi/asm/hwcap.h
index 3688fd15a32d..6d34d080372a 100644
--- a/arch/arm/include/uapi/asm/hwcap.h
+++ b/arch/arm/include/uapi/asm/hwcap.h
@@ -25,6 +25,6 @@
 #define HWCAP_IDIVT     (1 << 18)
 #define HWCAP_VFPD32    (1 << 19)       /* set if VFP has 32 regs (not 16) */
 #define HWCAP_IDIV      (HWCAP_IDIVA | HWCAP_IDIVT)
-
+#define HWCAP_LPAE      (1 << 20)
 
 #endif /* _UAPI__ASMARM_HWCAP_H */
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h
index 96ee0929790f..5af0ed1b825a 100644
--- a/arch/arm/include/uapi/asm/ptrace.h
+++ b/arch/arm/include/uapi/asm/ptrace.h
@@ -34,28 +34,47 @@
 
 /*
  * PSR bits
+ * Note on V7M there is no mode contained in the PSR
  */
 #define USR26_MODE      0x00000000
 #define FIQ26_MODE      0x00000001
 #define IRQ26_MODE      0x00000002
 #define SVC26_MODE      0x00000003
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+/*
+ * Use 0 here to get code right that creates a userspace
+ * or kernel space thread.
+ */
+#define USR_MODE        0x00000000
+#define SVC_MODE        0x00000000
+#else
 #define USR_MODE        0x00000010
+#define SVC_MODE        0x00000013
+#endif
 #define FIQ_MODE        0x00000011
 #define IRQ_MODE        0x00000012
-#define SVC_MODE        0x00000013
 #define ABT_MODE        0x00000017
 #define HYP_MODE        0x0000001a
 #define UND_MODE        0x0000001b
 #define SYSTEM_MODE     0x0000001f
 #define MODE32_BIT      0x00000010
 #define MODE_MASK       0x0000001f
-#define PSR_T_BIT       0x00000020
-#define PSR_F_BIT       0x00000040
-#define PSR_I_BIT       0x00000080
-#define PSR_A_BIT       0x00000100
-#define PSR_E_BIT       0x00000200
-#define PSR_J_BIT       0x01000000
-#define PSR_Q_BIT       0x08000000
+
+#define V4_PSR_T_BIT    0x00000020      /* >= V4T, but not V7M */
+#define V7M_PSR_T_BIT   0x01000000
+#if defined(__KERNEL__) && defined(CONFIG_CPU_V7M)
+#define PSR_T_BIT       V7M_PSR_T_BIT
+#else
+/* for compatibility */
+#define PSR_T_BIT       V4_PSR_T_BIT
+#endif
+
+#define PSR_F_BIT       0x00000040      /* >= V4, but not V7M */
+#define PSR_I_BIT       0x00000080      /* >= V4, but not V7M */
+#define PSR_A_BIT       0x00000100      /* >= V6, but not V7M */
+#define PSR_E_BIT       0x00000200      /* >= V6, but not V7M */
+#define PSR_J_BIT       0x01000000      /* >= V5J, but not V7M */
+#define PSR_Q_BIT       0x08000000      /* >= V5E, including V7M */
 #define PSR_V_BIT       0x10000000
 #define PSR_C_BIT       0x20000000
 #define PSR_Z_BIT       0x40000000
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5f3338eacad2..fccfbdb03df1 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -15,7 +15,7 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y           := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
+obj-y           := elf.o entry-common.o irq.o opcodes.o \
                    process.o ptrace.o return_address.o sched_clock.o \
                    setup.o signal.o stacktrace.o sys_arm.o time.o traps.o
 
@@ -23,6 +23,12 @@ obj-$(CONFIG_ATAGS)		+= atags_parse.o
 obj-$(CONFIG_ATAGS_PROC)        += atags_proc.o
 obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += atags_compat.o
 
+ifeq ($(CONFIG_CPU_V7M),y)
+obj-y           += entry-v7m.o
+else
+obj-y           += entry-armv.o
+endif
+
 obj-$(CONFIG_OC_ETM)            += etm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -32,7 +38,10 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)   += sleep.o suspend.o
-obj-$(CONFIG_SMP)               += smp.o smp_tlb.o
+obj-$(CONFIG_SMP)               += smp.o
+ifdef CONFIG_MMU
+obj-$(CONFIG_SMP)               += smp_tlb.o
+endif
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_ARM_ARCH_TIMER)    += arch_timer.o
@@ -82,6 +91,9 @@ obj-$(CONFIG_DEBUG_LL)	+= debug.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-$(CONFIG_ARM_VIRT_EXT)      += hyp-stub.o
-obj-$(CONFIG_ARM_PSCI)          += psci.o
+ifeq ($(CONFIG_ARM_PSCI),y)
+obj-y                           += psci.o
+obj-$(CONFIG_SMP)               += psci_smp.o
+endif
 
 extra-y := $(head-y) vmlinux.lds
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index ee68cce6b48e..ded041711beb 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -23,6 +23,7 @@
 #include <asm/thread_info.h>
 #include <asm/memory.h>
 #include <asm/procinfo.h>
+#include <asm/suspend.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <linux/kbuild.h>
 
@@ -145,6 +146,11 @@ int main(void)
 #ifdef MULTI_CACHE
   DEFINE(CACHE_FLUSH_KERN_ALL,  offsetof(struct cpu_cache_fns, flush_kern_all));
 #endif
+#ifdef CONFIG_ARM_CPU_SUSPEND
+  DEFINE(SLEEP_SAVE_SP_SZ,      sizeof(struct sleep_save_sp));
+  DEFINE(SLEEP_SAVE_SP_PHYS,    offsetof(struct sleep_save_sp, save_ptr_stash_phys));
+  DEFINE(SLEEP_SAVE_SP_VIRT,    offsetof(struct sleep_save_sp, save_ptr_stash));
+#endif
   BLANK();
   DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
   DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c45489..261fcc826169 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
         return 0;
 }
 
-static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
+static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
+                            struct list_head *head)
 {
         struct pci_sys_data *sys = NULL;
         int ret;
@@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                         if (hw->scan)
                                 sys->bus = hw->scan(nr, sys);
                         else
-                                sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+                                sys->bus = pci_scan_root_bus(parent, sys->busnr,
                                                 hw->ops, sys, &sys->resources);
 
                         if (!sys->bus)
@@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
         }
 }
 
-void pci_common_init(struct hw_pci *hw)
+void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
 {
         struct pci_sys_data *sys;
         LIST_HEAD(head);
@@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
         if (hw->preinit)
                 hw->preinit();
-        pcibios_init_hw(hw, &head);
+        pcibios_init_hw(parent, hw, &head);
         if (hw->postinit)
                 hw->postinit();
 
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index 5af04f6daa33..5859c8bc727c 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
         u32 i, j, cpuidx = 1;
         u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
 
-        u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
+        u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
         bool bootcpu_valid = false;
         cpus = of_find_node_by_path("/cpus");
 
@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
         for_each_child_of_node(cpus, cpu) {
                 u32 hwid;
 
+                if (of_node_cmp(cpu->type, "cpu"))
+                        continue;
+
                 pr_debug(" * %s...\n", cpu->full_name);
                 /*
                  * A device tree containing CPU nodes with missing "reg"
@@ -149,9 +152,10 @@ void __init arm_dt_init_cpu_maps(void)
                 tmp_map[i] = hwid;
         }
 
-        if (WARN(!bootcpu_valid, "DT missing boot CPU MPIDR[23:0], "
-                                 "fall back to default cpu_logical_map\n"))
+        if (!bootcpu_valid) {
+                pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
                 return;
+        }
 
         /*
          * Since the boot CPU node contains proper data, and all nodes have
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 582b405befc5..a39cfc2a1f90 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -685,15 +685,16 @@ ENTRY(__switch_to)
  UNWIND(.fnstart        )
  UNWIND(.cantunwind     )
         add     ip, r1, #TI_CPU_SAVE
-        ldr     r3, [r2, #TI_TP_VALUE]
  ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
  THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
  THUMB( str     sp, [ip], #4               )
  THUMB( str     lr, [ip], #4               )
+        ldr     r4, [r2, #TI_TP_VALUE]
+        ldr     r5, [r2, #TI_TP_VALUE + 4]
 #ifdef CONFIG_CPU_USE_DOMAINS
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
-        set_tls r3, r4, r5
+        switch_tls r1, r4, r5, r3, r7
 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
         ldr     r7, [r2, #TI_TASK]
         ldr     r8, =__stack_chk_guard
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index bc5bc0a97131..94104bf69719 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -350,6 +350,9 @@ ENDPROC(ftrace_stub)
 
         .align  5
 ENTRY(vector_swi)
+#ifdef CONFIG_CPU_V7M
+        v7m_exception_entry
+#else
         sub     sp, sp, #S_FRAME_SIZE
         stmia   sp, {r0 - r12}                  @ Calling r0 - r12
  ARM(   add     r8, sp, #S_PC           )
@@ -360,8 +363,19 @@ ENTRY(vector_swi)
         str     lr, [sp, #S_PC]                 @ Save calling PC
         str     r8, [sp, #S_PSR]                @ Save CPSR
         str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
+#endif
         zero_fp
 
+#ifdef CONFIG_ALIGNMENT_TRAP
+        ldr     ip, __cr_alignment
+        ldr     ip, [ip]
+        mcr     p15, 0, ip, c1, c0              @ update control register
+#endif
+
+        enable_irq
+        ct_user_exit
+        get_thread_info tsk
+
         /*
          * Get the system call number.
          */
@@ -375,9 +389,9 @@ ENTRY(vector_swi)
 #ifdef CONFIG_ARM_THUMB
         tst     r8, #PSR_T_BIT
         movne   r10, #0                         @ no thumb OABI emulation
-        ldreq   r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldreq   r10, [lr, #-4]          )       @ get SWI instruction
 #else
-        ldr     r10, [lr, #-4]                  @ get SWI instruction
+ USER(  ldr     r10, [lr, #-4]          )       @ get SWI instruction
 #endif
 #ifdef CONFIG_CPU_ENDIAN_BE8
         rev     r10, r10                        @ little endian instruction
@@ -392,22 +406,13 @@ ENTRY(vector_swi)
         /* Legacy ABI only, possibly thumb mode. */
         tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
         addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
-        ldreq   scno, [lr, #-4]
+ USER(  ldreq   scno, [lr, #-4]         )
 
 #else
         /* Legacy ABI only. */
-        ldr     scno, [lr, #-4]                 @ get SWI instruction
+ USER(  ldr     scno, [lr, #-4]         )       @ get SWI instruction
 #endif
 
-#ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     ip, __cr_alignment
-        ldr     ip, [ip]
-        mcr     p15, 0, ip, c1, c0              @ update control register
-#endif
-        enable_irq
-        ct_user_exit
-
-        get_thread_info tsk
         adr     tbl, sys_call_table             @ load syscall table pointer
 
 #if defined(CONFIG_OABI_COMPAT)
@@ -442,6 +447,21 @@ local_restart:
         eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
         bcs     arm_syscall     
         b       sys_ni_syscall                  @ not private func
+
+#if defined(CONFIG_OABI_COMPAT) || !defined(CONFIG_AEABI)
+        /*
+         * We failed to handle a fault trying to access the page
+         * containing the swi instruction, but we're not really in a
+         * position to return -EFAULT. Instead, return back to the
+         * instruction and re-enter the user fault handling path trying
+         * to page it in. This will likely result in sending SEGV to the
+         * current task.
+         */
+9001:
+        sub     lr, lr, #4
+        str     lr, [sp, #S_PC]
+        b       ret_fast_syscall
+#endif
 ENDPROC(vector_swi)
 
         /*
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 160f3376ba6d..de23a9beed13 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -5,6 +5,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/errno.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
 
 @ Bad Abort numbers
 @ -----------------
@@ -44,6 +45,116 @@
 #endif
         .endm
 
+#ifdef CONFIG_CPU_V7M
+/*
+ * ARMv7-M exception entry/exit macros.
+ *
+ * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
+ * automatically saved on the current stack (32 words) before
+ * switching to the exception stack (SP_main).
+ *
+ * If exception is taken while in user mode, SP_main is
+ * empty. Otherwise, SP_main is aligned to 64 bit automatically
+ * (CCR.STKALIGN set).
+ *
+ * Linux assumes that the interrupts are disabled when entering an
+ * exception handler and it may BUG if this is not the case. Interrupts
+ * are disabled during entry and reenabled in the exit macro.
+ *
+ * v7m_exception_slow_exit is used when returning from SVC or PendSV.
+ * When returning to kernel mode, we don't return from exception.
+ */
+        .macro  v7m_exception_entry
+        @ determine the location of the registers saved by the core during
+        @ exception entry. Depending on the mode the cpu was in when the
+        @ exception happend that is either on the main or the process stack.
+        @ Bit 2 of EXC_RETURN stored in the lr register specifies which stack
+        @ was used.
+        tst     lr, #EXC_RET_STACK_MASK
+        mrsne   r12, psp
+        moveq   r12, sp
+
+        @ we cannot rely on r0-r3 and r12 matching the value saved in the
+        @ exception frame because of tail-chaining. So these have to be
+        @ reloaded.
+        ldmia   r12!, {r0-r3}
+
+        @ Linux expects to have irqs off. Do it here before taking stack space
+        cpsid   i
+
+        sub     sp, #S_FRAME_SIZE-S_IP
+        stmdb   sp!, {r0-r11}
+
+        @ load saved r12, lr, return address and xPSR.
+        @ r0-r7 are used for signals and never touched from now on. Clobbering
+        @ r8-r12 is OK.
+        mov     r9, r12
+        ldmia   r9!, {r8, r10-r12}
+
+        @ calculate the original stack pointer value.
+        @ r9 currently points to the memory location just above the auto saved
+        @ xPSR.
+        @ The cpu might automatically 8-byte align the stack. Bit 9
+        @ of the saved xPSR specifies if stack aligning took place. In this case
+        @ another 32-bit value is included in the stack.
+
+        tst     r12, V7M_xPSR_FRAMEPTRALIGN
+        addne   r9, r9, #4
+
+        @ store saved r12 using str to have a register to hold the base for stm
+        str     r8, [sp, #S_IP]
+        add     r8, sp, #S_SP
+        @ store r13-r15, xPSR
+        stmia   r8!, {r9-r12}
+        @ store old_r0
+        str     r0, [r8]
+        .endm
+
+        /*
+         * PENDSV and SVCALL are configured to have the same exception
+         * priorities. As a kernel thread runs at SVCALL execution priority it
+         * can never be preempted and so we will never have to return to a
+         * kernel thread here.
+         */
+        .macro  v7m_exception_slow_exit ret_r0
+        cpsid   i
+        ldr     lr, =EXC_RET_THREADMODE_PROCESSSTACK
+
+        @ read original r12, sp, lr, pc and xPSR
+        add     r12, sp, #S_IP
+        ldmia   r12, {r1-r5}
+
+        @ an exception frame is always 8-byte aligned. To tell the hardware if
+        @ the sp to be restored is aligned or not set bit 9 of the saved xPSR
+        @ accordingly.
+        tst     r2, #4
+        subne   r2, r2, #4
+        orrne   r5, V7M_xPSR_FRAMEPTRALIGN
+        biceq   r5, V7M_xPSR_FRAMEPTRALIGN
+
+        @ write basic exception frame
+        stmdb   r2!, {r1, r3-r5}
+        ldmia   sp, {r1, r3-r5}
+        .if     \ret_r0
+        stmdb   r2!, {r0, r3-r5}
+        .else
+        stmdb   r2!, {r1, r3-r5}
+        .endif
+
+        @ restore process sp
+        msr     psp, r2
+
+        @ restore original r4-r11
+        ldmia   sp!, {r0-r11}
+
+        @ restore main sp
+        add     sp, sp, #S_FRAME_SIZE-S_IP
+
+        cpsie   i
+        bx      lr
+        .endm
+#endif  /* CONFIG_CPU_V7M */
+
         @
         @ Store/load the USER SP and LR registers by switching to the SYS
         @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
@@ -165,6 +276,18 @@
         rfeia   sp!
         .endm
 
+#ifdef CONFIG_CPU_V7M
+        /*
+         * Note we don't need to do clrex here as clearing the local monitor is
+         * part of each exception entry and exit sequence.
+         */
+        .macro  restore_user_regs, fast = 0, offset = 0
+        .if     \offset
+        add     sp, #\offset
+        .endif
+        v7m_exception_slow_exit ret_r0 = \fast
+        .endm
+#else   /* ifdef CONFIG_CPU_V7M */
         .macro  restore_user_regs, fast = 0, offset = 0
         clrex                                   @ clear the exclusive monitor
         mov     r2, sp
@@ -181,6 +304,7 @@
         add     sp, sp, #S_FRAME_SIZE - S_SP
         movs    pc, lr                          @ return & move spsr_svc into cpsr
         .endm
+#endif  /* ifdef CONFIG_CPU_V7M / else */
 
         .macro  get_thread_info, rd
         mov     \rd, sp
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S
new file mode 100644
index 000000000000..e00621f1403f
--- /dev/null
+++ b/arch/arm/kernel/entry-v7m.S
@@ -0,0 +1,143 @@
+/*
+ * linux/arch/arm/kernel/entry-v7m.S
+ *
+ * Copyright (C) 2008 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Low-level vector interface routines for the ARMv7-M architecture
+ */
+#include <asm/memory.h>
+#include <asm/glue.h>
+#include <asm/thread_notify.h>
+#include <asm/v7m.h>
+
+#include <mach/entry-macro.S>
+
+#include "entry-header.S"
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+#error "CONFIG_TRACE_IRQFLAGS not supported on the current ARMv7M implementation"
+#endif
+
+__invalid_entry:
+        v7m_exception_entry
+        adr     r0, strerr
+        mrs     r1, ipsr
+        mov     r2, lr
+        bl      printk
+        mov     r0, sp
+        bl      show_regs
+1:      b       1b
+ENDPROC(__invalid_entry)
+
+strerr: .asciz  "\nUnhandled exception: IPSR = %08lx LR = %08lx\n"
+
+        .align  2
+__irq_entry:
+        v7m_exception_entry
+
+        @
+        @ Invoke the IRQ handler
+        @
+        mrs     r0, ipsr
+        ldr     r1, =V7M_xPSR_EXCEPTIONNO
+        and     r0, r1
+        sub     r0, #16
+        mov     r1, sp
+        stmdb   sp!, {lr}
+        @ routine called with r0 = irq number, r1 = struct pt_regs *
+        bl      nvic_do_IRQ
+
+        pop     {lr}
+        @
+        @ Check for any pending work if returning to user
+        @
+        ldr     r1, =BASEADDR_V7M_SCB
+        ldr     r0, [r1, V7M_SCB_ICSR]
+        tst     r0, V7M_SCB_ICSR_RETTOBASE
+        beq     2f
+
+        get_thread_info tsk
+        ldr     r2, [tsk, #TI_FLAGS]
+        tst     r2, #_TIF_WORK_MASK
+        beq     2f                      @ no work pending
+        mov     r0, #V7M_SCB_ICSR_PENDSVSET
+        str     r0, [r1, V7M_SCB_ICSR]  @ raise PendSV
+
+2:
+        @ registers r0-r3 and r12 are automatically restored on exception
+        @ return. r4-r7 were not clobbered in v7m_exception_entry so for
+        @ correctness they don't need to be restored. So only r8-r11 must be
+        @ restored here. The easiest way to do so is to restore r0-r7, too.
+        ldmia   sp!, {r0-r11}
+        add     sp, #S_FRAME_SIZE-S_IP
+        cpsie   i
+        bx      lr
+ENDPROC(__irq_entry)
+
+__pendsv_entry:
+        v7m_exception_entry
+
+        ldr     r1, =BASEADDR_V7M_SCB
+        mov     r0, #V7M_SCB_ICSR_PENDSVCLR
+        str     r0, [r1, V7M_SCB_ICSR]  @ clear PendSV
+
+        @ execute the pending work, including reschedule
+        get_thread_info tsk
+        mov     why, #0
+        b       ret_to_user
+ENDPROC(__pendsv_entry)
+
+/*
+ * Register switch for ARMv7-M processors.
+ * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
+ * previous and next are guaranteed not to be the same.
+ */
+ENTRY(__switch_to)
+        .fnstart
+        .cantunwind
+        add     ip, r1, #TI_CPU_SAVE
+        stmia   ip!, {r4 - r11}         @ Store most regs on stack
+        str     sp, [ip], #4
+        str     lr, [ip], #4
+        mov     r5, r0
+        add     r4, r2, #TI_CPU_SAVE
+        ldr     r0, =thread_notify_head
+        mov     r1, #THREAD_NOTIFY_SWITCH
+        bl      atomic_notifier_call_chain
+        mov     ip, r4
+        mov     r0, r5
+        ldmia   ip!, {r4 - r11}         @ Load all regs saved previously
+        ldr     sp, [ip]
+        ldr     pc, [ip, #4]!
+        .fnend
+ENDPROC(__switch_to)
+
+        .data
+        .align  8
+/*
+ * Vector table (64 words => 256 bytes natural alignment)
+ */
+ENTRY(vector_table)
+        .long   0                       @ 0 - Reset stack pointer
+        .long   __invalid_entry         @ 1 - Reset
+        .long   __invalid_entry         @ 2 - NMI
+        .long   __invalid_entry         @ 3 - HardFault
+        .long   __invalid_entry         @ 4 - MemManage
+        .long   __invalid_entry         @ 5 - BusFault
+        .long   __invalid_entry         @ 6 - UsageFault
+        .long   __invalid_entry         @ 7 - Reserved
+        .long   __invalid_entry         @ 8 - Reserved
+        .long   __invalid_entry         @ 9 - Reserved
+        .long   __invalid_entry         @ 10 - Reserved
+        .long   vector_swi              @ 11 - SVCall
+        .long   __invalid_entry         @ 12 - Debug Monitor
+        .long   __invalid_entry         @ 13 - Reserved
+        .long   __pendsv_entry          @ 14 - PendSV
+        .long   __invalid_entry         @ 15 - SysTick
+        .rept   64 - 16
+        .long   __irq_entry             @ 16..64 - External Interrupts
+        .endr
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 6a2e09c952c7..75f14cc3e073 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -17,8 +17,12 @@
 #include <asm/assembler.h>
 #include <asm/ptrace.h>
 #include <asm/asm-offsets.h>
+#include <asm/memory.h>
 #include <asm/cp15.h>
 #include <asm/thread_info.h>
+#include <asm/v7m.h>
+#include <asm/mpu.h>
+#include <asm/page.h>
 
 /*
  * Kernel startup entry point.
@@ -50,21 +54,86 @@ ENTRY(stext)
 
         setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                 @ and irqs disabled
-#ifndef CONFIG_CPU_CP15
-        ldr     r9, =CONFIG_PROCESSOR_ID
-#else
+#if defined(CONFIG_CPU_CP15)
         mrc     p15, 0, r9, c0, c0              @ get processor id
+#elif defined(CONFIG_CPU_V7M)
+        ldr     r9, =BASEADDR_V7M_SCB
+        ldr     r9, [r9, V7M_SCB_CPUID]
+#else
+        ldr     r9, =CONFIG_PROCESSOR_ID
 #endif
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?
         beq     __error_p                               @ yes, error 'p'
 
-        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
+#ifdef CONFIG_ARM_MPU
+        /* Calculate the size of a region covering just the kernel */
+        ldr     r5, =PHYS_OFFSET                @ Region start: PHYS_OFFSET
+        ldr     r6, =(_end)                     @ Cover whole kernel
+        sub     r6, r6, r5                      @ Minimum size of region to map
+        clz     r6, r6                          @ Region size must be 2^N...
+        rsb     r6, r6, #31                     @ ...so round up region size
+        lsl     r6, r6, #MPU_RSR_SZ             @ Put size in right field
+        orr     r6, r6, #(1 << MPU_RSR_EN)      @ Set region enabled bit
+        bl      __setup_mpu
+#endif
+        ldr     r13, =__mmap_switched           @ address to jump to after
+                                                @ initialising sctlr
+        adr     lr, BSYM(1f)                    @ return (PIC) address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
  THUMB( mov     pc, r12                         )
+ 1:     b       __after_proc_init
 ENDPROC(stext)
 
+#ifdef CONFIG_SMP
+        __CPUINIT
+ENTRY(secondary_startup)
+        /*
+         * Common entry point for secondary CPUs.
+         *
+         * Ensure that we're in SVC mode, and IRQs are disabled.  Lookup
+         * the processor type - there is no need to check the machine type
+         * as it has already been validated by the primary processor.
+         */
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
+#ifndef CONFIG_CPU_CP15
+        ldr     r9, =CONFIG_PROCESSOR_ID
+#else
+        mrc     p15, 0, r9, c0, c0              @ get processor id
+#endif
+        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
+        movs    r10, r5                         @ invalid processor?
+        beq     __error_p                       @ yes, error 'p'
+
+        adr     r4, __secondary_data
+        ldmia   r4, {r7, r12}
+
+#ifdef CONFIG_ARM_MPU
+        /* Use MPU region info supplied by __cpu_up */
+        ldr     r6, [r7]                        @ get secondary_data.mpu_szr
+        bl      __setup_mpu                     @ Initialize the MPU
+#endif
+
+        adr     lr, BSYM(__after_proc_init)     @ return address
+        mov     r13, r12                        @ __secondary_switched address
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
+ENDPROC(secondary_startup)
+
+ENTRY(__secondary_switched)
+        ldr     sp, [r7, #8]                    @ set up the stack pointer
+        mov     fp, #0
+        b       secondary_start_kernel
+ENDPROC(__secondary_switched)
+
+        .type   __secondary_data, %object
+__secondary_data:
+        .long   secondary_data
+        .long   __secondary_switched
+#endif /* CONFIG_SMP */
+
 /*
  * Set the Control Register and Read the process ID.
  */
@@ -95,10 +164,97 @@ __after_proc_init:
 #endif
         mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
-
-        b       __mmap_switched                 @ clear the BSS and jump
-                                                @ to start_kernel
+        mov     pc, r13
 ENDPROC(__after_proc_init)
         .ltorg
 
+#ifdef CONFIG_ARM_MPU
+
+
+/* Set which MPU region should be programmed */
+.macro set_region_nr tmp, rgnr
+        mov     \tmp, \rgnr                     @ Use static region numbers
+        mcr     p15, 0, \tmp, c6, c2, 0         @ Write RGNR
+.endm
+
+/* Setup a single MPU region, either D or I side (D-side for unified) */
+.macro setup_region bar, acr, sr, side = MPU_DATA_SIDE
+        mcr     p15, 0, \bar, c6, c1, (0 + \side)       @ I/DRBAR
+        mcr     p15, 0, \acr, c6, c1, (4 + \side)       @ I/DRACR
+        mcr     p15, 0, \sr, c6, c1, (2 + \side)                @ I/DRSR
+.endm
+
+/*
+ * Setup the MPU and initial MPU Regions. We create the following regions:
+ * Region 0: Use this for probing the MPU details, so leave disabled.
+ * Region 1: Background region - covers the whole of RAM as strongly ordered
+ * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6
+ * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page
+ *
+ * r6: Value to be written to DRSR (and IRSR if required) for MPU_RAM_REGION
+*/
+
+ENTRY(__setup_mpu)
+
+        /* Probe for v7 PMSA compliance */
+        mrc     p15, 0, r0, c0, c1, 4           @ Read ID_MMFR0
+        and     r0, r0, #(MMFR0_PMSA)           @ PMSA field
+        teq     r0, #(MMFR0_PMSAv7)             @ PMSA v7
+        bne     __error_p                       @ Fail: ARM_MPU on NOT v7 PMSA
+
+        /* Determine whether the D/I-side memory map is unified. We set the
+         * flags here and continue to use them for the rest of this function */
+        mrc     p15, 0, r0, c0, c0, 4           @ MPUIR
+        ands    r5, r0, #MPUIR_DREGION_SZMASK   @ 0 size d region => No MPU
+        beq     __error_p                       @ Fail: ARM_MPU and no MPU
+        tst     r0, #MPUIR_nU                   @ MPUIR_nU = 0 for unified
+
+        /* Setup second region first to free up r6 */
+        set_region_nr r0, #MPU_RAM_REGION
+        isb
+        /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */
+        ldr     r0, =PHYS_OFFSET                @ RAM starts at PHYS_OFFSET
+        ldr     r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ PHYS_OFFSET, shared, enabled
+        beq     1f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ PHYS_OFFSET, shared, enabled
+1:      isb
+
+        /* First/background region */
+        set_region_nr r0, #MPU_BG_REGION
+        isb
+        /* Execute Never,  strongly ordered, inaccessible to PL0, rw PL1  */
+        mov     r0, #0                          @ BG region starts at 0x0
+        ldr     r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
+        mov     r6, #MPU_RSR_ALL_MEM            @ 4GB region, enabled
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ 0x0, BG region, enabled
+        beq     2f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ 0x0, BG region, enabled
+2:      isb
+
+        /* Vectors region */
+        set_region_nr r0, #MPU_VECTORS_REGION
+        isb
+        /* Shared, inaccessible to PL0, rw PL1 */
+        mov     r0, #CONFIG_VECTORS_BASE        @ Cover from VECTORS_BASE
+        ldr     r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
+        /* Writing N to bits 5:1 (RSR_SZ) --> region size 2^N+1 */
+        mov     r6, #(((PAGE_SHIFT - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN)
+
+        setup_region r0, r5, r6, MPU_DATA_SIDE  @ VECTORS_BASE, PL0 NA, enabled
+        beq     3f                              @ Memory-map not unified
+        setup_region r0, r5, r6, MPU_INSTR_SIDE @ VECTORS_BASE, PL0 NA, enabled
+3:      isb
+
+        /* Enable the MPU */
+        mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
+        bic     r0, r0, #CR_BR                  @ Disable the 'default mem-map'
+        orr     r0, r0, #CR_M                   @ Set SCTRL.M (MPU on)
+        mcr     p15, 0, r0, c1, c0, 0           @ Enable MPU
+        isb
+        mov pc,lr
+ENDPROC(__setup_mpu)
+#endif
 #include "head-common.S"
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553fe213..45e8935cae4e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -156,7 +156,7 @@ ENDPROC(stext)
  *
  * Returns:
  *  r0, r3, r5-r7 corrupted
- *  r4 = physical page table address
+ *  r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  */
 __create_page_tables:
         pgtbl   r4, r8                          @ page table address
@@ -331,6 +331,7 @@ __create_page_tables:
 #endif
 #ifdef CONFIG_ARM_LPAE
         sub     r4, r4, #0x1000         @ point to the PGD table
+        mov     r4, r4, lsr #ARCH_PGD_SHIFT
 #endif
         mov     pc, lr
 ENDPROC(__create_page_tables)
@@ -408,7 +409,7 @@ __secondary_data:
  *  r0  = cp#15 control register
  *  r1  = machine ID
  *  r2  = atags or dtb pointer
- *  r4  = page table pointer
+ *  r4  = page table (see ARCH_PGD_SHIFT in asm/memory.h)
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  */
@@ -427,10 +428,7 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
         bic     r0, r0, #CR_I
 #endif
-#ifdef CONFIG_ARM_LPAE
-        mov     r5, #0
-        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
-#else
+#ifndef CONFIG_ARM_LPAE
         mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                       domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S
index 1315c4ccfa56..4910232c4833 100644
--- a/arch/arm/kernel/hyp-stub.S
+++ b/arch/arm/kernel/hyp-stub.S
@@ -153,6 +153,13 @@ THUMB(	orr	r7, #(1 << 30)	)	@ HSCTLR.TE
         mrc     p15, 4, r7, c14, c1, 0  @ CNTHCTL
         orr     r7, r7, #3              @ PL1PCEN | PL1PCTEN
         mcr     p15, 4, r7, c14, c1, 0  @ CNTHCTL
+        mov     r7, #0
+        mcrr    p15, 4, r7, r7, c14     @ CNTVOFF
+
+        @ Disable virtual timer in case it was counting
+        mrc     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
+        bic     r7, #1                  @ Clear ENABLE
+        mcr     p15, 0, r7, c14, c3, 1  @ CNTV_CTL
 1:
 #endif
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 8ef8c9337809..4fb074c446bf 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -134,6 +134,10 @@ void machine_kexec(struct kimage *image)
         unsigned long reboot_code_buffer_phys;
         void *reboot_code_buffer;
 
+        if (num_online_cpus() > 1) {
+                pr_err("kexec: error: multiple CPUs still online\n");
+                return;
+        }
 
         page_list = image->head & PAGE_MASK;
 
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 1e9be5d25e56..85c3fb6c93c2 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -288,24 +288,16 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
 
                 if (strcmp(".ARM.exidx.init.text", secname) == 0)
                         maps[ARM_SEC_INIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].unw_sec = s;
                 else if (strcmp(".ARM.exidx", secname) == 0)
                         maps[ARM_SEC_CORE].unw_sec = s;
                 else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
                         maps[ARM_SEC_EXIT].unw_sec = s;
-                else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].unw_sec = s;
                 else if (strcmp(".init.text", secname) == 0)
                         maps[ARM_SEC_INIT].txt_sec = s;
-                else if (strcmp(".devinit.text", secname) == 0)
-                        maps[ARM_SEC_DEVINIT].txt_sec = s;
                 else if (strcmp(".text", secname) == 0)
                         maps[ARM_SEC_CORE].txt_sec = s;
                 else if (strcmp(".exit.text", secname) == 0)
                         maps[ARM_SEC_EXIT].txt_sec = s;
-                else if (strcmp(".devexit.text", secname) == 0)
-                        maps[ARM_SEC_DEVEXIT].txt_sec = s;
         }
 
         for (i = 0; i < ARM_SEC_MAX; i++)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 8c3094d0f7b7..d9f5cd4e533f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -569,6 +569,7 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                 return;
         }
 
+        perf_callchain_store(entry, regs->ARM_pc);
         tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
         while ((entry->nr < PERF_MAX_STACK_DEPTH) &&
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 282de4826abb..7f1efcd4a6e9 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -39,6 +39,7 @@
 #include <asm/thread_notify.h>
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
+#include <asm/tls.h>
 
 #ifdef CONFIG_CC_STACKPROTECTOR
 #include <linux/stackprotector.h>
@@ -184,30 +185,61 @@ int __init reboot_setup(char *str)
 
 __setup("reboot=", reboot_setup);
 
+/*
+ * Called by kexec, immediately prior to machine_kexec().
+ *
+ * This must completely disable all secondary CPUs; simply causing those CPUs
+ * to execute e.g. a RAM-based pin loop is not sufficient. This allows the
+ * kexec'd kernel to use any and all RAM as it sees fit, without having to
+ * avoid any code or data used by any SW CPU pin loop. The CPU hotplug
+ * functionality embodied in disable_nonboot_cpus() to achieve this.
+ */
 void machine_shutdown(void)
 {
-#ifdef CONFIG_SMP
-        smp_send_stop();
-#endif
+        disable_nonboot_cpus();
 }
 
+/*
+ * Halting simply requires that the secondary CPUs stop performing any
+ * activity (executing tasks, handling interrupts). smp_send_stop()
+ * achieves this.
+ */
 void machine_halt(void)
 {
-        machine_shutdown();
+        smp_send_stop();
+
         local_irq_disable();
         while (1);
 }
 
+/*
+ * Power-off simply requires that the secondary CPUs stop performing any
+ * activity (executing tasks, handling interrupts). smp_send_stop()
+ * achieves this. When the system power is turned off, it will take all CPUs
+ * with it.
+ */
 void machine_power_off(void)
 {
-        machine_shutdown();
+        smp_send_stop();
+
         if (pm_power_off)
                 pm_power_off();
 }
 
+/*
+ * Restart requires that the secondary CPUs stop performing any activity
+ * while the primary CPU resets the system. Systems with a single CPU can
+ * use soft_restart() as their machine descriptor's .restart hook, since that
+ * will cause the only available CPU to reset. Systems with multiple CPUs must
+ * provide a HW restart implementation, to ensure that all CPUs reset at once.
+ * This is required so that any code running after reset on the primary CPU
+ * doesn't have to co-ordinate with other CPUs to ensure they aren't still
+ * executing pre-reset code, and using RAM that the primary CPU's code wishes
+ * to use. Implementing such co-ordination would be essentially impossible.
+ */
 void machine_restart(char *cmd)
 {
-        machine_shutdown();
+        smp_send_stop();
 
         arm_pm_restart(reboot_mode, cmd);
 
@@ -343,7 +375,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
         clear_ptrace_hw_breakpoint(p);
 
         if (clone_flags & CLONE_SETTLS)
-                thread->tp_value = childregs->ARM_r3;
+                thread->tp_value[0] = childregs->ARM_r3;
+        thread->tp_value[1] = get_tpuser();
 
         thread_notify(THREAD_NOTIFY_COPY, thread);
 
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 36531643cc2c..46931880093d 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -158,7 +158,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
         {},
 };
 
-static int __init psci_init(void)
+void __init psci_init(void)
 {
         struct device_node *np;
         const char *method;
@@ -166,7 +166,7 @@ static int __init psci_init(void)
 
         np = of_find_matching_node(NULL, psci_of_match);
         if (!np)
-                return 0;
+                return;
 
         pr_info("probing function IDs from device-tree\n");
 
@@ -206,6 +206,5 @@ static int __init psci_init(void)
 
 out_put_node:
         of_node_put(np);
-        return 0;
+        return;
 }
-early_initcall(psci_init);
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
new file mode 100644
index 000000000000..219f1d73572a
--- /dev/null
+++ b/arch/arm/kernel/psci_smp.c
@@ -0,0 +1,84 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/init.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+
+#include <asm/psci.h>
+#include <asm/smp_plat.h>
+
+/*
+ * psci_smp assumes that the following is true about PSCI:
+ *
+ * cpu_suspend   Suspend the execution on a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * cpu_off       Power down a CPU
+ * @state        we don't currently describe affinity levels, so just pass 0.
+ * no return on successful call
+ *
+ * cpu_on        Power up a CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * @entry_point  the first instruction to be executed on return
+ * returns 0  success, < 0 on failure
+ *
+ * migrate       Migrate the context to a different CPU
+ * @cpuid        cpuid of target CPU, as from MPIDR
+ * returns 0  success, < 0 on failure
+ *
+ */
+
+extern void secondary_startup(void);
+
+static int __cpuinit psci_boot_secondary(unsigned int cpu,
+                                         struct task_struct *idle)
+{
+        if (psci_ops.cpu_on)
+                return psci_ops.cpu_on(cpu_logical_map(cpu),
+                                       __pa(secondary_startup));
+        return -ENODEV;
+}
+
+#ifdef CONFIG_HOTPLUG_CPU
+void __ref psci_cpu_die(unsigned int cpu)
+{
+       const struct psci_power_state ps = {
+               .type = PSCI_POWER_STATE_TYPE_POWER_DOWN,
+       };
+
+       if (psci_ops.cpu_off)
+               psci_ops.cpu_off(ps);
+
+       /* We should never return */
+       panic("psci: cpu %d failed to shutdown\n", cpu);
+}
+#endif
+
+bool __init psci_smp_available(void)
+{
+        /* is cpu_on available at least? */
+        return (psci_ops.cpu_on != NULL);
+}
+
+struct smp_operations __initdata psci_smp_ops = {
+        .smp_boot_secondary     = psci_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = psci_cpu_die,
+#endif
+};
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 03deeffd9f6d..2bc1514d6dbe 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -849,7 +849,7 @@ long arch_ptrace(struct task_struct *child, long request,
 #endif
 
                 case PTRACE_GET_THREAD_AREA:
-                        ret = put_user(task_thread_info(child)->tp_value,
+                        ret = put_user(task_thread_info(child)->tp_value[0],
                                        datap);
                         break;
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 1522c7ae31b0..9b653278c9e8 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -37,6 +37,7 @@
 #include <asm/cputype.h>
 #include <asm/elf.h>
 #include <asm/procinfo.h>
+#include <asm/psci.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/smp_plat.h>
@@ -128,7 +129,9 @@ struct stack {
         u32 und[3];
 } ____cacheline_aligned;
 
+#ifndef CONFIG_CPU_V7M
 static struct stack stacks[NR_CPUS];
+#endif
 
 char elf_platform[ELF_PLATFORM_SIZE];
 EXPORT_SYMBOL(elf_platform);
@@ -207,7 +210,7 @@ static const char *proc_arch[] = {
         "5TEJ",
         "6TEJ",
         "7",
-        "?(11)",
+        "7M",
         "?(12)",
         "?(13)",
         "?(14)",
@@ -216,6 +219,12 @@ static const char *proc_arch[] = {
         "?(17)",
 };
 
+#ifdef CONFIG_CPU_V7M
+static int __get_cpu_architecture(void)
+{
+        return CPU_ARCH_ARMv7M;
+}
+#else
 static int __get_cpu_architecture(void)
 {
         int cpu_arch;
@@ -248,6 +257,7 @@ static int __get_cpu_architecture(void)
 
         return cpu_arch;
 }
+#endif
 
 int __pure cpu_architecture(void)
 {
@@ -293,7 +303,9 @@ static void __init cacheid_init(void)
 {
         unsigned int arch = cpu_architecture();
 
-        if (arch >= CPU_ARCH_ARMv6) {
+        if (arch == CPU_ARCH_ARMv7M) {
+                cacheid = 0;
+        } else if (arch >= CPU_ARCH_ARMv6) {
                 unsigned int cachetype = read_cpuid_cachetype();
                 if ((cachetype & (7 << 29)) == 4 << 29) {
                         /* ARMv7 register format */
@@ -355,7 +367,7 @@ void __init early_print(const char *str, ...)
 
 static void __init cpuid_init_hwcaps(void)
 {
-        unsigned int divide_instrs;
+        unsigned int divide_instrs, vmsa;
 
         if (cpu_architecture() < CPU_ARCH_ARMv7)
                 return;
@@ -368,6 +380,11 @@ static void __init cpuid_init_hwcaps(void)
         case 1:
                 elf_hwcap |= HWCAP_IDIVT;
         }
+
+        /* LPAE implies atomic ldrd/strd instructions */
+        vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
+        if (vmsa >= 5)
+                elf_hwcap |= HWCAP_LPAE;
 }
 
 static void __init feat_v6_fixup(void)
@@ -392,6 +409,7 @@ static void __init feat_v6_fixup(void)
  */
 void notrace cpu_init(void)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned int cpu = smp_processor_id();
         struct stack *stk = &stacks[cpu];
 
@@ -442,9 +460,10 @@ void notrace cpu_init(void)
               "I" (offsetof(struct stack, und[0])),
               PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
             : "r14");
+#endif
 }
 
-int __cpu_logical_map[NR_CPUS];
+u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
 
 void __init smp_setup_processor_id(void)
 {
@@ -456,9 +475,82 @@ void __init smp_setup_processor_id(void)
         for (i = 1; i < nr_cpu_ids; ++i)
                 cpu_logical_map(i) = i == cpu ? 0 : i;
 
+        /*
+         * clear __my_cpu_offset on boot CPU to avoid hang caused by
+         * using percpu variable early, for example, lockdep will
+         * access percpu variable inside lock_release
+         */
+        set_my_cpu_offset(0);
+
         printk(KERN_INFO "Booting Linux on physical CPU 0x%x\n", mpidr);
 }
 
+struct mpidr_hash mpidr_hash;
+#ifdef CONFIG_SMP
+/**
+ * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
+ *                        level in order to build a linear index from an
+ *                        MPIDR value. Resulting algorithm is a collision
+ *                        free hash carried out through shifting and ORing
+ */
+static void __init smp_build_mpidr_hash(void)
+{
+        u32 i, affinity;
+        u32 fs[3], bits[3], ls, mask = 0;
+        /*
+         * Pre-scan the list of MPIDRS and filter out bits that do
+         * not contribute to affinity levels, ie they never toggle.
+         */
+        for_each_possible_cpu(i)
+                mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
+        pr_debug("mask of set bits 0x%x\n", mask);
+        /*
+         * Find and stash the last and first bit set at all affinity levels to
+         * check how many bits are required to represent them.
+         */
+        for (i = 0; i < 3; i++) {
+                affinity = MPIDR_AFFINITY_LEVEL(mask, i);
+                /*
+                 * Find the MSB bit and LSB bits position
+                 * to determine how many bits are required
+                 * to express the affinity level.
+                 */
+                ls = fls(affinity);
+                fs[i] = affinity ? ffs(affinity) - 1 : 0;
+                bits[i] = ls - fs[i];
+        }
+        /*
+         * An index can be created from the MPIDR by isolating the
+         * significant bits at each affinity level and by shifting
+         * them in order to compress the 24 bits values space to a
+         * compressed set of values. This is equivalent to hashing
+         * the MPIDR through shifting and ORing. It is a collision free
+         * hash though not minimal since some levels might contain a number
+         * of CPUs that is not an exact power of 2 and their bit
+         * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
+         */
+        mpidr_hash.shift_aff[0] = fs[0];
+        mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
+        mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
+                                                (bits[1] + bits[0]);
+        mpidr_hash.mask = mask;
+        mpidr_hash.bits = bits[2] + bits[1] + bits[0];
+        pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
+                                mpidr_hash.shift_aff[0],
+                                mpidr_hash.shift_aff[1],
+                                mpidr_hash.shift_aff[2],
+                                mpidr_hash.mask,
+                                mpidr_hash.bits);
+        /*
+         * 4x is an arbitrary value used to warn on a hash table much bigger
+         * than expected on most systems.
+         */
+        if (mpidr_hash_size() > 4 * num_possible_cpus())
+                pr_warn("Large number of MPIDR hash buckets detected\n");
+        sync_cache_w(&mpidr_hash);
+}
+#endif
+
 static void __init setup_processor(void)
 {
         struct proc_info_list *list;
@@ -796,10 +888,17 @@ void __init setup_arch(char **cmdline_p)
         unflatten_device_tree();
 
         arm_dt_init_cpu_maps();
+        psci_init();
 #ifdef CONFIG_SMP
         if (is_smp()) {
-                smp_set_ops(mdesc->smp);
+                if (!mdesc->smp_init || !mdesc->smp_init()) {
+                        if (psci_smp_available())
+                                smp_set_ops(&psci_smp_ops);
+                        else if (mdesc->smp)
+                                smp_set_ops(mdesc->smp);
+                }
                 smp_init_cpus();
+                smp_build_mpidr_hash();
         }
 #endif
 
@@ -872,6 +971,7 @@ static const char *hwcap_str[] = {
         "vfpv4",
         "idiva",
         "idivt",
+        "lpae",
         NULL
 };
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 296786bdbb73..1c16c35c271a 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -392,14 +392,19 @@ setup_return(struct pt_regs *regs, struct ksignal *ksig,
                 if (ksig->ka.sa.sa_flags & SA_SIGINFO)
                         idx += 3;
 
+                /*
+                 * Put the sigreturn code on the stack no matter which return
+                 * mechanism we use in order to remain ABI compliant
+                 */
                 if (__put_user(sigreturn_codes[idx],   rc) ||
                     __put_user(sigreturn_codes[idx+1], rc+1))
                         return 1;
 
-                if (cpsr & MODE32_BIT) {
+                if ((cpsr & MODE32_BIT) && !IS_ENABLED(CONFIG_ARM_MPU)) {
                         /*
                          * 32-bit code can use the new high-page
-                         * signal return code support.
+                         * signal return code support except when the MPU has
+                         * protected the vectors page from PL0
                          */
                         retcode = KERN_SIGRETURN_CODE + (idx << 2) + thumb;
                 } else {
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 987dcf33415c..db1536b8b30b 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -7,6 +7,49 @@
         .text
 
 /*
+ * Implementation of MPIDR hash algorithm through shifting
+ * and OR'ing.
+ *
+ * @dst: register containing hash result
+ * @rs0: register containing affinity level 0 bit shift
+ * @rs1: register containing affinity level 1 bit shift
+ * @rs2: register containing affinity level 2 bit shift
+ * @mpidr: register containing MPIDR value
+ * @mask: register containing MPIDR mask
+ *
+ * Pseudo C-code:
+ *
+ *u32 dst;
+ *
+ *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
+ *      u32 aff0, aff1, aff2;
+ *      u32 mpidr_masked = mpidr & mask;
+ *      aff0 = mpidr_masked & 0xff;
+ *      aff1 = mpidr_masked & 0xff00;
+ *      aff2 = mpidr_masked & 0xff0000;
+ *      dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2);
+ *}
+ * Input registers: rs0, rs1, rs2, mpidr, mask
+ * Output register: dst
+ * Note: input and output registers must be disjoint register sets
+         (eg: a macro instance with mpidr = r1 and dst = r1 is invalid)
+ */
+        .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
+        and     \mpidr, \mpidr, \mask                   @ mask out MPIDR bits
+        and     \dst, \mpidr, #0xff                     @ mask=aff0
+ ARM(   mov     \dst, \dst, lsr \rs0            )       @ dst=aff0>>rs0
+ THUMB( lsr     \dst, \dst, \rs0                )
+        and     \mask, \mpidr, #0xff00                  @ mask = aff1
+ ARM(   orr     \dst, \dst, \mask, lsr \rs1     )       @ dst|=(aff1>>rs1)
+ THUMB( lsr     \mask, \mask, \rs1              )
+ THUMB( orr     \dst, \dst, \mask               )
+        and     \mask, \mpidr, #0xff0000                @ mask = aff2
+ ARM(   orr     \dst, \dst, \mask, lsr \rs2     )       @ dst|=(aff2>>rs2)
+ THUMB( lsr     \mask, \mask, \rs2              )
+ THUMB( orr     \dst, \dst, \mask               )
+        .endm
+
+/*
  * Save CPU state for a suspend.  This saves the CPU general purpose
  * registers, and allocates space on the kernel stack to save the CPU
  * specific registers and some other data for resume.
@@ -29,12 +72,18 @@ ENTRY(__cpu_suspend)
         mov     r1, r4                  @ size of save block
         mov     r2, r5                  @ virtual SP
         ldr     r3, =sleep_save_sp
-#ifdef CONFIG_SMP
-        ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
-        ALT_UP(mov lr, #0)
-        and     lr, lr, #15
+        ldr     r3, [r3, #SLEEP_SAVE_SP_VIRT]
+        ALT_SMP(mrc p15, 0, r9, c0, c0, 5)
+        ALT_UP_B(1f)
+        ldr     r8, =mpidr_hash
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r8, {r4-r7}     @ r4 = mpidr mask (r5,r6,r7) = l[0,1,2] shifts
+        compute_mpidr_hash      lr, r5, r6, r7, r9, r4
         add     r3, r3, lr, lsl #2
-#endif
+1:
         bl      __cpu_suspend_save
         adr     lr, BSYM(cpu_suspend_abort)
         ldmfd   sp!, {r0, pc}           @ call suspend fn
@@ -81,15 +130,23 @@ ENDPROC(cpu_resume_after_mmu)
         .data
         .align
 ENTRY(cpu_resume)
-#ifdef CONFIG_SMP
-        adr     r0, sleep_save_sp
-        ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
-        ALT_UP(mov r1, #0)
-        and     r1, r1, #15
-        ldr     r0, [r0, r1, lsl #2]    @ stack phys addr
-#else
-        ldr     r0, sleep_save_sp       @ stack phys addr
-#endif
+        mov     r1, #0
+        ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
+        ALT_UP_B(1f)
+        adr     r2, mpidr_hash_ptr
+        ldr     r3, [r2]
+        add     r2, r2, r3              @ r2 = struct mpidr_hash phys address
+        /*
+         * This ldmia relies on the memory layout of the mpidr_hash
+         * struct mpidr_hash.
+         */
+        ldmia   r2, { r3-r6 }   @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
+        compute_mpidr_hash      r1, r4, r5, r6, r0, r3
+1:
+        adr     r0, _sleep_save_sp
+        ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
+        ldr     r0, [r0, r1, lsl #2]
+
         setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
         @ load phys pgd, stack, resume fn
   ARM(  ldmia   r0!, {r1, sp, pc}       )
@@ -98,7 +155,11 @@ THUMB(	mov	sp, r2			)
 THUMB(  bx      r3                      )
 ENDPROC(cpu_resume)
 
-sleep_save_sp:
-        .rept   CONFIG_NR_CPUS
-        .long   0                               @ preserve stack phys ptr here
-        .endr
+        .align 2
+mpidr_hash_ptr:
+        .long   mpidr_hash - .                  @ mpidr_hash struct offset
+
+        .type   sleep_save_sp, #object
+ENTRY(sleep_save_sp)
+_sleep_save_sp:
+        .space  SLEEP_SAVE_SP_SZ                @ struct sleep_save_sp
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 550d63cef68e..c5fb5469054b 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -45,6 +45,7 @@
 #include <asm/smp_plat.h>
 #include <asm/virt.h>
 #include <asm/mach/arch.h>
+#include <asm/mpu.h>
 
 /*
  * as from 2.5, kernels no longer have an init_tasks structure
@@ -78,6 +79,13 @@ void __init smp_set_ops(struct smp_operations *ops)
                 smp_ops = *ops;
 };
 
+static unsigned long get_arch_pgd(pgd_t *pgd)
+{
+        phys_addr_t pgdir = virt_to_phys(pgd);
+        BUG_ON(pgdir & ARCH_PGD_MASK);
+        return pgdir >> ARCH_PGD_SHIFT;
+}
+
 int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
 {
         int ret;
@@ -87,8 +95,14 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
          * its stack and the page tables.
          */
         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-        secondary_data.pgdir = virt_to_phys(idmap_pgd);
-        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
+#ifdef CONFIG_ARM_MPU
+        secondary_data.mpu_rgn_szr = mpu_rgn_info.rgns[MPU_RAM_REGION].drsr;
+#endif
+
+#ifdef CONFIG_MMU
+        secondary_data.pgdir = get_arch_pgd(idmap_pgd);
+        secondary_data.swapper_pg_dir = get_arch_pgd(swapper_pg_dir);
+#endif
         __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
         outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
@@ -112,9 +126,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *idle)
                 pr_err("CPU%u: failed to boot: %d\n", cpu, ret);
         }
 
-        secondary_data.stack = NULL;
-        secondary_data.pgdir = 0;
 
+        memset(&secondary_data, 0, sizeof(secondary_data));
         return ret;
 }
 
@@ -651,17 +664,6 @@ void smp_send_reschedule(int cpu)
         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
-#ifdef CONFIG_HOTPLUG_CPU
-static void smp_kill_cpus(cpumask_t *mask)
-{
-        unsigned int cpu;
-        for_each_cpu(cpu, mask)
-                platform_cpu_kill(cpu);
-}
-#else
-static void smp_kill_cpus(cpumask_t *mask) { }
-#endif
-
 void smp_send_stop(void)
 {
         unsigned long timeout;
@@ -679,8 +681,6 @@ void smp_send_stop(void)
 
         if (num_online_cpus() > 1)
                 pr_warning("SMP: failed to stop secondary CPUs\n");
-
-        smp_kill_cpus(&mask);
 }
 
 /*
diff --git a/arch/arm/kernel/smp_tlb.c b/arch/arm/kernel/smp_tlb.c
index 9a52a07aa40e..a98b62dca2fa 100644
--- a/arch/arm/kernel/smp_tlb.c
+++ b/arch/arm/kernel/smp_tlb.c
@@ -103,7 +103,7 @@ static void broadcast_tlb_a15_erratum(void)
 
 static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 {
-        int cpu, this_cpu;
+        int this_cpu;
         cpumask_t mask = { CPU_BITS_NONE };
 
         if (!erratum_a15_798181())
@@ -111,21 +111,7 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
 
         dummy_flush_tlb_a15_erratum();
         this_cpu = get_cpu();
-        for_each_online_cpu(cpu) {
-                if (cpu == this_cpu)
-                        continue;
-                /*
-                 * We only need to send an IPI if the other CPUs are running
-                 * the same ASID as the one being invalidated. There is no
-                 * need for locking around the active_asids check since the
-                 * switch_mm() function has at least one dmb() (as required by
-                 * this workaround) in case a context switch happens on
-                 * another CPU after the condition below.
-                 */
-                if (atomic64_read(&mm->context.id) ==
-                    atomic64_read(&per_cpu(active_asids, cpu)))
-                        cpumask_set_cpu(cpu, &mask);
-        }
+        a15_erratum_get_cpumask(this_cpu, mm, &mask);
         smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
         put_cpu();
 }
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index c59c97ea8268..41cf3cbf756d 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -1,15 +1,54 @@
 #include <linux/init.h>
+#include <linux/slab.h>
 
+#include <asm/cacheflush.h>
 #include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
+#include <asm/smp_plat.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
 
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
 
+#ifdef CONFIG_MMU
+/*
+ * Hide the first two arguments to __cpu_suspend - these are an implementation
+ * detail which platform code shouldn't have to know about.
+ */
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        struct mm_struct *mm = current->active_mm;
+        int ret;
+
+        if (!idmap_pgd)
+                return -EINVAL;
+
+        /*
+         * Provide a temporary page table with an identity mapping for
+         * the MMU-enable code, required for resuming.  On successful
+         * resume (indicated by a zero return code), we need to switch
+         * back to the correct page tables.
+         */
+        ret = __cpu_suspend(arg, fn);
+        if (ret == 0) {
+                cpu_switch_mm(mm->pgd, mm);
+                local_flush_bp_all();
+                local_flush_tlb_all();
+        }
+
+        return ret;
+}
+#else
+int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
+{
+        return __cpu_suspend(arg, fn);
+}
+#define idmap_pgd       NULL
+#endif
+
 /*
  * This is called by __cpu_suspend() to save the state, and do whatever
  * flushing is required to ensure that when the CPU goes to sleep we have
@@ -47,30 +86,19 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
                           virt_to_phys(save_ptr) + sizeof(*save_ptr));
 }
 
-/*
- * Hide the first two arguments to __cpu_suspend - these are an implementation
- * detail which platform code shouldn't have to know about.
- */
-int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
-{
-        struct mm_struct *mm = current->active_mm;
-        int ret;
-
-        if (!idmap_pgd)
-                return -EINVAL;
+extern struct sleep_save_sp sleep_save_sp;
 
-        /*
-         * Provide a temporary page table with an identity mapping for
-         * the MMU-enable code, required for resuming.  On successful
-         * resume (indicated by a zero return code), we need to switch
-         * back to the correct page tables.
-         */
-        ret = __cpu_suspend(arg, fn);
-        if (ret == 0) {
-                cpu_switch_mm(mm->pgd, mm);
-                local_flush_bp_all();
-                local_flush_tlb_all();
-        }
+static int cpu_suspend_alloc_sp(void)
+{
+        void *ctx_ptr;
+        /* ctx_ptr is an array of physical addresses */
+        ctx_ptr = kcalloc(mpidr_hash_size(), sizeof(u32), GFP_KERNEL);
 
-        return ret;
+        if (WARN_ON(!ctx_ptr))
+                return -ENOMEM;
+        sleep_save_sp.save_ptr_stash = ctx_ptr;
+        sleep_save_sp.save_ptr_stash_phys = virt_to_phys(ctx_ptr);
+        sync_cache_w(&sleep_save_sp);
+        return 0;
 }
+early_initcall(cpu_suspend_alloc_sp);
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index f10316b4ecdc..c5a59546a256 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -13,6 +13,7 @@
 
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/percpu.h>
 #include <linux/node.h>
@@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
  * cpu topology table
  */
 struct cputopo_arm cpu_topology[NR_CPUS];
+EXPORT_SYMBOL_GPL(cpu_topology);
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
 {
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 18b32e8e4497..cab094c234ee 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -581,7 +581,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
                 return regs->ARM_r0;
 
         case NR(set_tls):
-                thread->tp_value = regs->ARM_r0;
+                thread->tp_value[0] = regs->ARM_r0;
                 if (tls_emu)
                         return 0;
                 if (has_tls_reg) {
@@ -699,7 +699,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
         int reg = (instr >> 12) & 15;
         if (reg == 15)
                 return 1;
-        regs->uregs[reg] = current_thread_info()->tp_value;
+        regs->uregs[reg] = current_thread_info()->tp_value[0];
         regs->ARM_pc += 4;
         return 0;
 }
@@ -812,6 +812,7 @@ static void __init kuser_get_tls_init(unsigned long vectors)
 
 void __init early_trap_init(void *vectors_base)
 {
+#ifndef CONFIG_CPU_V7M
         unsigned long vectors = (unsigned long)vectors_base;
         extern char __stubs_start[], __stubs_end[];
         extern char __vectors_start[], __vectors_end[];
@@ -843,4 +844,11 @@ void __init early_trap_init(void *vectors_base)
 
         flush_icache_range(vectors, vectors + PAGE_SIZE);
         modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * on V7-M there is no need to copy the vector table to a dedicated
+         * memory area. The address is configurable and so a table in the kernel
+         * image can be used.
+         */
+#endif
 }
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index a871b8e00fca..fa25e4e425f6 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -70,10 +70,6 @@ SECTIONS
                 ARM_EXIT_DISCARD(EXIT_TEXT)
                 ARM_EXIT_DISCARD(EXIT_DATA)
                 EXIT_CALL
-#ifndef CONFIG_HOTPLUG
-                *(.ARM.exidx.devexit.text)
-                *(.ARM.extab.devexit.text)
-#endif
 #ifndef CONFIG_MMU
                 *(.fixup)
                 *(__ex_table)
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
index 370e1a8af6ac..ebf5015508b5 100644
--- a/arch/arm/kvm/Kconfig
+++ b/arch/arm/kvm/Kconfig
@@ -41,9 +41,9 @@ config KVM_ARM_HOST
           Provides host support for ARM processors.
 
 config KVM_ARM_MAX_VCPUS
-        int "Number maximum supported virtual CPUs per VM" if KVM_ARM_HOST
-        default 4 if KVM_ARM_HOST
-        default 0
+        int "Number maximum supported virtual CPUs per VM"
+        depends on KVM_ARM_HOST
+        default 4
         help
           Static number of max supported virtual CPUs per VM.
 
@@ -67,6 +67,4 @@ config KVM_ARM_TIMER
         ---help---
           Adds support for the Architected Timers in virtual machines
 
-source drivers/virtio/Kconfig
-
 endif # VIRTUALIZATION
diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile
index 53c5ed83d16f..d99bee4950e5 100644
--- a/arch/arm/kvm/Makefile
+++ b/arch/arm/kvm/Makefile
@@ -14,10 +14,11 @@ CFLAGS_mmu.o := -I.
 AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt)
 AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
 
-kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
+KVM := ../../../virt/kvm
+kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
 
 obj-y += kvm-arm.o init.o interrupts.o
 obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
 obj-y += coproc.o coproc_a15.o mmio.o psci.o perf.o
-obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
-obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
+obj-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+obj-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm/kvm/arch_timer.c b/arch/arm/kvm/arch_timer.c
deleted file mode 100644
index c55b6089e923..000000000000
--- a/arch/arm/kvm/arch_timer.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/cpu.h>
-#include <linux/of_irq.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-
-#include <clocksource/arm_arch_timer.h>
-#include <asm/arch_timer.h>
-
-#include <asm/kvm_vgic.h>
-#include <asm/kvm_arch_timer.h>
-
-static struct timecounter *timecounter;
-static struct workqueue_struct *wqueue;
-static struct kvm_irq_level timer_irq = {
-        .level  = 1,
-};
-
-static cycle_t kvm_phys_timer_read(void)
-{
-        return timecounter->cc->read(timecounter->cc);
-}
-
-static bool timer_is_armed(struct arch_timer_cpu *timer)
-{
-        return timer->armed;
-}
-
-/* timer_arm: as in "arm the timer", not as in ARM the company */
-static void timer_arm(struct arch_timer_cpu *timer, u64 ns)
-{
-        timer->armed = true;
-        hrtimer_start(&timer->timer, ktime_add_ns(ktime_get(), ns),
-                      HRTIMER_MODE_ABS);
-}
-
-static void timer_disarm(struct arch_timer_cpu *timer)
-{
-        if (timer_is_armed(timer)) {
-                hrtimer_cancel(&timer->timer);
-                cancel_work_sync(&timer->expired);
-                timer->armed = false;
-        }
-}
-
-static void kvm_timer_inject_irq(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        timer->cntv_ctl |= ARCH_TIMER_CTRL_IT_MASK;
-        kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id,
-                            vcpu->arch.timer_cpu.irq->irq,
-                            vcpu->arch.timer_cpu.irq->level);
-}
-
-static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
-{
-        struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
-
-        /*
-         * We disable the timer in the world switch and let it be
-         * handled by kvm_timer_sync_hwstate(). Getting a timer
-         * interrupt at this point is a sure sign of some major
-         * breakage.
-         */
-        pr_warn("Unexpected interrupt %d on vcpu %p\n", irq, vcpu);
-        return IRQ_HANDLED;
-}
-
-static void kvm_timer_inject_irq_work(struct work_struct *work)
-{
-        struct kvm_vcpu *vcpu;
-
-        vcpu = container_of(work, struct kvm_vcpu, arch.timer_cpu.expired);
-        vcpu->arch.timer_cpu.armed = false;
-        kvm_timer_inject_irq(vcpu);
-}
-
-static enum hrtimer_restart kvm_timer_expire(struct hrtimer *hrt)
-{
-        struct arch_timer_cpu *timer;
-        timer = container_of(hrt, struct arch_timer_cpu, timer);
-        queue_work(wqueue, &timer->expired);
-        return HRTIMER_NORESTART;
-}
-
-/**
- * kvm_timer_flush_hwstate - prepare to move the virt timer to the cpu
- * @vcpu: The vcpu pointer
- *
- * Disarm any pending soft timers, since the world-switch code will write the
- * virtual timer state back to the physical CPU.
- */
-void kvm_timer_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        /*
-         * We're about to run this vcpu again, so there is no need to
-         * keep the background timer running, as we're about to
-         * populate the CPU timer again.
-         */
-        timer_disarm(timer);
-}
-
-/**
- * kvm_timer_sync_hwstate - sync timer state from cpu
- * @vcpu: The vcpu pointer
- *
- * Check if the virtual timer was armed and either schedule a corresponding
- * soft timer or inject directly if already expired.
- */
-void kvm_timer_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-        cycle_t cval, now;
-        u64 ns;
-
-        if ((timer->cntv_ctl & ARCH_TIMER_CTRL_IT_MASK) ||
-                !(timer->cntv_ctl & ARCH_TIMER_CTRL_ENABLE))
-                return;
-
-        cval = timer->cntv_cval;
-        now = kvm_phys_timer_read() - vcpu->kvm->arch.timer.cntvoff;
-
-        BUG_ON(timer_is_armed(timer));
-
-        if (cval <= now) {
-                /*
-                 * Timer has already expired while we were not
-                 * looking. Inject the interrupt and carry on.
-                 */
-                kvm_timer_inject_irq(vcpu);
-                return;
-        }
-
-        ns = cyclecounter_cyc2ns(timecounter->cc, cval - now);
-        timer_arm(timer, ns);
-}
-
-void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        INIT_WORK(&timer->expired, kvm_timer_inject_irq_work);
-        hrtimer_init(&timer->timer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
-        timer->timer.function = kvm_timer_expire;
-        timer->irq = &timer_irq;
-}
-
-static void kvm_timer_init_interrupt(void *info)
-{
-        enable_percpu_irq(timer_irq.irq, 0);
-}
-
-
-static int kvm_timer_cpu_notify(struct notifier_block *self,
-                                unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                kvm_timer_init_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(timer_irq.irq);
-                break;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block kvm_timer_cpu_nb = {
-        .notifier_call = kvm_timer_cpu_notify,
-};
-
-static const struct of_device_id arch_timer_of_match[] = {
-        { .compatible   = "arm,armv7-timer",    },
-        {},
-};
-
-int kvm_timer_hyp_init(void)
-{
-        struct device_node *np;
-        unsigned int ppi;
-        int err;
-
-        timecounter = arch_timer_get_timecounter();
-        if (!timecounter)
-                return -ENODEV;
-
-        np = of_find_matching_node(NULL, arch_timer_of_match);
-        if (!np) {
-                kvm_err("kvm_arch_timer: can't find DT node\n");
-                return -ENODEV;
-        }
-
-        ppi = irq_of_parse_and_map(np, 2);
-        if (!ppi) {
-                kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
-                err = -EINVAL;
-                goto out;
-        }
-
-        err = request_percpu_irq(ppi, kvm_arch_timer_handler,
-                                 "kvm guest timer", kvm_get_running_vcpus());
-        if (err) {
-                kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
-                        ppi, err);
-                goto out;
-        }
-
-        timer_irq.irq = ppi;
-
-        err = register_cpu_notifier(&kvm_timer_cpu_nb);
-        if (err) {
-                kvm_err("Cannot register timer CPU notifier\n");
-                goto out_free;
-        }
-
-        wqueue = create_singlethread_workqueue("kvm_arch_timer");
-        if (!wqueue) {
-                err = -ENOMEM;
-                goto out_free;
-        }
-
-        kvm_info("%s IRQ%d\n", np->name, ppi);
-        on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
-
-        goto out;
-out_free:
-        free_percpu_irq(ppi, kvm_get_running_vcpus());
-out:
-        of_node_put(np);
-        return err;
-}
-
-void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
-{
-        struct arch_timer_cpu *timer = &vcpu->arch.timer_cpu;
-
-        timer_disarm(timer);
-}
-
-int kvm_timer_init(struct kvm *kvm)
-{
-        if (timecounter && wqueue) {
-                kvm->arch.timer.cntvoff = kvm_phys_timer_read();
-                kvm->arch.timer.enabled = 1;
-        }
-
-        return 0;
-}
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index ef1703b9587b..741f66a2edbd 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -800,8 +800,8 @@ long kvm_arch_vm_ioctl(struct file *filp,
 
 static void cpu_init_hyp_mode(void *dummy)
 {
-        unsigned long long boot_pgd_ptr;
-        unsigned long long pgd_ptr;
+        phys_addr_t boot_pgd_ptr;
+        phys_addr_t pgd_ptr;
         unsigned long hyp_stack_ptr;
         unsigned long stack_page;
         unsigned long vector_ptr;
@@ -809,8 +809,8 @@ static void cpu_init_hyp_mode(void *dummy)
         /* Switch from the HYP stub to our own HYP init vector */
         __hyp_set_vectors(kvm_get_idmap_vector());
 
-        boot_pgd_ptr = (unsigned long long)kvm_mmu_get_boot_httbr();
-        pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+        boot_pgd_ptr = kvm_mmu_get_boot_httbr();
+        pgd_ptr = kvm_mmu_get_httbr();
         stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
         hyp_stack_ptr = stack_page + PAGE_SIZE;
         vector_ptr = (unsigned long)__kvm_hyp_vector;
diff --git a/arch/arm/kvm/coproc.c b/arch/arm/kvm/coproc.c
index 8eea97be1ed5..4a5199070430 100644
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@@ -180,6 +180,10 @@ static const struct coproc_reg cp15_regs[] = {
                         NULL, reset_unknown, c6_DFAR },
         { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
                         NULL, reset_unknown, c6_IFAR },
+
+        /* PAR swapped by interrupt.S */
+        { CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
+
         /*
          * DC{C,I,CI}SW operations:
          */
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 3d74a0be47db..df4c82d47ad7 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -52,9 +52,6 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
-        if (kvm_psci_call(vcpu))
-                return 1;
-
         kvm_inject_undefined(vcpu);
         return 1;
 }
diff --git a/arch/arm/kvm/interrupts.S b/arch/arm/kvm/interrupts.S
index f7793df62f58..16cd4ba5d7fd 100644
--- a/arch/arm/kvm/interrupts.S
+++ b/arch/arm/kvm/interrupts.S
@@ -49,6 +49,7 @@ __kvm_hyp_code_start:
 ENTRY(__kvm_tlb_flush_vmid_ipa)
         push    {r2, r3}
 
+        dsb     ishst
         add     r0, r0, #KVM_VTTBR
         ldrd    r2, r3, [r0]
         mcrr    p15, 6, r2, r3, c2      @ Write VTTBR
@@ -291,6 +292,7 @@ THUMB(	orr	r2, r2, #PSR_T_BIT	)
         ldr     r2, =BSYM(panic)
         msr     ELR_hyp, r2
         ldr     r0, =\panic_str
+        clrex                           @ Clear exclusive monitor
         eret
 .endm
 
@@ -414,6 +416,10 @@ guest_trap:
         mrcne   p15, 4, r2, c6, c0, 4   @ HPFAR
         bne     3f
 
+        /* Preserve PAR */
+        mrrc    p15, 0, r0, r1, c7      @ PAR
+        push    {r0, r1}
+
         /* Resolve IPA using the xFAR */
         mcr     p15, 0, r2, c7, c8, 0   @ ATS1CPR
         isb
@@ -424,13 +430,20 @@ guest_trap:
         lsl     r2, r2, #4
         orr     r2, r2, r1, lsl #24
 
+        /* Restore PAR */
+        pop     {r0, r1}
+        mcrr    p15, 0, r0, r1, c7      @ PAR
+
 3:      load_vcpu                       @ Load VCPU pointer to r0
         str     r2, [r0, #VCPU_HPFAR]
 
 1:      mov     r1, #ARM_EXCEPTION_HVC
         b       __kvm_vcpu_return
 
-4:      pop     {r0, r1, r2}            @ Failed translation, return to guest
+4:      pop     {r0, r1}                @ Failed translation, return to guest
+        mcrr    p15, 0, r0, r1, c7      @ PAR
+        clrex
+        pop     {r0, r1, r2}
         eret
 
 /*
@@ -456,6 +469,7 @@ switch_to_guest_vfp:
 
         pop     {r3-r7}
         pop     {r0-r2}
+        clrex
         eret
 #endif
 
diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S
index 3c8f2f0b4c5e..6f18695a09cb 100644
--- a/arch/arm/kvm/interrupts_head.S
+++ b/arch/arm/kvm/interrupts_head.S
@@ -302,11 +302,14 @@ vcpu	.req	r0		@ vcpu pointer always in r0
         .endif
 
         mrc     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mrrc    p15, 0, r4, r5, c7      @ PAR
 
         .if \store_to_vcpu == 0
-        push    {r2}
+        push    {r2,r4-r5}
         .else
         str     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        strd    r4, r5, [r12]
         .endif
 .endm
 
@@ -319,12 +322,15 @@ vcpu	.req	r0		@ vcpu pointer always in r0
  */
 .macro write_cp15_state read_from_vcpu
         .if \read_from_vcpu == 0
-        pop     {r2}
+        pop     {r2,r4-r5}
         .else
         ldr     r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
+        add     r12, vcpu, #CP15_OFFSET(c7_PAR)
+        ldrd    r4, r5, [r12]
         .endif
 
         mcr     p15, 0, r2, c14, c1, 0  @ CNTKCTL
+        mcrr    p15, 0, r4, r5, c7      @ PAR
 
         .if \read_from_vcpu == 0
         pop     {r2-r12}
@@ -497,6 +503,10 @@ vcpu	.req	r0		@ vcpu pointer always in r0
         add     r5, vcpu, r4
         strd    r2, r3, [r5]
 
+        @ Ensure host CNTVCT == CNTPCT
+        mov     r2, #0
+        mcrr    p15, 4, r2, r2, c14     @ CNTVOFF
+
 1:
 #endif
         @ Allow physical timer/counter access for the host
diff --git a/arch/arm/kvm/mmio.c b/arch/arm/kvm/mmio.c
index 72a12f2171b2..b8e06b7a2833 100644
--- a/arch/arm/kvm/mmio.c
+++ b/arch/arm/kvm/mmio.c
@@ -86,12 +86,6 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
         sign_extend = kvm_vcpu_dabt_issext(vcpu);
         rt = kvm_vcpu_dabt_get_rd(vcpu);
 
-        if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
-                /* IO memory trying to read/write pc */
-                kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
-                return 1;
-        }
-
         mmio->is_write = is_write;
         mmio->phys_addr = fault_ipa;
         mmio->len = len;
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 84ba67b982c0..ca6bea4859b4 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -382,9 +382,6 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
         if (!pgd)
                 return -ENOMEM;
 
-        /* stage-2 pgd must be aligned to its size */
-        VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
-
         memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
         kvm_clean_pgd(pgd);
         kvm->arch.pgd = pgd;
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 7ee5bb7a3667..86a693a02ba3 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -75,7 +75,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
  * kvm_psci_call - handle PSCI call if r0 value is in range
  * @vcpu: Pointer to the VCPU struct
  *
- * Handle PSCI calls from guests through traps from HVC or SMC instructions.
+ * Handle PSCI calls from guests through traps from HVC instructions.
  * The calling convention is similar to SMC calls to the secure world where
  * the function number is placed in r0 and this function returns true if the
  * function number specified in r0 is withing the PSCI range, and false
diff --git a/arch/arm/kvm/reset.c b/arch/arm/kvm/reset.c
index b80256b554cd..b7840e7aa452 100644
--- a/arch/arm/kvm/reset.c
+++ b/arch/arm/kvm/reset.c
@@ -27,6 +27,8 @@
 #include <asm/kvm_arm.h>
 #include <asm/kvm_coproc.h>
 
+#include <kvm/arm_arch_timer.h>
+
 /******************************************************************************
  * Cortex-A15 Reset Values
  */
@@ -37,6 +39,11 @@ static struct kvm_regs a15_regs_reset = {
         .usr_regs.ARM_cpsr = SVC_MODE | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT,
 };
 
+static const struct kvm_irq_level a15_vtimer_irq = {
+        .irq = 27,
+        .level = 1,
+};
+
 
 /*******************************************************************************
  * Exported reset function
@@ -52,6 +59,7 @@ static struct kvm_regs a15_regs_reset = {
 int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
 {
         struct kvm_regs *cpu_reset;
+        const struct kvm_irq_level *cpu_vtimer_irq;
 
         switch (vcpu->arch.target) {
         case KVM_ARM_TARGET_CORTEX_A15:
@@ -59,6 +67,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
                         return -EINVAL;
                 cpu_reset = &a15_regs_reset;
                 vcpu->arch.midr = read_cpuid_id();
+                cpu_vtimer_irq = &a15_vtimer_irq;
                 break;
         default:
                 return -ENODEV;
@@ -70,5 +79,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
         /* Reset CP15 registers */
         kvm_reset_coprocs(vcpu);
 
+        /* Reset arch_timer context */
+        kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+
         return 0;
 }
diff --git a/arch/arm/kvm/vgic.c b/arch/arm/kvm/vgic.c
deleted file mode 100644
index 17c5ac7d10ed..000000000000
--- a/arch/arm/kvm/vgic.c
+++ /dev/null
@@ -1,1499 +0,0 @@
-/*
- * Copyright (C) 2012 ARM Ltd.
- * Author: Marc Zyngier <marc.zyngier@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/cpu.h>
-#include <linux/kvm.h>
-#include <linux/kvm_host.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <linux/irqchip/arm-gic.h>
-
-#include <asm/kvm_emulate.h>
-#include <asm/kvm_arm.h>
-#include <asm/kvm_mmu.h>
-
-/*
- * How the whole thing works (courtesy of Christoffer Dall):
- *
- * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
- *   something is pending
- * - VGIC pending interrupts are stored on the vgic.irq_state vgic
- *   bitmap (this bitmap is updated by both user land ioctls and guest
- *   mmio ops, and other in-kernel peripherals such as the
- *   arch. timers) and indicate the 'wire' state.
- * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
- *   recalculated
- * - To calculate the oracle, we need info for each cpu from
- *   compute_pending_for_cpu, which considers:
- *   - PPI: dist->irq_state & dist->irq_enable
- *   - SPI: dist->irq_state & dist->irq_enable & dist->irq_spi_target
- *   - irq_spi_target is a 'formatted' version of the GICD_ICFGR
- *     registers, stored on each vcpu. We only keep one bit of
- *     information per interrupt, making sure that only one vcpu can
- *     accept the interrupt.
- * - The same is true when injecting an interrupt, except that we only
- *   consider a single interrupt at a time. The irq_spi_cpu array
- *   contains the target CPU for each SPI.
- *
- * The handling of level interrupts adds some extra complexity. We
- * need to track when the interrupt has been EOIed, so we can sample
- * the 'line' again. This is achieved as such:
- *
- * - When a level interrupt is moved onto a vcpu, the corresponding
- *   bit in irq_active is set. As long as this bit is set, the line
- *   will be ignored for further interrupts. The interrupt is injected
- *   into the vcpu with the GICH_LR_EOI bit set (generate a
- *   maintenance interrupt on EOI).
- * - When the interrupt is EOIed, the maintenance interrupt fires,
- *   and clears the corresponding bit in irq_active. This allow the
- *   interrupt line to be sampled again.
- */
-
-#define VGIC_ADDR_UNDEF         (-1)
-#define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
-
-/* Physical address of vgic virtual cpu interface */
-static phys_addr_t vgic_vcpu_base;
-
-/* Virtual control interface base address */
-static void __iomem *vgic_vctrl_base;
-
-static struct device_node *vgic_node;
-
-#define ACCESS_READ_VALUE       (1 << 0)
-#define ACCESS_READ_RAZ         (0 << 0)
-#define ACCESS_READ_MASK(x)     ((x) & (1 << 0))
-#define ACCESS_WRITE_IGNORED    (0 << 1)
-#define ACCESS_WRITE_SETBIT     (1 << 1)
-#define ACCESS_WRITE_CLEARBIT   (2 << 1)
-#define ACCESS_WRITE_VALUE      (3 << 1)
-#define ACCESS_WRITE_MASK(x)    ((x) & (3 << 1))
-
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
-static void vgic_update_state(struct kvm *kvm);
-static void vgic_kick_vcpus(struct kvm *kvm);
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
-static u32 vgic_nr_lr;
-
-static unsigned int vgic_maint_irq;
-
-static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
-                                int cpuid, u32 offset)
-{
-        offset >>= 2;
-        if (!offset)
-                return x->percpu[cpuid].reg;
-        else
-                return x->shared.reg + offset - 1;
-}
-
-static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
-                                   int cpuid, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                return test_bit(irq, x->percpu[cpuid].reg_ul);
-
-        return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared.reg_ul);
-}
-
-static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
-                                    int irq, int val)
-{
-        unsigned long *reg;
-
-        if (irq < VGIC_NR_PRIVATE_IRQS) {
-                reg = x->percpu[cpuid].reg_ul;
-        } else {
-                reg =  x->shared.reg_ul;
-                irq -= VGIC_NR_PRIVATE_IRQS;
-        }
-
-        if (val)
-                set_bit(irq, reg);
-        else
-                clear_bit(irq, reg);
-}
-
-static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
-{
-        if (unlikely(cpuid >= VGIC_MAX_CPUS))
-                return NULL;
-        return x->percpu[cpuid].reg_ul;
-}
-
-static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
-{
-        return x->shared.reg_ul;
-}
-
-static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
-{
-        offset >>= 2;
-        BUG_ON(offset > (VGIC_NR_IRQS / 4));
-        if (offset < 4)
-                return x->percpu[cpuid] + offset;
-        else
-                return x->shared + offset - 8;
-}
-
-#define VGIC_CFG_LEVEL  0
-#define VGIC_CFG_EDGE   1
-
-static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int irq_val;
-
-        irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
-        return irq_val == VGIC_CFG_EDGE;
-}
-
-static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
-}
-
-static int vgic_irq_is_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_active, vcpu->vcpu_id, irq);
-}
-
-static void vgic_irq_set_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 1);
-}
-
-static void vgic_irq_clear_active(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_active, vcpu->vcpu_id, irq, 0);
-}
-
-static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        return vgic_bitmap_get_irq_val(&dist->irq_state, vcpu->vcpu_id, irq);
-}
-
-static void vgic_dist_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 1);
-}
-
-static void vgic_dist_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        vgic_bitmap_set_irq_val(&dist->irq_state, vcpu->vcpu_id, irq, 0);
-}
-
-static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                set_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                        vcpu->arch.vgic_cpu.pending_shared);
-}
-
-static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
-{
-        if (irq < VGIC_NR_PRIVATE_IRQS)
-                clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
-        else
-                clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
-                          vcpu->arch.vgic_cpu.pending_shared);
-}
-
-static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
-{
-        return *((u32 *)mmio->data) & mask;
-}
-
-static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
-{
-        *((u32 *)mmio->data) = value & mask;
-}
-
-/**
- * vgic_reg_access - access vgic register
- * @mmio:   pointer to the data describing the mmio access
- * @reg:    pointer to the virtual backing of vgic distributor data
- * @offset: least significant 2 bits used for word offset
- * @mode:   ACCESS_ mode (see defines above)
- *
- * Helper to make vgic register access easier using one of the access
- * modes defined for vgic register access
- * (read,raz,write-ignored,setbit,clearbit,write)
- */
-static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
-                            phys_addr_t offset, int mode)
-{
-        int word_offset = (offset & 3) * 8;
-        u32 mask = (1UL << (mmio->len * 8)) - 1;
-        u32 regval;
-
-        /*
-         * Any alignment fault should have been delivered to the guest
-         * directly (ARM ARM B3.12.7 "Prioritization of aborts").
-         */
-
-        if (reg) {
-                regval = *reg;
-        } else {
-                BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
-                regval = 0;
-        }
-
-        if (mmio->is_write) {
-                u32 data = mmio_data_read(mmio, mask) << word_offset;
-                switch (ACCESS_WRITE_MASK(mode)) {
-                case ACCESS_WRITE_IGNORED:
-                        return;
-
-                case ACCESS_WRITE_SETBIT:
-                        regval |= data;
-                        break;
-
-                case ACCESS_WRITE_CLEARBIT:
-                        regval &= ~data;
-                        break;
-
-                case ACCESS_WRITE_VALUE:
-                        regval = (regval & ~(mask << word_offset)) | data;
-                        break;
-                }
-                *reg = regval;
-        } else {
-                switch (ACCESS_READ_MASK(mode)) {
-                case ACCESS_READ_RAZ:
-                        regval = 0;
-                        /* fall through */
-
-                case ACCESS_READ_VALUE:
-                        mmio_data_write(mmio, mask, regval >> word_offset);
-                }
-        }
-}
-
-static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
-                             struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        u32 word_offset = offset & 3;
-
-        switch (offset & ~3) {
-        case 0:                 /* CTLR */
-                reg = vcpu->kvm->arch.vgic.enabled;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-                if (mmio->is_write) {
-                        vcpu->kvm->arch.vgic.enabled = reg & 1;
-                        vgic_update_state(vcpu->kvm);
-                        return true;
-                }
-                break;
-
-        case 4:                 /* TYPER */
-                reg  = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
-                reg |= (VGIC_NR_IRQS >> 5) - 1;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-
-        case 8:                 /* IIDR */
-                reg = 0x4B00043B;
-                vgic_reg_access(mmio, &reg, word_offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                break;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
-                               struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        vgic_reg_access(mmio, NULL, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
-        return false;
-}
-
-static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
-                                         struct kvm_exit_mmio *mmio,
-                                         phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                if (offset < 4) /* Force SGI enabled */
-                        *reg |= 0xffff;
-                vgic_retire_disabled_irqs(vcpu);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
-                                        struct kvm_exit_mmio *mmio,
-                                        phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
-                                          struct kvm_exit_mmio *mmio,
-                                          phys_addr_t offset)
-{
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_state,
-                                       vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
-        if (mmio->is_write) {
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
-                                     struct kvm_exit_mmio *mmio,
-                                     phys_addr_t offset)
-{
-        u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
-                                        vcpu->vcpu_id, offset);
-        vgic_reg_access(mmio, reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        return false;
-}
-
-#define GICD_ITARGETSR_SIZE     32
-#define GICD_CPUTARGETS_BITS    8
-#define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
-static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 val = 0;
-
-        irq -= VGIC_NR_PRIVATE_IRQS;
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
-                        if (test_bit(irq + i, bmap))
-                                val |= 1 << (c + i * 8);
-        }
-
-        return val;
-}
-
-static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int i, c;
-        unsigned long *bmap;
-        u32 target;
-
-        irq -= VGIC_NR_PRIVATE_IRQS;
-
-        /*
-         * Pick the LSB in each byte. This ensures we target exactly
-         * one vcpu per IRQ. If the byte is null, assume we target
-         * CPU0.
-         */
-        for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
-                int shift = i * GICD_CPUTARGETS_BITS;
-                target = ffs((val >> shift) & 0xffU);
-                target = target ? (target - 1) : 0;
-                dist->irq_spi_cpu[irq + i] = target;
-                kvm_for_each_vcpu(c, vcpu, kvm) {
-                        bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
-                        if (c == target)
-                                set_bit(irq + i, bmap);
-                        else
-                                clear_bit(irq + i, bmap);
-                }
-        }
-}
-
-static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
-                                   struct kvm_exit_mmio *mmio,
-                                   phys_addr_t offset)
-{
-        u32 reg;
-
-        /* We treat the banked interrupts targets as read-only */
-        if (offset < 32) {
-                u32 roreg = 1 << vcpu->vcpu_id;
-                roreg |= roreg << 8;
-                roreg |= roreg << 16;
-
-                vgic_reg_access(mmio, &roreg, offset,
-                                ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
-                return false;
-        }
-
-        reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-static u32 vgic_cfg_expand(u16 val)
-{
-        u32 res = 0;
-        int i;
-
-        /*
-         * Turn a 16bit value like abcd...mnop into a 32bit word
-         * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
-
-        return res;
-}
-
-static u16 vgic_cfg_compress(u32 val)
-{
-        u16 res = 0;
-        int i;
-
-        /*
-         * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
-         * abcd...mnop which is what we really care about.
-         */
-        for (i = 0; i < 16; i++)
-                res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
-
-        return res;
-}
-
-/*
- * The distributor uses 2 bits per IRQ for the CFG register, but the
- * LSB is always 0. As such, we only keep the upper bit, and use the
- * two above functions to compress/expand the bits
- */
-static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 val;
-        u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
-                                       vcpu->vcpu_id, offset >> 1);
-        if (offset & 2)
-                val = *reg >> 16;
-        else
-                val = *reg & 0xffff;
-
-        val = vgic_cfg_expand(val);
-        vgic_reg_access(mmio, &val, offset,
-                        ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                if (offset < 4) {
-                        *reg = ~0U; /* Force PPIs/SGIs to 1 */
-                        return false;
-                }
-
-                val = vgic_cfg_compress(val);
-                if (offset & 2) {
-                        *reg &= 0xffff;
-                        *reg |= val << 16;
-                } else {
-                        *reg &= 0xffff << 16;
-                        *reg |= val;
-                }
-        }
-
-        return false;
-}
-
-static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
-                                struct kvm_exit_mmio *mmio, phys_addr_t offset)
-{
-        u32 reg;
-        vgic_reg_access(mmio, &reg, offset,
-                        ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
-        if (mmio->is_write) {
-                vgic_dispatch_sgi(vcpu, reg);
-                vgic_update_state(vcpu->kvm);
-                return true;
-        }
-
-        return false;
-}
-
-/*
- * I would have liked to use the kvm_bus_io_*() API instead, but it
- * cannot cope with banked registers (only the VM pointer is passed
- * around, and we need the vcpu). One of these days, someone please
- * fix it!
- */
-struct mmio_range {
-        phys_addr_t base;
-        unsigned long len;
-        bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
-                            phys_addr_t offset);
-};
-
-static const struct mmio_range vgic_ranges[] = {
-        {
-                .base           = GIC_DIST_CTRL,
-                .len            = 12,
-                .handle_mmio    = handle_mmio_misc,
-        },
-        {
-                .base           = GIC_DIST_IGROUP,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_ENABLE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_enable_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_set_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_PENDING_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_clear_pending_reg,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_SET,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_ACTIVE_CLEAR,
-                .len            = VGIC_NR_IRQS / 8,
-                .handle_mmio    = handle_mmio_raz_wi,
-        },
-        {
-                .base           = GIC_DIST_PRI,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_priority_reg,
-        },
-        {
-                .base           = GIC_DIST_TARGET,
-                .len            = VGIC_NR_IRQS,
-                .handle_mmio    = handle_mmio_target_reg,
-        },
-        {
-                .base           = GIC_DIST_CONFIG,
-                .len            = VGIC_NR_IRQS / 4,
-                .handle_mmio    = handle_mmio_cfg_reg,
-        },
-        {
-                .base           = GIC_DIST_SOFTINT,
-                .len            = 4,
-                .handle_mmio    = handle_mmio_sgi_reg,
-        },
-        {}
-};
-
-static const
-struct mmio_range *find_matching_range(const struct mmio_range *ranges,
-                                       struct kvm_exit_mmio *mmio,
-                                       phys_addr_t base)
-{
-        const struct mmio_range *r = ranges;
-        phys_addr_t addr = mmio->phys_addr - base;
-
-        while (r->len) {
-                if (addr >= r->base &&
-                    (addr + mmio->len) <= (r->base + r->len))
-                        return r;
-                r++;
-        }
-
-        return NULL;
-}
-
-/**
- * vgic_handle_mmio - handle an in-kernel MMIO access
- * @vcpu:       pointer to the vcpu performing the access
- * @run:        pointer to the kvm_run structure
- * @mmio:       pointer to the data describing the access
- *
- * returns true if the MMIO access has been performed in kernel space,
- * and false if it needs to be emulated in user space.
- */
-bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
-                      struct kvm_exit_mmio *mmio)
-{
-        const struct mmio_range *range;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long base = dist->vgic_dist_base;
-        bool updated_state;
-        unsigned long offset;
-
-        if (!irqchip_in_kernel(vcpu->kvm) ||
-            mmio->phys_addr < base ||
-            (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
-                return false;
-
-        /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
-        if (mmio->len > 4) {
-                kvm_inject_dabt(vcpu, mmio->phys_addr);
-                return true;
-        }
-
-        range = find_matching_range(vgic_ranges, mmio, base);
-        if (unlikely(!range || !range->handle_mmio)) {
-                pr_warn("Unhandled access %d %08llx %d\n",
-                        mmio->is_write, mmio->phys_addr, mmio->len);
-                return false;
-        }
-
-        spin_lock(&vcpu->kvm->arch.vgic.lock);
-        offset = mmio->phys_addr - range->base - base;
-        updated_state = range->handle_mmio(vcpu, mmio, offset);
-        spin_unlock(&vcpu->kvm->arch.vgic.lock);
-        kvm_prepare_mmio(run, mmio);
-        kvm_handle_mmio_return(vcpu, run);
-
-        if (updated_state)
-                vgic_kick_vcpus(vcpu->kvm);
-
-        return true;
-}
-
-static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
-{
-        struct kvm *kvm = vcpu->kvm;
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        int nrcpus = atomic_read(&kvm->online_vcpus);
-        u8 target_cpus;
-        int sgi, mode, c, vcpu_id;
-
-        vcpu_id = vcpu->vcpu_id;
-
-        sgi = reg & 0xf;
-        target_cpus = (reg >> 16) & 0xff;
-        mode = (reg >> 24) & 3;
-
-        switch (mode) {
-        case 0:
-                if (!target_cpus)
-                        return;
-
-        case 1:
-                target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
-                break;
-
-        case 2:
-                target_cpus = 1 << vcpu_id;
-                break;
-        }
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (target_cpus & 1) {
-                        /* Flag the SGI as pending */
-                        vgic_dist_irq_set(vcpu, sgi);
-                        dist->irq_sgi_sources[c][sgi] |= 1 << vcpu_id;
-                        kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
-                }
-
-                target_cpus >>= 1;
-        }
-}
-
-static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
-        unsigned long pending_private, pending_shared;
-        int vcpu_id;
-
-        vcpu_id = vcpu->vcpu_id;
-        pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
-        pend_shared = vcpu->arch.vgic_cpu.pending_shared;
-
-        pending = vgic_bitmap_get_cpu_map(&dist->irq_state, vcpu_id);
-        enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
-        bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
-
-        pending = vgic_bitmap_get_shared_map(&dist->irq_state);
-        enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
-        bitmap_and(pend_shared, pending, enabled, VGIC_NR_SHARED_IRQS);
-        bitmap_and(pend_shared, pend_shared,
-                   vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
-                   VGIC_NR_SHARED_IRQS);
-
-        pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
-        pending_shared = find_first_bit(pend_shared, VGIC_NR_SHARED_IRQS);
-        return (pending_private < VGIC_NR_PRIVATE_IRQS ||
-                pending_shared < VGIC_NR_SHARED_IRQS);
-}
-
-/*
- * Update the interrupt state and determine which CPUs have pending
- * interrupts. Must be called with distributor lock held.
- */
-static void vgic_update_state(struct kvm *kvm)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int c;
-
-        if (!dist->enabled) {
-                set_bit(0, &dist->irq_pending_on_cpu);
-                return;
-        }
-
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (compute_pending_for_cpu(vcpu)) {
-                        pr_debug("CPU%d has pending interrupts\n", c);
-                        set_bit(c, &dist->irq_pending_on_cpu);
-                }
-        }
-}
-
-#define LR_CPUID(lr)    \
-        (((lr) & GICH_LR_PHYSID_CPUID) >> GICH_LR_PHYSID_CPUID_SHIFT)
-#define MK_LR_PEND(src, irq)    \
-        (GICH_LR_PENDING_BIT | ((src) << GICH_LR_PHYSID_CPUID_SHIFT) | (irq))
-
-/*
- * An interrupt may have been disabled after being made pending on the
- * CPU interface (the classic case is a timer running while we're
- * rebooting the guest - the interrupt would kick as soon as the CPU
- * interface gets enabled, with deadly consequences).
- *
- * The solution is to examine already active LRs, and check the
- * interrupt is still enabled. If not, just retire it.
- */
-static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-
-        for_each_set_bit(lr, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
-                int irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                if (!vgic_irq_is_enabled(vcpu, irq)) {
-                        vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-                        clear_bit(lr, vgic_cpu->lr_used);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_STATE;
-                        if (vgic_irq_is_active(vcpu, irq))
-                                vgic_irq_clear_active(vcpu, irq);
-                }
-        }
-}
-
-/*
- * Queue an interrupt to a CPU virtual interface. Return true on success,
- * or false if it wasn't possible to queue it.
- */
-static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        int lr;
-
-        /* Sanitize the input... */
-        BUG_ON(sgi_source_id & ~7);
-        BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
-        BUG_ON(irq >= VGIC_NR_IRQS);
-
-        kvm_debug("Queue IRQ%d\n", irq);
-
-        lr = vgic_cpu->vgic_irq_lr_map[irq];
-
-        /* Do we have an active interrupt for the same CPUID? */
-        if (lr != LR_EMPTY &&
-            (LR_CPUID(vgic_cpu->vgic_lr[lr]) == sgi_source_id)) {
-                kvm_debug("LR%d piggyback for IRQ%d %x\n",
-                          lr, irq, vgic_cpu->vgic_lr[lr]);
-                BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT;
-                return true;
-        }
-
-        /* Try to use another LR for this interrupt */
-        lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
-                               vgic_cpu->nr_lr);
-        if (lr >= vgic_cpu->nr_lr)
-                return false;
-
-        kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
-        vgic_cpu->vgic_lr[lr] = MK_LR_PEND(sgi_source_id, irq);
-        vgic_cpu->vgic_irq_lr_map[irq] = lr;
-        set_bit(lr, vgic_cpu->lr_used);
-
-        if (!vgic_irq_is_edge(vcpu, irq))
-                vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI;
-
-        return true;
-}
-
-static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        unsigned long sources;
-        int vcpu_id = vcpu->vcpu_id;
-        int c;
-
-        sources = dist->irq_sgi_sources[vcpu_id][irq];
-
-        for_each_set_bit(c, &sources, VGIC_MAX_CPUS) {
-                if (vgic_queue_irq(vcpu, c, irq))
-                        clear_bit(c, &sources);
-        }
-
-        dist->irq_sgi_sources[vcpu_id][irq] = sources;
-
-        /*
-         * If the sources bitmap has been cleared it means that we
-         * could queue all the SGIs onto link registers (see the
-         * clear_bit above), and therefore we are done with them in
-         * our emulated gic and can get rid of them.
-         */
-        if (!sources) {
-                vgic_dist_irq_clear(vcpu, irq);
-                vgic_cpu_irq_clear(vcpu, irq);
-                return true;
-        }
-
-        return false;
-}
-
-static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
-{
-        if (vgic_irq_is_active(vcpu, irq))
-                return true; /* level interrupt, already queued */
-
-        if (vgic_queue_irq(vcpu, 0, irq)) {
-                if (vgic_irq_is_edge(vcpu, irq)) {
-                        vgic_dist_irq_clear(vcpu, irq);
-                        vgic_cpu_irq_clear(vcpu, irq);
-                } else {
-                        vgic_irq_set_active(vcpu, irq);
-                }
-
-                return true;
-        }
-
-        return false;
-}
-
-/*
- * Fill the list registers with pending interrupts before running the
- * guest.
- */
-static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i, vcpu_id;
-        int overflow = 0;
-
-        vcpu_id = vcpu->vcpu_id;
-
-        /*
-         * We may not have any pending interrupt, or the interrupts
-         * may have been serviced from another vcpu. In all cases,
-         * move along.
-         */
-        if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
-                pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
-                goto epilog;
-        }
-
-        /* SGIs */
-        for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
-                if (!vgic_queue_sgi(vcpu, i))
-                        overflow = 1;
-        }
-
-        /* PPIs */
-        for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i))
-                        overflow = 1;
-        }
-
-        /* SPIs */
-        for_each_set_bit(i, vgic_cpu->pending_shared, VGIC_NR_SHARED_IRQS) {
-                if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
-                        overflow = 1;
-        }
-
-epilog:
-        if (overflow) {
-                vgic_cpu->vgic_hcr |= GICH_HCR_UIE;
-        } else {
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-                /*
-                 * We're about to run this VCPU, and we've consumed
-                 * everything the distributor had in store for
-                 * us. Claim we don't have anything pending. We'll
-                 * adjust that if needed while exiting.
-                 */
-                clear_bit(vcpu_id, &dist->irq_pending_on_cpu);
-        }
-}
-
-static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        bool level_pending = false;
-
-        kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr);
-
-        if (vgic_cpu->vgic_misr & GICH_MISR_EOI) {
-                /*
-                 * Some level interrupts have been EOIed. Clear their
-                 * active bit.
-                 */
-                int lr, irq;
-
-                for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_eisr,
-                                 vgic_cpu->nr_lr) {
-                        irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                        vgic_irq_clear_active(vcpu, irq);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_EOI;
-
-                        /* Any additional pending interrupt? */
-                        if (vgic_dist_irq_is_pending(vcpu, irq)) {
-                                vgic_cpu_irq_set(vcpu, irq);
-                                level_pending = true;
-                        } else {
-                                vgic_cpu_irq_clear(vcpu, irq);
-                        }
-
-                        /*
-                         * Despite being EOIed, the LR may not have
-                         * been marked as empty.
-                         */
-                        set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr);
-                        vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT;
-                }
-        }
-
-        if (vgic_cpu->vgic_misr & GICH_MISR_U)
-                vgic_cpu->vgic_hcr &= ~GICH_HCR_UIE;
-
-        return level_pending;
-}
-
-/*
- * Sync back the VGIC state after a guest run. The distributor lock is
- * needed so we don't get preempted in the middle of the state processing.
- */
-static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int lr, pending;
-        bool level_pending;
-
-        level_pending = vgic_process_maintenance(vcpu);
-
-        /* Clear mappings for empty LRs */
-        for_each_set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr,
-                         vgic_cpu->nr_lr) {
-                int irq;
-
-                if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
-                        continue;
-
-                irq = vgic_cpu->vgic_lr[lr] & GICH_LR_VIRTUALID;
-
-                BUG_ON(irq >= VGIC_NR_IRQS);
-                vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
-        }
-
-        /* Check if we still have something up our sleeve... */
-        pending = find_first_zero_bit((unsigned long *)vgic_cpu->vgic_elrsr,
-                                      vgic_cpu->nr_lr);
-        if (level_pending || pending < vgic_cpu->nr_lr)
-                set_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-
-void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-
-        spin_lock(&dist->lock);
-        __kvm_vgic_flush_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-
-void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return;
-
-        spin_lock(&dist->lock);
-        __kvm_vgic_sync_hwstate(vcpu);
-        spin_unlock(&dist->lock);
-}
-
-int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
-{
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-
-        return test_bit(vcpu->vcpu_id, &dist->irq_pending_on_cpu);
-}
-
-static void vgic_kick_vcpus(struct kvm *kvm)
-{
-        struct kvm_vcpu *vcpu;
-        int c;
-
-        /*
-         * We've injected an interrupt, time to find out who deserves
-         * a good kick...
-         */
-        kvm_for_each_vcpu(c, vcpu, kvm) {
-                if (kvm_vgic_vcpu_pending_irq(vcpu))
-                        kvm_vcpu_kick(vcpu);
-        }
-}
-
-static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
-{
-        int is_edge = vgic_irq_is_edge(vcpu, irq);
-        int state = vgic_dist_irq_is_pending(vcpu, irq);
-
-        /*
-         * Only inject an interrupt if:
-         * - edge triggered and we have a rising edge
-         * - level triggered and we change level
-         */
-        if (is_edge)
-                return level > state;
-        else
-                return level != state;
-}
-
-static bool vgic_update_irq_state(struct kvm *kvm, int cpuid,
-                                  unsigned int irq_num, bool level)
-{
-        struct vgic_dist *dist = &kvm->arch.vgic;
-        struct kvm_vcpu *vcpu;
-        int is_edge, is_level;
-        int enabled;
-        bool ret = true;
-
-        spin_lock(&dist->lock);
-
-        vcpu = kvm_get_vcpu(kvm, cpuid);
-        is_edge = vgic_irq_is_edge(vcpu, irq_num);
-        is_level = !is_edge;
-
-        if (!vgic_validate_injection(vcpu, irq_num, level)) {
-                ret = false;
-                goto out;
-        }
-
-        if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
-                cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
-                vcpu = kvm_get_vcpu(kvm, cpuid);
-        }
-
-        kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
-
-        if (level)
-                vgic_dist_irq_set(vcpu, irq_num);
-        else
-                vgic_dist_irq_clear(vcpu, irq_num);
-
-        enabled = vgic_irq_is_enabled(vcpu, irq_num);
-
-        if (!enabled) {
-                ret = false;
-                goto out;
-        }
-
-        if (is_level && vgic_irq_is_active(vcpu, irq_num)) {
-                /*
-                 * Level interrupt in progress, will be picked up
-                 * when EOId.
-                 */
-                ret = false;
-                goto out;
-        }
-
-        if (level) {
-                vgic_cpu_irq_set(vcpu, irq_num);
-                set_bit(cpuid, &dist->irq_pending_on_cpu);
-        }
-
-out:
-        spin_unlock(&dist->lock);
-
-        return ret;
-}
-
-/**
- * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
- * @kvm:     The VM structure pointer
- * @cpuid:   The CPU for PPIs
- * @irq_num: The IRQ number that is assigned to the device
- * @level:   Edge-triggered:  true:  to trigger the interrupt
- *                            false: to ignore the call
- *           Level-sensitive  true:  activates an interrupt
- *                            false: deactivates an interrupt
- *
- * The GIC is not concerned with devices being active-LOW or active-HIGH for
- * level-sensitive interrupts.  You can think of the level parameter as 1
- * being HIGH and 0 being LOW and all devices being active-HIGH.
- */
-int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
-                        bool level)
-{
-        if (vgic_update_irq_state(kvm, cpuid, irq_num, level))
-                vgic_kick_vcpus(kvm);
-
-        return 0;
-}
-
-static irqreturn_t vgic_maintenance_handler(int irq, void *data)
-{
-        /*
-         * We cannot rely on the vgic maintenance interrupt to be
-         * delivered synchronously. This means we can only use it to
-         * exit the VM, and we perform the handling of EOIed
-         * interrupts on the exit path (see vgic_process_maintenance).
-         */
-        return IRQ_HANDLED;
-}
-
-int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
-{
-        struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
-        struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
-        int i;
-
-        if (!irqchip_in_kernel(vcpu->kvm))
-                return 0;
-
-        if (vcpu->vcpu_id >= VGIC_MAX_CPUS)
-                return -EBUSY;
-
-        for (i = 0; i < VGIC_NR_IRQS; i++) {
-                if (i < VGIC_NR_PPIS)
-                        vgic_bitmap_set_irq_val(&dist->irq_enabled,
-                                                vcpu->vcpu_id, i, 1);
-                if (i < VGIC_NR_PRIVATE_IRQS)
-                        vgic_bitmap_set_irq_val(&dist->irq_cfg,
-                                                vcpu->vcpu_id, i, VGIC_CFG_EDGE);
-
-                vgic_cpu->vgic_irq_lr_map[i] = LR_EMPTY;
-        }
-
-        /*
-         * By forcing VMCR to zero, the GIC will restore the binary
-         * points to their reset values. Anything else resets to zero
-         * anyway.
-         */
-        vgic_cpu->vgic_vmcr = 0;
-
-        vgic_cpu->nr_lr = vgic_nr_lr;
-        vgic_cpu->vgic_hcr = GICH_HCR_EN; /* Get the show on the road... */
-
-        return 0;
-}
-
-static void vgic_init_maintenance_interrupt(void *info)
-{
-        enable_percpu_irq(vgic_maint_irq, 0);
-}
-
-static int vgic_cpu_notify(struct notifier_block *self,
-                           unsigned long action, void *cpu)
-{
-        switch (action) {
-        case CPU_STARTING:
-        case CPU_STARTING_FROZEN:
-                vgic_init_maintenance_interrupt(NULL);
-                break;
-        case CPU_DYING:
-        case CPU_DYING_FROZEN:
-                disable_percpu_irq(vgic_maint_irq);
-                break;
-        }
-
-        return NOTIFY_OK;
-}
-
-static struct notifier_block vgic_cpu_nb = {
-        .notifier_call = vgic_cpu_notify,
-};
-
-int kvm_vgic_hyp_init(void)
-{
-        int ret;
-        struct resource vctrl_res;
-        struct resource vcpu_res;
-
-        vgic_node = of_find_compatible_node(NULL, NULL, "arm,cortex-a15-gic");
-        if (!vgic_node) {
-                kvm_err("error: no compatible vgic node in DT\n");
-                return -ENODEV;
-        }
-
-        vgic_maint_irq = irq_of_parse_and_map(vgic_node, 0);
-        if (!vgic_maint_irq) {
-                kvm_err("error getting vgic maintenance irq from DT\n");
-                ret = -ENXIO;
-                goto out;
-        }
-
-        ret = request_percpu_irq(vgic_maint_irq, vgic_maintenance_handler,
-                                 "vgic", kvm_get_running_vcpus());
-        if (ret) {
-                kvm_err("Cannot register interrupt %d\n", vgic_maint_irq);
-                goto out;
-        }
-
-        ret = register_cpu_notifier(&vgic_cpu_nb);
-        if (ret) {
-                kvm_err("Cannot register vgic CPU notifier\n");
-                goto out_free_irq;
-        }
-
-        ret = of_address_to_resource(vgic_node, 2, &vctrl_res);
-        if (ret) {
-                kvm_err("Cannot obtain VCTRL resource\n");
-                goto out_free_irq;
-        }
-
-        vgic_vctrl_base = of_iomap(vgic_node, 2);
-        if (!vgic_vctrl_base) {
-                kvm_err("Cannot ioremap VCTRL\n");
-                ret = -ENOMEM;
-                goto out_free_irq;
-        }
-
-        vgic_nr_lr = readl_relaxed(vgic_vctrl_base + GICH_VTR);
-        vgic_nr_lr = (vgic_nr_lr & 0x3f) + 1;
-
-        ret = create_hyp_io_mappings(vgic_vctrl_base,
-                                     vgic_vctrl_base + resource_size(&vctrl_res),
-                                     vctrl_res.start);
-        if (ret) {
-                kvm_err("Cannot map VCTRL into hyp\n");
-                goto out_unmap;
-        }
-
-        kvm_info("%s@%llx IRQ%d\n", vgic_node->name,
-                 vctrl_res.start, vgic_maint_irq);
-        on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
-
-        if (of_address_to_resource(vgic_node, 3, &vcpu_res)) {
-                kvm_err("Cannot obtain VCPU resource\n");
-                ret = -ENXIO;
-                goto out_unmap;
-        }
-        vgic_vcpu_base = vcpu_res.start;
-
-        goto out;
-
-out_unmap:
-        iounmap(vgic_vctrl_base);
-out_free_irq:
-        free_percpu_irq(vgic_maint_irq, kvm_get_running_vcpus());
-out:
-        of_node_put(vgic_node);
-        return ret;
-}
-
-int kvm_vgic_init(struct kvm *kvm)
-{
-        int ret = 0, i;
-
-        mutex_lock(&kvm->lock);
-
-        if (vgic_initialized(kvm))
-                goto out;
-
-        if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
-            IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
-                kvm_err("Need to set vgic cpu and dist addresses first\n");
-                ret = -ENXIO;
-                goto out;
-        }
-
-        ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
-                                    vgic_vcpu_base, KVM_VGIC_V2_CPU_SIZE);
-        if (ret) {
-                kvm_err("Unable to remap VGIC CPU to VCPU\n");
-                goto out;
-        }
-
-        for (i = VGIC_NR_PRIVATE_IRQS; i < VGIC_NR_IRQS; i += 4)
-                vgic_set_target_reg(kvm, 0, i);
-
-        kvm_timer_init(kvm);
-        kvm->arch.vgic.ready = true;
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-
-int kvm_vgic_create(struct kvm *kvm)
-{
-        int ret = 0;
-
-        mutex_lock(&kvm->lock);
-
-        if (atomic_read(&kvm->online_vcpus) || kvm->arch.vgic.vctrl_base) {
-                ret = -EEXIST;
-                goto out;
-        }
-
-        spin_lock_init(&kvm->arch.vgic.lock);
-        kvm->arch.vgic.vctrl_base = vgic_vctrl_base;
-        kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
-        kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
-
-out:
-        mutex_unlock(&kvm->lock);
-        return ret;
-}
-
-static bool vgic_ioaddr_overlap(struct kvm *kvm)
-{
-        phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
-        phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
-
-        if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
-                return 0;
-        if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
-            (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
-                return -EBUSY;
-        return 0;
-}
-
-static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
-                              phys_addr_t addr, phys_addr_t size)
-{
-        int ret;
-
-        if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
-                return -EEXIST;
-        if (addr + size < addr)
-                return -EINVAL;
-
-        ret = vgic_ioaddr_overlap(kvm);
-        if (ret)
-                return ret;
-        *ioaddr = addr;
-        return ret;
-}
-
-int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
-{
-        int r = 0;
-        struct vgic_dist *vgic = &kvm->arch.vgic;
-
-        if (addr & ~KVM_PHYS_MASK)
-                return -E2BIG;
-
-        if (addr & (SZ_4K - 1))
-                return -EINVAL;
-
-        mutex_lock(&kvm->lock);
-        switch (type) {
-        case KVM_VGIC_V2_ADDR_TYPE_DIST:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
-                                       addr, KVM_VGIC_V2_DIST_SIZE);
-                break;
-        case KVM_VGIC_V2_ADDR_TYPE_CPU:
-                r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
-                                       addr, KVM_VGIC_V2_CPU_SIZE);
-                break;
-        default:
-                r = -ENODEV;
-        }
-
-        mutex_unlock(&kvm->lock);
-        return r;
-}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 02802386b894..699b71e7f7ec 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -163,6 +163,7 @@ config MACH_SAMA5_DT
         bool "Atmel SAMA5 Evaluation Kits with device-tree support"
         depends on SOC_SAMA5
         select USE_OF
+        select PHYLIB if NETDEVICES
         help
           Select this if you want to experiment device-tree with
           an Atmel Evaluation Kit.
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
index 6c24985515a2..ca900be144ce 100644
--- a/arch/arm/mach-at91/Kconfig.non_dt
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -14,15 +14,11 @@ config ARCH_AT91RM9200
         select SOC_AT91RM9200
 
 config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
+        bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20"
         select SOC_AT91SAM9260
 
 config ARCH_AT91SAM9261
-        bool "AT91SAM9261"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
+        bool "AT91SAM9261 or AT91SAM9G10"
         select SOC_AT91SAM9261
 
 config ARCH_AT91SAM9263
@@ -33,10 +29,6 @@ config ARCH_AT91SAM9RL
         bool "AT91SAM9RL"
         select SOC_AT91SAM9RL
 
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select SOC_AT91SAM9260
-
 config ARCH_AT91SAM9G45
         bool "AT91SAM9G45"
         select SOC_AT91SAM9G45
@@ -50,6 +42,14 @@ config ARCH_AT91X40
 
 endchoice
 
+config ARCH_AT91SAM9G20
+        bool
+        select ARCH_AT91SAM9260
+
+config ARCH_AT91SAM9G10
+        bool
+        select ARCH_AT91SAM9261
+
 # ----------------------------------------------------------
 
 if ARCH_AT91RM9200
@@ -62,13 +62,6 @@ config MACH_ONEARM
           Select this if you are using Ajeco's 1ARM Single Board Computer.
           <http://www.ajeco.fi/>
 
-config ARCH_AT91RM9200DK
-        bool "Atmel AT91RM9200-DK Development board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-DK Development board.
-          (Discontinued)
-
 config MACH_AT91RM9200EK
         bool "Atmel AT91RM9200-EK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
@@ -183,12 +176,6 @@ config MACH_AFEB9260
           <svn://194.85.238.22/home/users/george/svn/arm9eb>
           <http://groups.google.com/group/arm9fpga-evolution-board>
 
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
-
 config MACH_QIL_A9260
         bool "CALAO QIL-A9260 board"
         help
@@ -207,76 +194,6 @@ config MACH_FLEXIBITY
           Select this if you are using Flexibity Connect board
           <http://www.flexibity.com>
 
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G20
-
 comment "AT91SAM9G20 Board Type"
 
 config MACH_AT91SAM9G20EK
@@ -334,24 +251,64 @@ config MACH_GSIA18S
           produced by GeoSIG Ltd company. This is an internet accelerograph.
           <http://www.geosig.com>
 
-config MACH_USB_A9G20
-        bool "CALAO USB-A9G20"
-        depends on ARCH_AT91SAM9G20
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
         help
-          Select this if you are using a Calao Systems USB-A9G20.
-          <http://www.calao-systems.com>
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
 
 endif
 
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+        bool "Atmel AT91SAM9263-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
 
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
 endif
 
 # ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 788562dccb43..3b0a9538093c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -27,16 +27,13 @@ obj-$(CONFIG_SOC_SAMA5D3)	+= sama5d3.o
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45_devices.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
 obj-$(CONFIG_MACH_ONEARM)       += board-1arm.o
-obj-$(CONFIG_ARCH_AT91RM9200DK) += board-rm9200dk.o
 obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
 obj-$(CONFIG_MACH_CSB337)       += board-csb337.o
 obj-$(CONFIG_MACH_CSB637)       += board-csb637.o
@@ -55,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS)	+= board-rsi-ews.o
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
 obj-$(CONFIG_MACH_CAM60)        += board-cam60.o
 obj-$(CONFIG_MACH_SAM9_L9260)   += board-sam9-l9260.o
-obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a926x.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
 obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
@@ -67,7 +63,6 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
-obj-$(CONFIG_MACH_USB_A9263)    += board-usb-a926x.o
 
 # AT91SAM9RL board-specific support
 obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
@@ -80,7 +75,6 @@ obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)    += board-stamp9g20.o
 obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
 obj-$(CONFIG_MACH_GSIA18S)      += board-gsia18s.o board-stamp9g20.o
-obj-$(CONFIG_MACH_USB_A9G20)    += board-usb-a926x.o
 
 # AT91SAM9260/AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index d193a409bc45..9eb574397ee1 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -332,10 +332,6 @@ static void __init at91rm9200_initialize(void)
 {
         arm_pm_idle = at91rm9200_idle;
         arm_pm_restart = at91rm9200_restart;
-        at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
-                        | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
-                        | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
-                        | (1 << AT91RM9200_ID_IRQ6);
 
         /* Initialize GPIO subsystem */
         at91_gpio_init(at91rm9200_gpio,
@@ -388,6 +384,10 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91rm9200)
         .map_io = at91rm9200_map_io,
         .default_irq_priority = at91rm9200_default_irq_priority,
+        .extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
+                    | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
+                    | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
+                    | (1 << AT91RM9200_ID_IRQ6),
         .ioremap_registers = at91rm9200_ioremap_registers,
         .register_clocks = at91rm9200_register_clocks,
         .init = at91rm9200_initialize,
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a8ce24538da6..5de6074b4f4f 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -348,8 +348,6 @@ static void __init at91sam9260_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
-                        | (1 << AT91SAM9260_ID_IRQ2);
 
         /* Register GPIO subsystem */
         at91_gpio_init(at91sam9260_gpio, 3);
@@ -400,6 +398,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9260)
         .map_io = at91sam9260_map_io,
         .default_irq_priority = at91sam9260_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
+                    | (1 << AT91SAM9260_ID_IRQ2),
         .ioremap_registers = at91sam9260_ioremap_registers,
         .register_clocks = at91sam9260_register_clocks,
         .init = at91sam9260_initialize,
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 25efb5ac30f1..0e0793241ab7 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -290,8 +290,6 @@ static void __init at91sam9261_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
-                        | (1 << AT91SAM9261_ID_IRQ2);
 
         /* Register GPIO subsystem */
         at91_gpio_init(at91sam9261_gpio, 3);
@@ -342,6 +340,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9261)
         .map_io = at91sam9261_map_io,
         .default_irq_priority = at91sam9261_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
+                    | (1 << AT91SAM9261_ID_IRQ2),
         .ioremap_registers = at91sam9261_ioremap_registers,
         .register_clocks = at91sam9261_register_clocks,
         .init = at91sam9261_initialize,
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f44ffd2105a7..6ce7d1850893 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -327,7 +327,6 @@ static void __init at91sam9263_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 
         /* Register GPIO subsystem */
         at91_gpio_init(at91sam9263_gpio, 5);
@@ -378,6 +377,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9263)
         .map_io = at91sam9263_map_io,
         .default_irq_priority = at91sam9263_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1),
         .ioremap_registers = at91sam9263_ioremap_registers,
         .register_clocks = at91sam9263_register_clocks,
         .init = at91sam9263_initialize,
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce067652..474ee04d24b9 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -266,6 +266,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
         CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
+        CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
         /* fake hclk clock */
         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
@@ -374,7 +376,6 @@ static void __init at91sam9g45_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9g45_restart;
-        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
 
         /* Register GPIO subsystem */
         at91_gpio_init(at91sam9g45_gpio, 5);
@@ -425,6 +426,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9g45)
         .map_io = at91sam9g45_map_io,
         .default_irq_priority = at91sam9g45_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
         .ioremap_registers = at91sam9g45_ioremap_registers,
         .register_clocks = at91sam9g45_register_clocks,
         .init = at91sam9g45_initialize,
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index f77fae5591bc..d4ec0d9a9872 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -293,7 +293,6 @@ static void __init at91sam9rl_initialize(void)
 {
         arm_pm_idle = at91sam9_idle;
         arm_pm_restart = at91sam9_alt_restart;
-        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
 
         /* Register GPIO subsystem */
         at91_gpio_init(at91sam9rl_gpio, 4);
@@ -344,6 +343,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 AT91_SOC_START(at91sam9rl)
         .map_io = at91sam9rl_map_io,
         .default_irq_priority = at91sam9rl_default_irq_priority,
+        .extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
         .ioremap_registers = at91sam9rl_ioremap_registers,
         .register_clocks = at91sam9rl_register_clocks,
         .init = at91sam9rl_initialize,
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index e631fec040ce..2abee6626aac 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -249,6 +249,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
         CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
 };
 
 /*
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 19ca79396905..bad94b84a46f 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -55,8 +55,6 @@ static void at91x40_idle(void)
 void __init at91x40_initialize(unsigned long main_clock)
 {
         arm_pm_idle = at91x40_idle;
-        at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
-                        | (1 << AT91X40_ID_IRQ2);
 }
 
 /*
@@ -86,9 +84,10 @@ static unsigned int at91x40_default_irq_priority[NR_AIC_IRQS] __initdata = {
 
 void __init at91x40_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 {
+        u32  extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
+                        | (1 << AT91X40_ID_IRQ2);
         if (!priority)
                 priority = at91x40_default_irq_priority;
 
-        at91_aic_init(priority, at91_extern_irq);
+        at91_aic_init(priority, extern_irq);
 }
-
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index 705305e62bbc..ad95f6a23a28 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -62,7 +62,8 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
 
 static void __init sama5_dt_device_init(void)
 {
-        if (of_machine_is_compatible("atmel,sama5d3xcm"))
+        if (of_machine_is_compatible("atmel,sama5d3xcm") &&
+            IS_ENABLED(CONFIG_PHYLIB))
                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                         ksz9021rn_phy_fixup);
 
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
deleted file mode 100644
index 690541b18cbc..000000000000
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-rm9200dk.c
- *
- *  Copyright (C) 2005 SAN People
- *
- *  Epson S1D framebuffer glue code is:
- *     Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/at91rm9200_mc.h>
-#include <mach/at91_ramc.h>
-
-#include "at91_aic.h"
-#include "board.h"
-#include "generic.h"
-
-
-static void __init dk_init_early(void)
-{
-        /* Initialize processor: 18.432 MHz crystal */
-        at91_initialize(18432000);
-}
-
-static struct macb_platform_data __initdata dk_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PC4,
-        .is_rmii        = 1,
-};
-
-static struct at91_usbh_data __initdata dk_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-static struct at91_udc_data __initdata dk_udc_data = {
-        .vbus_pin       = AT91_PIN_PD4,
-        .pullup_pin     = AT91_PIN_PD5,
-};
-
-static struct at91_cf_data __initdata dk_cf_data = {
-        .irq_pin        = -EINVAL,
-        .det_pin        = AT91_PIN_PB0,
-        .vcc_pin        = -EINVAL,
-        .rst_pin        = AT91_PIN_PC5,
-};
-
-#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
-static struct mci_platform_data __initdata dk_mci0_data = {
-        .slot[0] = {
-                .bus_width      = 4,
-                .detect_pin     = -EINVAL,
-                .wp_pin         = -EINVAL,
-        },
-};
-#endif
-
-static struct spi_board_info dk_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        },
-        {       /* UR6HCPS2-SP40 PS2-to-SPI adapter */
-                .modalias       = "ur6hcps2",
-                .chip_select    = 1,
-                .max_speed_hz   = 250 *  1000,
-        },
-        {       /* TLV1504 ADC, 4 channels, 10 bits; one is a temp sensor */
-                .modalias       = "tlv1504",
-                .chip_select    = 2,
-                .max_speed_hz   = 20 * 1000 * 1000,
-        },
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        {       /* DataFlash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 3,
-                .max_speed_hz   = 15 * 1000 * 1000,
-        }
-#endif
-};
-
-static struct i2c_board_info __initdata dk_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ics1523", 0x26),
-        },
-        {
-                I2C_BOARD_INFO("x9429", 0x28),
-        },
-        {
-                I2C_BOARD_INFO("24c1024", 0x50),
-        }
-};
-
-static struct mtd_partition __initdata dk_nand_partition[] = {
-        {
-                .name   = "NAND Partition 1",
-                .offset = 0,
-                .size   = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct atmel_nand_data __initdata dk_nand_data = {
-        .ale            = 22,
-        .cle            = 21,
-        .det_pin        = AT91_PIN_PB1,
-        .rdy_pin        = AT91_PIN_PC2,
-        .enable_pin     = -EINVAL,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = dk_nand_partition,
-        .num_parts      = ARRAY_SIZE(dk_nand_partition),
-};
-
-#define DK_FLASH_BASE   AT91_CHIPSELECT_0
-#define DK_FLASH_SIZE   SZ_2M
-
-static struct physmap_flash_data dk_flash_data = {
-        .width          = 2,
-};
-
-static struct resource dk_flash_resource = {
-        .start          = DK_FLASH_BASE,
-        .end            = DK_FLASH_BASE + DK_FLASH_SIZE - 1,
-        .flags          = IORESOURCE_MEM,
-};
-
-static struct platform_device dk_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data  = &dk_flash_data,
-                        },
-        .resource       = &dk_flash_resource,
-        .num_resources  = 1,
-};
-
-static struct gpio_led dk_leds[] = {
-        {
-                .name                   = "led0",
-                .gpio                   = AT91_PIN_PB2,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-static void __init dk_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
-        at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
-                           | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
-                           | ATMEL_UART_RI);
-        at91_add_device_serial();
-        /* Ethernet */
-        at91_add_device_eth(&dk_eth_data);
-        /* USB Host */
-        at91_add_device_usbh(&dk_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&dk_udc_data);
-        at91_set_multi_drive(dk_udc_data.pullup_pin, 1);        /* pullup_pin is connected to reset */
-        /* Compact Flash */
-        at91_add_device_cf(&dk_cf_data);
-        /* I2C */
-        at91_add_device_i2c(dk_i2c_devices, ARRAY_SIZE(dk_i2c_devices));
-        /* SPI */
-        at91_add_device_spi(dk_spi_devices, ARRAY_SIZE(dk_spi_devices));
-#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
-        /* DataFlash card */
-        at91_set_gpio_output(AT91_PIN_PB7, 0);
-#else
-        /* MMC */
-        at91_set_gpio_output(AT91_PIN_PB7, 1);  /* this MMC card slot can optionally use SPI signaling (CS3). */
-        at91_add_device_mci(0, &dk_mci0_data);
-#endif
-        /* NAND */
-        at91_add_device_nand(&dk_nand_data);
-        /* NOR Flash */
-        platform_device_register(&dk_flash);
-        /* LEDs */
-        at91_gpio_leds(dk_leds, ARRAY_SIZE(dk_leds));
-        /* VGA */
-//      dk_add_device_video();
-}
-
-MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
-        /* Maintainer: SAN People/Atmel */
-        .init_time      = at91rm9200_timer_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = dk_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = dk_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b446645c7727..d3437624ca4e 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -264,11 +264,7 @@ static void __init ek_add_device_ts(void) {}
  */
 static struct at73c213_board_info at73c213_data = {
         .ssc_id         = 1,
-#if defined(CONFIG_MACH_AT91SAM9261EK)
-        .shortname      = "AT91SAM9261-EK external DAC",
-#else
-        .shortname      = "AT91SAM9G10-EK external DAC",
-#endif
+        .shortname      = "AT91SAM9261/9G10-EK external DAC",
 };
 
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -412,9 +408,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
         .default_monspecs               = &at91fb_default_stn_monspecs,
         .atmel_lcdfb_power_control      = at91_lcdc_stn_power_control,
         .guard_time                     = 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 
 #else
@@ -468,9 +461,6 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
         .default_monspecs               = &at91fb_default_tft_monspecs,
         .atmel_lcdfb_power_control      = at91_lcdc_tft_power_control,
         .guard_time                     = 1,
-#if defined(CONFIG_MACH_AT91SAM9G10EK)
-        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
-#endif
 };
 #endif
 
@@ -574,6 +564,10 @@ static void __init ek_board_init(void)
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
         at91_add_device_serial();
+
+        if (cpu_is_at91sam9g10())
+                ek_lcdc_data.lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB;
+
         /* USB Host */
         at91_add_device_usbh(&ek_usbh_data);
         /* USB Device */
@@ -606,11 +600,17 @@ static void __init ek_board_init(void)
         at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
 
-#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
-#else
+        /* Maintainer: Atmel */
+        .init_time      = at91sam926x_pit_init,
+        .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
+        .init_early     = ek_init_early,
+        .init_irq       = at91_init_irq_default,
+        .init_machine   = ek_board_init,
+MACHINE_END
+
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
-#endif
         /* Maintainer: Atmel */
         .init_time      = at91sam926x_pit_init,
         .map_io         = at91_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
deleted file mode 100644
index 2487d944a1bc..000000000000
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ /dev/null
@@ -1,384 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-usb-a926x.c
- *
- *  Copyright (C) 2005 SAN People
- *  Copyright (C) 2007 Atmel Corporation.
- *  Copyright (C) 2007 Calao-systems
- *  Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/spi/mmc_spi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/at91sam9_smc.h>
-
-#include "at91_aic.h"
-#include "at91_shdwc.h"
-#include "board.h"
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init ek_init_early(void)
-{
-        /* Initialize processor: 12.00 MHz crystal */
-        at91_initialize(12000000);
-}
-
-/*
- * USB Host port
- */
-static struct at91_usbh_data __initdata ek_usbh_data = {
-        .ports          = 2,
-        .vbus_pin       = {-EINVAL, -EINVAL},
-        .overcurrent_pin= {-EINVAL, -EINVAL},
-};
-
-/*
- * USB Device port
- */
-static struct at91_udc_data __initdata ek_udc_data = {
-        .vbus_pin       = AT91_PIN_PB11,
-        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
-};
-
-static void __init ek_add_device_udc(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_udc_data.vbus_pin = AT91_PIN_PC5;
-
-        at91_add_device_udc(&ek_udc_data);
-}
-
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-#define MMC_SPI_CARD_DETECT_INT AT91_PIN_PC4
-static int at91_mmc_spi_init(struct device *dev,
-        irqreturn_t (*detect_int)(int, void *), void *data)
-{
-        /* Configure Interrupt pin as input, no pull-up */
-        at91_set_gpio_input(MMC_SPI_CARD_DETECT_INT, 0);
-        return request_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), detect_int,
-                IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
-                "mmc-spi-detect", data);
-}
-
-static void at91_mmc_spi_exit(struct device *dev, void *data)
-{
-        free_irq(gpio_to_irq(MMC_SPI_CARD_DETECT_INT), data);
-}
-
-static struct mmc_spi_platform_data at91_mmc_spi_pdata = {
-        .init = at91_mmc_spi_init,
-        .exit = at91_mmc_spi_exit,
-        .detect_delay = 100, /* msecs */
-};
-#endif
-
-/*
- * SPI devices.
- */
-static struct spi_board_info usb_a9263_spi_devices[] = {
-        {       /* DataFlash chip */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        }
-};
-
-static struct spi_board_info usb_a9g20_spi_devices[] = {
-#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
-        {
-                .modalias = "mmc_spi",
-                .max_speed_hz = 20000000,       /* max spi clock (SCK) speed in HZ */
-                .bus_num = 1,
-                .chip_select = 0,
-                .platform_data = &at91_mmc_spi_pdata,
-                .mode = SPI_MODE_3,
-        },
-#endif
-};
-
-static void __init ek_add_device_spi(void)
-{
-        if (machine_is_usb_a9263())
-                at91_add_device_spi(usb_a9263_spi_devices, ARRAY_SIZE(usb_a9263_spi_devices));
-        else if (machine_is_usb_a9g20())
-                at91_add_device_spi(usb_a9g20_spi_devices, ARRAY_SIZE(usb_a9g20_spi_devices));
-}
-
-/*
- * MACB Ethernet device
- */
-static struct macb_platform_data __initdata ek_macb_data = {
-        .phy_irq_pin    = AT91_PIN_PE31,
-        .is_rmii        = 1,
-};
-
-static void __init ek_add_device_eth(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_macb_data.phy_irq_pin = AT91_PIN_PA31;
-
-        at91_add_device_eth(&ek_macb_data);
-}
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata ek_nand_partition[] = {
-        {
-                .name   = "barebox",
-                .offset = 0,
-                .size   = 3 * SZ_128K,
-        }, {
-                .name   = "bareboxenv",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "bareboxenv2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "oftree",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = SZ_128K,
-        }, {
-                .name   = "kernel",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 4 * SZ_1M,
-        }, {
-                .name   = "rootfs",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = 120 * SZ_1M,
-        }, {
-                .name   = "data",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-
-static struct atmel_nand_data __initdata ek_nand_data = {
-        .ale            = 21,
-        .cle            = 22,
-        .det_pin        = -EINVAL,
-        .rdy_pin        = AT91_PIN_PA22,
-        .enable_pin     = AT91_PIN_PD15,
-        .ecc_mode       = NAND_ECC_SOFT,
-        .on_flash_bbt   = 1,
-        .parts          = ek_nand_partition,
-        .num_parts      = ARRAY_SIZE(ek_nand_partition),
-};
-
-static struct sam9_smc_config __initdata usb_a9260_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 1,
-
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 2,
-};
-
-static struct sam9_smc_config __initdata usb_a9g20_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 2,
-        .ncs_write_setup        = 0,
-        .nwe_setup              = 2,
-
-        .ncs_read_pulse         = 4,
-        .nrd_pulse              = 4,
-        .ncs_write_pulse        = 4,
-        .nwe_pulse              = 4,
-
-        .read_cycle             = 7,
-        .write_cycle            = 7,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
-        .tdf_cycles             = 3,
-};
-
-static void __init ek_add_device_nand(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20()) {
-                ek_nand_data.rdy_pin    = AT91_PIN_PC13;
-                ek_nand_data.enable_pin = AT91_PIN_PC14;
-        }
-
-        /* configure chip-select 3 (NAND) */
-        if (machine_is_usb_a9g20())
-                sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
-        else
-                sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
-
-        at91_add_device_nand(&ek_nand_data);
-}
-
-
-/*
- * GPIO Buttons
- */
-#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
-static struct gpio_keys_button ek_buttons[] = {
-        {       /* USER PUSH BUTTON */
-                .code           = KEY_ENTER,
-                .gpio           = AT91_PIN_PB10,
-                .active_low     = 1,
-                .desc           = "user_pb",
-                .wakeup         = 1,
-        }
-};
-
-static struct gpio_keys_platform_data ek_button_data = {
-        .buttons        = ek_buttons,
-        .nbuttons       = ARRAY_SIZE(ek_buttons),
-};
-
-static struct platform_device ek_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ek_button_data,
-        }
-};
-
-static void __init ek_add_device_buttons(void)
-{
-        at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
-        at91_set_deglitch(AT91_PIN_PB10, 1);
-
-        platform_device_register(&ek_button_device);
-}
-#else
-static void __init ek_add_device_buttons(void) {}
-#endif
-
-/*
- * LEDs
- */
-static struct gpio_led ek_leds[] = {
-        {       /* user_led (green) */
-                .name                   = "user_led",
-                .gpio                   = AT91_PIN_PB21,
-                .active_low             = 1,
-                .default_trigger        = "heartbeat",
-        }
-};
-
-static struct i2c_board_info __initdata ek_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("rv3029c2", 0x56),
-        },
-};
-
-static void __init ek_add_device_leds(void)
-{
-        if (machine_is_usb_a9260() || machine_is_usb_a9g20())
-                ek_leds[0].active_low = 0;
-
-        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
-}
-
-static void __init ek_board_init(void)
-{
-        /* Serial */
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&ek_usbh_data);
-        /* USB Device */
-        ek_add_device_udc();
-        /* SPI */
-        ek_add_device_spi();
-        /* Ethernet */
-        ek_add_device_eth();
-        /* NAND */
-        ek_add_device_nand();
-        /* Push Buttons */
-        ek_add_device_buttons();
-        /* LEDs */
-        ek_add_device_leds();
-
-        if (machine_is_usb_a9g20()) {
-                /* I2C */
-                at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
-        } else {
-                /* I2C */
-                at91_add_device_i2c(NULL, 0);
-                /* shutdown controller, wakeup button (5 msec low) */
-                at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
-                                | AT91_SHDW_WKMODE0_LOW
-                                | AT91_SHDW_RTTWKEN);
-        }
-}
-
-MACHINE_START(USB_A9263, "CALAO USB_A9263")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9260, "CALAO USB_A9260")
-        /* Maintainer: calao-systems */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
-
-MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
-        /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
-        .init_time      = at91sam926x_pit_init,
-        .map_io         = at91_map_io,
-        .handle_irq     = at91_aic_handle_irq,
-        .init_early     = ek_init_early,
-        .init_irq       = at91_init_irq_default,
-        .init_machine   = ek_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index da841885d01c..6b2630a92f71 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -75,7 +75,7 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
-                                || cpu_is_at91sam9n12()))
+                                || cpu_is_sama5d3()))
 
 #define cpu_has_upll()          (cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
@@ -489,7 +489,7 @@ static int at91_clk_show(struct seq_file *s, void *unused)
                 seq_printf(s, "UCKR = %8x\n", uckr);
         }
         seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
-        if (cpu_has_upll())
+        if (cpu_has_upll() || cpu_is_at91sam9n12())
                 seq_printf(s, "USB  = %8x\n", at91_pmc_read(AT91_PMC_USB));
         seq_printf(s, "SR   = %8x\n", sr);
 
@@ -614,6 +614,8 @@ static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 {
         if (pll == &pllb && (reg & AT91_PMC_USB96M))
                 return freq / 2;
+        else if (pll == &utmi_clk || cpu_is_at91sam9n12())
+                return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
         else
                 return freq;
 }
@@ -683,6 +685,8 @@ static struct clk *const standard_pmc_clocks[] __initconst = {
 /* PLLB generated USB full speed clock init */
 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 {
+        unsigned int reg;
+
         /*
          * USB clock init:  choose 48 MHz PLLB value,
          * disable 48MHz clock during usb peripheral suspend.
@@ -691,22 +695,35 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
          */
         uhpck.parent = &pllb;
 
-        at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+        reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
         if (cpu_is_at91rm9200()) {
+                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
                 at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
                    cpu_is_at91sam9g10()) {
+                reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
+                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
+                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
+        } else if (cpu_is_at91sam9n12()) {
+                /* Divider for USB clock is in USB clock register for 9n12 */
+                reg = AT91_PMC_USBS_PLLB;
+
+                /* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
+                reg |= AT91_PMC_OHCIUSBDIV_2;
+                at91_pmc_write(AT91_PMC_USB, reg);
+
+                /* Still setup masks */
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         }
         at91_pmc_write(AT91_CKGR_PLLBR, 0);
 
-        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+        udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
+        uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
 }
 
 /* UPLL generated USB full speed clock init */
@@ -725,8 +742,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
         /* Now set uhpck values */
         uhpck.parent = &utmi_clk;
         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-        uhpck.rate_hz = utmi_clk.rate_hz;
-        uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
+        uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
 }
 
 static int __init at91_pmc_init(unsigned long main_clock)
diff --git a/arch/arm/mach-at91/cpuidle.c b/arch/arm/mach-at91/cpuidle.c
index 69f9e3bbf4e5..4ec6a6d9b9be 100644
--- a/arch/arm/mach-at91/cpuidle.c
+++ b/arch/arm/mach-at91/cpuidle.c
@@ -51,7 +51,7 @@ static struct cpuidle_driver at91_idle_driver = {
         .states[1]              = {
                 .enter                  = at91_enter_idle,
                 .exit_latency           = 10,
-                .target_residency       = 100000,
+                .target_residency       = 10000,
                 .flags                  = CPUIDLE_FLAG_TIME_VALID,
                 .name                   = "RAM_SR",
                 .desc                   = "WFI and DDR Self Refresh",
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 78ab06548658..f6de36aefe85 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -85,4 +85,4 @@ extern void __init at91_gpio_irq_setup(void);
 extern int  __init at91_gpio_of_irq_setup(struct device_node *node,
                                           struct device_node *parent);
 
-extern int at91_extern_irq;
+extern u32 at91_get_extern_irq(void);
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 2bd7f51b0b82..c604cc69acb5 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -130,7 +130,10 @@ extern void __iomem *at91_pmc_base;
 #define         AT91_PMC_USBS           (0x1 <<  0)             /* USB OHCI Input clock selection */
 #define                 AT91_PMC_USBS_PLLA              (0 << 0)
 #define                 AT91_PMC_USBS_UPLL              (1 << 0)
+#define                 AT91_PMC_USBS_PLLB              (1 << 0)        /* [AT91SAMN12 only] */
 #define         AT91_PMC_OHCIUSBDIV     (0xF <<  8)             /* Divider for USB OHCI Clock */
+#define                 AT91_PMC_OHCIUSBDIV_1   (0x0 <<  8)
+#define                 AT91_PMC_OHCIUSBDIV_2   (0x1 <<  8)
 
 #define AT91_PMC_SMD            0x3c                    /* Soft Modem Clock Register [some SAM9 only] */
 #define         AT91_PMC_SMDS           (0x1  <<  0)            /* SMD input clock selection */
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index e0ca59171022..3d192c5aee66 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -232,7 +232,14 @@ static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
         at91_aic_write(AT91_AIC5_EOICR, 0);
 }
 
-unsigned long *at91_extern_irq;
+static unsigned long *at91_extern_irq;
+
+u32 at91_get_extern_irq(void)
+{
+        if (!at91_extern_irq)
+                return 0;
+        return *at91_extern_irq;
+}
 
 #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
 
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 530db304ec5e..15afb5d9271f 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -212,7 +212,7 @@ static int at91_pm_enter(suspend_state_t state)
                         (at91_pmc_read(AT91_PMC_PCSR)
                                         | (1 << AT91_ID_FIQ)
                                         | (1 << AT91_ID_SYS)
-                                        | (at91_extern_irq))
+                                        | (at91_get_extern_irq()))
                                 & at91_aic_read(AT91_AIC_IMR),
                         state);
 
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index e2f4bdd146d6..b17fbcf4d9e8 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -48,7 +48,7 @@ void __init at91_init_irq_default(void)
 void __init at91_init_interrupts(unsigned int *priority)
 {
         /* Initialize the AIC interrupt controller */
-        at91_aic_init(priority, at91_extern_irq);
+        at91_aic_init(priority, at91_boot_soc.extern_irq);
 
         /* Enable GPIO interrupts */
         at91_gpio_irq_setup();
@@ -80,7 +80,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 
         desc->pfn = __phys_to_pfn(base);
         desc->length = length;
-        desc->type = MT_DEVICE;
+        desc->type = MT_MEMORY_NONCACHED;
 
         pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
                 base, length, desc->virtual);
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 43a225f9e713..a1e1482c6da8 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -6,6 +6,7 @@
 
 struct at91_init_soc {
         int builtin;
+        u32 extern_irq;
         unsigned int *default_irq_priority;
         void (*map_io)(void);
         void (*ioremap_registers)(void);
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm.c
index 22e8421b1df3..28599326d4ad 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm.c
@@ -15,7 +15,6 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/irqchip.h>
 #include <linux/clocksource.h>
 
 #include <asm/mach/arch.h>
@@ -54,7 +53,6 @@ static void __init board_init(void)
 static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
 
 DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
-        .init_irq = irqchip_init,
         .init_time = clocksource_of_init,
         .init_machine = board_init,
         .dt_compat = bcm11351_dt_compat,
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 2d00165e85ec..01ad4d41e728 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -22,8 +22,7 @@ config ARCH_CLEP7312
 
 config ARCH_EDB7211
         bool "EDB7211"
-        select ARCH_SELECT_MEMORY_MODEL
-        select ARCH_SPARSEMEM_ENABLE
+        select ARCH_HAS_HOLES_MEMORYMODEL
         help
           Say Y here if you intend to run this kernel on a Cirrus Logic EDB-7211
           evaluation board.
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 992995af666a..f30ed2b496fb 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,10 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := common.o
-obj-m                   :=
-obj-n                   :=
-obj-                    :=
+obj-y                           := common.o devices.o
 
 obj-$(CONFIG_ARCH_AUTCPU12)     += board-autcpu12.o
 obj-$(CONFIG_ARCH_CDB89712)     += board-cdb89712.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index f38584709df7..5867aebd8d0c 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -26,6 +26,8 @@
 #include <linux/gpio.h>
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
 #include <linux/platform_device.h>
@@ -40,38 +42,49 @@
 #include <asm/page.h>
 
 #include <asm/mach/map.h>
-#include <mach/autcpu12.h>
 
 #include "common.h"
+#include "devices.h"
 
-#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
-#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+/* NOR flash */
+#define AUTCPU12_FLASH_BASE     (CS0_PHYS_BASE)
+
+/* Board specific hardware definitions */
+#define AUTCPU12_CHAR_LCD_BASE  (CS1_PHYS_BASE + 0x00000000)
+#define AUTCPU12_CSAUX1_BASE    (CS1_PHYS_BASE + 0x04000000)
+#define AUTCPU12_CAN_BASE       (CS1_PHYS_BASE + 0x08000000)
+#define AUTCPU12_TOUCH_BASE     (CS1_PHYS_BASE + 0x0a000000)
+#define AUTCPU12_IO_BASE        (CS1_PHYS_BASE + 0x0c000000)
+#define AUTCPU12_LPT_BASE       (CS1_PHYS_BASE + 0x0e000000)
+
+/* NVRAM */
+#define AUTCPU12_NVRAM_BASE     (CS1_PHYS_BASE + 0x02000000)
 
+/* SmartMedia flash */
 #define AUTCPU12_SMC_BASE       (CS1_PHYS_BASE + 0x06000000)
 #define AUTCPU12_SMC_SEL_BASE   (AUTCPU12_SMC_BASE + 0x10)
 
+/* Ethernet */
+#define AUTCPU12_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
+#define AUTCPU12_CS8900_IRQ     (IRQ_EINT3)
+
+/* NAND flash */
 #define AUTCPU12_MMGPIO_BASE    (CLPS711X_NR_GPIO)
 #define AUTCPU12_SMC_NCE        (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
 #define AUTCPU12_SMC_RDY        CLPS711X_GPIO(1, 2)
 #define AUTCPU12_SMC_ALE        CLPS711X_GPIO(1, 3)
 #define AUTCPU12_SMC_CLE        CLPS711X_GPIO(1, 3)
 
+/* LCD contrast digital potentiometer */
+#define AUTCPU12_DPOT_CS        CLPS711X_GPIO(4, 0)
+#define AUTCPU12_DPOT_CLK       CLPS711X_GPIO(4, 1)
+#define AUTCPU12_DPOT_UD        CLPS711X_GPIO(4, 2)
+
 static struct resource autcpu12_cs8900_resource[] __initdata = {
         DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
         DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
 };
 
-static struct resource autcpu12_nvram_resource[] __initdata = {
-        DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
-};
-
-static struct platform_device autcpu12_nvram_pdev __initdata = {
-        .name           = "autcpu12_nvram",
-        .id             = -1,
-        .resource       = autcpu12_nvram_resource,
-        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
-};
-
 static struct resource autcpu12_nand_resource[] __initdata = {
         DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
 };
@@ -147,17 +160,106 @@ static struct platform_device autcpu12_mmgpio_pdev __initdata = {
         },
 };
 
+static const struct gpio autcpu12_gpios[] __initconst = {
+        { AUTCPU12_DPOT_CS,     GPIOF_OUT_INIT_HIGH,    "DPOT CS" },
+        { AUTCPU12_DPOT_CLK,    GPIOF_OUT_INIT_LOW,     "DPOT CLK" },
+        { AUTCPU12_DPOT_UD,     GPIOF_OUT_INIT_LOW,     "DPOT UD" },
+};
+
+static struct mtd_partition autcpu12_flash_partitions[] = {
+        {
+                .name   = "NOR.0",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct physmap_flash_data autcpu12_flash_pdata = {
+        .width          = 4,
+        .parts          = autcpu12_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(autcpu12_flash_partitions),
+};
+
+static struct resource autcpu12_flash_resources[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_FLASH_BASE, SZ_8M),
+};
+
+static struct platform_device autcpu12_flash_pdev __initdata = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .resource       = autcpu12_flash_resources,
+        .num_resources  = ARRAY_SIZE(autcpu12_flash_resources),
+        .dev            = {
+                .platform_data  = &autcpu12_flash_pdata,
+        },
+};
+
+static struct resource autcpu12_nvram_resource[] __initdata = {
+        DEFINE_RES_MEM(AUTCPU12_NVRAM_BASE, 0),
+};
+
+static struct platdata_mtd_ram autcpu12_nvram_pdata = {
+        .bankwidth      = 4,
+};
+
+static struct platform_device autcpu12_nvram_pdev __initdata = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = autcpu12_nvram_resource,
+        .num_resources  = ARRAY_SIZE(autcpu12_nvram_resource),
+        .dev            = {
+                .platform_data  = &autcpu12_nvram_pdata,
+        },
+};
+
+static void __init autcpu12_nvram_init(void)
+{
+        void __iomem *nvram;
+        unsigned int save[2];
+        resource_size_t nvram_size = SZ_128K;
+
+        /*
+         * Check for 32K/128K
+         * Read ofs 0K
+         * Read ofs 64K
+         * Write complement to ofs 64K
+         * Read and check result on ofs 0K
+         * Restore contents
+         */
+        nvram = ioremap(autcpu12_nvram_resource[0].start, SZ_128K);
+        if (nvram) {
+                save[0] = readl(nvram + 0);
+                save[1] = readl(nvram + SZ_64K);
+                writel(~save[0], nvram + SZ_64K);
+                if (readl(nvram + 0) != save[0]) {
+                        writel(save[0], nvram + 0);
+                        nvram_size = SZ_32K;
+                } else
+                        writel(save[1], nvram + SZ_64K);
+                iounmap(nvram);
+
+                autcpu12_nvram_resource[0].end =
+                        autcpu12_nvram_resource[0].start + nvram_size - 1;
+                platform_device_register(&autcpu12_nvram_pdev);
+        } else
+                pr_err("Failed to remap NVRAM resource\n");
+}
+
 static void __init autcpu12_init(void)
 {
+        clps711x_devices_init();
+        platform_device_register(&autcpu12_flash_pdev);
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
                                         ARRAY_SIZE(autcpu12_cs8900_resource));
         platform_device_register(&autcpu12_mmgpio_pdev);
-        platform_device_register(&autcpu12_nvram_pdev);
+        autcpu12_nvram_init();
 }
 
 static void __init autcpu12_init_late(void)
 {
+        gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
+
         if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
                 /* We are need both drivers to handle NAND */
                 platform_device_register(&autcpu12_nand_pdev);
@@ -169,6 +271,7 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
         .atag_offset    = 0x20000,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = autcpu12_init,
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c
index baab7da33c9b..a9e38c6bcfb4 100644
--- a/arch/arm/mach-clps711x/board-cdb89712.c
+++ b/arch/arm/mach-clps711x/board-cdb89712.c
@@ -39,6 +39,7 @@
 #include <asm/mach/map.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define CDB89712_CS8900_BASE    (CS2_PHYS_BASE + 0x300)
 #define CDB89712_CS8900_IRQ     (IRQ_EINT3)
@@ -127,6 +128,7 @@ static struct platform_device cdb89712_sram_pdev __initdata = {
 
 static void __init cdb89712_init(void)
 {
+        clps711x_devices_init();
         platform_device_register(&cdb89712_flash_pdev);
         platform_device_register(&cdb89712_bootrom_pdev);
         platform_device_register(&cdb89712_sram_pdev);
@@ -139,6 +141,7 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
         .atag_offset    = 0x100,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = cdb89712_init,
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 014aa3c19a03..b4764246d0f8 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -39,6 +39,7 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_clep7312,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 5f928e9ed2ef..9dfb990f0801 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -12,6 +12,7 @@
 #include <linux/delay.h>
 #include <linux/memblock.h>
 #include <linux/types.h>
+#include <linux/i2c-gpio.h>
 #include <linux/interrupt.h>
 #include <linux/backlight.h>
 #include <linux/platform_device.h>
@@ -29,6 +30,7 @@
 #include <mach/hardware.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define VIDEORAM_SIZE           SZ_128K
 
@@ -36,11 +38,24 @@
 #define EDB7211_LCDEN           CLPS711X_GPIO(3, 2)
 #define EDB7211_LCDBL           CLPS711X_GPIO(3, 3)
 
+#define EDB7211_I2C_SDA         CLPS711X_GPIO(3, 4)
+#define EDB7211_I2C_SCL         CLPS711X_GPIO(3, 5)
+
 #define EDB7211_FLASH0_BASE     (CS0_PHYS_BASE)
 #define EDB7211_FLASH1_BASE     (CS1_PHYS_BASE)
+
 #define EDB7211_CS8900_BASE     (CS2_PHYS_BASE + 0x300)
 #define EDB7211_CS8900_IRQ      (IRQ_EINT3)
 
+/* The extra 8 lines of the keyboard matrix */
+#define EDB7211_EXTKBD_BASE     (CS3_PHYS_BASE)
+
+static struct i2c_gpio_platform_data edb7211_i2c_pdata __initdata = {
+        .sda_pin        = EDB7211_I2C_SDA,
+        .scl_pin        = EDB7211_I2C_SCL,
+        .scl_is_output_only = 1,
+};
+
 static struct resource edb7211_cs8900_resource[] __initdata = {
         DEFINE_RES_MEM(EDB7211_CS8900_BASE, SZ_1K),
         DEFINE_RES_IRQ(EDB7211_CS8900_IRQ),
@@ -94,13 +109,14 @@ static struct plat_lcd_data edb7211_lcd_power_pdata = {
 
 static void edb7211_lcd_backlight_set_intensity(int intensity)
 {
-        gpio_set_value(EDB7211_LCDBL, intensity);
+        gpio_set_value(EDB7211_LCDBL, !!intensity);
+        clps_writel((clps_readl(PMPCON) & 0xf0ff) | (intensity << 8), PMPCON);
 }
 
 static struct generic_bl_info edb7211_lcd_backlight_pdata = {
         .name                   = "lcd-backlight.0",
         .default_intensity      = 0x01,
-        .max_intensity          = 0x01,
+        .max_intensity          = 0x0f,
         .set_bl_intensity       = edb7211_lcd_backlight_set_intensity,
 };
 
@@ -112,8 +128,8 @@ static struct gpio edb7211_gpios[] __initconst = {
 
 static struct map_desc edb7211_io_desc[] __initdata = {
         {       /* Memory-mapped extra keyboard row */
-                .virtual        = IO_ADDRESS(EP7211_PHYS_EXTKBD),
-                .pfn            = __phys_to_pfn(EP7211_PHYS_EXTKBD),
+                .virtual        = IO_ADDRESS(EDB7211_EXTKBD_BASE),
+                .pfn            = __phys_to_pfn(EDB7211_EXTKBD_BASE),
                 .length         = SZ_1M,
                 .type           = MT_DEVICE,
         },
@@ -151,6 +167,11 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
 
 static void __init edb7211_init(void)
 {
+        clps711x_devices_init();
+}
+
+static void __init edb7211_init_late(void)
+{
         gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios));
 
         platform_device_register(&edb7211_flash_pdev);
@@ -163,6 +184,9 @@ static void __init edb7211_init(void)
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
         platform_device_register_simple("cs89x0", 0, edb7211_cs8900_resource,
                                         ARRAY_SIZE(edb7211_cs8900_resource));
+        platform_device_register_data(&platform_bus, "i2c-gpio", 0,
+                                      &edb7211_i2c_pdata,
+                                      sizeof(edb7211_i2c_pdata));
 }
 
 MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
@@ -172,9 +196,11 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
         .fixup          = fixup_edb7211,
         .reserve        = edb7211_reserve,
         .map_io         = edb7211_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = edb7211_init,
+        .init_late      = edb7211_init_late,
         .handle_irq     = clps711x_handle_irq,
         .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
index c5675efc8c6a..b1561e3d7c5c 100644
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ b/arch/arm/mach-clps711x/board-fortunet.c
@@ -77,6 +77,7 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fortunet_fixup,
         .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .handle_irq     = clps711x_handle_irq,
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 8d3ee6771135..dd81b06f68fe 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -23,10 +23,12 @@
 #include <linux/string.h>
 #include <linux/mm.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/leds.h>
 #include <linux/sizes.h>
 #include <linux/backlight.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand-gpio.h>
@@ -38,11 +40,11 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <mach/syspld.h>
 
 #include <video/platform_lcd.h>
 
 #include "common.h"
+#include "devices.h"
 
 #define P720T_USERLED           CLPS711X_GPIO(3, 0)
 #define P720T_NAND_CLE          CLPS711X_GPIO(4, 0)
@@ -51,6 +53,178 @@
 
 #define P720T_NAND_BASE         (CLPS711X_SDRAM1_BASE)
 
+#define P720T_MMGPIO_BASE       (CLPS711X_NR_GPIO)
+
+#define SYSPLD_PHYS_BASE        IOMEM(CS1_PHYS_BASE)
+
+#define PLD_INT                 (SYSPLD_PHYS_BASE + 0x000000)
+#define PLD_INT_MMGPIO_BASE     (P720T_MMGPIO_BASE + 0)
+#define PLD_INT_PENIRQ          (PLD_INT_MMGPIO_BASE + 5)
+#define PLD_INT_UCB_IRQ         (PLD_INT_MMGPIO_BASE + 1)
+#define PLD_INT_KBD_ATN         (PLD_INT_MMGPIO_BASE + 0) /* EINT1 */
+
+#define PLD_PWR                 (SYSPLD_PHYS_BASE + 0x000004)
+#define PLD_PWR_MMGPIO_BASE     (P720T_MMGPIO_BASE + 8)
+#define PLD_PWR_EXT             (PLD_PWR_MMGPIO_BASE + 5)
+#define PLD_PWR_MODE            (PLD_PWR_MMGPIO_BASE + 4) /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON               (PLD_PWR_MMGPIO_BASE + 3) /* LCD bias voltage enable */
+#define PLD_S3_ON               (PLD_PWR_MMGPIO_BASE + 2) /* LCD backlight enable */
+#define PLD_S2_ON               (PLD_PWR_MMGPIO_BASE + 1) /* LCD 3V3 supply enable */
+#define PLD_S1_ON               (PLD_PWR_MMGPIO_BASE + 0) /* LCD 3V supply enable */
+
+#define PLD_KBD                 (SYSPLD_PHYS_BASE + 0x000008)
+#define PLD_KBD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 16)
+#define PLD_KBD_WAKE            (PLD_KBD_MMGPIO_BASE + 1)
+#define PLD_KBD_EN              (PLD_KBD_MMGPIO_BASE + 0)
+
+#define PLD_SPI                 (SYSPLD_PHYS_BASE + 0x00000c)
+#define PLD_SPI_MMGPIO_BASE     (P720T_MMGPIO_BASE + 24)
+#define PLD_SPI_EN              (PLD_SPI_MMGPIO_BASE + 0)
+
+#define PLD_IO                  (SYSPLD_PHYS_BASE + 0x000010)
+#define PLD_IO_MMGPIO_BASE      (P720T_MMGPIO_BASE + 32)
+#define PLD_IO_BOOTSEL          (PLD_IO_MMGPIO_BASE + 6) /* Boot sel switch */
+#define PLD_IO_USER             (PLD_IO_MMGPIO_BASE + 5) /* User defined switch */
+#define PLD_IO_LED3             (PLD_IO_MMGPIO_BASE + 4)
+#define PLD_IO_LED2             (PLD_IO_MMGPIO_BASE + 3)
+#define PLD_IO_LED1             (PLD_IO_MMGPIO_BASE + 2)
+#define PLD_IO_LED0             (PLD_IO_MMGPIO_BASE + 1)
+#define PLD_IO_LEDEN            (PLD_IO_MMGPIO_BASE + 0)
+
+#define PLD_IRDA                (SYSPLD_PHYS_BASE + 0x000014)
+#define PLD_IRDA_MMGPIO_BASE    (P720T_MMGPIO_BASE + 40)
+#define PLD_IRDA_EN             (PLD_IRDA_MMGPIO_BASE + 0)
+
+#define PLD_COM2                (SYSPLD_PHYS_BASE + 0x000018)
+#define PLD_COM2_MMGPIO_BASE    (P720T_MMGPIO_BASE + 48)
+#define PLD_COM2_EN             (PLD_COM2_MMGPIO_BASE + 0)
+
+#define PLD_COM1                (SYSPLD_PHYS_BASE + 0x00001c)
+#define PLD_COM1_MMGPIO_BASE    (P720T_MMGPIO_BASE + 56)
+#define PLD_COM1_EN             (PLD_COM1_MMGPIO_BASE + 0)
+
+#define PLD_AUD                 (SYSPLD_PHYS_BASE + 0x000020)
+#define PLD_AUD_MMGPIO_BASE     (P720T_MMGPIO_BASE + 64)
+#define PLD_AUD_DIV1            (PLD_AUD_MMGPIO_BASE + 6)
+#define PLD_AUD_DIV0            (PLD_AUD_MMGPIO_BASE + 5)
+#define PLD_AUD_CLK_SEL1        (PLD_AUD_MMGPIO_BASE + 4)
+#define PLD_AUD_CLK_SEL0        (PLD_AUD_MMGPIO_BASE + 3)
+#define PLD_AUD_MIC_PWR         (PLD_AUD_MMGPIO_BASE + 2)
+#define PLD_AUD_MIC_GAIN        (PLD_AUD_MMGPIO_BASE + 1)
+#define PLD_AUD_CODEC_EN        (PLD_AUD_MMGPIO_BASE + 0)
+
+#define PLD_CF                  (SYSPLD_PHYS_BASE + 0x000024)
+#define PLD_CF_MMGPIO_BASE      (P720T_MMGPIO_BASE + 72)
+#define PLD_CF2_SLEEP           (PLD_CF_MMGPIO_BASE + 5)
+#define PLD_CF1_SLEEP           (PLD_CF_MMGPIO_BASE + 4)
+#define PLD_CF2_nPDREQ          (PLD_CF_MMGPIO_BASE + 3)
+#define PLD_CF1_nPDREQ          (PLD_CF_MMGPIO_BASE + 2)
+#define PLD_CF2_nIRQ            (PLD_CF_MMGPIO_BASE + 1)
+#define PLD_CF1_nIRQ            (PLD_CF_MMGPIO_BASE + 0)
+
+#define PLD_SDC                 (SYSPLD_PHYS_BASE + 0x000028)
+#define PLD_SDC_MMGPIO_BASE     (P720T_MMGPIO_BASE + 80)
+#define PLD_SDC_INT_EN          (PLD_SDC_MMGPIO_BASE + 2)
+#define PLD_SDC_WP              (PLD_SDC_MMGPIO_BASE + 1)
+#define PLD_SDC_CD              (PLD_SDC_MMGPIO_BASE + 0)
+
+#define PLD_CODEC               (SYSPLD_PHYS_BASE + 0x400000)
+#define PLD_CODEC_MMGPIO_BASE   (P720T_MMGPIO_BASE + 88)
+#define PLD_CODEC_IRQ3          (PLD_CODEC_MMGPIO_BASE + 4)
+#define PLD_CODEC_IRQ2          (PLD_CODEC_MMGPIO_BASE + 3)
+#define PLD_CODEC_IRQ1          (PLD_CODEC_MMGPIO_BASE + 2)
+#define PLD_CODEC_EN            (PLD_CODEC_MMGPIO_BASE + 0)
+
+#define PLD_BRITE               (SYSPLD_PHYS_BASE + 0x400004)
+#define PLD_BRITE_MMGPIO_BASE   (P720T_MMGPIO_BASE + 96)
+#define PLD_BRITE_UP            (PLD_BRITE_MMGPIO_BASE + 1)
+#define PLD_BRITE_DN            (PLD_BRITE_MMGPIO_BASE + 0)
+
+#define PLD_LCDEN               (SYSPLD_PHYS_BASE + 0x400008)
+#define PLD_LCDEN_MMGPIO_BASE   (P720T_MMGPIO_BASE + 104)
+#define PLD_LCDEN_EN            (PLD_LCDEN_MMGPIO_BASE + 0)
+
+#define PLD_TCH                 (SYSPLD_PHYS_BASE + 0x400010)
+#define PLD_TCH_MMGPIO_BASE     (P720T_MMGPIO_BASE + 112)
+#define PLD_TCH_PENIRQ          (PLD_TCH_MMGPIO_BASE + 1)
+#define PLD_TCH_EN              (PLD_TCH_MMGPIO_BASE + 0)
+
+#define PLD_GPIO                (SYSPLD_PHYS_BASE + 0x400014)
+#define PLD_GPIO_MMGPIO_BASE    (P720T_MMGPIO_BASE + 120)
+#define PLD_GPIO2               (PLD_GPIO_MMGPIO_BASE + 2)
+#define PLD_GPIO1               (PLD_GPIO_MMGPIO_BASE + 1)
+#define PLD_GPIO0               (PLD_GPIO_MMGPIO_BASE + 0)
+
+static struct gpio p720t_gpios[] __initconst = {
+        { PLD_S1_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S1_ON" },
+        { PLD_S2_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S2_ON" },
+        { PLD_S3_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S3_ON" },
+        { PLD_S4_ON,    GPIOF_OUT_INIT_LOW,     "PLD_S4_ON" },
+        { PLD_KBD_EN,   GPIOF_OUT_INIT_LOW,     "PLD_KBD_EN" },
+        { PLD_SPI_EN,   GPIOF_OUT_INIT_LOW,     "PLD_SPI_EN" },
+        { PLD_IO_USER,  GPIOF_OUT_INIT_LOW,     "PLD_IO_USER" },
+        { PLD_IO_LED0,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED0" },
+        { PLD_IO_LED1,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED1" },
+        { PLD_IO_LED2,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED2" },
+        { PLD_IO_LED3,  GPIOF_OUT_INIT_LOW,     "PLD_IO_LED3" },
+        { PLD_IO_LEDEN, GPIOF_OUT_INIT_LOW,     "PLD_IO_LEDEN" },
+        { PLD_IRDA_EN,  GPIOF_OUT_INIT_LOW,     "PLD_IRDA_EN" },
+        { PLD_COM1_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM1_EN" },
+        { PLD_COM2_EN,  GPIOF_OUT_INIT_HIGH,    "PLD_COM2_EN" },
+        { PLD_CODEC_EN, GPIOF_OUT_INIT_LOW,     "PLD_CODEC_EN" },
+        { PLD_LCDEN_EN, GPIOF_OUT_INIT_LOW,     "PLD_LCDEN_EN" },
+        { PLD_TCH_EN,   GPIOF_OUT_INIT_LOW,     "PLD_TCH_EN" },
+        { P720T_USERLED,GPIOF_OUT_INIT_LOW,     "USER_LED" },
+};
+
+static struct resource p720t_mmgpio_resource[] __initdata = {
+        DEFINE_RES_MEM_NAMED(0, 4, "dat"),
+};
+
+static struct bgpio_pdata p720t_mmgpio_pdata = {
+        .ngpio  = 8,
+};
+
+static struct platform_device p720t_mmgpio __initdata = {
+        .name           = "basic-mmio-gpio",
+        .id             = -1,
+        .resource       = p720t_mmgpio_resource,
+        .num_resources  = ARRAY_SIZE(p720t_mmgpio_resource),
+        .dev            = {
+                .platform_data  = &p720t_mmgpio_pdata,
+        },
+};
+
+static void __init p720t_mmgpio_init(void __iomem *addrbase, int gpiobase)
+{
+        p720t_mmgpio_resource[0].start = (unsigned long)addrbase;
+        p720t_mmgpio_pdata.base = gpiobase;
+
+        platform_device_register(&p720t_mmgpio);
+}
+
+static struct {
+        void __iomem    *addrbase;
+        int             gpiobase;
+} mmgpios[] __initconst = {
+        { PLD_INT,      PLD_INT_MMGPIO_BASE },
+        { PLD_PWR,      PLD_PWR_MMGPIO_BASE },
+        { PLD_KBD,      PLD_KBD_MMGPIO_BASE },
+        { PLD_SPI,      PLD_SPI_MMGPIO_BASE },
+        { PLD_IO,       PLD_IO_MMGPIO_BASE },
+        { PLD_IRDA,     PLD_IRDA_MMGPIO_BASE },
+        { PLD_COM2,     PLD_COM2_MMGPIO_BASE },
+        { PLD_COM1,     PLD_COM1_MMGPIO_BASE },
+        { PLD_AUD,      PLD_AUD_MMGPIO_BASE },
+        { PLD_CF,       PLD_CF_MMGPIO_BASE },
+        { PLD_SDC,      PLD_SDC_MMGPIO_BASE },
+        { PLD_CODEC,    PLD_CODEC_MMGPIO_BASE },
+        { PLD_BRITE,    PLD_BRITE_MMGPIO_BASE },
+        { PLD_LCDEN,    PLD_LCDEN_MMGPIO_BASE },
+        { PLD_TCH,      PLD_TCH_MMGPIO_BASE },
+        { PLD_GPIO,     PLD_GPIO_MMGPIO_BASE },
+};
+
 static struct resource p720t_nand_resource[] __initdata = {
         DEFINE_RES_MEM(P720T_NAND_BASE, SZ_4),
 };
@@ -92,11 +266,15 @@ static struct platform_device p720t_nand_pdev __initdata = {
 static void p720t_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
 {
         if (power) {
-                PLD_LCDEN = PLD_LCDEN_EN;
-                PLD_PWR |= PLD_S4_ON | PLD_S2_ON | PLD_S1_ON;
+                gpio_set_value(PLD_LCDEN_EN, 1);
+                gpio_set_value(PLD_S1_ON, 1);
+                gpio_set_value(PLD_S2_ON, 1);
+                gpio_set_value(PLD_S4_ON, 1);
         } else {
-                PLD_PWR &= ~(PLD_S4_ON | PLD_S2_ON | PLD_S1_ON);
-                PLD_LCDEN = 0;
+                gpio_set_value(PLD_S1_ON, 0);
+                gpio_set_value(PLD_S2_ON, 0);
+                gpio_set_value(PLD_S4_ON, 0);
+                gpio_set_value(PLD_LCDEN_EN, 0);
         }
 }
 
@@ -106,10 +284,7 @@ static struct plat_lcd_data p720t_lcd_power_pdata = {
 
 static void p720t_lcd_backlight_set_intensity(int intensity)
 {
-        if (intensity)
-                PLD_PWR |= PLD_S3_ON;
-        else
-                PLD_PWR = 0;
+        gpio_set_value(PLD_S3_ON, intensity);
 }
 
 static struct generic_bl_info p720t_lcd_backlight_pdata = {
@@ -119,19 +294,6 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
         .set_bl_intensity       = p720t_lcd_backlight_set_intensity,
 };
 
-/*
- * Map the P720T system PLD. It occupies two address spaces:
- * 0x10000000 and 0x10400000. We map both regions as one.
- */
-static struct map_desc p720t_io_desc[] __initdata = {
-        {
-                .virtual        = SYSPLD_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SYSPLD_PHYS_BASE),
-                .length         = SZ_8M,
-                .type           = MT_DEVICE,
-        },
-};
-
 static void __init
 fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
 {
@@ -157,33 +319,6 @@ fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
         }
 }
 
-static void __init p720t_map_io(void)
-{
-        clps711x_map_io();
-        iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
-}
-
-static void __init p720t_init_early(void)
-{
-        /*
-         * Power down as much as possible in case we don't
-         * have the drivers loaded.
-         */
-        PLD_LCDEN = 0;
-        PLD_PWR  &= ~(PLD_S4_ON|PLD_S3_ON|PLD_S2_ON|PLD_S1_ON);
-
-        PLD_KBD   = 0;
-        PLD_IO    = 0;
-        PLD_IRDA  = 0;
-        PLD_CODEC = 0;
-        PLD_TCH   = 0;
-        PLD_SPI   = 0;
-        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
-                PLD_COM2 = 0;
-                PLD_COM1 = 0;
-        }
-}
-
 static struct gpio_led p720t_gpio_leds[] = {
         {
                 .name                   = "User LED",
@@ -199,7 +334,20 @@ static struct gpio_led_platform_data p720t_gpio_led_pdata __initdata = {
 
 static void __init p720t_init(void)
 {
+        int i;
+
+        clps711x_devices_init();
+
+        for (i = 0; i < ARRAY_SIZE(mmgpios); i++)
+                p720t_mmgpio_init(mmgpios[i].addrbase, mmgpios[i].gpiobase);
+
         platform_device_register(&p720t_nand_pdev);
+}
+
+static void __init p720t_init_late(void)
+{
+        WARN_ON(gpio_request_array(p720t_gpios, ARRAY_SIZE(p720t_gpios)));
+
         platform_device_register_data(&platform_bus, "platform-lcd", 0,
                                       &p720t_lcd_power_pdata,
                                       sizeof(p720t_lcd_power_pdata));
@@ -207,10 +355,6 @@ static void __init p720t_init(void)
                                       &p720t_lcd_backlight_pdata,
                                       sizeof(p720t_lcd_backlight_pdata));
         platform_device_register_simple("video-clps711x", 0, NULL, 0);
-}
-
-static void __init p720t_init_late(void)
-{
         platform_device_register_data(&platform_bus, "leds-gpio", 0,
                                       &p720t_gpio_led_pdata,
                                       sizeof(p720t_gpio_led_pdata));
@@ -221,8 +365,8 @@ MACHINE_START(P720T, "ARM-Prospector720T")
         .atag_offset    = 0x100,
         .nr_irqs        = CLPS711X_NR_IRQS,
         .fixup          = fixup_p720t,
-        .map_io         = p720t_map_io,
-        .init_early     = p720t_init_early,
+        .map_io         = clps711x_map_io,
+        .init_early     = clps711x_init_early,
         .init_irq       = clps711x_init_irq,
         .init_time      = clps711x_timer_init,
         .init_machine   = p720t_init,
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index 20ff50f3ccf0..f6d1746366d4 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -27,12 +27,14 @@
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/clockchips.h>
+#include <linux/clocksource.h>
 #include <linux/clk-provider.h>
 
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/sched_clock.h>
 #include <asm/system_misc.h>
 
 #include <mach/hardware.h>
@@ -213,7 +215,7 @@ void __init clps711x_init_irq(void)
         }
 }
 
-inline u32 fls16(u32 x)
+static inline u32 fls16(u32 x)
 {
         u32 r = 15;
 
@@ -237,27 +239,52 @@ inline u32 fls16(u32 x)
 
 asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs)
 {
-        u32 irqstat;
-        void __iomem *base = CLPS711X_VIRT_BASE;
-
-        irqstat = readl_relaxed(base + INTSR1) & readl_relaxed(base + INTMR1);
-        if (irqstat) {
-                handle_IRQ(fls16(irqstat), regs);
-                return;
-        }
+        do {
+                u32 irqstat;
+                void __iomem *base = CLPS711X_VIRT_BASE;
+
+                irqstat = readw_relaxed(base + INTSR1) &
+                          readw_relaxed(base + INTMR1);
+                if (irqstat)
+                        handle_IRQ(fls16(irqstat), regs);
+
+                irqstat = readw_relaxed(base + INTSR2) &
+                          readw_relaxed(base + INTMR2);
+                if (irqstat) {
+                        handle_IRQ(fls16(irqstat) + 16, regs);
+                        continue;
+                }
+
+                break;
+        } while (1);
+}
 
-        irqstat = readl_relaxed(base + INTSR2) & readl_relaxed(base + INTMR2);
-        if (likely(irqstat))
-                handle_IRQ(fls16(irqstat) + 16, regs);
+static u32 notrace clps711x_sched_clock_read(void)
+{
+        return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D);
 }
 
 static void clps711x_clockevent_set_mode(enum clock_event_mode mode,
                                          struct clock_event_device *evt)
 {
+        disable_irq(IRQ_TC2OI);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                enable_irq(IRQ_TC2OI);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Not supported */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                /* Left event sources disabled, no more interrupts appear */
+                break;
+        }
 }
 
 static struct clock_event_device clockevent_clps711x = {
-        .name           = "CLPS711x Clockevents",
+        .name           = "clps711x-clockevent",
         .rating         = 300,
         .features       = CLOCK_EVT_FEAT_PERIODIC,
         .set_mode       = clps711x_clockevent_set_mode,
@@ -271,8 +298,8 @@ static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id)
 }
 
 static struct irqaction clps711x_timer_irq = {
-        .name           = "CLPS711x Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .name           = "clps711x-timer",
+        .flags          = IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = clps711x_timer_interrupt,
 };
 
@@ -301,6 +328,7 @@ void __init clps711x_timer_init(void)
                 cpu = ext;
                 bus = cpu;
                 spi = 135400;
+                pll = 0;
         } else {
                 cpu = pll;
                 if (cpu >= 36864000)
@@ -319,9 +347,9 @@ void __init clps711x_timer_init(void)
                 else
                         timh = 541440;
         } else
-                timh = cpu / 144;
+                timh = DIV_ROUND_CLOSEST(cpu, 144);
 
-        timl = timh / 256;
+        timl = DIV_ROUND_CLOSEST(timh, 256);
 
         /* All clocks are fixed */
         add_fixed_clk(clk_pll, "pll", pll);
@@ -334,13 +362,24 @@ void __init clps711x_timer_init(void)
 
         pr_info("CPU frequency set at %i Hz.\n", cpu);
 
+        /* Start Timer1 in free running mode (Low frequency) */
+        tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M);
+        clps_writel(tmp, SYSCON1);
+
+        setup_sched_clock(clps711x_sched_clock_read, 16, timl);
+
+        clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D,
+                              "clps711x_clocksource", timl, 300, 16,
+                              clocksource_mmio_readw_down);
+
+        /* Set Timer2 prescaler */
         clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D);
 
-        tmp = clps_readl(SYSCON1);
-        tmp |= SYSCON1_TC2S | SYSCON1_TC2M;
+        /* Start Timer2 in prescale mode (High frequency)*/
+        tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S;
         clps_writel(tmp, SYSCON1);
 
-        clockevents_config_and_register(&clockevent_clps711x, timh, 1, 0xffff);
+        clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0);
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
 }
@@ -353,15 +392,11 @@ void clps711x_restart(char mode, const char *cmd)
 static void clps711x_idle(void)
 {
         clps_writel(1, HALT);
-        __asm__ __volatile__(
-        "mov    r0, r0\n\
-        mov     r0, r0");
+        asm("mov r0, r0");
+        asm("mov r0, r0");
 }
 
-static int __init clps711x_idle_init(void)
+void __init clps711x_init_early(void)
 {
         arm_pm_idle = clps711x_idle;
-        return 0;
 }
-
-arch_initcall(clps711x_idle_init);
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index f84a7292c70e..2a22f4c6cc75 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -13,3 +13,4 @@ extern void clps711x_init_irq(void);
 extern void clps711x_timer_init(void);
 extern void clps711x_handle_irq(struct pt_regs *regs);
 extern void clps711x_restart(char mode, const char *cmd);
+extern void clps711x_init_early(void);
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
new file mode 100644
index 000000000000..856b81cf2f8a
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.c
@@ -0,0 +1,68 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Author: Alexander Shiyan <shc_work@mail.ru>, 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/sizes.h>
+
+#include <mach/hardware.h>
+
+static const phys_addr_t clps711x_gpios[][2] __initconst = {
+        { PADR, PADDR },
+        { PBDR, PBDDR },
+        { PCDR, PCDDR },
+        { PDDR, PDDDR },
+        { PEDR, PEDDR },
+};
+
+static void __init clps711x_add_gpio(void)
+{
+        unsigned i;
+        struct resource gpio_res[2];
+
+        memset(gpio_res, 0, sizeof(gpio_res));
+
+        gpio_res[0].flags = IORESOURCE_MEM;
+        gpio_res[1].flags = IORESOURCE_MEM;
+
+        for (i = 0; i < ARRAY_SIZE(clps711x_gpios); i++) {
+                gpio_res[0].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][0];
+                gpio_res[0].end = gpio_res[0].start;
+                gpio_res[1].start = CLPS711X_PHYS_BASE + clps711x_gpios[i][1];
+                gpio_res[1].end = gpio_res[1].start;
+
+                platform_device_register_simple("clps711x-gpio", i,
+                                                gpio_res, ARRAY_SIZE(gpio_res));
+        }
+}
+
+const struct resource clps711x_syscon_res[] __initconst = {
+        /* SYSCON1, SYSFLG1 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON1, SZ_128),
+        /* SYSCON2, SYSFLG2 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON2, SZ_128),
+        /* SYSCON3 */
+        DEFINE_RES_MEM(CLPS711X_PHYS_BASE + SYSCON3, SZ_64),
+};
+
+static void __init clps711x_add_syscon(void)
+{
+        unsigned i;
+
+        for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
+                platform_device_register_simple("clps711x-syscon", i + 1,
+                                                &clps711x_syscon_res[i], 1);
+}
+
+void __init clps711x_devices_init(void)
+{
+        clps711x_add_gpio();
+        clps711x_add_syscon();
+}
diff --git a/arch/arm/mach-clps711x/devices.h b/arch/arm/mach-clps711x/devices.h
new file mode 100644
index 000000000000..a5efc1744b84
--- /dev/null
+++ b/arch/arm/mach-clps711x/devices.h
@@ -0,0 +1,12 @@
+/*
+ *  CLPS711X common devices definitions
+ *
+ *  Copyright (C) 2013 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+void clps711x_devices_init(void);
diff --git a/arch/arm/mach-clps711x/include/mach/autcpu12.h b/arch/arm/mach-clps711x/include/mach/autcpu12.h
deleted file mode 100644
index 0452f5f3f034..000000000000
--- a/arch/arm/mach-clps711x/include/mach/autcpu12.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * AUTCPU12 specific defines
- *
- * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_AUTCPU12_H
-#define __ASM_ARCH_AUTCPU12_H
-
-/*
- * The flash bank is wired to chip select 0
- */
-#define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
-
-/* offset for device specific information structure */
-#define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
-
-/* Videomemory in the internal SRAM (CS 6) */
-#define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
-
-/*
-* All special IO's are tied to CS1
-*/
-#define AUTCPU12_PHYS_CHAR_LCD          CS1_PHYS_BASE +0x00000000  /* physical */
-
-#define AUTCPU12_PHYS_NVRAM             CS1_PHYS_BASE +0x02000000  /* physical */
-
-#define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
-
-#define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
-
-#define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
-
-#define AUTCPU12_PHYS_IO                CS1_PHYS_BASE +0x0C000000  /* physical */
-
-#define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
-
-/*
-* defines for lcd contrast 
-*/
-#define AUTCPU12_DPOT_PORT_OFFSET       PEDR
-#define AUTCPU12_DPOT_CS                (1<<0)
-#define AUTCPU12_DPOT_CLK               (1<<1)
-#define AUTCPU12_DPOT_UD                (1<<2)
-
-#endif
diff --git a/arch/arm/mach-clps711x/include/mach/clps711x.h b/arch/arm/mach-clps711x/include/mach/clps711x.h
index 01d1b9559710..0286f4bf9945 100644
--- a/arch/arm/mach-clps711x/include/mach/clps711x.h
+++ b/arch/arm/mach-clps711x/include/mach/clps711x.h
@@ -21,6 +21,8 @@
 #ifndef __MACH_CLPS711X_H
 #define __MACH_CLPS711X_H
 
+#include <linux/mfd/syscon/clps711x.h>
+
 #define CLPS711X_PHYS_BASE      (0x80000000)
 
 #define PADR            (0x0000)
@@ -96,83 +98,9 @@
 #define RANDID2         (0x2708)
 #define RANDID3         (0x270c)
 
-/* common bits: SYSCON1 / SYSCON2 */
-#define SYSCON_UARTEN           (1 << 8)
-
-#define SYSCON1_KBDSCAN(x)      ((x) & 15)
-#define SYSCON1_KBDSCANMASK     (15)
-#define SYSCON1_TC1M            (1 << 4)
-#define SYSCON1_TC1S            (1 << 5)
-#define SYSCON1_TC2M            (1 << 6)
-#define SYSCON1_TC2S            (1 << 7)
-#define SYSCON1_UART1EN         SYSCON_UARTEN
-#define SYSCON1_BZTOG           (1 << 9)
-#define SYSCON1_BZMOD           (1 << 10)
-#define SYSCON1_DBGEN           (1 << 11)
-#define SYSCON1_LCDEN           (1 << 12)
-#define SYSCON1_CDENTX          (1 << 13)
-#define SYSCON1_CDENRX          (1 << 14)
-#define SYSCON1_SIREN           (1 << 15)
-#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
-#define SYSCON1_ADCKSEL_MASK    (3 << 16)
-#define SYSCON1_EXCKEN          (1 << 18)
-#define SYSCON1_WAKEDIS         (1 << 19)
-#define SYSCON1_IRTXM           (1 << 20)
-
-/* common bits: SYSFLG1 / SYSFLG2 */
-#define SYSFLG_UBUSY            (1 << 11)
-#define SYSFLG_URXFE            (1 << 22)
-#define SYSFLG_UTXFF            (1 << 23)
-
-#define SYSFLG1_MCDR            (1 << 0)
-#define SYSFLG1_DCDET           (1 << 1)
-#define SYSFLG1_WUDR            (1 << 2)
-#define SYSFLG1_WUON            (1 << 3)
-#define SYSFLG1_CTS             (1 << 8)
-#define SYSFLG1_DSR             (1 << 9)
-#define SYSFLG1_DCD             (1 << 10)
-#define SYSFLG1_UBUSY           SYSFLG_UBUSY
-#define SYSFLG1_NBFLG           (1 << 12)
-#define SYSFLG1_RSTFLG          (1 << 13)
-#define SYSFLG1_PFFLG           (1 << 14)
-#define SYSFLG1_CLDFLG          (1 << 15)
-#define SYSFLG1_URXFE           SYSFLG_URXFE
-#define SYSFLG1_UTXFF           SYSFLG_UTXFF
-#define SYSFLG1_CRXFE           (1 << 24)
-#define SYSFLG1_CTXFF           (1 << 25)
-#define SYSFLG1_SSIBUSY         (1 << 26)
-#define SYSFLG1_ID              (1 << 29)
-#define SYSFLG1_VERID(x)        (((x) >> 30) & 3)
-#define SYSFLG1_VERID_MASK      (3 << 30)
-
-#define SYSFLG2_SSRXOF          (1 << 0)
-#define SYSFLG2_RESVAL          (1 << 1)
-#define SYSFLG2_RESFRM          (1 << 2)
-#define SYSFLG2_SS2RXFE         (1 << 3)
-#define SYSFLG2_SS2TXFF         (1 << 4)
-#define SYSFLG2_SS2TXUF         (1 << 5)
-#define SYSFLG2_CKMODE          (1 << 6)
-#define SYSFLG2_UBUSY           SYSFLG_UBUSY
-#define SYSFLG2_URXFE           SYSFLG_URXFE
-#define SYSFLG2_UTXFF           SYSFLG_UTXFF
-
 #define LCDCON_GSEN             (1 << 30)
 #define LCDCON_GSMD             (1 << 31)
 
-#define SYSCON2_SERSEL          (1 << 0)
-#define SYSCON2_KBD6            (1 << 1)
-#define SYSCON2_DRAMZ           (1 << 2)
-#define SYSCON2_KBWEN           (1 << 3)
-#define SYSCON2_SS2TXEN         (1 << 4)
-#define SYSCON2_PCCARD1         (1 << 5)
-#define SYSCON2_PCCARD2         (1 << 6)
-#define SYSCON2_SS2RXEN         (1 << 7)
-#define SYSCON2_UART2EN         SYSCON_UARTEN
-#define SYSCON2_SS2MAEN         (1 << 9)
-#define SYSCON2_OSTB            (1 << 12)
-#define SYSCON2_CLKENSL         (1 << 13)
-#define SYSCON2_BUZFREQ         (1 << 14)
-
 /* common bits: UARTDR1 / UARTDR2 */
 #define UARTDR_FRMERR           (1 << 8)
 #define UARTDR_PARERR           (1 << 9)
@@ -228,18 +156,6 @@
 #define DAI64FS_MCLK256EN       (1 << 3)
 #define DAI64FS_LOOPBACK        (1 << 5)
 
-#define SYSCON3_ADCCON          (1 << 0)
-#define SYSCON3_CLKCTL0         (1 << 1)
-#define SYSCON3_CLKCTL1         (1 << 2)
-#define SYSCON3_DAISEL          (1 << 3)
-#define SYSCON3_ADCCKNSEN       (1 << 4)
-#define SYSCON3_VERSN(x)        (((x) >> 5) & 7)
-#define SYSCON3_VERSN_MASK      (7 << 5)
-#define SYSCON3_FASTWAKE        (1 << 8)
-#define SYSCON3_DAIEN           (1 << 9)
-#define SYSCON3_128FS           SYSCON3_DAIEN
-#define SYSCON3_ENPD67          (1 << 10)
-
 #define SDCONF_ACTIVE           (1 << 10)
 #define SDCONF_CLKCTL           (1 << 9)
 #define SDCONF_WIDTH_4          (0 << 7)
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h
index 2f23dd5d73e4..c5a8ea6839ef 100644
--- a/arch/arm/mach-clps711x/include/mach/hardware.h
+++ b/arch/arm/mach-clps711x/include/mach/hardware.h
@@ -70,11 +70,4 @@
 #define CLPS711X_SDRAM0_BASE    (0xc0000000)
 #define CLPS711X_SDRAM1_BASE    (0xd0000000)
 
-#if defined (CONFIG_ARCH_EDB7211)
-
-/* The extra 8 lines of the keyboard matrix are wired to chip select 3 */
-#define EP7211_PHYS_EXTKBD      CS3_PHYS_BASE
-
-#endif /* CONFIG_ARCH_EDB7211 */
-
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
deleted file mode 100644
index fc0e028d9405..000000000000
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/memory.h
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET        UL(0xc0000000)
-
-/*
- * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
- * uses only one of the two banks (bank #1).  However, even within
- * bank #1, memory is discontiguous.
- *
- * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
- * them, so we use 24 for the node max shift to get 16MB node sizes.
- */
-
-#define SECTION_SIZE_BITS       24
-#define MAX_PHYSMEM_BITS        32
-
-#endif
-
diff --git a/arch/arm/mach-clps711x/include/mach/syspld.h b/arch/arm/mach-clps711x/include/mach/syspld.h
deleted file mode 100644
index 9a433155bf58..000000000000
--- a/arch/arm/mach-clps711x/include/mach/syspld.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/syspld.h
- *
- *  System Control PLD register definitions.
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_SYSPLD_H
-#define __ASM_ARCH_SYSPLD_H
-
-#define SYSPLD_PHYS_BASE        (0x10000000)
-#define SYSPLD_VIRT_BASE        IO_ADDRESS(SYSPLD_PHYS_BASE)
-
-#define SYSPLD_REG(type, off)   (*(volatile type *)(SYSPLD_VIRT_BASE + (off)))
-
-#define PLD_INT         SYSPLD_REG(u32, 0x000000)
-#define PLD_INT_PENIRQ          (1 << 5)
-#define PLD_INT_UCB_IRQ         (1 << 1)
-#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
-
-#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
-#define PLD_PWR_EXT             (1 << 5)
-#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
-#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
-#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
-#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
-#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
-
-#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
-#define PLD_KBD_WAKE            (1 << 1)
-#define PLD_KBD_EN              (1 << 0)
-
-#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
-#define PLD_SPI_EN              (1 << 0)
-
-#define PLD_IO          SYSPLD_REG(u32, 0x000010)
-#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
-#define PLD_IO_USER             (1 << 5)        /* user defined switch */
-#define PLD_IO_LED3             (1 << 4)
-#define PLD_IO_LED2             (1 << 3)
-#define PLD_IO_LED1             (1 << 2)
-#define PLD_IO_LED0             (1 << 1)
-#define PLD_IO_LEDEN            (1 << 0)
-
-#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
-#define PLD_IRDA_EN             (1 << 0)
-
-#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
-#define PLD_COM2_EN             (1 << 0)
-
-#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
-#define PLD_COM1_EN             (1 << 0)
-
-#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
-#define PLD_AUD_DIV1            (1 << 6)
-#define PLD_AUD_DIV0            (1 << 5)
-#define PLD_AUD_CLK_SEL1        (1 << 4)
-#define PLD_AUD_CLK_SEL0        (1 << 3)
-#define PLD_AUD_MIC_PWR         (1 << 2)
-#define PLD_AUD_MIC_GAIN        (1 << 1)
-#define PLD_AUD_CODEC_EN        (1 << 0)
-
-#define PLD_CF          SYSPLD_REG(u32, 0x000024)
-#define PLD_CF2_SLEEP           (1 << 5)
-#define PLD_CF1_SLEEP           (1 << 4)
-#define PLD_CF2_nPDREQ          (1 << 3)
-#define PLD_CF1_nPDREQ          (1 << 2)
-#define PLD_CF2_nIRQ            (1 << 1)
-#define PLD_CF1_nIRQ            (1 << 0)
-
-#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
-#define PLD_SDC_INT_EN          (1 << 2)
-#define PLD_SDC_WP              (1 << 1)
-#define PLD_SDC_CD              (1 << 0)
-
-#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
-
-#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
-#define PLD_CODEC_IRQ3          (1 << 4)
-#define PLD_CODEC_IRQ2          (1 << 3)
-#define PLD_CODEC_IRQ1          (1 << 2)
-#define PLD_CODEC_EN            (1 << 0)
-
-#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
-#define PLD_BRITE_UP            (1 << 1)
-#define PLD_BRITE_DN            (1 << 0)
-
-#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
-#define PLD_LCDEN_EN            (1 << 0)
-
-#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
-
-#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
-#define PLD_TCH_PENIRQ          (1 << 1)
-#define PLD_TCH_EN              (1 << 0)
-
-#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
-#define PLD_GPIO2               (1 << 2)
-#define PLD_GPIO1               (1 << 1)
-#define PLD_GPIO0               (1 << 0)
-
-#endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..e026b19b23ea 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -40,6 +40,7 @@ config ARCH_DAVINCI_DA850
         bool "DA850/OMAP-L138/AM18x based system"
         select ARCH_DAVINCI_DA8XX
         select ARCH_HAS_CPUFREQ
+        select CPU_FREQ_TABLE
         select CP_INTC
 
 config ARCH_DAVINCI_DA8XX
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index dd1ffccc75e9..63997a1128e6 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,7 +5,7 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o psc.o \
-                           dma.o usb.o common.o sram.o aemif.o
+                           usb.o common.o sram.o aemif.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 8a24b6c6339f..bea6793a7ede 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -985,7 +985,6 @@ static struct regulator_init_data tps65070_regulator_data[] = {
 static struct touchscreen_init_data tps6507x_touchscreen_data = {
         .poll_period =  30,     /* ms between touch samples */
         .min_pressure = 0x30,   /* minimum pressure to trigger touch */
-        .vref = 0,              /* turn off vref when not using A/D */
         .vendor = 0,            /* /sys/class/input/input?/id/vendor */
         .product = 65070,       /* /sys/class/input/input?/id/product */
         .version = 0x100,       /* /sys/class/input/input?/id/version */
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 739be7e738fe..513eee14f77d 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -151,7 +151,6 @@ static __init void davinci_sffsdr_init(void)
 }
 
 MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
-        /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
         .atag_offset  = 0x100,
         .map_io       = davinci_sffsdr_map_io,
         .init_irq     = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index ba798370fc96..78ea395d2aca 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -26,12 +26,12 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/mux.h>
 #include <mach/cp_intc.h>
 #include <mach/tnetv107x.h>
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d6933848abf..a0d4f6038b60 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1004,7 +1004,7 @@ static const struct da850_opp da850_opp_96 = {
 
 #define OPP(freq)               \
         {                               \
-                .index = (unsigned int) &da850_opp_##freq,      \
+                .driver_data = (unsigned int) &da850_opp_##freq,        \
                 .frequency = freq * 1000, \
         }
 
@@ -1016,7 +1016,7 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
         OPP(200),
         OPP(96),
         {
-                .index          = 0,
+                .driver_data            = 0,
                 .frequency      = CPUFREQ_TABLE_END,
         },
 };
@@ -1044,7 +1044,7 @@ static int da850_set_voltage(unsigned int index)
         if (!cvdd)
                 return -ENODEV;
 
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
 
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -1125,7 +1125,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         struct pll_data *pll = clk->pll_data;
         int ret;
 
-        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
         prediv = opp->prediv;
         mult = opp->mult;
         postdiv = opp->postdiv;
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 1ab3df423dac..a883043d0820 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/platform_data/davinci_asp.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/keyscan-davinci.h>
 #include <mach/hardware.h>
-#include <mach/edma.h>
 
 #include <media/davinci/vpfe_capture.h>
 #include <media/davinci/vpif_types.h>
@@ -77,32 +77,32 @@ void davinci_map_sysmod(void);
 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000
 
 /* DM355 function declarations */
-void __init dm355_init(void);
+void dm355_init(void);
 void dm355_init_spi0(unsigned chipselect_mask,
                 const struct spi_board_info *info, unsigned len);
-void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
+void dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata);
 int dm355_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM365 function declarations */
-void __init dm365_init(void);
-void __init dm365_init_asp(struct snd_platform_data *pdata);
-void __init dm365_init_vc(struct snd_platform_data *pdata);
-void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
-void __init dm365_init_rtc(void);
+void dm365_init(void);
+void dm365_init_asp(struct snd_platform_data *pdata);
+void dm365_init_vc(struct snd_platform_data *pdata);
+void dm365_init_ks(struct davinci_ks_platform_data *pdata);
+void dm365_init_rtc(void);
 void dm365_init_spi0(unsigned chipselect_mask,
                         const struct spi_board_info *info, unsigned len);
 int dm365_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM644x function declarations */
-void __init dm644x_init(void);
-void __init dm644x_init_asp(struct snd_platform_data *pdata);
-int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
+void dm644x_init(void);
+void dm644x_init_asp(struct snd_platform_data *pdata);
+int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
 
 /* DM646x function declarations */
-void __init dm646x_init(void);
-void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
-void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-int __init dm646x_init_edma(struct edma_rsv_info *rsv);
+void dm646x_init(void);
+void dm646x_init_mcasp0(struct snd_platform_data *pdata);
+void dm646x_init_mcasp1(struct snd_platform_data *pdata);
+int dm646x_init_edma(struct edma_rsv_info *rsv);
 void dm646x_video_init(void);
 void dm646x_setup_vpif(struct vpif_display_config *,
                        struct vpif_capture_config *);
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index bf572525175d..eb254fe861ac 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -105,27 +105,27 @@ struct platform_device da8xx_serial_device = {
         },
 };
 
-static const s8 da8xx_queue_tc_mapping[][2] = {
+static s8 da8xx_queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
         {1, 1},
         {-1, -1}
 };
 
-static const s8 da8xx_queue_priority_mapping[][2] = {
+static s8 da8xx_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
         {1, 7},
         {-1, -1}
 };
 
-static const s8 da850_queue_tc_mapping[][2] = {
+static s8 da850_queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
         {-1, -1}
 };
 
-static const s8 da850_queue_priority_mapping[][2] = {
+static s8 da850_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
         {-1, -1}
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index cfb194df18ed..128cb9ae80f4 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -18,10 +18,10 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk.h>
 #include <linux/slab.h>
+#include <linux/platform_data/edma.h>
 
 #include <mach/common.h>
 #include <mach/irqs.h>
-#include <mach/edma.h>
 #include <mach/tnetv107x.h>
 
 #include "clock.h"
@@ -58,14 +58,14 @@
 #define TNETV107X_DMACH_SDIO1_RX                28
 #define TNETV107X_DMACH_SDIO1_TX                29
 
-static const s8 edma_tc_mapping[][2] = {
+static s8 edma_tc_mapping[][2] = {
         /* event queue no       TC no   */
         {        0,              0      },
         {        1,              1      },
         {       -1,             -1      }
 };
 
-static const s8 edma_priority_mapping[][2] = {
+static s8 edma_priority_mapping[][2] = {
         /* event queue no       Prio    */
         {        0,              3      },
         {        1,              7      },
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index a7068a3aa9d3..90b83d00fe2b 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -19,9 +19,10 @@
 #include <mach/irqs.h>
 #include <mach/cputype.h>
 #include <mach/mux.h>
-#include <mach/edma.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <mach/time.h>
+#include <linux/platform_data/edma.h>
+
 
 #include "davinci.h"
 #include "clock.h"
@@ -34,6 +35,9 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
+#define DAVINCI_DMA_MMCRXEVT    26
+#define DAVINCI_DMA_MMCTXEVT    27
+
 void __iomem  *davinci_sysmod_base;
 
 void davinci_map_sysmod(void)
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index a11034a358f1..42ef53f62c6c 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -19,7 +19,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
@@ -28,6 +27,7 @@
 #include <mach/common.h>
 #include <linux/platform_data/spi-davinci.h>
 #include <mach/gpio-davinci.h>
+#include <linux/platform_data/edma.h>
 
 #include "davinci.h"
 #include "clock.h"
@@ -569,7 +569,7 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static const s8
+static s8
 queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
@@ -577,7 +577,7 @@ queue_tc_mapping[][2] = {
         {-1, -1},
 };
 
-static const s8
+static s8
 queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 40fa4fee9331..fa7af5eda52d 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,11 +18,11 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/spi/spi.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
 #include <mach/irqs.h>
@@ -826,7 +826,7 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 };
 
 /* Four Transfer Controllers on DM365 */
-static const s8
+static s8
 dm365_queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
@@ -836,7 +836,7 @@ dm365_queue_tc_mapping[][2] = {
         {-1, -1},
 };
 
-static const s8
+static s8
 dm365_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 7},
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 4d37d3e2a193..a49d18246fe9 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -12,11 +12,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -497,7 +497,7 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static const s8
+static s8
 queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
@@ -505,7 +505,7 @@ queue_tc_mapping[][2] = {
         {-1, -1},
 };
 
-static const s8
+static s8
 queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 3},
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index ac7b431c4c8e..d1259e80141b 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -13,11 +13,11 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/edma.h>
 
 #include <asm/mach/map.h>
 
 #include <mach/cputype.h>
-#include <mach/edma.h>
 #include <mach/irqs.h>
 #include <mach/psc.h>
 #include <mach/mux.h>
@@ -531,7 +531,7 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 
 /* Four Transfer Controllers on DM646x */
-static const s8
+static s8
 dm646x_queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
@@ -541,7 +541,7 @@ dm646x_queue_tc_mapping[][2] = {
         {-1, -1},
 };
 
-static const s8
+static s8
 dm646x_queue_priority_mapping[][2] = {
         /* {event queue no, Priority} */
         {0, 4},
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index d13d8dfa2b0d..827bbe9baed4 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -51,7 +51,7 @@
 #define CP_INTC_HOST_PRIO_VECTOR(n)     (0x1600 + (n << 2))
 #define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
 
-void __init cp_intc_init(void);
-int __init cp_intc_of_init(struct device_node *, struct device_node *);
+void cp_intc_init(void);
+int cp_intc_of_init(struct device_node *, struct device_node *);
 
 #endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 2e1c9eae0a58..3c797e2272f8 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -20,8 +20,8 @@
 #include <linux/videodev2.h>
 
 #include <mach/serial.h>
-#include <mach/edma.h>
 #include <mach/pm.h>
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/i2c-davinci.h>
 #include <linux/platform_data/mmc-davinci.h>
 #include <linux/platform_data/usb-davinci.h>
@@ -79,8 +79,8 @@ extern unsigned int da850_max_speed;
 #define DA8XX_SHARED_RAM_BASE   0x80000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
-void __init da830_init(void);
-void __init da850_init(void);
+void da830_init(void);
+void da850_init(void);
 
 int da830_register_edma(struct edma_rsv_info *rsv);
 int da850_register_edma(struct edma_rsv_info *rsv[2]);
@@ -94,17 +94,17 @@ int da8xx_register_uio_pruss(void);
 int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
 int da8xx_register_mmcsd0(struct davinci_mmc_config *config);
 int da850_register_mmcsd1(struct davinci_mmc_config *config);
-void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
+void da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(char *async_clk);
 int da8xx_register_cpuidle(void);
-void __iomem * __init da8xx_get_mem_ctlr(void);
+void __iomem *da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
-int __init da850_register_sata(unsigned long refclkpn);
-int __init da850_register_vpif(void);
-int __init da850_register_vpif_display
+int da850_register_sata(unsigned long refclkpn);
+int da850_register_vpif(void);
+int da850_register_vpif_display
                         (struct vpif_display_config *display_config);
-int __init da850_register_vpif_capture
+int da850_register_vpif_capture
                         (struct vpif_capture_config *capture_config);
 void da8xx_restart(char mode, const char *cmd);
 void da8xx_rproc_reserve_cma(void);
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
deleted file mode 100644
index 7e84c906ceff..000000000000
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- *  TI DAVINCI dma definitions
- *
- *  Copyright (C) 2006-2009 Texas Instruments.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-/*
- * This EDMA3 programming framework exposes two basic kinds of resource:
- *
- *  Channel     Triggers transfers, usually from a hardware event but
- *              also manually or by "chaining" from DMA completions.
- *              Each channel is coupled to a Parameter RAM (PaRAM) slot.
- *
- *  Slot        Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- *              "set"), source and destination addresses, a link to a
- *              next PaRAM slot (if any), options for the transfer, and
- *              instructions for updating those addresses.  There are
- *              more than twice as many slots as event channels.
- *
- * Each PaRAM set describes a sequence of transfers, either for one large
- * buffer or for several discontiguous smaller buffers.  An EDMA transfer
- * is driven only from a channel, which performs the transfers specified
- * in its PaRAM slot until there are no more transfers.  When that last
- * transfer completes, the "link" field may be used to reload the channel's
- * PaRAM slot with a new transfer descriptor.
- *
- * The EDMA Channel Controller (CC) maps requests from channels into physical
- * Transfer Controller (TC) requests when the channel triggers (by hardware
- * or software events, or by chaining).  The two physical DMA channels provided
- * by the TCs are thus shared by many logical channels.
- *
- * DaVinci hardware also has a "QDMA" mechanism which is not currently
- * supported through this interface.  (DSP firmware uses it though.)
- */
-
-#ifndef EDMA_H_
-#define EDMA_H_
-
-/* PaRAM slots are laid out like this */
-struct edmacc_param {
-        unsigned int opt;
-        unsigned int src;
-        unsigned int a_b_cnt;
-        unsigned int dst;
-        unsigned int src_dst_bidx;
-        unsigned int link_bcntrld;
-        unsigned int src_dst_cidx;
-        unsigned int ccnt;
-};
-
-#define CCINT0_INTERRUPT     16
-#define CCERRINT_INTERRUPT   17
-#define TCERRINT0_INTERRUPT   18
-#define TCERRINT1_INTERRUPT   19
-
-/* fields in edmacc_param.opt */
-#define SAM             BIT(0)
-#define DAM             BIT(1)
-#define SYNCDIM         BIT(2)
-#define STATIC          BIT(3)
-#define EDMA_FWID       (0x07 << 8)
-#define TCCMODE         BIT(11)
-#define EDMA_TCC(t)     ((t) << 12)
-#define TCINTEN         BIT(20)
-#define ITCINTEN        BIT(21)
-#define TCCHEN          BIT(22)
-#define ITCCHEN         BIT(23)
-
-#define TRWORD (0x7<<2)
-#define PAENTRY (0x1ff<<5)
-
-/* Drivers should avoid using these symbolic names for dm644x
- * channels, and use platform_device IORESOURCE_DMA resources
- * instead.  (Other DaVinci chips have different peripherals
- * and thus have different DMA channel mappings.)
- */
-#define DAVINCI_DMA_MCBSP_TX              2
-#define DAVINCI_DMA_MCBSP_RX              3
-#define DAVINCI_DMA_VPSS_HIST             4
-#define DAVINCI_DMA_VPSS_H3A              5
-#define DAVINCI_DMA_VPSS_PRVU             6
-#define DAVINCI_DMA_VPSS_RSZ              7
-#define DAVINCI_DMA_IMCOP_IMXINT          8
-#define DAVINCI_DMA_IMCOP_VLCDINT         9
-#define DAVINCI_DMA_IMCO_PASQINT         10
-#define DAVINCI_DMA_IMCOP_DSQINT         11
-#define DAVINCI_DMA_SPI_SPIX             16
-#define DAVINCI_DMA_SPI_SPIR             17
-#define DAVINCI_DMA_UART0_URXEVT0        18
-#define DAVINCI_DMA_UART0_UTXEVT0        19
-#define DAVINCI_DMA_UART1_URXEVT1        20
-#define DAVINCI_DMA_UART1_UTXEVT1        21
-#define DAVINCI_DMA_UART2_URXEVT2        22
-#define DAVINCI_DMA_UART2_UTXEVT2        23
-#define DAVINCI_DMA_MEMSTK_MSEVT         24
-#define DAVINCI_DMA_MMCRXEVT             26
-#define DAVINCI_DMA_MMCTXEVT             27
-#define DAVINCI_DMA_I2C_ICREVT           28
-#define DAVINCI_DMA_I2C_ICXEVT           29
-#define DAVINCI_DMA_GPIO_GPINT0          32
-#define DAVINCI_DMA_GPIO_GPINT1          33
-#define DAVINCI_DMA_GPIO_GPINT2          34
-#define DAVINCI_DMA_GPIO_GPINT3          35
-#define DAVINCI_DMA_GPIO_GPINT4          36
-#define DAVINCI_DMA_GPIO_GPINT5          37
-#define DAVINCI_DMA_GPIO_GPINT6          38
-#define DAVINCI_DMA_GPIO_GPINT7          39
-#define DAVINCI_DMA_GPIO_GPBNKINT0       40
-#define DAVINCI_DMA_GPIO_GPBNKINT1       41
-#define DAVINCI_DMA_GPIO_GPBNKINT2       42
-#define DAVINCI_DMA_GPIO_GPBNKINT3       43
-#define DAVINCI_DMA_GPIO_GPBNKINT4       44
-#define DAVINCI_DMA_TIMER0_TINT0         48
-#define DAVINCI_DMA_TIMER1_TINT1         49
-#define DAVINCI_DMA_TIMER2_TINT2         50
-#define DAVINCI_DMA_TIMER3_TINT3         51
-#define DAVINCI_DMA_PWM0                 52
-#define DAVINCI_DMA_PWM1                 53
-#define DAVINCI_DMA_PWM2                 54
-
-/* DA830 specific EDMA3 information */
-#define EDMA_DA830_NUM_DMACH            32
-#define EDMA_DA830_NUM_TCC              32
-#define EDMA_DA830_NUM_PARAMENTRY       128
-#define EDMA_DA830_NUM_EVQUE            2
-#define EDMA_DA830_NUM_TC               2
-#define EDMA_DA830_CHMAP_EXIST          0
-#define EDMA_DA830_NUM_REGIONS          4
-#define DA830_DMACH2EVENT_MAP0          0x000FC03Fu
-#define DA830_DMACH2EVENT_MAP1          0x00000000u
-#define DA830_EDMA_ARM_OWN              0x30FFCCFFu
-
-/*ch_status paramater of callback function possible values*/
-#define DMA_COMPLETE 1
-#define DMA_CC_ERROR 2
-#define DMA_TC1_ERROR 3
-#define DMA_TC2_ERROR 4
-
-enum address_mode {
-        INCR = 0,
-        FIFO = 1
-};
-
-enum fifo_width {
-        W8BIT = 0,
-        W16BIT = 1,
-        W32BIT = 2,
-        W64BIT = 3,
-        W128BIT = 4,
-        W256BIT = 5
-};
-
-enum dma_event_q {
-        EVENTQ_0 = 0,
-        EVENTQ_1 = 1,
-        EVENTQ_2 = 2,
-        EVENTQ_3 = 3,
-        EVENTQ_DEFAULT = -1
-};
-
-enum sync_dimension {
-        ASYNC = 0,
-        ABSYNC = 1
-};
-
-#define EDMA_CTLR_CHAN(ctlr, chan)      (((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i)                    ((i) >> 16)
-#define EDMA_CHAN_SLOT(i)               ((i) & 0xffff)
-
-#define EDMA_CHANNEL_ANY                -1      /* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY                   -1      /* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY             1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
-#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
-
-#define EDMA_MAX_CC               2
-
-/* alloc/free DMA channels and their dedicated parameter RAM slots */
-int edma_alloc_channel(int channel,
-        void (*callback)(unsigned channel, u16 ch_status, void *data),
-        void *data, enum dma_event_q);
-void edma_free_channel(unsigned channel);
-
-/* alloc/free parameter RAM slots */
-int edma_alloc_slot(unsigned ctlr, int slot);
-void edma_free_slot(unsigned slot);
-
-/* alloc/free a set of contiguous parameter RAM slots */
-int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count);
-int edma_free_cont_slots(unsigned slot, int count);
-
-/* calls that operate on part of a parameter RAM slot */
-void edma_set_src(unsigned slot, dma_addr_t src_port,
-                                enum address_mode mode, enum fifo_width);
-void edma_set_dest(unsigned slot, dma_addr_t dest_port,
-                                 enum address_mode mode, enum fifo_width);
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst);
-void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx);
-void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx);
-void edma_set_transfer_params(unsigned slot, u16 acnt, u16 bcnt, u16 ccnt,
-                u16 bcnt_rld, enum sync_dimension sync_mode);
-void edma_link(unsigned from, unsigned to);
-void edma_unlink(unsigned from);
-
-/* calls that operate on an entire parameter RAM slot */
-void edma_write_slot(unsigned slot, const struct edmacc_param *params);
-void edma_read_slot(unsigned slot, struct edmacc_param *params);
-
-/* channel control operations */
-int edma_start(unsigned channel);
-void edma_stop(unsigned channel);
-void edma_clean_channel(unsigned channel);
-void edma_clear_event(unsigned channel);
-void edma_pause(unsigned channel);
-void edma_resume(unsigned channel);
-
-struct edma_rsv_info {
-
-        const s16       (*rsv_chans)[2];
-        const s16       (*rsv_slots)[2];
-};
-
-/* platform_data for EDMA driver */
-struct edma_soc_info {
-
-        /* how many dma resources of each type */
-        unsigned        n_channel;
-        unsigned        n_region;
-        unsigned        n_slot;
-        unsigned        n_tc;
-        unsigned        n_cc;
-        /*
-         * Default queue is expected to be a low-priority queue.
-         * This way, long transfers on the default queue started
-         * by the codec engine will not cause audio defects.
-         */
-        enum dma_event_q        default_queue;
-
-        /* Resource reservation for other cores */
-        struct edma_rsv_info    *rsv;
-
-        const s8        (*queue_tc_mapping)[2];
-        const s8        (*queue_priority_mapping)[2];
-};
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 1656a02e3eda..366e975effa8 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -51,9 +51,9 @@ struct tnetv107x_device_info {
 extern struct platform_device tnetv107x_wdt_device;
 extern struct platform_device tnetv107x_serial_device;
 
-extern void __init tnetv107x_init(void);
-extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
-extern void __init tnetv107x_irq_init(void);
+extern void tnetv107x_init(void);
+extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
+extern void tnetv107x_irq_init(void);
 void tnetv107x_restart(char mode, const char *cmd);
 
 #endif
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 36469d813951..dff7b2fd4e20 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -22,8 +22,7 @@ config MACH_CM_A510
 
 config MACH_DOVE_DT
         bool "Marvell Dove Flattened Device Tree"
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_GATING
+        select DOVE_CLK
         select REGULATOR
         select REGULATOR_FIXED_VOLTAGE
         select USE_OF
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index 0b142803b2e1..f3755ac81148 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,7 +10,6 @@
 
 #include <linux/init.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/usb-ehci-orion.h>
@@ -49,7 +48,7 @@ static void __init dove_legacy_clk_init(void)
 
 static void __init dove_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
         dove_legacy_clk_init();
 }
 
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e2b5da031f96..2a9443d04d92 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of.h>
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index b13cc74114db..8a53f346cdb3 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void)
         iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
 }
 
-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size,
+static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
                                             unsigned int flags, void *caller)
 {
         return (void __iomem *)cookie;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index ff18fc2ea46f..f5f65b58181e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -14,9 +14,11 @@ menu "SAMSUNG EXYNOS SoCs Support"
 config ARCH_EXYNOS4
         bool "SAMSUNG EXYNOS4"
         default y
+        select GIC_NON_BANKED
         select HAVE_ARM_SCU if SMP
         select HAVE_SMP
         select MIGHT_HAVE_CACHE_L2X0
+        select PINCTRL
         help
           Samsung EXYNOS4 SoCs based systems
 
@@ -24,6 +26,7 @@ config ARCH_EXYNOS5
         bool "SAMSUNG EXYNOS5"
         select HAVE_ARM_SCU if SMP
         select HAVE_SMP
+        select PINCTRL
         help
           Samsung EXYNOS5 (Cortex-A15) SoC based systems
 
@@ -34,6 +37,7 @@ config CPU_EXYNOS4210
         default y
         depends on ARCH_EXYNOS4
         select ARM_CPU_SUSPEND if PM
+        select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS
         select S5P_PM if PM
         select S5P_SLEEP if PM
@@ -45,6 +49,7 @@ config SOC_EXYNOS4212
         bool "SAMSUNG EXYNOS4212"
         default y
         depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
         select S5P_PM if PM
         select S5P_SLEEP if PM
         select SAMSUNG_DMADEV
@@ -55,6 +60,7 @@ config SOC_EXYNOS4412
         bool "SAMSUNG EXYNOS4412"
         default y
         depends on ARCH_EXYNOS4
+        select PINCTRL_EXYNOS
         select SAMSUNG_DMADEV
         help
           Enable EXYNOS4412 SoC support
@@ -63,6 +69,7 @@ config SOC_EXYNOS5250
         bool "SAMSUNG EXYNOS5250"
         default y
         depends on ARCH_EXYNOS5
+        select PINCTRL_EXYNOS
         select PM_GENERIC_DOMAINS if PM
         select S5P_PM if PM
         select S5P_SLEEP if PM
@@ -71,352 +78,42 @@ config SOC_EXYNOS5250
         help
           Enable EXYNOS5250 SoC support
 
+config SOC_EXYNOS5420
+        bool "SAMSUNG EXYNOS5420"
+        default y
+        depends on ARCH_EXYNOS5
+        select PM_GENERIC_DOMAINS if PM
+        select S5P_PM if PM
+        select S5P_SLEEP if PM
+        help
+          Enable EXYNOS5420 SoC support
+
 config SOC_EXYNOS5440
         bool "SAMSUNG EXYNOS5440"
         default y
         depends on ARCH_EXYNOS5
         select ARCH_HAS_OPP
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select AUTO_ZRELADDR
-        select PINCTRL
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
         select PINCTRL_EXYNOS5440
         select PM_OPP
         help
           Enable EXYNOS5440 SoC support
 
-config EXYNOS_ATAGS
-        bool "ATAGS based boot for EXYNOS (deprecated)"
-        depends on !ARCH_MULTIPLATFORM
-        depends on ATAGS
-        default y
-        help
-          The EXYNOS platform is moving towards being completely probed
-          through device tree. This enables support for board files using
-          the traditional ATAGS boot format.
-          Note that this option is not available for multiplatform builds.
-
-if EXYNOS_ATAGS
-
-config EXYNOS_DEV_DMA
-        bool
-        help
-          Compile in amba device definitions for DMA controller
-
-config EXYNOS4_DEV_AHCI
-        bool
-        help
-          Compile in platform device definitions for AHCI
-
-config EXYNOS4_SETUP_FIMD0
-        bool
-        help
-          Common setup code for FIMD0.
-
-config EXYNOS4_DEV_USB_OHCI
-        bool
-        help
-          Compile in platform device definition for USB OHCI
-
-config EXYNOS4_SETUP_I2C1
-        bool
-        help
-          Common setup code for i2c bus 1.
-
-config EXYNOS4_SETUP_I2C2
-        bool
-        help
-          Common setup code for i2c bus 2.
-
-config EXYNOS4_SETUP_I2C3
-        bool
-        help
-          Common setup code for i2c bus 3.
-
-config EXYNOS4_SETUP_I2C4
-        bool
-        help
-          Common setup code for i2c bus 4.
-
-config EXYNOS4_SETUP_I2C5
-        bool
-        help
-          Common setup code for i2c bus 5.
-
-config EXYNOS4_SETUP_I2C6
-        bool
-        help
-          Common setup code for i2c bus 6.
-
-config EXYNOS4_SETUP_I2C7
-        bool
-        help
-          Common setup code for i2c bus 7.
-
-config EXYNOS4_SETUP_KEYPAD
-        bool
-        help
-          Common setup code for keypad.
-
-config EXYNOS4_SETUP_SDHCI
-        bool
-        select EXYNOS4_SETUP_SDHCI_GPIO
-        help
-          Internal helper functions for EXYNOS4 based SDHCI systems.
-
-config EXYNOS4_SETUP_SDHCI_GPIO
-        bool
-        help
-          Common setup code for SDHCI gpio.
-
-config EXYNOS4_SETUP_FIMC
-        bool
-        help
-          Common setup code for the camera interfaces.
-
-config EXYNOS4_SETUP_USB_PHY
-        bool
-        help
-          Common setup code for USB PHY controller
-
-config EXYNOS_SETUP_SPI
-        bool
-        help
-          Common setup code for SPI GPIO configurations.
-
-# machine support
-
-if ARCH_EXYNOS4
-
-comment "EXYNOS4210 Boards"
-
-config MACH_SMDKC210
-        bool "SMDKC210"
-        select MACH_SMDKV310
-        help
-          Machine support for Samsung SMDKC210
-
-config MACH_SMDKV310
-        bool "SMDKV310"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC1
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung SMDKV310
-
-config MACH_ARMLEX4210
-        bool "ARMLEX4210"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_AHCI
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_RTC
-        select S3C_DEV_WDT
-        help
-          Machine support for Samsung ARMLEX4210 based on EXYNOS4210
-
-config MACH_UNIVERSAL_C210
-        bool "Mobile UNIVERSAL_C210 Board"
-        select CLKSRC_MMIO
-        select CLKSRC_SAMSUNG_PWM
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_USB_HSOTG
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_ONENAND
-        select S5P_DEV_TV
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        help
-          Machine support for Samsung Mobile Universal S5PC210 Reference
-          Board.
-
-config MACH_NURI
-        bool "Mobile NURI Board"
-        select CPU_EXYNOS4210
-        select EXYNOS4_SETUP_FIMC
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C5
-        select EXYNOS4_SETUP_I2C6
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C5
-        select S3C_DEV_I2C6
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_CSIS0
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_USB_EHCI
-        select S5P_GPIO_INT
-        select S5P_SETUP_MIPIPHY
-        select SAMSUNG_DEV_ADC
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for Samsung Mobile NURI Board.
-
-config MACH_ORIGEN
-        bool "ORIGEN"
-        select CPU_EXYNOS4210
-        select EXYNOS4_DEV_USB_OHCI
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_G2D
-        select S5P_DEV_I2C_HDMIPHY
-        select S5P_DEV_JPEG
-        select S5P_DEV_MFC
-        select S5P_DEV_TV
-        select S5P_DEV_USB_EHCI
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_PWM
-        help
-          Machine support for ORIGEN based on Samsung EXYNOS4210
-
-comment "EXYNOS4212 Boards"
-
-config MACH_SMDK4212
-        bool "SMDK4212"
-        select EXYNOS4_SETUP_FIMD0
-        select EXYNOS4_SETUP_I2C1
-        select EXYNOS4_SETUP_I2C3
-        select EXYNOS4_SETUP_I2C7
-        select EXYNOS4_SETUP_KEYPAD
-        select EXYNOS4_SETUP_SDHCI
-        select EXYNOS4_SETUP_USB_PHY
-        select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_SYSMMU
-        select S3C24XX_PWM
-        select S3C_DEV_HSMMC2
-        select S3C_DEV_HSMMC3
-        select S3C_DEV_I2C1
-        select S3C_DEV_I2C3
-        select S3C_DEV_I2C7
-        select S3C_DEV_RTC
-        select S3C_DEV_USB_HSOTG
-        select S3C_DEV_WDT
-        select S5P_DEV_FIMC0
-        select S5P_DEV_FIMC1
-        select S5P_DEV_FIMC2
-        select S5P_DEV_FIMC3
-        select S5P_DEV_FIMD0
-        select S5P_DEV_MFC
-        select SAMSUNG_DEV_BACKLIGHT
-        select SAMSUNG_DEV_KEYPAD
-        select SAMSUNG_DEV_PWM
-        select SOC_EXYNOS4212
-        help
-          Machine support for Samsung SMDK4212
-
-comment "EXYNOS4412 Boards"
-
-config MACH_SMDK4412
-        bool "SMDK4412"
-        select MACH_SMDK4212
-        select SOC_EXYNOS4412
-        help
-          Machine support for Samsung SMDK4412
-endif
-
-endif
-
 comment "Flattened Device Tree based board for EXYNOS SoCs"
 
 config MACH_EXYNOS4_DT
         bool "Samsung Exynos4 Machine using device tree"
+        default y
         depends on ARCH_EXYNOS4
         select ARM_AMBA
         select CLKSRC_OF
         select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
         select CPU_EXYNOS4210
         select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-        select PINCTRL
-        select PINCTRL_EXYNOS
         select S5P_DEV_MFC
-        select USE_OF
         help
           Machine support for Samsung Exynos4 machine with device tree enabled.
           Select this if a fdt blob is available for the Exynos4 SoC based board.
@@ -429,28 +126,11 @@ config MACH_EXYNOS5_DT
         depends on ARCH_EXYNOS5
         select ARM_AMBA
         select CLKSRC_OF
-        select USE_OF
+        select USB_ARCH_HAS_XHCI
         help
           Machine support for Samsung EXYNOS5 machine with device tree enabled.
           Select this if a fdt blob is available for the EXYNOS5 SoC based board.
 
-if ARCH_EXYNOS4
-
-comment "Configuration for HSMMC 8-bit bus width"
-
-config EXYNOS4_SDHCI_CH0_8BIT
-        bool "Channel 0 with 8-bit bus"
-        help
-          Support HSMMC Channel 0 8-bit bus.
-          If selected, Channel 1 is disabled.
-
-config EXYNOS4_SDHCI_CH2_8BIT
-        bool "Channel 2 with 8-bit bus"
-        help
-          Support HSMMC Channel 2 8-bit bus.
-          If selected, Channel 3 is disabled.
-endif
-
 endmenu
 
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index b09b027178f3..e970a7a4e278 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -32,38 +32,5 @@ AFLAGS_exynos-smc.o		:=-Wa,-march=armv7-a$(plus_sec)
 
 # machine support
 
-obj-$(CONFIG_MACH_SMDKC210)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_SMDKV310)             += mach-smdkv310.o
-obj-$(CONFIG_MACH_ARMLEX4210)           += mach-armlex4210.o
-obj-$(CONFIG_MACH_UNIVERSAL_C210)       += mach-universal_c210.o
-obj-$(CONFIG_MACH_NURI)                 += mach-nuri.o
-obj-$(CONFIG_MACH_ORIGEN)               += mach-origen.o
-
-obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
-obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
-
 obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
 obj-$(CONFIG_MACH_EXYNOS5_DT)           += mach-exynos5-dt.o
-
-# device support
-
-obj-y                                   += dev-uart.o
-obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
-obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
-obj-$(CONFIG_EXYNOS_DEV_DMA)            += dma.o
-obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
-
-obj-$(CONFIG_ARCH_EXYNOS)               += setup-i2c0.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
-obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C2)        += setup-i2c2.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C3)        += setup-i2c3.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C4)        += setup-i2c4.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C5)        += setup-i2c5.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
-obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
-obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
-obj-$(CONFIG_EXYNOS_SETUP_SPI)          += setup-spi.o
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index f7e504b7874d..2c655db4b78e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -40,20 +40,9 @@
 
 #include <mach/regs-irq.h>
 #include <mach/regs-pmu.h>
-#include <mach/regs-gpio.h>
-#include <mach/irqs.h>
 
 #include <plat/cpu.h>
-#include <plat/devs.h>
 #include <plat/pm.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/adc-core.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/tv-core.h>
-#include <plat/spi-core.h>
 #include <plat/regs-serial.h>
 
 #include "common.h"
@@ -64,36 +53,31 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static const char name_exynos4212[] = "EXYNOS4212";
 static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5420[] = "EXYNOS5420";
 static const char name_exynos5440[] = "EXYNOS5440";
 
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
-static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 static int exynos_init(void);
 
-unsigned long xxti_f = 0, xusbxti_f = 0;
-
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = EXYNOS4210_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4210,
         }, {
                 .idcode         = EXYNOS4212_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4212,
         }, {
                 .idcode         = EXYNOS4412_CPU_ID,
                 .idmask         = EXYNOS4_CPU_MASK,
                 .map_io         = exynos4_map_io,
-                .init_uarts     = exynos4_init_uarts,
                 .init           = exynos_init,
                 .name           = name_exynos4412,
         }, {
@@ -103,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = exynos_init,
                 .name           = name_exynos5250,
         }, {
+                .idcode         = EXYNOS5420_SOC_ID,
+                .idmask         = EXYNOS5_SOC_MASK,
+                .map_io         = exynos5_map_io,
+                .init           = exynos_init,
+                .name           = name_exynos5420,
+        }, {
                 .idcode         = EXYNOS5440_SOC_ID,
                 .idmask         = EXYNOS5_SOC_MASK,
                 .map_io         = exynos5440_map_io,
@@ -113,15 +103,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 
 /* Initial IO mappings */
 
-static struct map_desc exynos_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CHIPID,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_CHIPID),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-
 static struct map_desc exynos4_iodesc[] __initdata = {
         {
                 .virtual        = (unsigned long)S3C_VA_SYS,
@@ -304,13 +285,6 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
         },
 };
 
-static struct samsung_pwm_variant exynos4_pwm_variant = {
-        .bits           = 32,
-        .div_base       = 0,
-        .has_tint_cstat = true,
-        .tclk_mask      = 0,
-};
-
 void exynos4_restart(char mode, const char *cmd)
 {
         __raw_writel(0x1, S5P_SWRESET);
@@ -322,10 +296,10 @@ void exynos5_restart(char mode, const char *cmd)
         u32 val;
         void __iomem *addr;
 
-        if (of_machine_is_compatible("samsung,exynos5250")) {
-                val = 0x1;
-                addr = EXYNOS_SWRESET;
-        } else if (of_machine_is_compatible("samsung,exynos5440")) {
+        val = 0x1;
+        addr = EXYNOS_SWRESET;
+
+        if (of_machine_is_compatible("samsung,exynos5440")) {
                 u32 status;
                 np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
 
@@ -336,9 +310,6 @@ void exynos5_restart(char mode, const char *cmd)
                 val = __raw_readl(addr);
 
                 val = (val & 0xffff0000) | (status & 0xffff);
-        } else {
-                pr_err("%s: cannot support non-DT\n", __func__);
-                return;
         }
 
         __raw_writel(val, addr);
@@ -353,8 +324,7 @@ void __init exynos_init_late(void)
         exynos_pm_late_initcall();
 }
 
-#ifdef CONFIG_OF
-int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
+static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
                                         int depth, void *data)
 {
         struct map_desc iodesc;
@@ -376,7 +346,6 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
         iotable_init(&iodesc, 1);
         return 1;
 }
-#endif
 
 /*
  * exynos_map_io
@@ -384,19 +353,11 @@ int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
  * register the standard cpu IO areas
  */
 
-void __init exynos_init_io(struct map_desc *mach_desc, int size)
+void __init exynos_init_io(void)
 {
         debug_ll_io_init();
 
-#ifdef CONFIG_OF
-        if (initial_boot_params)
-                of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
-        else
-#endif
-                iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
-
-        if (mach_desc)
-                iotable_init(mach_desc, size);
+        of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 
         /* detect cpu id and rev. */
         s5p_init_cpu(S5P_VA_CHIPID);
@@ -417,34 +378,6 @@ static void __init exynos4_map_io(void)
                 iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
         if (soc_is_exynos4212() || soc_is_exynos4412())
                 iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-
-        /* initialize device information early */
-        exynos4_default_sdhci0();
-        exynos4_default_sdhci1();
-        exynos4_default_sdhci2();
-        exynos4_default_sdhci3();
-
-        s3c_adc_setname("samsung-adc-v3");
-
-        s3c_fimc_setname(0, "exynos4-fimc");
-        s3c_fimc_setname(1, "exynos4-fimc");
-        s3c_fimc_setname(2, "exynos4-fimc");
-        s3c_fimc_setname(3, "exynos4-fimc");
-
-        s3c_sdhci_setname(0, "exynos4-sdhci");
-        s3c_sdhci_setname(1, "exynos4-sdhci");
-        s3c_sdhci_setname(2, "exynos4-sdhci");
-        s3c_sdhci_setname(3, "exynos4-sdhci");
-
-        /* The I2C bus controllers are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-
-        s5p_fb_setname(0, "exynos4-fb");
-        s5p_hdmi_setname("exynos4-hdmi");
-
-        s3c64xx_spi_setname("exynos4210-spi");
 }
 
 static void __init exynos5_map_io(void)
@@ -460,81 +393,10 @@ static void __init exynos5440_map_io(void)
         iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
 }
 
-void __init exynos_set_timer_source(u8 channels)
-{
-        exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
-        exynos4_pwm_variant.output_mask &= ~channels;
-}
-
 void __init exynos_init_time(void)
 {
-        unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
-                EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
-                EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
-                EXYNOS4_IRQ_TIMER4_VIC,
-        };
-
-        if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
-                of_clk_init(NULL);
-                clocksource_of_init();
-#endif
-        } else {
-                /* todo: remove after migrating legacy E4 platforms to dt */
-#ifdef CONFIG_ARCH_EXYNOS4
-                exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
-                exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
-#endif
-#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
-                if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-                        samsung_pwm_clocksource_init(S3C_VA_TIMER,
-                                        timer_irqs, &exynos4_pwm_variant);
-                else
-#endif
-                        mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
-                                        EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
-        }
-}
-
-static unsigned int max_combiner_nr(void)
-{
-        if (soc_is_exynos5250())
-                return EXYNOS5_MAX_COMBINER_NR;
-        else if (soc_is_exynos4412())
-                return EXYNOS4412_MAX_COMBINER_NR;
-        else if (soc_is_exynos4212())
-                return EXYNOS4212_MAX_COMBINER_NR;
-        else
-                return EXYNOS4210_MAX_COMBINER_NR;
-}
-
-
-void __init exynos4_init_irq(void)
-{
-        unsigned int gic_bank_offset;
-
-        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-
-        if (!of_have_populated_dt())
-                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
-#ifdef CONFIG_OF
-        else
-                irqchip_init();
-#endif
-
-        if (!of_have_populated_dt())
-                combiner_init(S5P_VA_COMBINER_BASE, NULL,
-                              max_combiner_nr(), COMBINER_IRQ(0, 0));
-
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
-}
-
-void __init exynos5_init_irq(void)
-{
-#ifdef CONFIG_OF
-        irqchip_init();
-#endif
-        gic_arch_extn.irq_set_wake = s3c_irq_wake;
+        of_clk_init(NULL);
+        clocksource_of_init();
 }
 
 struct bus_type exynos_subsys = {
@@ -552,59 +414,19 @@ static int __init exynos_core_init(void)
 }
 core_initcall(exynos_core_init);
 
-#ifdef CONFIG_CACHE_L2X0
 static int __init exynos4_l2x0_cache_init(void)
 {
         int ret;
 
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                return 0;
-
         ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
-        if (!ret) {
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                return 0;
-        }
+        if (ret)
+                return ret;
 
-        if (!(__raw_readl(S5P_VA_L2CC + L2X0_CTRL) & 0x1)) {
-                l2x0_saved_regs.phy_base = EXYNOS4_PA_L2CC;
-                /* TAG, Data Latency Control: 2 cycles */
-                l2x0_saved_regs.tag_latency = 0x110;
-
-                if (soc_is_exynos4212() || soc_is_exynos4412())
-                        l2x0_saved_regs.data_latency = 0x120;
-                else
-                        l2x0_saved_regs.data_latency = 0x110;
-
-                l2x0_saved_regs.prefetch_ctrl = 0x30000007;
-                l2x0_saved_regs.pwr_ctrl =
-                        (L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN);
-
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-
-                __raw_writel(l2x0_saved_regs.tag_latency,
-                                S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-                __raw_writel(l2x0_saved_regs.data_latency,
-                                S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-
-                /* L2X0 Prefetch Control */
-                __raw_writel(l2x0_saved_regs.prefetch_ctrl,
-                                S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
-
-                /* L2X0 Power Control */
-                __raw_writel(l2x0_saved_regs.pwr_ctrl,
-                                S5P_VA_L2CC + L2X0_POWER_CTRL);
-
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-                clean_dcache_area(&l2x0_saved_regs, sizeof(struct l2x0_regs));
-        }
-
-        l2x0_init(S5P_VA_L2CC, L2_AUX_VAL, L2_AUX_MASK);
+        l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
+        clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
         return 0;
 }
 early_initcall(exynos4_l2x0_cache_init);
-#endif
 
 static int __init exynos_init(void)
 {
@@ -612,350 +434,3 @@ static int __init exynos_init(void)
 
         return device_register(&exynos4_dev);
 }
-
-/* uart registration process */
-
-static void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
-                tcfg->has_fracval = 1;
-
-        s3c24xx_init_uartdevs("exynos4210-uart", exynos4_uart_resources, cfg, no);
-}
-
-static void __iomem *exynos_eint_base;
-
-static DEFINE_SPINLOCK(eint_lock);
-
-static unsigned int eint0_15_data[16];
-
-static inline int exynos4_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS4_GPX0(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX1(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX2(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS4_GPX3(irq);
-
-        return -EINVAL;
-}
-
-static inline int exynos5_irq_to_gpio(unsigned int irq)
-{
-        if (irq < IRQ_EINT(0))
-                return -EINVAL;
-
-        irq -= IRQ_EINT(0);
-        if (irq < 8)
-                return EXYNOS5_GPX0(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX1(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX2(irq);
-
-        irq -= 8;
-        if (irq < 8)
-                return EXYNOS5_GPX3(irq);
-
-        return -EINVAL;
-}
-
-static unsigned int exynos4_eint0_15_src_int[16] = {
-        EXYNOS4_IRQ_EINT0,
-        EXYNOS4_IRQ_EINT1,
-        EXYNOS4_IRQ_EINT2,
-        EXYNOS4_IRQ_EINT3,
-        EXYNOS4_IRQ_EINT4,
-        EXYNOS4_IRQ_EINT5,
-        EXYNOS4_IRQ_EINT6,
-        EXYNOS4_IRQ_EINT7,
-        EXYNOS4_IRQ_EINT8,
-        EXYNOS4_IRQ_EINT9,
-        EXYNOS4_IRQ_EINT10,
-        EXYNOS4_IRQ_EINT11,
-        EXYNOS4_IRQ_EINT12,
-        EXYNOS4_IRQ_EINT13,
-        EXYNOS4_IRQ_EINT14,
-        EXYNOS4_IRQ_EINT15,
-};
-
-static unsigned int exynos5_eint0_15_src_int[16] = {
-        EXYNOS5_IRQ_EINT0,
-        EXYNOS5_IRQ_EINT1,
-        EXYNOS5_IRQ_EINT2,
-        EXYNOS5_IRQ_EINT3,
-        EXYNOS5_IRQ_EINT4,
-        EXYNOS5_IRQ_EINT5,
-        EXYNOS5_IRQ_EINT6,
-        EXYNOS5_IRQ_EINT7,
-        EXYNOS5_IRQ_EINT8,
-        EXYNOS5_IRQ_EINT9,
-        EXYNOS5_IRQ_EINT10,
-        EXYNOS5_IRQ_EINT11,
-        EXYNOS5_IRQ_EINT12,
-        EXYNOS5_IRQ_EINT13,
-        EXYNOS5_IRQ_EINT14,
-        EXYNOS5_IRQ_EINT15,
-};
-static inline void exynos_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask |= EINT_OFFSET_BIT(data->irq);
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-
-static void exynos_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-
-        spin_lock(&eint_lock);
-        mask = __raw_readl(EINT_MASK(exynos_eint_base, data->irq));
-        mask &= ~(EINT_OFFSET_BIT(data->irq));
-        __raw_writel(mask, EINT_MASK(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-}
-
-static inline void exynos_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel(EINT_OFFSET_BIT(data->irq),
-                     EINT_PEND(exynos_eint_base, data->irq));
-}
-
-static void exynos_irq_eint_maskack(struct irq_data *data)
-{
-        exynos_irq_eint_mask(data);
-        exynos_irq_eint_ack(data);
-}
-
-static int exynos_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = EINT_OFFSET(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-
-        shift = (offs & 0x7) * 4;
-        mask = 0x7 << shift;
-
-        spin_lock(&eint_lock);
-        ctrl = __raw_readl(EINT_CON(exynos_eint_base, data->irq));
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, EINT_CON(exynos_eint_base, data->irq));
-        spin_unlock(&eint_lock);
-
-        if (soc_is_exynos5250())
-                s3c_gpio_cfgpin(exynos5_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-        else
-                s3c_gpio_cfgpin(exynos4_irq_to_gpio(data->irq), S3C_GPIO_SFN(0xf));
-
-        return 0;
-}
-
-static struct irq_chip exynos_irq_eint = {
-        .name           = "exynos-eint",
-        .irq_mask       = exynos_irq_eint_mask,
-        .irq_unmask     = exynos_irq_eint_unmask,
-        .irq_mask_ack   = exynos_irq_eint_maskack,
-        .irq_ack        = exynos_irq_eint_ack,
-        .irq_set_type   = exynos_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-
-/*
- * exynos4_irq_demux_eint
- *
- * This function demuxes the IRQ from from EINTs 16 to 31.
- * It is designed to be inlined into the specific handler
- * s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void exynos_irq_demux_eint(unsigned int start)
-{
-        unsigned int irq;
-
-        u32 status = __raw_readl(EINT_PEND(exynos_eint_base, start));
-        u32 mask = __raw_readl(EINT_MASK(exynos_eint_base, start));
-
-        status &= ~mask;
-        status &= 0xff;
-
-        while (status) {
-                irq = fls(status) - 1;
-                generic_handle_irq(irq + start);
-                status &= ~(1 << irq);
-        }
-}
-
-static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        exynos_irq_demux_eint(IRQ_EINT(16));
-        exynos_irq_demux_eint(IRQ_EINT(24));
-        chained_irq_exit(chip, desc);
-}
-
-static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
-{
-        u32 *irq_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-
-        chained_irq_enter(chip, desc);
-        generic_handle_irq(*irq_data);
-        chained_irq_exit(chip, desc);
-}
-
-static int __init exynos_init_irq_eint(void)
-{
-        int irq;
-
-#ifdef CONFIG_PINCTRL_SAMSUNG
-        /*
-         * The Samsung pinctrl driver provides an integrated gpio/pinmux/pinconf
-         * functionality along with support for external gpio and wakeup
-         * interrupts. If the samsung pinctrl driver is enabled and includes
-         * the wakeup interrupt support, then the setting up external wakeup
-         * interrupts here can be skipped. This check here is temporary to
-         * allow exynos4 platforms that do not use Samsung pinctrl driver to
-         * co-exist with platforms that do. When all of the Samsung Exynos4
-         * platforms switch over to using the pinctrl driver, the wakeup
-         * interrupt support code here can be completely removed.
-         */
-        static const struct of_device_id exynos_pinctrl_ids[] = {
-                { .compatible = "samsung,exynos4210-pinctrl", },
-                { .compatible = "samsung,exynos4x12-pinctrl", },
-                { .compatible = "samsung,exynos5250-pinctrl", },
-        };
-        struct device_node *pctrl_np, *wkup_np;
-        const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
-
-        for_each_matching_node(pctrl_np, exynos_pinctrl_ids) {
-                if (of_device_is_available(pctrl_np)) {
-                        wkup_np = of_find_compatible_node(pctrl_np, NULL,
-                                                        wkup_compat);
-                        if (wkup_np)
-                                return -ENODEV;
-                }
-        }
-#endif
-        if (soc_is_exynos5440())
-                return 0;
-
-        if (soc_is_exynos5250())
-                exynos_eint_base = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
-        else
-                exynos_eint_base = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
-
-        if (exynos_eint_base == NULL) {
-                pr_err("unable to ioremap for EINT base address\n");
-                return -ENOMEM;
-        }
-
-        for (irq = 0 ; irq <= 31 ; irq++) {
-                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos_irq_eint,
-                                         handle_level_irq);
-                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
-        }
-
-        irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos_irq_demux_eint16_31);
-
-        for (irq = 0 ; irq <= 15 ; irq++) {
-                eint0_15_data[irq] = IRQ_EINT(irq);
-
-                if (soc_is_exynos5250()) {
-                        irq_set_handler_data(exynos5_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                } else {
-                        irq_set_handler_data(exynos4_eint0_15_src_int[irq],
-                                             &eint0_15_data[irq]);
-                        irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
-                                                exynos_irq_eint0_15);
-                }
-        }
-
-        return 0;
-}
-arch_initcall(exynos_init_irq_eint);
-
-static struct resource exynos4_pmu_resource[] = {
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
-#if defined(CONFIG_SOC_EXYNOS4412)
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
-        DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
-#endif
-};
-
-static struct platform_device exynos4_device_pmu = {
-        .name           = "arm-pmu",
-        .num_resources  = ARRAY_SIZE(exynos4_pmu_resource),
-        .resource       = exynos4_pmu_resource,
-};
-
-static int __init exynos_armpmu_init(void)
-{
-        if (!of_have_populated_dt()) {
-                if (soc_is_exynos4210() || soc_is_exynos4212())
-                        exynos4_device_pmu.num_resources = 2;
-                platform_device_register(&exynos4_device_pmu);
-        }
-
-        return 0;
-}
-arch_initcall(exynos_armpmu_init);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 11fc1e29819b..38d45fd23be4 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -19,9 +19,7 @@ void exynos_init_time(void);
 extern unsigned long xxti_f, xusbxti_f;
 
 struct map_desc;
-void exynos_init_io(struct map_desc *mach_desc, int size);
-void exynos4_init_irq(void);
-void exynos5_init_irq(void);
+void exynos_init_io(void);
 void exynos4_restart(char mode, const char *cmd);
 void exynos5_restart(char mode, const char *cmd);
 void exynos_init_late(void);
diff --git a/arch/arm/mach-exynos/dev-ahci.c b/arch/arm/mach-exynos/dev-ahci.c
deleted file mode 100644
index ce1aad3eeeb9..000000000000
--- a/arch/arm/mach-exynos/dev-ahci.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-ahci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - AHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/ahci_platform.h>
-
-#include <plat/cpu.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-#include <mach/regs-pmu.h>
-
-/* PHY Control Register */
-#define SATA_CTRL0              0x0
-/* PHY Link Control Register */
-#define SATA_CTRL1              0x4
-/* PHY Status Register */
-#define SATA_PHY_STATUS         0x8
-
-#define SATA_CTRL0_RX_DATA_VALID(x)     (x << 27)
-#define SATA_CTRL0_SPEED_MODE           (1 << 26)
-#define SATA_CTRL0_M_PHY_CAL            (1 << 19)
-#define SATA_CTRL0_PHY_CMU_RST_N        (1 << 10)
-#define SATA_CTRL0_M_PHY_LN_RST_N       (1 << 9)
-#define SATA_CTRL0_PHY_POR_N            (1 << 8)
-
-#define SATA_CTRL1_RST_PMALIVE_N        (1 << 8)
-#define SATA_CTRL1_RST_RXOOB_N          (1 << 7)
-#define SATA_CTRL1_RST_RX_N             (1 << 6)
-#define SATA_CTRL1_RST_TX_N             (1 << 5)
-
-#define SATA_PHY_STATUS_CMU_OK          (1 << 18)
-#define SATA_PHY_STATUS_LANE_OK         (1 << 16)
-
-#define LANE0           0x200
-#define COM_LANE        0xA00
-
-#define HOST_PORTS_IMPL 0xC
-#define SCLK_SATA_FREQ  (67 * MHZ)
-
-static void __iomem *phy_base, *phy_ctrl;
-
-struct phy_reg {
-        u8      reg;
-        u8      val;
-};
-
-/* SATA PHY setup */
-static const struct phy_reg exynos4_sataphy_cmu[] = {
-        { 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
-        { 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
-        { 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
-        { 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
-        { 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
-        { 0x6b, 0xc8 }, { 0x6c, 0x06 },
-};
-
-static const struct phy_reg exynos4_sataphy_lane[] = {
-        { 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
-        { 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
-        { 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
-        { 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
-        { 0x51, 0x0f },
-};
-
-static const struct phy_reg exynos4_sataphy_comlane[] = {
-        { 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
-        { 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
-        { 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
-        { 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
-        { 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
-        { 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
-        { 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
-        { 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
-        { 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
-        { 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
-        { 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
-        { 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
-        { 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
-        { 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
-};
-
-static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
-{
-        unsigned long timeout;
-
-        /* wait for maximum of 3 sec */
-        timeout = jiffies + msecs_to_jiffies(3000);
-        while (!(__raw_readl(reg) & bit)) {
-                if (time_after(jiffies, timeout))
-                        return -1;
-                cpu_relax();
-        }
-        return 0;
-}
-
-static int ahci_phy_init(void __iomem *mmio)
-{
-        int i, ctrl0;
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
-                __raw_writeb(exynos4_sataphy_cmu[i].val,
-                phy_base + (exynos4_sataphy_cmu[i].reg * 4));
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
-                __raw_writeb(exynos4_sataphy_lane[i].val,
-                phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
-
-        for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
-                __raw_writeb(exynos4_sataphy_comlane[i].val,
-                phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
-
-        __raw_writeb(0x07, phy_base);
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_CMU_OK) < 0) {
-                printk(KERN_ERR "PHY CMU not ready\n");
-                return -EBUSY;
-        }
-
-        __raw_writeb(0x03, phy_base + (COM_LANE * 4));
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
-                                SATA_PHY_STATUS_LANE_OK) < 0) {
-                printk(KERN_ERR "PHY LANE not ready\n");
-                return -EBUSY;
-        }
-
-        ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
-        ctrl0 |= SATA_CTRL0_M_PHY_CAL;
-        __raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
-
-        return 0;
-}
-
-static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
-{
-        struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
-        int val, ret;
-
-        phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
-        if (!phy_base) {
-                dev_err(dev, "failed to allocate memory for SATA PHY\n");
-                return -ENOMEM;
-        }
-
-        phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
-        if (!phy_ctrl) {
-                dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        clk_sata = clk_get(dev, "sata");
-        if (IS_ERR(clk_sata)) {
-                dev_err(dev, "failed to get sata clock\n");
-                ret = PTR_ERR(clk_sata);
-                clk_sata = NULL;
-                goto err2;
-
-        }
-        clk_enable(clk_sata);
-
-        clk_sataphy = clk_get(dev, "sataphy");
-        if (IS_ERR(clk_sataphy)) {
-                dev_err(dev, "failed to get sataphy clock\n");
-                ret = PTR_ERR(clk_sataphy);
-                clk_sataphy = NULL;
-                goto err3;
-        }
-        clk_enable(clk_sataphy);
-
-        clk_sclk_sata = clk_get(dev, "sclk_sata");
-        if (IS_ERR(clk_sclk_sata)) {
-                dev_err(dev, "failed to get sclk_sata\n");
-                ret = PTR_ERR(clk_sclk_sata);
-                clk_sclk_sata = NULL;
-                goto err4;
-        }
-        clk_enable(clk_sclk_sata);
-        clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
-
-        __raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
-
-        /* Enable PHY link control */
-        val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
-                        SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL1);
-
-        /* Set communication speed as 3Gbps and enable PHY power */
-        val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
-                        SATA_CTRL0_PHY_POR_N;
-        __raw_writel(val, phy_ctrl + SATA_CTRL0);
-
-        /* Port0 is available */
-        __raw_writel(0x1, mmio + HOST_PORTS_IMPL);
-
-        return ahci_phy_init(mmio);
-
-err4:
-        clk_disable(clk_sataphy);
-        clk_put(clk_sataphy);
-err3:
-        clk_disable(clk_sata);
-        clk_put(clk_sata);
-err2:
-        iounmap(phy_ctrl);
-err1:
-        iounmap(phy_base);
-
-        return ret;
-}
-
-static struct ahci_platform_data exynos4_ahci_pdata = {
-        .init = exynos4_ahci_init,
-};
-
-static struct resource exynos4_ahci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SATA, SZ_64K),
-        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_SATA),
-};
-
-static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ahci = {
-        .name           = "ahci",
-        .id             = -1,
-        .resource       = exynos4_ahci_resource,
-        .num_resources  = ARRAY_SIZE(exynos4_ahci_resource),
-        .dev            = {
-                .platform_data          = &exynos4_ahci_pdata,
-                .dma_mask               = &exynos4_ahci_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-audio.c b/arch/arm/mach-exynos/dev-audio.c
deleted file mode 100644
index c662c89794b2..000000000000
--- a/arch/arm/mach-exynos/dev-audio.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dev-audio.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/asoc-s3c.h>
-
-#include <plat/gpio-cfg.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-#define EXYNOS4_AUDSS_INT_MEM   (0x03000000)
-
-static int exynos4_cfg_i2s(struct platform_device *pdev)
-{
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
-                break;
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata i2sv5_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
-                                         | QUIRK_NEED_RSTCLR,
-                        .idma_addr = EXYNOS4_AUDSS_INT_MEM,
-                },
-        },
-};
-
-static struct resource exynos4_i2s0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
-        [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
-};
-
-struct platform_device exynos4_device_i2s0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
-        .resource = exynos4_i2s0_resource,
-        .dev = {
-                .platform_data = &i2sv5_pdata,
-        },
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = exynos4_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_NO_MUXPSR,
-                },
-        },
-};
-
-static struct resource exynos4_i2s1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
-};
-
-struct platform_device exynos4_device_i2s1 = {
-        .name = "samsung-i2s",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
-        .resource = exynos4_i2s1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-static struct resource exynos4_i2s2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_I2S2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
-};
-
-struct platform_device exynos4_device_i2s2 = {
-        .name = "samsung-i2s",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
-        .resource = exynos4_i2s2_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 1:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
-                break;
-        case 2:
-                s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
-                break;
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = exynos4_pcm_cfg_gpio,
-};
-
-static struct resource exynos4_pcm0_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM0, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
-};
-
-struct platform_device exynos4_device_pcm0 = {
-        .name = "samsung-pcm",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
-        .resource = exynos4_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource exynos4_pcm1_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM1, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
-};
-
-struct platform_device exynos4_device_pcm1 = {
-        .name = "samsung-pcm",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
-        .resource = exynos4_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource exynos4_pcm2_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_PCM2, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_PCM2_TX),
-        [2] = DEFINE_RES_DMA(DMACH_PCM2_RX),
-};
-
-struct platform_device exynos4_device_pcm2 = {
-        .name = "samsung-pcm",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
-        .resource = exynos4_pcm2_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-/* AC97 Controller platform devices */
-
-static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
-{
-        return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
-}
-
-static struct resource exynos4_ac97_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_AC97, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
-        [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
-        [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
-        [4] = DEFINE_RES_IRQ(EXYNOS4_IRQ_AC97),
-};
-
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-        .cfg_gpio = exynos4_ac97_cfg_gpio,
-};
-
-static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ac97 = {
-        .name = "samsung-ac97",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
-        .resource = exynos4_ac97_resource,
-        .dev = {
-                .platform_data = &s3c_ac97_pdata,
-                .dma_mask = &exynos4_ac97_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
-
-/* S/PDIF Controller platform_device */
-
-static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
-{
-        s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(4));
-
-        return 0;
-}
-
-static struct resource exynos4_spdif_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SPDIF, SZ_256),
-        [1] = DEFINE_RES_DMA(DMACH_SPDIF),
-};
-
-static struct s3c_audio_pdata samsung_spdif_pdata = {
-        .cfg_gpio = exynos4_spdif_cfg_gpio,
-};
-
-static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_spdif = {
-        .name = "samsung-spdif",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
-        .resource = exynos4_spdif_resource,
-        .dev = {
-                .platform_data = &samsung_spdif_pdata,
-                .dma_mask = &exynos4_spdif_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-};
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
deleted file mode 100644
index d5bc129e6bb7..000000000000
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* linux/arch/arm/mach-exynos/dev-ohci.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - OHCI support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <plat/devs.h>
-#include <plat/usb-phy.h>
-
-static struct resource exynos4_ohci_resource[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
-        [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
-};
-
-static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
-
-struct platform_device exynos4_device_ohci = {
-        .name           = "exynos-ohci",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(exynos4_ohci_resource),
-        .resource       = exynos4_ohci_resource,
-        .dev            = {
-                .dma_mask               = &exynos4_ohci_dma_mask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        }
-};
-
-void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
-{
-        struct exynos4_ohci_platdata *npd;
-
-        npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
-                        &exynos4_device_ohci);
-
-        if (!npd->phy_init)
-                npd->phy_init = s5p_usb_phy_init;
-        if (!npd->phy_exit)
-                npd->phy_exit = s5p_usb_phy_exit;
-}
diff --git a/arch/arm/mach-exynos/dev-uart.c b/arch/arm/mach-exynos/dev-uart.c
deleted file mode 100644
index c48aff02c786..000000000000
--- a/arch/arm/mach-exynos/dev-uart.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Base EXYNOS UART resource and device definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include <plat/devs.h>
-
-#define EXYNOS_UART_RESOURCE(_series, _nr)      \
-static struct resource exynos##_series##_uart##_nr##_resource[] = {     \
-        [0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART),        \
-        [1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr),  \
-};
-
-EXYNOS_UART_RESOURCE(4, 0)
-EXYNOS_UART_RESOURCE(4, 1)
-EXYNOS_UART_RESOURCE(4, 2)
-EXYNOS_UART_RESOURCE(4, 3)
-
-struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
-        [0] = {
-                .resources      = exynos4_uart0_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart0_resource),
-        },
-        [1] = {
-                .resources      = exynos4_uart1_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart1_resource),
-        },
-        [2] = {
-                .resources      = exynos4_uart2_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart2_resource),
-        },
-        [3] = {
-                .resources      = exynos4_uart3_resource,
-                .nr_resources   = ARRAY_SIZE(exynos4_uart3_resource),
-        },
-};
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
deleted file mode 100644
index 87e07d6fc615..000000000000
--- a/arch/arm/mach-exynos/dma.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/* linux/arch/arm/mach-exynos4/dma.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/pl330.h>
-#include <linux/of.h>
-
-#include <asm/irq.h>
-#include <plat/devs.h>
-#include <plat/irqs.h>
-#include <plat/cpu.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/dma.h>
-
-static u8 exynos4210_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MSM_REQ0,
-        DMACH_MSM_REQ2,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-};
-
-static u8 exynos4212_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI1,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI5,
-};
-
-static u8 exynos5250_pdma0_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM2_RX,
-        DMACH_PCM2_TX,
-        DMACH_SPI0_RX,
-        DMACH_SPI0_TX,
-        DMACH_SPI2_RX,
-        DMACH_SPI2_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S2_RX,
-        DMACH_I2S2_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART2_RX,
-        DMACH_UART2_TX,
-        DMACH_UART4_RX,
-        DMACH_UART4_TX,
-        DMACH_SLIMBUS0_RX,
-        DMACH_SLIMBUS0_TX,
-        DMACH_SLIMBUS2_RX,
-        DMACH_SLIMBUS2_TX,
-        DMACH_SLIMBUS4_RX,
-        DMACH_SLIMBUS4_TX,
-        DMACH_AC97_MICIN,
-        DMACH_AC97_PCMIN,
-        DMACH_AC97_PCMOUT,
-        DMACH_MIPI_HSI0,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI4,
-        DMACH_MIPI_HSI6,
-};
-
-static struct dma_pl330_platdata exynos_pdma0_pdata;
-
-static AMBA_AHB_DEVICE(exynos_pdma0, "dma-pl330.0", 0x00041330,
-        EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos_pdma0_pdata);
-
-static u8 exynos4210_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MSM_REQ1,
-        DMACH_MSM_REQ3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-};
-
-static u8 exynos4212_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_MIPI_HSI2,
-        DMACH_MIPI_HSI3,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_SPDIF,
-        DMACH_MIPI_HSI6,
-        DMACH_MIPI_HSI7,
-};
-
-static u8 exynos5250_pdma1_peri[] = {
-        DMACH_PCM0_RX,
-        DMACH_PCM0_TX,
-        DMACH_PCM1_RX,
-        DMACH_PCM1_TX,
-        DMACH_SPI1_RX,
-        DMACH_SPI1_TX,
-        DMACH_PWM,
-        DMACH_SPDIF,
-        DMACH_I2S0S_TX,
-        DMACH_I2S0_RX,
-        DMACH_I2S0_TX,
-        DMACH_I2S1_RX,
-        DMACH_I2S1_TX,
-        DMACH_UART0_RX,
-        DMACH_UART0_TX,
-        DMACH_UART1_RX,
-        DMACH_UART1_TX,
-        DMACH_UART3_RX,
-        DMACH_UART3_TX,
-        DMACH_SLIMBUS1_RX,
-        DMACH_SLIMBUS1_TX,
-        DMACH_SLIMBUS3_RX,
-        DMACH_SLIMBUS3_TX,
-        DMACH_SLIMBUS5_RX,
-        DMACH_SLIMBUS5_TX,
-        DMACH_SLIMBUS0AUX_RX,
-        DMACH_SLIMBUS0AUX_TX,
-        DMACH_DISP1,
-        DMACH_MIPI_HSI1,
-        DMACH_MIPI_HSI3,
-        DMACH_MIPI_HSI5,
-        DMACH_MIPI_HSI7,
-};
-
-static struct dma_pl330_platdata exynos_pdma1_pdata;
-
-static AMBA_AHB_DEVICE(exynos_pdma1,  "dma-pl330.1", 0x00041330,
-        EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos_pdma1_pdata);
-
-static u8 mdma_peri[] = {
-        DMACH_MTOM_0,
-        DMACH_MTOM_1,
-        DMACH_MTOM_2,
-        DMACH_MTOM_3,
-        DMACH_MTOM_4,
-        DMACH_MTOM_5,
-        DMACH_MTOM_6,
-        DMACH_MTOM_7,
-};
-
-static struct dma_pl330_platdata exynos_mdma1_pdata = {
-        .nr_valid_peri = ARRAY_SIZE(mdma_peri),
-        .peri_id = mdma_peri,
-};
-
-static AMBA_AHB_DEVICE(exynos_mdma1,  "dma-pl330.2", 0x00041330,
-        EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos_mdma1_pdata);
-
-static int __init exynos_dma_init(void)
-{
-        if (of_have_populated_dt())
-                return 0;
-
-        if (soc_is_exynos4210()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4210_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
-
-                if (samsung_rev() == EXYNOS4210_REV_0)
-                        exynos_mdma1_device.res.start = EXYNOS4_PA_S_MDMA1;
-        } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos4212_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
-        } else if (soc_is_exynos5250()) {
-                exynos_pdma0_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma0_peri);
-                exynos_pdma0_pdata.peri_id = exynos5250_pdma0_peri;
-                exynos_pdma1_pdata.nr_valid_peri =
-                        ARRAY_SIZE(exynos5250_pdma1_peri);
-                exynos_pdma1_pdata.peri_id = exynos5250_pdma1_peri;
-
-                exynos_pdma0_device.res.start = EXYNOS5_PA_PDMA0;
-                exynos_pdma0_device.res.end = EXYNOS5_PA_PDMA0 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA0;
-                exynos_pdma1_device.res.start = EXYNOS5_PA_PDMA1;
-                exynos_pdma1_device.res.end = EXYNOS5_PA_PDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_PDMA1;
-                exynos_mdma1_device.res.start = EXYNOS5_PA_MDMA1;
-                exynos_mdma1_device.res.end = EXYNOS5_PA_MDMA1 + SZ_4K;
-                exynos_pdma0_device.irq[0] = EXYNOS5_IRQ_MDMA1;
-        }
-
-        dma_cap_set(DMA_SLAVE, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma0_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma0_pdata.cap_mask);
-        amba_device_register(&exynos_pdma0_device, &iomem_resource);
-
-        dma_cap_set(DMA_SLAVE, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_CYCLIC, exynos_pdma1_pdata.cap_mask);
-        dma_cap_set(DMA_PRIVATE, exynos_pdma1_pdata.cap_mask);
-        amba_device_register(&exynos_pdma1_device, &iomem_resource);
-
-        dma_cap_set(DMA_MEMCPY, exynos_mdma1_pdata.cap_mask);
-        amba_device_register(&exynos_mdma1_device, &iomem_resource);
-
-        return 0;
-}
-arch_initcall(exynos_dma_init);
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index ed11f100d479..932129ef26c6 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -48,20 +48,18 @@ static const struct firmware_ops exynos_firmware_ops = {
 
 void __init exynos_firmware_init(void)
 {
-        if (of_have_populated_dt()) {
-                struct device_node *nd;
-                const __be32 *addr;
+        struct device_node *nd;
+        const __be32 *addr;
 
-                nd = of_find_compatible_node(NULL, NULL,
-                                                "samsung,secure-firmware");
-                if (!nd)
-                        return;
+        nd = of_find_compatible_node(NULL, NULL,
+                                        "samsung,secure-firmware");
+        if (!nd)
+                return;
 
-                addr = of_get_address(nd, 0, NULL, NULL);
-                if (!addr) {
-                        pr_err("%s: No address specified.\n", __func__);
-                        return;
-                }
+        addr = of_get_address(nd, 0, NULL, NULL);
+        if (!addr) {
+                pr_err("%s: No address specified.\n", __func__);
+                return;
         }
 
         pr_info("Running under secure firmware.\n");
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* Macro for EXYNOS GPIO numbering */
-
-#define EXYNOS_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-/* EXYNOS4 GPIO bank sizes */
-
-#define EXYNOS4_GPIO_A0_NR      (8)
-#define EXYNOS4_GPIO_A1_NR      (6)
-#define EXYNOS4_GPIO_B_NR       (8)
-#define EXYNOS4_GPIO_C0_NR      (5)
-#define EXYNOS4_GPIO_C1_NR      (5)
-#define EXYNOS4_GPIO_D0_NR      (4)
-#define EXYNOS4_GPIO_D1_NR      (4)
-#define EXYNOS4_GPIO_E0_NR      (5)
-#define EXYNOS4_GPIO_E1_NR      (8)
-#define EXYNOS4_GPIO_E2_NR      (6)
-#define EXYNOS4_GPIO_E3_NR      (8)
-#define EXYNOS4_GPIO_E4_NR      (8)
-#define EXYNOS4_GPIO_F0_NR      (8)
-#define EXYNOS4_GPIO_F1_NR      (8)
-#define EXYNOS4_GPIO_F2_NR      (8)
-#define EXYNOS4_GPIO_F3_NR      (6)
-#define EXYNOS4_GPIO_J0_NR      (8)
-#define EXYNOS4_GPIO_J1_NR      (5)
-#define EXYNOS4_GPIO_K0_NR      (7)
-#define EXYNOS4_GPIO_K1_NR      (7)
-#define EXYNOS4_GPIO_K2_NR      (7)
-#define EXYNOS4_GPIO_K3_NR      (7)
-#define EXYNOS4_GPIO_L0_NR      (8)
-#define EXYNOS4_GPIO_L1_NR      (3)
-#define EXYNOS4_GPIO_L2_NR      (8)
-#define EXYNOS4_GPIO_X0_NR      (8)
-#define EXYNOS4_GPIO_X1_NR      (8)
-#define EXYNOS4_GPIO_X2_NR      (8)
-#define EXYNOS4_GPIO_X3_NR      (8)
-#define EXYNOS4_GPIO_Y0_NR      (6)
-#define EXYNOS4_GPIO_Y1_NR      (4)
-#define EXYNOS4_GPIO_Y2_NR      (6)
-#define EXYNOS4_GPIO_Y3_NR      (8)
-#define EXYNOS4_GPIO_Y4_NR      (8)
-#define EXYNOS4_GPIO_Y5_NR      (8)
-#define EXYNOS4_GPIO_Y6_NR      (8)
-#define EXYNOS4_GPIO_Z_NR       (7)
-
-/* EXYNOS4 GPIO bank numbers */
-
-enum exynos4_gpio_number {
-        EXYNOS4_GPIO_A0_START   = 0,
-        EXYNOS4_GPIO_A1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
-        EXYNOS4_GPIO_B_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
-        EXYNOS4_GPIO_C0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
-        EXYNOS4_GPIO_C1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
-        EXYNOS4_GPIO_D0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
-        EXYNOS4_GPIO_D1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
-        EXYNOS4_GPIO_E0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
-        EXYNOS4_GPIO_E1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
-        EXYNOS4_GPIO_E2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
-        EXYNOS4_GPIO_E3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
-        EXYNOS4_GPIO_E4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
-        EXYNOS4_GPIO_F0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
-        EXYNOS4_GPIO_F1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
-        EXYNOS4_GPIO_F2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
-        EXYNOS4_GPIO_F3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
-        EXYNOS4_GPIO_J0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
-        EXYNOS4_GPIO_J1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
-        EXYNOS4_GPIO_K0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
-        EXYNOS4_GPIO_K1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
-        EXYNOS4_GPIO_K2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
-        EXYNOS4_GPIO_K3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
-        EXYNOS4_GPIO_L0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
-        EXYNOS4_GPIO_L1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
-        EXYNOS4_GPIO_L2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
-        EXYNOS4_GPIO_X0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
-        EXYNOS4_GPIO_X1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
-        EXYNOS4_GPIO_X2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
-        EXYNOS4_GPIO_X3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
-        EXYNOS4_GPIO_Y0_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
-        EXYNOS4_GPIO_Y1_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
-        EXYNOS4_GPIO_Y2_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
-        EXYNOS4_GPIO_Y3_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
-        EXYNOS4_GPIO_Y4_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
-        EXYNOS4_GPIO_Y5_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
-        EXYNOS4_GPIO_Y6_START   = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
-        EXYNOS4_GPIO_Z_START    = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
-};
-
-/* EXYNOS4 GPIO number definitions */
-
-#define EXYNOS4_GPA0(_nr)       (EXYNOS4_GPIO_A0_START + (_nr))
-#define EXYNOS4_GPA1(_nr)       (EXYNOS4_GPIO_A1_START + (_nr))
-#define EXYNOS4_GPB(_nr)        (EXYNOS4_GPIO_B_START + (_nr))
-#define EXYNOS4_GPC0(_nr)       (EXYNOS4_GPIO_C0_START + (_nr))
-#define EXYNOS4_GPC1(_nr)       (EXYNOS4_GPIO_C1_START + (_nr))
-#define EXYNOS4_GPD0(_nr)       (EXYNOS4_GPIO_D0_START + (_nr))
-#define EXYNOS4_GPD1(_nr)       (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr)       (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr)       (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr)       (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr)       (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr)       (EXYNOS4_GPIO_E4_START + (_nr))
-#define EXYNOS4_GPF0(_nr)       (EXYNOS4_GPIO_F0_START + (_nr))
-#define EXYNOS4_GPF1(_nr)       (EXYNOS4_GPIO_F1_START + (_nr))
-#define EXYNOS4_GPF2(_nr)       (EXYNOS4_GPIO_F2_START + (_nr))
-#define EXYNOS4_GPF3(_nr)       (EXYNOS4_GPIO_F3_START + (_nr))
-#define EXYNOS4_GPJ0(_nr)       (EXYNOS4_GPIO_J0_START + (_nr))
-#define EXYNOS4_GPJ1(_nr)       (EXYNOS4_GPIO_J1_START + (_nr))
-#define EXYNOS4_GPK0(_nr)       (EXYNOS4_GPIO_K0_START + (_nr))
-#define EXYNOS4_GPK1(_nr)       (EXYNOS4_GPIO_K1_START + (_nr))
-#define EXYNOS4_GPK2(_nr)       (EXYNOS4_GPIO_K2_START + (_nr))
-#define EXYNOS4_GPK3(_nr)       (EXYNOS4_GPIO_K3_START + (_nr))
-#define EXYNOS4_GPL0(_nr)       (EXYNOS4_GPIO_L0_START + (_nr))
-#define EXYNOS4_GPL1(_nr)       (EXYNOS4_GPIO_L1_START + (_nr))
-#define EXYNOS4_GPL2(_nr)       (EXYNOS4_GPIO_L2_START + (_nr))
-#define EXYNOS4_GPX0(_nr)       (EXYNOS4_GPIO_X0_START + (_nr))
-#define EXYNOS4_GPX1(_nr)       (EXYNOS4_GPIO_X1_START + (_nr))
-#define EXYNOS4_GPX2(_nr)       (EXYNOS4_GPIO_X2_START + (_nr))
-#define EXYNOS4_GPX3(_nr)       (EXYNOS4_GPIO_X3_START + (_nr))
-#define EXYNOS4_GPY0(_nr)       (EXYNOS4_GPIO_Y0_START + (_nr))
-#define EXYNOS4_GPY1(_nr)       (EXYNOS4_GPIO_Y1_START + (_nr))
-#define EXYNOS4_GPY2(_nr)       (EXYNOS4_GPIO_Y2_START + (_nr))
-#define EXYNOS4_GPY3(_nr)       (EXYNOS4_GPIO_Y3_START + (_nr))
-#define EXYNOS4_GPY4(_nr)       (EXYNOS4_GPIO_Y4_START + (_nr))
-#define EXYNOS4_GPY5(_nr)       (EXYNOS4_GPIO_Y5_START + (_nr))
-#define EXYNOS4_GPY6(_nr)       (EXYNOS4_GPIO_Y6_START + (_nr))
-#define EXYNOS4_GPZ(_nr)        (EXYNOS4_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS4 specific gpios */
-
-#define EXYNOS4_GPIO_END        (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-
-/* EXYNOS5 GPIO bank sizes */
-
-#define EXYNOS5_GPIO_A0_NR      (8)
-#define EXYNOS5_GPIO_A1_NR      (6)
-#define EXYNOS5_GPIO_A2_NR      (8)
-#define EXYNOS5_GPIO_B0_NR      (5)
-#define EXYNOS5_GPIO_B1_NR      (5)
-#define EXYNOS5_GPIO_B2_NR      (4)
-#define EXYNOS5_GPIO_B3_NR      (4)
-#define EXYNOS5_GPIO_C0_NR      (7)
-#define EXYNOS5_GPIO_C1_NR      (4)
-#define EXYNOS5_GPIO_C2_NR      (7)
-#define EXYNOS5_GPIO_C3_NR      (7)
-#define EXYNOS5_GPIO_C4_NR      (7)
-#define EXYNOS5_GPIO_D0_NR      (4)
-#define EXYNOS5_GPIO_D1_NR      (8)
-#define EXYNOS5_GPIO_Y0_NR      (6)
-#define EXYNOS5_GPIO_Y1_NR      (4)
-#define EXYNOS5_GPIO_Y2_NR      (6)
-#define EXYNOS5_GPIO_Y3_NR      (8)
-#define EXYNOS5_GPIO_Y4_NR      (8)
-#define EXYNOS5_GPIO_Y5_NR      (8)
-#define EXYNOS5_GPIO_Y6_NR      (8)
-#define EXYNOS5_GPIO_X0_NR      (8)
-#define EXYNOS5_GPIO_X1_NR      (8)
-#define EXYNOS5_GPIO_X2_NR      (8)
-#define EXYNOS5_GPIO_X3_NR      (8)
-#define EXYNOS5_GPIO_E0_NR      (8)
-#define EXYNOS5_GPIO_E1_NR      (2)
-#define EXYNOS5_GPIO_F0_NR      (4)
-#define EXYNOS5_GPIO_F1_NR      (4)
-#define EXYNOS5_GPIO_G0_NR      (8)
-#define EXYNOS5_GPIO_G1_NR      (8)
-#define EXYNOS5_GPIO_G2_NR      (2)
-#define EXYNOS5_GPIO_H0_NR      (4)
-#define EXYNOS5_GPIO_H1_NR      (8)
-#define EXYNOS5_GPIO_V0_NR      (8)
-#define EXYNOS5_GPIO_V1_NR      (8)
-#define EXYNOS5_GPIO_V2_NR      (8)
-#define EXYNOS5_GPIO_V3_NR      (8)
-#define EXYNOS5_GPIO_V4_NR      (2)
-#define EXYNOS5_GPIO_Z_NR       (7)
-
-/* EXYNOS5 GPIO bank numbers */
-
-enum exynos5_gpio_number {
-        EXYNOS5_GPIO_A0_START           = 0,
-        EXYNOS5_GPIO_A1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
-        EXYNOS5_GPIO_A2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
-        EXYNOS5_GPIO_B0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
-        EXYNOS5_GPIO_B1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
-        EXYNOS5_GPIO_B2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
-        EXYNOS5_GPIO_B3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
-        EXYNOS5_GPIO_C0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
-        EXYNOS5_GPIO_C1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
-        EXYNOS5_GPIO_C2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
-        EXYNOS5_GPIO_C3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-        EXYNOS5_GPIO_C4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
-        EXYNOS5_GPIO_D0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
-        EXYNOS5_GPIO_D1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
-        EXYNOS5_GPIO_Y0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
-        EXYNOS5_GPIO_Y1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
-        EXYNOS5_GPIO_Y2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
-        EXYNOS5_GPIO_Y3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
-        EXYNOS5_GPIO_Y4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
-        EXYNOS5_GPIO_Y5_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
-        EXYNOS5_GPIO_Y6_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
-        EXYNOS5_GPIO_X0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
-        EXYNOS5_GPIO_X1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
-        EXYNOS5_GPIO_X2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
-        EXYNOS5_GPIO_X3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
-        EXYNOS5_GPIO_E0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
-        EXYNOS5_GPIO_E1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
-        EXYNOS5_GPIO_F0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
-        EXYNOS5_GPIO_F1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
-        EXYNOS5_GPIO_G0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
-        EXYNOS5_GPIO_G1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
-        EXYNOS5_GPIO_G2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
-        EXYNOS5_GPIO_H0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
-        EXYNOS5_GPIO_H1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
-        EXYNOS5_GPIO_V0_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
-        EXYNOS5_GPIO_V1_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
-        EXYNOS5_GPIO_V2_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
-        EXYNOS5_GPIO_V3_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
-        EXYNOS5_GPIO_V4_START           = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
-        EXYNOS5_GPIO_Z_START            = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
-};
-
-/* EXYNOS5 GPIO number definitions */
-
-#define EXYNOS5_GPA0(_nr)       (EXYNOS5_GPIO_A0_START + (_nr))
-#define EXYNOS5_GPA1(_nr)       (EXYNOS5_GPIO_A1_START + (_nr))
-#define EXYNOS5_GPA2(_nr)       (EXYNOS5_GPIO_A2_START + (_nr))
-#define EXYNOS5_GPB0(_nr)       (EXYNOS5_GPIO_B0_START + (_nr))
-#define EXYNOS5_GPB1(_nr)       (EXYNOS5_GPIO_B1_START + (_nr))
-#define EXYNOS5_GPB2(_nr)       (EXYNOS5_GPIO_B2_START + (_nr))
-#define EXYNOS5_GPB3(_nr)       (EXYNOS5_GPIO_B3_START + (_nr))
-#define EXYNOS5_GPC0(_nr)       (EXYNOS5_GPIO_C0_START + (_nr))
-#define EXYNOS5_GPC1(_nr)       (EXYNOS5_GPIO_C1_START + (_nr))
-#define EXYNOS5_GPC2(_nr)       (EXYNOS5_GPIO_C2_START + (_nr))
-#define EXYNOS5_GPC3(_nr)       (EXYNOS5_GPIO_C3_START + (_nr))
-#define EXYNOS5_GPC4(_nr)       (EXYNOS5_GPIO_C4_START + (_nr))
-#define EXYNOS5_GPD0(_nr)       (EXYNOS5_GPIO_D0_START + (_nr))
-#define EXYNOS5_GPD1(_nr)       (EXYNOS5_GPIO_D1_START + (_nr))
-#define EXYNOS5_GPY0(_nr)       (EXYNOS5_GPIO_Y0_START + (_nr))
-#define EXYNOS5_GPY1(_nr)       (EXYNOS5_GPIO_Y1_START + (_nr))
-#define EXYNOS5_GPY2(_nr)       (EXYNOS5_GPIO_Y2_START + (_nr))
-#define EXYNOS5_GPY3(_nr)       (EXYNOS5_GPIO_Y3_START + (_nr))
-#define EXYNOS5_GPY4(_nr)       (EXYNOS5_GPIO_Y4_START + (_nr))
-#define EXYNOS5_GPY5(_nr)       (EXYNOS5_GPIO_Y5_START + (_nr))
-#define EXYNOS5_GPY6(_nr)       (EXYNOS5_GPIO_Y6_START + (_nr))
-#define EXYNOS5_GPX0(_nr)       (EXYNOS5_GPIO_X0_START + (_nr))
-#define EXYNOS5_GPX1(_nr)       (EXYNOS5_GPIO_X1_START + (_nr))
-#define EXYNOS5_GPX2(_nr)       (EXYNOS5_GPIO_X2_START + (_nr))
-#define EXYNOS5_GPX3(_nr)       (EXYNOS5_GPIO_X3_START + (_nr))
-#define EXYNOS5_GPE0(_nr)       (EXYNOS5_GPIO_E0_START + (_nr))
-#define EXYNOS5_GPE1(_nr)       (EXYNOS5_GPIO_E1_START + (_nr))
-#define EXYNOS5_GPF0(_nr)       (EXYNOS5_GPIO_F0_START + (_nr))
-#define EXYNOS5_GPF1(_nr)       (EXYNOS5_GPIO_F1_START + (_nr))
-#define EXYNOS5_GPG0(_nr)       (EXYNOS5_GPIO_G0_START + (_nr))
-#define EXYNOS5_GPG1(_nr)       (EXYNOS5_GPIO_G1_START + (_nr))
-#define EXYNOS5_GPG2(_nr)       (EXYNOS5_GPIO_G2_START + (_nr))
-#define EXYNOS5_GPH0(_nr)       (EXYNOS5_GPIO_H0_START + (_nr))
-#define EXYNOS5_GPH1(_nr)       (EXYNOS5_GPIO_H1_START + (_nr))
-#define EXYNOS5_GPV0(_nr)       (EXYNOS5_GPIO_V0_START + (_nr))
-#define EXYNOS5_GPV1(_nr)       (EXYNOS5_GPIO_V1_START + (_nr))
-#define EXYNOS5_GPV2(_nr)       (EXYNOS5_GPIO_V2_START + (_nr))
-#define EXYNOS5_GPV3(_nr)       (EXYNOS5_GPIO_V3_START + (_nr))
-#define EXYNOS5_GPV4(_nr)       (EXYNOS5_GPIO_V4_START + (_nr))
-#define EXYNOS5_GPZ(_nr)        (EXYNOS5_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS5 specific gpios */
-
-#define EXYNOS5_GPIO_END        (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
-
-/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
-
-#define S3C_GPIO_END            (EXYNOS5_GPIO_END)
-
-/* define the number of gpios */
-
-#define ARCH_NR_GPIOS           (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* PPI: Private Peripheral Interrupt */
-
-#define IRQ_PPI(x)                      (x + 16)
-
-/* SPI: Shared Peripheral Interrupt */
-
-#define IRQ_SPI(x)                      (x + 32)
-
-/* COMBINER */
-
-#define MAX_IRQ_IN_COMBINER             8
-#define COMBINER_GROUP(x)               ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y)              (COMBINER_GROUP(x) + y)
-
-/* For EXYNOS4 and EXYNOS5 */
-
-#define EXYNOS_IRQ_EINT16_31            IRQ_SPI(32)
-
-/* For EXYNOS4 SoCs */
-
-#define EXYNOS4_IRQ_EINT0               IRQ_SPI(16)
-#define EXYNOS4_IRQ_EINT1               IRQ_SPI(17)
-#define EXYNOS4_IRQ_EINT2               IRQ_SPI(18)
-#define EXYNOS4_IRQ_EINT3               IRQ_SPI(19)
-#define EXYNOS4_IRQ_EINT4               IRQ_SPI(20)
-#define EXYNOS4_IRQ_EINT5               IRQ_SPI(21)
-#define EXYNOS4_IRQ_EINT6               IRQ_SPI(22)
-#define EXYNOS4_IRQ_EINT7               IRQ_SPI(23)
-#define EXYNOS4_IRQ_EINT8               IRQ_SPI(24)
-#define EXYNOS4_IRQ_EINT9               IRQ_SPI(25)
-#define EXYNOS4_IRQ_EINT10              IRQ_SPI(26)
-#define EXYNOS4_IRQ_EINT11              IRQ_SPI(27)
-#define EXYNOS4_IRQ_EINT12              IRQ_SPI(28)
-#define EXYNOS4_IRQ_EINT13              IRQ_SPI(29)
-#define EXYNOS4_IRQ_EINT14              IRQ_SPI(30)
-#define EXYNOS4_IRQ_EINT15              IRQ_SPI(31)
-
-#define EXYNOS4_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS4_IRQ_MDMA1               IRQ_SPI(34)
-#define EXYNOS4_IRQ_PDMA0               IRQ_SPI(35)
-#define EXYNOS4_IRQ_PDMA1               IRQ_SPI(36)
-#define EXYNOS4_IRQ_TIMER0_VIC          IRQ_SPI(37)
-#define EXYNOS4_IRQ_TIMER1_VIC          IRQ_SPI(38)
-#define EXYNOS4_IRQ_TIMER2_VIC          IRQ_SPI(39)
-#define EXYNOS4_IRQ_TIMER3_VIC          IRQ_SPI(40)
-#define EXYNOS4_IRQ_TIMER4_VIC          IRQ_SPI(41)
-#define EXYNOS4_IRQ_MCT_L0              IRQ_SPI(42)
-#define EXYNOS4_IRQ_WDT                 IRQ_SPI(43)
-#define EXYNOS4_IRQ_RTC_ALARM           IRQ_SPI(44)
-#define EXYNOS4_IRQ_RTC_TIC             IRQ_SPI(45)
-#define EXYNOS4_IRQ_GPIO_XB             IRQ_SPI(46)
-#define EXYNOS4_IRQ_GPIO_XA             IRQ_SPI(47)
-#define EXYNOS4_IRQ_MCT_L1              IRQ_SPI(48)
-
-#define EXYNOS4_IRQ_UART0               IRQ_SPI(52)
-#define EXYNOS4_IRQ_UART1               IRQ_SPI(53)
-#define EXYNOS4_IRQ_UART2               IRQ_SPI(54)
-#define EXYNOS4_IRQ_UART3               IRQ_SPI(55)
-#define EXYNOS4_IRQ_UART4               IRQ_SPI(56)
-#define EXYNOS4_IRQ_MCT_G0              IRQ_SPI(57)
-#define EXYNOS4_IRQ_IIC                 IRQ_SPI(58)
-#define EXYNOS4_IRQ_IIC1                IRQ_SPI(59)
-#define EXYNOS4_IRQ_IIC2                IRQ_SPI(60)
-#define EXYNOS4_IRQ_IIC3                IRQ_SPI(61)
-#define EXYNOS4_IRQ_IIC4                IRQ_SPI(62)
-#define EXYNOS4_IRQ_IIC5                IRQ_SPI(63)
-#define EXYNOS4_IRQ_IIC6                IRQ_SPI(64)
-#define EXYNOS4_IRQ_IIC7                IRQ_SPI(65)
-#define EXYNOS4_IRQ_SPI0                IRQ_SPI(66)
-#define EXYNOS4_IRQ_SPI1                IRQ_SPI(67)
-#define EXYNOS4_IRQ_SPI2                IRQ_SPI(68)
-
-#define EXYNOS4_IRQ_USB_HOST            IRQ_SPI(70)
-#define EXYNOS4_IRQ_USB_HSOTG           IRQ_SPI(71)
-#define EXYNOS4_IRQ_MODEM_IF            IRQ_SPI(72)
-#define EXYNOS4_IRQ_HSMMC0              IRQ_SPI(73)
-#define EXYNOS4_IRQ_HSMMC1              IRQ_SPI(74)
-#define EXYNOS4_IRQ_HSMMC2              IRQ_SPI(75)
-#define EXYNOS4_IRQ_HSMMC3              IRQ_SPI(76)
-#define EXYNOS4_IRQ_DWMCI               IRQ_SPI(77)
-
-#define EXYNOS4_IRQ_MIPI_CSIS0          IRQ_SPI(78)
-#define EXYNOS4_IRQ_MIPI_CSIS1          IRQ_SPI(80)
-
-#define EXYNOS4_IRQ_ONENAND_AUDI        IRQ_SPI(82)
-#define EXYNOS4_IRQ_ROTATOR             IRQ_SPI(83)
-#define EXYNOS4_IRQ_FIMC0               IRQ_SPI(84)
-#define EXYNOS4_IRQ_FIMC1               IRQ_SPI(85)
-#define EXYNOS4_IRQ_FIMC2               IRQ_SPI(86)
-#define EXYNOS4_IRQ_FIMC3               IRQ_SPI(87)
-#define EXYNOS4_IRQ_JPEG                IRQ_SPI(88)
-#define EXYNOS4_IRQ_2D                  IRQ_SPI(89)
-#define EXYNOS4_IRQ_PCIE                IRQ_SPI(90)
-
-#define EXYNOS4_IRQ_MIXER               IRQ_SPI(91)
-#define EXYNOS4_IRQ_HDMI                IRQ_SPI(92)
-#define EXYNOS4_IRQ_IIC_HDMIPHY         IRQ_SPI(93)
-#define EXYNOS4_IRQ_MFC                 IRQ_SPI(94)
-#define EXYNOS4_IRQ_SDO                 IRQ_SPI(95)
-
-#define EXYNOS4_IRQ_AUDIO_SS            IRQ_SPI(96)
-#define EXYNOS4_IRQ_I2S0                IRQ_SPI(97)
-#define EXYNOS4_IRQ_I2S1                IRQ_SPI(98)
-#define EXYNOS4_IRQ_I2S2                IRQ_SPI(99)
-#define EXYNOS4_IRQ_AC97                IRQ_SPI(100)
-
-#define EXYNOS4_IRQ_SPDIF               IRQ_SPI(104)
-#define EXYNOS4_IRQ_ADC0                IRQ_SPI(105)
-#define EXYNOS4_IRQ_PEN0                IRQ_SPI(106)
-#define EXYNOS4_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS4_IRQ_PEN1                IRQ_SPI(108)
-#define EXYNOS4_IRQ_KEYPAD              IRQ_SPI(109)
-#define EXYNOS4_IRQ_POWER_PMU           IRQ_SPI(110)
-#define EXYNOS4_IRQ_GPS                 IRQ_SPI(111)
-#define EXYNOS4_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS4_IRQ_SLIMBUS             IRQ_SPI(113)
-
-#define EXYNOS4_IRQ_TSI                 IRQ_SPI(115)
-#define EXYNOS4_IRQ_SATA                IRQ_SPI(116)
-
-#define EXYNOS4_IRQ_PMU                 COMBINER_IRQ(2, 2)
-#define EXYNOS4_IRQ_PMU_CPU1            COMBINER_IRQ(3, 2)
-#define EXYNOS4_IRQ_PMU_CPU2            COMBINER_IRQ(18, 2)
-#define EXYNOS4_IRQ_PMU_CPU3            COMBINER_IRQ(19, 2)
-
-#define EXYNOS4_IRQ_TMU_TRIG0           COMBINER_IRQ(2, 4)
-#define EXYNOS4_IRQ_TMU_TRIG1           COMBINER_IRQ(3, 4)
-
-#define EXYNOS4_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(4, 0)
-#define EXYNOS4_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(4, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC0_0      COMBINER_IRQ(4, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC1_0      COMBINER_IRQ(4, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC2_0      COMBINER_IRQ(4, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC3_0      COMBINER_IRQ(4, 5)
-#define EXYNOS4_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 6)
-#define EXYNOS4_IRQ_SYSMMU_2D_0         COMBINER_IRQ(4, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(5, 0)
-#define EXYNOS4_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(5, 1)
-#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0    COMBINER_IRQ(5, 2)
-#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0    COMBINER_IRQ(5, 3)
-#define EXYNOS4_IRQ_SYSMMU_TV_M0_0      COMBINER_IRQ(5, 4)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0     COMBINER_IRQ(5, 5)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0     COMBINER_IRQ(5, 6)
-#define EXYNOS4_IRQ_SYSMMU_PCIE_0       COMBINER_IRQ(5, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0   COMBINER_IRQ(16, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0   COMBINER_IRQ(16, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0    COMBINER_IRQ(16, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0    COMBINER_IRQ(16, 5)
-
-#define EXYNOS4_IRQ_FIMD0_FIFO          COMBINER_IRQ(11, 0)
-#define EXYNOS4_IRQ_FIMD0_VSYNC         COMBINER_IRQ(11, 1)
-#define EXYNOS4_IRQ_FIMD0_SYSTEM        COMBINER_IRQ(11, 2)
-
-#define EXYNOS4210_MAX_COMBINER_NR      16
-#define EXYNOS4212_MAX_COMBINER_NR      18
-#define EXYNOS4412_MAX_COMBINER_NR      20
-#define EXYNOS4_MAX_COMBINER_NR         EXYNOS4412_MAX_COMBINER_NR
-
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS     16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS     9
-
-/*
- * For Compatibility:
- * the default is for EXYNOS4, and
- * for exynos5, should be re-mapped at function
- */
-
-#define IRQ_TIMER0_VIC                  EXYNOS4_IRQ_TIMER0_VIC
-#define IRQ_TIMER1_VIC                  EXYNOS4_IRQ_TIMER1_VIC
-#define IRQ_TIMER2_VIC                  EXYNOS4_IRQ_TIMER2_VIC
-#define IRQ_TIMER3_VIC                  EXYNOS4_IRQ_TIMER3_VIC
-#define IRQ_TIMER4_VIC                  EXYNOS4_IRQ_TIMER4_VIC
-
-#define IRQ_WDT                         EXYNOS4_IRQ_WDT
-#define IRQ_RTC_ALARM                   EXYNOS4_IRQ_RTC_ALARM
-#define IRQ_RTC_TIC                     EXYNOS4_IRQ_RTC_TIC
-#define IRQ_GPIO_XB                     EXYNOS4_IRQ_GPIO_XB
-#define IRQ_GPIO_XA                     EXYNOS4_IRQ_GPIO_XA
-
-#define IRQ_IIC                         EXYNOS4_IRQ_IIC
-#define IRQ_IIC1                        EXYNOS4_IRQ_IIC1
-#define IRQ_IIC3                        EXYNOS4_IRQ_IIC3
-#define IRQ_IIC5                        EXYNOS4_IRQ_IIC5
-#define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
-#define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
-
-#define IRQ_SPI0                        EXYNOS4_IRQ_SPI0
-#define IRQ_SPI1                        EXYNOS4_IRQ_SPI1
-#define IRQ_SPI2                        EXYNOS4_IRQ_SPI2
-
-#define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
-#define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
-
-#define IRQ_HSMMC0                      EXYNOS4_IRQ_HSMMC0
-#define IRQ_HSMMC1                      EXYNOS4_IRQ_HSMMC1
-#define IRQ_HSMMC2                      EXYNOS4_IRQ_HSMMC2
-#define IRQ_HSMMC3                      EXYNOS4_IRQ_HSMMC3
-
-#define IRQ_MIPI_CSIS0                  EXYNOS4_IRQ_MIPI_CSIS0
-
-#define IRQ_ONENAND_AUDI                EXYNOS4_IRQ_ONENAND_AUDI
-
-#define IRQ_FIMC0                       EXYNOS4_IRQ_FIMC0
-#define IRQ_FIMC1                       EXYNOS4_IRQ_FIMC1
-#define IRQ_FIMC2                       EXYNOS4_IRQ_FIMC2
-#define IRQ_FIMC3                       EXYNOS4_IRQ_FIMC3
-#define IRQ_JPEG                        EXYNOS4_IRQ_JPEG
-#define IRQ_2D                          EXYNOS4_IRQ_2D
-
-#define IRQ_MIXER                       EXYNOS4_IRQ_MIXER
-#define IRQ_HDMI                        EXYNOS4_IRQ_HDMI
-#define IRQ_IIC_HDMIPHY                 EXYNOS4_IRQ_IIC_HDMIPHY
-#define IRQ_MFC                         EXYNOS4_IRQ_MFC
-#define IRQ_SDO                         EXYNOS4_IRQ_SDO
-
-#define IRQ_I2S0                        EXYNOS4_IRQ_I2S0
-
-#define IRQ_ADC                         EXYNOS4_IRQ_ADC0
-#define IRQ_TC                          EXYNOS4_IRQ_PEN0
-
-#define IRQ_KEYPAD                      EXYNOS4_IRQ_KEYPAD
-
-#define IRQ_FIMD0_FIFO                  EXYNOS4_IRQ_FIMD0_FIFO
-#define IRQ_FIMD0_VSYNC                 EXYNOS4_IRQ_FIMD0_VSYNC
-#define IRQ_FIMD0_SYSTEM                EXYNOS4_IRQ_FIMD0_SYSTEM
-
-#define IRQ_GPIO1_NR_GROUPS             EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS             EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
-/* For EXYNOS5 SoCs */
-
-#define EXYNOS5_IRQ_MDMA0               IRQ_SPI(33)
-#define EXYNOS5_IRQ_PDMA0               IRQ_SPI(34)
-#define EXYNOS5_IRQ_PDMA1               IRQ_SPI(35)
-#define EXYNOS5_IRQ_TIMER0_VIC          IRQ_SPI(36)
-#define EXYNOS5_IRQ_TIMER1_VIC          IRQ_SPI(37)
-#define EXYNOS5_IRQ_TIMER2_VIC          IRQ_SPI(38)
-#define EXYNOS5_IRQ_TIMER3_VIC          IRQ_SPI(39)
-#define EXYNOS5_IRQ_TIMER4_VIC          IRQ_SPI(40)
-#define EXYNOS5_IRQ_RTIC                IRQ_SPI(41)
-#define EXYNOS5_IRQ_WDT                 IRQ_SPI(42)
-#define EXYNOS5_IRQ_RTC_ALARM           IRQ_SPI(43)
-#define EXYNOS5_IRQ_RTC_TIC             IRQ_SPI(44)
-#define EXYNOS5_IRQ_GPIO_XB             IRQ_SPI(45)
-#define EXYNOS5_IRQ_GPIO_XA             IRQ_SPI(46)
-#define EXYNOS5_IRQ_GPIO                IRQ_SPI(47)
-#define EXYNOS5_IRQ_IEM_IEC             IRQ_SPI(48)
-#define EXYNOS5_IRQ_IEM_APC             IRQ_SPI(49)
-#define EXYNOS5_IRQ_GPIO_C2C            IRQ_SPI(50)
-#define EXYNOS5_IRQ_IIC                 IRQ_SPI(56)
-#define EXYNOS5_IRQ_IIC1                IRQ_SPI(57)
-#define EXYNOS5_IRQ_IIC2                IRQ_SPI(58)
-#define EXYNOS5_IRQ_IIC3                IRQ_SPI(59)
-#define EXYNOS5_IRQ_IIC4                IRQ_SPI(60)
-#define EXYNOS5_IRQ_IIC5                IRQ_SPI(61)
-#define EXYNOS5_IRQ_IIC6                IRQ_SPI(62)
-#define EXYNOS5_IRQ_IIC7                IRQ_SPI(63)
-#define EXYNOS5_IRQ_IIC_HDMIPHY         IRQ_SPI(64)
-#define EXYNOS5_IRQ_TMU                 IRQ_SPI(65)
-#define EXYNOS5_IRQ_FIQ_0               IRQ_SPI(66)
-#define EXYNOS5_IRQ_FIQ_1               IRQ_SPI(67)
-#define EXYNOS5_IRQ_SPI0                IRQ_SPI(68)
-#define EXYNOS5_IRQ_SPI1                IRQ_SPI(69)
-#define EXYNOS5_IRQ_SPI2                IRQ_SPI(70)
-#define EXYNOS5_IRQ_USB_HOST            IRQ_SPI(71)
-#define EXYNOS5_IRQ_USB3_DRD            IRQ_SPI(72)
-#define EXYNOS5_IRQ_MIPI_HSI            IRQ_SPI(73)
-#define EXYNOS5_IRQ_USB_HSOTG           IRQ_SPI(74)
-#define EXYNOS5_IRQ_HSMMC0              IRQ_SPI(75)
-#define EXYNOS5_IRQ_HSMMC1              IRQ_SPI(76)
-#define EXYNOS5_IRQ_HSMMC2              IRQ_SPI(77)
-#define EXYNOS5_IRQ_HSMMC3              IRQ_SPI(78)
-#define EXYNOS5_IRQ_MIPICSI0            IRQ_SPI(79)
-#define EXYNOS5_IRQ_MIPICSI1            IRQ_SPI(80)
-#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT   IRQ_SPI(81)
-#define EXYNOS5_IRQ_MIPIDSI0            IRQ_SPI(82)
-#define EXYNOS5_IRQ_WDT_IOP             IRQ_SPI(83)
-#define EXYNOS5_IRQ_ROTATOR             IRQ_SPI(84)
-#define EXYNOS5_IRQ_GSC0                IRQ_SPI(85)
-#define EXYNOS5_IRQ_GSC1                IRQ_SPI(86)
-#define EXYNOS5_IRQ_GSC2                IRQ_SPI(87)
-#define EXYNOS5_IRQ_GSC3                IRQ_SPI(88)
-#define EXYNOS5_IRQ_JPEG                IRQ_SPI(89)
-#define EXYNOS5_IRQ_EFNFCON_DMA         IRQ_SPI(90)
-#define EXYNOS5_IRQ_2D                  IRQ_SPI(91)
-#define EXYNOS5_IRQ_EFNFCON_0           IRQ_SPI(92)
-#define EXYNOS5_IRQ_EFNFCON_1           IRQ_SPI(93)
-#define EXYNOS5_IRQ_MIXER               IRQ_SPI(94)
-#define EXYNOS5_IRQ_HDMI                IRQ_SPI(95)
-#define EXYNOS5_IRQ_MFC                 IRQ_SPI(96)
-#define EXYNOS5_IRQ_AUDIO_SS            IRQ_SPI(97)
-#define EXYNOS5_IRQ_I2S0                IRQ_SPI(98)
-#define EXYNOS5_IRQ_I2S1                IRQ_SPI(99)
-#define EXYNOS5_IRQ_I2S2                IRQ_SPI(100)
-#define EXYNOS5_IRQ_AC97                IRQ_SPI(101)
-#define EXYNOS5_IRQ_PCM0                IRQ_SPI(102)
-#define EXYNOS5_IRQ_PCM1                IRQ_SPI(103)
-#define EXYNOS5_IRQ_PCM2                IRQ_SPI(104)
-#define EXYNOS5_IRQ_SPDIF               IRQ_SPI(105)
-#define EXYNOS5_IRQ_ADC0                IRQ_SPI(106)
-#define EXYNOS5_IRQ_ADC1                IRQ_SPI(107)
-#define EXYNOS5_IRQ_SATA_PHY            IRQ_SPI(108)
-#define EXYNOS5_IRQ_SATA_PMEMREQ        IRQ_SPI(109)
-#define EXYNOS5_IRQ_CAM_C               IRQ_SPI(110)
-#define EXYNOS5_IRQ_EAGLE_PMU           IRQ_SPI(111)
-#define EXYNOS5_IRQ_INTFEEDCTRL_SSS     IRQ_SPI(112)
-#define EXYNOS5_IRQ_DP1_INTP1           IRQ_SPI(113)
-#define EXYNOS5_IRQ_CEC                 IRQ_SPI(114)
-#define EXYNOS5_IRQ_SATA                IRQ_SPI(115)
-
-#define EXYNOS5_IRQ_MMC44               IRQ_SPI(123)
-#define EXYNOS5_IRQ_MDMA1               IRQ_SPI(124)
-#define EXYNOS5_IRQ_FIMC_LITE0          IRQ_SPI(125)
-#define EXYNOS5_IRQ_FIMC_LITE1          IRQ_SPI(126)
-#define EXYNOS5_IRQ_RP_TIMER            IRQ_SPI(127)
-
-/* EXYNOS5440 */
-
-#define EXYNOS5440_IRQ_UART0            IRQ_SPI(2)
-#define EXYNOS5440_IRQ_UART1            IRQ_SPI(3)
-
-#define EXYNOS5_IRQ_PMU                 COMBINER_IRQ(1, 2)
-
-#define EXYNOS5_IRQ_SYSMMU_GSC0_0       COMBINER_IRQ(2, 0)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_1       COMBINER_IRQ(2, 1)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_0       COMBINER_IRQ(2, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_1       COMBINER_IRQ(2, 3)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_0       COMBINER_IRQ(2, 4)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_1       COMBINER_IRQ(2, 5)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_0       COMBINER_IRQ(2, 6)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_1       COMBINER_IRQ(2, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_LITE2_0      COMBINER_IRQ(3, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_1      COMBINER_IRQ(3, 1)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_0      COMBINER_IRQ(3, 2)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_1      COMBINER_IRQ(3, 3)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_0      COMBINER_IRQ(3, 4)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_1      COMBINER_IRQ(3, 5)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0    COMBINER_IRQ(4, 0)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1    COMBINER_IRQ(4, 1)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_0       COMBINER_IRQ(4, 2)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_1       COMBINER_IRQ(4, 3)
-
-#define EXYNOS5_IRQ_SYSMMU_FD_0         COMBINER_IRQ(5, 0)
-#define EXYNOS5_IRQ_SYSMMU_FD_1         COMBINER_IRQ(5, 1)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_0     COMBINER_IRQ(5, 4)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_1     COMBINER_IRQ(5, 5)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_0       COMBINER_IRQ(5, 6)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_1       COMBINER_IRQ(5, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ARM_0        COMBINER_IRQ(6, 0)
-#define EXYNOS5_IRQ_SYSMMU_ARM_1        COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0      COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1      COMBINER_IRQ(6, 3)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_0       COMBINER_IRQ(6, 4)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_1       COMBINER_IRQ(6, 5)
-#define EXYNOS5_IRQ_SYSMMU_SSS_0        COMBINER_IRQ(6, 6)
-#define EXYNOS5_IRQ_SYSMMU_SSS_1        COMBINER_IRQ(6, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_0      COMBINER_IRQ(7, 0)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_1      COMBINER_IRQ(7, 1)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_0      COMBINER_IRQ(7, 2)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_1      COMBINER_IRQ(7, 3)
-#define EXYNOS5_IRQ_SYSMMU_TV_0         COMBINER_IRQ(7, 4)
-#define EXYNOS5_IRQ_SYSMMU_TV_1         COMBINER_IRQ(7, 5)
-
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0      COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1      COMBINER_IRQ(8, 6)
-
-#define EXYNOS5_IRQ_SYSMMU_DIS1_0       COMBINER_IRQ(9, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_1       COMBINER_IRQ(9, 5)
-
-#define EXYNOS5_IRQ_DP                  COMBINER_IRQ(10, 3)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_0       COMBINER_IRQ(10, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_1       COMBINER_IRQ(10, 5)
-#define EXYNOS5_IRQ_SYSMMU_ISP_0        COMBINER_IRQ(10, 6)
-#define EXYNOS5_IRQ_SYSMMU_ISP_1        COMBINER_IRQ(10, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ODC_0        COMBINER_IRQ(11, 0)
-#define EXYNOS5_IRQ_SYSMMU_ODC_1        COMBINER_IRQ(11, 1)
-#define EXYNOS5_IRQ_SYSMMU_DRC_0        COMBINER_IRQ(11, 6)
-#define EXYNOS5_IRQ_SYSMMU_DRC_1        COMBINER_IRQ(11, 7)
-
-#define EXYNOS5_IRQ_MDMA1_ABORT         COMBINER_IRQ(13, 1)
-
-#define EXYNOS5_IRQ_MDMA0_ABORT         COMBINER_IRQ(15, 3)
-
-#define EXYNOS5_IRQ_FIMD1_FIFO          COMBINER_IRQ(18, 4)
-#define EXYNOS5_IRQ_FIMD1_VSYNC         COMBINER_IRQ(18, 5)
-#define EXYNOS5_IRQ_FIMD1_SYSTEM        COMBINER_IRQ(18, 6)
-
-#define EXYNOS5_IRQ_ARMIOP_GIC          COMBINER_IRQ(19, 0)
-#define EXYNOS5_IRQ_ARMISP_GIC          COMBINER_IRQ(19, 1)
-#define EXYNOS5_IRQ_IOP_GIC             COMBINER_IRQ(19, 3)
-#define EXYNOS5_IRQ_ISP_GIC             COMBINER_IRQ(19, 4)
-
-#define EXYNOS5_IRQ_PMU_CPU1            COMBINER_IRQ(22, 4)
-
-#define EXYNOS5_IRQ_EINT0               COMBINER_IRQ(23, 0)
-
-#define EXYNOS5_IRQ_EINT1               COMBINER_IRQ(24, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_0      COMBINER_IRQ(24, 1)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_1      COMBINER_IRQ(24, 2)
-#define EXYNOS5_IRQ_SYSMMU_2D_0         COMBINER_IRQ(24, 5)
-#define EXYNOS5_IRQ_SYSMMU_2D_1         COMBINER_IRQ(24, 6)
-
-#define EXYNOS5_IRQ_EINT2               COMBINER_IRQ(25, 0)
-#define EXYNOS5_IRQ_EINT3               COMBINER_IRQ(25, 1)
-
-#define EXYNOS5_IRQ_EINT4               COMBINER_IRQ(26, 0)
-#define EXYNOS5_IRQ_EINT5               COMBINER_IRQ(26, 1)
-
-#define EXYNOS5_IRQ_EINT6               COMBINER_IRQ(27, 0)
-#define EXYNOS5_IRQ_EINT7               COMBINER_IRQ(27, 1)
-
-#define EXYNOS5_IRQ_EINT8               COMBINER_IRQ(28, 0)
-#define EXYNOS5_IRQ_EINT9               COMBINER_IRQ(28, 1)
-
-#define EXYNOS5_IRQ_EINT10              COMBINER_IRQ(29, 0)
-#define EXYNOS5_IRQ_EINT11              COMBINER_IRQ(29, 1)
-
-#define EXYNOS5_IRQ_EINT12              COMBINER_IRQ(30, 0)
-#define EXYNOS5_IRQ_EINT13              COMBINER_IRQ(30, 1)
-
-#define EXYNOS5_IRQ_EINT14              COMBINER_IRQ(31, 0)
-#define EXYNOS5_IRQ_EINT15              COMBINER_IRQ(31, 1)
-
-#define EXYNOS5_MAX_COMBINER_NR         32
-
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS     14
-#define EXYNOS5_IRQ_GPIO2_NR_GROUPS     9
-#define EXYNOS5_IRQ_GPIO3_NR_GROUPS     5
-#define EXYNOS5_IRQ_GPIO4_NR_GROUPS     1
-
-#define MAX_COMBINER_NR                 (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
-                                        EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
-
-#define S5P_EINT_BASE1                  COMBINER_IRQ(MAX_COMBINER_NR, 0)
-#define S5P_EINT_BASE2                  (S5P_EINT_BASE1 + 16)
-#define S5P_GPIOINT_BASE                (S5P_EINT_BASE1 + 32)
-#define IRQ_GPIO_END                    (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE                  (IRQ_GPIO_END + 64)
-
-/* Set the default NR_IRQS */
-#define EXYNOS_NR_IRQS                  (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-
-#ifndef CONFIG_SPARSE_IRQ
-#define NR_IRQS                         EXYNOS_NR_IRQS
-#endif
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
 #define EXYNOS4x12_PA_SYSRAM_NS         0x0204F000
 #define EXYNOS5250_PA_SYSRAM_NS         0x0204F000
 
-#define EXYNOS4_PA_FIMC0                0x11800000
-#define EXYNOS4_PA_FIMC1                0x11810000
-#define EXYNOS4_PA_FIMC2                0x11820000
-#define EXYNOS4_PA_FIMC3                0x11830000
-
-#define EXYNOS4_PA_JPEG                 0x11840000
-
-/* x = 0...1 */
-#define EXYNOS4_PA_FIMC_LITE(x)         (0x12390000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_G2D                  0x12800000
-
-#define EXYNOS4_PA_I2S0                 0x03830000
-#define EXYNOS4_PA_I2S1                 0xE3100000
-#define EXYNOS4_PA_I2S2                 0xE2A00000
-
-#define EXYNOS4_PA_PCM0                 0x03840000
-#define EXYNOS4_PA_PCM1                 0x13980000
-#define EXYNOS4_PA_PCM2                 0x13990000
-
-#define EXYNOS4_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-
-#define EXYNOS4_PA_ONENAND              0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA          0x0C600000
-
 #define EXYNOS_PA_CHIPID                0x10000000
 
 #define EXYNOS4_PA_SYSCON               0x10010000
@@ -71,10 +46,6 @@
 #define EXYNOS4_PA_WATCHDOG             0x10060000
 #define EXYNOS5_PA_WATCHDOG             0x101D0000
 
-#define EXYNOS4_PA_RTC                  0x10070000
-
-#define EXYNOS4_PA_KEYPAD               0x100A0000
-
 #define EXYNOS4_PA_DMC0                 0x10400000
 #define EXYNOS4_PA_DMC1                 0x10410000
 
@@ -87,207 +58,22 @@
 #define EXYNOS5_PA_GIC_DIST             0x10481000
 
 #define EXYNOS4_PA_COREPERI             0x10500000
-#define EXYNOS4_PA_TWD                  0x10500600
 #define EXYNOS4_PA_L2CC                 0x10502000
 
-#define EXYNOS4_PA_TMU                  0x100C0000
-
-#define EXYNOS4_PA_MDMA0                0x10810000
-#define EXYNOS4_PA_MDMA1                0x12850000
-#define EXYNOS4_PA_S_MDMA1              0x12840000
-#define EXYNOS4_PA_PDMA0                0x12680000
-#define EXYNOS4_PA_PDMA1                0x12690000
-#define EXYNOS5_PA_MDMA0                0x10800000
-#define EXYNOS5_PA_MDMA1                0x11C10000
-#define EXYNOS5_PA_PDMA0                0x121A0000
-#define EXYNOS5_PA_PDMA1                0x121B0000
-
-#define EXYNOS4_PA_SYSMMU_MDMA          0x10A40000
-#define EXYNOS4_PA_SYSMMU_2D_ACP        0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0         0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1         0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2         0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3         0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG          0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0         0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1         0x12220000
-#define EXYNOS4_PA_SYSMMU_FIMC_ISP      0x12260000
-#define EXYNOS4_PA_SYSMMU_FIMC_DRC      0x12270000
-#define EXYNOS4_PA_SYSMMU_FIMC_FD       0x122A0000
-#define EXYNOS4_PA_SYSMMU_ISPCPU        0x122B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE0    0x123B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE1    0x123C0000
-#define EXYNOS4_PA_SYSMMU_PCIe          0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D           0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR       0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2         0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV            0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
-
-#define EXYNOS5_PA_GSC0                 0x13E00000
-#define EXYNOS5_PA_GSC1                 0x13E10000
-#define EXYNOS5_PA_GSC2                 0x13E20000
-#define EXYNOS5_PA_GSC3                 0x13E30000
-
-#define EXYNOS5_PA_SYSMMU_MDMA1         0x10A40000
-#define EXYNOS5_PA_SYSMMU_SSS           0x10A50000
-#define EXYNOS5_PA_SYSMMU_2D            0x10A60000
-#define EXYNOS5_PA_SYSMMU_MFC_L         0x11200000
-#define EXYNOS5_PA_SYSMMU_MFC_R         0x11210000
-#define EXYNOS5_PA_SYSMMU_ROTATOR       0x11D40000
-#define EXYNOS5_PA_SYSMMU_MDMA2         0x11D50000
-#define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
-#define EXYNOS5_PA_SYSMMU_IOP           0x12360000
-#define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_ISP           0x13260000
-#define EXYNOS5_PA_SYSMMU_DRC           0x12370000
-#define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
-#define EXYNOS5_PA_SYSMMU_SCALERP       0x13290000
-#define EXYNOS5_PA_SYSMMU_FD            0x132A0000
-#define EXYNOS5_PA_SYSMMU_ISPCPU        0x132B0000
-#define EXYNOS5_PA_SYSMMU_ODC           0x132C0000
-#define EXYNOS5_PA_SYSMMU_DIS0          0x132D0000
-#define EXYNOS5_PA_SYSMMU_DIS1          0x132E0000
-#define EXYNOS5_PA_SYSMMU_3DNR          0x132F0000
-#define EXYNOS5_PA_SYSMMU_LITE0         0x13C40000
-#define EXYNOS5_PA_SYSMMU_LITE1         0x13C50000
-#define EXYNOS5_PA_SYSMMU_GSC0          0x13E80000
-#define EXYNOS5_PA_SYSMMU_GSC1          0x13E90000
-#define EXYNOS5_PA_SYSMMU_GSC2          0x13EA0000
-#define EXYNOS5_PA_SYSMMU_GSC3          0x13EB0000
-#define EXYNOS5_PA_SYSMMU_FIMD1         0x14640000
-#define EXYNOS5_PA_SYSMMU_TV            0x14650000
-
-#define EXYNOS4_PA_SPI0                 0x13920000
-#define EXYNOS4_PA_SPI1                 0x13930000
-#define EXYNOS4_PA_SPI2                 0x13940000
-#define EXYNOS5_PA_SPI0                 0x12D20000
-#define EXYNOS5_PA_SPI1                 0x12D30000
-#define EXYNOS5_PA_SPI2                 0x12D40000
-
-#define EXYNOS4_PA_GPIO1                0x11400000
-#define EXYNOS4_PA_GPIO2                0x11000000
-#define EXYNOS4_PA_GPIO3                0x03860000
-#define EXYNOS5_PA_GPIO1                0x11400000
-#define EXYNOS5_PA_GPIO2                0x13400000
-#define EXYNOS5_PA_GPIO3                0x10D10000
-#define EXYNOS5_PA_GPIO4                0x03860000
-
-#define EXYNOS4_PA_MIPI_CSIS0           0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1           0x11890000
-
-#define EXYNOS4_PA_FIMD0                0x11C00000
-
-#define EXYNOS4_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI                0x12550000
-#define EXYNOS5_PA_DWMCI0               0x12200000
-#define EXYNOS5_PA_DWMCI1               0x12210000
-#define EXYNOS5_PA_DWMCI2               0x12220000
-#define EXYNOS5_PA_DWMCI3               0x12230000
-
-#define EXYNOS4_PA_HSOTG                0x12480000
-#define EXYNOS4_PA_USB_HSPHY            0x125B0000
-
-#define EXYNOS4_PA_SATA                 0x12560000
-#define EXYNOS4_PA_SATAPHY              0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL         0x126B0000
-
 #define EXYNOS4_PA_SROMC                0x12570000
 #define EXYNOS5_PA_SROMC                0x12250000
 
-#define EXYNOS4_PA_EHCI                 0x12580000
-#define EXYNOS4_PA_OHCI                 0x12590000
 #define EXYNOS4_PA_HSPHY                0x125B0000
-#define EXYNOS4_PA_MFC                  0x13400000
 
 #define EXYNOS4_PA_UART                 0x13800000
 #define EXYNOS5_PA_UART                 0x12C00000
 
-#define EXYNOS4_PA_VP                   0x12C00000
-#define EXYNOS4_PA_MIXER                0x12C10000
-#define EXYNOS4_PA_SDO                  0x12C20000
-#define EXYNOS4_PA_HDMI                 0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY          0x138E0000
-
-#define EXYNOS4_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-#define EXYNOS5_PA_IIC(x)               (0x12C60000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_ADC                  0x13910000
-#define EXYNOS4_PA_ADC1                 0x13911000
-
-#define EXYNOS4_PA_AC97                 0x139A0000
-
-#define EXYNOS4_PA_SPDIF                0x139B0000
-
 #define EXYNOS4_PA_TIMER                0x139D0000
 #define EXYNOS5_PA_TIMER                0x12DD0000
 
-#define EXYNOS4_PA_SDRAM                0x40000000
-#define EXYNOS5_PA_SDRAM                0x40000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0                   EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1                   EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2                   EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3                   EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC                      EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1                     EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2                     EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3                     EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4                     EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5                     EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6                     EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7                     EXYNOS4_PA_IIC(7)
-#define S3C_PA_RTC                      EXYNOS4_PA_RTC
-#define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
-#define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
-#define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
-#define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
-#define S3C_PA_USB_HSOTG                EXYNOS4_PA_HSOTG
-
-#define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
-#define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2                    EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3                    EXYNOS4_PA_FIMC3
-#define S5P_PA_JPEG                     EXYNOS4_PA_JPEG
-#define S5P_PA_G2D                      EXYNOS4_PA_G2D
-#define S5P_PA_FIMD0                    EXYNOS4_PA_FIMD0
-#define S5P_PA_HDMI                     EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY              EXYNOS4_PA_IIC_HDMIPHY
-#define S5P_PA_MFC                      EXYNOS4_PA_MFC
-#define S5P_PA_MIPI_CSIS0               EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1               EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_MIXER                    EXYNOS4_PA_MIXER
-#define S5P_PA_ONENAND                  EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDO                      EXYNOS4_PA_SDO
-#define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
-#define S5P_PA_VP                       EXYNOS4_PA_VP
-
-#define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
-#define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
-
 /* Compatibility UART */
 
-#define EXYNOS4_PA_UART0                0x13800000
-#define EXYNOS4_PA_UART1                0x13810000
-#define EXYNOS4_PA_UART2                0x13820000
-#define EXYNOS4_PA_UART3                0x13830000
-#define EXYNOS4_SZ_UART                 SZ_256
-
-#define EXYNOS5_PA_UART0                0x12C00000
-#define EXYNOS5_PA_UART1                0x12C10000
-#define EXYNOS5_PA_UART2                0x12C20000
-#define EXYNOS5_PA_UART3                0x12C30000
-
 #define EXYNOS5440_PA_UART0             0x000B0000
-#define EXYNOS5440_PA_UART1             0x000C0000
-#define EXYNOS5440_SZ_UART              SZ_256
 
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 296090e7f423..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
 
 static inline void s3c_pm_arch_prepare_irqs(void)
 {
-        u32 eintmask = s3c_irqwake_eintmask;
-
-        if (of_have_populated_dt())
-                eintmask = exynos_get_eint_wake_mask();
-
-        __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
+        __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
         __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
 }
 
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
         /* nothing here yet */
 }
 
+/* Compatibility definitions to make plat-samsung/pm.c compile */
+#define IRQ_EINT_BIT(x)         1
+#define s3c_irqwake_intallow    0
+#define s3c_irqwake_eintallow   0
+
 #endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#define EINT_REG_NR(x)                  (EINT_OFFSET(x) >> 3)
-#define EINT_CON(b, x)                  (b + 0xE00 + (EINT_REG_NR(x) * 4))
-#define EINT_FLTCON(b, x)               (b + 0xE80 + (EINT_REG_NR(x) * 4))
-#define EINT_MASK(b, x)                 (b + 0xF00 + (EINT_REG_NR(x) * 4))
-#define EINT_PEND(b, x)                 (b + 0xF40 + (EINT_REG_NR(x) * 4))
-
-#define EINT_OFFSET_BIT(x)              (1 << (EINT_OFFSET(x) & 0x7))
-
-/* compatibility for plat-s5p/irq-pm.c */
-#define EXYNOS4_EINT40CON               (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x)                 (EXYNOS4_EINT40CON + ((x) * 0x4))
-
-#define EXYNOS4_EINT40FLTCON0           (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x)              (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
-
-#define EXYNOS4_EINT40MASK              (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x)                (EXYNOS4_EINT40MASK + ((x) * 0x4))
-
-#define EXYNOS4_EINT40PEND              (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x)                (EXYNOS4_EINT40PEND + ((x) * 0x4))
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-
-#define EXYNOS4_HSOTG_PHYREG(x)         ((x) + S3C_VA_USB_HSPHY)
-
-#define EXYNOS4_PHYPWR                  EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK           (0xf << 9)
-#define PHY1_HSIC1_SLEEP                (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND        (1 << 11)
-#define PHY1_HSIC0_SLEEP                (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND        (1 << 9)
-
-#define PHY1_STD_NORMAL_MASK            (0x7 << 6)
-#define PHY1_STD_SLEEP                  (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN       (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND          (1 << 6)
-
-#define PHY0_NORMAL_MASK                (0x39 << 0)
-#define PHY0_SLEEP                      (1 << 5)
-#define PHY0_OTG_DISABLE                (1 << 4)
-#define PHY0_ANALOG_POWERDOWN           (1 << 3)
-#define PHY0_FORCE_SUSPEND              (1 << 0)
-
-#define EXYNOS4_PHYCLK                  EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N                (1 << 7)
-#define PHY0_COMMON_ON_N                (1 << 4)
-#define PHY0_ID_PULLUP                  (1 << 2)
-
-#define EXYNOS4_CLKSEL_SHIFT            (0)
-
-#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
-#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
-#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
-
-#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
-#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
-#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
-#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
-#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
-#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
-
-#define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
-#define HOST_LINK_PORT2_SWRST           (1 << 9)
-#define HOST_LINK_PORT1_SWRST           (1 << 8)
-#define HOST_LINK_PORT0_SWRST           (1 << 7)
-#define HOST_LINK_ALL_SWRST             (1 << 6)
-
-#define PHY1_SWRST_MASK                 (0x7 << 3)
-#define PHY1_HSIC_SWRST                 (1 << 5)
-#define PHY1_STD_SWRST                  (1 << 4)
-#define PHY1_ALL_SWRST                  (1 << 3)
-
-#define PHY0_SWRST_MASK                 (0x7 << 0)
-#define PHY0_PHYLINK_SWRST              (1 << 2)
-#define PHY0_HLINK_SWRST                (1 << 1)
-#define PHY0_SWRST                      (1 << 0)
-
-#define EXYNOS4_PHY1CON                 EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN                       (1 << 0)
-
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos/include/mach/uncompress.h b/arch/arm/mach-exynos/include/mach/uncompress.h
index 2979995d5a6a..5d7ce36be46f 100644
--- a/arch/arm/mach-exynos/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos/include/mach/uncompress.h
@@ -15,9 +15,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/map.h>
-
-volatile u8 *uart_base;
-
 #include <plat/uncompress.h>
 
 static unsigned int __raw_readl(unsigned int ptr)
@@ -31,13 +28,12 @@ static void arch_detect_cpu(void)
 
         /*
          * product_id is bits 31:12
-         *    bits 23:20 describe the exynosX family
-         *
+         * bits 23:20 describe the exynosX family
+         * bits 27:24 describe the exynosX family in exynos5420
          */
         chip_id >>= 20;
-        chip_id &= 0xf;
 
-        if (chip_id == 0x5)
+        if ((chip_id & 0x0f) == 0x5 || (chip_id & 0xf0) == 0x50)
                 uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
         else
                 uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
deleted file mode 100644
index 5f0f55701374..000000000000
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/io.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/smsc911x.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/sdhci.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define ARMLEX4210_ULCON_DEFAULT        S3C2410_LCON_CS8
-
-#define ARMLEX4210_UFCON_DEFAULT        (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ARMLEX4210_UCON_DEFAULT,
-                .ulcon          = ARMLEX4210_ULCON_DEFAULT,
-                .ufcon          = ARMLEX4210_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPX2(5),
-        .ext_cd_gpio_invert     = 1,
-        .max_width              = 4,
-};
-
-static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-        .max_width              = 4,
-};
-
-static void __init armlex4210_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
-        s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
-}
-
-static void __init armlex4210_wlan_init(void)
-{
-        /* enable */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
-
-        /* reset */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
-
-        /* wakeup */
-        s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
-}
-
-static struct resource armlex4210_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(3), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(27), 1, NULL, IORESOURCE_IRQ \
-                                        | IRQF_TRIGGER_HIGH),
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device armlex4210_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(armlex4210_smsc911x_resources),
-        .resource       = armlex4210_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static struct platform_device *armlex4210_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_rtc,
-        &s3c_device_wdt,
-        &armlex4210_smsc911x,
-        &exynos4_device_ahci,
-};
-
-static void __init armlex4210_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-static void __init armlex4210_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(armlex4210_uartcfgs,
-                           ARRAY_SIZE(armlex4210_uartcfgs));
-}
-
-static void __init armlex4210_machine_init(void)
-{
-        armlex4210_smsc911x_init();
-
-        armlex4210_sdhci_init();
-
-        armlex4210_wlan_init();
-
-        platform_add_devices(armlex4210_devices,
-                             ARRAY_SIZE(armlex4210_devices));
-}
-
-MACHINE_START(ARMLEX4210, "ARMLEX4210")
-        /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = armlex4210_map_io,
-        .init_machine   = armlex4210_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index b9ed834a7eee..0099c6c13bba 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -23,11 +23,6 @@
 
 #include "common.h"
 
-static void __init exynos4_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
-
 static void __init exynos4_dt_machine_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -55,8 +50,7 @@ static void __init exynos4_reserve(void)
 DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
         .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = exynos4_dt_map_io,
+        .map_io         = exynos_init_io,
         .init_early     = exynos_firmware_init,
         .init_machine   = exynos4_dt_machine_init,
         .init_late      = exynos_init_late,
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..f874b773ca13 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -23,11 +23,6 @@
 
 #include "common.h"
 
-static void __init exynos5_dt_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-}
-
 static void __init exynos5_dt_machine_init(void)
 {
         struct device_node *i2c_np;
@@ -57,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
 
 static char const *exynos5_dt_compat[] __initdata = {
         "samsung,exynos5250",
+        "samsung,exynos5420",
         "samsung,exynos5440",
         NULL
 };
@@ -76,9 +72,8 @@ static void __init exynos5_reserve(void)
 
 DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .init_irq       = exynos5_init_irq,
         .smp            = smp_ops(exynos_smp_ops),
-        .map_io         = exynos5_dt_map_io,
+        .map_io         = exynos_init_io,
         .init_machine   = exynos5_dt_machine_init,
         .init_late      = exynos_init_late,
         .init_time      = exynos_init_time,
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
deleted file mode 100644
index 5c8b2878dbbd..000000000000
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ /dev/null
@@ -1,1388 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-nuri.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/i2c-gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/power/max8903_charger.h>
-#include <linux/power/max17042_battery.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mfd/max8997-private.h>
-#include <linux/mmc/host.h>
-#include <linux/fb.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <drm/exynos_drm.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-#include <media/s5p_fimc.h>
-#include <media/v4l2-mediabus.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <plat/adc.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/mfc.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define NURI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define NURI_ULCON_DEFAULT      S3C2410_LCON_CS8
-
-#define NURI_UFCON_DEFAULT      (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC = 0,
-        FIXED_REG_ID_MAX8903,
-        FIXED_REG_ID_CAM_A28V,
-        FIXED_REG_ID_CAM_12V,
-        FIXED_REG_ID_CAM_VT_15V,
-};
-
-static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
-        {
-                .hwport         = 0,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 1,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 2,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-        {
-                .hwport         = 3,
-                .ucon           = NURI_UCON_DEFAULT,
-                .ulcon          = NURI_ULCON_DEFAULT,
-                .ufcon          = NURI_UFCON_DEFAULT,
-        },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_ERASE),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-static struct regulator_consumer_supply emmc_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-        REGULATOR_SUPPLY("vmmc", "dw_mmc"),
-};
-
-static struct regulator_init_data emmc_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(emmc_supplies),
-        .consumer_supplies      = emmc_supplies,
-};
-
-static struct fixed_voltage_config emmc_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN (inverted)",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPL1(1),
-        .enable_high            = false,
-        .init_data              = &emmc_fixed_voltage_init_data,
-};
-
-static struct platform_device emmc_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC,
-        .dev                    = {
-                .platform_data  = &emmc_fixed_voltage_config,
-        },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(3),      /* XEINT_27 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-
-/* WLAN */
-static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init nuri_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
-}
-
-/* GPIO KEYS */
-static struct gpio_keys_button nuri_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_POWER,
-                .gpio                   = EXYNOS4_GPX2(7),      /* XEINT23 */
-                .desc                   = "gpio-keys: KEY_POWER",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data nuri_gpio_keys_data = {
-        .buttons                = nuri_gpio_keys_tables,
-        .nbuttons               = ARRAY_SIZE(nuri_gpio_keys_tables),
-};
-
-static struct platform_device nuri_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &nuri_gpio_keys_data,
-        },
-};
-
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .xres           = 1024,
-                        .yres           = 600,
-                        .hsync_len      = 40,
-                        .left_margin    = 79,
-                        .right_margin   = 200,
-                        .vsync_len      = 10,
-                        .upper_margin   = 10,
-                        .lower_margin   = 11,
-                        .refresh        = 60,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win nuri_fb_win0 = {
-        .max_bpp        = 24,
-        .default_bpp    = 16,
-        .xres           = 1024,
-        .yres           = 600,
-        .virtual_x      = 1024,
-        .virtual_y      = 2 * 600,
-};
-
-static struct fb_videomode nuri_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 1,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-        .refresh        = 60,
-};
-
-static struct s3c_fb_platdata nuri_fb_pdata __initdata = {
-        .win[0]         = &nuri_fb_win0,
-        .vtiming        = &nuri_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
-{
-        int gpio = EXYNOS4_GPE1(5);
-
-        gpio_request(gpio, "LVDS_nSHDN");
-        gpio_direction_output(gpio, power);
-        gpio_free(gpio);
-}
-
-static int nuri_bl_init(struct device *dev)
-{
-        return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
-                                "LCD_LD0_EN");
-}
-
-static int nuri_bl_notify(struct device *dev, int brightness)
-{
-        if (brightness < 1)
-                brightness = 0;
-
-        gpio_set_value(EXYNOS4_GPE2(3), 1);
-
-        return brightness;
-}
-
-static void nuri_bl_exit(struct device *dev)
-{
-        gpio_free(EXYNOS4_GPE2(3));
-}
-
-/* nuri pwm backlight */
-static struct platform_pwm_backlight_data nuri_backlight_data = {
-        .pwm_id                 = 0,
-        .pwm_period_ns          = 30000,
-        .max_brightness         = 100,
-        .dft_brightness         = 50,
-        .init                   = nuri_bl_init,
-        .notify                 = nuri_bl_notify,
-        .exit                   = nuri_bl_exit,
-};
-
-static struct platform_device nuri_backlight_device = {
-        .name                   = "pwm-backlight",
-        .id                     = -1,
-        .dev                    = {
-                .parent         = &s3c_device_timer[0].dev,
-                .platform_data  = &nuri_backlight_data,
-        },
-};
-
-static struct plat_lcd_data nuri_lcd_platform_data = {
-        .set_power              = nuri_lcd_power_on,
-};
-
-static struct platform_device nuri_lcd_device = {
-        .name                   = "platform-lcd",
-        .id                     = -1,
-        .dev                    = {
-                .platform_data  = &nuri_lcd_platform_data,
-        },
-};
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-
-/* TSP */
-static struct mxt_platform_data mxt_platform_data = {
-        .x_line                 = 18,
-        .y_line                 = 11,
-        .x_size                 = 1024,
-        .y_size                 = 600,
-        .blen                   = 0x1,
-        .threshold              = 0x28,
-        .voltage                = 2800000,              /* 2.8V */
-        .orient                 = MXT_DIAGONAL_COUNTER,
-        .irqflags               = IRQF_TRIGGER_FALLING,
-};
-
-static struct s3c2410_platform_i2c i2c3_data __initdata = {
-        .flags          = 0,
-        .bus_num        = 3,
-        .slave_addr     = 0x10,
-        .frequency      = 400 * 1000,
-        .sda_delay      = 100,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
-                .platform_data  = &mxt_platform_data,
-                .irq            = IRQ_EINT(4),
-        },
-};
-
-static void __init nuri_tsp_init(void)
-{
-        int gpio;
-
-        /* TOUCH_INT: XEINT_4 */
-        gpio = EXYNOS4_GPX0(4);
-        gpio_request(gpio, "TOUCH_INT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-}
-
-static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
-        REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
-};
-static struct regulator_consumer_supply nuri_max8997_ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vdd_reg", "6-003c"), /* S5K6AA camera */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
-        REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* USB */
-        REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
-        REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.2"), /* TFLASH */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
-        REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
-};
-static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
-        REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
-        REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
-        REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
-};
-static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
-        REGULATOR_SUPPLY("vdd_int", "exynos4210-busfreq.0"), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
-        REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
-        REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
-        REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
-        REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
-};
-static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
-        REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
-};
-
-static struct regulator_consumer_supply __initdata max8997_charger_[] = {
-        REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
-};
-static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
-        REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
-};
-
-static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
-        REGULATOR_SUPPLY("gps_clk", "bcm4751"),
-        REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
-        REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo1_),
-        .consumer_supplies      = max8997_ldo1_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo3_),
-        .consumer_supplies      = max8997_ldo3_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo4_),
-        .consumer_supplies      = max8997_ldo4_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo5_data = {
-        .constraints    = {
-                .name           = "VHSIC_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo5_),
-        .consumer_supplies      = max8997_ldo5_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V_PDA",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(nuri_max8997_ldo6_consumer),
-        .consumer_supplies      = nuri_max8997_ldo6_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo7_),
-        .consumer_supplies      = max8997_ldo7_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V_C210",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo8_),
-        .consumer_supplies      = max8997_ldo8_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V_PDA",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V_C210",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "LVDS_VDD3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo11_),
-        .consumer_supplies      = max8997_ldo11_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo12_data = {
-        .constraints    = {
-                .name           = "VT_CAM_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo12_),
-        .consumer_supplies      = max8997_ldo12_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo13_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo13_),
-        .consumer_supplies      = max8997_ldo13_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_MOTOR",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo14_),
-        .consumer_supplies      = max8997_ldo14_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo15_data = {
-        .constraints    = {
-                .name           = "VTOUCH_ADVV2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo15_),
-        .consumer_supplies      = max8997_ldo15_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_SENSOR_IO_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo16_),
-        .consumer_supplies      = max8997_ldo16_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo18_data = {
-        .constraints    = {
-                .name           = "VTOUCH_VDD2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_ldo18_),
-        .consumer_supplies      = max8997_ldo18_,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1350000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
-        .consumer_supplies = max8997_buck1_,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
-        .consumer_supplies = max8997_buck2_,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V_C210",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
-        .consumer_supplies = max8997_buck3_,
-};
-
-static struct regulator_init_data __initdata max8997_buck4_data = {
-        .constraints    = {
-                .name           = "CAM_ISP_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
-        .consumer_supplies = max8997_buck4_,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V_C210",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck6_data = {
-        .constraints    = {
-                .name           = "CAM_AF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
-        .consumer_supplies = max8997_buck6_,
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VCC_SUB_2.0V",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
-        .consumer_supplies = max8997_32khz_ap_,
-};
-
-static struct regulator_init_data __initdata max8997_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout1_),
-        .consumer_supplies      = max8997_esafeout1_,
-};
-
-static struct regulator_init_data __initdata max8997_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_esafeout2_),
-        .consumer_supplies      = max8997_esafeout2_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_cv_data = {
-        .constraints    = {
-                .name           = "CHARGER_CV",
-                .min_uV         = 4200000,
-                .max_uV         = 4200000,
-                .apply_uV       = 1,
-        },
-};
-
-static struct regulator_init_data __initdata max8997_charger_data = {
-        .constraints    = {
-                .name           = "CHARGER",
-                .min_uA         = 200000,
-                .max_uA         = 950000,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS |
-                                REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_charger_),
-        .consumer_supplies      = max8997_charger_,
-};
-
-static struct regulator_init_data __initdata max8997_charger_topoff_data = {
-        .constraints    = {
-                .name           = "CHARGER TOPOFF",
-                .min_uA         = 50000,
-                .max_uA         = 200000,
-                .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(max8997_chg_toff_),
-        .consumer_supplies      = max8997_chg_toff_,
-};
-
-static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
-        { MAX8997_LDO1, &max8997_ldo1_data },
-        { MAX8997_LDO2, &max8997_ldo2_data },
-        { MAX8997_LDO3, &max8997_ldo3_data },
-        { MAX8997_LDO4, &max8997_ldo4_data },
-        { MAX8997_LDO5, &max8997_ldo5_data },
-        { MAX8997_LDO6, &max8997_ldo6_data },
-        { MAX8997_LDO7, &max8997_ldo7_data },
-        { MAX8997_LDO8, &max8997_ldo8_data },
-        { MAX8997_LDO9, &max8997_ldo9_data },
-        { MAX8997_LDO10, &max8997_ldo10_data },
-        { MAX8997_LDO11, &max8997_ldo11_data },
-        { MAX8997_LDO12, &max8997_ldo12_data },
-        { MAX8997_LDO13, &max8997_ldo13_data },
-        { MAX8997_LDO14, &max8997_ldo14_data },
-        { MAX8997_LDO15, &max8997_ldo15_data },
-        { MAX8997_LDO16, &max8997_ldo16_data },
-
-        { MAX8997_LDO18, &max8997_ldo18_data },
-        { MAX8997_LDO21, &max8997_ldo21_data },
-
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-        { MAX8997_BUCK4, &max8997_buck4_data },
-        { MAX8997_BUCK5, &max8997_buck5_data },
-        { MAX8997_BUCK6, &max8997_buck6_data },
-        { MAX8997_BUCK7, &max8997_buck7_data },
-
-        { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
-        { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
-
-        { MAX8997_ENVICHG, &max8997_vichg_data },
-        { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
-        { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
-        { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
-        { MAX8997_CHARGER, &max8997_charger_data },
-        { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
-};
-
-static struct max8997_platform_data __initdata nuri_max8997_pdata = {
-        .wakeup                 = 1,
-
-        .num_regulators         = ARRAY_SIZE(nuri_max8997_regulators),
-        .regulators             = nuri_max8997_regulators,
-
-        .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
-
-        .buck1_voltage[0] = 1350000, /* 1.35V */
-        .buck1_voltage[1] = 1300000, /* 1.3V */
-        .buck1_voltage[2] = 1250000, /* 1.25V */
-        .buck1_voltage[3] = 1200000, /* 1.2V */
-        .buck1_voltage[4] = 1150000, /* 1.15V */
-        .buck1_voltage[5] = 1100000, /* 1.1V */
-        .buck1_voltage[6] = 1000000, /* 1.0V */
-        .buck1_voltage[7] = 950000, /* 0.95V */
-
-        .buck2_voltage[0] = 1100000, /* 1.1V */
-        .buck2_voltage[1] = 1000000, /* 1.0V */
-        .buck2_voltage[2] = 950000, /* 0.95V */
-        .buck2_voltage[3] = 900000, /* 0.9V */
-        .buck2_voltage[4] = 1100000, /* 1.1V */
-        .buck2_voltage[5] = 1000000, /* 1.0V */
-        .buck2_voltage[6] = 950000, /* 0.95V */
-        .buck2_voltage[7] = 900000, /* 0.9V */
-
-        .buck5_voltage[0] = 1200000, /* 1.2V */
-        .buck5_voltage[1] = 1200000, /* 1.2V */
-        .buck5_voltage[2] = 1200000, /* 1.2V */
-        .buck5_voltage[3] = 1200000, /* 1.2V */
-        .buck5_voltage[4] = 1200000, /* 1.2V */
-        .buck5_voltage[5] = 1200000, /* 1.2V */
-        .buck5_voltage[6] = 1200000, /* 1.2V */
-        .buck5_voltage[7] = 1200000, /* 1.2V */
-};
-
-/* GPIO I2C 5 (PMIC) */
-enum { I2C5_MAX8997 };
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        [I2C5_MAX8997] = {
-                I2C_BOARD_INFO("max8997", 0xCC >> 1),
-                .platform_data  = &nuri_max8997_pdata,
-        },
-};
-
-static struct max17042_platform_data nuri_battery_platform_data = {
-};
-
-/* GPIO I2C 9 (Fuel Gauge) */
-static struct i2c_gpio_platform_data i2c9_gpio_data = {
-        .sda_pin                = EXYNOS4_GPY4(0),      /* XM0ADDR_8 */
-        .scl_pin                = EXYNOS4_GPY4(1),      /* XM0ADDR_9 */
-};
-static struct platform_device i2c9_gpio = {
-        .name                   = "i2c-gpio",
-        .id                     = 9,
-        .dev                    = {
-                .platform_data  = &i2c9_gpio_data,
-        },
-};
-enum { I2C9_MAX17042};
-static struct i2c_board_info i2c9_devs[] __initdata = {
-        [I2C9_MAX17042] = {
-                I2C_BOARD_INFO("max17042", 0x36),
-                .platform_data = &nuri_battery_platform_data,
-        },
-};
-
-/* MAX8903 Secondary Charger */
-static struct regulator_consumer_supply supplies_max8903[] = {
-        REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
-};
-
-static struct regulator_init_data max8903_charger_en_data = {
-        .constraints = {
-                .name           = "VOUT_CHARGER",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
-        .consumer_supplies = supplies_max8903,
-};
-
-static struct fixed_voltage_config max8903_charger_en = {
-        .supply_name = "VOUT_CHARGER",
-        .microvolts = 5000000, /* Assume 5VDC */
-        .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
-        .enable_high = 0, /* Enable = Low */
-        .enabled_at_boot = 1,
-        .init_data = &max8903_charger_en_data,
-};
-
-static struct platform_device max8903_fixed_reg_dev = {
-        .name = "reg-fixed-voltage",
-        .id = FIXED_REG_ID_MAX8903,
-        .dev = { .platform_data = &max8903_charger_en },
-};
-
-static struct max8903_pdata nuri_max8903 = {
-        /*
-         * cen: don't control with the driver, let it be
-         * controlled by regulator above
-         */
-        .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
-        /* uok, usus: not connected */
-        .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
-        /* flt: vcc_1.8V_pda */
-        .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
-
-        .dc_valid = true,
-        .usb_valid = false, /* USB is not wired to MAX8903 */
-};
-
-static struct platform_device nuri_max8903_device = {
-        .name                   = "max8903-charger",
-        .dev                    = {
-                .platform_data  = &nuri_max8903,
-        },
-};
-
-static void __init nuri_power_init(void)
-{
-        int gpio;
-        int ta_en = 0;
-
-        gpio = EXYNOS4_GPX0(7);
-        gpio_request(gpio, "AP_PMIC_IRQ");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-        gpio = EXYNOS4_GPX2(3);
-        gpio_request(gpio, "FUEL_ALERT");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-
-        gpio = nuri_max8903.dok;
-        gpio_request(gpio, "TA_nCONNECTED");
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-        ta_en = gpio_get_value(gpio) ? 0 : 1;
-
-        gpio = nuri_max8903.chg;
-        gpio_request(gpio, "TA_nCHG");
-        gpio_direction_input(gpio);
-
-        gpio = nuri_max8903.dcm;
-        gpio_request(gpio, "CURR_ADJ");
-        gpio_direction_output(gpio, ta_en);
-}
-
-/* USB EHCI */
-static struct s5p_ehci_platdata nuri_ehci_pdata;
-
-static void __init nuri_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat nuri_hsotg_pdata;
-
-/* CAMERA */
-static struct regulator_consumer_supply cam_vt_cam15_supply =
-        REGULATOR_SUPPLY("vdd_core", "6-003c");
-
-static struct regulator_init_data cam_vt_cam15_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_cam15_supply,
-};
-
-static struct fixed_voltage_config cam_vt_cam15_fixed_voltage_cfg = {
-        .supply_name    = "VT_CAM_1.5V",
-        .microvolts     = 1500000,
-        .gpio           = EXYNOS4_GPE2(2), /* VT_CAM_1.5V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_cam15_reg_init_data,
-};
-
-static struct platform_device cam_vt_cam15_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_15V,
-        .dev = { .platform_data = &cam_vt_cam15_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_vdda_supply[] = {
-        REGULATOR_SUPPLY("vdda", "6-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data cam_vdda_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = ARRAY_SIZE(cam_vdda_supply),
-        .consumer_supplies = cam_vdda_supply,
-};
-
-static struct fixed_voltage_config cam_vdda_fixed_voltage_cfg = {
-        .supply_name    = "CAM_IO_EN",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_IO_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_vdda_reg_init_data,
-};
-
-static struct platform_device cam_vdda_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_A28V,
-        .dev = { .platform_data = &cam_vdda_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply camera_8m_12v_supply =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data cam_8m_12v_reg_init_data = {
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &camera_8m_12v_supply,
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS
-        },
-};
-
-static struct fixed_voltage_config cam_8m_12v_fixed_voltage_cfg = {
-        .supply_name    = "8M_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(5), /* 8M_1.2V_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_8m_12v_reg_init_data,
-};
-
-static struct platform_device cam_8m_12v_fixed_rdev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_12V,
-        .dev = { .platform_data = &cam_8m_12v_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-
-#define GPIO_CAM_MEGA_RST       EXYNOS4_GPY3(7) /* ISP_RESET */
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPL2(5)
-#define GPIO_CAM_VT_NSTBY       EXYNOS4_GPL2(0)
-#define GPIO_CAM_VT_NRST        EXYNOS4_GPL2(1)
-
-static struct s5k6aa_platform_data s5k6aa_pldata = {
-        .mclk_frequency = 24000000UL,
-        .gpio_reset     = { GPIO_CAM_VT_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VT_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-};
-
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3c),
-        .platform_data = &s5k6aa_pldata,
-};
-
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset = GPIO_CAM_MEGA_RST,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data  = &m5mols_platdata,
-};
-
-static struct fimc_source_info nuri_camera_sensors[] = {
-        {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_RISING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .clk_frequency  = 24000000UL,
-                .i2c_bus_num    = 6,
-        }, {
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .clk_frequency  = 24000000UL,
-        },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = nuri_camera_sensors,
-        .num_clients    = ARRAY_SIZE(nuri_camera_sensors),
-};
-
-static struct gpio nuri_camera_gpios[] = {
-        { GPIO_CAM_VT_NSTBY,    GPIOF_OUT_INIT_LOW, "CAM_VGA_NSTBY" },
-        { GPIO_CAM_VT_NRST,     GPIOF_OUT_INIT_LOW, "CAM_VGA_NRST"  },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,           "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_RST,    GPIOF_OUT_INIT_LOW, "CAM_8M_NRST" },
-};
-
-static void __init nuri_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-
-        if (gpio_request_array(nuri_camera_gpios,
-                               ARRAY_SIZE(nuri_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-
-        m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
-        if (m5mols_board_info.irq >= 0)
-                s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
-        else
-                pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
-
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_VT_NRST);
-        gpio_free(GPIO_CAM_VT_NSTBY);
-        gpio_free(GPIO_CAM_MEGA_RST);
-
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A)) {
-                pr_err("%s: Camera port A setup failed\n", __func__);
-                return;
-        }
-        /* Increase drive strength of the sensor clock output */
-        s5p_gpio_set_drvstr(EXYNOS4_GPJ1(3), S5P_GPIO_DRVSTR_LV4);
-}
-
-static struct s3c2410_platform_i2c nuri_i2c6_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-        .bus_num        = 6,
-};
-
-static struct s3c2410_platform_i2c nuri_i2c0_platdata __initdata = {
-        .frequency      = 400000U,
-        .sda_delay      = 200,
-};
-
-/* DEVFREQ controlling memory/bus */
-static struct platform_device exynos4_bus_devfreq = {
-        .name                   = "exynos4210-busfreq",
-};
-
-static struct platform_device *nuri_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s3c_device_i2c5, /* PMIC should initialize first */
-        &s3c_device_i2c0,
-        &s3c_device_i2c6,
-        &emmc_fixed_voltage,
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimd0,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_wdt,
-        &s3c_device_timer[0],
-        &s5p_device_ehci,
-        &s3c_device_i2c3,
-        &i2c9_gpio,
-        &s3c_device_adc,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &s3c_device_rtc,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_fimc_md,
-        &s3c_device_usb_hsotg,
-
-        /* NURI Devices */
-        &nuri_gpio_keys,
-        &nuri_lcd_device,
-        &nuri_backlight_device,
-        &max8903_fixed_reg_dev,
-        &nuri_max8903_device,
-        &cam_vt_cam15_fixed_rdev,
-        &cam_vdda_fixed_rdev,
-        &cam_8m_12v_fixed_rdev,
-        &exynos4_bus_devfreq,
-};
-
-static void __init nuri_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void __init nuri_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init nuri_machine_init(void)
-{
-        nuri_sdhci_init();
-        nuri_tsp_init();
-        nuri_power_init();
-
-        s3c_i2c0_set_platdata(&nuri_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-        s3c_i2c3_set_platdata(&i2c3_data);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-        s3c_i2c5_set_platdata(NULL);
-        i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-        i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
-        i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
-        s3c_i2c6_set_platdata(&nuri_i2c6_platdata);
-
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&nuri_fb_pdata);
-#endif
-
-        nuri_camera_init();
-
-        nuri_ehci_init();
-        s3c_hsotg_set_platdata(&nuri_hsotg_pdata);
-
-        /* Last */
-        platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
-}
-
-MACHINE_START(NURI, "NURI")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = nuri_map_io,
-        .init_machine   = nuri_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &nuri_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
deleted file mode 100644
index 27f03ed5d067..000000000000
--- a/arch/arm/mach-exynos/mach-origen.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-origen.c
- *
- * Copyright (c) 2011 Insignal Co., Ltd.
- *              http://www.insignal.co.kr/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/max8997.h>
-#include <linux/lcd.h>
-#include <linux/rfkill-gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/sdhci.h>
-#include <plat/clock.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/hdmi.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define ORIGEN_ULCON_DEFAULT    S3C2410_LCON_CS8
-
-#define ORIGEN_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = ORIGEN_UCON_DEFAULT,
-                .ulcon          = ORIGEN_ULCON_DEFAULT,
-                .ufcon          = ORIGEN_UFCON_DEFAULT,
-        },
-};
-
-static struct regulator_consumer_supply __initdata ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"), /* MIPI */
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo6_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"), /* MIPI */
-};
-static struct regulator_consumer_supply __initdata ldo7_consumer[] = {
-        REGULATOR_SUPPLY("avdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vdd", "s5p-adc"), /* ADC */
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"), /* HDMI */
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"), /* OTG */
-};
-static struct regulator_consumer_supply __initdata ldo9_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo11_consumer[] = {
-        REGULATOR_SUPPLY("dvdd", "alc5625"), /* Realtek ALC5625 */
-};
-static struct regulator_consumer_supply __initdata ldo14_consumer[] = {
-        REGULATOR_SUPPLY("avdd18", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata ldo17_consumer[] = {
-        REGULATOR_SUPPLY("vdd33", "swb-a31"), /* AR6003 WLAN & CSR 8810 BT */
-};
-static struct regulator_consumer_supply __initdata buck1_consumer[] = {
-        REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck2_consumer[] = {
-        REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
-};
-static struct regulator_consumer_supply __initdata buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdd_g3d", "mali_drm"), /* G3D */
-};
-static struct regulator_consumer_supply __initdata buck7_consumer[] = {
-        REGULATOR_SUPPLY("vcc", "platform-lcd"), /* LCD */
-};
-
-static struct regulator_init_data __initdata max8997_ldo1_data = {
-        .constraints    = {
-                .name           = "VDD_ABB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo2_data  = {
-        .constraints    = {
-                .name           = "VDD_ALIVE_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo3_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo3_consumer),
-        .consumer_supplies      = ldo3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo4_data = {
-        .constraints    = {
-                .name           = "VDD_RTC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo6_data = {
-        .constraints    = {
-                .name           = "VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo6_consumer),
-        .consumer_supplies      = ldo6_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo7_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo7_consumer),
-        .consumer_supplies      = ldo7_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo8_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo8_consumer),
-        .consumer_supplies      = ldo8_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo9_data = {
-        .constraints    = {
-                .name           = "DVDD_SWB_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo9_consumer),
-        .consumer_supplies      = ldo9_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo10_data = {
-        .constraints    = {
-                .name           = "VDD_PLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_ldo11_data = {
-        .constraints    = {
-                .name           = "VDD_AUD_3V",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo11_consumer),
-        .consumer_supplies      = ldo11_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo14_data = {
-        .constraints    = {
-                .name           = "AVDD18_SWB_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo14_consumer),
-        .consumer_supplies      = ldo14_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo17_data = {
-        .constraints    = {
-                .name           = "VDD_SWB_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(ldo17_consumer),
-        .consumer_supplies      = ldo17_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_ldo21_data = {
-        .constraints    = {
-                .name           = "VDD_MIF_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_1.2V",
-                .min_uV         = 950000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck1_consumer),
-        .consumer_supplies      = buck1_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .always_on      = 1,
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck2_consumer),
-        .consumer_supplies      = buck2_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_1.1V",
-                .min_uV         = 900000,
-                .max_uV         = 1100000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                        REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck3_consumer),
-        .consumer_supplies      = buck3_consumer,
-};
-
-static struct regulator_init_data __initdata max8997_buck5_data = {
-        .constraints    = {
-                .name           = "VDDQ_M1M2_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data __initdata max8997_buck7_data = {
-        .constraints    = {
-                .name           = "VDD_LCD_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(buck7_consumer),
-        .consumer_supplies      = buck7_consumer,
-};
-
-static struct max8997_regulator_data __initdata origen_max8997_regulators[] = {
-        { MAX8997_LDO1,         &max8997_ldo1_data },
-        { MAX8997_LDO2,         &max8997_ldo2_data },
-        { MAX8997_LDO3,         &max8997_ldo3_data },
-        { MAX8997_LDO4,         &max8997_ldo4_data },
-        { MAX8997_LDO6,         &max8997_ldo6_data },
-        { MAX8997_LDO7,         &max8997_ldo7_data },
-        { MAX8997_LDO8,         &max8997_ldo8_data },
-        { MAX8997_LDO9,         &max8997_ldo9_data },
-        { MAX8997_LDO10,        &max8997_ldo10_data },
-        { MAX8997_LDO11,        &max8997_ldo11_data },
-        { MAX8997_LDO14,        &max8997_ldo14_data },
-        { MAX8997_LDO17,        &max8997_ldo17_data },
-        { MAX8997_LDO21,        &max8997_ldo21_data },
-        { MAX8997_BUCK1,        &max8997_buck1_data },
-        { MAX8997_BUCK2,        &max8997_buck2_data },
-        { MAX8997_BUCK3,        &max8997_buck3_data },
-        { MAX8997_BUCK5,        &max8997_buck5_data },
-        { MAX8997_BUCK7,        &max8997_buck7_data },
-};
-
-static struct max8997_platform_data __initdata origen_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(origen_max8997_regulators),
-        .regulators     = origen_max8997_regulators,
-
-        .wakeup = true,
-        .buck1_gpiodvs  = false,
-        .buck2_gpiodvs  = false,
-        .buck5_gpiodvs  = false,
-
-        .ignore_gpiodvs_side_effect = true,
-        .buck125_default_idx = 0x0,
-
-        .buck125_gpios[0]       = EXYNOS4_GPX0(0),
-        .buck125_gpios[1]       = EXYNOS4_GPX0(1),
-        .buck125_gpios[2]       = EXYNOS4_GPX0(2),
-
-        .buck1_voltage[0]       = 1350000,
-        .buck1_voltage[1]       = 1300000,
-        .buck1_voltage[2]       = 1250000,
-        .buck1_voltage[3]       = 1200000,
-        .buck1_voltage[4]       = 1150000,
-        .buck1_voltage[5]       = 1100000,
-        .buck1_voltage[6]       = 1000000,
-        .buck1_voltage[7]       = 950000,
-
-        .buck2_voltage[0]       = 1100000,
-        .buck2_voltage[1]       = 1100000,
-        .buck2_voltage[2]       = 1100000,
-        .buck2_voltage[3]       = 1100000,
-        .buck2_voltage[4]       = 1000000,
-        .buck2_voltage[5]       = 1000000,
-        .buck2_voltage[6]       = 1000000,
-        .buck2_voltage[7]       = 1000000,
-
-        .buck5_voltage[0]       = 1200000,
-        .buck5_voltage[1]       = 1200000,
-        .buck5_voltage[2]       = 1200000,
-        .buck5_voltage[3]       = 1200000,
-        .buck5_voltage[4]       = 1200000,
-        .buck5_voltage[5]       = 1200000,
-        .buck5_voltage[6]       = 1200000,
-        .buck5_voltage[7]       = 1200000,
-};
-
-/* I2C0 */
-static struct i2c_board_info i2c0_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", (0xCC >> 1)),
-                .platform_data  = &origen_max8997_pdata,
-                .irq            = IRQ_EINT(4),
-        },
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata origen_ehci_pdata;
-
-static void __init origen_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &origen_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OHCI */
-static struct exynos4_ohci_platdata origen_ohci_pdata;
-
-static void __init origen_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
-
-        exynos4_ohci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat origen_hsotg_pdata;
-
-static struct gpio_led origen_gpio_leds[] = {
-        {
-                .name                   = "origen::status1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = EXYNOS4_GPX1(3),
-                .active_low             = 1,
-        },
-        {
-                .name                   = "origen::status2",
-                .default_trigger        = "mmc0",
-                .gpio                   = EXYNOS4_GPX1(4),
-                .active_low             = 1,
-        },
-};
-
-static struct gpio_led_platform_data origen_gpio_led_info = {
-        .leds           = origen_gpio_leds,
-        .num_leds       = ARRAY_SIZE(origen_gpio_leds),
-};
-
-static struct platform_device origen_leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &origen_gpio_led_info,
-        },
-};
-
-static struct gpio_keys_button origen_gpio_keys_table[] = {
-        {
-                .code                   = KEY_MENU,
-                .gpio                   = EXYNOS4_GPX1(5),
-                .desc                   = "gpio-keys: KEY_MENU",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_HOME,
-                .gpio                   = EXYNOS4_GPX1(6),
-                .desc                   = "gpio-keys: KEY_HOME",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_BACK,
-                .gpio                   = EXYNOS4_GPX1(7),
-                .desc                   = "gpio-keys: KEY_BACK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_UP,
-                .gpio                   = EXYNOS4_GPX2(0),
-                .desc                   = "gpio-keys: KEY_UP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_DOWN,
-                .gpio                   = EXYNOS4_GPX2(1),
-                .desc                   = "gpio-keys: KEY_DOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .wakeup                 = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data origen_gpio_keys_data = {
-        .buttons        = origen_gpio_keys_table,
-        .nbuttons       = ARRAY_SIZE(origen_gpio_keys_table),
-};
-
-static struct platform_device origen_device_gpiokeys = {
-        .name           = "gpio-keys",
-        .dev            = {
-                .platform_data  = &origen_gpio_keys_data,
-        },
-};
-
-static void lcd_hv070wsa_set_power(struct plat_lcd_data *pd, unsigned int power)
-{
-        int ret;
-
-        if (power)
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_HIGH, "GPE3_4");
-        else
-                ret = gpio_request_one(EXYNOS4_GPE3(4),
-                                        GPIOF_OUT_INIT_LOW, "GPE3_4");
-
-        gpio_free(EXYNOS4_GPE3(4));
-
-        if (ret)
-                pr_err("failed to request gpio for LCD power: %d\n", ret);
-}
-
-static struct plat_lcd_data origen_lcd_hv070wsa_data = {
-        .set_power = lcd_hv070wsa_set_power,
-};
-
-static struct platform_device origen_lcd_hv070wsa = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &origen_lcd_hv070wsa_data,
-};
-
-static struct pwm_lookup origen_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.0", 0, "pwm-backlight.0", NULL),
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 64,
-                        .right_margin   = 16,
-                        .upper_margin   = 64,
-                        .lower_margin   = 16,
-                        .hsync_len      = 48,
-                        .vsync_len      = 3,
-                        .xres           = 1024,
-                        .yres           = 600,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win origen_fb_win0 = {
-        .xres                   = 1024,
-        .yres                   = 600,
-        .max_bpp                = 32,
-        .default_bpp            = 24,
-        .virtual_x              = 1024,
-        .virtual_y              = 2 * 600,
-};
-
-static struct fb_videomode origen_lcd_timing = {
-        .left_margin    = 64,
-        .right_margin   = 16,
-        .upper_margin   = 64,
-        .lower_margin   = 16,
-        .hsync_len      = 48,
-        .vsync_len      = 3,
-        .xres           = 1024,
-        .yres           = 600,
-};
-
-static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
-        .win[0]         = &origen_fb_win0,
-        .vtiming        = &origen_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
-                                VIDCON1_INV_VCLK,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-/* Bluetooth rfkill gpio platform data */
-static struct rfkill_gpio_platform_data origen_bt_pdata = {
-        .reset_gpio     = EXYNOS4_GPX2(2),
-        .shutdown_gpio  = -1,
-        .type           = RFKILL_TYPE_BLUETOOTH,
-        .name           = "origen-bt",
-};
-
-/* Bluetooth Platform device */
-static struct platform_device origen_device_bluetooth = {
-        .name           = "rfkill_gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &origen_bt_pdata,
-        },
-};
-
-static struct platform_device *origen_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc0,
-        &s3c_device_i2c0,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_g2d,
-        &s5p_device_hdmi,
-        &s5p_device_i2c_hdmiphy,
-        &s5p_device_jpeg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &s5p_device_mixer,
-        &exynos4_device_ohci,
-        &origen_device_gpiokeys,
-        &origen_lcd_hv070wsa,
-        &origen_leds_gpio,
-        &origen_device_bluetooth,
-};
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info origen_bl_gpio_info = {
-        .no             = EXYNOS4_GPD0(0),
-        .func           = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data origen_bl_data = {
-        .pwm_id         = 0,
-        .pwm_period_ns  = 1000,
-};
-
-static void __init origen_bt_setup(void)
-{
-        gpio_request(EXYNOS4_GPA0(0), "GPIO BT_UART");
-        /* 4 UART Pins configuration */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPA0(0), 4, S3C_GPIO_SFN(2));
-        /* Setup BT Reset, this gpio will be requesed by rfkill-gpio */
-        s3c_gpio_cfgpin(EXYNOS4_GPX2(2), S3C_GPIO_OUTPUT);
-        s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
-}
-
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-
-static void s5p_tv_setup(void)
-{
-        /* Direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void __init origen_power_init(void)
-{
-        gpio_request(EXYNOS4_GPX0(4), "PMIC_IRQ");
-        s3c_gpio_cfgpin(EXYNOS4_GPX0(4), S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(EXYNOS4_GPX0(4), S3C_GPIO_PULL_NONE);
-}
-
-static void __init origen_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init origen_machine_init(void)
-{
-        origen_power_init();
-
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
-
-        /*
-         * Since sdhci instance 2 can contain a bootable media,
-         * sdhci instance 0 is registered after instance 2.
-         */
-        s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata);
-        s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
-
-        origen_ehci_init();
-        origen_ohci_init();
-        s3c_hsotg_set_platdata(&origen_hsotg_pdata);
-
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&origen_lcd_pdata);
-#endif
-
-        platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices));
-
-        pwm_add_table(origen_pwm_lookup, ARRAY_SIZE(origen_pwm_lookup));
-        samsung_bl_set(&origen_bl_gpio_info, &origen_bl_data);
-
-        origen_bt_setup();
-}
-
-MACHINE_START(ORIGEN, "ORIGEN")
-        /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = origen_map_io,
-        .init_machine   = origen_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &origen_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
deleted file mode 100644
index 2c8af9617920..000000000000
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/mach-smdk4x12.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/lcd.h>
-#include <linux/mfd/max8997.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/regulator/machine.h>
-#include <linux/serial_core.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/backlight.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/gpio-cfg.h>
-#include <plat/keypad.h>
-#include <plat/mfc.h>
-#include <plat/regs-serial.h>
-#include <plat/sdhci.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK4X12_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDK4X12_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdk4x12_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDK4X12_UCON_DEFAULT,
-                .ulcon          = SMDK4X12_ULCON_DEFAULT,
-                .ufcon          = SMDK4X12_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdk4x12_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-};
-
-static struct regulator_consumer_supply max8997_buck1 =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct regulator_consumer_supply max8997_buck2 =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply max8997_buck3 =
-        REGULATOR_SUPPLY("vdd_g3d", NULL);
-
-static struct regulator_init_data max8997_buck1_data = {
-        .constraints    = {
-                .name           = "VDD_ARM_SMDK4X12",
-                .min_uV         = 925000,
-                .max_uV         = 1350000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck1,
-};
-
-static struct regulator_init_data max8997_buck2_data = {
-        .constraints    = {
-                .name           = "VDD_INT_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .always_on      = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck2,
-};
-
-static struct regulator_init_data max8997_buck3_data = {
-        .constraints    = {
-                .name           = "VDD_G3D_SMDK4X12",
-                .min_uV         = 950000,
-                .max_uV         = 1150000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                                  REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8997_buck3,
-};
-
-static struct max8997_regulator_data smdk4x12_max8997_regulators[] = {
-        { MAX8997_BUCK1, &max8997_buck1_data },
-        { MAX8997_BUCK2, &max8997_buck2_data },
-        { MAX8997_BUCK3, &max8997_buck3_data },
-};
-
-static struct max8997_platform_data smdk4x12_max8997_pdata = {
-        .num_regulators = ARRAY_SIZE(smdk4x12_max8997_regulators),
-        .regulators     = smdk4x12_max8997_regulators,
-
-        .buck1_voltage[0] = 1100000,    /* 1.1V */
-        .buck1_voltage[1] = 1100000,    /* 1.1V */
-        .buck1_voltage[2] = 1100000,    /* 1.1V */
-        .buck1_voltage[3] = 1100000,    /* 1.1V */
-        .buck1_voltage[4] = 1100000,    /* 1.1V */
-        .buck1_voltage[5] = 1100000,    /* 1.1V */
-        .buck1_voltage[6] = 1000000,    /* 1.0V */
-        .buck1_voltage[7] = 950000,     /* 0.95V */
-
-        .buck2_voltage[0] = 1100000,    /* 1.1V */
-        .buck2_voltage[1] = 1000000,    /* 1.0V */
-        .buck2_voltage[2] = 950000,     /* 0.95V */
-        .buck2_voltage[3] = 900000,     /* 0.9V */
-        .buck2_voltage[4] = 1100000,    /* 1.1V */
-        .buck2_voltage[5] = 1000000,    /* 1.0V */
-        .buck2_voltage[6] = 950000,     /* 0.95V */
-        .buck2_voltage[7] = 900000,     /* 0.9V */
-
-        .buck5_voltage[0] = 1100000,    /* 1.1V */
-        .buck5_voltage[1] = 1100000,    /* 1.1V */
-        .buck5_voltage[2] = 1100000,    /* 1.1V */
-        .buck5_voltage[3] = 1100000,    /* 1.1V */
-        .buck5_voltage[4] = 1100000,    /* 1.1V */
-        .buck5_voltage[5] = 1100000,    /* 1.1V */
-        .buck5_voltage[6] = 1100000,    /* 1.1V */
-        .buck5_voltage[7] = 1100000,    /* 1.1V */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs0[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8997", 0x66),
-                .platform_data  = &smdk4x12_max8997_pdata,
-        }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs1[] __initdata = {
-        { I2C_BOARD_INFO("wm8994", 0x1a), }
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs3[] __initdata = {
-        /* nothing here yet */
-};
-
-static struct i2c_board_info smdk4x12_i2c_devs7[] __initdata = {
-        /* nothing here yet */
-};
-
-static struct samsung_bl_gpio_info smdk4x12_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdk4x12_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-static struct pwm_lookup smdk4x12_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-
-static uint32_t smdk4x12_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
-        KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
-        KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
-        KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
-};
-
-static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
-        .keymap         = smdk4x12_keymap,
-        .keymap_size    = ARRAY_SIZE(smdk4x12_keymap),
-};
-
-static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
-        .keymap_data    = &smdk4x12_keymap_data,
-        .rows           = 3,
-        .cols           = 8,
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 8,
-                        .right_margin   = 8,
-                        .upper_margin   = 6,
-                        .lower_margin   = 6,
-                        .hsync_len      = 6,
-                        .vsync_len      = 4,
-                        .xres           = 480,
-                        .yres           = 800,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 800 * 2,
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-};
-
-static struct fb_videomode smdk4x12_lcd_timing = {
-        .left_margin    = 8,
-        .right_margin   = 8,
-        .upper_margin   = 6,
-        .lower_margin   = 6,
-        .hsync_len      = 6,
-        .vsync_len      = 4,
-        .xres           = 480,
-        .yres           = 800,
-};
-
-static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
-        .win[0]         = &smdk4x12_fb_win0,
-        .vtiming        = &smdk4x12_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-/* USB OTG */
-static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
-
-static struct platform_device *smdk4x12_devices[] __initdata = {
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c1,
-        &s3c_device_i2c3,
-        &s3c_device_i2c7,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_fimd0,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &samsung_device_keypad,
-};
-
-static void __init smdk4x12_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
-}
-
-static void __init smdk4x12_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdk4x12_machine_init(void)
-{
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, smdk4x12_i2c_devs0,
-                                ARRAY_SIZE(smdk4x12_i2c_devs0));
-
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, smdk4x12_i2c_devs1,
-                                ARRAY_SIZE(smdk4x12_i2c_devs1));
-
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, smdk4x12_i2c_devs3,
-                                ARRAY_SIZE(smdk4x12_i2c_devs3));
-
-        s3c_i2c7_set_platdata(NULL);
-        i2c_register_board_info(7, smdk4x12_i2c_devs7,
-                                ARRAY_SIZE(smdk4x12_i2c_devs7));
-
-        samsung_bl_set(&smdk4x12_bl_gpio_info, &smdk4x12_bl_data);
-        pwm_add_table(smdk4x12_pwm_lookup, ARRAY_SIZE(smdk4x12_pwm_lookup));
-
-        samsung_keypad_set_platdata(&smdk4x12_keypad_data);
-
-        s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
-
-        s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
-#endif
-
-        platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
-}
-
-MACHINE_START(SMDK4212, "SMDK4212")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
-
-MACHINE_START(SMDK4412, "SMDK4412")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdk4x12_map_io,
-        .init_machine   = smdk4x12_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .restart        = exynos4_restart,
-        .reserve        = &smdk4x12_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
deleted file mode 100644
index d95b8cf85253..000000000000
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/serial_core.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/lcd.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/smsc911x.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/input.h>
-#include <linux/pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-ohci-exynos.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/platform_lcd.h>
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/regs-srom.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/fb.h>
-#include <plat/keypad.h>
-#include <plat/sdhci.h>
-#include <plat/gpio-cfg.h>
-#include <plat/backlight.h>
-#include <plat/mfc.h>
-#include <plat/clock.h>
-#include <plat/hdmi.h>
-
-#include <mach/irqs.h>
-#include <mach/map.h>
-
-#include <drm/exynos_drm.h>
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDKV310_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDKV310_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .flags          = 0,
-                .ucon           = SMDKV310_UCON_DEFAULT,
-                .ulcon          = SMDKV310_ULCON_DEFAULT,
-                .ufcon          = SMDKV310_UFCON_DEFAULT,
-        },
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK0(2),
-        .ext_cd_gpio_invert     = 1,
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_INTERNAL,
-#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
-        .max_width              = 8,
-        .host_caps              = MMC_CAP_8_BIT_DATA,
-#endif
-};
-
-static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = EXYNOS4_GPK2(2),
-        .ext_cd_gpio_invert     = 1,
-};
-
-static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power) {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-                /* fire nRESET on power up */
-                gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
-                mdelay(100);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 0);
-                mdelay(10);
-
-                gpio_set_value(EXYNOS4_GPX0(6), 1);
-                mdelay(10);
-
-                gpio_free(EXYNOS4_GPX0(6));
-        } else {
-#if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_free(EXYNOS4_GPD0(1));
-#endif
-        }
-}
-
-static struct plat_lcd_data smdkv310_lcd_lte480wv_data = {
-        .set_power              = lcd_lte480wv_set_power,
-};
-
-static struct platform_device smdkv310_lcd_lte480wv = {
-        .name                   = "platform-lcd",
-        .dev.parent             = &s5p_device_fimd0.dev,
-        .dev.platform_data      = &smdkv310_lcd_lte480wv_data,
-};
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel  = {
-                .timing = {
-                        .left_margin    = 13,
-                        .right_margin   = 8,
-                        .upper_margin   = 7,
-                        .lower_margin   = 5,
-                        .hsync_len      = 3,
-                        .vsync_len      = 1,
-                        .xres           = 800,
-                        .yres           = 480,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 0,
-        .bpp            = 32,
-};
-#else
-static struct s3c_fb_pd_win smdkv310_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 24,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct fb_videomode smdkv310_lcd_timing = {
-        .left_margin    = 13,
-        .right_margin   = 8,
-        .upper_margin   = 7,
-        .lower_margin   = 5,
-        .hsync_len      = 3,
-        .vsync_len      = 1,
-        .xres           = 800,
-        .yres           = 480,
-};
-
-static struct s3c_fb_platdata smdkv310_lcd0_pdata __initdata = {
-        .win[0]         = &smdkv310_fb_win0,
-        .vtiming        = &smdkv310_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static struct resource smdkv310_smsc911x_resources[] = {
-        [0] = DEFINE_RES_MEM(EXYNOS4_PA_SROM_BANK(1), SZ_64K),
-        [1] = DEFINE_RES_NAMED(IRQ_EINT(5), 1, NULL, IORESOURCE_IRQ \
-                                                | IRQF_TRIGGER_LOW),
-};
-
-static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .mac            = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
-};
-
-static struct platform_device smdkv310_smsc911x = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smdkv310_smsc911x_resources),
-        .resource       = smdkv310_smsc911x_resources,
-        .dev            = {
-                .platform_data  = &smsc9215_config,
-        },
-};
-
-static uint32_t smdkv310_keymap[] __initdata = {
-        /* KEY(row, col, keycode) */
-        KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
-        KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
-        KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
-        KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
-};
-
-static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
-        .keymap         = smdkv310_keymap,
-        .keymap_size    = ARRAY_SIZE(smdkv310_keymap),
-};
-
-static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
-        .keymap_data    = &smdkv310_keymap_data,
-        .rows           = 2,
-        .cols           = 8,
-};
-
-static struct i2c_board_info i2c_devs1[] __initdata = {
-        {I2C_BOARD_INFO("wm8994", 0x1a),},
-};
-
-/* USB EHCI */
-static struct s5p_ehci_platdata smdkv310_ehci_pdata;
-
-static void __init smdkv310_ehci_init(void)
-{
-        struct s5p_ehci_platdata *pdata = &smdkv310_ehci_pdata;
-
-        s5p_ehci_set_platdata(pdata);
-}
-
-/* USB OHCI */
-static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
-
-static void __init smdkv310_ohci_init(void)
-{
-        struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
-
-        exynos4_ohci_set_platdata(pdata);
-}
-
-/* USB OTG */
-static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
-
-/* Audio device */
-static struct platform_device smdkv310_device_audio = {
-        .name = "smdk-audio",
-        .id = -1,
-};
-
-static struct platform_device *smdkv310_devices[] __initdata = {
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c1,
-        &s5p_device_i2c_hdmiphy,
-        &s3c_device_rtc,
-        &s3c_device_usb_hsotg,
-        &s3c_device_wdt,
-        &s5p_device_ehci,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_fimc_md,
-        &s5p_device_g2d,
-        &s5p_device_jpeg,
-        &exynos4_device_ac97,
-        &exynos4_device_i2s0,
-        &exynos4_device_ohci,
-        &samsung_device_keypad,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &exynos4_device_spdif,
-        &samsung_asoc_idma,
-        &s5p_device_fimd0,
-        &smdkv310_device_audio,
-        &smdkv310_lcd_lte480wv,
-        &smdkv310_smsc911x,
-        &exynos4_device_ahci,
-        &s5p_device_hdmi,
-        &s5p_device_mixer,
-};
-
-static void __init smdkv310_smsc911x_init(void)
-{
-        u32 cs1;
-
-        /* configure nCS1 width to 16 bits */
-        cs1 = __raw_readl(S5P_SROM_BW) &
-                ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
-        cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
-                (1 << S5P_SROM_BW__WAITENABLE__SHIFT) |
-                (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
-                S5P_SROM_BW__NCS1__SHIFT;
-        __raw_writel(cs1, S5P_SROM_BW);
-
-        /* set timing for nCS1 suitable for ethernet chip */
-        __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
-                     (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
-                     (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
-                     (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
-                     (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
-}
-
-/* LCD Backlight data */
-static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
-        .no = EXYNOS4_GPD0(1),
-        .func = S3C_GPIO_SFN(2),
-};
-
-static struct platform_pwm_backlight_data smdkv310_bl_data = {
-        .pwm_id = 1,
-        .pwm_period_ns  = 1000,
-};
-
-/* I2C module and id for HDMIPHY */
-static struct i2c_board_info hdmiphy_info = {
-        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
-};
-
-static struct pwm_lookup smdkv310_pwm_lookup[] = {
-        PWM_LOOKUP("s3c24xx-pwm.1", 0, "pwm-backlight.0", NULL),
-};
-
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        WARN_ON(gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug"));
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init smdkv310_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
-        xxti_f = 12000000;
-        xusbxti_f = 24000000;
-}
-
-static void __init smdkv310_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init smdkv310_machine_init(void)
-{
-        s3c_i2c1_set_platdata(NULL);
-        i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
-
-        smdkv310_smsc911x_init();
-
-        s3c_sdhci0_set_platdata(&smdkv310_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&smdkv310_hsmmc1_pdata);
-        s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
-        s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
-
-        s5p_tv_setup();
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
-
-        samsung_keypad_set_platdata(&smdkv310_keypad_data);
-
-        samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
-        pwm_add_table(smdkv310_pwm_lookup, ARRAY_SIZE(smdkv310_pwm_lookup));
-
-#ifdef CONFIG_DRM_EXYNOS_FIMD
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
-#endif
-
-        smdkv310_ehci_init();
-        smdkv310_ohci_init();
-        s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
-
-        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
-}
-
-MACHINE_START(SMDKV310, "SMDKV310")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
-
-MACHINE_START(SMDKC210, "SMDKC210")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = smdkv310_map_io,
-        .init_machine   = smdkv310_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &smdkv310_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
deleted file mode 100644
index 74ddb2b55614..000000000000
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ /dev/null
@@ -1,1159 +0,0 @@
-/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/platform_device.h>
-#include <linux/serial_core.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio_keys.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/fb.h>
-#include <linux/mfd/max8998.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/max8952.h>
-#include <linux/mmc/host.h>
-#include <linux/i2c-gpio.h>
-#include <linux/i2c/mcs.h>
-#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <linux/platform_data/mipi-csis.h>
-#include <linux/platform_data/s3c-hsotg.h>
-#include <drm/exynos_drm.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/regs-serial.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/gpio-cfg.h>
-#include <plat/fb.h>
-#include <plat/mfc.h>
-#include <plat/sdhci.h>
-#include <plat/fimc-core.h>
-#include <plat/camport.h>
-
-#include <mach/map.h>
-
-#include <media/v4l2-mediabus.h>
-#include <media/s5p_fimc.h>
-#include <media/m5mols.h>
-#include <media/s5k6aa.h>
-
-#include "common.h"
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
-
-#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG256 |      \
-                                 S5PV210_UFCON_RXTRIG256)
-
-static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-        [3] = {
-                .hwport         = 3,
-                .ucon           = UNIVERSAL_UCON_DEFAULT,
-                .ulcon          = UNIVERSAL_ULCON_DEFAULT,
-                .ufcon          = UNIVERSAL_UFCON_DEFAULT,
-        },
-};
-
-static struct regulator_consumer_supply max8952_consumer =
-        REGULATOR_SUPPLY("vdd_arm", NULL);
-
-static struct regulator_init_data universal_max8952_reg_data = {
-        .constraints    = {
-                .name           = "VARM_1.2V",
-                .min_uV         = 770000,
-                .max_uV         = 1400000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
-                .always_on      = 1,
-                .boot_on        = 1,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &max8952_consumer,
-};
-
-static struct max8952_platform_data universal_max8952_pdata __initdata = {
-        .gpio_vid0      = EXYNOS4_GPX0(3),
-        .gpio_vid1      = EXYNOS4_GPX0(4),
-        .gpio_en        = -1, /* Not controllable, set "Always High" */
-        .default_mode   = 0, /* vid0 = 0, vid1 = 0 */
-        .dvs_mode       = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
-        .sync_freq      = 0, /* default: fastest */
-        .ramp_speed     = 0, /* default: fastest */
-        .reg_data       = &universal_max8952_reg_data,
-};
-
-static struct regulator_consumer_supply lp3974_buck1_consumer =
-        REGULATOR_SUPPLY("vdd_int", NULL);
-
-static struct regulator_consumer_supply lp3974_buck2_consumer =
-        REGULATOR_SUPPLY("vddg3d", NULL);
-
-static struct regulator_consumer_supply lp3974_buck3_consumer[] = {
-        REGULATOR_SUPPLY("vdet", "s5p-sdo"),
-        REGULATOR_SUPPLY("vdd_reg", "0-003c"),
-};
-
-static struct regulator_init_data lp3974_buck1_data = {
-        .constraints    = {
-                .name           = "VINT_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck1_consumer,
-};
-
-static struct regulator_init_data lp3974_buck2_data = {
-        .constraints    = {
-                .name           = "VG3D_1.1V",
-                .min_uV         = 750000,
-                .max_uV         = 1500000,
-                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
-                        REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &lp3974_buck2_consumer,
-};
-
-static struct regulator_init_data lp3974_buck3_data = {
-        .constraints    = {
-                .name           = "VCC_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_buck3_consumer),
-        .consumer_supplies = lp3974_buck3_consumer,
-};
-
-static struct regulator_init_data lp3974_buck4_data = {
-        .constraints    = {
-                .name           = "VMEM_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .apply_uV       = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo2_data = {
-        .constraints    = {
-                .name           = "VALIVE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo3_consumer[] = {
-        REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vdd_pll", "exynos4-hdmi"),
-        REGULATOR_SUPPLY("vddcore", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo3_data = {
-        .constraints    = {
-                .name           = "VUSB+MIPI_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo3_consumer),
-        .consumer_supplies = lp3974_ldo3_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo4_consumer[] = {
-        REGULATOR_SUPPLY("vdd_osc", "exynos4-hdmi"),
-};
-
-static struct regulator_init_data lp3974_ldo4_data = {
-        .constraints    = {
-                .name           = "VADC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo4_consumer),
-        .consumer_supplies = lp3974_ldo4_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo5_data = {
-        .constraints    = {
-                .name           = "VTF_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo6_data = {
-        .constraints    = {
-                .name           = "LDO6",
-                .min_uV         = 2000000,
-                .max_uV         = 2000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo7_consumer[] = {
-        REGULATOR_SUPPLY("vddio", "s5p-mipi-csis.0"),
-};
-
-static struct regulator_init_data lp3974_ldo7_data = {
-        .constraints    = {
-                .name           = "VLCD+VMIPI_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo7_consumer),
-        .consumer_supplies      = lp3974_ldo7_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo8_consumer[] = {
-        REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
-        REGULATOR_SUPPLY("vdd33a_dac", "s5p-sdo"),
-};
-
-static struct regulator_init_data lp3974_ldo8_data = {
-        .constraints    = {
-                .name           = "VUSB+VDAC_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies = ARRAY_SIZE(lp3974_ldo8_consumer),
-        .consumer_supplies = lp3974_ldo8_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo9_consumer =
-        REGULATOR_SUPPLY("vddio", "0-003c");
-
-static struct regulator_init_data lp3974_ldo9_data = {
-        .constraints    = {
-                .name           = "VCC_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo9_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo10_data = {
-        .constraints    = {
-                .name           = "VPLL_1.1V",
-                .min_uV         = 1100000,
-                .max_uV         = 1100000,
-                .boot_on        = 1,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo11_consumer =
-        REGULATOR_SUPPLY("dig_28", "0-001f");
-
-static struct regulator_init_data lp3974_ldo11_data = {
-        .constraints    = {
-                .name           = "CAM_AF_3.3V",
-                .min_uV         = 3300000,
-                .max_uV         = 3300000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo11_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo12_data = {
-        .constraints    = {
-                .name           = "PS_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_ldo13_data = {
-        .constraints    = {
-                .name           = "VHIC_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_consumer_supply lp3974_ldo14_consumer =
-        REGULATOR_SUPPLY("dig_18", "0-001f");
-
-static struct regulator_init_data lp3974_ldo14_data = {
-        .constraints    = {
-                .name           = "CAM_I_HOST_1.8V",
-                .min_uV         = 1800000,
-                .max_uV         = 1800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo14_consumer,
-};
-
-
-static struct regulator_consumer_supply lp3974_ldo15_consumer =
-        REGULATOR_SUPPLY("dig_12", "0-001f");
-
-static struct regulator_init_data lp3974_ldo15_data = {
-        .constraints    = {
-                .name           = "CAM_S_DIG+FM33_CORE_1.2V",
-                .min_uV         = 1200000,
-                .max_uV         = 1200000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &lp3974_ldo15_consumer,
-};
-
-static struct regulator_consumer_supply lp3974_ldo16_consumer[] = {
-        REGULATOR_SUPPLY("vdda", "0-003c"),
-        REGULATOR_SUPPLY("a_sensor", "0-001f"),
-};
-
-static struct regulator_init_data lp3974_ldo16_data = {
-        .constraints    = {
-                .name           = "CAM_S_ANA_2.8V",
-                .min_uV         = 2800000,
-                .max_uV         = 2800000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(lp3974_ldo16_consumer),
-        .consumer_supplies      = lp3974_ldo16_consumer,
-};
-
-static struct regulator_init_data lp3974_ldo17_data = {
-        .constraints    = {
-                .name           = "VCC_3.0V_LCD",
-                .min_uV         = 3000000,
-                .max_uV         = 3000000,
-                .apply_uV       = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .boot_on        = 1,
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_32khz_ap_data = {
-        .constraints    = {
-                .name           = "32KHz AP",
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_32khz_cp_data = {
-        .constraints    = {
-                .name           = "32KHz CP",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_vichg_data = {
-        .constraints    = {
-                .name           = "VICHG",
-                .state_mem      = {
-                        .disabled       = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_esafeout1_data = {
-        .constraints    = {
-                .name           = "SAFEOUT1",
-                .min_uV         = 4800000,
-                .max_uV         = 4800000,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .always_on      = 1,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct regulator_init_data lp3974_esafeout2_data = {
-        .constraints    = {
-                .name           = "SAFEOUT2",
-                .boot_on        = 1,
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                .state_mem      = {
-                        .enabled        = 1,
-                },
-        },
-};
-
-static struct max8998_regulator_data lp3974_regulators[] = {
-        { MAX8998_LDO2,  &lp3974_ldo2_data },
-        { MAX8998_LDO3,  &lp3974_ldo3_data },
-        { MAX8998_LDO4,  &lp3974_ldo4_data },
-        { MAX8998_LDO5,  &lp3974_ldo5_data },
-        { MAX8998_LDO6,  &lp3974_ldo6_data },
-        { MAX8998_LDO7,  &lp3974_ldo7_data },
-        { MAX8998_LDO8,  &lp3974_ldo8_data },
-        { MAX8998_LDO9,  &lp3974_ldo9_data },
-        { MAX8998_LDO10, &lp3974_ldo10_data },
-        { MAX8998_LDO11, &lp3974_ldo11_data },
-        { MAX8998_LDO12, &lp3974_ldo12_data },
-        { MAX8998_LDO13, &lp3974_ldo13_data },
-        { MAX8998_LDO14, &lp3974_ldo14_data },
-        { MAX8998_LDO15, &lp3974_ldo15_data },
-        { MAX8998_LDO16, &lp3974_ldo16_data },
-        { MAX8998_LDO17, &lp3974_ldo17_data },
-        { MAX8998_BUCK1, &lp3974_buck1_data },
-        { MAX8998_BUCK2, &lp3974_buck2_data },
-        { MAX8998_BUCK3, &lp3974_buck3_data },
-        { MAX8998_BUCK4, &lp3974_buck4_data },
-        { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
-        { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
-        { MAX8998_ENVICHG, &lp3974_vichg_data },
-        { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
-        { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
-};
-
-static struct max8998_platform_data universal_lp3974_pdata = {
-        .num_regulators         = ARRAY_SIZE(lp3974_regulators),
-        .regulators             = lp3974_regulators,
-        .buck1_voltage1         = 1100000,      /* INT */
-        .buck1_voltage2         = 1000000,
-        .buck1_voltage3         = 1100000,
-        .buck1_voltage4         = 1000000,
-        .buck1_set1             = EXYNOS4_GPX0(5),
-        .buck1_set2             = EXYNOS4_GPX0(6),
-        .buck2_voltage1         = 1200000,      /* G3D */
-        .buck2_voltage2         = 1100000,
-        .buck1_default_idx      = 0,
-        .buck2_set3             = EXYNOS4_GPE2(0),
-        .buck2_default_idx      = 0,
-        .wakeup                 = true,
-};
-
-
-enum fixed_regulator_id {
-        FIXED_REG_ID_MMC0,
-        FIXED_REG_ID_HDMI_5V,
-        FIXED_REG_ID_CAM_S_IF,
-        FIXED_REG_ID_CAM_I_CORE,
-        FIXED_REG_ID_CAM_VT_DIO,
-};
-
-static struct regulator_consumer_supply hdmi_fixed_consumer =
-        REGULATOR_SUPPLY("hdmi-en", "exynos4-hdmi");
-
-static struct regulator_init_data hdmi_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "HDMI_5V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &hdmi_fixed_consumer,
-};
-
-static struct fixed_voltage_config hdmi_fixed_voltage_config = {
-        .supply_name            = "HDMI_EN1",
-        .microvolts             = 5000000,
-        .gpio                   = EXYNOS4_GPE0(1),
-        .enable_high            = true,
-        .init_data              = &hdmi_fixed_voltage_init_data,
-};
-
-static struct platform_device hdmi_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_HDMI_5V,
-        .dev                    = {
-                .platform_data  = &hdmi_fixed_voltage_config,
-        },
-};
-
-/* GPIO I2C 5 (PMIC) */
-static struct i2c_board_info i2c5_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("max8952", 0xC0 >> 1),
-                .platform_data  = &universal_max8952_pdata,
-        }, {
-                I2C_BOARD_INFO("lp3974", 0xCC >> 1),
-                .platform_data  = &universal_lp3974_pdata,
-        },
-};
-
-/* I2C3 (TSP) */
-static struct mxt_platform_data qt602240_platform_data = {
-        .x_line         = 19,
-        .y_line         = 11,
-        .x_size         = 800,
-        .y_size         = 480,
-        .blen           = 0x11,
-        .threshold      = 0x28,
-        .voltage        = 2800000,              /* 2.8V */
-        .orient         = MXT_DIAGONAL,
-        .irqflags       = IRQF_TRIGGER_FALLING,
-};
-
-static struct i2c_board_info i2c3_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("qt602240_ts", 0x4a),
-                .platform_data = &qt602240_platform_data,
-        },
-};
-
-static void __init universal_tsp_init(void)
-{
-        int gpio;
-
-        /* TSP_LDO_ON: XMDMADDR_11 */
-        gpio = EXYNOS4_GPE2(3);
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_export(gpio, 0);
-
-        /* TSP_INT: XMDMADDR_7 */
-        gpio = EXYNOS4_GPE1(7);
-        gpio_request(gpio, "TSP_INT");
-
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-        i2c3_devs[0].irq = gpio_to_irq(gpio);
-}
-
-
-/* GPIO I2C 12 (3 Touchkey) */
-static uint32_t touchkey_keymap[] = {
-        /* MCS_KEY_MAP(value, keycode) */
-        MCS_KEY_MAP(0, KEY_MENU),               /* KEY_SEND */
-        MCS_KEY_MAP(1, KEY_BACK),               /* KEY_END */
-};
-
-static struct mcs_platform_data touchkey_data = {
-        .keymap         = touchkey_keymap,
-        .keymap_size    = ARRAY_SIZE(touchkey_keymap),
-        .key_maxval     = 2,
-};
-
-/* GPIO I2C 3_TOUCH 2.8V */
-#define I2C_GPIO_BUS_12         12
-static struct i2c_gpio_platform_data i2c_gpio12_data = {
-        .sda_pin        = EXYNOS4_GPE4(0),      /* XMDMDATA_8 */
-        .scl_pin        = EXYNOS4_GPE4(1),      /* XMDMDATA_9 */
-};
-
-static struct platform_device i2c_gpio12 = {
-        .name           = "i2c-gpio",
-        .id             = I2C_GPIO_BUS_12,
-        .dev            = {
-                .platform_data  = &i2c_gpio12_data,
-        },
-};
-
-static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
-        {
-                I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
-                .platform_data = &touchkey_data,
-        },
-};
-
-static void __init universal_touchkey_init(void)
-{
-        int gpio;
-
-        gpio = EXYNOS4_GPE3(7);                 /* XMDMDATA_7 */
-        gpio_request(gpio, "3_TOUCH_INT");
-        s5p_register_gpio_interrupt(gpio);
-        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
-        i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
-
-        gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
-}
-
-static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
-        .frequency      = 300 * 1000,
-        .sda_delay      = 200,
-};
-
-/* GPIO KEYS */
-static struct gpio_keys_button universal_gpio_keys_tables[] = {
-        {
-                .code                   = KEY_VOLUMEUP,
-                .gpio                   = EXYNOS4_GPX2(0),      /* XEINT16 */
-                .desc                   = "gpio-keys: KEY_VOLUMEUP",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_VOLUMEDOWN,
-                .gpio                   = EXYNOS4_GPX2(1),      /* XEINT17 */
-                .desc                   = "gpio-keys: KEY_VOLUMEDOWN",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CONFIG,
-                .gpio                   = EXYNOS4_GPX2(2),      /* XEINT18 */
-                .desc                   = "gpio-keys: KEY_CONFIG",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_CAMERA,
-                .gpio                   = EXYNOS4_GPX2(3),      /* XEINT19 */
-                .desc                   = "gpio-keys: KEY_CAMERA",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        }, {
-                .code                   = KEY_OK,
-                .gpio                   = EXYNOS4_GPX3(5),      /* XEINT29 */
-                .desc                   = "gpio-keys: KEY_OK",
-                .type                   = EV_KEY,
-                .active_low             = 1,
-                .debounce_interval      = 1,
-        },
-};
-
-static struct gpio_keys_platform_data universal_gpio_keys_data = {
-        .buttons        = universal_gpio_keys_tables,
-        .nbuttons       = ARRAY_SIZE(universal_gpio_keys_tables),
-};
-
-static struct platform_device universal_gpio_keys = {
-        .name                   = "gpio-keys",
-        .dev                    = {
-                .platform_data  = &universal_gpio_keys_data,
-        },
-};
-
-/* eMMC */
-static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
-        .max_width              = 8,
-        .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
-        .cd_type                = S3C_SDHCI_CD_PERMANENT,
-};
-
-static struct regulator_consumer_supply mmc0_supplies[] = {
-        REGULATOR_SUPPLY("vmmc", "exynos4-sdhci.0"),
-};
-
-static struct regulator_init_data mmc0_fixed_voltage_init_data = {
-        .constraints            = {
-                .name           = "VMEM_VDD_2.8V",
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(mmc0_supplies),
-        .consumer_supplies      = mmc0_supplies,
-};
-
-static struct fixed_voltage_config mmc0_fixed_voltage_config = {
-        .supply_name            = "MASSMEMORY_EN",
-        .microvolts             = 2800000,
-        .gpio                   = EXYNOS4_GPE1(3),
-        .enable_high            = true,
-        .init_data              = &mmc0_fixed_voltage_init_data,
-};
-
-static struct platform_device mmc0_fixed_voltage = {
-        .name                   = "reg-fixed-voltage",
-        .id                     = FIXED_REG_ID_MMC0,
-        .dev                    = {
-                .platform_data  = &mmc0_fixed_voltage_config,
-        },
-};
-
-/* SD */
-static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .ext_cd_gpio            = EXYNOS4_GPX3(4),      /* XEINT_28 */
-        .ext_cd_gpio_invert     = 1,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-};
-
-/* WiFi */
-static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
-        .max_width              = 4,
-        .host_caps              = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
-        .cd_type                = S3C_SDHCI_CD_EXTERNAL,
-};
-
-static void __init universal_sdhci_init(void)
-{
-        s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
-        s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
-        s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
-}
-
-/* I2C1 */
-static struct i2c_board_info i2c1_devs[] __initdata = {
-        /* Gyro, To be updated */
-};
-
-#ifdef CONFIG_DRM_EXYNOS
-static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
-        .panel = {
-                .timing = {
-                        .left_margin    = 16,
-                        .right_margin   = 16,
-                        .upper_margin   = 2,
-                        .lower_margin   = 28,
-                        .hsync_len      = 2,
-                        .vsync_len      = 1,
-                        .xres           = 480,
-                        .yres           = 800,
-                        .refresh        = 55,
-                },
-        },
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .default_win    = 3,
-        .bpp            = 32,
-};
-#else
-/* Frame Buffer */
-static struct s3c_fb_pd_win universal_fb_win0 = {
-        .max_bpp        = 32,
-        .default_bpp    = 16,
-        .xres           = 480,
-        .yres           = 800,
-        .virtual_x      = 480,
-        .virtual_y      = 2 * 800,
-};
-
-static struct fb_videomode universal_lcd_timing = {
-        .left_margin    = 16,
-        .right_margin   = 16,
-        .upper_margin   = 2,
-        .lower_margin   = 28,
-        .hsync_len      = 2,
-        .vsync_len      = 1,
-        .xres           = 480,
-        .yres           = 800,
-        .refresh        = 55,
-};
-
-static struct s3c_fb_platdata universal_lcd_pdata __initdata = {
-        .win[0]         = &universal_fb_win0,
-        .vtiming        = &universal_lcd_timing,
-        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB |
-                          VIDCON0_CLKSEL_LCD,
-        .vidcon1        = VIDCON1_INV_VCLK | VIDCON1_INV_VDEN
-                          | VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
-        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
-};
-#endif
-
-static struct regulator_consumer_supply cam_vt_dio_supply =
-        REGULATOR_SUPPLY("vdd_core", "0-003c");
-
-static struct regulator_init_data cam_vt_dio_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_vt_dio_supply,
-};
-
-static struct fixed_voltage_config cam_vt_dio_fixed_voltage_cfg = {
-        .supply_name    = "CAM_VT_D_IO",
-        .microvolts     = 2800000,
-        .gpio           = EXYNOS4_GPE2(1), /* CAM_PWR_EN2 */
-        .enable_high    = 1,
-        .init_data      = &cam_vt_dio_reg_init_data,
-};
-
-static struct platform_device cam_vt_dio_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_VT_DIO,
-        .dev = { .platform_data = &cam_vt_dio_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_i_core_supply =
-        REGULATOR_SUPPLY("core", "0-001f");
-
-static struct regulator_init_data cam_i_core_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_i_core_supply,
-};
-
-static struct fixed_voltage_config cam_i_core_fixed_voltage_cfg = {
-        .supply_name    = "CAM_I_CORE_1.2V",
-        .microvolts     = 1200000,
-        .gpio           = EXYNOS4_GPE2(2),      /* CAM_8M_CORE_EN */
-        .enable_high    = 1,
-        .init_data      = &cam_i_core_reg_init_data,
-};
-
-static struct platform_device cam_i_core_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_I_CORE,
-        .dev = { .platform_data = &cam_i_core_fixed_voltage_cfg },
-};
-
-static struct regulator_consumer_supply cam_s_if_supply =
-        REGULATOR_SUPPLY("d_sensor", "0-001f");
-
-static struct regulator_init_data cam_s_if_reg_init_data = {
-        .constraints = { .valid_ops_mask = REGULATOR_CHANGE_STATUS },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &cam_s_if_supply,
-};
-
-static struct fixed_voltage_config cam_s_if_fixed_voltage_cfg = {
-        .supply_name    = "CAM_S_IF_1.8V",
-        .microvolts     = 1800000,
-        .gpio           = EXYNOS4_GPE3(0),      /* CAM_PWR_EN1 */
-        .enable_high    = 1,
-        .init_data      = &cam_s_if_reg_init_data,
-};
-
-static struct platform_device cam_s_if_fixed_reg_dev = {
-        .name = "reg-fixed-voltage", .id = FIXED_REG_ID_CAM_S_IF,
-        .dev = { .platform_data = &cam_s_if_fixed_voltage_cfg },
-};
-
-static struct s5p_platform_mipi_csis mipi_csis_platdata = {
-        .clk_rate       = 166000000UL,
-        .lanes          = 2,
-        .hs_settle      = 12,
-};
-
-#define GPIO_CAM_LEVEL_EN(n)    EXYNOS4_GPE4(n + 3)
-#define GPIO_CAM_8M_ISP_INT     EXYNOS4_GPX1(5) /* XEINT_13 */
-#define GPIO_CAM_MEGA_nRST      EXYNOS4_GPE2(5)
-#define GPIO_CAM_VGA_NRST       EXYNOS4_GPE4(7)
-#define GPIO_CAM_VGA_NSTBY      EXYNOS4_GPE4(6)
-
-static int s5k6aa_set_power(int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-
-static struct s5k6aa_platform_data s5k6aa_platdata = {
-        .mclk_frequency = 21600000UL,
-        .gpio_reset     = { GPIO_CAM_VGA_NRST, 0 },
-        .gpio_stby      = { GPIO_CAM_VGA_NSTBY, 0 },
-        .bus_type       = V4L2_MBUS_PARALLEL,
-        .horiz_flip     = 1,
-        .set_power      = s5k6aa_set_power,
-};
-
-static struct i2c_board_info s5k6aa_board_info = {
-        I2C_BOARD_INFO("S5K6AA", 0x3C),
-        .platform_data = &s5k6aa_platdata,
-};
-
-static int m5mols_set_power(struct device *dev, int on)
-{
-        gpio_set_value(GPIO_CAM_LEVEL_EN(1), !on);
-        gpio_set_value(GPIO_CAM_LEVEL_EN(2), !!on);
-        return 0;
-}
-
-static struct m5mols_platform_data m5mols_platdata = {
-        .gpio_reset     = GPIO_CAM_MEGA_nRST,
-        .reset_polarity = 0,
-        .set_power      = m5mols_set_power,
-};
-
-static struct i2c_board_info m5mols_board_info = {
-        I2C_BOARD_INFO("M5MOLS", 0x1F),
-        .platform_data = &m5mols_platdata,
-};
-
-static struct fimc_source_info universal_camera_sensors[] = {
-        {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &s5k6aa_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        }, {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_MIPI_CSI2,
-                .board_info     = &m5mols_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 24000000UL,
-        },
-};
-
-static struct s5p_platform_fimc fimc_md_platdata = {
-        .source_info    = universal_camera_sensors,
-        .num_clients    = ARRAY_SIZE(universal_camera_sensors),
-};
-
-static struct gpio universal_camera_gpios[] = {
-        { GPIO_CAM_LEVEL_EN(1), GPIOF_OUT_INIT_HIGH, "CAM_LVL_EN1" },
-        { GPIO_CAM_LEVEL_EN(2), GPIOF_OUT_INIT_LOW,  "CAM_LVL_EN2" },
-        { GPIO_CAM_8M_ISP_INT,  GPIOF_IN,            "8M_ISP_INT"  },
-        { GPIO_CAM_MEGA_nRST,   GPIOF_OUT_INIT_LOW,  "CAM_8M_NRST" },
-        { GPIO_CAM_VGA_NRST,    GPIOF_OUT_INIT_LOW,  "CAM_VGA_NRST"  },
-        { GPIO_CAM_VGA_NSTBY,   GPIOF_OUT_INIT_LOW,  "CAM_VGA_NSTBY" },
-};
-
-/* USB OTG */
-static struct s3c_hsotg_plat universal_hsotg_pdata;
-
-static void __init universal_camera_init(void)
-{
-        s3c_set_platdata(&mipi_csis_platdata, sizeof(mipi_csis_platdata),
-                         &s5p_device_mipi_csis0);
-        s3c_set_platdata(&fimc_md_platdata,  sizeof(fimc_md_platdata),
-                         &s5p_device_fimc_md);
-
-        if (gpio_request_array(universal_camera_gpios,
-                               ARRAY_SIZE(universal_camera_gpios))) {
-                pr_err("%s: GPIO request failed\n", __func__);
-                return;
-        }
-
-        if (!s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xf)))
-                m5mols_board_info.irq = gpio_to_irq(GPIO_CAM_8M_ISP_INT);
-        else
-                pr_err("Failed to configure 8M_ISP_INT GPIO\n");
-
-        /* Free GPIOs controlled directly by the sensor drivers. */
-        gpio_free(GPIO_CAM_MEGA_nRST);
-        gpio_free(GPIO_CAM_8M_ISP_INT);
-        gpio_free(GPIO_CAM_VGA_NRST);
-        gpio_free(GPIO_CAM_VGA_NSTBY);
-
-        if (exynos4_fimc_setup_gpio(S5P_CAMPORT_A))
-                pr_err("Camera port A setup failed\n");
-}
-
-static struct platform_device *universal_devices[] __initdata = {
-        /* Samsung Platform Devices */
-        &s5p_device_mipi_csis0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc3,
-        &s5p_device_g2d,
-        &mmc0_fixed_voltage,
-        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc2,
-        &s3c_device_hsmmc3,
-        &s3c_device_i2c0,
-        &s3c_device_i2c3,
-        &s3c_device_i2c5,
-        &s5p_device_i2c_hdmiphy,
-        &hdmi_fixed_voltage,
-        &s5p_device_hdmi,
-        &s5p_device_sdo,
-        &s5p_device_mixer,
-
-        /* Universal Devices */
-        &i2c_gpio12,
-        &universal_gpio_keys,
-        &s5p_device_onenand,
-        &s5p_device_fimd0,
-        &s5p_device_jpeg,
-        &s3c_device_usb_hsotg,
-        &s5p_device_mfc,
-        &s5p_device_mfc_l,
-        &s5p_device_mfc_r,
-        &cam_vt_dio_fixed_reg_dev,
-        &cam_i_core_fixed_reg_dev,
-        &cam_s_if_fixed_reg_dev,
-        &s5p_device_fimc_md,
-};
-
-static void __init universal_map_io(void)
-{
-        exynos_init_io(NULL, 0);
-        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
-        exynos_set_timer_source(BIT(2) | BIT(4));
-        xxti_f = 0;
-        xusbxti_f = 24000000;
-}
-
-static void s5p_tv_setup(void)
-{
-        /* direct HPD to HDMI chip */
-        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
-        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
-}
-
-static void __init universal_reserve(void)
-{
-        s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
-}
-
-static void __init universal_machine_init(void)
-{
-        universal_sdhci_init();
-        s5p_tv_setup();
-
-        s3c_i2c0_set_platdata(&universal_i2c0_platdata);
-        i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
-
-        universal_tsp_init();
-        s3c_i2c3_set_platdata(NULL);
-        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
-
-        s3c_i2c5_set_platdata(NULL);
-        s5p_i2c_hdmiphy_set_platdata(NULL);
-        i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
-
-#ifdef CONFIG_DRM_EXYNOS
-        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
-        exynos4_fimd0_gpio_setup_24bpp();
-#else
-        s5p_fimd0_set_platdata(&universal_lcd_pdata);
-#endif
-
-        universal_touchkey_init();
-        i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
-                        ARRAY_SIZE(i2c_gpio12_devs));
-
-        s3c_hsotg_set_platdata(&universal_hsotg_pdata);
-        universal_camera_init();
-
-        /* Last */
-        platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
-}
-
-MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
-        /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(exynos_smp_ops),
-        .init_irq       = exynos4_init_irq,
-        .map_io         = universal_map_io,
-        .init_machine   = universal_machine_init,
-        .init_late      = exynos_init_late,
-        .init_time      = exynos_init_time,
-        .reserve        = &universal_reserve,
-        .restart        = exynos4_restart,
-MACHINE_END
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index a0e8ff7758a4..deba1308ff16 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -50,6 +50,8 @@ static inline void __iomem *cpu_boot_reg(int cpu)
         boot_reg = cpu_boot_reg_base();
         if (soc_is_exynos4412())
                 boot_reg += 4*cpu;
+        else if (soc_is_exynos5420())
+                boot_reg += 4;
         return boot_reg;
 }
 
@@ -180,10 +182,14 @@ static void __init exynos_smp_init_cpus(void)
         void __iomem *scu_base = scu_base_addr();
         unsigned int i, ncores;
 
-        if (soc_is_exynos5250())
-                ncores = 2;
-        else
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+        else
+                /*
+                 * CPU Nodes are passed thru DT and set_cpu_possible
+                 * is set by "arm_dt_init_cpu_maps".
+                 */
+                return;
 
         /* sanity check */
         if (ncores > nr_cpu_ids) {
@@ -200,7 +206,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
 {
         int i;
 
-        if (!(soc_is_exynos5250() || soc_is_exynos5440()))
+        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                 scu_enable(scu_base_addr());
 
         /*
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index e3faaa812016..41c20692a13f 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -30,7 +30,6 @@
 #include <plat/regs-srom.h>
 
 #include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-pmu.h>
 #include <mach/pm-core.h>
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 9f1351de52f7..1703593e366c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -74,17 +74,6 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain)
         return exynos_pd_power(domain, false);
 }
 
-#define EXYNOS_GPD(PD, BASE, NAME)                      \
-static struct exynos_pm_domain PD = {                   \
-        .base = (void __iomem *)BASE,                   \
-        .name = NAME,                                   \
-        .pd = {                                         \
-                .power_off = exynos_pd_power_off,       \
-                .power_on = exynos_pd_power_on, \
-        },                                              \
-}
-
-#ifdef CONFIG_OF
 static void exynos_add_device_to_domain(struct exynos_pm_domain *pd,
                                          struct device *dev)
 {
@@ -157,7 +146,7 @@ static struct notifier_block platform_nb = {
         .notifier_call = exynos_pm_notifier_call,
 };
 
-static __init int exynos_pm_dt_parse_domains(void)
+static __init int exynos4_pm_init_power_domain(void)
 {
         struct platform_device *pdev;
         struct device_node *np;
@@ -193,94 +182,6 @@ static __init int exynos_pm_dt_parse_domains(void)
 
         return 0;
 }
-#else
-static __init int exynos_pm_dt_parse_domains(void)
-{
-        return 0;
-}
-#endif /* CONFIG_OF */
-
-static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
-                                                struct exynos_pm_domain *pd)
-{
-        if (pdev->dev.bus) {
-                if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
-                        pm_genpd_dev_need_restore(&pdev->dev, true);
-                else
-                        pr_info("%s: error in adding %s device to %s power"
-                                "domain\n", __func__, dev_name(&pdev->dev),
-                                pd->name);
-        }
-}
-
-EXYNOS_GPD(exynos4_pd_mfc, S5P_PMU_MFC_CONF, "pd-mfc");
-EXYNOS_GPD(exynos4_pd_g3d, S5P_PMU_G3D_CONF, "pd-g3d");
-EXYNOS_GPD(exynos4_pd_lcd0, S5P_PMU_LCD0_CONF, "pd-lcd0");
-EXYNOS_GPD(exynos4_pd_lcd1, S5P_PMU_LCD1_CONF, "pd-lcd1");
-EXYNOS_GPD(exynos4_pd_tv, S5P_PMU_TV_CONF, "pd-tv");
-EXYNOS_GPD(exynos4_pd_cam, S5P_PMU_CAM_CONF, "pd-cam");
-EXYNOS_GPD(exynos4_pd_gps, S5P_PMU_GPS_CONF, "pd-gps");
-
-static struct exynos_pm_domain *exynos4_pm_domains[] = {
-        &exynos4_pd_mfc,
-        &exynos4_pd_g3d,
-        &exynos4_pd_lcd0,
-        &exynos4_pd_lcd1,
-        &exynos4_pd_tv,
-        &exynos4_pd_cam,
-        &exynos4_pd_gps,
-};
-
-static __init int exynos4_pm_init_power_domain(void)
-{
-        int idx;
-
-        if (of_have_populated_dt())
-                return exynos_pm_dt_parse_domains();
-
-        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
-                struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
-                int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
-
-                pm_genpd_init(&pd->pd, NULL, !on);
-        }
-
-#ifdef CONFIG_S5P_DEV_FIMD0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_TV
-        exynos_pm_add_dev_to_genpd(&s5p_device_hdmi, &exynos4_pd_tv);
-        exynos_pm_add_dev_to_genpd(&s5p_device_mixer, &exynos4_pd_tv);
-#endif
-#ifdef CONFIG_S5P_DEV_MFC
-        exynos_pm_add_dev_to_genpd(&s5p_device_mfc, &exynos4_pd_mfc);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC0
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC1
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC2
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc2, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_FIMC3
-        exynos_pm_add_dev_to_genpd(&s5p_device_fimc3, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS0
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis0, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_CSIS1
-        exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
-#endif
-#ifdef CONFIG_S5P_DEV_G2D
-        exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
-#endif
-#ifdef CONFIG_S5P_DEV_JPEG
-        exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
-#endif
-        return 0;
-}
 arch_initcall(exynos4_pm_init_power_domain);
 
 int __init exynos_pm_late_initcall(void)
diff --git a/arch/arm/mach-exynos/setup-fimc.c b/arch/arm/mach-exynos/setup-fimc.c
deleted file mode 100644
index 6a45078d9d12..000000000000
--- a/arch/arm/mach-exynos/setup-fimc.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co., Ltd.
- *
- * Exynos4 camera interface GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/camport.h>
-
-int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
-{
-        u32 gpio8, gpio5;
-        u32 sfn;
-        int ret;
-
-        switch (id) {
-        case S5P_CAMPORT_A:
-                gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
-                gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(2);
-                break;
-
-        case S5P_CAMPORT_B:
-                gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
-                gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
-                sfn = S3C_GPIO_SFN(3);
-                break;
-
-        default:
-                WARN(1, "Wrong camport id: %d\n", id);
-                return -EINVAL;
-        }
-
-        ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
-        if (ret)
-                return ret;
-
-        return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-fimd0.c b/arch/arm/mach-exynos/setup-fimd0.c
deleted file mode 100644
index 5665bb4e980b..000000000000
--- a/arch/arm/mach-exynos/setup-fimd0.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-fimd0.c
- *
- * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
- *             http://www.samsung.com
- *
- * Base Exynos4 FIMD 0 configuration
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/fb.h>
-#include <linux/gpio.h>
-
-#include <video/samsung_fimd.h>
-#include <plat/gpio-cfg.h>
-
-#include <mach/map.h>
-
-void exynos4_fimd0_gpio_setup_24bpp(void)
-{
-        unsigned int reg;
-
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
-
-        /*
-         * Set DISPLAY_CONTROL register for Display path selection.
-         *
-         * DISPLAY_CONTROL[1:0]
-         * ---------------------
-         *  00 | MIE
-         *  01 | MDINE
-         *  10 | FIMD : selected
-         *  11 | FIMD
-         */
-        reg = __raw_readl(S3C_VA_SYS + 0x0210);
-        reg |= (1 << 1);
-        __raw_writel(reg, S3C_VA_SYS + 0x0210);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c0.c b/arch/arm/mach-exynos/setup-i2c0.c
deleted file mode 100644
index e2d9dfbf102c..000000000000
--- a/arch/arm/mach-exynos/setup-i2c0.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        if (soc_is_exynos5250() || soc_is_exynos5440())
-                /* will be implemented with gpio function */
-                return;
-
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c1.c b/arch/arm/mach-exynos/setup-i2c1.c
deleted file mode 100644
index 8d2279cc85dc..000000000000
--- a/arch/arm/mach-exynos/setup-i2c1.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c1.c
- *
- * Copyright (C) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C1 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c1_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c2.c b/arch/arm/mach-exynos/setup-i2c2.c
deleted file mode 100644
index 0ed62fc42a77..000000000000
--- a/arch/arm/mach-exynos/setup-i2c2.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c2.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *
- * I2C2 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c2_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c3.c b/arch/arm/mach-exynos/setup-i2c3.c
deleted file mode 100644
index 7787fd26076b..000000000000
--- a/arch/arm/mach-exynos/setup-i2c3.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c3.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C3 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c3_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c4.c b/arch/arm/mach-exynos/setup-i2c4.c
deleted file mode 100644
index edc847f89826..000000000000
--- a/arch/arm/mach-exynos/setup-i2c4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c4.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C4 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c4_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c5.c b/arch/arm/mach-exynos/setup-i2c5.c
deleted file mode 100644
index d88af7f75954..000000000000
--- a/arch/arm/mach-exynos/setup-i2c5.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c5.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C5 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c5_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c6.c b/arch/arm/mach-exynos/setup-i2c6.c
deleted file mode 100644
index c590286c9d3a..000000000000
--- a/arch/arm/mach-exynos/setup-i2c6.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c6.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C6 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c6_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-i2c7.c b/arch/arm/mach-exynos/setup-i2c7.c
deleted file mode 100644
index 1bba75568a5f..000000000000
--- a/arch/arm/mach-exynos/setup-i2c7.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * linux/arch/arm/mach-exynos4/setup-i2c7.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *
- * I2C7 GPIO configuration.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct platform_device; /* don't need the contents */
-
-#include <linux/gpio.h>
-#include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/gpio-cfg.h>
-
-void s3c_i2c7_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
-                              S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-exynos/setup-keypad.c b/arch/arm/mach-exynos/setup-keypad.c
deleted file mode 100644
index 7862bfb5933d..000000000000
--- a/arch/arm/mach-exynos/setup-keypad.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-keypad.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * GPIO configuration for Exynos4 KeyPad device
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
-{
-        /* Keypads can be of various combinations, Just making sure */
-
-        if (rows > 8) {
-                /* Set all the necessary GPX2 pins: KP_ROW[0~7] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-
-                /* Set all the necessary GPX3 pins: KP_ROW[8~] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX3(0), (rows - 8),
-                                         S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-        } else {
-                /* Set all the necessary GPX2 pins: KP_ROW[x] */
-                s3c_gpio_cfgall_range(EXYNOS4_GPX2(0), rows, S3C_GPIO_SFN(3),
-                                        S3C_GPIO_PULL_UP);
-        }
-
-        /* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
-        s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
-}
diff --git a/arch/arm/mach-exynos/setup-sdhci-gpio.c b/arch/arm/mach-exynos/setup-sdhci-gpio.c
deleted file mode 100644
index d5b98c866738..000000000000
--- a/arch/arm/mach-exynos/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/card.h>
-
-#include <mach/gpio.h>
-#include <plat/gpio-cfg.h>
-#include <plat/sdhci.h>
-
-void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK0[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                        /* Data pin GPK1[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
-                        /* Data pin GPK0[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK1[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
-                /* Data pin GPK1[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK2[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        switch (width) {
-        case 8:
-                for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                        /* Data pin GPK3[3:6] to special-function 3 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        case 4:
-                for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
-                        /* Data pin GPK2[3:6] to special-function 2 */
-                        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                        s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-                }
-        default:
-                break;
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
-
-void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
-{
-        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
-        unsigned int gpio;
-
-        /* Set all the necessary GPK3[0:1] pins to special-function 2 */
-        for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
-                /* Data pin GPK3[3:6] to special-function 2 */
-                s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-
-        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
-                s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
-                s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
-        }
-}
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
deleted file mode 100644
index 4999829d1c6e..000000000000
--- a/arch/arm/mach-exynos/setup-spi.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-spi.c
- *
- * Copyright (C) 2011 Samsung Electronics Ltd.
- *             http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/gpio.h>
-#include <plat/gpio-cfg.h>
-
-#ifdef CONFIG_S3C64XX_DEV_SPI0
-int s3c64xx_spi0_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI1
-int s3c64xx_spi1_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
-        s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
-
-#ifdef CONFIG_S3C64XX_DEV_SPI2
-int s3c64xx_spi2_cfg_gpio(void)
-{
-        s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
-        s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
-        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
-                              S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
-        return 0;
-}
-#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
deleted file mode 100644
index 6af40662a449..000000000000
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <mach/regs-pmu.h>
-#include <mach/regs-usb-phy.h>
-#include <plat/cpu.h>
-#include <plat/usb-phy.h>
-
-static atomic_t host_usage;
-
-static int exynos4_usb_host_phy_is_on(void)
-{
-        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
-}
-
-static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
-{
-        struct clk *xusbxti_clk;
-        u32 phyclk;
-
-        xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
-        if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                if (soc_is_exynos4210()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
-
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_12M;
-                                break;
-                        case 48 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_48M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                phyclk |= EXYNOS4210_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
-                        /* set clock frequency for PLL */
-                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
-
-                        switch (clk_get_rate(xusbxti_clk)) {
-                        case 9600 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
-                                break;
-                        case 10 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_10M;
-                                break;
-                        case 12 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_12M;
-                                break;
-                        case 19200 * KHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
-                                break;
-                        case 20 * MHZ:
-                                phyclk |= EXYNOS4X12_CLKSEL_20M;
-                                break;
-                        default:
-                        case 24 * MHZ:
-                                /* default reference clock */
-                                phyclk |= EXYNOS4X12_CLKSEL_24M;
-                                break;
-                        }
-                        writel(phyclk, EXYNOS4_PHYCLK);
-                }
-                clk_put(xusbxti_clk);
-        }
-}
-
-static int exynos4210_usb_phy0_init(struct platform_device *pdev)
-{
-        u32 rstcon;
-
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) | S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-
-        exynos4210_usb_phy_clkset(pdev);
-
-        /* set to normal PHY0 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK), EXYNOS4_PHYPWR);
-
-        /* reset PHY0 and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-
-        rstcon &= ~PHY0_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy0_exit(struct platform_device *pdev)
-{
-        writel((readl(EXYNOS4_PHYPWR) | PHY0_ANALOG_POWERDOWN |
-                                PHY0_OTG_DISABLE), EXYNOS4_PHYPWR);
-
-        writel(readl(S5P_USBDEVICE_PHY_CONTROL) & ~S5P_USBDEVICE_PHY_ENABLE,
-                        S5P_USBDEVICE_PHY_CONTROL);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy1_init(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        u32 rstcon;
-        int err;
-
-        atomic_inc(&host_usage);
-
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-
-        if (exynos4_usb_host_phy_is_on())
-                return 0;
-
-        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-
-        exynos4210_usb_phy_clkset(pdev);
-
-        /* floating prevention logic: disable */
-        writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
-
-        /* set to normal HSIC 0 and 1 of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
-                        EXYNOS4_PHYPWR);
-
-        /* set to normal standard USB of PHY1 */
-        writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
-
-        /* reset all ports of both PHY and Link */
-        rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
-                PHY1_SWRST_MASK;
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(10);
-
-        rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
-        writel(rstcon, EXYNOS4_RSTCON);
-        udelay(80);
-
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-
-        return 0;
-}
-
-static int exynos4210_usb_phy1_exit(struct platform_device *pdev)
-{
-        struct clk *otg_clk;
-        int err;
-
-        if (atomic_dec_return(&host_usage) > 0)
-                return 0;
-
-        otg_clk = clk_get(&pdev->dev, "otg");
-        if (IS_ERR(otg_clk)) {
-                dev_err(&pdev->dev, "Failed to get otg clock\n");
-                return PTR_ERR(otg_clk);
-        }
-
-        err = clk_enable(otg_clk);
-        if (err) {
-                clk_put(otg_clk);
-                return err;
-        }
-
-        writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
-                        EXYNOS4_PHYPWR);
-
-        writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
-                        S5P_USBHOST_PHY_CONTROL);
-
-        clk_disable(otg_clk);
-        clk_put(otg_clk);
-
-        return 0;
-}
-
-int s5p_usb_phy_init(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_init(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_init(pdev);
-
-        return -EINVAL;
-}
-
-int s5p_usb_phy_exit(struct platform_device *pdev, int type)
-{
-        if (type == USB_PHY_TYPE_DEVICE)
-                return exynos4210_usb_phy0_exit(pdev);
-        else if (type == USB_PHY_TYPE_HOST)
-                return exynos4210_usb_phy1_exit(pdev);
-
-        return -EINVAL;
-}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index e7df2dd43a40..dc5d6becd8c7 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -176,7 +176,6 @@ static const char *highbank_match[] __initconst = {
 
 DT_MACHINE_START(HIGHBANK, "Highbank")
         .smp            = smp_ops(highbank_smp_ops),
-        .map_io         = debug_ll_io_init,
         .init_irq       = highbank_init_irq,
         .init_time      = highbank_timer_init,
         .init_machine   = highbank_init,
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328464f3..60661a4b0e24 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -56,9 +56,6 @@ config MXC_USE_EPIT
           uses the same clocks as the GPT. Anyway, on some systems the GPT
           may be in use for other purposes.
 
-config MXC_ULPI
-        bool
-
 config ARCH_HAS_RNGA
         bool
 
@@ -176,6 +173,7 @@ config ARCH_MX1ADS
 config MACH_SCB9328
         bool "Synertronixx scb9328"
         select IMX_HAVE_PLATFORM_IMX_UART
+        select SOC_IMX1
         help
           Say Y here if you are using a Synertronixx scb9328 board
 
@@ -233,7 +231,7 @@ config MACH_EUKREA_CPUIMX25SD
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX25
 
 choice
@@ -284,7 +282,7 @@ config MACH_PCM038
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -314,7 +312,7 @@ config MACH_CPUIMX27
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for Eukrea CPUIMX27 platform. This includes
@@ -369,7 +367,7 @@ config MACH_MX27_3DS
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for MX27PDK platform. This includes specific
@@ -414,7 +412,7 @@ config MACH_PCA100
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX27
         help
           Include support for phyCARD-s (aka pca100) platform. This
@@ -481,7 +479,7 @@ config MACH_MX31LILLY
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for mx31 based LILLY1131 modules. This includes
@@ -497,7 +495,7 @@ config MACH_MX31LITE
         select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for MX31 LITEKIT platform. This includes specific
@@ -514,7 +512,7 @@ config MACH_PCM037
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_MXC_W1
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for Phytec pcm037 platform. This includes
@@ -544,7 +542,7 @@ config MACH_MX31_3DS
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_DEBUG_BOARD
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for MX31PDK (3DS) platform. This includes specific
@@ -571,7 +569,7 @@ config MACH_MX31MOBOARD
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_SPI_IMX
         select LEDS_GPIO_REGISTER
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for mx31moboard platform. This includes specific
@@ -595,7 +593,7 @@ config MACH_ARMADILLO5X0
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_MMC
         select IMX_HAVE_PLATFORM_MXC_NAND
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX31
         help
           Include support for Atmark Armadillo-500 platform. This includes
@@ -639,7 +637,7 @@ config MACH_PCM043
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX35
         help
           Include support for Phytec pcm043 platform. This includes
@@ -673,7 +671,7 @@ config MACH_EUKREA_CPUIMX35SD
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select MXC_ULPI if USB_ULPI
+        select USB_ULPI_VIEWPORT if USB_ULPI
         select SOC_IMX35
         help
           Include support for Eukrea CPUIMX35 platform. This includes
@@ -816,6 +814,41 @@ config SOC_IMX6Q
         help
           This enables support for Freescale i.MX6 Quad processor.
 
+config SOC_IMX6SL
+        bool "i.MX6 SoloLite support"
+        select ARM_ERRATA_754322
+        select ARM_ERRATA_775420
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_IMX_ANATOP
+        select HAVE_IMX_GPC
+        select HAVE_IMX_MMDC
+        select HAVE_IMX_SRC
+        select MFD_SYSCON
+        select PINCTRL
+        select PINCTRL_IMX6SL
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+
+        help
+          This enables support for Freescale i.MX6 SoloLite processor.
+
+config SOC_VF610
+        bool "Vybrid Family VF610 support"
+        select CPU_V7
+        select ARM_GIC
+        select CLKSRC_OF
+        select PINCTRL
+        select PINCTRL_VF610
+        select VF_PIT_TIMER
+        select PL310_ERRATA_588369 if CACHE_PL310
+        select PL310_ERRATA_727915 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+
+        help
+          This enable support for Freescale Vybrid VF610 processor.
+
 endif
 
 source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c490ac0..e20f22d58fd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
 
-obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 
@@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
+obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
 
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
@@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
 
+obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
+
 obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b6a3c6..9afac26fa1cc 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
         "tve_sel", "lp_apm",
         "uart_root", "dummy"/* spdif0_clk_root */,
         "dummy", "dummy", };
+static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
+static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
+static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
+static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
+static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
+
 
 enum imx5_clks {
         dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
         owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
         cko1_sel, cko1_podf, cko1,
         cko2_sel, cko2_podf, cko2,
-        srtc_gate, pata_gate,
+        srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
+        spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
+        spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
         clk_max
 };
 
@@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 {
         int i;
 
+        of_clk_init(NULL);
+
         clk[dummy] = imx_clk_fixed("dummy", 0);
-        clk[ckil] = imx_clk_fixed("ckil", rate_ckil);
-        clk[osc] = imx_clk_fixed("osc", rate_osc);
-        clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1);
-        clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2);
+        clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
+        clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
+        clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
+        clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
 
         clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
                                 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
         clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
         clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
+        clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
+        clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
+        clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
+                                spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
+        clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
+        clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -310,8 +327,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
-        clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
-        clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
         clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
@@ -378,6 +393,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
         clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
         clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
+        clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
+                                spdif_sel, ARRAY_SIZE(spdif_sel));
+        clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
+        clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
+        clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
+                                mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
+        clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -485,6 +509,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
         clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
         clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
+        clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
 
         clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
                                 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -495,6 +520,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
                                 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
         clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
         clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
+        clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
+                                mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
@@ -542,42 +569,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         return 0;
 }
 
-#ifdef CONFIG_OF
-static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
-                                   unsigned long *ckih1, unsigned long *ckih2)
-{
-        struct device_node *np;
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        *ckil = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        *osc = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        *ckih1 = rate;
-                else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
-                        *ckih2 = rate;
-        }
-}
-
 int __init mx51_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx51_clocks_init(ckil, osc, ckih1, ckih2);
+        return mx51_clocks_init(0, 0, 0, 0);
 }
 
 int __init mx53_clocks_init_dt(void)
 {
-        unsigned long ckil, osc, ckih1, ckih2;
-
-        clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
-        return mx53_clocks_init(ckil, osc, ckih1, ckih2);
+        return mx53_clocks_init(0, 0, 0, 0);
 }
-#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e3148ce852d..4282e99f5ca1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -238,7 +238,7 @@ enum mx6q_clks {
         pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
         ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
         sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
-        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max
+        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
 };
 
 static struct clk *clk[clk_max];
@@ -270,27 +270,16 @@ static struct clk_div_table video_div_table[] = {
         { }
 };
 
-int __init mx6q_clocks_init(void)
+static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
         struct device_node *np;
         void __iomem *base;
         int i, irq;
 
         clk[dummy] = imx_clk_fixed("dummy", 0);
-
-        /* retrieve the freqency of fixed clocks from device tree */
-        for_each_compatible_node(np, NULL, "fixed-clock") {
-                u32 rate;
-                if (of_property_read_u32(np, "clock-frequency", &rate))
-                        continue;
-
-                if (of_device_is_compatible(np, "fsl,imx-ckil"))
-                        clk[ckil] = imx_clk_fixed("ckil", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
-                        clk[ckih] = imx_clk_fixed("ckih", rate);
-                else if (of_device_is_compatible(np, "fsl,imx-osc"))
-                        clk[osc] = imx_clk_fixed("osc", rate);
-        }
+        clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
+        clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
+        clk[osc] = imx_obtain_fixed_clock("osc", 0);
 
         np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
         base = of_iomap(np, 0);
@@ -312,7 +301,6 @@ int __init mx6q_clocks_init(void)
         clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,        "pll5_video",   "osc", base + 0xa0, 0x7f);
         clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll6_enet",    "osc", base + 0xe0, 0x3);
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x3);
-        clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,       "pll8_mlb",     "osc", base + 0xd0, 0x0);
 
         /*
          * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -360,7 +348,7 @@ int __init mx6q_clocks_init(void)
         clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
         clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm");
+        np = ccm_node;
         base = of_iomap(np, 0);
         WARN_ON(!base);
         ccm_base = base;
@@ -481,7 +469,14 @@ int __init mx6q_clocks_init(void)
         clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
         clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
         clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
-        clk[gpu2d_core]   = imx_clk_gate2("gpu2d_core",    "gpu2d_core_podf",   base + 0x6c, 24);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of imx6q clock gpu3d_shader get
+                 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
+                 */
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
+        else
+                clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
         clk[gpu3d_core]   = imx_clk_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
         clk[hdmi_iahb]    = imx_clk_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
         clk[hdmi_isfr]    = imx_clk_gate2("hdmi_isfr",     "pll3_pfd1_540m",    base + 0x70, 4);
@@ -499,7 +494,14 @@ int __init mx6q_clocks_init(void)
         clk[ldb_di1]      = imx_clk_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
         clk[ipu2_di1]     = imx_clk_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
         clk[hsi_tx]       = imx_clk_gate2("hsi_tx",        "hsi_tx_podf",       base + 0x74, 16);
-        clk[mlb]          = imx_clk_gate2("mlb",           "axi",               base + 0x74, 18);
+        if (cpu_is_imx6dl())
+                /*
+                 * The multiplexer and divider of the imx6q clock gpu2d get
+                 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
+                 */
+                clk[mlb] = imx_clk_gate2("mlb",            "gpu2d_core_podf",   base + 0x74, 18);
+        else
+                clk[mlb] = imx_clk_gate2("mlb",            "axi",               base + 0x74, 18);
         clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20);
         clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
@@ -528,6 +530,7 @@ int __init mx6q_clocks_init(void)
         clk[usdhc2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
         clk[usdhc3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
         clk[usdhc4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clk[eim_slow]     = imx_clk_gate2("eim_slow",      "emi_slow_podf",     base + 0x80, 10);
         clk[vdo_axi]      = imx_clk_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
         clk[vpu_axi]      = imx_clk_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
         clk[cko1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
@@ -547,6 +550,8 @@ int __init mx6q_clocks_init(void)
         clk_register_clkdev(clk[ahb], "ahb", NULL);
         clk_register_clkdev(clk[cko1], "cko1", NULL);
         clk_register_clkdev(clk[arm], NULL, "cpu0");
+        clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
+        clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
 
         if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
                 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
@@ -576,6 +581,5 @@ int __init mx6q_clocks_init(void)
         WARN_ON(!base);
         irq = irq_of_parse_and_map(np, 0);
         mxc_timer_init(base, irq);
-
-        return 0;
 }
+CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 000000000000..a307ac22dffe
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <dt-bindings/clock/imx6sl-clock.h>
+
+#include "clk.h"
+#include "common.h"
+
+static const char const *step_sels[]            = { "osc", "pll2_pfd2", };
+static const char const *pll1_sw_sels[]         = { "pll1_sys", "step", };
+static const char const *ocram_alt_sels[]       = { "pll2_pfd2", "pll3_pfd1", };
+static const char const *ocram_sels[]           = { "periph", "ocram_alt_sels", };
+static const char const *pre_periph_sels[]      = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
+static const char const *periph_clk2_sels[]     = { "pll3_usb_otg", "osc", "osc", "dummy", };
+static const char const *periph2_clk2_sels[]    = { "pll3_usb_otg", "pll2_bus", };
+static const char const *periph_sels[]          = { "pre_periph_sel", "periph_clk2_podf", };
+static const char const *periph2_sels[]         = { "pre_periph2_sel", "periph2_clk2_podf", };
+static const char const *csi_lcdif_sels[]       = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
+static const char const *usdhc_sels[]           = { "pll2_pfd2", "pll2_pfd0", };
+static const char const *ssi_sels[]             = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
+static const char const *perclk_sels[]          = { "ipg", "osc", };
+static const char const *epdc_pxp_sels[]        = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
+static const char const *gpu2d_ovg_sels[]       = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
+static const char const *gpu2d_sels[]           = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
+static const char const *lcdif_pix_sels[]       = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
+static const char const *epdc_pix_sels[]        = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
+static const char const *audio_sels[]           = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
+static const char const *ecspi_sels[]           = { "pll3_60m", "osc", };
+static const char const *uart_sels[]            = { "pll3_80m", "osc", };
+
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+        { }
+};
+
+static struct clk_div_table post_div_table[] = {
+        { .val = 2, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 0, .div = 4, },
+        { }
+};
+
+static struct clk_div_table video_div_table[] = {
+        { .val = 0, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 2, .div = 1, },
+        { .val = 3, .div = 4, },
+        { }
+};
+
+static struct clk *clks[IMX6SL_CLK_CLK_END];
+static struct clk_onecell_data clk_data;
+
+static void __init imx6sl_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int irq;
+        int i;
+
+        clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
+        clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        /*                                             type               name            parent  base         div_mask */
+        clks[IMX6SL_CLK_PLL1_SYS]      = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc", base,        0x7f);
+        clks[IMX6SL_CLK_PLL2_BUS]      = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc", base + 0x30, 0x1);
+        clks[IMX6SL_CLK_PLL3_USB_OTG]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc", base + 0x10, 0x3);
+        clks[IMX6SL_CLK_PLL4_AUDIO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc", base + 0x70, 0x7f);
+        clks[IMX6SL_CLK_PLL5_VIDEO]    = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc", base + 0xa0, 0x7f);
+        clks[IMX6SL_CLK_PLL6_ENET]     = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc", base + 0xe0, 0x3);
+        clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc", base + 0x20, 0x3);
+
+        /*
+         * usbphy1 and usbphy2 are implemented as dummy gates using reserve
+         * bit 20.  They are used by phy driver to keep the refcount of
+         * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
+         * turned on during boot, and software will not need to control it
+         * anymore after that.
+         */
+        clks[IMX6SL_CLK_USBPHY1]      = imx_clk_gate("usbphy1",      "pll3_usb_otg",  base + 0x10, 20);
+        clks[IMX6SL_CLK_USBPHY2]      = imx_clk_gate("usbphy2",      "pll7_usb_host", base + 0x20, 20);
+        clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy",         base + 0x10, 6);
+        clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy",         base + 0x20, 6);
+
+        /*                                                           dev   name              parent_name      flags                reg        shift width div: flags, div_table lock */
+        clks[IMX6SL_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div",  "pll4_audio",    CLK_SET_RATE_PARENT, base + 0x70,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div",  "pll5_video",    CLK_SET_RATE_PARENT, base + 0xa0,  19, 2,   0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2,   0, video_div_table, &imx_ccm_lock);
+        clks[IMX6SL_CLK_ENET_REF]       = clk_register_divider_table(NULL, "enet_ref",       "pll6_enet",     0,                   base + 0xe0,  0,  2,   0, clk_enet_ref_table, &imx_ccm_lock);
+
+        /*                                       name         parent_name     reg           idx */
+        clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus",     base + 0x100, 0);
+        clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus",     base + 0x100, 1);
+        clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus",     base + 0x100, 2);
+        clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0,  0);
+        clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0,  1);
+        clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0,  2);
+        clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0,  3);
+
+        /*                                                name         parent_name     mult div */
+        clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2",      1, 2);
+        clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
+        clks[IMX6SL_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
+        clks[IMX6SL_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
+
+        np = ccm_node;
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+
+        /*                                              name                reg       shift width parent_names     num_parents */
+        clks[IMX6SL_CLK_STEP]             = imx_clk_mux("step",             base + 0xc,  8,  1, step_sels,         ARRAY_SIZE(step_sels));
+        clks[IMX6SL_CLK_PLL1_SW]          = imx_clk_mux("pll1_sw",          base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clks[IMX6SL_CLK_OCRAM_ALT_SEL]    = imx_clk_mux("ocram_alt_sel",    base + 0x14, 7,  1, ocram_alt_sels,    ARRAY_SIZE(ocram_alt_sels));
+        clks[IMX6SL_CLK_OCRAM_SEL]        = imx_clk_mux("ocram_sel",        base + 0x14, 6,  1, ocram_sels,        ARRAY_SIZE(ocram_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH2_SEL]  = imx_clk_mux("pre_periph2_sel",  base + 0x18, 21, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PRE_PERIPH_SEL]   = imx_clk_mux("pre_periph_sel",   base + 0x18, 18, 2, pre_periph_sels,   ARRAY_SIZE(pre_periph_sels));
+        clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clks[IMX6SL_CLK_PERIPH_CLK2_SEL]  = imx_clk_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clks[IMX6SL_CLK_CSI_SEL]          = imx_clk_mux("csi_sel",          base + 0x3c, 9,  2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_LCDIF_AXI_SEL]    = imx_clk_mux("lcdif_axi_sel",    base + 0x3c, 14, 2, csi_lcdif_sels,    ARRAY_SIZE(csi_lcdif_sels));
+        clks[IMX6SL_CLK_USDHC1_SEL]       = imx_clk_mux("usdhc1_sel",       base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC2_SEL]       = imx_clk_mux("usdhc2_sel",       base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC3_SEL]       = imx_clk_mux("usdhc3_sel",       base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_USDHC4_SEL]       = imx_clk_mux("usdhc4_sel",       base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SL_CLK_SSI1_SEL]         = imx_clk_mux("ssi1_sel",         base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI2_SEL]         = imx_clk_mux("ssi2_sel",         base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_SSI3_SEL]         = imx_clk_mux("ssi3_sel",         base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SL_CLK_PERCLK_SEL]       = imx_clk_mux("perclk_sel",       base + 0x1c, 6,  1, perclk_sels,       ARRAY_SIZE(perclk_sels));
+        clks[IMX6SL_CLK_PXP_AXI_SEL]      = imx_clk_mux("pxp_axi_sel",      base + 0x34, 6,  3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_EPDC_AXI_SEL]     = imx_clk_mux("epdc_axi_sel",     base + 0x34, 15, 3, epdc_pxp_sels,     ARRAY_SIZE(epdc_pxp_sels));
+        clks[IMX6SL_CLK_GPU2D_OVG_SEL]    = imx_clk_mux("gpu2d_ovg_sel",    base + 0x18, 4,  2, gpu2d_ovg_sels,    ARRAY_SIZE(gpu2d_ovg_sels));
+        clks[IMX6SL_CLK_GPU2D_SEL]        = imx_clk_mux("gpu2d_sel",        base + 0x18, 8,  2, gpu2d_sels,        ARRAY_SIZE(gpu2d_sels));
+        clks[IMX6SL_CLK_LCDIF_PIX_SEL]    = imx_clk_mux("lcdif_pix_sel",    base + 0x38, 6,  3, lcdif_pix_sels,    ARRAY_SIZE(lcdif_pix_sels));
+        clks[IMX6SL_CLK_EPDC_PIX_SEL]     = imx_clk_mux("epdc_pix_sel",     base + 0x38, 15, 3, epdc_pix_sels,     ARRAY_SIZE(epdc_pix_sels));
+        clks[IMX6SL_CLK_SPDIF0_SEL]       = imx_clk_mux("spdif0_sel",       base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_SPDIF1_SEL]       = imx_clk_mux("spdif1_sel",       base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SL_CLK_ECSPI_SEL]        = imx_clk_mux("ecspi_sel",        base + 0x38, 18, 1, ecspi_sels,        ARRAY_SIZE(ecspi_sels));
+        clks[IMX6SL_CLK_UART_SEL]         = imx_clk_mux("uart_sel",         base + 0x24, 6,  1, uart_sels,         ARRAY_SIZE(uart_sels));
+
+        /*                                          name       reg        shift width busy: reg, shift parent_names  num_parents */
+        clks[IMX6SL_CLK_PERIPH]  = imx_clk_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
+        clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
+
+        /*                                                   name                 parent_name          reg       shift width */
+        clks[IMX6SL_CLK_OCRAM_PODF]        = imx_clk_divider("ocram_podf",        "ocram_sel",         base + 0x14, 16, 3);
+        clks[IMX6SL_CLK_PERIPH_CLK2_PODF]  = imx_clk_divider("periph_clk2_podf",  "periph_clk2_sel",   base + 0x14, 27, 3);
+        clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel",  base + 0x14, 0,  3);
+        clks[IMX6SL_CLK_IPG]               = imx_clk_divider("ipg",               "ahb",               base + 0x14, 8,  2);
+        clks[IMX6SL_CLK_CSI_PODF]          = imx_clk_divider("csi_podf",          "csi_sel",           base + 0x3c, 11, 3);
+        clks[IMX6SL_CLK_LCDIF_AXI_PODF]    = imx_clk_divider("lcdif_axi_podf",    "lcdif_axi_sel",     base + 0x3c, 16, 3);
+        clks[IMX6SL_CLK_USDHC1_PODF]       = imx_clk_divider("usdhc1_podf",       "usdhc1_sel",        base + 0x24, 11, 3);
+        clks[IMX6SL_CLK_USDHC2_PODF]       = imx_clk_divider("usdhc2_podf",       "usdhc2_sel",        base + 0x24, 16, 3);
+        clks[IMX6SL_CLK_USDHC3_PODF]       = imx_clk_divider("usdhc3_podf",       "usdhc3_sel",        base + 0x24, 19, 3);
+        clks[IMX6SL_CLK_USDHC4_PODF]       = imx_clk_divider("usdhc4_podf",       "usdhc4_sel",        base + 0x24, 22, 3);
+        clks[IMX6SL_CLK_SSI1_PRED]         = imx_clk_divider("ssi1_pred",         "ssi1_sel",          base + 0x28, 6,  3);
+        clks[IMX6SL_CLK_SSI1_PODF]         = imx_clk_divider("ssi1_podf",         "ssi1_pred",         base + 0x28, 0,  6);
+        clks[IMX6SL_CLK_SSI2_PRED]         = imx_clk_divider("ssi2_pred",         "ssi2_sel",          base + 0x2c, 6,  3);
+        clks[IMX6SL_CLK_SSI2_PODF]         = imx_clk_divider("ssi2_podf",         "ssi2_pred",         base + 0x2c, 0,  6);
+        clks[IMX6SL_CLK_SSI3_PRED]         = imx_clk_divider("ssi3_pred",         "ssi3_sel",          base + 0x28, 22, 3);
+        clks[IMX6SL_CLK_SSI3_PODF]         = imx_clk_divider("ssi3_podf",         "ssi3_pred",         base + 0x28, 16, 6);
+        clks[IMX6SL_CLK_PERCLK]            = imx_clk_divider("perclk",            "perclk_sel",        base + 0x1c, 0,  6);
+        clks[IMX6SL_CLK_PXP_AXI_PODF]      = imx_clk_divider("pxp_axi_podf",      "pxp_axi_sel",       base + 0x34, 3,  3);
+        clks[IMX6SL_CLK_EPDC_AXI_PODF]     = imx_clk_divider("epdc_axi_podf",     "epdc_axi_sel",      base + 0x34, 12, 3);
+        clks[IMX6SL_CLK_GPU2D_OVG_PODF]    = imx_clk_divider("gpu2d_ovg_podf",    "gpu2d_ovg_sel",     base + 0x18, 26, 3);
+        clks[IMX6SL_CLK_GPU2D_PODF]        = imx_clk_divider("gpu2d_podf",        "gpu2d_sel",         base + 0x18, 29, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PRED]    = imx_clk_divider("lcdif_pix_pred",    "lcdif_pix_sel",     base + 0x38, 3,  3);
+        clks[IMX6SL_CLK_EPDC_PIX_PRED]     = imx_clk_divider("epdc_pix_pred",     "epdc_pix_sel",      base + 0x38, 12, 3);
+        clks[IMX6SL_CLK_LCDIF_PIX_PODF]    = imx_clk_divider("lcdif_pix_podf",    "lcdif_pix_pred",    base + 0x1c, 20, 3);
+        clks[IMX6SL_CLK_EPDC_PIX_PODF]     = imx_clk_divider("epdc_pix_podf",     "epdc_pix_pred",     base + 0x18, 23, 3);
+        clks[IMX6SL_CLK_SPDIF0_PRED]       = imx_clk_divider("spdif0_pred",       "spdif0_sel",        base + 0x30, 25, 3);
+        clks[IMX6SL_CLK_SPDIF0_PODF]       = imx_clk_divider("spdif0_podf",       "spdif0_pred",       base + 0x30, 22, 3);
+        clks[IMX6SL_CLK_SPDIF1_PRED]       = imx_clk_divider("spdif1_pred",       "spdif1_sel",        base + 0x30, 12, 3);
+        clks[IMX6SL_CLK_SPDIF1_PODF]       = imx_clk_divider("spdif1_podf",       "spdif1_pred",       base + 0x30, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel",  base + 0x28, 9,  3);
+        clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
+        clks[IMX6SL_CLK_ECSPI_ROOT]        = imx_clk_divider("ecspi_root",        "ecspi_sel",         base + 0x38, 19, 6);
+        clks[IMX6SL_CLK_UART_ROOT]         = imx_clk_divider("uart_root",         "uart_sel",          base + 0x24, 0,  6);
+
+        /*                                                name         parent_name reg       shift width busy: reg, shift */
+        clks[IMX6SL_CLK_AHB]       = imx_clk_busy_divider("ahb",       "periph",  base + 0x14, 10, 3,    base + 0x48, 1);
+        clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc",      "periph2", base + 0x14, 3,  3,    base + 0x48, 2);
+        clks[IMX6SL_CLK_ARM]       = imx_clk_busy_divider("arm",       "pll1_sw", base + 0x10, 0,  3,    base + 0x48, 16);
+
+        /*                                            name            parent_name          reg         shift */
+        clks[IMX6SL_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",       "ecspi_root",        base + 0x6c, 0);
+        clks[IMX6SL_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",       "ecspi_root",        base + 0x6c, 2);
+        clks[IMX6SL_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",       "ecspi_root",        base + 0x6c, 4);
+        clks[IMX6SL_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",       "ecspi_root",        base + 0x6c, 6);
+        clks[IMX6SL_CLK_EPIT1]        = imx_clk_gate2("epit1",        "perclk",            base + 0x6c, 12);
+        clks[IMX6SL_CLK_EPIT2]        = imx_clk_gate2("epit2",        "perclk",            base + 0x6c, 14);
+        clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
+        clks[IMX6SL_CLK_GPT]          = imx_clk_gate2("gpt",          "perclk",            base + 0x6c, 20);
+        clks[IMX6SL_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",   "perclk",            base + 0x6c, 22);
+        clks[IMX6SL_CLK_GPU2D_OVG]    = imx_clk_gate2("gpu2d_ovg",    "gpu2d_ovg_podf",    base + 0x6c, 26);
+        clks[IMX6SL_CLK_I2C1]         = imx_clk_gate2("i2c1",         "perclk",            base + 0x70, 6);
+        clks[IMX6SL_CLK_I2C2]         = imx_clk_gate2("i2c2",         "perclk",            base + 0x70, 8);
+        clks[IMX6SL_CLK_I2C3]         = imx_clk_gate2("i2c3",         "perclk",            base + 0x70, 10);
+        clks[IMX6SL_CLK_OCOTP]        = imx_clk_gate2("ocotp",        "ipg",               base + 0x70, 12);
+        clks[IMX6SL_CLK_CSI]          = imx_clk_gate2("csi",          "csi_podf",          base + 0x74, 0);
+        clks[IMX6SL_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",      "pxp_axi_podf",      base + 0x74, 2);
+        clks[IMX6SL_CLK_EPDC_AXI]     = imx_clk_gate2("epdc_axi",     "epdc_axi_podf",     base + 0x74, 4);
+        clks[IMX6SL_CLK_LCDIF_AXI]    = imx_clk_gate2("lcdif_axi",    "lcdif_axi_podf",    base + 0x74, 6);
+        clks[IMX6SL_CLK_LCDIF_PIX]    = imx_clk_gate2("lcdif_pix",    "lcdif_pix_podf",    base + 0x74, 8);
+        clks[IMX6SL_CLK_EPDC_PIX]     = imx_clk_gate2("epdc_pix",     "epdc_pix_podf",     base + 0x74, 10);
+        clks[IMX6SL_CLK_OCRAM]        = imx_clk_gate2("ocram",        "ocram_podf",        base + 0x74, 28);
+        clks[IMX6SL_CLK_PWM1]         = imx_clk_gate2("pwm1",         "perclk",            base + 0x78, 16);
+        clks[IMX6SL_CLK_PWM2]         = imx_clk_gate2("pwm2",         "perclk",            base + 0x78, 18);
+        clks[IMX6SL_CLK_PWM3]         = imx_clk_gate2("pwm3",         "perclk",            base + 0x78, 20);
+        clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
+        clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
+        clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+        clks[IMX6SL_CLK_SSI1]         = imx_clk_gate2("ssi1",         "ssi1_podf",         base + 0x7c, 18);
+        clks[IMX6SL_CLK_SSI2]         = imx_clk_gate2("ssi2",         "ssi2_podf",         base + 0x7c, 20);
+        clks[IMX6SL_CLK_SSI3]         = imx_clk_gate2("ssi3",         "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SL_CLK_UART]         = imx_clk_gate2("uart",         "ipg",               base + 0x7c, 24);
+        clks[IMX6SL_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",  "uart_root",         base + 0x7c, 26);
+        clks[IMX6SL_CLK_USBOH3]       = imx_clk_gate2("usboh3",       "ipg",               base + 0x80, 0);
+        clks[IMX6SL_CLK_USDHC1]       = imx_clk_gate2("usdhc1",       "usdhc1_podf",       base + 0x80, 2);
+        clks[IMX6SL_CLK_USDHC2]       = imx_clk_gate2("usdhc2",       "usdhc2_podf",       base + 0x80, 4);
+        clks[IMX6SL_CLK_USDHC3]       = imx_clk_gate2("usdhc3",       "usdhc3_podf",       base + 0x80, 6);
+        clks[IMX6SL_CLK_USDHC4]       = imx_clk_gate2("usdhc4",       "usdhc4_podf",       base + 0x80, 8);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX6SL clk %d: register failed with %ld\n",
+                                i, PTR_ERR(clks[i]));
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+
+        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
+        }
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
+}
+CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3df9a7a..a9fad5f8d340 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
         .recalc_rate    = clk_pllv3_enet_recalc_rate,
 };
 
-static const struct clk_ops clk_pllv3_mlb_ops = {
-        .prepare        = clk_pllv3_prepare,
-        .unprepare      = clk_pllv3_unprepare,
-        .enable         = clk_pllv3_enable,
-        .disable        = clk_pllv3_disable,
-};
-
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
                           const char *parent_name, void __iomem *base,
                           u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
         case IMX_PLLV3_ENET:
                 ops = &clk_pllv3_enet_ops;
                 break;
-        case IMX_PLLV3_MLB:
-                ops = &clk_pllv3_mlb_ops;
-                break;
         default:
                 ops = &clk_pllv3_ops;
         }
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 000000000000..d617c0b7c809
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,319 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <dt-bindings/clock/vf610-clock.h>
+
+#include "clk.h"
+
+#define CCM_CCR                 (ccm_base + 0x00)
+#define CCM_CSR                 (ccm_base + 0x04)
+#define CCM_CCSR                (ccm_base + 0x08)
+#define CCM_CACRR               (ccm_base + 0x0c)
+#define CCM_CSCMR1              (ccm_base + 0x10)
+#define CCM_CSCDR1              (ccm_base + 0x14)
+#define CCM_CSCDR2              (ccm_base + 0x18)
+#define CCM_CSCDR3              (ccm_base + 0x1c)
+#define CCM_CSCMR2              (ccm_base + 0x20)
+#define CCM_CSCDR4              (ccm_base + 0x24)
+#define CCM_CLPCR               (ccm_base + 0x2c)
+#define CCM_CISR                (ccm_base + 0x30)
+#define CCM_CIMR                (ccm_base + 0x34)
+#define CCM_CGPR                (ccm_base + 0x3c)
+#define CCM_CCGR0               (ccm_base + 0x40)
+#define CCM_CCGR1               (ccm_base + 0x44)
+#define CCM_CCGR2               (ccm_base + 0x48)
+#define CCM_CCGR3               (ccm_base + 0x4c)
+#define CCM_CCGR4               (ccm_base + 0x50)
+#define CCM_CCGR5               (ccm_base + 0x54)
+#define CCM_CCGR6               (ccm_base + 0x58)
+#define CCM_CCGR7               (ccm_base + 0x5c)
+#define CCM_CCGR8               (ccm_base + 0x60)
+#define CCM_CCGR9               (ccm_base + 0x64)
+#define CCM_CCGR10              (ccm_base + 0x68)
+#define CCM_CCGR11              (ccm_base + 0x6c)
+#define CCM_CMEOR0              (ccm_base + 0x70)
+#define CCM_CMEOR1              (ccm_base + 0x74)
+#define CCM_CMEOR2              (ccm_base + 0x78)
+#define CCM_CMEOR3              (ccm_base + 0x7c)
+#define CCM_CMEOR4              (ccm_base + 0x80)
+#define CCM_CMEOR5              (ccm_base + 0x84)
+#define CCM_CPPDSR              (ccm_base + 0x88)
+#define CCM_CCOWR               (ccm_base + 0x8c)
+#define CCM_CCPGR0              (ccm_base + 0x90)
+#define CCM_CCPGR1              (ccm_base + 0x94)
+#define CCM_CCPGR2              (ccm_base + 0x98)
+#define CCM_CCPGR3              (ccm_base + 0x9c)
+
+#define CCM_CCGRx_CGn(n)        ((n) * 2)
+
+#define PFD_PLL1_BASE           (anatop_base + 0x2b0)
+#define PFD_PLL2_BASE           (anatop_base + 0x100)
+#define PFD_PLL3_BASE           (anatop_base + 0xf0)
+
+static void __iomem *anatop_base;
+static void __iomem *ccm_base;
+
+/* sources for multiplexer clocks, this is used multiple times */
+static const char const *fast_sels[]    = { "firc", "fxosc", };
+static const char const *slow_sels[]    = { "sirc_32k", "sxosc", };
+static const char const *pll1_sels[]    = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
+static const char const *pll2_sels[]    = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
+static const char const *sys_sels[]     = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
+static const char const *ddr_sels[]     = { "pll2_pfd2", "sys_sel", };
+static const char const *rmii_sels[]    = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
+static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
+static const char const *esai_sels[]    = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *sai_sels[]     = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
+static const char const *nfc_sels[]     = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
+static const char const *qspi_sels[]    = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
+static const char const *esdhc_sels[]   = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
+static const char const *dcu_sels[]     = { "pll1_pfd2", "pll3_main", };
+static const char const *gpu_sels[]     = { "pll2_pfd2", "pll3_pfd2", };
+static const char const *vadc_sels[]    = { "pll6_main_div", "pll3_main_div", "pll3_main", };
+/* FTM counter clock source, not module clock */
+static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
+static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
+
+static struct clk_div_table pll4_main_div_table[] = {
+        { .val = 0, .div = 1 },
+        { .val = 1, .div = 2 },
+        { .val = 2, .div = 6 },
+        { .val = 3, .div = 8 },
+        { .val = 4, .div = 10 },
+        { .val = 5, .div = 12 },
+        { .val = 6, .div = 14 },
+        { .val = 7, .div = 16 },
+        { }
+};
+
+static struct clk *clk[VF610_CLK_END];
+static struct clk_onecell_data clk_data;
+
+static void __init vf610_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+
+        clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
+        clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
+        clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
+
+        clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
+        clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
+        clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
+        clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
+
+        clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
+        anatop_base = of_iomap(np, 0);
+        BUG_ON(!anatop_base);
+
+        np = ccm_node;
+        ccm_base = of_iomap(np, 0);
+        BUG_ON(!ccm_base);
+
+        clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
+        clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
+
+        clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
+        clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
+        clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
+        clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
+
+        clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
+        clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
+        clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
+        clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
+        clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
+
+        clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
+        clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
+        clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
+        clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
+        clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
+
+        clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
+        /* Enet pll: fixed 50Mhz */
+        clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
+        /* pll6: default 960Mhz */
+        clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
+        clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
+        clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
+        clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
+        clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
+        clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
+        clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
+        clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
+
+        clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
+        clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
+        clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
+
+        clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
+        clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
+        clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
+        clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
+        clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
+        clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
+        clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
+        clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
+        clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
+        clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
+        clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
+
+        clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
+        clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
+        clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
+        clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
+        clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
+        clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
+
+        clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
+        clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
+
+        clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
+        clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
+        clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
+
+        clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
+
+        clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
+        clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
+        clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
+        clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
+        clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
+        clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
+
+        /*
+         * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
+         * selectable clock sources, both use a common enable bit
+         * in CCM_CSCDR1, selecting "dummy" clock as parent of
+         * "ftm0_ext_fix" make it serve only for enable/disable.
+         */
+        clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
+        clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
+        clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
+        clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
+        clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
+        clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
+
+        /* ftm(n)_clk are FTM module operation clock */
+        clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
+        clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
+
+        clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
+        clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
+        clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
+        clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
+        clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
+        clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
+        clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
+
+        clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
+        clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
+        clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
+        clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
+
+        clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
+        clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
+        clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
+
+        clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
+        clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
+        clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
+
+        clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
+        clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
+        clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
+        clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
+        clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
+        clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
+
+        clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
+        clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
+        clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
+        clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
+        clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
+
+        clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
+        clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
+        clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
+
+        clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
+        clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
+        clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
+        clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
+        clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
+
+        clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
+        clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
+        clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
+
+        clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
+
+        clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
+        clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
+
+        clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
+
+        clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
+        clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
+
+        clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
+        clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
+
+        /* Add the clocks to provider list */
+        clk_data.clks = clk;
+        clk_data.clk_num = ARRAY_SIZE(clk);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 37e884ed1cd4..55bc80a00666 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,4 +1,39 @@
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/slab.h>
 #include <linux/spinlock.h>
 #include "clk.h"
 
 DEFINE_SPINLOCK(imx_ccm_lock);
+
+static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
+{
+        struct of_phandle_args phandle;
+        struct clk *clk = ERR_PTR(-ENODEV);
+        char *path;
+
+        path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
+        if (!path)
+                return ERR_PTR(-ENOMEM);
+
+        phandle.np = of_find_node_by_path(path);
+        kfree(path);
+
+        if (phandle.np) {
+                clk = of_clk_get_from_provider(&phandle);
+                of_node_put(phandle.np);
+        }
+        return clk;
+}
+
+struct clk * __init imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate)
+{
+        struct clk *clk;
+
+        clk = imx_obtain_fixed_clock_from_dt(name);
+        if (IS_ERR(clk))
+                clk = imx_clk_fixed(name, rate);
+        return clk;
+}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c66dff..0e4e8bb261b9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
         IMX_PLLV3_USB,
         IMX_PLLV3_AV,
         IMX_PLLV3_ENET,
-        IMX_PLLV3_MLB,
 };
 
 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
                 void __iomem *reg, u8 bit_idx,
                 u8 clk_gate_flags, spinlock_t *lock);
 
+struct clk * imx_obtain_fixed_clock(
+                        const char *name, unsigned long rate);
+
 static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
                 void __iomem *reg, u8 shift)
 {
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f99cee..ee78847abf47 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,12 +68,12 @@ extern int mx27_clocks_init_dt(void);
 extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
-extern int mx6q_clocks_init(void);
 extern struct platform_device *mxc_register_gpio(char *name, int id,
         resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
 extern void mxc_set_cpu_type(unsigned int type);
 extern void mxc_restart(char, const char *);
 extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc_arch_reset_init_dt(void);
 extern int mx53_revision(void);
 extern int imx6q_revision(void);
 extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f7b591..a3b0b04b45c9 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
 #ifndef __ASM_ARCH_MXC_HARDWARE_H__
 #define __ASM_ARCH_MXC_HARDWARE_H__
 
+#include <asm/io.h>
 #include <asm/sizes.h>
 
 #define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 82348391582a..3e1ec5ffe630 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -19,6 +19,8 @@
 
 static void __init imx25_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0a77ff..4e235ecb4021 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,6 +22,8 @@ static void __init imx27_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611e29ab..818a1cc2fe45 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -20,6 +20,8 @@
 
 static void __init imx31_dt_init(void)
 {
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc322111..53e43e579dd7 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -23,6 +23,8 @@ static void __init imx51_dt_init(void)
 {
         struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
+        mxc_arch_reset_init_dt();
+
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
         platform_device_register_full(&devinfo);
 }
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52dc46b..0a920d184867 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
 
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/platform_data/asoc-imx-ssi.h>
 
 #include "irq-common.h"
 
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c616feed..98c58944015a 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,25 +21,12 @@
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "hardware.h"
 #include "mx53.h"
 
-static void __init imx53_qsb_init(void)
-{
-        struct clk *clk;
-
-        clk = clk_get_sys(NULL, "ssi_ext1");
-        if (IS_ERR(clk)) {
-                pr_err("failed to get clk ssi_ext1\n");
-                return;
-        }
-
-        clk_register_clkdev(clk, NULL, "0-000a");
-}
-
 static void __init imx53_dt_init(void)
 {
-        if (of_machine_is_compatible("fsl,imx53-qsb"))
-                imx53_qsb_init();
+        mxc_arch_reset_init_dt();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd81379a..f5965220a4d8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clocksource.h>
 #include <linux/cpu.h>
@@ -145,6 +146,45 @@ static void __init imx6q_sabrelite_init(void)
         imx6q_sabrelite_cko1_setup();
 }
 
+static void __init imx6q_sabresd_cko1_setup(void)
+{
+        struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
+        unsigned long rate;
+
+        cko1_sel = clk_get_sys(NULL, "cko1_sel");
+        pll4 = clk_get_sys(NULL, "pll4_audio");
+        pll4_post = clk_get_sys(NULL, "pll4_post_div");
+        cko1 = clk_get_sys(NULL, "cko1");
+        if (IS_ERR(cko1_sel) || IS_ERR(pll4)
+                        || IS_ERR(pll4_post) || IS_ERR(cko1)) {
+                pr_err("cko1 setup failed!\n");
+                goto put_clk;
+        }
+        /*
+         * Setting pll4 at 768MHz (24MHz * 32)
+         * So its child clock can get 24MHz easily
+         */
+        clk_set_rate(pll4, 768000000);
+
+        clk_set_parent(cko1_sel, pll4_post);
+        rate = clk_round_rate(cko1, 24000000);
+        clk_set_rate(cko1, rate);
+put_clk:
+        if (!IS_ERR(cko1_sel))
+                clk_put(cko1_sel);
+        if (!IS_ERR(pll4_post))
+                clk_put(pll4_post);
+        if (!IS_ERR(pll4))
+                clk_put(pll4);
+        if (!IS_ERR(cko1))
+                clk_put(cko1);
+}
+
+static void __init imx6q_sabresd_init(void)
+{
+        imx6q_sabresd_cko1_setup();
+}
+
 static void __init imx6q_1588_init(void)
 {
         struct regmap *gpr;
@@ -165,6 +205,9 @@ static void __init imx6q_init_machine(void)
 {
         if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
                 imx6q_sabrelite_init();
+        else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
+                        of_machine_is_compatible("fsl,imx6dl-sabresd"))
+                imx6q_sabresd_init();
 
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
@@ -253,10 +296,44 @@ static void __init imx6q_map_io(void)
         imx_scu_map_io();
 }
 
+#ifdef CONFIG_CACHE_L2X0
+static void __init imx6q_init_l2cache(void)
+{
+        void __iomem *l2x0_base;
+        struct device_node *np;
+        unsigned int val;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
+        if (!np)
+                goto out;
+
+        l2x0_base = of_iomap(np, 0);
+        if (!l2x0_base) {
+                of_node_put(np);
+                goto out;
+        }
+
+        /* Configure the L2 PREFETCH and POWER registers */
+        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+        val |= 0x70800000;
+        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
+        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
+
+        iounmap(l2x0_base);
+        of_node_put(np);
+
+out:
+        l2x0_of_init(0, ~0UL);
+}
+#else
+static inline void imx6q_init_l2cache(void) {}
+#endif
+
 static void __init imx6q_init_irq(void)
 {
         imx6q_init_revision();
-        l2x0_of_init(0, ~0UL);
+        imx6q_init_l2cache();
         imx_src_init();
         imx_gpc_init();
         irqchip_init();
@@ -264,7 +341,7 @@ static void __init imx6q_init_irq(void)
 
 static void __init imx6q_timer_init(void)
 {
-        mx6q_clocks_init();
+        of_clk_init(NULL);
         clocksource_of_init();
         imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
                               imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 000000000000..132db2609507
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/irqchip.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "common.h"
+
+static void __init imx6sl_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init imx6sl_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        imx_src_init();
+        imx_gpc_init();
+        irqchip_init();
+}
+
+static void __init imx6sl_timer_init(void)
+{
+        of_clk_init(NULL);
+}
+
+static const char *imx6sl_dt_compat[] __initdata = {
+        "fsl,imx6sl",
+        NULL,
+};
+
+DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = imx6sl_init_irq,
+        .init_time      = imx6sl_timer_init,
+        .init_machine   = imx6sl_init_machine,
+        .dt_compat      = imx6sl_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index dae4cd7be040..6f424eced181 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -268,10 +268,11 @@ static struct mc13xxx_led_platform_data moboard_led[] = {
 static struct mc13xxx_leds_platform_data moboard_leds = {
         .num_leds = ARRAY_SIZE(moboard_led),
         .led = moboard_led,
-        .flags = MC13783_LED_SLEWLIMTC,
-        .abmode = MC13783_LED_AB_DISABLED,
-        .tc1_period = MC13783_LED_PERIOD_10MS,
-        .tc2_period = MC13783_LED_PERIOD_10MS,
+        .led_control[0] = MC13783_LED_C0_ENABLE | MC13783_LED_C0_ABMODE(0),
+        .led_control[1] = MC13783_LED_C1_SLEWLIM,
+        .led_control[2] = MC13783_LED_C2_SLEWLIM,
+        .led_control[3] = MC13783_LED_C3_PERIOD(0),
+        .led_control[4] = MC13783_LED_C3_PERIOD(0),
 };
 
 static struct mc13xxx_buttons_platform_data moboard_buttons = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb1ffdf..19bb6441a7d4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
                 imx27_add_fsl_usb2_udc(&otg_device_pdata);
         }
 
-        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-                                ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
+        usbh2_pdata.otg = imx_otg_ulpi_create(
+                        ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
 
         if (usbh2_pdata.otg)
                 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 000000000000..816991deb9b8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include "common.h"
+
+static void __init vf610_init_machine(void)
+{
+        mxc_arch_reset_init_dt();
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void __init vf610_init_irq(void)
+{
+        l2x0_of_init(0, ~0UL);
+        irqchip_init();
+}
+
+static void __init vf610_init_time(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+
+static const char *vf610_dt_compat[] __initdata = {
+        "fsl,vf610",
+        NULL,
+};
+
+DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
+        .init_irq       = vf610_init_irq,
+        .init_time      = vf610_init_time,
+        .init_machine   = vf610_init_machine,
+        .dt_compat      = vf610_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c52d3eb..e065fedb3ad4 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
 void __init imx1_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
-        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
         imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
                         MX1_NUM_GPIO_PORT);
 }
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
 
 void __init imx1_soc_init(void)
 {
+        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec53..2e91ab2ca378 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
 void __init imx21_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX21);
-        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
         imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
                         MX21_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
 
 void __init imx21_soc_init(void)
 {
+        mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7af..e065c117f5a6 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX25);
         mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
 }
 
 void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
 
 void __init imx25_soc_init(void)
 {
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5f..7d82a5a5b16b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
 void __init imx27_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX27);
-        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
         imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
                         MX27_NUM_GPIO_PORT);
 }
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
 
 void __init imx27_soc_init(void)
 {
+        mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a682174..0884ca90d15a 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -65,7 +65,7 @@ static void imx3_idle(void)
                 : "=r" (reg));
 }
 
-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
+static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                          unsigned int mtype, void *caller)
 {
         if (mtype == MT_DEVICE) {
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
 void __init imx31_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX31);
-        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
         arch_ioremap_caller = imx3_ioremap_caller;
         arm_pm_idle = imx3_idle;
         mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
 
         imx3_init_l2x0();
 
+        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX35);
         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
         arm_pm_idle = imx3_idle;
         arch_ioremap_caller = imx3_ioremap_caller;
         mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
 
         imx3_init_l2x0();
 
+        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
         mxc_device_init();
 
         mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70e5081..cf193d87274a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
         imx51_ipu_mipi_setup();
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
         imx_src_init();
 }
 
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX53);
         mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
-        mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
         imx_src_init();
 }
 
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
 
 void __init imx51_soc_init(void)
 {
+        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
         mxc_device_init();
 
         /* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d73bf85..7cdc79a9657c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 #include <linux/err.h>
 #include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <asm/system_misc.h>
 #include <asm/proc-fns.h>
@@ -30,6 +32,7 @@
 #include "hardware.h"
 
 static void __iomem *wdog_base;
+static struct clk *wdog_clk;
 
 /*
  * Reset the system. It is called by machine_restart().
@@ -38,16 +41,13 @@ void mxc_restart(char mode, const char *cmd)
 {
         unsigned int wcr_enable;
 
-        if (cpu_is_mx1()) {
-                wcr_enable = (1 << 0);
-        } else {
-                struct clk *clk;
+        if (wdog_clk)
+                clk_enable(wdog_clk);
 
-                clk = clk_get_sys("imx2-wdt.0", NULL);
-                if (!IS_ERR(clk))
-                        clk_prepare_enable(clk);
+        if (cpu_is_mx1())
+                wcr_enable = (1 << 0);
+        else
                 wcr_enable = (1 << 2);
-        }
 
         /* Assert SRS signal */
         __raw_writew(wcr_enable, wdog_base);
@@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd)
         /* wait for reset to assert... */
         mdelay(500);
 
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+        pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
 
         /* delay to allow the serial port to show the message */
         mdelay(50);
@@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd)
         soft_restart(0);
 }
 
-void mxc_arch_reset_init(void __iomem *base)
+void __init mxc_arch_reset_init(void __iomem *base)
 {
         wdog_base = base;
+
+        wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+
+        clk_prepare(wdog_clk);
+}
+
+void __init mxc_arch_reset_init_dt(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
+        wdog_base = of_iomap(np, 0);
+        WARN_ON(!wdog_base);
+
+        wdog_clk = of_clk_get(np, 0);
+        if (IS_ERR(wdog_clk)) {
+                pr_warn("%s: failed to get wdog clock\n", __func__);
+                wdog_clk = NULL;
+                return;
+        }
+
+        clk_prepare(wdog_clk);
 }
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10c..000000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- * Copyright 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include "ulpi.h"
-
-/* ULPIVIEW register bits */
-#define ULPIVW_WU               (1 << 31)       /* Wakeup */
-#define ULPIVW_RUN              (1 << 30)       /* read/write run */
-#define ULPIVW_WRITE            (1 << 29)       /* 0 = read  1 = write */
-#define ULPIVW_SS               (1 << 27)       /* SyncState */
-#define ULPIVW_PORT_MASK        0x07    /* Port field */
-#define ULPIVW_PORT_SHIFT       24
-#define ULPIVW_ADDR_MASK        0xff    /* data address field */
-#define ULPIVW_ADDR_SHIFT       16
-#define ULPIVW_RDATA_MASK       0xff    /* read data field */
-#define ULPIVW_RDATA_SHIFT      8
-#define ULPIVW_WDATA_MASK       0xff    /* write data field */
-#define ULPIVW_WDATA_SHIFT      0
-
-static int ulpi_poll(void __iomem *view, u32 bit)
-{
-        int timeout = 10000;
-
-        while (timeout--) {
-                u32 data = __raw_readl(view);
-
-                if (!(data & bit))
-                        return 0;
-
-                cpu_relax();
-        };
-
-        printk(KERN_WARNING "timeout polling for ULPI device\n");
-
-        return -ETIMEDOUT;
-}
-
-static int ulpi_read(struct usb_phy *otg, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        /* read the register */
-        __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
-
-        /* wait for completion */
-        ret = ulpi_poll(view, ULPIVW_RUN);
-        if (ret)
-                return ret;
-
-        return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
-}
-
-static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
-{
-        int ret;
-        void __iomem *view = otg->io_priv;
-
-        /* make sure the interface is running */
-        if (!(__raw_readl(view) & ULPIVW_SS)) {
-                __raw_writel(ULPIVW_WU, view);
-                /* wait for wakeup */
-                ret = ulpi_poll(view, ULPIVW_WU);
-                if (ret)
-                        return ret;
-        }
-
-        __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
-                      (reg << ULPIVW_ADDR_SHIFT) |
-                      ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
-
-        /* wait for completion */
-        return ulpi_poll(view, ULPIVW_RUN);
-}
-
-struct usb_phy_io_ops mxc_ulpi_access_ops = {
-        .read   = ulpi_read,
-        .write  = ulpi_write,
-};
-EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
-
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
-{
-        return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
-}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..23f5c0349e80 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
 #ifndef __MACH_ULPI_H
 #define __MACH_ULPI_H
 
-#ifdef CONFIG_USB_ULPI
-struct usb_phy *imx_otg_ulpi_create(unsigned int flags);
+#include <linux/usb/ulpi.h>
+
+#ifdef CONFIG_USB_ULPI_VIEWPORT
+static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
+{
+        return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
+}
 #else
 static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 {
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
 }
 #endif
 
-extern struct usb_phy_io_ops mxc_ulpi_access_ops;
-
 #endif /* __MACH_ULPI_H */
 
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index d14d6b76f4c2..ec759ded7b60 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -8,5 +8,5 @@ obj-y					:= core.o lm.o leds.o
 obj-$(CONFIG_ARCH_INTEGRATOR_AP)        += integrator_ap.o
 obj-$(CONFIG_ARCH_INTEGRATOR_CP)        += integrator_cp.o
 
-obj-$(CONFIG_PCI)                       += pci_v3.o pci.o
+obj-$(CONFIG_PCI)                       += pci_v3.o
 obj-$(CONFIG_INTEGRATOR_IMPD1)          += impd1.o
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index be5859efe10e..306d025d9730 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -305,29 +305,6 @@
 /* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
 
 /* ------------------------------------------------------------------------
- *  Where in the memory map does PCI live?
- * ------------------------------------------------------------------------
- *  This represents a fairly liberal usage of address space.  Even though
- *  the V3 only has two windows (therefore we need to map stuff on the fly),
- *  we maintain the same addresses, even if they're not mapped.
- *
- */
-#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
-/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
- */
-#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
-/*  unused (128-16)M from B1000000-B7FFFFFF
- */
-#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
-/*  unused ((128-16)M - 64K) from XXX
- */
-#define PHYS_PCI_V3_BASE                0x62000000
-
-#define PCI_MEMORY_VADDR                IOMEM(0xe8000000)
-#define PCI_CONFIG_VADDR                IOMEM(0xec000000)
-#define PCI_V3_VADDR                    IOMEM(0xed000000)
-
-/* ------------------------------------------------------------------------
  *  Integrator Interrupt Controllers
  * ------------------------------------------------------------------------
  *
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index b23c8e4f28e8..a5b15c4e8def 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -41,7 +41,6 @@
 #include <linux/stat.h>
 #include <linux/sys_soc.h>
 #include <linux/termios.h>
-#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -57,10 +56,10 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
-#include <asm/mach/pci.h>
 #include <asm/mach/time.h>
 
 #include "common.h"
+#include "pci_v3.h"
 
 /* Base address to the AP system controller */
 void __iomem *ap_syscon_base;
@@ -78,10 +77,6 @@ void __iomem *ap_syscon_base;
 
 /*
  * Logical      Physical
- * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
- * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
- * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
- * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  * ef000000                     Cache flush
  * f1000000     10000000        Core module registers
  * f1100000     11000000        System controller registers
@@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
-                .length         = SZ_16M,
-                .type           = MT_DEVICE
-        }, {
-                .virtual        = (unsigned long)PCI_V3_VADDR,
-                .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE
         }
 };
 
 static void __init ap_map_io(void)
 {
         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
-        vga_base = (unsigned long)PCI_MEMORY_VADDR;
-        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+        pci_v3_early_init();
 }
 
 #ifdef CONFIG_PM
@@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void)
  * for eventual deletion.
  */
 
+static struct platform_device pci_v3_device = {
+        .name           = "pci-v3",
+        .id             = 0,
+};
+
 static struct resource cfi_flash_resource = {
         .start          = INTEGRATOR_FLASH_BASE,
         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
@@ -672,6 +656,7 @@ static void __init ap_init(void)
         unsigned long sc_dec;
         int i;
 
+        platform_device_register(&pci_v3_device);
         platform_device_register(&cfi_flash_device);
 
         ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
deleted file mode 100644
index 6c1667e728f5..000000000000
--- a/arch/arm/mach-integrator/pci.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *  linux/arch/arm/mach-integrator/pci-integrator.c
- *
- *  Copyright (C) 1999 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- *
- *  PCI functions for Integrator
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-
-#include <asm/mach/pci.h>
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-/* 
- * A small note about bridges and interrupts.  The DECchip 21050 (and
- * later) adheres to the PCI-PCI bridge specification.  This says that
- * the interrupts on the other side of a bridge are swizzled in the
- * following manner:
- *
- * Dev    Interrupt   Interrupt 
- *        Pin on      Pin on 
- *        Device      Connector
- *
- *   4    A           A
- *        B           B
- *        C           C
- *        D           D
- * 
- *   5    A           B
- *        B           C
- *        C           D
- *        D           A
- *
- *   6    A           C
- *        B           D
- *        C           A
- *        D           B
- *
- *   7    A           D
- *        B           A
- *        C           B
- *        D           C
- *
- * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
- * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
- */
-
-/*
- * This routine handles multiple bridges.
- */
-static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
-{
-        if (*pinp == 0)
-                *pinp = 1;
-
-        return pci_common_swizzle(dev, pinp);
-}
-
-static int irq_tab[4] __initdata = {
-        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
-};
-
-/*
- * map the specified device/slot/pin to an IRQ.  This works out such
- * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
- */
-static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int intnr = ((slot - 9) + (pin - 1)) & 3;
-
-        return irq_tab[intnr];
-}
-
-extern void pci_v3_init(void *);
-
-static struct hw_pci integrator_pci __initdata = {
-        .swizzle                = integrator_swizzle,
-        .map_irq                = integrator_map_irq,
-        .setup                  = pci_v3_setup,
-        .nr_controllers         = 1,
-        .ops                    = &pci_v3_ops,
-        .preinit                = pci_v3_preinit,
-        .postinit               = pci_v3_postinit,
-};
-
-static int __init integrator_pci_init(void)
-{
-        if (machine_is_integrator())
-                pci_common_init(&integrator_pci);
-        return 0;
-}
-
-subsys_initcall(integrator_pci_init);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index e7fcea7f3300..bef100527c42 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,16 +27,199 @@
 #include <linux/spinlock.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <video/vga.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
 #include <mach/irqs.h>
 
+#include <asm/mach/map.h>
 #include <asm/signal.h>
 #include <asm/mach/pci.h>
 #include <asm/irq_regs.h>
 
-#include <asm/hardware/pci_v3.h>
+#include "pci_v3.h"
+
+/*
+ * Where in the memory map does PCI live?
+ *
+ * This represents a fairly liberal usage of address space.  Even though
+ * the V3 only has two windows (therefore we need to map stuff on the fly),
+ * we maintain the same addresses, even if they're not mapped.
+ */
+#define PHYS_PCI_MEM_BASE               0x40000000 /* 256M */
+#define PHYS_PCI_PRE_BASE               0x50000000 /* 256M */
+#define PHYS_PCI_IO_BASE                0x60000000 /* 16M */
+#define PHYS_PCI_CONFIG_BASE            0x61000000 /* 16M */
+#define PHYS_PCI_V3_BASE                0x62000000 /* 64K */
+
+#define PCI_MEMORY_VADDR               IOMEM(0xe8000000)
+#define PCI_CONFIG_VADDR               IOMEM(0xec000000)
+
+/*
+ * V3 Local Bus to PCI Bridge definitions
+ *
+ * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ * All V3 register names are prefaced by V3_ to avoid clashing with any other
+ * PCI definitions.  Their names match the user's manual.
+ *
+ * I'm assuming that I20 is disabled.
+ *
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
+#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
+#define V3_PCI_CFG_M_EN3V               (1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE             0xfff00000
+#define V3_LB_BASE_SWAP                 (3 << 8)
+#define V3_LB_BASE_ADR_SIZE             (15 << 4)
+#define V3_LB_BASE_PREFETCH             (1 << 3)
+#define V3_LB_BASE_ENABLE               (1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
+
+#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR               0xfff0
+#define V3_LB_MAP_TYPE                  (7 << 1)
+#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK             (0 << 1)
+#define V3_LB_MAP_TYPE_IO               (1 << 1)
+#define V3_LB_MAP_TYPE_MEM              (3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
+
+#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE            0xff00
+#define V3_LB_BASE2_SWAP                (3 << 6)
+#define V3_LB_BASE2_ENABLE              (1 << 0)
+
+#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR              0xff00
+
+#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
 
 /*
  * The V3 PCI interface chip in Integrator provides several windows from
@@ -101,15 +284,28 @@
  * the mappings into PCI memory.
  */
 
+/* Filled in by probe */
+static void __iomem *pci_v3_base;
+/* CPU side memory ranges */
+static struct resource conf_mem; /* FIXME: remap this instead of static map */
+static struct resource io_mem;
+static struct resource non_mem;
+static struct resource pre_mem;
+/* PCI side memory ranges */
+static u64 non_mem_pci;
+static u64 non_mem_pci_sz;
+static u64 pre_mem_pci;
+static u64 pre_mem_pci_sz;
+
 // V3 access routines
-#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readb(o)    (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
+#define v3_readb(o)    (__raw_readb(pci_v3_base + (unsigned int)(o)))
 
-#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readw(o)    (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
+#define v3_readw(o)    (__raw_readw(pci_v3_base + (unsigned int)(o)))
 
-#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
-#define v3_readl(o)    (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
+#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
+#define v3_readl(o)    (__raw_readl(pci_v3_base + (unsigned int)(o)))
 
 /*============================================================================
  *
@@ -165,19 +361,6 @@
  */
 static DEFINE_RAW_SPINLOCK(v3_lock);
 
-#define PCI_BUS_NONMEM_START    0x00000000
-#define PCI_BUS_NONMEM_SIZE     SZ_256M
-
-#define PCI_BUS_PREMEM_START    PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
-#define PCI_BUS_PREMEM_SIZE     SZ_256M
-
-#if PCI_BUS_NONMEM_START & 0x000fffff
-#error PCI_BUS_NONMEM_START must be megabyte aligned
-#endif
-#if PCI_BUS_PREMEM_START & 0x000fffff
-#error PCI_BUS_PREMEM_START must be megabyte aligned
-#endif
-
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
 
@@ -243,13 +426,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
          * prefetchable), this frees up base1 for re-use by
          * configuration memory
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
 
         /*
          * Set up base1/map1 to point into configuration space.
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
                         V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP1, mapaddress);
 
@@ -261,16 +444,16 @@ static void v3_close_config_window(void)
         /*
          * Reassign base1 for use by prefetchable PCI memory
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                         V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
                         V3_LB_MAP_TYPE_MEM_MULTIPLE);
 
         /*
          * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
 }
 
@@ -337,25 +520,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
         return PCIBIOS_SUCCESSFUL;
 }
 
-struct pci_ops pci_v3_ops = {
+static struct pci_ops pci_v3_ops = {
         .read   = v3_read_config,
         .write  = v3_write_config,
 };
 
-static struct resource non_mem = {
-        .name   = "PCI non-prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
-};
-
-static struct resource pre_mem = {
-        .name   = "PCI prefetchable",
-        .start  = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
-        .end    = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
-};
-
 static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 {
         if (request_resource(&iomem_resource, &non_mem)) {
@@ -471,7 +640,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
         return IRQ_HANDLED;
 }
 
-int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
+static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 {
         int ret = 0;
 
@@ -479,7 +648,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
                 return -EINVAL;
 
         if (nr == 0) {
-                sys->mem_offset = PHYS_PCI_MEM_BASE;
+                sys->mem_offset = non_mem.start;
                 ret = pci_v3_setup_resources(sys);
         }
 
@@ -490,18 +659,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
  * V3_LB_BASE? - local bus address
  * V3_LB_MAP?  - pci bus address
  */
-void __init pci_v3_preinit(void)
+static void __init pci_v3_preinit(void)
 {
         unsigned long flags;
         unsigned int temp;
-        int ret;
-
-        /* Remap the Integrator system controller */
-        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
-        if (!ap_syscon_base) {
-                pr_err("unable to remap the AP syscon for PCIv3\n");
-                return;
-        }
 
         pcibios_min_mem = 0x00100000;
 
@@ -525,25 +686,25 @@ void __init pci_v3_preinit(void)
          * Setup window 0 - PCI non-prefetchable memory
          *  Local: 0x40000000 Bus: 0x00000000 Size: 256MB
          */
-        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
+        v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
+        v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(non_mem_pci) |
                         V3_LB_MAP_TYPE_MEM);
 
         /*
          * Setup window 1 - PCI prefetchable memory
          *  Local: 0x50000000 Bus: 0x10000000 Size: 256MB
          */
-        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
+        v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
                         V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
                         V3_LB_BASE_ENABLE);
-        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
+        v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(pre_mem_pci) |
                         V3_LB_MAP_TYPE_MEM_MULTIPLE);
 
         /*
          * Setup window 2 - PCI IO
          */
-        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
+        v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
                         V3_LB_BASE_ENABLE);
         v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
 
@@ -578,18 +739,10 @@ void __init pci_v3_preinit(void)
         v3_writeb(V3_LB_IMASK, 0x28);
         __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
 
-        /*
-         * Grab the PCI error interrupt.
-         */
-        ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
-        if (ret)
-                printk(KERN_ERR "PCI: unable to grab PCI error "
-                       "interrupt: %d\n", ret);
-
         raw_spin_unlock_irqrestore(&v3_lock, flags);
 }
 
-void __init pci_v3_postinit(void)
+static void __init pci_v3_postinit(void)
 {
         unsigned int pci_cmd;
 
@@ -608,5 +761,284 @@ void __init pci_v3_postinit(void)
                        "interrupt: %d\n", ret);
 #endif
 
-        register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
+        register_isa_ports(non_mem.start, io_mem.start, 0);
+}
+
+/*
+ * A small note about bridges and interrupts.  The DECchip 21050 (and
+ * later) adheres to the PCI-PCI bridge specification.  This says that
+ * the interrupts on the other side of a bridge are swizzled in the
+ * following manner:
+ *
+ * Dev    Interrupt   Interrupt
+ *        Pin on      Pin on
+ *        Device      Connector
+ *
+ *   4    A           A
+ *        B           B
+ *        C           C
+ *        D           D
+ *
+ *   5    A           B
+ *        B           C
+ *        C           D
+ *        D           A
+ *
+ *   6    A           C
+ *        B           D
+ *        C           A
+ *        D           B
+ *
+ *   7    A           D
+ *        B           A
+ *        C           B
+ *        D           C
+ *
+ * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
+ * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
+ */
+
+/*
+ * This routine handles multiple bridges.
+ */
+static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
+{
+        if (*pinp == 0)
+                *pinp = 1;
+
+        return pci_common_swizzle(dev, pinp);
+}
+
+static int irq_tab[4] __initdata = {
+        IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
+};
+
+/*
+ * map the specified device/slot/pin to an IRQ.  This works out such
+ * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
+ */
+static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int intnr = ((slot - 9) + (pin - 1)) & 3;
+
+        return irq_tab[intnr];
+}
+
+static struct hw_pci pci_v3 __initdata = {
+        .swizzle                = pci_v3_swizzle,
+        .setup                  = pci_v3_setup,
+        .nr_controllers         = 1,
+        .ops                    = &pci_v3_ops,
+        .preinit                = pci_v3_preinit,
+        .postinit               = pci_v3_postinit,
+};
+
+#ifdef CONFIG_OF
+
+static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_irq oirq;
+        int ret;
+
+        ret = of_irq_map_pci(dev, &oirq);
+        if (ret) {
+                dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret);
+                /* Proper return code 0 == NO_IRQ */
+                return 0;
+        }
+
+        return irq_create_of_mapping(oirq.controller, oirq.specifier,
+                                     oirq.size);
+}
+
+static int __init pci_v3_dtprobe(struct platform_device *pdev,
+                                struct device_node *np)
+{
+        struct of_pci_range_parser parser;
+        struct of_pci_range range;
+        struct resource *res;
+        int irq, ret;
+
+        if (of_pci_range_parser_init(&parser, np))
+                return -EINVAL;
+
+        /* Get base for bridge registers */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
+                return -ENODEV;
+        }
+        pci_v3_base = devm_ioremap(&pdev->dev, res->start,
+                                   resource_size(res));
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+
+        /* Get and request error IRQ resource */
+        irq = platform_get_irq(pdev, 0);
+        if (irq <= 0) {
+                dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
+                return -ENODEV;
+        }
+        ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
+                        "PCIv3 error", NULL);
+        if (ret < 0) {
+                dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
+                return ret;
+        }
+
+        for_each_of_pci_range(&parser, &range) {
+                if (!range.flags) {
+                        of_pci_range_to_resource(&range, np, &conf_mem);
+                        conf_mem.name = "PCIv3 config";
+                }
+                if (range.flags & IORESOURCE_IO) {
+                        of_pci_range_to_resource(&range, np, &io_mem);
+                        io_mem.name = "PCIv3 I/O";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        !(range.flags & IORESOURCE_PREFETCH)) {
+                        non_mem_pci = range.pci_addr;
+                        non_mem_pci_sz = range.size;
+                        of_pci_range_to_resource(&range, np, &non_mem);
+                        non_mem.name = "PCIv3 non-prefetched mem";
+                }
+                if ((range.flags & IORESOURCE_MEM) &&
+                        (range.flags & IORESOURCE_PREFETCH)) {
+                        pre_mem_pci = range.pci_addr;
+                        pre_mem_pci_sz = range.size;
+                        of_pci_range_to_resource(&range, np, &pre_mem);
+                        pre_mem.name = "PCIv3 prefetched mem";
+                }
+        }
+
+        if (!conf_mem.start || !io_mem.start ||
+            !non_mem.start || !pre_mem.start) {
+                dev_err(&pdev->dev, "missing ranges in device node\n");
+                return -EINVAL;
+        }
+
+        pci_v3.map_irq = pci_v3_map_irq_dt;
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+
+        return 0;
+}
+
+#else
+
+static inline int pci_v3_dtprobe(struct platform_device *pdev,
+                                  struct device_node *np)
+{
+        return -EINVAL;
+}
+
+#endif
+
+static int __init pci_v3_probe(struct platform_device *pdev)
+{
+        struct device_node *np = pdev->dev.of_node;
+        int ret;
+
+        /* Remap the Integrator system controller */
+        ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
+        if (!ap_syscon_base) {
+                dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
+                return -ENODEV;
+        }
+
+        /* Device tree probe path */
+        if (np)
+                return pci_v3_dtprobe(pdev, np);
+
+        pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
+        if (!pci_v3_base) {
+                dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
+                return -ENODEV;
+        }
+
+        ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
+                        ret);
+                return -ENODEV;
+        }
+
+        conf_mem.name = "PCIv3 config";
+        conf_mem.start = PHYS_PCI_CONFIG_BASE;
+        conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
+        conf_mem.flags = IORESOURCE_MEM;
+
+        io_mem.name = "PCIv3 I/O";
+        io_mem.start = PHYS_PCI_IO_BASE;
+        io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
+        io_mem.flags = IORESOURCE_MEM;
+
+        non_mem_pci = 0x00000000;
+        non_mem_pci_sz = SZ_256M;
+        non_mem.name = "PCIv3 non-prefetched mem";
+        non_mem.start = PHYS_PCI_MEM_BASE;
+        non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1;
+        non_mem.flags = IORESOURCE_MEM;
+
+        pre_mem_pci = 0x10000000;
+        pre_mem_pci_sz = SZ_256M;
+        pre_mem.name = "PCIv3 prefetched mem";
+        pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M;
+        pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1;
+        pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+        pci_v3.map_irq = pci_v3_map_irq;
+
+        pci_common_init_dev(&pdev->dev, &pci_v3);
+
+        return 0;
+}
+
+static const struct of_device_id pci_ids[] = {
+        { .compatible = "v3,v360epc-pci", },
+        {},
+};
+
+static struct platform_driver pci_v3_driver = {
+        .driver = {
+                .name = "pci-v3",
+                .of_match_table = pci_ids,
+        },
+};
+
+static int __init pci_v3_init(void)
+{
+        return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
+}
+
+subsys_initcall(pci_v3_init);
+
+/*
+ * Static mappings for the PCIv3 bridge
+ *
+ * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
+ * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
+ * fee00000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
+ */
+static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
+        {
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }, {
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
+                .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE
+        }
+};
+
+int __init pci_v3_early_init(void)
+{
+        iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
+        vga_base = (unsigned long)PCI_MEMORY_VADDR;
+        pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
+        return 0;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h
new file mode 100644
index 000000000000..755fd29fed4a
--- /dev/null
+++ b/arch/arm/mach-integrator/pci_v3.h
@@ -0,0 +1,2 @@
+/* Simple oneliner include to the PCIv3 early init */
+extern int pci_v3_early_init(void);
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 183dc8b5511b..faaf7d4482c5 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,7 +23,7 @@
 
 #include "pci.h"
 
-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
+static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie,
         size_t size, unsigned int mtype, void *caller)
 {
         void __iomem * retval;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 3181f61ea63e..1c5bd7637b05 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -469,7 +469,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         break;
                 case IOP13XX_INIT_ADMA_1:
@@ -479,7 +478,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         break;
                 case IOP13XX_INIT_ADMA_2:
@@ -489,7 +487,6 @@ void __init iop13xx_platform_init(void)
                         dma_cap_set(DMA_MEMCPY, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR, plat_data->cap_mask);
                         dma_cap_set(DMA_XOR_VAL, plat_data->cap_mask);
-                        dma_cap_set(DMA_MEMSET, plat_data->cap_mask);
                         dma_cap_set(DMA_INTERRUPT, plat_data->cap_mask);
                         dma_cap_set(DMA_PQ, plat_data->cap_mask);
                         dma_cap_set(DMA_PQ_VAL, plat_data->cap_mask);
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 73a2d905af8a..30e1ebe3a891 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -235,7 +235,6 @@ config IXP4XX_QMGR
 config IXP4XX_NPE
         tristate "IXP4xx Network Processor Engine support"
         select FW_LOADER
-        select HOTPLUG
         help
           This driver supports IXP4xx built-in network coprocessors
           and is automatically selected by Ethernet and HSS drivers.
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 6600cff6bd92..d7223b3b81f3 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const char *cmd)
  * fallback to the default.
  */
 
-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size,
+static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
                                            unsigned int mtype, void *caller)
 {
         if (!is_pci_memory(addr))
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
new file mode 100644
index 000000000000..51a50e996840
--- /dev/null
+++ b/arch/arm/mach-keystone/Kconfig
@@ -0,0 +1,15 @@
+config ARCH_KEYSTONE
+        bool "Texas Instruments Keystone Devices"
+        depends on ARCH_MULTI_V7
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_ARM_ARCH_TIMER
+        select HAVE_SMP
+        select CLKSRC_MMIO
+        select GENERIC_CLOCKEVENTS
+        select HAVE_SCHED_CLOCK
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_ERRATA_798181 if SMP
+        help
+          Support for boards based on the Texas Instruments Keystone family of
+          SoCs.
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
new file mode 100644
index 000000000000..ddc52b05dc84
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile
@@ -0,0 +1,6 @@
+obj-y                                   := keystone.o smc.o
+
+plus_sec := $(call as-instr,.arch_extension sec,+sec)
+AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
+
+obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-keystone/Makefile.boot b/arch/arm/mach-keystone/Makefile.boot
new file mode 100644
index 000000000000..f3835c43af61
--- /dev/null
+++ b/arch/arm/mach-keystone/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x80008000
diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c
new file mode 100644
index 000000000000..fe4d9ff93a7e
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.c
@@ -0,0 +1,75 @@
+/*
+ * Keystone2 based boards and SOC related code.
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include <asm/setup.h>
+#include <asm/mach/map.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/smp_plat.h>
+
+#include "keystone.h"
+
+#define PLL_RESET_WRITE_KEY_MASK                0xffff0000
+#define PLL_RESET_WRITE_KEY                     0x5a69
+#define PLL_RESET                               BIT(16)
+
+static void __iomem *keystone_rstctrl;
+
+static void __init keystone_init(void)
+{
+        struct device_node *node;
+
+        node = of_find_compatible_node(NULL, NULL, "ti,keystone-reset");
+        if (WARN_ON(!node))
+                pr_warn("ti,keystone-reset node undefined\n");
+
+        keystone_rstctrl = of_iomap(node, 0);
+        if (WARN_ON(!keystone_rstctrl))
+                pr_warn("ti,keystone-reset iomap error\n");
+
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char *keystone_match[] __initconst = {
+        "ti,keystone-evm",
+        NULL,
+};
+
+void keystone_restart(char mode, const char *cmd)
+{
+        u32 val;
+
+        BUG_ON(!keystone_rstctrl);
+
+        /* Enable write access to RSTCTRL */
+        val = readl(keystone_rstctrl);
+        val &= PLL_RESET_WRITE_KEY_MASK;
+        val |= PLL_RESET_WRITE_KEY;
+        writel(val, keystone_rstctrl);
+
+        /* Reset the SOC */
+        val = readl(keystone_rstctrl);
+        val &= ~PLL_RESET;
+        writel(val, keystone_rstctrl);
+}
+
+DT_MACHINE_START(KEYSTONE, "Keystone")
+        .smp            = smp_ops(keystone_smp_ops),
+        .init_machine   = keystone_init,
+        .dt_compat      = keystone_match,
+        .restart        = keystone_restart,
+MACHINE_END
diff --git a/arch/arm/mach-keystone/keystone.h b/arch/arm/mach-keystone/keystone.h
new file mode 100644
index 000000000000..60bef9dedb12
--- /dev/null
+++ b/arch/arm/mach-keystone/keystone.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#ifndef __KEYSTONE_H__
+#define __KEYSTONE_H__
+
+#define KEYSTONE_MON_CPU_UP_IDX         0x00
+
+#ifndef __ASSEMBLER__
+
+extern struct smp_operations keystone_smp_ops;
+extern void secondary_startup(void);
+extern u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr);
+
+#endif /* __ASSEMBLER__ */
+#endif /* __KEYSTONE_H__ */
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
new file mode 100644
index 000000000000..1d4181e1daf2
--- /dev/null
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -0,0 +1,43 @@
+/*
+ * Keystone SOC SMP platform code
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *      Cyril Chemparathy <cyril@ti.com>
+ *      Santosh Shilimkar <santosh.shillimkar@ti.com>
+ *
+ * Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/smp_plat.h>
+#include <asm/prom.h>
+
+#include "keystone.h"
+
+static int __cpuinit keystone_smp_boot_secondary(unsigned int cpu,
+                                                struct task_struct *idle)
+{
+        unsigned long start = virt_to_phys(&secondary_startup);
+        int error;
+
+        pr_debug("keystone-smp: booting cpu %d, vector %08lx\n",
+                 cpu, start);
+
+        error = keystone_cpu_smc(KEYSTONE_MON_CPU_UP_IDX, cpu, start);
+        if (error)
+                pr_err("CPU %d bringup failed with %d\n", cpu, error);
+
+        return error;
+}
+
+struct smp_operations keystone_smp_ops __initdata = {
+        .smp_init_cpus          = arm_dt_init_cpu_maps,
+        .smp_boot_secondary     = keystone_smp_boot_secondary,
+};
diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S
new file mode 100644
index 000000000000..9b9e4f7b241e
--- /dev/null
+++ b/arch/arm/mach-keystone/smc.S
@@ -0,0 +1,29 @@
+/*
+ * Keystone Secure APIs
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+/**
+ * u32 keystone_cpu_smc(u32 command, u32 cpu, u32 addr)
+ *
+ * Low level CPU monitor API
+ * @command:    Monitor command.
+ * @cpu:        CPU Number
+ * @addr:       Kernel jump address for boot CPU
+ *
+ * Return: Non zero value on failure
+ */
+ENTRY(keystone_cpu_smc)
+        stmfd   sp!, {r4-r12, lr}
+        smc     #0
+        dsb
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(keystone_cpu_smc)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 7509a89af967..b634f9650a7b 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -8,12 +8,6 @@ config MACH_D2NET_V2
           Say 'Y' here if you want your kernel to support the
           LaCie d2 Network v2 NAS.
 
-config MACH_DB88F6281_BP
-        bool "Marvell DB-88F6281-BP Development Board"
-        help
-          Say 'Y' here if you want your kernel to support the
-          Marvell DB-88F6281-BP Development Board.
-
 config MACH_DOCKSTAR
         bool "Seagate FreeAgent DockStar"
         help
@@ -134,13 +128,12 @@ comment "Device tree entries"
 
 config ARCH_KIRKWOOD_DT
         bool "Marvell Kirkwood Flattened Device Tree"
+        select KIRKWOOD_CLK
         select POWER_SUPPLY
         select POWER_RESET
         select POWER_RESET_GPIO
         select REGULATOR
         select REGULATOR_FIXED_VOLTAGE
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_GATING
         select USE_OF
         help
           Say 'Y' here if you want your kernel to support the
@@ -153,6 +146,13 @@ config MACH_CLOUDBOX_DT
           Say 'Y' here if you want your kernel to support the LaCie
           CloudBox NAS, using Flattened Device Tree.
 
+config MACH_DB88F628X_BP_DT
+        bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
+        help
+          Say 'Y' here if you want your kernel to support the Marvell
+          DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
+          Device Tree).
+
 config MACH_DLINK_KIRKWOOD_DT
         bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -227,6 +227,7 @@ config MACH_KM_KIRKWOOD_DT
 config MACH_LSXL_DT
         bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
+        select POWER_RESET_RESTART
         help
           Say 'Y' here if you want your kernel to support the
           Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
@@ -272,14 +273,6 @@ config MACH_NETSPACE_V2_DT
           Say 'Y' here if you want your kernel to support the LaCie
           Network Space v2 NAS, using Flattened Device Tree.
 
-config MACH_NSA310_DT
-        bool "ZyXEL NSA-310 (Flattened Device Tree)"
-        select ARCH_KIRKWOOD_DT
-        select ARM_ATAG_DTB_COMPAT
-        help
-          Say 'Y' here if you want your kernel to support the
-          ZyXEL NSA-310 board (Flattened Device Tree).
-
 config MACH_OPENBLOCKS_A6_DT
         bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -296,6 +289,13 @@ config MACH_READYNAS_DT
           Say 'Y' here if you want your kernel to support the
           NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
 
+config MACH_SHEEVAPLUG_DT
+        bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell (eSATA) SheevaPlug (Flattened Device Tree).
+
 config MACH_TOPKICK_DT
         bool "USI Topkick (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -308,6 +308,7 @@ config MACH_TS219_DT
         select ARCH_KIRKWOOD_DT
         select ARM_APPENDED_DTB
         select ARM_ATAG_DTB_COMPAT
+        select POWER_RESET_QNAP
         help
           Say 'Y' here if you want your kernel to support the QNAP
           TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index e1f3735d3415..ac4cd75dd499 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,7 +1,6 @@
 obj-y                           += common.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_D2NET_V2)             += d2net_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_DB88F6281_BP)         += db88f6281-bp-setup.o
 obj-$(CONFIG_MACH_DOCKSTAR)             += dockstar-setup.o
 obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG)     += sheevaplug-setup.o
 obj-$(CONFIG_MACH_GURUPLUG)             += guruplug-setup.o
@@ -21,6 +20,7 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 
 obj-$(CONFIG_ARCH_KIRKWOOD_DT)          += board-dt.o
 obj-$(CONFIG_MACH_CLOUDBOX_DT)          += board-ns2.o
+obj-$(CONFIG_MACH_DB88F628X_BP_DT)      += board-db88f628x-bp.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_DREAMPLUG_DT)         += board-dreamplug.o
@@ -37,8 +37,8 @@ obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT)	+= board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT)   += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT)  += board-ns2.o
 obj-$(CONFIG_MACH_NETSPACE_V2_DT)       += board-ns2.o
-obj-$(CONFIG_MACH_NSA310_DT)            += board-nsa310.o
 obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT)     += board-openblocks_a6.o
 obj-$(CONFIG_MACH_READYNAS_DT)          += board-readynas.o
+obj-$(CONFIG_MACH_SHEEVAPLUG_DT)        += board-sheevaplug.o
 obj-$(CONFIG_MACH_TOPKICK_DT)           += board-usi_topkick.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
new file mode 100644
index 000000000000..2f574bc8ed40
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
@@ -0,0 +1,24 @@
+/*
+ * Saeed Bishara <saeed@marvell.com>
+ *
+ * Marvell DB-88F628{1,2}-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+void __init db88f628x_init(void)
+{
+        kirkwood_ge00_init(&db88f628x_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e9647b80cb59..6e122ed3282f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,7 +15,6 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
 #include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -25,11 +24,6 @@
 #include <plat/common.h>
 #include "common.h"
 
-static struct of_device_id kirkwood_dt_match_table[] __initdata = {
-        { .compatible = "simple-bus", },
-        { }
-};
-
 /*
  * There are still devices that doesn't know about DT yet.  Get clock
  * gates here and add a clock lookup alias, so that old platform
@@ -77,7 +71,7 @@ static void __init kirkwood_legacy_clk_init(void)
 
 static void __init kirkwood_of_clk_init(void)
 {
-        mvebu_clocks_init();
+        of_clk_init(NULL);
         kirkwood_legacy_clk_init();
 }
 
@@ -97,6 +91,8 @@ static void __init kirkwood_dt_init(void)
 
         kirkwood_l2_init();
 
+        kirkwood_cpufreq_init();
+
         /* Setup root of clk tree */
         kirkwood_of_clk_init();
 
@@ -112,6 +108,9 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("globalscale,guruplug"))
                 guruplug_dt_init();
 
+        if (of_machine_is_compatible("globalscale,sheevaplug"))
+                sheevaplug_dt_init();
+
         if (of_machine_is_compatible("dlink,dns-kirkwood"))
                 dnskw_init();
 
@@ -147,6 +146,10 @@ static void __init kirkwood_dt_init(void)
             of_machine_is_compatible("lacie,netspace_v2"))
                 ns2_init();
 
+        if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
+            of_machine_is_compatible("marvell,db-88f6282-bp"))
+                db88f628x_init();
+
         if (of_machine_is_compatible("mpl,cec4"))
                 mplcec4_init();
 
@@ -159,12 +162,13 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("usi,topkick"))
                 usi_topkick_init();
 
-        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
 static const char * const kirkwood_dt_board_compat[] = {
         "globalscale,dreamplug",
         "globalscale,guruplug",
+        "globalscale,sheevaplug",
         "dlink,dns-320",
         "dlink,dns-325",
         "iom,iconnect",
@@ -181,6 +185,8 @@ static const char * const kirkwood_dt_board_compat[] = {
         "lacie,netspace_max_v2",
         "lacie,netspace_mini_v2",
         "lacie,netspace_v2",
+        "marvell,db-88f6281-bp",
+        "marvell,db-88f6282-bp",
         "mpl,cec4",
         "netgear,readynas-duo-v2",
         "plathome,openblocks-a6",
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index c8ebde4919e2..98b5ad1bba90 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -22,11 +22,3 @@ void __init iconnect_init(void)
 {
         kirkwood_ge00_init(&iconnect_ge00_data);
 }
-
-static int __init iconnect_pci_init(void)
-{
-        if (of_machine_is_compatible("iom,iconnect"))
-                kirkwood_pcie_init(KW_PCIE0);
-        return 0;
-}
-subsys_initcall(iconnect_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
index 4ec8b7ae784a..348395238df6 100644
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -25,19 +25,6 @@ static struct mv643xx_eth_platform_data lsxl_ge01_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
-/*
- * On the LS-XHL/LS-CHLv2, the shutdown process is following:
- * - Userland monitors key events until the power switch goes to off position
- * - The board reboots
- * - U-boot starts and goes into an idle mode waiting for the user
- *   to move the switch to ON position
- *
- */
-static void lsxl_power_off(void)
-{
-        kirkwood_restart('h', NULL);
-}
-
 void __init lsxl_init(void)
 {
         /*
@@ -46,7 +33,4 @@ void __init lsxl_init(void)
 
         kirkwood_ge00_init(&lsxl_ge00_data);
         kirkwood_ge01_init(&lsxl_ge01_data);
-
-        /* register power-off method */
-        pm_power_off = lsxl_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
index 7d6dc669e17f..938712e248f1 100644
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ b/arch/arm/mach-kirkwood/board-mplcec4.c
@@ -29,7 +29,6 @@ void __init mplcec4_init(void)
          */
         kirkwood_ge00_init(&mplcec4_ge00_data);
         kirkwood_ge01_init(&mplcec4_ge01_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
 
 
diff --git a/arch/arm/mach-kirkwood/board-nsa310.c b/arch/arm/mach-kirkwood/board-nsa310.c
deleted file mode 100644
index 55ade93b93bf..000000000000
--- a/arch/arm/mach-kirkwood/board-nsa310.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/nsa-310-setup.c
- *
- * ZyXEL NSA-310 Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <mach/kirkwood.h>
-#include <linux/of.h>
-#include "common.h"
-
-static int __init nsa310_pci_init(void)
-{
-        if (of_machine_is_compatible("zyxel,nsa310"))
-                kirkwood_pcie_init(KW_PCIE0);
-
-        return 0;
-}
-
-subsys_initcall(nsa310_pci_init);
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
index fb42c20e273f..341b82d9cadb 100644
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ b/arch/arm/mach-kirkwood/board-readynas.c
@@ -24,5 +24,4 @@ static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
 void __init netgear_readynas_init(void)
 {
         kirkwood_ge00_init(&netgear_readynas_ge00_data);
-        kirkwood_pcie_init(KW_PCIE0);
 }
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
new file mode 100644
index 000000000000..fa389373ca74
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-sheevaplug.c
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-kirkwood/board-sheevaplug.c
+ *
+ * Marvell Sheevaplug Reference Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include "common.h"
+
+static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+void __init sheevaplug_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_ge00_init(&sheevaplug_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
index 4695d5f35fc9..860f44ab457d 100644
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -23,7 +23,6 @@
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
-#include "tsx1x-common.h"
 
 static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
@@ -38,6 +37,4 @@ void __init qnap_dt_ts219_init(void)
                 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
 
         kirkwood_ge00_init(&qnap_ts219_ge00_data);
-
-        pm_power_off = qnap_tsx1x_power_off;
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f38922897563..7c72c725b711 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -598,6 +598,29 @@ void __init kirkwood_audio_init(void)
 }
 
 /*****************************************************************************
+ * CPU Frequency
+ ****************************************************************************/
+static struct resource kirkwood_cpufreq_resources[] = {
+        [0] = {
+                .start  = CPU_CONTROL_PHYS,
+                .end    = CPU_CONTROL_PHYS + 3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device kirkwood_cpufreq_device = {
+        .name           = "kirkwood-cpufreq",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(kirkwood_cpufreq_resources),
+        .resource       = kirkwood_cpufreq_resources,
+};
+
+void __init kirkwood_cpufreq_init(void)
+{
+        platform_device_register(&kirkwood_cpufreq_device);
+}
+
+/*****************************************************************************
  * General
  ****************************************************************************/
 /*
@@ -648,30 +671,6 @@ char * __init kirkwood_id(void)
 
 void __init kirkwood_setup_wins(void)
 {
-        /*
-         * The PCIe windows will no longer be statically allocated
-         * here once Kirkwood is migrated to the pci-mvebu driver.
-         */
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE_IO_SIZE,
-                                          KIRKWOOD_PCIE_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie0.0",
-                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_IO_SIZE,
-                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
-                                          MVEBU_MBUS_PCI_IO);
-        mvebu_mbus_add_window_remap_flags("pcie1.0",
-                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
-                                          KIRKWOOD_PCIE1_MEM_SIZE,
-                                          MVEBU_MBUS_NO_REMAP,
-                                          MVEBU_MBUS_PCI_MEM);
         mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE,
                               KIRKWOOD_NAND_MEM_SIZE);
         mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE,
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 21da3b1ebd7b..1c09f3f93fbb 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -51,6 +51,8 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
                             int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
 void kirkwood_cpuidle_init(void);
+void kirkwood_cpufreq_init(void);
+
 void kirkwood_restart(char, const char *);
 void kirkwood_clk_init(void);
 
@@ -65,6 +67,11 @@ void guruplug_dt_init(void);
 #else
 static inline void guruplug_dt_init(void) {};
 #endif
+#ifdef CONFIG_MACH_SHEEVAPLUG_DT
+void sheevaplug_dt_init(void);
+#else
+static inline void sheevaplug_dt_init(void) {};
+#endif
 #ifdef CONFIG_MACH_TS219_DT
 void qnap_dt_ts219_init(void);
 #else
@@ -119,6 +126,12 @@ void km_kirkwood_init(void);
 static inline void km_kirkwood_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DB88F628X_BP_DT
+void db88f628x_init(void);
+#else
+static inline void db88f628x_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_MPLCEC4_DT
 void mplcec4_init(void);
 #else
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
deleted file mode 100644
index 5a369fe74754..000000000000
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
- *
- * Marvell DB-88F6281-BP Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/sizes.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/kirkwood.h>
-#include <linux/platform_data/mmc-mvsdio.h>
-#include "common.h"
-#include "mpp.h"
-
-static struct mtd_partition db88f6281_nand_parts[] = {
-        {
-                .name = "u-boot",
-                .offset = 0,
-                .size = SZ_1M
-        }, {
-                .name = "uImage",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = SZ_4M
-        }, {
-                .name = "root",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size = MTDPART_SIZ_FULL
-        },
-};
-
-static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-
-static struct mv_sata_platform_data db88f6281_sata_data = {
-        .n_ports        = 2,
-};
-
-static struct mvsdio_platform_data db88f6281_mvsdio_data = {
-        .gpio_write_protect     = 37,
-        .gpio_card_detect       = 38,
-};
-
-static unsigned int db88f6281_mpp_config[] __initdata = {
-        MPP0_NF_IO2,
-        MPP1_NF_IO3,
-        MPP2_NF_IO4,
-        MPP3_NF_IO5,
-        MPP4_NF_IO6,
-        MPP5_NF_IO7,
-        MPP18_NF_IO0,
-        MPP19_NF_IO1,
-        MPP37_GPIO,
-        MPP38_GPIO,
-        0
-};
-
-static void __init db88f6281_init(void)
-{
-        /*
-         * Basic setup. Needs to be called early.
-         */
-        kirkwood_init();
-        kirkwood_mpp_conf(db88f6281_mpp_config);
-
-        kirkwood_nand_init(ARRAY_AND_SIZE(db88f6281_nand_parts), 25);
-        kirkwood_ehci_init();
-        kirkwood_ge00_init(&db88f6281_ge00_data);
-        kirkwood_sata_init(&db88f6281_sata_data);
-        kirkwood_uart0_init();
-        kirkwood_sdio_init(&db88f6281_mvsdio_data);
-}
-
-static int __init db88f6281_pci_init(void)
-{
-        if (machine_is_db88f6281_bp()) {
-                u32 dev, rev;
-
-                kirkwood_pcie_id(&dev, &rev);
-                if (dev == MV88F6282_DEV_ID)
-                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
-                else
-                        kirkwood_pcie_init(KW_PCIE0);
-        }
-        return 0;
-}
-subsys_initcall(db88f6281_pci_init);
-
-MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
-        /* Maintainer: Saeed Bishara <saeed@marvell.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = db88f6281_init,
-        .map_io         = kirkwood_map_io,
-        .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
-        .init_time      = kirkwood_timer_init,
-        .restart        = kirkwood_restart,
-MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 5c82b7dce4e2..d4cbe5e81bb4 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -17,6 +17,7 @@
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
 #define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
+#define CPU_CONTROL_PHYS        (BRIDGE_PHYS_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 
 #define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
@@ -69,6 +70,7 @@
 #define CGC_RUNIT               (1 << 7)
 #define CGC_XOR0                (1 << 8)
 #define CGC_AUDIO               (1 << 9)
+#define CGC_POWERSAVE           (1 << 11)
 #define CGC_SATA0               (1 << 14)
 #define CGC_SATA1               (1 << 15)
 #define CGC_XOR1                (1 << 16)
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 827cde42414f..e96fd71abd76 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
-            (dev == MV88F6282_DEV_ID))
+        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
                 return MPP_F6281_MASK;
+        if (dev == MV88F6282_DEV_ID)
+                return MPP_F6282_MASK;
         if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                 return MPP_F6192_MASK;
         if (dev == MV88F6180_DEV_ID)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 7f43e6c2f8c0..ddcb09f5bdd3 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,6 +12,7 @@
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/clk.h>
+#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
@@ -253,6 +254,27 @@ static void __init add_pcie_port(int index, void __iomem *base)
 
 void __init kirkwood_pcie_init(unsigned int portmask)
 {
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE_IO_SIZE,
+                                          KIRKWOOD_PCIE_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie0.0",
+                                          KIRKWOOD_PCIE_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_IO_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_IO_SIZE,
+                                          KIRKWOOD_PCIE1_IO_BUS_BASE,
+                                          MVEBU_MBUS_PCI_IO);
+        mvebu_mbus_add_window_remap_flags("pcie1.0",
+                                          KIRKWOOD_PCIE1_MEM_PHYS_BASE,
+                                          KIRKWOOD_PCIE1_MEM_SIZE,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+
         vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
 
         if (portmask & KW_PCIE0)
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 5b660ec09ef5..0c002099c3a3 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -210,7 +210,7 @@ struct pxa168fb_mach_info aspenite_lcd_info = {
         .invert_pixclock        = 0,
 };
 
-static unsigned int aspenite_matrix_key_map[] = {
+static const unsigned int aspenite_matrix_key_map[] = {
         KEY(0, 6, KEY_UP),      /* SW 4 */
         KEY(0, 7, KEY_DOWN),    /* SW 5 */
         KEY(1, 6, KEY_LEFT),    /* SW 6 */
@@ -219,11 +219,15 @@ static unsigned int aspenite_matrix_key_map[] = {
         KEY(4, 7, KEY_ESC),     /* SW 9 */
 };
 
+static struct matrix_keymap_data aspenite_matrix_keymap_data = {
+        .keymap                 = aspenite_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(aspenite_matrix_key_map),
+};
+
 static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
         .matrix_key_rows        = 5,
         .matrix_key_cols        = 8,
-        .matrix_key_map         = aspenite_matrix_key_map,
-        .matrix_key_map_size    = ARRAY_SIZE(aspenite_matrix_key_map),
+        .matrix_keymap_data     = &aspenite_matrix_keymap_data,
         .debounce_interval      = 30,
 };
 
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index e4d95b4c6bb2..6aa53fb29d26 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -61,11 +61,15 @@ static unsigned int teton_bga_matrix_key_map[] = {
         KEY(1, 7, KEY_RIGHT),
 };
 
+static struct matrix_keymap_data teton_bga_matrix_keymap_data = {
+        .keymap                 = teton_bga_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(teton_bga_matrix_key_map),
+};
+
 static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
         .matrix_key_rows        = 2,
         .matrix_key_cols        = 8,
-        .matrix_key_map         = teton_bga_matrix_key_map,
-        .matrix_key_map_size    = ARRAY_SIZE(teton_bga_matrix_key_map),
+        .matrix_keymap_data     = &teton_bga_matrix_keymap_data,
         .debounce_interval      = 30,
 };
 
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index fceb093b9494..614e41e7881b 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -48,9 +48,7 @@ config ARCH_MSM8X60
         select CPU_V7
         select GPIO_MSM_V2
         select HAVE_SMP
-        select MSM_GPIOMUX
         select MSM_SCM if SMP
-        select MSM_V2_TLMM
         select USE_OF
 
 config ARCH_MSM8960
@@ -58,9 +56,8 @@ config ARCH_MSM8960
         select ARM_GIC
         select CPU_V7
         select HAVE_SMP
-        select MSM_GPIOMUX
+        select GPIO_MSM_V2
         select MSM_SCM if SMP
-        select MSM_V2_TLMM
         select USE_OF
 
 config MSM_HAS_DEBUG_UART_HS
@@ -124,10 +121,10 @@ config MSM_SMD
         bool
 
 config MSM_GPIOMUX
-        bool
-
-config MSM_V2_TLMM
-        bool
+        depends on !(ARCH_MSM8X60 || ARCH_MSM8960)
+        bool "MSM V1 TLMM GPIOMUX architecture"
+        help
+          Support for MSM V1 TLMM GPIOMUX architecture.
 
 config MSM_SCM
         bool
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 17519faf082f..d257ff40e16b 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,18 @@
 obj-y += io.o timer.o
 obj-y += clock.o
-obj-$(CONFIG_DEBUG_FS) += clock-debug.o
 
 obj-$(CONFIG_MSM_VIC) += irq-vic.o
 obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
 
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
-obj-$(CONFIG_ARCH_MSM7X30) += dma.o
-obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
+obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
+obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 
 obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
 
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o
+obj-$(CONFIG_ARCH_MSM7X30) += dma.o
+obj-$(CONFIG_ARCH_QSD8X50) += dma.o
+
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 obj-$(CONFIG_MSM_SCM) += scm.o scm-boot.o
@@ -27,7 +29,5 @@ obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
 obj-$(CONFIG_ARCH_MSM8X60) += board-dt-8660.o
 obj-$(CONFIG_ARCH_MSM8960) += board-dt-8960.o
-
-obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-v1.o gpiomux.o
-obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
-obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
+obj-$(CONFIG_MSM_GPIOMUX) += gpiomux.o
+obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 7dcfc5300bbd..492f5cd87b0a 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
 
@@ -44,7 +43,6 @@ static const char *msm8x60_fluid_match[] __initdata = {
 DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
         .smp = smp_ops(msm_smp_ops),
         .map_io = msm_map_msm8x60_io,
-        .init_irq = irqchip_init,
         .init_machine = msm8x60_dt_init,
         .init_late = msm8x60_init_late,
         .init_time      = msm_dt_timer_init,
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index 73019363ffa4..bb5530957c4f 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 
 #include <asm/mach/arch.h>
@@ -31,7 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
 DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
         .smp = smp_ops(msm_smp_ops),
         .map_io = msm_map_msm8960_io,
-        .init_irq = irqchip_init,
         .init_time      = msm_dt_timer_init,
         .init_machine = msm_dt_init,
         .dt_compat = msm8960_dt_match,
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 82eaf88d2026..803651ad4f62 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x01a,
         &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
@@ -91,7 +92,6 @@ static void __init halibut_fixup(struct tag *tags, char **cmdline,
 static void __init halibut_map_io(void)
 {
         msm_map_common_io();
-        msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
 }
 
 static void __init halibut_init_late(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 520c141acd03..db3d8c0bc8a4 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x30,
         &msm_device_gpio_7x30,
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
@@ -116,7 +117,6 @@ static void __init msm7x30_init(void)
 static void __init msm7x30_map_io(void)
 {
         msm_map_msm7x30_io();
-        msm_clock_init(msm_clocks_7x30, msm_num_clocks_7x30);
 }
 
 static void __init msm7x30_init_late(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 38a532d6937c..f14a73d86bc0 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_8x50,
         &msm_device_gpio_8x50,
         &msm_device_uart3,
         &msm_device_smd,
@@ -172,7 +173,6 @@ static void __init qsd8x50_init_mmc(void)
 static void __init qsd8x50_map_io(void)
 {
         msm_map_qsd8x50_io();
-        msm_clock_init(msm_clocks_8x50, msm_num_clocks_8x50);
 }
 
 static void __init qsd8x50_init_irq(void)
diff --git a/arch/arm/mach-msm/board-trout-panel.c b/arch/arm/mach-msm/board-trout-panel.c
index f9a5db6d2ced..77b0a26f897f 100644
--- a/arch/arm/mach-msm/board-trout-panel.c
+++ b/arch/arm/mach-msm/board-trout-panel.c
@@ -7,7 +7,6 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/leds.h>
-#include <linux/clk.h>
 #include <linux/err.h>
 
 #include <asm/io.h>
@@ -19,6 +18,7 @@
 
 #include "board-trout.h"
 #include "proc_comm.h"
+#include "clock-pcom.h"
 #include "devices.h"
 
 #define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255
@@ -170,7 +170,6 @@ static struct mddi_table mddi_toshiba_init_table[] = {
 #define INTMASK_VWAKEOUT (1U << 0)
 
 
-static struct clk *gp_clk;
 static int trout_new_backlight = 1;
 static struct vreg *vreg_mddi_1v5;
 static struct vreg *vreg_lcm_2v85;
@@ -273,18 +272,14 @@ int __init trout_init_panel(void)
         } else {
                 uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT,
                                                 GPIO_NO_PULL, GPIO_8MA);
+                uint32_t id = P_GP_CLK;
+                uint32_t rate = 19200000;
+
                 msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0);
 
-                gp_clk = clk_get(NULL, "gp_clk");
-                if (IS_ERR(gp_clk)) {
-                        printk(KERN_ERR "trout_init_panel: could not get gp"
-                               "clock\n");
-                        gp_clk = NULL;
-                }
-                rc = clk_set_rate(gp_clk, 19200000);
-                if (rc)
-                        printk(KERN_ERR "trout_init_panel: set clock rate "
-                               "failed\n");
+                msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
+                if (id < 0)
+                        pr_err("trout_init_panel: set clock rate failed\n");
         }
 
         rc = platform_device_register(&msm_device_mdp);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 80fe1c5ff5c1..64a46eb4fc49 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
 extern int trout_init_mmc(unsigned int);
 
 static struct platform_device *devices[] __initdata = {
+        &msm_clock_7x01a,
         &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
@@ -94,8 +95,6 @@ static void __init trout_map_io(void)
         /* route UART3 to the "H2W" extended usb connector */
         writeb(0x80, TROUT_CPLD_BASE + 0x00);
 #endif
-
-        msm_clock_init(msm_clocks_7x01a, msm_num_clocks_7x01a);
 }
 
 static void __init trout_init_late(void)
diff --git a/arch/arm/mach-msm/clock-7x30.h b/arch/arm/mach-msm/clock-7x30.h
deleted file mode 100644
index 14104453688b..000000000000
--- a/arch/arm/mach-msm/clock-7x30.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-#define __ARCH_ARM_MACH_MSM_CLOCK_7X30_H
-
-enum {
-        L_7X30_NONE_CLK = -1,
-        L_7X30_ADM_CLK,
-        L_7X30_I2C_CLK,
-        L_7X30_I2C_2_CLK,
-        L_7X30_QUP_I2C_CLK,
-        L_7X30_UART1DM_CLK,
-        L_7X30_UART1DM_P_CLK,
-        L_7X30_UART2DM_CLK,
-        L_7X30_UART2DM_P_CLK,
-        L_7X30_EMDH_CLK,
-        L_7X30_EMDH_P_CLK,
-        L_7X30_PMDH_CLK,
-        L_7X30_PMDH_P_CLK,
-        L_7X30_GRP_2D_CLK,
-        L_7X30_GRP_2D_P_CLK,
-        L_7X30_GRP_3D_SRC_CLK,
-        L_7X30_GRP_3D_CLK,
-        L_7X30_GRP_3D_P_CLK,
-        L_7X30_IMEM_CLK,
-        L_7X30_SDC1_CLK,
-        L_7X30_SDC1_P_CLK,
-        L_7X30_SDC2_CLK,
-        L_7X30_SDC2_P_CLK,
-        L_7X30_SDC3_CLK,
-        L_7X30_SDC3_P_CLK,
-        L_7X30_SDC4_CLK,
-        L_7X30_SDC4_P_CLK,
-        L_7X30_MDP_CLK,
-        L_7X30_MDP_P_CLK,
-        L_7X30_MDP_LCDC_PCLK_CLK,
-        L_7X30_MDP_LCDC_PAD_PCLK_CLK,
-        L_7X30_MDP_VSYNC_CLK,
-        L_7X30_MI2S_CODEC_RX_M_CLK,
-        L_7X30_MI2S_CODEC_RX_S_CLK,
-        L_7X30_MI2S_CODEC_TX_M_CLK,
-        L_7X30_MI2S_CODEC_TX_S_CLK,
-        L_7X30_MI2S_M_CLK,
-        L_7X30_MI2S_S_CLK,
-        L_7X30_LPA_CODEC_CLK,
-        L_7X30_LPA_CORE_CLK,
-        L_7X30_LPA_P_CLK,
-        L_7X30_MIDI_CLK,
-        L_7X30_MDC_CLK,
-        L_7X30_ROTATOR_IMEM_CLK,
-        L_7X30_ROTATOR_P_CLK,
-        L_7X30_SDAC_M_CLK,
-        L_7X30_SDAC_CLK,
-        L_7X30_UART1_CLK,
-        L_7X30_UART2_CLK,
-        L_7X30_UART3_CLK,
-        L_7X30_TV_CLK,
-        L_7X30_TV_DAC_CLK,
-        L_7X30_TV_ENC_CLK,
-        L_7X30_HDMI_CLK,
-        L_7X30_TSIF_REF_CLK,
-        L_7X30_TSIF_P_CLK,
-        L_7X30_USB_HS_SRC_CLK,
-        L_7X30_USB_HS_CLK,
-        L_7X30_USB_HS_CORE_CLK,
-        L_7X30_USB_HS_P_CLK,
-        L_7X30_USB_HS2_CLK,
-        L_7X30_USB_HS2_CORE_CLK,
-        L_7X30_USB_HS2_P_CLK,
-        L_7X30_USB_HS3_CLK,
-        L_7X30_USB_HS3_CORE_CLK,
-        L_7X30_USB_HS3_P_CLK,
-        L_7X30_VFE_CLK,
-        L_7X30_VFE_P_CLK,
-        L_7X30_VFE_MDC_CLK,
-        L_7X30_VFE_CAMIF_CLK,
-        L_7X30_CAMIF_PAD_P_CLK,
-        L_7X30_CAM_M_CLK,
-        L_7X30_JPEG_CLK,
-        L_7X30_JPEG_P_CLK,
-        L_7X30_VPE_CLK,
-        L_7X30_MFC_CLK,
-        L_7X30_MFC_DIV2_CLK,
-        L_7X30_MFC_P_CLK,
-        L_7X30_SPI_CLK,
-        L_7X30_SPI_P_CLK,
-        L_7X30_CSI0_CLK,
-        L_7X30_CSI0_VFE_CLK,
-        L_7X30_CSI0_P_CLK,
-        L_7X30_CSI1_CLK,
-        L_7X30_CSI1_VFE_CLK,
-        L_7X30_CSI1_P_CLK,
-        L_7X30_GLBL_ROOT_CLK,
-
-        L_7X30_AXI_LI_VG_CLK,
-        L_7X30_AXI_LI_GRP_CLK,
-        L_7X30_AXI_LI_JPEG_CLK,
-        L_7X30_AXI_GRP_2D_CLK,
-        L_7X30_AXI_MFC_CLK,
-        L_7X30_AXI_VPE_CLK,
-        L_7X30_AXI_LI_VFE_CLK,
-        L_7X30_AXI_LI_APPS_CLK,
-        L_7X30_AXI_MDP_CLK,
-        L_7X30_AXI_IMEM_CLK,
-        L_7X30_AXI_LI_ADSP_A_CLK,
-        L_7X30_AXI_ROTATOR_CLK,
-
-        L_7X30_NR_CLKS
-};
-
-struct clk_ops;
-extern struct clk_ops clk_ops_7x30;
-
-struct clk_ops *clk_7x30_is_local(uint32_t id);
-int clk_7x30_init(void);
-
-void pll_enable(uint32_t pll);
-void pll_disable(uint32_t pll);
-
-extern int internal_pwr_rail_ctl_auto(unsigned rail_id, bool enable);
-
-#define CLK_7X30(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .con_id = clk_name, \
-        .dev_id = clk_dev, \
-        .clk = &(struct clk){ \
-                .id = L_7X30_##clk_id, \
-                .remote_id = P_##clk_id, \
-                .flags = clk_flags, \
-                .dbg_name = #clk_id, \
-        }, \
-        }
-
-#define CLK_7X30S(clk_name, l_id, r_id, clk_dev, clk_flags) {   \
-        .con_id = clk_name, \
-        .dev_id = clk_dev, \
-        .clk = &(struct clk){ \
-                .id = L_7X30_##l_id, \
-                .remote_id = P_##r_id, \
-                .flags = clk_flags, \
-                .dbg_name = #l_id, \
-                .ops = &clk_ops_pcom, \
-        }, \
-        }
-
-#endif
diff --git a/arch/arm/mach-msm/clock-debug.c b/arch/arm/mach-msm/clock-debug.c
deleted file mode 100644
index 4886404d42f5..000000000000
--- a/arch/arm/mach-msm/clock-debug.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/ctype.h>
-#include <linux/debugfs.h>
-#include <linux/clk.h>
-#include "clock.h"
-
-static int clock_debug_rate_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int ret;
-
-        /* Only increases to max rate will succeed, but that's actually good
-         * for debugging purposes so we don't check for error. */
-        if (clock->flags & CLK_MAX)
-                clk_set_max_rate(clock, val);
-        if (clock->flags & CLK_MIN)
-                ret = clk_set_min_rate(clock, val);
-        else
-                ret = clk_set_rate(clock, val);
-        if (ret != 0)
-                printk(KERN_ERR "clk_set%s_rate failed (%d)\n",
-                        (clock->flags & CLK_MIN) ? "_min" : "", ret);
-        return ret;
-}
-
-static int clock_debug_rate_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-        *val = clk_get_rate(clock);
-        return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
-                        clock_debug_rate_set, "%llu\n");
-
-static int clock_debug_enable_set(void *data, u64 val)
-{
-        struct clk *clock = data;
-        int rc = 0;
-
-        if (val)
-                rc = clock->ops->enable(clock->id);
-        else
-                clock->ops->disable(clock->id);
-
-        return rc;
-}
-
-static int clock_debug_enable_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-
-        *val = clock->ops->is_enabled(clock->id);
-
-        return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
-                        clock_debug_enable_set, "%llu\n");
-
-static int clock_debug_local_get(void *data, u64 *val)
-{
-        struct clk *clock = data;
-
-        *val = clock->ops->is_local(clock->id);
-
-        return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(clock_local_fops, clock_debug_local_get,
-                        NULL, "%llu\n");
-
-static struct dentry *debugfs_base;
-
-int __init clock_debug_init(void)
-{
-        debugfs_base = debugfs_create_dir("clk", NULL);
-        if (!debugfs_base)
-                return -ENOMEM;
-        return 0;
-}
-
-int __init clock_debug_add(struct clk *clock)
-{
-        char temp[50], *ptr;
-        struct dentry *clk_dir;
-
-        if (!debugfs_base)
-                return -ENOMEM;
-
-        strncpy(temp, clock->dbg_name, ARRAY_SIZE(temp)-1);
-        for (ptr = temp; *ptr; ptr++)
-                *ptr = tolower(*ptr);
-
-        clk_dir = debugfs_create_dir(temp, debugfs_base);
-        if (!clk_dir)
-                return -ENOMEM;
-
-        if (!debugfs_create_file("rate", S_IRUGO | S_IWUSR, clk_dir,
-                                clock, &clock_rate_fops))
-                goto error;
-
-        if (!debugfs_create_file("enable", S_IRUGO | S_IWUSR, clk_dir,
-                                clock, &clock_enable_fops))
-                goto error;
-
-        if (!debugfs_create_file("is_local", S_IRUGO, clk_dir, clock,
-                                &clock_local_fops))
-                goto error;
-        return 0;
-error:
-        debugfs_remove_recursive(clk_dir);
-        return -ENOMEM;
-}
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index a52c970df157..9a80449518e6 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -13,20 +13,33 @@
  *
  */
 
+#include <linux/kernel.h>
 #include <linux/err.h>
-#include <linux/ctype.h>
-#include <linux/stddef.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+
 #include <mach/clk.h>
 
 #include "proc_comm.h"
 #include "clock.h"
 #include "clock-pcom.h"
 
-/*
- * glue for the proc_comm interface
- */
-static int pc_clk_enable(unsigned id)
+struct clk_pcom {
+        unsigned id;
+        unsigned long flags;
+        struct msm_clk msm_clk;
+};
+
+static inline struct clk_pcom *to_clk_pcom(struct clk_hw *hw)
 {
+        return container_of(to_msm_clk(hw), struct clk_pcom, msm_clk);
+}
+
+static int pc_clk_enable(struct clk_hw *hw)
+{
+        unsigned id = to_clk_pcom(hw)->id;
         int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
         if (rc < 0)
                 return rc;
@@ -34,14 +47,16 @@ static int pc_clk_enable(unsigned id)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-static void pc_clk_disable(unsigned id)
+static void pc_clk_disable(struct clk_hw *hw)
 {
+        unsigned id = to_clk_pcom(hw)->id;
         msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
 }
 
-int pc_clk_reset(unsigned id, enum clk_reset_action action)
+static int pc_clk_reset(struct clk_hw *hw, enum clk_reset_action action)
 {
         int rc;
+        unsigned id = to_clk_pcom(hw)->id;
 
         if (action == CLK_RESET_ASSERT)
                 rc = msm_proc_comm(PCOM_CLKCTL_RPC_RESET_ASSERT, &id, NULL);
@@ -54,85 +69,109 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-static int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(struct clk_hw *hw, unsigned long new_rate,
+                           unsigned long p_rate)
 {
-        /* The rate _might_ be rounded off to the nearest KHz value by the
+        struct clk_pcom *p = to_clk_pcom(hw);
+        unsigned id = p->id, rate = new_rate;
+        int rc;
+
+        /*
+         * The rate _might_ be rounded off to the nearest KHz value by the
          * remote function. So a return value of 0 doesn't necessarily mean
          * that the exact rate was set successfully.
          */
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_min_rate(unsigned id, unsigned rate)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
-        else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_max_rate(unsigned id, unsigned rate)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
-        if (rc < 0)
-                return rc;
+        if (p->flags & CLKFLAG_MIN)
+                rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
         else
-                return (int)id < 0 ? -EINVAL : 0;
-}
-
-static int pc_clk_set_flags(unsigned id, unsigned flags)
-{
-        int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
+                rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_RATE, &id, &rate);
         if (rc < 0)
                 return rc;
         else
                 return (int)id < 0 ? -EINVAL : 0;
 }
 
-static unsigned pc_clk_get_rate(unsigned id)
+static unsigned long pc_clk_recalc_rate(struct clk_hw *hw, unsigned long p_rate)
 {
+        unsigned id = to_clk_pcom(hw)->id;
         if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
                 return 0;
         else
                 return id;
 }
 
-static unsigned pc_clk_is_enabled(unsigned id)
+static int pc_clk_is_enabled(struct clk_hw *hw)
 {
+        unsigned id = to_clk_pcom(hw)->id;
         if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
                 return 0;
         else
                 return id;
 }
 
-static long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long *p_rate)
 {
-
         /* Not really supported; pc_clk_set_rate() does rounding on it's own. */
         return rate;
 }
 
-static bool pc_clk_is_local(unsigned id)
-{
-        return false;
-}
-
-struct clk_ops clk_ops_pcom = {
+static struct clk_ops clk_ops_pcom = {
         .enable = pc_clk_enable,
         .disable = pc_clk_disable,
-        .auto_off = pc_clk_disable,
-        .reset = pc_clk_reset,
         .set_rate = pc_clk_set_rate,
-        .set_min_rate = pc_clk_set_min_rate,
-        .set_max_rate = pc_clk_set_max_rate,
-        .set_flags = pc_clk_set_flags,
-        .get_rate = pc_clk_get_rate,
+        .recalc_rate = pc_clk_recalc_rate,
         .is_enabled = pc_clk_is_enabled,
         .round_rate = pc_clk_round_rate,
-        .is_local = pc_clk_is_local,
 };
+
+static int msm_clock_pcom_probe(struct platform_device *pdev)
+{
+        const struct pcom_clk_pdata *pdata = pdev->dev.platform_data;
+        int i, ret;
+
+        for (i = 0; i < pdata->num_lookups; i++) {
+                const struct clk_pcom_desc *desc = &pdata->lookup[i];
+                struct clk *c;
+                struct clk_pcom *p;
+                struct clk_hw *hw;
+                struct clk_init_data init;
+
+                p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+                if (!p)
+                        return -ENOMEM;
+
+                p->id = desc->id;
+                p->flags = desc->flags;
+                p->msm_clk.reset = pc_clk_reset;
+
+                hw = &p->msm_clk.hw;
+                hw->init = &init;
+
+                init.name = desc->name;
+                init.ops = &clk_ops_pcom;
+                init.num_parents = 0;
+                init.flags = CLK_IS_ROOT;
+
+                if (!(p->flags & CLKFLAG_AUTO_OFF))
+                        init.flags |= CLK_IGNORE_UNUSED;
+
+                c = devm_clk_register(&pdev->dev, hw);
+                ret = clk_register_clkdev(c, desc->con, desc->dev);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static struct platform_driver msm_clock_pcom_driver = {
+        .probe          = msm_clock_pcom_probe,
+        .driver         = {
+                .name   = "msm-clock-pcom",
+                .owner  = THIS_MODULE,
+        },
+};
+module_platform_driver(msm_clock_pcom_driver);
+
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-msm/clock-pcom.h b/arch/arm/mach-msm/clock-pcom.h
index 974d0032f3a3..5bb164fd46a8 100644
--- a/arch/arm/mach-msm/clock-pcom.h
+++ b/arch/arm/mach-msm/clock-pcom.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+/*
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -120,21 +121,25 @@
 
 #define P_NR_CLKS               102
 
-struct clk_ops;
-extern struct clk_ops clk_ops_pcom;
+struct clk_pcom_desc {
+        unsigned id;
+        const char *name;
+        const char *con;
+        const char *dev;
+        unsigned long flags;
+};
 
-int pc_clk_reset(unsigned id, enum clk_reset_action action);
+struct pcom_clk_pdata {
+        struct clk_pcom_desc *lookup;
+        u32 num_lookups;
+};
 
 #define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) {        \
-        .con_id = clk_name, \
-        .dev_id = clk_dev, \
-        .clk = &(struct clk){ \
-                .id = P_##clk_id, \
-                .remote_id = P_##clk_id, \
-                .ops = &clk_ops_pcom, \
-                .flags = clk_flags, \
-                .dbg_name = #clk_id, \
-        }, \
+        .id = P_##clk_id,                                       \
+        .name = #clk_id,                                        \
+        .con = clk_name,                                        \
+        .dev = clk_dev,                                         \
+        .flags = clk_flags,                                     \
         }
 
 #endif
diff --git a/arch/arm/mach-msm/clock.c b/arch/arm/mach-msm/clock.c
index d9145dfc2a3b..35ea02b52483 100644
--- a/arch/arm/mach-msm/clock.c
+++ b/arch/arm/mach-msm/clock.c
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.c
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -14,171 +14,15 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/spinlock.h>
-#include <linux/pm_qos.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/string.h>
+#include <linux/clk-provider.h>
 #include <linux/module.h>
-#include <linux/clkdev.h>
 
 #include "clock.h"
 
-static DEFINE_MUTEX(clocks_mutex);
-static DEFINE_SPINLOCK(clocks_lock);
-static LIST_HEAD(clocks);
-
-/*
- * Standard clock functions defined in include/linux/clk.h
- */
-int clk_enable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        clk->count++;
-        if (clk->count == 1)
-                clk->ops->enable(clk->id);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&clocks_lock, flags);
-        BUG_ON(clk->count == 0);
-        clk->count--;
-        if (clk->count == 0)
-                clk->ops->disable(clk->id);
-        spin_unlock_irqrestore(&clocks_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
 int clk_reset(struct clk *clk, enum clk_reset_action action)
 {
-        return clk->ops->reset(clk->remote_id, action);
+        struct clk_hw *hw = __clk_get_hw(clk);
+        struct msm_clk *m = to_msm_clk(hw);
+        return m->reset(hw, action);
 }
 EXPORT_SYMBOL(clk_reset);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->ops->get_rate(clk->id);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        int ret;
-        if (clk->flags & CLKFLAG_MAX) {
-                ret = clk->ops->set_max_rate(clk->id, rate);
-                if (ret)
-                        return ret;
-        }
-        if (clk->flags & CLKFLAG_MIN) {
-                ret = clk->ops->set_min_rate(clk->id, rate);
-                if (ret)
-                        return ret;
-        }
-
-        if (clk->flags & CLKFLAG_MAX || clk->flags & CLKFLAG_MIN)
-                return ret;
-
-        return clk->ops->set_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->round_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_min_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->set_min_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_min_rate);
-
-int clk_set_max_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->ops->set_max_rate(clk->id, rate);
-}
-EXPORT_SYMBOL(clk_set_max_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-        return -ENOSYS;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-        return ERR_PTR(-ENOSYS);
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_flags(struct clk *clk, unsigned long flags)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        return clk->ops->set_flags(clk->id, flags);
-}
-EXPORT_SYMBOL(clk_set_flags);
-
-/* EBI1 is the only shared clock that several clients want to vote on as of
- * this commit. If this changes in the future, then it might be better to
- * make clk_min_rate handle the voting or make ebi1_clk_set_min_rate more
- * generic to support different clocks.
- */
-static struct clk *ebi1_clk;
-
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks)
-{
-        unsigned n;
-
-        mutex_lock(&clocks_mutex);
-        for (n = 0; n < num_clocks; n++) {
-                clkdev_add(&clock_tbl[n]);
-                list_add_tail(&clock_tbl[n].clk->list, &clocks);
-        }
-        mutex_unlock(&clocks_mutex);
-
-        ebi1_clk = clk_get(NULL, "ebi1_clk");
-        BUG_ON(ebi1_clk == NULL);
-
-}
-
-/* The bootloader and/or AMSS may have left various clocks enabled.
- * Disable any clocks that belong to us (CLKFLAG_AUTO_OFF) but have
- * not been explicitly enabled by a clk_enable() call.
- */
-static int __init clock_late_init(void)
-{
-        unsigned long flags;
-        struct clk *clk;
-        unsigned count = 0;
-
-        clock_debug_init();
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(clk, &clocks, list) {
-                clock_debug_add(clk);
-                if (clk->flags & CLKFLAG_AUTO_OFF) {
-                        spin_lock_irqsave(&clocks_lock, flags);
-                        if (!clk->count) {
-                                count++;
-                                clk->ops->auto_off(clk->id);
-                        }
-                        spin_unlock_irqrestore(&clocks_lock, flags);
-                }
-        }
-        mutex_unlock(&clocks_mutex);
-        pr_info("clock_late_init() disabled %d unused clocks\n", count);
-        return 0;
-}
-
-late_initcall(clock_late_init);
-
diff --git a/arch/arm/mach-msm/clock.h b/arch/arm/mach-msm/clock.h
index 2c007f606d29..42d29dd7aafc 100644
--- a/arch/arm/mach-msm/clock.h
+++ b/arch/arm/mach-msm/clock.h
@@ -1,7 +1,7 @@
 /* arch/arm/mach-msm/clock.h
  *
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2007-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -17,56 +17,27 @@
 #ifndef __ARCH_ARM_MACH_MSM_CLOCK_H
 #define __ARCH_ARM_MACH_MSM_CLOCK_H
 
-#include <linux/init.h>
-#include <linux/list.h>
+#include <linux/clk-provider.h>
 #include <mach/clk.h>
 
-#define CLKFLAG_INVERT                  0x00000001
-#define CLKFLAG_NOINVERT                0x00000002
-#define CLKFLAG_NONEST                  0x00000004
-#define CLKFLAG_NORESET                 0x00000008
-
 #define CLK_FIRST_AVAILABLE_FLAG        0x00000100
 #define CLKFLAG_AUTO_OFF                0x00000200
 #define CLKFLAG_MIN                     0x00000400
 #define CLKFLAG_MAX                     0x00000800
 
-struct clk_ops {
-        int (*enable)(unsigned id);
-        void (*disable)(unsigned id);
-        void (*auto_off)(unsigned id);
-        int (*reset)(unsigned id, enum clk_reset_action action);
-        int (*set_rate)(unsigned id, unsigned rate);
-        int (*set_min_rate)(unsigned id, unsigned rate);
-        int (*set_max_rate)(unsigned id, unsigned rate);
-        int (*set_flags)(unsigned id, unsigned flags);
-        unsigned (*get_rate)(unsigned id);
-        unsigned (*is_enabled)(unsigned id);
-        long (*round_rate)(unsigned id, unsigned rate);
-        bool (*is_local)(unsigned id);
-};
-
-struct clk {
-        uint32_t id;
-        uint32_t remote_id;
-        uint32_t count;
-        uint32_t flags;
-        struct clk_ops *ops;
-        const char *dbg_name;
-        struct list_head list;
-};
-
 #define OFF CLKFLAG_AUTO_OFF
 #define CLK_MIN CLKFLAG_MIN
 #define CLK_MAX CLKFLAG_MAX
 #define CLK_MINMAX (CLK_MIN | CLK_MAX)
 
-#ifdef CONFIG_DEBUG_FS
-int __init clock_debug_init(void);
-int __init clock_debug_add(struct clk *clock);
-#else
-static inline int __init clock_debug_init(void) { return 0; }
-static inline int __init clock_debug_add(struct clk *clock) { return 0; }
-#endif
+struct msm_clk {
+        int (*reset)(struct clk_hw *hw, enum clk_reset_action action);
+        struct clk_hw hw;
+};
+
+static inline struct msm_clk *to_msm_clk(struct clk_hw *hw)
+{
+        return container_of(hw, struct msm_clk, hw);
+}
 
 #endif
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index ce8215a269e5..421cf7751a80 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void);
 extern void msm_map_msm8960_io(void);
 extern void msm_map_qsd8x50_io(void);
 
-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                           unsigned int mtype, void *caller);
 
 extern struct smp_operations msm_smp_ops;
diff --git a/arch/arm/mach-msm/core.h b/arch/arm/mach-msm/core.h
deleted file mode 100644
index a9bab53dddf4..000000000000
--- a/arch/arm/mach-msm/core.h
+++ /dev/null
@@ -1,2 +0,0 @@
-extern struct smp_operations msm_smp_ops;
-extern void msm_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 1a0a2306b115..6d50fb964863 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -425,7 +425,7 @@ struct platform_device msm_device_mdp = {
         .resource = resources_mdp,
 };
 
-struct clk_lookup msm_clocks_7x01a[] = {
+static struct clk_pcom_desc msm_clocks_7x01a[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, 0),
@@ -469,4 +469,12 @@ struct clk_lookup msm_clocks_7x01a[] = {
         CLK_PCOM("vfe_mdc_clk", VFE_MDC_CLK,    NULL, OFF),
 };
 
-unsigned msm_num_clocks_7x01a = ARRAY_SIZE(msm_clocks_7x01a);
+static struct pcom_clk_pdata msm_clock_7x01a_pdata = {
+        .lookup = msm_clocks_7x01a,
+        .num_lookups = ARRAY_SIZE(msm_clocks_7x01a),
+};
+
+struct platform_device msm_clock_7x01a = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_7x01a_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 12f482c07740..d4db75acff56 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -28,8 +28,8 @@
 
 #include <asm/mach/flash.h>
 
+#include "clock.h"
 #include "clock-pcom.h"
-#include "clock-7x30.h"
 
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
@@ -161,7 +161,7 @@ struct platform_device msm_device_hsusb_host = {
         },
 };
 
-struct clk_lookup msm_clocks_7x30[] = {
+static struct clk_pcom_desc msm_clocks_7x30[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("adsp_clk",    ADSP_CLK,       NULL, 0),
         CLK_PCOM("cam_m_clk",   CAM_M_CLK,      NULL, 0),
@@ -177,7 +177,6 @@ struct clk_lookup msm_clocks_7x30[] = {
         CLK_PCOM("grp_2d_pclk", GRP_2D_P_CLK,   NULL, 0),
         CLK_PCOM("grp_clk",     GRP_3D_CLK,     NULL, 0),
         CLK_PCOM("grp_pclk",    GRP_3D_P_CLK,   NULL, 0),
-        CLK_7X30S("grp_src_clk", GRP_3D_SRC_CLK, GRP_3D_CLK,    NULL, 0),
         CLK_PCOM("hdmi_clk",    HDMI_CLK,       NULL, 0),
         CLK_PCOM("imem_clk",    IMEM_CLK,       NULL, OFF),
         CLK_PCOM("jpeg_clk",    JPEG_CLK,       NULL, OFF),
@@ -210,7 +209,6 @@ struct clk_lookup msm_clocks_7x30[] = {
         CLK_PCOM("sdac_clk",    SDAC_CLK,       NULL, OFF),
         CLK_PCOM("spi_clk",     SPI_CLK,        NULL, 0),
         CLK_PCOM("spi_pclk",    SPI_P_CLK,      NULL, 0),
-        CLK_7X30S("tv_src_clk", TV_CLK,         TV_ENC_CLK,     NULL, 0),
         CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
         CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
         CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
@@ -237,5 +235,12 @@ struct clk_lookup msm_clocks_7x30[] = {
         CLK_PCOM("csi_vfe_clk", CSI0_VFE_CLK,   NULL, 0),
 };
 
-unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
+static struct pcom_clk_pdata msm_clock_7x30_pdata = {
+        .lookup = msm_clocks_7x30,
+        .num_lookups = ARRAY_SIZE(msm_clocks_7x30),
+};
 
+struct platform_device msm_clock_7x30 = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_7x30_pdata,
+};
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2e1b3ec9dfc7..f5518112284b 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -28,6 +28,7 @@
 #include <asm/mach/flash.h>
 
 #include <linux/platform_data/mmc-msm_sdcc.h>
+#include "clock.h"
 #include "clock-pcom.h"
 
 static struct resource msm_gpio_resources[] = {
@@ -322,7 +323,7 @@ int __init msm_add_sdcc(unsigned int controller,
         return platform_device_register(pdev);
 }
 
-struct clk_lookup msm_clocks_8x50[] = {
+static struct clk_pcom_desc msm_clocks_8x50[] = {
         CLK_PCOM("adm_clk",     ADM_CLK,        NULL, 0),
         CLK_PCOM("ce_clk",      CE_CLK,         NULL, 0),
         CLK_PCOM("ebi1_clk",    EBI1_CLK,       NULL, CLK_MIN),
@@ -376,5 +377,12 @@ struct clk_lookup msm_clocks_8x50[] = {
         CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
 };
 
-unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
+static struct pcom_clk_pdata msm_clock_8x50_pdata = {
+        .lookup = msm_clocks_8x50,
+        .num_lookups = ARRAY_SIZE(msm_clocks_8x50),
+};
 
+struct platform_device msm_clock_8x50 = {
+        .name = "msm-clock-pcom",
+        .dev.platform_data = &msm_clock_8x50_pdata,
+};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index da902cf51161..dccefad9f9b9 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -16,10 +16,6 @@
 #ifndef __ARCH_ARM_MACH_MSM_DEVICES_H
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
 
-#include <linux/clkdev.h>
-
-#include "clock.h"
-
 extern struct platform_device msm_device_gpio_7201;
 extern struct platform_device msm_device_gpio_7x30;
 extern struct platform_device msm_device_gpio_8x50;
@@ -50,13 +46,8 @@ extern struct platform_device msm_device_mddi0;
 extern struct platform_device msm_device_mddi1;
 extern struct platform_device msm_device_mdp;
 
-extern struct clk_lookup msm_clocks_7x01a[];
-extern unsigned msm_num_clocks_7x01a;
-
-extern struct clk_lookup msm_clocks_7x30[];
-extern unsigned msm_num_clocks_7x30;
-
-extern struct clk_lookup msm_clocks_8x50[];
-extern unsigned msm_num_clocks_8x50;
+extern struct platform_device msm_clock_7x01a;
+extern struct platform_device msm_clock_7x30;
+extern struct platform_device msm_clock_8x50;
 
 #endif
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index b279fd8a31b1..f8f6adfa07c6 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -284,6 +284,7 @@ static int __init msm_init_datamover(void)
         clk = clk_get(NULL, "adm_clk");
         if (IS_ERR(clk))
                 return PTR_ERR(clk);
+        clk_prepare(clk);
         msm_dmov_clk = clk;
         ret = request_irq(INT_ADM_AARM, msm_datamover_irq_handler, 0, "msmdatamover", NULL);
         if (ret)
@@ -291,6 +292,4 @@ static int __init msm_init_datamover(void)
         disable_irq(INT_ADM_AARM);
         return 0;
 }
-
-arch_initcall(msm_init_datamover);
-
+module_init(msm_init_datamover);
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c
deleted file mode 100644
index 273396d2b127..000000000000
--- a/arch/arm/mach-msm/gpiomux-v2.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#include <linux/io.h>
-#include <mach/msm_iomap.h>
-#include "gpiomux.h"
-
-void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
-{
-        writel(val & ~GPIOMUX_CTL_MASK,
-               MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
-}
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h
deleted file mode 100644
index 3bf10e7f0381..000000000000
--- a/arch/arm/mach-msm/gpiomux-v2.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
-#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
-
-#define GPIOMUX_NGPIOS 173
-
-typedef u16 gpiomux_config_t;
-
-enum {
-        GPIOMUX_DRV_2MA  = 0UL << 6,
-        GPIOMUX_DRV_4MA  = 1UL << 6,
-        GPIOMUX_DRV_6MA  = 2UL << 6,
-        GPIOMUX_DRV_8MA  = 3UL << 6,
-        GPIOMUX_DRV_10MA = 4UL << 6,
-        GPIOMUX_DRV_12MA = 5UL << 6,
-        GPIOMUX_DRV_14MA = 6UL << 6,
-        GPIOMUX_DRV_16MA = 7UL << 6,
-};
-
-enum {
-        GPIOMUX_FUNC_GPIO = 0UL  << 2,
-        GPIOMUX_FUNC_1    = 1UL  << 2,
-        GPIOMUX_FUNC_2    = 2UL  << 2,
-        GPIOMUX_FUNC_3    = 3UL  << 2,
-        GPIOMUX_FUNC_4    = 4UL  << 2,
-        GPIOMUX_FUNC_5    = 5UL  << 2,
-        GPIOMUX_FUNC_6    = 6UL  << 2,
-        GPIOMUX_FUNC_7    = 7UL  << 2,
-        GPIOMUX_FUNC_8    = 8UL  << 2,
-        GPIOMUX_FUNC_9    = 9UL  << 2,
-        GPIOMUX_FUNC_A    = 10UL << 2,
-        GPIOMUX_FUNC_B    = 11UL << 2,
-        GPIOMUX_FUNC_C    = 12UL << 2,
-        GPIOMUX_FUNC_D    = 13UL << 2,
-        GPIOMUX_FUNC_E    = 14UL << 2,
-        GPIOMUX_FUNC_F    = 15UL << 2,
-};
-
-enum {
-        GPIOMUX_PULL_NONE   = 0UL,
-        GPIOMUX_PULL_DOWN   = 1UL,
-        GPIOMUX_PULL_KEEPER = 2UL,
-        GPIOMUX_PULL_UP     = 3UL,
-};
-
-#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
index 53af21abd155..2b8e2d217082 100644
--- a/arch/arm/mach-msm/gpiomux.c
+++ b/arch/arm/mach-msm/gpiomux.c
@@ -17,9 +17,24 @@
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include "gpiomux.h"
+#include "proc_comm.h"
 
 static DEFINE_SPINLOCK(gpiomux_lock);
 
+static void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
+{
+        unsigned tlmm_config  = (val & ~GPIOMUX_CTL_MASK) |
+                                ((gpio & 0x3ff) << 4);
+        unsigned tlmm_disable = 0;
+        int rc;
+
+        rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
+                           &tlmm_config, &tlmm_disable);
+        if (rc)
+                pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
+                       __func__, rc, tlmm_config, tlmm_disable);
+}
+
 int msm_gpiomux_write(unsigned gpio,
                       gpiomux_config_t active,
                       gpiomux_config_t suspended)
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
index 00459f6ee13c..8e82f41a8923 100644
--- a/arch/arm/mach-msm/gpiomux.h
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -20,12 +20,7 @@
 #include <linux/bitops.h>
 #include <linux/errno.h>
 #include <mach/msm_gpiomux.h>
-
-#if defined(CONFIG_MSM_V2_TLMM)
-#include "gpiomux-v2.h"
-#else
 #include "gpiomux-v1.h"
-#endif
 
 /**
  * struct msm_gpiomux_config: gpiomux settings for one gpio line.
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 8cebedb11233..c34e246a3e07 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -20,16 +20,11 @@
 #include <linux/types.h>
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
-/* platform device data structures */
-
-struct clk_lookup;
-
 /* common init routines for use by arch/arm/mach-msm/board-*.c */
 
 void __init msm_add_devices(void);
 void __init msm_init_irq(void);
 void __init msm_init_gpio(void);
-void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
 int __init msm_add_sdcc(unsigned int controller,
                         struct msm_mmc_platform_data *plat,
                         unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/clk.h b/arch/arm/mach-msm/include/mach/clk.h
index e8d38428d813..fd4f4a7a83b3 100644
--- a/arch/arm/mach-msm/include/mach/clk.h
+++ b/arch/arm/mach-msm/include/mach/clk.h
@@ -25,16 +25,7 @@ enum clk_reset_action {
 
 struct clk;
 
-/* Rate is minimum clock rate in Hz */
-int clk_set_min_rate(struct clk *clk, unsigned long rate);
-
-/* Rate is maximum clock rate in Hz */
-int clk_set_max_rate(struct clk *clk, unsigned long rate);
-
 /* Assert/Deassert reset to a hardware block associated with a clock */
 int clk_reset(struct clk *clk, enum clk_reset_action action);
 
-/* Set clock-specific configuration parameters */
-int clk_set_flags(struct clk *clk, unsigned long flags);
-
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 9819a556acae..7bca8d7108d6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -32,13 +32,6 @@
  *
  */
 
-
-#define MSM8960_QGIC_DIST_PHYS  0x02000000
-#define MSM8960_QGIC_DIST_SIZE  SZ_4K
-
-#define MSM8960_QGIC_CPU_PHYS   0x02002000
-#define MSM8960_QGIC_CPU_SIZE   SZ_4K
-
 #define MSM8960_TMR_PHYS        0x0200A000
 #define MSM8960_TMR_SIZE        SZ_4K
 
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 199372e62def..75a7b62c1c74 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -35,12 +35,6 @@
  *
  */
 
-#define MSM8X60_QGIC_DIST_PHYS  0x02080000
-#define MSM8X60_QGIC_DIST_SIZE  SZ_4K
-
-#define MSM8X60_QGIC_CPU_PHYS   0x02081000
-#define MSM8X60_QGIC_CPU_SIZE   SZ_4K
-
 #define MSM_TLMM_BASE           IOMEM(0xF0004000)
 #define MSM_TLMM_PHYS           0x00800000
 #define MSM_TLMM_SIZE           SZ_16K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 2ab7cf0919b3..c56e81ffdcde 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -62,8 +62,6 @@
 
 /* Virtual addresses shared across all MSM targets. */
 #define MSM_CSR_BASE            IOMEM(0xE0001000)
-#define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
-#define MSM_QGIC_CPU_BASE       IOMEM(0xF0001000)
 #define MSM_TMR_BASE            IOMEM(0xF0200000)
 #define MSM_TMR0_BASE           IOMEM(0xF0201000)
 #define MSM_GPIO1_BASE          IOMEM(0xE0003000)
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 123ef9cbce1b..3dc04ccaf59f 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -107,8 +107,6 @@ void __init msm_map_qsd8x50_io(void)
 
 #ifdef CONFIG_ARCH_MSM8X60
 static struct map_desc msm8x60_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(QGIC_DIST, MSM8X60),
-        MSM_CHIP_DEVICE(QGIC_CPU, MSM8X60),
         MSM_CHIP_DEVICE(TMR, MSM8X60),
         MSM_CHIP_DEVICE(TMR0, MSM8X60),
 #ifdef CONFIG_DEBUG_MSM8660_UART
@@ -124,8 +122,6 @@ void __init msm_map_msm8x60_io(void)
 
 #ifdef CONFIG_ARCH_MSM8960
 static struct map_desc msm8960_io_desc[] __initdata = {
-        MSM_CHIP_DEVICE(QGIC_DIST, MSM8960),
-        MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
         MSM_CHIP_DEVICE(TMR, MSM8960),
         MSM_CHIP_DEVICE(TMR0, MSM8960),
 #ifdef CONFIG_DEBUG_MSM8960_UART
@@ -172,7 +168,7 @@ void __init msm_map_msm7x30_io(void)
 }
 #endif /* CONFIG_ARCH_MSM7X30 */
 
-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                    unsigned int mtype, void *caller)
 {
         if (mtype == MT_DEVICE) {
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bcacd9d5..9eb63d724602 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,12 +10,11 @@ config ARCH_MVEBU
         select PLAT_ORION
         select SPARSE_IRQ
         select CLKDEV_LOOKUP
-        select MVEBU_CLK_CORE
-        select MVEBU_CLK_CPU
-        select MVEBU_CLK_GATING
         select MVEBU_MBUS
         select ZONE_DMA if ARM_LPAE
         select ARCH_REQUIRE_GPIOLIB
+        select MIGHT_HAVE_PCI
+        select PCI_QUIRKS if PCI
 
 if ARCH_MVEBU
 
@@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP
 
 config MACH_ARMADA_370
         bool "Marvell Armada 370 boards"
+        select ARMADA_370_CLK
         select MACH_ARMADA_370_XP
         select PINCTRL_ARMADA_370
         help
@@ -38,6 +38,7 @@ config MACH_ARMADA_370
 
 config MACH_ARMADA_XP
         bool "Marvell Armada XP boards"
+        select ARMADA_XP_CLK
         select MACH_ARMADA_370_XP
         select PINCTRL_ARMADA_XP
         help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 1c48890bb72b..97cbb8021919 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,13 +14,13 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
 #include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
 #include <linux/dma-mapping.h>
 #include <linux/mbus.h>
-#include <linux/irqchip.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -29,45 +29,49 @@
 #include "common.h"
 #include "coherency.h"
 
-static struct map_desc armada_370_xp_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
-                .length         = ARMADA_370_XP_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-void __init armada_370_xp_map_io(void)
+static void __init armada_370_xp_map_io(void)
 {
-        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+        debug_ll_io_init();
 }
 
-void __init armada_370_xp_timer_and_clk_init(void)
-{
-        mvebu_clocks_init();
-        armada_370_xp_timer_init();
-}
+/*
+ * This initialization will be replaced by a DT-based
+ * initialization once the mvebu-mbus driver gains DT support.
+ */
 
-void __init armada_370_xp_init_early(void)
+#define ARMADA_370_XP_MBUS_WINS_OFFS   0x20000
+#define ARMADA_370_XP_MBUS_WINS_SIZE   0x100
+#define ARMADA_370_XP_SDRAM_WINS_OFFS  0x20180
+#define ARMADA_370_XP_SDRAM_WINS_SIZE  0x20
+
+static void __init armada_370_xp_mbus_init(void)
 {
         char *mbus_soc_name;
+        struct device_node *dn;
+        const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
+        const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
 
-        /*
-         * This initialization will be replaced by a DT-based
-         * initialization once the mvebu-mbus driver gains DT support.
-         */
         if (of_machine_is_compatible("marvell,armada370"))
                 mbus_soc_name = "marvell,armada370-mbus";
         else
                 mbus_soc_name = "marvell,armadaxp-mbus";
 
+        dn = of_find_node_by_name(NULL, "internal-regs");
+        BUG_ON(!dn);
+
         mvebu_mbus_init(mbus_soc_name,
-                        ARMADA_370_XP_MBUS_WINS_BASE,
+                        of_translate_address(dn, &mbus_wins_offs),
                         ARMADA_370_XP_MBUS_WINS_SIZE,
-                        ARMADA_370_XP_SDRAM_WINS_BASE,
+                        of_translate_address(dn, &sdram_wins_offs),
                         ARMADA_370_XP_SDRAM_WINS_SIZE);
+}
 
+static void __init armada_370_xp_timer_and_clk_init(void)
+{
+        of_clk_init(NULL);
+        armada_370_xp_timer_init();
+        coherency_init();
+        armada_370_xp_mbus_init();
 #ifdef CONFIG_CACHE_L2X0
         l2x0_of_init(0, ~0UL);
 #endif
@@ -76,7 +80,6 @@ void __init armada_370_xp_init_early(void)
 static void __init armada_370_xp_dt_init(void)
 {
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        coherency_init();
 }
 
 static const char * const armada_370_xp_dt_compat[] = {
@@ -88,8 +91,6 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)")
         .smp            = smp_ops(armada_xp_smp_ops),
         .init_machine   = armada_370_xp_dt_init,
         .map_io         = armada_370_xp_map_io,
-        .init_early     = armada_370_xp_init_early,
-        .init_irq       = irqchip_init,
         .init_time      = armada_370_xp_timer_and_clk_init,
         .restart        = mvebu_restart,
         .dt_compat      = armada_370_xp_dt_compat,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 2070e1b4f342..c612b2c4ed6c 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -15,16 +15,6 @@
 #ifndef __MACH_ARMADA_370_XP_H
 #define __MACH_ARMADA_370_XP_H
 
-#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfec00000)
-#define ARMADA_370_XP_REGS_SIZE         SZ_1M
-
-/* These defines can go away once mvebu-mbus has a DT binding */
-#define ARMADA_370_XP_MBUS_WINS_BASE    (ARMADA_370_XP_REGS_PHYS_BASE + 0x20000)
-#define ARMADA_370_XP_MBUS_WINS_SIZE    0x100
-#define ARMADA_370_XP_SDRAM_WINS_BASE   (ARMADA_370_XP_REGS_PHYS_BASE + 0x20180)
-#define ARMADA_370_XP_SDRAM_WINS_SIZE   0x20
-
 #ifdef CONFIG_SMP
 #include <linux/cpumask.h>
 
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 8278960066c3..be117591f7f2 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -25,16 +25,11 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <asm/smp_plat.h>
+#include <asm/cacheflush.h>
 #include "armada-370-xp.h"
 
-/*
- * Some functions in this file are called very early during SMP
- * initialization. At that time the device tree framework is not yet
- * ready, and it is not possible to get the register address to
- * ioremap it. That's why the pointer below is given with an initial
- * value matching its virtual mapping
- */
-static void __iomem *coherency_base = ARMADA_370_XP_REGS_VIRT_BASE + 0x20200;
+unsigned long __cpuinitdata coherency_phys_base;
+static void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 
 /* Coherency fabric registers */
@@ -47,18 +42,6 @@ static struct of_device_id of_coherency_table[] = {
         { /* end of list */ },
 };
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void)
-{
-        int reg, cnt;
-
-        reg = readl(coherency_base + COHERENCY_FABRIC_CFG_OFFSET);
-        cnt = (reg & 0xF) + 1;
-
-        return cnt;
-}
-#endif
-
 /* Function defined in coherency_ll.S */
 int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
 
@@ -143,13 +126,31 @@ int __init coherency_init(void)
 
         np = of_find_matching_node(NULL, of_coherency_table);
         if (np) {
+                struct resource res;
                 pr_info("Initializing Coherency fabric\n");
+                of_address_to_resource(np, 0, &res);
+                coherency_phys_base = res.start;
+                /*
+                 * Ensure secondary CPUs will see the updated value,
+                 * which they read before they join the coherency
+                 * fabric, and therefore before they are coherent with
+                 * the boot CPU cache.
+                 */
+                sync_cache_w(&coherency_phys_base);
                 coherency_base = of_iomap(np, 0);
                 coherency_cpu_base = of_iomap(np, 1);
                 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-                bus_register_notifier(&platform_bus_type,
-                                        &mvebu_hwcc_platform_nb);
         }
 
         return 0;
 }
+
+static int __init coherency_late_init(void)
+{
+        if (of_find_matching_node(NULL, of_coherency_table))
+                bus_register_notifier(&platform_bus_type,
+                                      &mvebu_hwcc_platform_nb);
+        return 0;
+}
+
+postcore_initcall(coherency_late_init);
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 2f428137f6fe..df33ad8a6c08 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -14,10 +14,6 @@
 #ifndef __MACH_370_XP_COHERENCY_H
 #define __MACH_370_XP_COHERENCY_H
 
-#ifdef CONFIG_SMP
-int coherency_get_cpu_count(void);
-#endif
-
 int set_cpu_coherent(int cpu_id, int smp_group_id);
 int coherency_init(void);
 
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index aa27bc2ffb60..98defd5e92cd 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -15,6 +15,8 @@
 #ifndef __ARCH_MVEBU_COMMON_H
 #define __ARCH_MVEBU_COMMON_H
 
+#define ARMADA_XP_MAX_CPUS 4
+
 void mvebu_restart(char mode, const char *cmd);
 
 void armada_370_xp_init_irq(void);
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index a06e0ede8c08..7147300c8af2 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -21,12 +21,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-/*
- * At this stage the secondary CPUs don't have acces yet to the MMU, so
- * we have to provide physical addresses
- */
-#define ARMADA_XP_CFB_BASE           0xD0020200
-
         __CPUINIT
 
 /*
@@ -35,15 +29,21 @@
  * startup
  */
 ENTRY(armada_xp_secondary_startup)
+        /* Get coherency fabric base physical address */
+        adr     r0, 1f
+        ldr     r1, [r0]
+        ldr     r0, [r0, r1]
 
         /* Read CPU id */
         mrc     p15, 0, r1, c0, c0, 5
         and     r1, r1, #0xF
 
         /* Add CPU to coherency fabric */
-        ldr     r0, =ARMADA_XP_CFB_BASE
-
         bl      ll_set_cpu_coherent
         b       secondary_startup
 
 ENDPROC(armada_xp_secondary_startup)
+
+        .align 2
+1:
+        .long   coherency_phys_base - .
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 875ea748391c..93f2f3ab45f1 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -88,8 +88,16 @@ static int __cpuinit armada_xp_boot_secondary(unsigned int cpu,
 
 static void __init armada_xp_smp_init_cpus(void)
 {
+        struct device_node *np;
         unsigned int i, ncores;
-        ncores = coherency_get_cpu_count();
+
+        np = of_find_node_by_name(NULL, "cpus");
+        if (!np)
+                panic("No 'cpus' node found\n");
+
+        ncores = of_get_child_count(np);
+        if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
+                panic("Invalid number of CPUs in DT\n");
 
         /* Limit possible CPUs to defconfig */
         if (ncores > nr_cpu_ids) {
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4dc2fbba0ecd..616fe0210da1 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -3,7 +3,6 @@ config SOC_IMX23
         select ARM_AMBA
         select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
-        select HAVE_PWM
         select PINCTRL_IMX23
 
 config SOC_IMX28
@@ -12,7 +11,6 @@ config SOC_IMX28
         select ARM_CPU_SUSPEND if PM
         select CPU_ARM926T
         select HAVE_CAN_FLEXCAN if CAN
-        select HAVE_PWM
         select PINCTRL_IMX28
 
 config ARCH_MXS
@@ -25,6 +23,7 @@ config ARCH_MXS
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK_PREPARE
         select PINCTRL
+        select SOC_BUS
         select SOC_IMX23
         select SOC_IMX28
         select STMP_DEVICE
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 5b62b6489d4b..7fa611c1b287 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -19,13 +19,13 @@
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/irqchip/mxs.h>
 #include <linux/micrel_phy.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
+#include <linux/sys_soc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -39,12 +39,28 @@
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
 
+#define HW_DIGCTL_CHIPID        0x310
+#define HW_DIGCTL_CHIPID_MASK   (0xffff << 16)
+#define HW_DIGCTL_REV_MASK      0xff
+#define HW_DIGCTL_CHIPID_MX23   (0x3780 << 16)
+#define HW_DIGCTL_CHIPID_MX28   (0x2800 << 16)
+
+#define MXS_CHIP_REVISION_1_0   0x10
+#define MXS_CHIP_REVISION_1_1   0x11
+#define MXS_CHIP_REVISION_1_2   0x12
+#define MXS_CHIP_REVISION_1_3   0x13
+#define MXS_CHIP_REVISION_1_4   0x14
+#define MXS_CHIP_REV_UNKNOWN    0xff
+
 #define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
 
 #define MXS_SET_ADDR            0x4
 #define MXS_CLR_ADDR            0x8
 #define MXS_TOG_ADDR            0xc
 
+static u32 chipid;
+static u32 socid;
+
 static inline void __mxs_setl(u32 mask, void __iomem *reg)
 {
         __raw_writel(mask, reg + MXS_SET_ADDR);
@@ -352,29 +368,123 @@ static void __init tx28_post_init(void)
         pinctrl_put(pctl);
 }
 
-static void __init cfa10049_init(void)
+static void __init crystalfontz_init(void)
 {
         update_fec_mac_prop(OUI_CRYSTALFONTZ);
 }
 
-static void __init cfa10037_init(void)
+static const char __init *mxs_get_soc_id(void)
 {
-        update_fec_mac_prop(OUI_CRYSTALFONTZ);
+        struct device_node *np;
+        void __iomem *digctl_base;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
+        digctl_base = of_iomap(np, 0);
+        WARN_ON(!digctl_base);
+
+        chipid = readl(digctl_base + HW_DIGCTL_CHIPID);
+        socid = chipid & HW_DIGCTL_CHIPID_MASK;
+
+        iounmap(digctl_base);
+        of_node_put(np);
+
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                return "i.MX23";
+        case HW_DIGCTL_CHIPID_MX28:
+                return "i.MX28";
+        default:
+                return "Unknown";
+        }
+}
+
+static u32 __init mxs_get_cpu_rev(void)
+{
+        u32 rev = chipid & HW_DIGCTL_REV_MASK;
+
+        switch (socid) {
+        case HW_DIGCTL_CHIPID_MX23:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_0;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x2:
+                        return MXS_CHIP_REVISION_1_2;
+                case 0x3:
+                        return MXS_CHIP_REVISION_1_3;
+                case 0x4:
+                        return MXS_CHIP_REVISION_1_4;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        case HW_DIGCTL_CHIPID_MX28:
+                switch (rev) {
+                case 0x0:
+                        return MXS_CHIP_REVISION_1_1;
+                case 0x1:
+                        return MXS_CHIP_REVISION_1_2;
+                default:
+                        return MXS_CHIP_REV_UNKNOWN;
+                }
+        default:
+                return MXS_CHIP_REV_UNKNOWN;
+        }
+}
+
+static const char __init *mxs_get_revision(void)
+{
+        u32 rev = mxs_get_cpu_rev();
+
+        if (rev != MXS_CHIP_REV_UNKNOWN)
+                return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf,
+                                rev & 0xf);
+        else
+                return kasprintf(GFP_KERNEL, "%s", "Unknown");
 }
 
 static void __init mxs_machine_init(void)
 {
+        struct device_node *root;
+        struct device *parent;
+        struct soc_device *soc_dev;
+        struct soc_device_attribute *soc_dev_attr;
+        int ret;
+
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return;
+
+        root = of_find_node_by_path("/");
+        ret = of_property_read_string(root, "model", &soc_dev_attr->machine);
+        if (ret)
+                return;
+
+        soc_dev_attr->family = "Freescale MXS Family";
+        soc_dev_attr->soc_id = mxs_get_soc_id();
+        soc_dev_attr->revision = mxs_get_revision();
+
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr);
+                return;
+        }
+
+        parent = soc_device_to_device(soc_dev);
+
         if (of_machine_is_compatible("fsl,imx28-evk"))
                 imx28_evk_init();
         else if (of_machine_is_compatible("bluegiga,apx4devkit"))
                 apx4devkit_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10037"))
-                cfa10037_init();
-        else if (of_machine_is_compatible("crystalfontz,cfa10049"))
-                cfa10049_init();
+        else if (of_machine_is_compatible("crystalfontz,cfa10037") ||
+                 of_machine_is_compatible("crystalfontz,cfa10049") ||
+                 of_machine_is_compatible("crystalfontz,cfa10055") ||
+                 of_machine_is_compatible("crystalfontz,cfa10057"))
+                crystalfontz_init();
 
         of_platform_populate(NULL, of_default_bus_match_table,
-                             mxs_auxdata_lookup, NULL);
+                             mxs_auxdata_lookup, parent);
 
         if (of_machine_is_compatible("karo,tx28"))
                 tx28_post_init();
@@ -434,8 +544,6 @@ static const char *mxs_dt_compat[] __initdata = {
 };
 
 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
-        .map_io         = debug_ll_io_init,
-        .init_irq       = irqchip_init,
         .handle_irq     = icoll_handle_irq,
         .init_time      = mxs_timer_init,
         .init_machine   = mxs_machine_init,
diff --git a/arch/arm/mach-mxs/pm.h b/arch/arm/mach-mxs/pm.h
index f57e7cdece2e..09d77b00a96b 100644
--- a/arch/arm/mach-mxs/pm.h
+++ b/arch/arm/mach-mxs/pm.h
@@ -9,6 +9,10 @@
 #ifndef __ARCH_MXS_PM_H
 #define __ARCH_MXS_PM_H
 
+#ifdef CONFIG_PM
 void mxs_pm_init(void);
+#else
+#define mxs_pm_init NULL
+#endif
 
 #endif
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 9b9d105f194c..5981c3db9b41 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,6 +6,7 @@ config ARCH_NOMADIK
         select ARM_VIC
         select CLKSRC_NOMADIK_MTU
         select CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        select CLKSRC_OF
         select COMMON_CLK
         select CPU_ARM926T
         select GENERIC_CLOCKEVENTS
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 59f6ff5c9bae..2df209ed1a07 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -25,11 +25,8 @@
 #include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
-#include <linux/irqchip.h>
 #include <linux/platform_data/clk-nomadik.h>
-#include <linux/platform_data/pinctrl-nomadik.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <linux/clocksource.h>
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 #include <linux/of_address.h>
@@ -91,48 +88,6 @@
 #define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
 #define NOMADIK_UART1_VBASE     0xF01FB000
 
-static unsigned long out_low[] = { PIN_OUTPUT_LOW };
-static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
-static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
-static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
-
-static struct pinctrl_map __initdata nhk8815_pinmap[] = {
-        PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
-        /* Hog in MMC/SD card mux */
-        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
-        /* MCCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
-        /* MCCMD */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
-        /* MCCMDDIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
-        /* MCDAT3-0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
-        /* MCDAT0DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
-        /* MCDAT31DIR */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
-        /* MCMSFBCLK */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
-        /* CD input GPIO */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
-        /* CD bias drive */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
-        /* I2C0 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO62_D3", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO63_D2", in_pullup),
-        /* I2C1 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO53_L4", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO54_L3", in_pullup),
-        /* I2C2 */
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO73_C21", in_pullup),
-        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO74_C20", in_pullup),
-};
-
 /* This is needed for LL-debug/earlyprintk/debug-macro.S */
 static struct map_desc cpu8815_io_desc[] __initdata = {
         {
@@ -172,7 +127,7 @@ static void __init cpu8815_timer_init_of(void)
         /* We need this to be up now */
         nomadik_clk_init();
 
-        mtu = of_find_node_by_path("/mtu0");
+        mtu = of_find_node_by_path("/mtu@101e2000");
         if (!mtu)
                 return;
         base = of_iomap(mtu, 0);
@@ -188,7 +143,7 @@ static void __init cpu8815_timer_init_of(void)
         src_cr |= SRC_CR_INIT_VAL;
         writel(src_cr, base);
 
-        nmdk_timer_init(base, irq);
+        clocksource_of_init();
 }
 
 static struct fsmc_nand_timings cpu8815_nand_timings = {
@@ -280,28 +235,10 @@ device_initcall(cpu8815_mmcsd_init);
 
 /* These are mostly to get the right device names for the clock lookups */
 static struct of_dev_auxdata cpu8815_auxdata_lookup[] __initdata = {
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO0_BASE,
-                "gpio.0", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO1_BASE,
-                "gpio.1", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO2_BASE,
-                "gpio.2", NULL),
-        OF_DEV_AUXDATA("st,nomadik-gpio", NOMADIK_GPIO3_BASE,
-                "gpio.3", NULL),
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl-stn8815", 0,
-                "pinctrl-stn8815", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART0_BASE,
-                "uart0", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_UART1_BASE,
-                "uart1", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RNG_BASE,
-                "rng", NULL),
-        OF_DEV_AUXDATA("arm,primecell", NOMADIK_RTC_BASE,
-                "rtc-pl031", NULL),
         OF_DEV_AUXDATA("stericsson,fsmc-nand", NOMADIK_FSMC_BASE,
-                "fsmc-nand", &cpu8815_nand_data),
+                NULL, &cpu8815_nand_data),
         OF_DEV_AUXDATA("arm,primecell", NOMADIK_SDI_BASE,
-                "mmci", &mmcsd_plat_data),
+                NULL, &mmcsd_plat_data),
         { /* sentinel */ },
 };
 
@@ -311,7 +248,6 @@ static void __init cpu8815_init_of(void)
         /* At full speed latency must be >=2, so 0x249 in low bits */
         l2x0_of_init(0x00730249, 0xfe000fff);
 #endif
-        pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
         of_platform_populate(NULL, of_default_bus_match_table,
                         cpu8815_auxdata_lookup, NULL);
 }
@@ -323,7 +259,6 @@ static const char * cpu8815_board_compat[] = {
 
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
         .map_io         = cpu8815_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = cpu8815_timer_init_of,
         .init_machine   = cpu8815_init_of,
         .restart        = cpu8815_restart,
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig
new file mode 100644
index 000000000000..59d8f0a70919
--- /dev/null
+++ b/arch/arm/mach-nspire/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_NSPIRE
+        bool "TI-NSPIRE based"
+        depends on ARCH_MULTI_V4_V5
+        depends on MMU
+        select CPU_ARM926T
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_IRQ_CHIP
+        select SPARSE_IRQ
+        select ARM_AMBA
+        select ARM_VIC
+        select ARM_TIMER_SP804
+        select USE_OF
+        select CLKSRC_OF
+        help
+          This enables support for systems using the TI-NSPIRE CPU
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
new file mode 100644
index 000000000000..1bec256eba07
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += nspire.o
+obj-y                           += clcd.o
diff --git a/arch/arm/mach-nspire/Makefile.boot b/arch/arm/mach-nspire/Makefile.boot
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-nspire/Makefile.boot
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
new file mode 100644
index 000000000000..abea12617b17
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.c
@@ -0,0 +1,119 @@
+/*
+ *      linux/arch/arm/mach-nspire/clcd.c
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/dma-mapping.h>
+
+static struct clcd_panel nspire_cx_lcd_panel = {
+        .mode           = {
+                .name           = "Color LCD",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .pixclock       = 1,
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+                .right_margin   = 50,
+                .left_margin    = 38,
+                .lower_margin   = 3,
+                .upper_margin   = 17,
+        },
+        .width          = 65, /* ~6.50 cm */
+        .height         = 49, /* ~4.87 cm */
+        .tim2           = TIM2_IPC,
+        .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
+        .bpp            = 16,
+        .caps           = CLCD_CAP_565,
+};
+
+static struct clcd_panel nspire_classic_lcd_panel = {
+        .mode           = {
+                .name           = "Grayscale LCD",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .pixclock       = 1,
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+                .right_margin   = 6,
+                .left_margin    = 6,
+        },
+        .width          = 71, /* 7.11cm */
+        .height         = 53, /* 5.33cm */
+        .tim2           = 0x80007d0,
+        .cntl           = CNTL_LCDMONO8,
+        .bpp            = 8,
+        .grayscale      = 1,
+        .caps           = CLCD_CAP_5551,
+};
+
+int nspire_clcd_setup(struct clcd_fb *fb)
+{
+        struct clcd_panel *panel;
+        size_t panel_size;
+        const char *type;
+        dma_addr_t dma;
+        int err;
+
+        BUG_ON(!fb->dev->dev.of_node);
+
+        err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
+        if (err) {
+                pr_err("CLCD: Could not find lcd-type property\n");
+                return err;
+        }
+
+        if (!strcmp(type, "cx")) {
+                panel = &nspire_cx_lcd_panel;
+        } else if (!strcmp(type, "classic")) {
+                panel = &nspire_classic_lcd_panel;
+        } else {
+                pr_err("CLCD: Unknown lcd-type %s\n", type);
+                return -EINVAL;
+        }
+
+        panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
+        panel_size = ALIGN(panel_size, PAGE_SIZE);
+
+        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+                panel_size, &dma, GFP_KERNEL);
+
+        if (!fb->fb.screen_base) {
+                pr_err("CLCD: unable to map framebuffer\n");
+                return -ENOMEM;
+        }
+
+        fb->fb.fix.smem_start = dma;
+        fb->fb.fix.smem_len = panel_size;
+        fb->panel = panel;
+
+        return 0;
+}
+
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+        return dma_mmap_writecombine(&fb->dev->dev, vma,
+                fb->fb.screen_base, fb->fb.fix.smem_start,
+                fb->fb.fix.smem_len);
+}
+
+void nspire_clcd_remove(struct clcd_fb *fb)
+{
+        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+                fb->fb.screen_base, fb->fb.fix.smem_start);
+}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
new file mode 100644
index 000000000000..8c33d2c18371
--- /dev/null
+++ b/arch/arm/mach-nspire/clcd.h
@@ -0,0 +1,14 @@
+/*
+ *      linux/arch/arm/mach-nspire/clcd.h
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+int nspire_clcd_setup(struct clcd_fb *fb);
+int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
+void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/mmio.h b/arch/arm/mach-nspire/mmio.h
new file mode 100644
index 000000000000..8813471af4cf
--- /dev/null
+++ b/arch/arm/mach-nspire/mmio.h
@@ -0,0 +1,20 @@
+/*
+ *      linux/arch/arm/mach-nspire/mmio.h
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define NSPIRE_MISC_PHYS_BASE           0x900A0000
+#define NSPIRE_MISC_HWRESET             0x08
+
+#define NSPIRE_PWR_PHYS_BASE            0x900B0000
+#define NSPIRE_PWR_VIRT_BASE            0xFEEB0000
+#define NSPIRE_PWR_BUS_DISABLE1         0x18
+#define NSPIRE_PWR_BUS_DISABLE2         0x20
+
+#define NSPIRE_LCD_PHYS_BASE            0xC0000000
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
new file mode 100644
index 000000000000..99e26092a9f7
--- /dev/null
+++ b/arch/arm/mach-nspire/nspire.c
@@ -0,0 +1,89 @@
+/*
+ *      linux/arch/arm/mach-nspire/nspire.c
+ *
+ *      Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/init.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-vic.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/clocksource.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/mach/map.h>
+
+#include <asm/hardware/timer-sp.h>
+
+#include "mmio.h"
+#include "clcd.h"
+
+static const char *nspire_dt_match[] __initconst = {
+        "ti,nspire",
+        "ti,nspire-cx",
+        "ti,nspire-tp",
+        "ti,nspire-clp",
+        NULL,
+};
+
+static void __init nspire_map_io(void)
+{
+        debug_ll_io_init();
+}
+
+static struct clcd_board nspire_clcd_data = {
+        .name           = "LCD",
+        .caps           = CLCD_CAP_5551 | CLCD_CAP_565,
+        .check          = clcdfb_check,
+        .decode         = clcdfb_decode,
+        .setup          = nspire_clcd_setup,
+        .mmap           = nspire_clcd_mmap,
+        .remove         = nspire_clcd_remove,
+};
+
+
+static struct of_dev_auxdata nspire_auxdata[] __initdata = {
+        OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
+                        NULL, &nspire_clcd_data),
+        { }
+};
+
+static void __init nspire_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        nspire_auxdata, NULL);
+}
+
+static void __init nspire_init_time(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+
+static void nspire_restart(char mode, const char *cmd)
+{
+        void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
+        if (!base)
+                return;
+
+        writel(2, base + NSPIRE_MISC_HWRESET);
+}
+
+DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
+        .dt_compat      = nspire_dt_match,
+        .map_io         = nspire_map_io,
+        .init_time      = nspire_init_time,
+        .init_machine   = nspire_init,
+        .restart        = nspire_restart,
+MACHINE_END
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index 222d58c0ae76..3889b6cd211e 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -19,10 +19,6 @@ obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
 # Power Management
 obj-$(CONFIG_PM) += pm.o sleep.o
 
-# DSP
-obj-$(CONFIG_OMAP_MBOX_FWK)     += mailbox_mach.o
-mailbox_mach-objs               := mailbox.o
-
 i2c-omap-$(CONFIG_I2C_OMAP)             := i2c.o
 obj-y                                   += $(i2c-omap-m) $(i2c-omap-y)
 
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 0dac3d239e32..fd90cafc2e36 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -41,7 +41,6 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 #include <mach/flash.h>
 
@@ -50,7 +49,6 @@
 
 #include "common.h"
 #include "board-h2.h"
-#include "dma.h"
 
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
 #define OMAP1610_ETHR_START             0x04000300
@@ -276,39 +274,6 @@ static struct platform_device h2_kp_device = {
         .resource       = h2_kp_resources,
 };
 
-#define H2_IRDA_FIRSEL_GPIO_PIN 17
-
-static struct omap_irda_config h2_irda_data = {
-        .transceiver_cap        = IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-
-static struct resource h2_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 irda_dmamask = 0xffffffff;
-
-static struct platform_device h2_irda_device = {
-        .name           = "omapirda",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &h2_irda_data,
-                .dma_mask       = &irda_dmamask,
-        },
-        .num_resources  = ARRAY_SIZE(h2_irda_resources),
-        .resource       = h2_irda_resources,
-};
-
 static struct gpio_led h2_gpio_led_pins[] = {
         {
                 .name           = "h2:red",
@@ -339,7 +304,6 @@ static struct platform_device *h2_devices[] __initdata = {
         &h2_nor_device,
         &h2_nand_device,
         &h2_smc91x_device,
-        &h2_irda_device,
         &h2_kp_device,
         &h2_gpio_leds,
 };
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 62a15e289c79..91449c5cb70f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -234,16 +234,26 @@ static struct i2c_board_info nokia770_i2c_board_info_2[] __initdata = {
         {
                 I2C_BOARD_INFO("retu-mfd", 0x01),
         },
+        {
+                I2C_BOARD_INFO("tahvo-mfd", 0x02),
+        },
 };
 
 static void __init nokia770_cbus_init(void)
 {
         const int retu_irq_gpio = 62;
+        const int tahvo_irq_gpio = 40;
 
         if (gpio_request_one(retu_irq_gpio, GPIOF_IN, "Retu IRQ"))
                 return;
+        if (gpio_request_one(tahvo_irq_gpio, GPIOF_IN, "Tahvo IRQ")) {
+                gpio_free(retu_irq_gpio);
+                return;
+        }
         irq_set_irq_type(gpio_to_irq(retu_irq_gpio), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(tahvo_irq_gpio), IRQ_TYPE_EDGE_RISING);
         nokia770_i2c_board_info_2[0].irq = gpio_to_irq(retu_irq_gpio);
+        nokia770_i2c_board_info_2[1].irq = gpio_to_irq(tahvo_irq_gpio);
         i2c_register_board_info(2, nokia770_i2c_board_info_2,
                                 ARRAY_SIZE(nokia770_i2c_board_info_2));
         platform_device_register(&nokia770_cbus_device);
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 845a1a7aef95..3b8e98f4353c 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -38,14 +38,12 @@
 #include <mach/mux.h>
 #include <mach/tc.h>
 #include <linux/omap-dma.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "common.h"
-#include "dma.h"
 
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
@@ -167,40 +165,11 @@ static struct platform_device palmte_backlight_device = {
         },
 };
 
-static struct omap_irda_config palmte_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-
-static struct resource palmte_irda_resources[] = {
-        [0]     = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device palmte_irda_device = {
-        .name           = "omapirda",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &palmte_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmte_irda_resources),
-        .resource       = palmte_irda_resources,
-};
-
 static struct platform_device *palmte_devices[] __initdata = {
         &palmte_rom_device,
         &palmte_kp_device,
         &palmte_lcd_device,
         &palmte_backlight_device,
-        &palmte_irda_device,
 };
 
 static struct omap_usb_config palmte_usb_config __initdata = {
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 65a4a3e357f2..ca501208825f 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -38,14 +38,12 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "common.h"
-#include "dma.h"
 
 #define PALMTT_USBDETECT_GPIO   0
 #define PALMTT_CABLE_GPIO       1
@@ -163,33 +161,6 @@ static struct platform_device palmtt_lcd_device = {
         .name           = "lcd_palmtt",
         .id             = -1,
 };
-static struct omap_irda_config palmtt_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-
-static struct resource palmtt_irda_resources[] = {
-        [0]     = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device palmtt_irda_device = {
-        .name           = "omapirda",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &palmtt_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmtt_irda_resources),
-        .resource       = palmtt_irda_resources,
-};
 
 static struct platform_device palmtt_spi_device = {
         .name           = "spi_palmtt",
@@ -234,7 +205,6 @@ static struct platform_device *palmtt_devices[] __initdata = {
         &palmtt_flash_device,
         &palmtt_kp_device,
         &palmtt_lcd_device,
-        &palmtt_irda_device,
         &palmtt_spi_device,
         &palmtt_backlight_device,
         &palmtt_led_device,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 01c970071fd8..470e12d67360 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -40,14 +40,12 @@
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
 #include <mach/tc.h>
-#include <mach/irda.h>
 #include <linux/platform_data/keypad-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/usb.h>
 
 #include "common.h"
-#include "dma.h"
 
 #define PALMZ71_USBDETECT_GPIO  0
 #define PALMZ71_PENIRQ_GPIO     6
@@ -153,34 +151,6 @@ static struct platform_device palmz71_lcd_device = {
         .id     = -1,
 };
 
-static struct omap_irda_config palmz71_irda_config = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-
-static struct resource palmz71_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device palmz71_irda_device = {
-        .name   = "omapirda",
-        .id     = -1,
-        .dev = {
-                .platform_data = &palmz71_irda_config,
-        },
-        .num_resources  = ARRAY_SIZE(palmz71_irda_resources),
-        .resource       = palmz71_irda_resources,
-};
-
 static struct platform_device palmz71_spi_device = {
         .name   = "spi_palmz71",
         .id     = -1,
@@ -202,7 +172,6 @@ static struct platform_device *devices[] __initdata = {
         &palmz71_rom_device,
         &palmz71_kp_device,
         &palmz71_lcd_device,
-        &palmz71_irda_device,
         &palmz71_spi_device,
         &palmz71_backlight_device,
 };
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 9732a98f3e06..0a8d3349149c 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -37,7 +37,6 @@
 #include <mach/flash.h>
 #include <mach/mux.h>
 #include <linux/omap-dma.h>
-#include <mach/irda.h>
 #include <mach/tc.h>
 #include <mach/board-sx1.h>
 
@@ -45,7 +44,6 @@
 #include <mach/usb.h>
 
 #include "common.h"
-#include "dma.h"
 
 /* Write to I2C device */
 int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value)
@@ -228,39 +226,6 @@ static struct platform_device sx1_kp_device = {
         .resource       = sx1_kp_resources,
 };
 
-/*----------- IRDA -------------------------*/
-
-static struct omap_irda_config sx1_irda_data = {
-        .transceiver_cap        = IR_SIRMODE,
-        .rx_channel             = OMAP_DMA_UART3_RX,
-        .tx_channel             = OMAP_DMA_UART3_TX,
-        .dest_start             = UART3_THR,
-        .src_start              = UART3_RHR,
-        .tx_trigger             = 0,
-        .rx_trigger             = 0,
-};
-
-static struct resource sx1_irda_resources[] = {
-        [0] = {
-                .start  = INT_UART3,
-                .end    = INT_UART3,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 irda_dmamask = 0xffffffff;
-
-static struct platform_device sx1_irda_device = {
-        .name           = "omapirda",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &sx1_irda_data,
-                .dma_mask       = &irda_dmamask,
-        },
-        .num_resources  = ARRAY_SIZE(sx1_irda_resources),
-        .resource       = sx1_irda_resources,
-};
-
 /*----------- MTD -------------------------*/
 
 static struct mtd_partition sx1_partitions[] = {
@@ -366,7 +331,6 @@ static struct omap_lcd_config sx1_lcd_config __initdata = {
 static struct platform_device *sx1_devices[] __initdata = {
         &sx1_flash_device,
         &sx1_kp_device,
-        &sx1_irda_device,
 };
 
 /*-----------------------------------------*/
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 0af635205e8a..325e6030095e 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -30,7 +30,6 @@
 
 #include "common.h"
 #include "clock.h"
-#include "dma.h"
 #include "mmc.h"
 #include "sram.h"
 
@@ -223,16 +222,16 @@ void __init omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                 case 0:
                         base = OMAP1_MMC1_BASE;
                         irq = INT_MMC;
-                        rx_req = OMAP_DMA_MMC_RX;
-                        tx_req = OMAP_DMA_MMC_TX;
+                        rx_req = 22;
+                        tx_req = 21;
                         break;
                 case 1:
                         if (!cpu_is_omap16xx())
                                 return;
                         base = OMAP1_MMC2_BASE;
                         irq = INT_1610_MMC2;
-                        rx_req = OMAP_DMA_MMC2_RX;
-                        tx_req = OMAP_DMA_MMC2_TX;
+                        rx_req = 55;
+                        tx_req = 54;
                         break;
                 default:
                         continue;
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index a94b3a718d1a..5bb8ce86d54b 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -30,8 +30,6 @@
 
 #include <mach/irqs.h>
 
-#include "dma.h"
-
 #define OMAP1_DMA_BASE                  (0xfffed800)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 #define OMAP1_DMA_STRIDE                0x40
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
deleted file mode 100644
index d05909c96715..000000000000
--- a/arch/arm/mach-omap1/dma.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  OMAP1 DMA channel definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __OMAP1_DMA_CHANNEL_H
-#define __OMAP1_DMA_CHANNEL_H
-
-/* DMA channels for omap1 */
-#define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCBSP1_TX              8
-#define OMAP_DMA_MCBSP1_RX              9
-#define OMAP_DMA_MCBSP3_TX              10
-#define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_MCBSP2_TX              16
-#define OMAP_DMA_MCBSP2_RX              17
-#define OMAP_DMA_UART3_TX               18
-#define OMAP_DMA_UART3_RX               19
-#define OMAP_DMA_CAMERA_IF_RX           20
-#define OMAP_DMA_MMC_TX                 21
-#define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_TX0           29
-
-/* These are only for 1610 */
-#define OMAP_DMA_MMC2_TX                54
-#define OMAP_DMA_MMC2_RX                55
-
-#endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap1/include/mach/irda.h b/arch/arm/mach-omap1/include/mach/irda.h
deleted file mode 100644
index 40f60339d1c6..000000000000
--- a/arch/arm/mach-omap1/include/mach/irda.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/irda.h
- *
- *  Copyright (C) 2005-2006 Komal Shah <komal_shah802003@yahoo.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef ASMARM_ARCH_IRDA_H
-#define ASMARM_ARCH_IRDA_H
-
-/* board specific transceiver capabilities */
-
-#define IR_SEL          1       /* Selects IrDA */
-#define IR_SIRMODE      2
-#define IR_FIRMODE      4
-#define IR_MIRMODE      8
-
-struct omap_irda_config {
-        int transceiver_cap;
-        int (*transceiver_mode)(struct device *dev, int mode);
-        int (*select_irda)(struct device *dev, int state);
-        int rx_channel;
-        int tx_channel;
-        unsigned long dest_start;
-        unsigned long src_start;
-        int tx_trigger;
-        int rx_trigger;
-        int mode;
-};
-
-#endif
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 77924be37d41..26a2b01c7c4f 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -32,8 +32,6 @@
 #include <mach/hardware.h>
 #include <mach/lcdc.h>
 
-#include "dma.h"
-
 int omap_lcd_dma_running(void)
 {
         /*
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
deleted file mode 100644
index efc8f207f6fc..000000000000
--- a/arch/arm/mach-omap1/mailbox.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * Mailbox reservation modules for OMAP1
- *
- * Copyright (C) 2006-2009 Nokia Corporation
- * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <plat/mailbox.h>
-
-#define MAILBOX_ARM2DSP1                0x00
-#define MAILBOX_ARM2DSP1b               0x04
-#define MAILBOX_DSP2ARM1                0x08
-#define MAILBOX_DSP2ARM1b               0x0c
-#define MAILBOX_DSP2ARM2                0x10
-#define MAILBOX_DSP2ARM2b               0x14
-#define MAILBOX_ARM2DSP1_Flag           0x18
-#define MAILBOX_DSP2ARM1_Flag           0x1c
-#define MAILBOX_DSP2ARM2_Flag           0x20
-
-static void __iomem *mbox_base;
-
-struct omap_mbox1_fifo {
-        unsigned long cmd;
-        unsigned long data;
-        unsigned long flag;
-};
-
-struct omap_mbox1_priv {
-        struct omap_mbox1_fifo tx_fifo;
-        struct omap_mbox1_fifo rx_fifo;
-};
-
-static inline int mbox_read_reg(size_t ofs)
-{
-        return __raw_readw(mbox_base + ofs);
-}
-
-static inline void mbox_write_reg(u32 val, size_t ofs)
-{
-        __raw_writew(val, mbox_base + ofs);
-}
-
-/* msg */
-static mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
-        mbox_msg_t msg;
-
-        msg = mbox_read_reg(fifo->data);
-        msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
-
-        return msg;
-}
-
-static void
-omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
-
-        mbox_write_reg(msg & 0xffff, fifo->data);
-        mbox_write_reg(msg >> 16, fifo->cmd);
-}
-
-static int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        return 0;
-}
-
-static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
-{
-        struct omap_mbox1_fifo *fifo =
-                &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
-
-        return mbox_read_reg(fifo->flag);
-}
-
-/* irq */
-static void
-omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_RX)
-                enable_irq(mbox->irq);
-}
-
-static void
-omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_RX)
-                disable_irq(mbox->irq);
-}
-
-static int
-omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
-{
-        if (irq == IRQ_TX)
-                return 0;
-        return 1;
-}
-
-static struct omap_mbox_ops omap1_mbox_ops = {
-        .type           = OMAP_MBOX_TYPE1,
-        .fifo_read      = omap1_mbox_fifo_read,
-        .fifo_write     = omap1_mbox_fifo_write,
-        .fifo_empty     = omap1_mbox_fifo_empty,
-        .fifo_full      = omap1_mbox_fifo_full,
-        .enable_irq     = omap1_mbox_enable_irq,
-        .disable_irq    = omap1_mbox_disable_irq,
-        .is_irq         = omap1_mbox_is_irq,
-};
-
-/* FIXME: the following struct should be created automatically by the user id */
-
-/* DSP */
-static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
-        .tx_fifo = {
-                .cmd    = MAILBOX_ARM2DSP1b,
-                .data   = MAILBOX_ARM2DSP1,
-                .flag   = MAILBOX_ARM2DSP1_Flag,
-        },
-        .rx_fifo = {
-                .cmd    = MAILBOX_DSP2ARM1b,
-                .data   = MAILBOX_DSP2ARM1,
-                .flag   = MAILBOX_DSP2ARM1_Flag,
-        },
-};
-
-static struct omap_mbox mbox_dsp_info = {
-        .name   = "dsp",
-        .ops    = &omap1_mbox_ops,
-        .priv   = &omap1_mbox_dsp_priv,
-};
-
-static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
-
-static int omap1_mbox_probe(struct platform_device *pdev)
-{
-        struct resource *mem;
-        int ret;
-        struct omap_mbox **list;
-
-        list = omap1_mboxes;
-        list[0]->irq = platform_get_irq_byname(pdev, "dsp");
-
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        mbox_base = ioremap(mem->start, resource_size(mem));
-        if (!mbox_base)
-                return -ENOMEM;
-
-        ret = omap_mbox_register(&pdev->dev, list);
-        if (ret) {
-                iounmap(mbox_base);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int omap1_mbox_remove(struct platform_device *pdev)
-{
-        omap_mbox_unregister();
-        iounmap(mbox_base);
-        return 0;
-}
-
-static struct platform_driver omap1_mbox_driver = {
-        .probe  = omap1_mbox_probe,
-        .remove = omap1_mbox_remove,
-        .driver = {
-                .name   = "omap-mailbox",
-        },
-};
-
-static int __init omap1_mbox_init(void)
-{
-        return platform_driver_register(&omap1_mbox_driver);
-}
-
-static void __exit omap1_mbox_exit(void)
-{
-        platform_driver_unregister(&omap1_mbox_driver);
-}
-
-module_init(omap1_mbox_init);
-module_exit(omap1_mbox_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
-MODULE_ALIAS("platform:omap1-mailbox");
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index b0d4723c9a90..8ed67f8d1762 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -27,7 +27,6 @@
 #include <mach/irqs.h>
 
 #include "iomap.h"
-#include "dma.h"
 
 #define DPS_RSTCT2_PER_EN       (1 << 0)
 #define DSP_RSTCT2_WD_PER_EN    (1 << 1)
@@ -114,12 +113,12 @@ struct resource omap7xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -141,12 +140,12 @@ struct resource omap7xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -191,12 +190,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -218,12 +217,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP2_RX,
+                        .start = 17,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP2_TX,
+                        .start = 16,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -245,12 +244,12 @@ struct resource omap15xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -298,12 +297,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP1_RX,
+                        .start = 9,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP1_TX,
+                        .start = 8,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -325,12 +324,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP2_RX,
+                        .start = 17,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP2_TX,
+                        .start = 16,
                         .flags = IORESOURCE_DMA,
                 },
         },
@@ -352,12 +351,12 @@ struct resource omap16xx_mcbsp_res[][6] = {
                 },
                 {
                         .name  = "rx",
-                        .start = OMAP_DMA_MCBSP3_RX,
+                        .start = 11,
                         .flags = IORESOURCE_DMA,
                 },
                 {
                         .name  = "tx",
-                        .start = OMAP_DMA_MCBSP3_TX,
+                        .start = 10,
                         .flags = IORESOURCE_DMA,
                 },
         },
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f49cd51e162a..c7b32a966f67 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -4,6 +4,7 @@ config ARCH_OMAP
 config ARCH_OMAP2PLUS
         bool "TI OMAP2/3/4/5 SoCs with device tree support" if (ARCH_MULTI_V6 || ARCH_MULTI_V7)
         select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_BANDGAP
         select ARCH_HAS_HOLES_MEMORYMODEL
         select ARCH_OMAP
         select ARCH_REQUIRE_GPIOLIB
@@ -17,6 +18,7 @@ config ARCH_OMAP2PLUS
         select PROC_DEVICETREE if PROC_FS
         select SOC_BUS
         select SPARSE_IRQ
+        select TI_PRIV_EDMA
         select USE_OF
         help
           Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
@@ -149,6 +151,14 @@ config SOC_AM33XX
         select MULTI_IRQ_HANDLER
         select COMMON_CLK
 
+config SOC_AM43XX
+        bool "TI AM43x"
+        select CPU_V7
+        select MULTI_IRQ_HANDLER
+        select ARM_GIC
+        select COMMON_CLK
+        select MACH_OMAP_GENERIC
+
 config OMAP_PACKAGE_ZAF
        bool
 
@@ -167,12 +177,6 @@ config OMAP_PACKAGE_CUS
 config OMAP_PACKAGE_CBP
        bool
 
-config OMAP_PACKAGE_CBL
-       bool
-
-config OMAP_PACKAGE_CBS
-       bool
-
 comment "OMAP Board Type"
         depends on ARCH_OMAP2PLUS
 
@@ -378,22 +382,6 @@ config MACH_TI8148EVM
         depends on SOC_TI81XX
         default y
 
-config MACH_OMAP_4430SDP
-        bool "OMAP 4430 SDP board"
-        default y
-        depends on ARCH_OMAP4
-        select OMAP_PACKAGE_CBL
-        select OMAP_PACKAGE_CBS
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-
-config MACH_OMAP4_PANDA
-        bool "OMAP4 Panda Board"
-        default y
-        depends on ARCH_OMAP4
-        select OMAP_PACKAGE_CBL
-        select OMAP_PACKAGE_CBS
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-
 config OMAP3_EMU
         bool "OMAP3 debugging peripherals"
         depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 55a9d6777683..ea5a27ff9941 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
 obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
@@ -34,10 +35,10 @@ obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)	+= sdrc.o
 
 smp-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
-                                           sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y)
-obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y)
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common) $(smp-y) sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common) $(smp-y) sleep44xx.o
+obj-$(CONFIG_SOC_AM43XX)                += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,12 +59,13 @@ obj-$(CONFIG_SOC_OMAP2420)		+= omap2-restart.o
 obj-$(CONFIG_SOC_OMAP2430)              += omap2-restart.o
 obj-$(CONFIG_SOC_AM33XX)                += am33xx-restart.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap3-restart.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-restart.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap4-restart.o
 
 # Pin multiplexing
 obj-$(CONFIG_SOC_OMAP2420)              += mux2420.o
 obj-$(CONFIG_SOC_OMAP2430)              += mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)                += mux34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += mux44xx.o
 
 # SMS/SDRC
 obj-$(CONFIG_ARCH_OMAP2)                += sdrc2xxx.o
@@ -110,6 +112,7 @@ obj-$(CONFIG_ARCH_OMAP2)		+= prm2xxx_3xxx.o prm2xxx.o cm2xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prm2xxx_3xxx.o prm3xxx.o cm3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += prm33xx.o cm33xx.o
+obj-$(CONFIG_SOC_AM43XX)                += prm33xx.o cm33xx.o
 omap-prcm-4-5-common                    =  cminst44xx.o cm44xx.o prm44xx.o \
                                            prcm_mpu44xx.o prminst44xx.o \
                                            vc44xx_data.o vp44xx_data.o
@@ -125,8 +128,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
+obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -140,7 +144,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(powerdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += powerdomains54xx_data.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
@@ -155,7 +161,9 @@ obj-$(CONFIG_ARCH_OMAP4)		+= $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_AM43XX)                += $(clockdomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += clockdomains54xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -198,14 +206,12 @@ obj-$(CONFIG_ARCH_OMAP3)		+= omap_hwmod_2xxx_3xxx_interconnect_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += omap_hwmod_3xxx_data.o
 obj-$(CONFIG_SOC_AM33XX)                += omap_hwmod_33xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_hwmod_44xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap_hwmod_54xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
 obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
 
-obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
-mailbox_mach-objs                       := mailbox.o
-
 iommu-$(CONFIG_OMAP_IOMMU)              := omap-iommu.o
 obj-y                                   += $(iommu-m) $(iommu-y)
 
@@ -251,8 +257,6 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
 obj-$(CONFIG_MACH_TOUCHBOOK)            += board-omap3touchbook.o
-obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
-obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
 obj-$(CONFIG_MACH_OMAP3517EVM)          += board-am3517evm.o
 
diff --git a/arch/arm/mach-omap2/am33xx.h b/arch/arm/mach-omap2/am33xx.h
index 43296c1af9ee..5eef093e6738 100644
--- a/arch/arm/mach-omap2/am33xx.h
+++ b/arch/arm/mach-omap2/am33xx.h
@@ -21,6 +21,7 @@
 #define AM33XX_SCM_BASE         0x44E10000
 #define AM33XX_CTRL_BASE        AM33XX_SCM_BASE
 #define AM33XX_PRCM_BASE        0x44E00000
+#define AM43XX_PRCM_BASE        0x44DF0000
 #define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + 0x3FC)
 
 #endif /* __ASM_ARCH_AM33XX_H */
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
deleted file mode 100644
index 56a9a4f855c7..000000000000
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/*
- * Board support file for OMAP4430 SDP.
- *
- * Copyright (C) 2009 Texas Instruments
- *
- * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/gpio_keys.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/pwm.h>
-#include <linux/leds.h>
-#include <linux/leds_pwm.h>
-#include <linux/pwm_backlight.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap4-keypad.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "omap4-keypad.h"
-#include <linux/wl12xx.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-
-#include "soc.h"
-#include "mux.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-
-#define ETH_KS8851_IRQ                  34
-#define ETH_KS8851_POWER_ON             48
-#define ETH_KS8851_QUART                138
-#define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
-#define OMAP4_SFH7741_ENABLE_GPIO               188
-
-#define GPIO_WIFI_PMENA         54
-#define GPIO_WIFI_IRQ           53
-
-static const int sdp4430_keymap[] = {
-        KEY(0, 0, KEY_E),
-        KEY(0, 1, KEY_R),
-        KEY(0, 2, KEY_T),
-        KEY(0, 3, KEY_HOME),
-        KEY(0, 4, KEY_F5),
-        KEY(0, 5, KEY_UNKNOWN),
-        KEY(0, 6, KEY_I),
-        KEY(0, 7, KEY_LEFTSHIFT),
-
-        KEY(1, 0, KEY_D),
-        KEY(1, 1, KEY_F),
-        KEY(1, 2, KEY_G),
-        KEY(1, 3, KEY_SEND),
-        KEY(1, 4, KEY_F6),
-        KEY(1, 5, KEY_UNKNOWN),
-        KEY(1, 6, KEY_K),
-        KEY(1, 7, KEY_ENTER),
-
-        KEY(2, 0, KEY_X),
-        KEY(2, 1, KEY_C),
-        KEY(2, 2, KEY_V),
-        KEY(2, 3, KEY_END),
-        KEY(2, 4, KEY_F7),
-        KEY(2, 5, KEY_UNKNOWN),
-        KEY(2, 6, KEY_DOT),
-        KEY(2, 7, KEY_CAPSLOCK),
-
-        KEY(3, 0, KEY_Z),
-        KEY(3, 1, KEY_KPPLUS),
-        KEY(3, 2, KEY_B),
-        KEY(3, 3, KEY_F1),
-        KEY(3, 4, KEY_F8),
-        KEY(3, 5, KEY_UNKNOWN),
-        KEY(3, 6, KEY_O),
-        KEY(3, 7, KEY_SPACE),
-
-        KEY(4, 0, KEY_W),
-        KEY(4, 1, KEY_Y),
-        KEY(4, 2, KEY_U),
-        KEY(4, 3, KEY_F2),
-        KEY(4, 4, KEY_VOLUMEUP),
-        KEY(4, 5, KEY_UNKNOWN),
-        KEY(4, 6, KEY_L),
-        KEY(4, 7, KEY_LEFT),
-
-        KEY(5, 0, KEY_S),
-        KEY(5, 1, KEY_H),
-        KEY(5, 2, KEY_J),
-        KEY(5, 3, KEY_F3),
-        KEY(5, 4, KEY_F9),
-        KEY(5, 5, KEY_VOLUMEDOWN),
-        KEY(5, 6, KEY_M),
-        KEY(5, 7, KEY_RIGHT),
-
-        KEY(6, 0, KEY_Q),
-        KEY(6, 1, KEY_A),
-        KEY(6, 2, KEY_N),
-        KEY(6, 3, KEY_BACK),
-        KEY(6, 4, KEY_BACKSPACE),
-        KEY(6, 5, KEY_UNKNOWN),
-        KEY(6, 6, KEY_P),
-        KEY(6, 7, KEY_UP),
-
-        KEY(7, 0, KEY_PROG1),
-        KEY(7, 1, KEY_PROG2),
-        KEY(7, 2, KEY_PROG3),
-        KEY(7, 3, KEY_PROG4),
-        KEY(7, 4, KEY_F4),
-        KEY(7, 5, KEY_UNKNOWN),
-        KEY(7, 6, KEY_OK),
-        KEY(7, 7, KEY_DOWN),
-};
-static struct omap_device_pad keypad_pads[] = {
-        {       .name   = "kpd_col1.kpd_col1",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col1.kpd_col1",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col2.kpd_col2",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col3.kpd_col3",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col4.kpd_col4",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_col5.kpd_col5",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "gpmc_a23.kpd_col7",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "gpmc_a22.kpd_col6",
-                .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
-        },
-        {       .name   = "kpd_row0.kpd_row0",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row1.kpd_row1",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row2.kpd_row2",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row3.kpd_row3",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row4.kpd_row4",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "kpd_row5.kpd_row5",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "gpmc_a18.kpd_row6",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-        {       .name   = "gpmc_a19.kpd_row7",
-                .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
-                        OMAP_MUX_MODE1 | OMAP_INPUT_EN,
-        },
-};
-
-static struct matrix_keymap_data sdp4430_keymap_data = {
-        .keymap                 = sdp4430_keymap,
-        .keymap_size            = ARRAY_SIZE(sdp4430_keymap),
-};
-
-static struct omap4_keypad_platform_data sdp4430_keypad_data = {
-        .keymap_data            = &sdp4430_keymap_data,
-        .rows                   = 8,
-        .cols                   = 8,
-};
-
-static struct omap_board_data keypad_data = {
-        .id                     = 1,
-        .pads                   = keypad_pads,
-        .pads_cnt               = ARRAY_SIZE(keypad_pads),
-};
-
-static struct gpio_led sdp4430_gpio_leds[] = {
-        {
-                .name   = "omap4:green:debug0",
-                .gpio   = 61,
-        },
-        {
-                .name   = "omap4:green:debug1",
-                .gpio   = 30,
-        },
-        {
-                .name   = "omap4:green:debug2",
-                .gpio   = 7,
-        },
-        {
-                .name   = "omap4:green:debug3",
-                .gpio   = 8,
-        },
-        {
-                .name   = "omap4:green:debug4",
-                .gpio   = 50,
-        },
-        {
-                .name   = "omap4:blue:user",
-                .gpio   = 169,
-        },
-        {
-                .name   = "omap4:red:user",
-                .gpio   = 170,
-        },
-        {
-                .name   = "omap4:green:user",
-                .gpio   = 139,
-        },
-
-};
-
-static struct gpio_keys_button sdp4430_gpio_keys[] = {
-        {
-                .desc                   = "Proximity Sensor",
-                .type                   = EV_SW,
-                .code                   = SW_FRONT_PROXIMITY,
-                .gpio                   = OMAP4_SFH7741_SENSOR_OUTPUT_GPIO,
-                .active_low             = 0,
-        }
-};
-
-static struct gpio_led_platform_data sdp4430_led_data = {
-        .leds   = sdp4430_gpio_leds,
-        .num_leds       = ARRAY_SIZE(sdp4430_gpio_leds),
-};
-
-static struct pwm_lookup sdp4430_pwm_lookup[] = {
-        PWM_LOOKUP("twl-pwm", 0, "leds_pwm", "omap4::keypad"),
-        PWM_LOOKUP("twl-pwm", 1, "pwm-backlight", NULL),
-        PWM_LOOKUP("twl-pwmled", 0, "leds_pwm", "omap4:green:chrg"),
-};
-
-static struct led_pwm sdp4430_pwm_leds[] = {
-        {
-                .name           = "omap4::keypad",
-                .max_brightness = 127,
-                .pwm_period_ns  = 7812500,
-        },
-        {
-                .name           = "omap4:green:chrg",
-                .max_brightness = 255,
-                .pwm_period_ns  = 7812500,
-        },
-};
-
-static struct led_pwm_platform_data sdp4430_pwm_data = {
-        .num_leds       = ARRAY_SIZE(sdp4430_pwm_leds),
-        .leds           = sdp4430_pwm_leds,
-};
-
-static struct platform_device sdp4430_leds_pwm = {
-        .name   = "leds_pwm",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_pwm_data,
-        },
-};
-
-/* Dummy regulator for pwm-backlight driver */
-static struct regulator_consumer_supply backlight_supply =
-        REGULATOR_SUPPLY("enable", "pwm-backlight");
-
-static struct platform_pwm_backlight_data sdp4430_backlight_data = {
-        .max_brightness = 127,
-        .dft_brightness = 127,
-        .pwm_period_ns = 7812500,
-};
-
-static struct platform_device sdp4430_backlight_pwm = {
-        .name   = "pwm-backlight",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_backlight_data,
-        },
-};
-
-static int omap_prox_activate(struct device *dev)
-{
-        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 1);
-        return 0;
-}
-
-static void omap_prox_deactivate(struct device *dev)
-{
-        gpio_set_value(OMAP4_SFH7741_ENABLE_GPIO , 0);
-}
-
-static struct gpio_keys_platform_data sdp4430_gpio_keys_data = {
-        .buttons        = sdp4430_gpio_keys,
-        .nbuttons       = ARRAY_SIZE(sdp4430_gpio_keys),
-        .enable         = omap_prox_activate,
-        .disable        = omap_prox_deactivate,
-};
-
-static struct platform_device sdp4430_gpio_keys_device = {
-        .name   = "gpio-keys",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &sdp4430_gpio_keys_data,
-        },
-};
-
-static struct platform_device sdp4430_leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &sdp4430_led_data,
-        },
-};
-static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ks8851",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 24000000,
-                /*
-                 * .irq is set to gpio_to_irq(ETH_KS8851_IRQ)
-                 * in omap_4430sdp_init
-                 */
-        },
-};
-
-static struct gpio sdp4430_eth_gpios[] __initdata = {
-        { ETH_KS8851_POWER_ON,  GPIOF_OUT_INIT_HIGH,    "eth_power"     },
-        { ETH_KS8851_QUART,     GPIOF_OUT_INIT_HIGH,    "quart"         },
-        { ETH_KS8851_IRQ,       GPIOF_IN,               "eth_irq"       },
-};
-
-static int __init omap_ethernet_init(void)
-{
-        int status;
-
-        /* Request of GPIO lines */
-        status = gpio_request_array(sdp4430_eth_gpios,
-                                    ARRAY_SIZE(sdp4430_eth_gpios));
-        if (status)
-                pr_err("Cannot request ETH GPIOs\n");
-
-        return status;
-}
-
-static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
-        REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
-        REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
-};
-
-static struct regulator_init_data sdp4430_vbat_data = {
-        .constraints = {
-                .always_on      = 1,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vbat_supply),
-        .consumer_supplies      = sdp4430_vbat_supply,
-};
-
-static struct fixed_voltage_config sdp4430_vbat_pdata = {
-        .supply_name    = "VBAT",
-        .microvolts     = 3750000,
-        .init_data      = &sdp4430_vbat_data,
-        .gpio           = -EINVAL,
-};
-
-static struct platform_device sdp4430_vbat = {
-        .name           = "reg-fixed-voltage",
-        .id             = -1,
-        .dev = {
-                .platform_data = &sdp4430_vbat_pdata,
-        },
-};
-
-static struct platform_device sdp4430_dmic_codec = {
-        .name   = "dmic-codec",
-        .id     = -1,
-};
-
-static struct platform_device sdp4430_hdmi_audio_codec = {
-        .name   = "hdmi-audio-codec",
-        .id     = -1,
-};
-
-static struct omap_abe_twl6040_data sdp4430_abe_audio_data = {
-        .card_name = "SDP4430",
-        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_ep         = 1,
-        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        .has_vibra      = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-
-        .has_dmic       = 1,
-        .has_hsmic      = 1,
-        .has_mainmic    = 1,
-        .has_submic     = 1,
-        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-
-        .jack_detection = 1,
-        /* MCLK input is 38.4MHz */
-        .mclk_freq      = 38400000,
-};
-
-static struct platform_device sdp4430_abe_audio = {
-        .name           = "omap-abe-twl6040",
-        .id             = -1,
-        .dev = {
-                .platform_data = &sdp4430_abe_audio_data,
-        },
-};
-
-static struct platform_device *sdp4430_devices[] __initdata = {
-        &sdp4430_gpio_keys_device,
-        &sdp4430_leds_gpio,
-        &sdp4430_leds_pwm,
-        &sdp4430_backlight_pwm,
-        &sdp4430_vbat,
-        &sdp4430_dmic_codec,
-        &sdp4430_abe_audio,
-        &sdp4430_hdmi_audio_codec,
-};
-
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 2,
-                .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .nonremovable   = true,
-                .ocr_mask       = MMC_VDD_29_30,
-                .no_off_init    = true,
-        },
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-        {
-                .mmc            = 5,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-                .pm_caps        = MMC_PM_KEEP_POWER,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-                .ocr_mask       = MMC_VDD_165_195,
-                .nonremovable   = true,
-        },
-        {}      /* Terminator */
-};
-
-static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
-};
-
-static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
-        .supply = "vmmc",
-        .dev_name = "omap_hsmmc.4",
-};
-
-static struct regulator_init_data sdp4430_vmmc5 = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = 1,
-        .consumer_supplies = &omap4_sdp4430_vmmc5_supply,
-};
-
-static struct fixed_voltage_config sdp4430_vwlan = {
-        .supply_name            = "vwl1271",
-        .microvolts             = 1800000, /* 1.8V */
-        .gpio                   = GPIO_WIFI_PMENA,
-        .startup_delay          = 70000, /* 70msec */
-        .enable_high            = 1,
-        .enabled_at_boot        = 0,
-        .init_data              = &sdp4430_vmmc5,
-};
-
-static struct platform_device omap_vwlan_device = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev = {
-                .platform_data = &sdp4430_vwlan,
-        },
-};
-
-static struct regulator_init_data sdp4430_vaux1 = {
-        .constraints = {
-                .min_uV                 = 1000000,
-                .max_uV                 = 3000000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = ARRAY_SIZE(sdp4430_vaux_supply),
-        .consumer_supplies      = sdp4430_vaux_supply,
-};
-
-static struct regulator_init_data sdp4430_vusim = {
-        .constraints = {
-                .min_uV                 = 1200000,
-                .max_uV                 = 2900000,
-                .apply_uV               = true,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask  = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-};
-
-static struct twl6040_codec_data twl6040_codec = {
-        /* single-step ramp for headset and handsfree */
-        .hs_left_step   = 0x0f,
-        .hs_right_step  = 0x0f,
-        .hf_left_step   = 0x1d,
-        .hf_right_step  = 0x1d,
-};
-
-static struct twl6040_vibra_data twl6040_vibra = {
-        .vibldrv_res = 8,
-        .vibrdrv_res = 3,
-        .viblmotor_res = 10,
-        .vibrmotor_res = 10,
-        .vddvibl_uV = 0,        /* fixed volt supply - VBAT */
-        .vddvibr_uV = 0,        /* fixed volt supply - VBAT */
-};
-
-static struct twl6040_platform_data twl6040_data = {
-        .codec          = &twl6040_codec,
-        .vibra          = &twl6040_vibra,
-        .audpwron_gpio  = 127,
-};
-
-static struct i2c_board_info __initdata sdp4430_i2c_1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-                .irq = 119 + OMAP44XX_IRQ_GIC_START,
-                .platform_data = &twl6040_data,
-        },
-};
-
-static struct twl4030_platform_data sdp4430_twldata = {
-        /* Regulators */
-        .vusim          = &sdp4430_vusim,
-        .vaux1          = &sdp4430_vaux1,
-};
-
-static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tmp105", 0x48),
-        },
-        {
-                I2C_BOARD_INFO("bh1780", 0x29),
-        },
-};
-static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("hmc5843", 0x1e),
-        },
-};
-static int __init omap4_i2c_init(void)
-{
-        omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC |
-                        TWL_COMMON_REGULATOR_VAUX2 |
-                        TWL_COMMON_REGULATOR_VAUX3 |
-                        TWL_COMMON_REGULATOR_VMMC |
-                        TWL_COMMON_REGULATOR_VPP |
-                        TWL_COMMON_REGULATOR_VANA |
-                        TWL_COMMON_REGULATOR_VCXIO |
-                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG |
-                        TWL_COMMON_REGULATOR_V1V8 |
-                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &sdp4430_twldata, sdp4430_i2c_1_boardinfo,
-                        ARRAY_SIZE(sdp4430_i2c_1_boardinfo));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
-                                ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
-        omap_register_i2c_bus(4, 400, sdp4430_i2c_4_boardinfo,
-                                ARRAY_SIZE(sdp4430_i2c_4_boardinfo));
-        return 0;
-}
-
-static void __init omap_sfh7741prox_init(void)
-{
-        int error;
-
-        error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
-                                 GPIOF_OUT_INIT_LOW, "sfh7741");
-        if (error < 0)
-                pr_err("%s:failed to request GPIO %d, error %d\n",
-                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        /* NIRQ2 for twl6040 */
-        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        /* GPIO_127 for twl6040 */
-        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* McPDM */
-        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        /* DMIC */
-        OMAP4_MUX(ABE_DMIC_CLK1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
-        OMAP4_MUX(ABE_DMIC_DIN1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_DMIC_DIN2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_DMIC_DIN3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McBSP1 */
-        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        /* McBSP2 */
-        OMAP4_MUX(ABE_MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-#else
-#define board_mux       NULL
- #endif
-
-static void __init omap4_sdp4430_wifi_mux_init(void)
-{
-        omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
-                                OMAP_PIN_OFF_WAKEUPENABLE);
-        omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
-
-        omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
-                                OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
-
-}
-
-static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
-        .board_ref_clock = WL12XX_REFCLOCK_26,
-        .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
-};
-
-static void __init omap4_sdp4430_wifi_init(void)
-{
-        int ret;
-
-        omap4_sdp4430_wifi_mux_init();
-        omap4_sdp4430_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-        ret = wl12xx_set_platform_data(&omap4_sdp4430_wlan_data);
-        if (ret)
-                pr_err("Error setting wl12xx data: %d\n", ret);
-        ret = platform_device_register(&omap_vwlan_device);
-        if (ret)
-                pr_err("Error registering wl12xx device: %d\n", ret);
-}
-
-static void __init omap_4430sdp_init(void)
-{
-        int status;
-        int package = OMAP_PACKAGE_CBS;
-
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                package = OMAP_PACKAGE_CBL;
-        omap4_mux_init(board_mux, NULL, package);
-
-        omap4_i2c_init();
-        omap_sfh7741prox_init();
-        regulator_register_always_on(0, "backlight-enable",
-                                     &backlight_supply, 1, 0);
-        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap4_sdp4430_wifi_init();
-        omap4_twl6030_hsmmc_init(mmc);
-
-        usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-        usb_musb_init(&musb_board_data);
-
-        status = omap_ethernet_init();
-        if (status) {
-                pr_err("Ethernet initialization failed: %d\n", status);
-        } else {
-                sdp4430_spi_board_info[0].irq = gpio_to_irq(ETH_KS8851_IRQ);
-                spi_register_board_info(sdp4430_spi_board_info,
-                                ARRAY_SIZE(sdp4430_spi_board_info));
-        }
-
-        pwm_add_table(sdp4430_pwm_lookup, ARRAY_SIZE(sdp4430_pwm_lookup));
-        status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
-        if (status)
-                pr_err("Keypad initialization failed: %d\n", status);
-
-        omap_4430sdp_display_init();
-}
-
-MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
-        /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(omap4_smp_ops),
-        .reserve        = omap_reserve,
-        .map_io         = omap4_map_io,
-        .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
-        .init_machine   = omap_4430sdp_init,
-        .init_late      = omap4430_init_late,
-        .init_time      = omap4_local_timer_init,
-        .restart        = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ee6218c74807..d4622ed26252 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -293,7 +293,8 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
 static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
         REGULATOR_SUPPLY("vcc", "spi1.0"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 576420544178..f1d91ba5d1ac 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -222,6 +222,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 
 static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c33adea0247c..fc20a61f6b2a 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -112,6 +112,9 @@ struct gpmc_timings nand_default_timings[1] = {
                 .cs_rd_off = 36,
                 .cs_wr_off = 36,
 
+                .we_on = 6,
+                .oe_on = 6,
+
                 .adv_on = 6,
                 .adv_rd_off = 24,
                 .adv_wr_off = 36,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 88aa6b1835c3..e5fbfed69aa2 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -185,3 +185,19 @@ DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
         .restart        = omap44xx_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_AM43XX
+static const char *am43_boards_compat[] __initdata = {
+        "ti,am43",
+        NULL,
+};
+
+DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
+        .map_io         = am33xx_map_io,
+        .init_early     = am43xx_init_early,
+        .init_irq       = omap_gic_of_init,
+        .init_machine   = omap_generic_init,
+        .init_time      = omap3_sync32k_timer_init,
+        .dt_compat      = am43_boards_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d0d17bc58d9b..62e4f701b63b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -272,7 +272,8 @@ static struct regulator_init_data ldp_vaux1 = {
 
 static struct regulator_consumer_supply ldp_vpll2_supplies[] = {
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
-        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
 static struct regulator_init_data ldp_vpll2 = {
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d0de7b406..8c026269baca 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -174,6 +174,7 @@ static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = {
         .ud_gpio = OMAP3EVM_LCD_PANEL_UD,
 };
 
+#ifdef CONFIG_BROKEN
 static void __init omap3_evm_display_init(void)
 {
         int r;
@@ -193,6 +194,7 @@ static void __init omap3_evm_display_init(void)
         else
                 gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
 }
+#endif
 
 static struct omap_dss_device omap3_evm_lcd_device = {
         .name                   = "lcd",
@@ -715,7 +717,9 @@ static void __init omap3_evm_init(void)
 
         omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
         omap3evm_init_smsc911x();
+#ifdef CONFIG_BROKEN
         omap3_evm_display_init();
+#endif
         omap3_evm_wl12xx_init();
         omap_twl4030_audio_init("omap3evm", NULL);
 }
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 28133d5b4fed..b1547a0edfcd 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -343,6 +343,7 @@ static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
 static struct regulator_consumer_supply pandora_vdds_supplies[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
deleted file mode 100644
index 1e2c75eee912..000000000000
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/*
- * Board support file for OMAP4430 based PandaBoard.
- *
- * Copyright (C) 2010 Texas Instruments
- *
- * Author: David Anders <x0132446@ti.com>
- *
- * Based on mach-omap2/board-4430sdp.c
- *
- * Author: Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Based on mach-omap2/board-3430sdp.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-#include <linux/i2c/twl.h>
-#include <linux/mfd/twl6040.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/ti_wilink_st.h>
-#include <linux/usb/musb.h>
-#include <linux/usb/phy.h>
-#include <linux/usb/nop-usb-xceiv.h>
-#include <linux/wl12xx.h>
-#include <linux/irqchip/arm-gic.h>
-#include <linux/platform_data/omap-abe-twl6040.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include "common.h"
-#include "soc.h"
-#include "mmc.h"
-#include "hsmmc.h"
-#include "control.h"
-#include "mux.h"
-#include "common-board-devices.h"
-#include "dss-common.h"
-
-#define GPIO_HUB_POWER          1
-#define GPIO_HUB_NRESET         62
-#define GPIO_WIFI_PMENA         43
-#define GPIO_WIFI_IRQ           53
-
-/* wl127x BT, FM, GPS connectivity chip */
-static struct ti_st_plat_data wilink_platform_data = {
-        .nshutdown_gpio = 46,
-        .dev_name       = "/dev/ttyO1",
-        .flow_cntrl     = 1,
-        .baud_rate      = 3000000,
-        .chip_enable    = NULL,
-        .suspend        = NULL,
-        .resume         = NULL,
-};
-
-static struct platform_device wl1271_device = {
-        .name   = "kim",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &wilink_platform_data,
-        },
-};
-
-static struct gpio_led gpio_leds[] = {
-        {
-                .name                   = "pandaboard::status1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = 7,
-        },
-        {
-                .name                   = "pandaboard::status2",
-                .default_trigger        = "mmc0",
-                .gpio                   = 8,
-        },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
-        .leds           = gpio_leds,
-        .num_leds       = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &gpio_led_info,
-        },
-};
-
-static struct omap_abe_twl6040_data panda_abe_audio_data = {
-        /* Audio out */
-        .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* HandsFree through expansion connector */
-        .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
-        .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* PandaBoard: FM RX, PandaBoardES: audio in */
-        .has_afm        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* No jack detection. */
-        .jack_detection = 0,
-        /* MCLK input is 38.4MHz */
-        .mclk_freq      = 38400000,
-
-};
-
-static struct platform_device panda_abe_audio = {
-        .name           = "omap-abe-twl6040",
-        .id             = -1,
-        .dev = {
-                .platform_data = &panda_abe_audio_data,
-        },
-};
-
-static struct platform_device panda_hdmi_audio_codec = {
-        .name   = "hdmi-audio-codec",
-        .id     = -1,
-};
-
-static struct platform_device btwilink_device = {
-        .name   = "btwilink",
-        .id     = -1,
-};
-
-/* PHY device on HS USB Port 1 i.e. nop_usb_xceiv.1 */
-static struct nop_usb_xceiv_platform_data hsusb1_phy_data = {
-        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        .clk_rate = 19200000,
-};
-
-static struct usbhs_phy_data phy_data[] __initdata = {
-        {
-                .port = 1,
-                .reset_gpio = GPIO_HUB_NRESET,
-                .vcc_gpio = GPIO_HUB_POWER,
-                .vcc_polarity = 1,
-                .platform_data = &hsusb1_phy_data,
-        },
-};
-
-static struct platform_device *panda_devices[] __initdata = {
-        &leds_gpio,
-        &wl1271_device,
-        &panda_abe_audio,
-        &panda_hdmi_audio_codec,
-        &btwilink_device,
-};
-
-static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-};
-
-static void __init omap4_ehci_init(void)
-{
-        int ret;
-
-        /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
-        ret = clk_add_alias("main_clk", "nop_usb_xceiv.1", "auxclk3_ck", NULL);
-        if (ret)
-                pr_err("Failed to add main_clk alias to auxclk3_ck\n");
-
-        usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
-        usbhs_init(&usbhs_bdata);
-}
-
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_UTMI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
-static struct omap2_hsmmc_info mmc[] = {
-        {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = -EINVAL,
-                .gpio_cd        = -EINVAL,
-        },
-        {
-                .name           = "wl1271",
-                .mmc            = 5,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
-                .gpio_wp        = -EINVAL,
-                .gpio_cd        = -EINVAL,
-                .ocr_mask       = MMC_VDD_165_195,
-                .nonremovable   = true,
-        },
-        {}      /* Terminator */
-};
-
-static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
-};
-
-static struct regulator_init_data panda_vmmc5 = {
-        .constraints = {
-                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
-        .consumer_supplies = omap4_panda_vmmc5_supply,
-};
-
-static struct fixed_voltage_config panda_vwlan = {
-        .supply_name = "vwl1271",
-        .microvolts = 1800000, /* 1.8V */
-        .gpio = GPIO_WIFI_PMENA,
-        .startup_delay = 70000, /* 70msec */
-        .enable_high = 1,
-        .enabled_at_boot = 0,
-        .init_data = &panda_vmmc5,
-};
-
-static struct platform_device omap_vwlan_device = {
-        .name           = "reg-fixed-voltage",
-        .id             = 1,
-        .dev = {
-                .platform_data = &panda_vwlan,
-        },
-};
-
-static struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
-        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
-};
-
-static struct twl6040_codec_data twl6040_codec = {
-        /* single-step ramp for headset and handsfree */
-        .hs_left_step   = 0x0f,
-        .hs_right_step  = 0x0f,
-        .hf_left_step   = 0x1d,
-        .hf_right_step  = 0x1d,
-};
-
-static struct twl6040_platform_data twl6040_data = {
-        .codec          = &twl6040_codec,
-        .audpwron_gpio  = 127,
-};
-
-static struct i2c_board_info __initdata panda_i2c_1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6040", 0x4b),
-                .irq = 119 + OMAP44XX_IRQ_GIC_START,
-                .platform_data = &twl6040_data,
-        },
-};
-
-/* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata;
-
-/*
- * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
- * is connected as I2C slave device, and can be accessed at address 0x50
- */
-static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
-        {
-                I2C_BOARD_INFO("eeprom", 0x50),
-        },
-};
-
-static int __init omap4_panda_i2c_init(void)
-{
-        omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC |
-                        TWL_COMMON_REGULATOR_VAUX2 |
-                        TWL_COMMON_REGULATOR_VAUX3 |
-                        TWL_COMMON_REGULATOR_VMMC |
-                        TWL_COMMON_REGULATOR_VPP |
-                        TWL_COMMON_REGULATOR_VANA |
-                        TWL_COMMON_REGULATOR_VCXIO |
-                        TWL_COMMON_REGULATOR_VUSB |
-                        TWL_COMMON_REGULATOR_CLK32KG |
-                        TWL_COMMON_REGULATOR_V1V8 |
-                        TWL_COMMON_REGULATOR_V2V1);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata, panda_i2c_1_boardinfo,
-                        ARRAY_SIZE(panda_i2c_1_boardinfo));
-        omap_register_i2c_bus(2, 400, NULL, 0);
-        /*
-         * Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz
-         */
-        omap_register_i2c_bus(3, 100, panda_i2c_eeprom,
-                                        ARRAY_SIZE(panda_i2c_eeprom));
-        omap_register_i2c_bus(4, 400, NULL, 0);
-        return 0;
-}
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        /* WLAN IRQ - GPIO 53 */
-        OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
-        /* WLAN POWER ENABLE - GPIO 43 */
-        OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* WLAN SDIO: MMC5 CMD */
-        OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC5 CLK */
-        OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* WLAN SDIO: MMC5 DAT[0-3] */
-        OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        /* gpio 0 - TFP410 PD */
-        OMAP4_MUX(KPD_COL1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE3),
-        /* dispc2_data23 */
-        OMAP4_MUX(USBB2_ULPITLL_STP, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data22 */
-        OMAP4_MUX(USBB2_ULPITLL_DIR, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data21 */
-        OMAP4_MUX(USBB2_ULPITLL_NXT, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data20 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT0, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data19 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT1, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data18 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT2, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data15 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data14 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data13 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data12 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data11 */
-        OMAP4_MUX(USBB2_ULPITLL_DAT7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data10 */
-        OMAP4_MUX(DPM_EMU3, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data9 */
-        OMAP4_MUX(DPM_EMU4, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data16 */
-        OMAP4_MUX(DPM_EMU5, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data17 */
-        OMAP4_MUX(DPM_EMU6, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_hsync */
-        OMAP4_MUX(DPM_EMU7, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_pclk */
-        OMAP4_MUX(DPM_EMU8, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_vsync */
-        OMAP4_MUX(DPM_EMU9, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_de */
-        OMAP4_MUX(DPM_EMU10, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data8 */
-        OMAP4_MUX(DPM_EMU11, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data7 */
-        OMAP4_MUX(DPM_EMU12, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data6 */
-        OMAP4_MUX(DPM_EMU13, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data5 */
-        OMAP4_MUX(DPM_EMU14, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data4 */
-        OMAP4_MUX(DPM_EMU15, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data3 */
-        OMAP4_MUX(DPM_EMU16, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data2 */
-        OMAP4_MUX(DPM_EMU17, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data1 */
-        OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* dispc2_data0 */
-        OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
-        /* NIRQ2 for twl6040 */
-        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
-                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
-        /* GPIO_127 for twl6040 */
-        OMAP4_MUX(HDQ_SIO, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
-        /* McPDM */
-        OMAP4_MUX(ABE_PDM_UL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_DL_DATA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_PDM_FRAME, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
-        OMAP4_MUX(ABE_PDM_LB_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_CLKS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        /* McBSP1 */
-        OMAP4_MUX(ABE_MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-        OMAP4_MUX(ABE_MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
-        OMAP4_MUX(ABE_MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT |
-                  OMAP_PULL_ENA),
-        OMAP4_MUX(ABE_MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
-
-        /* UART2 - BT/FM/GPS shared transport */
-        OMAP4_MUX(UART2_CTS,    OMAP_PIN_INPUT  | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_RTS,    OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_RX,     OMAP_PIN_INPUT  | OMAP_MUX_MODE0),
-        OMAP4_MUX(UART2_TX,     OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-#else
-#define board_mux       NULL
-#endif
-
-
-static void omap4_panda_init_rev(void)
-{
-        if (cpu_is_omap443x()) {
-                /* PandaBoard 4430 */
-                /* ASoC audio configuration */
-                panda_abe_audio_data.card_name = "PandaBoard";
-                panda_abe_audio_data.has_hsmic = 1;
-        } else {
-                /* PandaBoard ES */
-                /* ASoC audio configuration */
-                panda_abe_audio_data.card_name = "PandaBoardES";
-        }
-}
-
-static void __init omap4_panda_init(void)
-{
-        int package = OMAP_PACKAGE_CBS;
-        int ret;
-
-        if (omap_rev() == OMAP4430_REV_ES1_0)
-                package = OMAP_PACKAGE_CBL;
-        omap4_mux_init(board_mux, NULL, package);
-
-        omap_panda_wlan_data.irq = gpio_to_irq(GPIO_WIFI_IRQ);
-        ret = wl12xx_set_platform_data(&omap_panda_wlan_data);
-        if (ret)
-                pr_err("error setting wl12xx data: %d\n", ret);
-
-        omap4_panda_init_rev();
-        omap4_panda_i2c_init();
-        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
-        platform_device_register(&omap_vwlan_device);
-        omap_serial_init();
-        omap_sdrc_init(NULL, NULL);
-        omap4_twl6030_hsmmc_init(mmc);
-        omap4_ehci_init();
-        usb_bind_phy("musb-hdrc.2.auto", 0, "omap-usb2.3.auto");
-        usb_musb_init(&musb_board_data);
-        omap4_panda_display_init();
-}
-
-MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
-        /* Maintainer: David Anders - Texas Instruments Inc */
-        .atag_offset    = 0x100,
-        .smp            = smp_ops(omap4_smp_ops),
-        .reserve        = omap_reserve,
-        .map_io         = omap4_map_io,
-        .init_early     = omap4430_init_early,
-        .init_irq       = gic_init_irq,
-        .init_machine   = omap4_panda_init,
-        .init_late      = omap4430_init_late,
-        .init_time      = omap4_local_timer_init,
-        .restart        = omap44xx_restart,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4ca6b680aa72..5748b5d06c23 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -68,6 +68,7 @@
 
 #define OVERO_SMSC911X_CS      5
 #define OVERO_SMSC911X_GPIO    176
+#define OVERO_SMSC911X_NRESET  64
 #define OVERO_SMSC911X2_CS     4
 #define OVERO_SMSC911X2_GPIO   65
 
@@ -122,7 +123,7 @@ static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .id             = 0,
         .cs             = OVERO_SMSC911X_CS,
         .gpio_irq       = OVERO_SMSC911X_GPIO,
-        .gpio_reset     = -EINVAL,
+        .gpio_reset     = OVERO_SMSC911X_NRESET,
         .flags          = SMSC911X_USE_32BIT,
 };
 
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 18ca61e300b3..9c2dd102fbbb 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -553,6 +553,7 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_sdi", "omapdss_sdi.0"),
         /* Si4713 supply */
         REGULATOR_SUPPLY("vdd", "2-0063"),
         /* lis3lv02d */
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index af3544ce4f02..ba6534d7f155 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -431,15 +431,11 @@ DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
  *  - Driver code is not yet migrated to use hwmod/runtime pm
  *  - Modules outside kernel access (to disable them by default)
  *
- *     - debugss
  *     - mmu (gfx domain)
  *     - cefuse
  *     - usbotg_fck (its additional clock and not really a modulemode)
  *     - ieee5000
  */
-DEFINE_CLK_GATE(debugss_ick, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
 
 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
                 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
@@ -862,6 +858,69 @@ static struct clk_hw_omap wdt1_fck_hw = {
 
 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
 
+static const char *pwmss_clk_parents[] = {
+        "dpll_per_m2_ck",
+};
+
+static const struct clk_ops ehrpwm_tbclk_ops = {
+        .enable         = &omap2_dflt_clk_enable,
+        .disable        = &omap2_dflt_clk_disable,
+};
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS0_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS1_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
+                         NULL, NULL, 0,
+                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
+                         AM33XX_PWMSS2_TBCLKEN_SHIFT,
+                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
+
+/*
+ * debugss optional clocks
+ */
+DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
+                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
+
+static const char *stm_pmd_clock_mux_ck_parents[] = {
+        "dbg_sysclk_ck", "dbg_clka_ck",
+};
+
+DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
+               AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
+               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+               AM33XX_TRC_PMD_CLKSEL_SHIFT,
+               AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
+                   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+
+DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
+                   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+                   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
+                   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
+                   NULL);
+
 /*
  * clkdev
  */
@@ -899,7 +958,6 @@ static struct omap_clk am33xx_clks[] = {
         CLK("481cc000.d_can",   NULL,           &dcan0_fck),
         CLK(NULL,       "dcan1_fck",            &dcan1_fck),
         CLK("481d0000.d_can",   NULL,           &dcan1_fck),
-        CLK(NULL,       "debugss_ick",          &debugss_ick),
         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
         CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
         CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
@@ -942,6 +1000,16 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
         CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
         CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
+        CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
+        CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
+        CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
+        CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
+        CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
+        CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
+        CLK(NULL,       "clkout2_ck",           &clkout2_ck),
+        CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
+        CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
+        CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
 };
 
 
@@ -952,6 +1020,7 @@ static const char *enable_init_clks[] = {
         "l4hs_gclk",
         "l4fw_gclk",
         "l4ls_gclk",
+        "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
 };
 
 int __init am33xx_clk_init(void)
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 45cd26430d1f..334b76745900 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3329,11 +3329,7 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
         CLK(NULL,       "ts_fck",       &ts_fck),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
         CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
@@ -3343,7 +3339,6 @@ static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
         CLK(NULL,       "usbhost_ick",  &usbhost_ick),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
 };
 
 /*
@@ -3463,12 +3458,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
         CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
         CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck),
         CLK(NULL,       "aes2_ick",     &aes2_ick),
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 8f3bf4e50908..bbd6a3f717e6 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
 
 #include <linux/kernel.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/io.h>
 
 #include "clock.h"
 #include "clock36xx.h"
-
+#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
 
 /**
  * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
  */
 int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 {
-        struct clk_hw_omap *parent;
+        struct clk_divider *parent;
         struct clk_hw *parent_hw;
-        u32 dummy_v, orig_v, clksel_shift;
+        u32 dummy_v, orig_v;
         int ret;
 
         /* Clear PWRDN bit of HSDIVIDER */
         ret = omap2_dflt_clk_enable(clk);
 
         parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
-        parent = to_clk_hw_omap(parent_hw);
+        parent = to_clk_divider(parent_hw);
 
         /* Restore the dividers */
         if (!ret) {
-                clksel_shift = __ffs(parent->clksel_mask);
-                orig_v = __raw_readl(parent->clksel_reg);
+                orig_v = __raw_readl(parent->reg);
                 dummy_v = orig_v;
 
                 /* Write any other value different from the Read value */
-                dummy_v ^= (1 << clksel_shift);
-                __raw_writel(dummy_v, parent->clksel_reg);
+                dummy_v ^= (1 << parent->shift);
+                __raw_writel(dummy_v, parent->reg);
 
                 /* Write the original divider */
-                __raw_writel(orig_v, parent->clksel_reg);
+                __raw_writel(orig_v, parent->reg);
         }
 
         return ret;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 2da37656a693..daeecf1b89fa 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -216,6 +216,7 @@ extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
 extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
+extern void __init omap54xx_clockdomains_init(void);
 
 extern void clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains54xx_data.c b/arch/arm/mach-omap2/clockdomains54xx_data.c
new file mode 100644
index 000000000000..1a3c69d2e14c
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains54xx_data.c
@@ -0,0 +1,464 @@
+/*
+ * OMAP54XX Clock domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+
+#include "cm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu54xx.h"
+
+/* Static Dependencies for OMAP4 Clock Domains */
+
+static struct clkdm_dep c2c_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dsp_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep ipu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep mipiext_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+        { .clkdm_name = "abe_clkdm" },
+        { .clkdm_name = "dsp_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "emif_clkdm" },
+        { .clkdm_name = "gpu_clkdm" },
+        { .clkdm_name = "ipu_clkdm" },
+        { .clkdm_name = "iva_clkdm" },
+        { .clkdm_name = "l3init_clkdm" },
+        { .clkdm_name = "l3main1_clkdm" },
+        { .clkdm_name = "l3main2_clkdm" },
+        { .clkdm_name = "l4cfg_clkdm" },
+        { .clkdm_name = "l4per_clkdm" },
+        { .clkdm_name = "l4sec_clkdm" },
+        { .clkdm_name = "wkupaon_clkdm" },
+        { NULL },
+};
+
+static struct clockdomain l4sec_54xx_clkdm = {
+        .name             = "l4sec_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS,
+        .dep_bit          = OMAP54XX_L4SEC_STATDEP_SHIFT,
+        .wkdep_srcs       = l4sec_wkup_sleep_deps,
+        .sleepdep_srcs    = l4sec_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain iva_54xx_clkdm = {
+        .name             = "iva_clkdm",
+        .pwrdm            = { .name = "iva_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_IVA_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_IVA_IVA_CDOFFS,
+        .dep_bit          = OMAP54XX_IVA_STATDEP_SHIFT,
+        .wkdep_srcs       = iva_wkup_sleep_deps,
+        .sleepdep_srcs    = iva_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mipiext_54xx_clkdm = {
+        .name             = "mipiext_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS,
+        .wkdep_srcs       = mipiext_wkup_sleep_deps,
+        .sleepdep_srcs    = mipiext_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main2_54xx_clkdm = {
+        .name             = "l3main2_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN2_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3main1_54xx_clkdm = {
+        .name             = "l3main1_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+        .dep_bit          = OMAP54XX_L3MAIN1_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_54xx_clkdm = {
+        .name             = "custefuse_clkdm",
+        .pwrdm            = { .name = "custefuse_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CUSTEFUSE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_54xx_clkdm = {
+        .name             = "ipu_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_IPU_CDOFFS,
+        .dep_bit          = OMAP54XX_IPU_STATDEP_SHIFT,
+        .wkdep_srcs       = ipu_wkup_sleep_deps,
+        .sleepdep_srcs    = ipu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_54xx_clkdm = {
+        .name             = "l4cfg_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS,
+        .dep_bit          = OMAP54XX_L4CFG_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain abe_54xx_clkdm = {
+        .name             = "abe_clkdm",
+        .pwrdm            = { .name = "abe_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_ABE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS,
+        .dep_bit          = OMAP54XX_ABE_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dss_54xx_clkdm = {
+        .name             = "dss_clkdm",
+        .pwrdm            = { .name = "dss_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_DSS_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_DSS_DSS_CDOFFS,
+        .dep_bit          = OMAP54XX_DSS_STATDEP_SHIFT,
+        .wkdep_srcs       = dss_wkup_sleep_deps,
+        .sleepdep_srcs    = dss_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp_54xx_clkdm = {
+        .name             = "dsp_clkdm",
+        .pwrdm            = { .name = "dsp_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_DSP_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS,
+        .dep_bit          = OMAP54XX_DSP_STATDEP_SHIFT,
+        .wkdep_srcs       = dsp_wkup_sleep_deps,
+        .sleepdep_srcs    = dsp_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain c2c_54xx_clkdm = {
+        .name             = "c2c_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_C2C_CDOFFS,
+        .wkdep_srcs       = c2c_wkup_sleep_deps,
+        .sleepdep_srcs    = c2c_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l4per_54xx_clkdm = {
+        .name             = "l4per_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS,
+        .dep_bit          = OMAP54XX_L4PER_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_54xx_clkdm = {
+        .name             = "gpu_clkdm",
+        .pwrdm            = { .name = "gpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_GPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_GPU_GPU_CDOFFS,
+        .dep_bit          = OMAP54XX_GPU_STATDEP_SHIFT,
+        .wkdep_srcs       = gpu_wkup_sleep_deps,
+        .sleepdep_srcs    = gpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_54xx_clkdm = {
+        .name             = "wkupaon_clkdm",
+        .pwrdm            = { .name = "wkupaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_WKUPAON_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+        .dep_bit          = OMAP54XX_WKUPAON_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu0_54xx_clkdm = {
+        .name             = "mpu0_clkdm",
+        .pwrdm            = { .name = "cpu0_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C0_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu1_54xx_clkdm = {
+        .name             = "mpu1_clkdm",
+        .pwrdm            = { .name = "cpu1_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .cm_inst          = OMAP54XX_PRCM_MPU_CM_C1_INST,
+        .clkdm_offs       = OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain coreaon_54xx_clkdm = {
+        .name             = "coreaon_clkdm",
+        .pwrdm            = { .name = "coreaon_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_COREAON_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain mpu_54xx_clkdm = {
+        .name             = "mpu_clkdm",
+        .pwrdm            = { .name = "mpu_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_AON_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_AON_MPU_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+        .wkdep_srcs       = mpu_wkup_sleep_deps,
+        .sleepdep_srcs    = mpu_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3init_54xx_clkdm = {
+        .name             = "l3init_clkdm",
+        .pwrdm            = { .name = "l3init_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_L3INIT_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+        .dep_bit          = OMAP54XX_L3INIT_STATDEP_SHIFT,
+        .wkdep_srcs       = l3init_wkup_sleep_deps,
+        .sleepdep_srcs    = l3init_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dma_54xx_clkdm = {
+        .name             = "dma_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_DMA_CDOFFS,
+        .wkdep_srcs       = dma_wkup_sleep_deps,
+        .sleepdep_srcs    = dma_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_54xx_clkdm = {
+        .name             = "l3instr_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain emif_54xx_clkdm = {
+        .name             = "emif_clkdm",
+        .pwrdm            = { .name = "core_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CORE_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS,
+        .dep_bit          = OMAP54XX_EMIF_STATDEP_SHIFT,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_54xx_clkdm = {
+        .name             = "emu_clkdm",
+        .pwrdm            = { .name = "emu_pwrdm" },
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .cm_inst          = OMAP54XX_PRM_EMU_CM_INST,
+        .clkdm_offs       = OMAP54XX_PRM_EMU_CM_EMU_CDOFFS,
+        .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain cam_54xx_clkdm = {
+        .name             = "cam_clkdm",
+        .pwrdm            = { .name = "cam_pwrdm" },
+        .prcm_partition   = OMAP54XX_CM_CORE_PARTITION,
+        .cm_inst          = OMAP54XX_CM_CORE_CAM_INST,
+        .clkdm_offs       = OMAP54XX_CM_CORE_CAM_CAM_CDOFFS,
+        .wkdep_srcs       = cam_wkup_sleep_deps,
+        .sleepdep_srcs    = cam_wkup_sleep_deps,
+        .flags            = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_omap54xx[] __initdata = {
+        &l4sec_54xx_clkdm,
+        &iva_54xx_clkdm,
+        &mipiext_54xx_clkdm,
+        &l3main2_54xx_clkdm,
+        &l3main1_54xx_clkdm,
+        &custefuse_54xx_clkdm,
+        &ipu_54xx_clkdm,
+        &l4cfg_54xx_clkdm,
+        &abe_54xx_clkdm,
+        &dss_54xx_clkdm,
+        &dsp_54xx_clkdm,
+        &c2c_54xx_clkdm,
+        &l4per_54xx_clkdm,
+        &gpu_54xx_clkdm,
+        &wkupaon_54xx_clkdm,
+        &mpu0_54xx_clkdm,
+        &mpu1_54xx_clkdm,
+        &coreaon_54xx_clkdm,
+        &mpu_54xx_clkdm,
+        &l3init_54xx_clkdm,
+        &dma_54xx_clkdm,
+        &l3instr_54xx_clkdm,
+        &emif_54xx_clkdm,
+        &emu_54xx_clkdm,
+        &cam_54xx_clkdm,
+        NULL
+};
+
+void __init omap54xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&omap4_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_omap54xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
new file mode 100644
index 000000000000..e83b8e352b6e
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -0,0 +1,1737 @@
+/*
+ * OMAP54xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
+
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
+#define OMAP54XX_ABE_DYNDEP_SHIFT                                       3
+#define OMAP54XX_ABE_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_ABE_DYNDEP_MASK                                        (1 << 3)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_ABE_STATDEP_SHIFT                                      3
+#define OMAP54XX_ABE_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_ABE_STATDEP_MASK                                       (1 << 3)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
+ * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
+ */
+#define OMAP54XX_AUTO_DPLL_MODE_SHIFT                                   0
+#define OMAP54XX_AUTO_DPLL_MODE_WIDTH                                   0x3
+#define OMAP54XX_AUTO_DPLL_MODE_MASK                                    (0x7 << 0)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_C2C_DYNDEP_SHIFT                                       18
+#define OMAP54XX_C2C_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_C2C_DYNDEP_MASK                                        (1 << 18)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_C2C_STATDEP_SHIFT                                      18
+#define OMAP54XX_C2C_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_C2C_STATDEP_MASK                                       (1 << 18)
+
+/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CAM_DYNDEP_SHIFT                                       9
+#define OMAP54XX_CAM_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_CAM_DYNDEP_MASK                                        (1 << 9)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_CAM_STATDEP_SHIFT                                      9
+#define OMAP54XX_CAM_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_CAM_STATDEP_MASK                                       (1 << 9)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                        13
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK                         (1 << 13)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT                          12
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK                           (1 << 12)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK                             (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT                           9
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK                            (1 << 9)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT                          11
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK                           (1 << 11)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT                           8
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK                            (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT                           13
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK                            (1 << 13)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK                             (1 << 9)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK                             (1 << 10)
+
+/* Used by CM_C2C_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK                        (1 << 11)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK                          (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT                    12
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK                     (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT              14
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK               (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK                         (1 << 9)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT                   8
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK                    (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT                  9
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK                   (1 << 9)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT                             9
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK                              (1 << 9)
+
+/* Used by CM_DMA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_DSP_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT                            9
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK                             (1 << 9)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK                          (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK                         (1 << 10)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT                        8
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK                         (1 << 8)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK                          (1 << 11)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK                         (1 << 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK                          (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT                            10
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK                             (1 << 10)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT                       10
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK                        (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK                         (1 << 9)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT                         10
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK                          (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT                         8
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK                          (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT                       12
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK                        (1 << 12)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT                       11
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK                        (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT                   20
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK                    (1 << 20)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                        26
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK                         (1 << 26)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT                   21
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK                    (1 << 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                        27
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK                         (1 << 27)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT                   6
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK                    (1 << 6)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT                        7
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK                         (1 << 7)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT                            16
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH                            0x1
+#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK                             (1 << 16)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_IVA_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT                     12
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK                      (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT                  28
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK                   (1 << 28)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT                  29
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH                  0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK                   (1 << 29)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT                      8
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK                       (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT                      9
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK                       (1 << 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT      11
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH      0x1
+#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK       (1 << 11)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT               9
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK                (1 << 9)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK                       (1 << 10)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L3MAIN2_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT                       8
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK                        (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT                       9
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK                        (1 << 9)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT                     8
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK                      (1 << 8)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT                11
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK                 (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT                       2
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK                        (1 << 2)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT                           17
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK                            (1 << 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT                           18
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH                           0x1
+#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK                            (1 << 18)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT                             8
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK                              (1 << 8)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT                             14
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH                             0x1
+#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK                              (1 << 14)
+
+/* Used by CM_ABE_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT                     15
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK                      (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT                      3
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK                       (1 << 3)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT                      4
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK                       (1 << 4)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT                        15
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK                         (1 << 15)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT                        17
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK                         (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT                        18
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK                         (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT                        19
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK                         (1 << 19)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT                       19
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH                       0x1
+#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK                        (1 << 19)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK                     (1 << 11)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT                      10
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK                       (1 << 10)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT                     9
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK                      (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT                              8
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH                              0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK                               (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT                          15
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH                          0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK                           (1 << 15)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK                          (1 << 14)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT                        9
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK                         (1 << 9)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT                        10
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK                         (1 << 10)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT                         11
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK                          (1 << 11)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT                         12
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK                          (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT                         13
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK                          (1 << 13)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK                          (1 << 14)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                        22
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK                         (1 << 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                        23
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK                         (1 << 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                        24
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK                         (1 << 24)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK                      (1 << 10)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK                     (1 << 13)
+
+/* Used by CM_MIPIEXT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT               12
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH               0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK                (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT                     10
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH                     0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK                      (1 << 10)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT                    13
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK                     (1 << 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT                5
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH                0x1
+#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK                 (1 << 5)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT                         14
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH                         0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK                          (1 << 14)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT                      15
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK                       (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT                   31
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH                   0x1
+#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK                    (1 << 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                        30
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK                         (1 << 30)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT                      25
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH                      0x1
+#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK                       (1 << 25)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT                    11
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH                    0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK                     (1 << 11)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT                        12
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH                        0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK                         (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT              13
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH              0x1
+#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK               (1 << 13)
+
+/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT                                8
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH                                0x1
+#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK                                 (1 << 8)
+
+/*
+ * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SHIFT                                           24
+#define OMAP54XX_CLKSEL_WIDTH                                           0x1
+#define OMAP54XX_CLKSEL_MASK                                            (1 << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
+ * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
+ */
+#define OMAP54XX_CLKSEL_0_0_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_0_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_0_0_MASK                                        (1 << 0)
+
+/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
+#define OMAP54XX_CLKSEL_0_1_SHIFT                                       0
+#define OMAP54XX_CLKSEL_0_1_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_0_1_MASK                                        (0x3 << 0)
+
+/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
+#define OMAP54XX_CLKSEL_24_25_SHIFT                                     24
+#define OMAP54XX_CLKSEL_24_25_WIDTH                                     0x2
+#define OMAP54XX_CLKSEL_24_25_MASK                                      (0x3 << 24)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT                              26
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK                               (1 << 26)
+
+/* Used by CM_ABE_AESS_CLKCTRL */
+#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT                                 24
+#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_AESS_FCLK_MASK                                  (1 << 24)
+
+/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
+#define OMAP54XX_CLKSEL_DIV_SHIFT                                       25
+#define OMAP54XX_CLKSEL_DIV_WIDTH                                       0x1
+#define OMAP54XX_CLKSEL_DIV_MASK                                        (1 << 25)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT                             24
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH                             0x2
+#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK                              (0x3 << 24)
+
+/* Used by CM_CAM_FDIF_CLKCTRL */
+#define OMAP54XX_CLKSEL_FCLK_SHIFT                                      24
+#define OMAP54XX_CLKSEL_FCLK_WIDTH                                      0x1
+#define OMAP54XX_CLKSEL_FCLK_MASK                                       (1 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT                             24
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH                             0x1
+#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK                              (1 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT                              25
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH                              0x1
+#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK                               (1 << 25)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT                               26
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH                               0x1
+#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK                                (1 << 26)
+
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT                           26
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH                           0x2
+#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK                            (0x3 << 26)
+
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L3_SHIFT                                        4
+#define OMAP54XX_CLKSEL_L3_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L3_MASK                                         (1 << 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_CLKSEL_L3_1_1_SHIFT                                    1
+#define OMAP54XX_CLKSEL_L3_1_1_WIDTH                                    0x1
+#define OMAP54XX_CLKSEL_L3_1_1_MASK                                     (1 << 1)
+
+/* Used by CM_CLKSEL_CORE */
+#define OMAP54XX_CLKSEL_L4_SHIFT                                        8
+#define OMAP54XX_CLKSEL_L4_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_L4_MASK                                         (1 << 8)
+
+/* Used by CM_EMIF_EMIF1_CLKCTRL */
+#define OMAP54XX_CLKSEL_LL_SHIFT                                        24
+#define OMAP54XX_CLKSEL_LL_WIDTH                                        0x1
+#define OMAP54XX_CLKSEL_LL_MASK                                         (1 << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_CLKSEL_OPP_SHIFT                                       0
+#define OMAP54XX_CLKSEL_OPP_WIDTH                                       0x2
+#define OMAP54XX_CLKSEL_OPP_MASK                                        (0x3 << 0)
+
+/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
+#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT                                 24
+#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH                                 0x1
+#define OMAP54XX_CLKSEL_OPP_24_24_MASK                                  (1 << 24)
+
+/*
+ * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
+ * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_SHIFT                                    24
+#define OMAP54XX_CLKSEL_SOURCE_WIDTH                                    0x2
+#define OMAP54XX_CLKSEL_SOURCE_MASK                                     (0x3 << 24)
+
+/*
+ * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL
+ */
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT                        24
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH                        0x1
+#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK                         (1 << 24)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT                                   24
+#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P1_MASK                                    (1 << 24)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT                                   25
+#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH                                   0x1
+#define OMAP54XX_CLKSEL_UTMI_P2_MASK                                    (1 << 25)
+
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
+ * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
+ * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
+ * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_CLKST_SHIFT                                            9
+#define OMAP54XX_CLKST_WIDTH                                            0x1
+#define OMAP54XX_CLKST_MASK                                             (1 << 9)
+
+/*
+ * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
+ * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
+ * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
+ * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
+ * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
+ * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
+ * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
+ */
+#define OMAP54XX_CLKTRCTRL_SHIFT                                        0
+#define OMAP54XX_CLKTRCTRL_WIDTH                                        0x2
+#define OMAP54XX_CLKTRCTRL_MASK                                         (0x3 << 0)
+
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
+#define OMAP54XX_CLKX2ST_SHIFT                                          11
+#define OMAP54XX_CLKX2ST_WIDTH                                          0x1
+#define OMAP54XX_CLKX2ST_MASK                                           (1 << 11)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_COREAON_DYNDEP_SHIFT                                   16
+#define OMAP54XX_COREAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_COREAON_DYNDEP_MASK                                    (1 << 16)
+
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_COREAON_STATDEP_SHIFT                                  16
+#define OMAP54XX_COREAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_COREAON_STATDEP_MASK                                   (1 << 16)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT                                 17
+#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH                                 0x1
+#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK                                  (1 << 17)
+
+/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT                                17
+#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH                                0x1
+#define OMAP54XX_CUSTEFUSE_STATDEP_MASK                                 (1 << 17)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_CUSTOM_SHIFT                                           6
+#define OMAP54XX_CUSTOM_WIDTH                                           0x2
+#define OMAP54XX_CUSTOM_MASK                                            (0x3 << 6)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DCC_EN_SHIFT                                           22
+#define OMAP54XX_DCC_EN_WIDTH                                           0x1
+#define OMAP54XX_DCC_EN_MASK                                            (1 << 22)
+
+/*
+ * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
+ */
+#define OMAP54XX_CM_DEBUG_OUT_SHIFT                                     0
+#define OMAP54XX_CM_DEBUG_OUT_WIDTH                                     0xd
+#define OMAP54XX_CM_DEBUG_OUT_MASK                                      (0x1fff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                   0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                    (0xffffffff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
+ * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_8_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_8_WIDTH                                    0x9
+#define OMAP54XX_DEBUG_OUT_0_8_MASK                                     (0x1ff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
+ * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_4_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_4_WIDTH                                    0x5
+#define OMAP54XX_DEBUG_OUT_0_4_MASK                                     (0x1f << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
+ * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_5_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_5_WIDTH                                    0x6
+#define OMAP54XX_DEBUG_OUT_0_5_MASK                                     (0x3f << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
+ * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_10_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_10_WIDTH                                   0xb
+#define OMAP54XX_DEBUG_OUT_0_10_MASK                                    (0x7ff << 0)
+
+/*
+ * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
+ * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
+ */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                    0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                     (0x7f << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_19_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_19_WIDTH                                   0x14
+#define OMAP54XX_DEBUG_OUT_0_19_MASK                                    (0xfffff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                    0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                    0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                     (0x3ff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_26_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_26_WIDTH                                   0x1b
+#define OMAP54XX_DEBUG_OUT_0_26_MASK                                    (0x7ffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_13_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_13_WIDTH                                   0xe
+#define OMAP54XX_DEBUG_OUT_0_13_MASK                                    (0x3fff << 0)
+
+/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
+#define OMAP54XX_DEBUG_OUT_0_21_SHIFT                                   0
+#define OMAP54XX_DEBUG_OUT_0_21_WIDTH                                   0x16
+#define OMAP54XX_DEBUG_OUT_0_21_MASK                                    (0x3fffff << 0)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define OMAP54XX_DELTAMSTEP_SHIFT                                       0
+#define OMAP54XX_DELTAMSTEP_WIDTH                                       0x14
+#define OMAP54XX_DELTAMSTEP_MASK                                        (0xfffff << 0)
+
+/*
+ * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
+ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+#define OMAP54XX_DELTAMSTEP_0_20_SHIFT                                  0
+#define OMAP54XX_DELTAMSTEP_0_20_WIDTH                                  0x15
+#define OMAP54XX_DELTAMSTEP_0_20_MASK                                   (0x1fffff << 0)
+
+/*
+ * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
+ * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
+ * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
+ * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
+ */
+#define OMAP54XX_DIVHS_SHIFT                                            0
+#define OMAP54XX_DIVHS_WIDTH                                            0x6
+#define OMAP54XX_DIVHS_MASK                                             (0x3f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
+ * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
+ */
+#define OMAP54XX_DIVHS_0_4_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_4_WIDTH                                        0x5
+#define OMAP54XX_DIVHS_0_4_MASK                                         (0x1f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
+ * CM_DIV_M2_DPLL_USB
+ */
+#define OMAP54XX_DIVHS_0_6_SHIFT                                        0
+#define OMAP54XX_DIVHS_0_6_WIDTH                                        0x7
+#define OMAP54XX_DIVHS_0_6_MASK                                         (0x7f << 0)
+
+/* Used by CM_DLL_CTRL */
+#define OMAP54XX_DLL_OVERRIDE_SHIFT                                     0
+#define OMAP54XX_DLL_OVERRIDE_WIDTH                                     0x1
+#define OMAP54XX_DLL_OVERRIDE_MASK                                      (1 << 0)
+
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT                                 2
+#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH                                 0x1
+#define OMAP54XX_DLL_OVERRIDE_2_2_MASK                                  (1 << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DLL_RESET_SHIFT                                        3
+#define OMAP54XX_DLL_RESET_WIDTH                                        0x1
+#define OMAP54XX_DLL_RESET_MASK                                         (1 << 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT                                  23
+#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH                                  0x1
+#define OMAP54XX_DPLL_BYP_CLKSEL_MASK                                   (1 << 23)
+
+/* Used by CM_CLKSEL_DPLL_CORE */
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT                            20
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH                            0x1
+#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK                             (1 << 20)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT                                8
+#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH                                0x3
+#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK                                 (0x7 << 8)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT                                2
+#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH                                0x6
+#define OMAP54XX_DPLL_CORE_H12_DIV_MASK                                 (0x3f << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT                                 11
+#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH                                 0x5
+#define OMAP54XX_DPLL_CORE_M2_DIV_MASK                                  (0x1f << 11)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DIV_SHIFT                                         0
+#define OMAP54XX_DPLL_DIV_WIDTH                                         0x7
+#define OMAP54XX_DPLL_DIV_MASK                                          (0x7f << 0)
+
+/*
+ * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_DIV_0_7_SHIFT                                     0
+#define OMAP54XX_DPLL_DIV_0_7_WIDTH                                     0x8
+#define OMAP54XX_DPLL_DIV_0_7_MASK                                      (0xff << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT                               8
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH                               0x1
+#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK                                (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_EN_SHIFT                                          0
+#define OMAP54XX_DPLL_EN_WIDTH                                          0x3
+#define OMAP54XX_DPLL_EN_MASK                                           (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_LPMODE_EN_SHIFT                                   10
+#define OMAP54XX_DPLL_LPMODE_EN_WIDTH                                   0x1
+#define OMAP54XX_DPLL_LPMODE_EN_MASK                                    (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
+ * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
+ */
+#define OMAP54XX_DPLL_MULT_SHIFT                                        8
+#define OMAP54XX_DPLL_MULT_WIDTH                                        0xb
+#define OMAP54XX_DPLL_MULT_MASK                                         (0x7ff << 8)
+
+/*
+ * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
+ * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
+ */
+#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT                                8
+#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH                                0xc
+#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK                                 (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define OMAP54XX_DPLL_REGM4XEN_SHIFT                                    11
+#define OMAP54XX_DPLL_REGM4XEN_WIDTH                                    0x1
+#define OMAP54XX_DPLL_REGM4XEN_MASK                                     (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SD_DIV_SHIFT                                      24
+#define OMAP54XX_DPLL_SD_DIV_WIDTH                                      0x8
+#define OMAP54XX_DPLL_SD_DIV_MASK                                       (0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
+#define OMAP54XX_DPLL_SELFREQDCO_SHIFT                                  21
+#define OMAP54XX_DPLL_SELFREQDCO_WIDTH                                  0x1
+#define OMAP54XX_DPLL_SELFREQDCO_MASK                                   (1 << 21)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_ACK_SHIFT                                     13
+#define OMAP54XX_DPLL_SSC_ACK_WIDTH                                     0x1
+#define OMAP54XX_DPLL_SSC_ACK_MASK                                      (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT                              14
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH                              0x1
+#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK                               (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
+ * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
+ */
+#define OMAP54XX_DPLL_SSC_EN_SHIFT                                      12
+#define OMAP54XX_DPLL_SSC_EN_WIDTH                                      0x1
+#define OMAP54XX_DPLL_SSC_EN_MASK                                       (1 << 12)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_DSP_DYNDEP_SHIFT                                       1
+#define OMAP54XX_DSP_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSP_DYNDEP_MASK                                        (1 << 1)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSP_STATDEP_SHIFT                                      1
+#define OMAP54XX_DSP_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSP_STATDEP_MASK                                       (1 << 1)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_DSS_DYNDEP_SHIFT                                       8
+#define OMAP54XX_DSS_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_DSS_DYNDEP_MASK                                        (1 << 8)
+
+/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_DSS_STATDEP_SHIFT                                      8
+#define OMAP54XX_DSS_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_DSS_STATDEP_MASK                                       (1 << 8)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_EMIF_DYNDEP_SHIFT                                      4
+#define OMAP54XX_EMIF_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_EMIF_DYNDEP_MASK                                       (1 << 4)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_EMIF_STATDEP_SHIFT                                     4
+#define OMAP54XX_EMIF_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_EMIF_STATDEP_MASK                                      (1 << 4)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP54XX_FREQ_UPDATE_SHIFT                                      0
+#define OMAP54XX_FREQ_UPDATE_WIDTH                                      0x1
+#define OMAP54XX_FREQ_UPDATE_MASK                                       (1 << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_FUNC_SHIFT                                             16
+#define OMAP54XX_FUNC_WIDTH                                             0xc
+#define OMAP54XX_FUNC_MASK                                              (0xfff << 16)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT                                 0
+#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH                                 0x1
+#define OMAP54XX_GPMC_FREQ_UPDATE_MASK                                  (1 << 0)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_GPU_DYNDEP_SHIFT                                       10
+#define OMAP54XX_GPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_GPU_DYNDEP_MASK                                        (1 << 10)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_GPU_STATDEP_SHIFT                                      10
+#define OMAP54XX_GPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_GPU_STATDEP_MASK                                       (1 << 10)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_IDLEST_SHIFT                                           16
+#define OMAP54XX_IDLEST_WIDTH                                           0x2
+#define OMAP54XX_IDLEST_MASK                                            (0x3 << 16)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IPU_DYNDEP_SHIFT                                       0
+#define OMAP54XX_IPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IPU_DYNDEP_MASK                                        (1 << 0)
+
+/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_IPU_STATDEP_SHIFT                                      0
+#define OMAP54XX_IPU_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IPU_STATDEP_MASK                                       (1 << 0)
+
+/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_IVA_DYNDEP_SHIFT                                       2
+#define OMAP54XX_IVA_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_IVA_DYNDEP_MASK                                        (1 << 2)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_IVA_STATDEP_SHIFT                                      2
+#define OMAP54XX_IVA_STATDEP_WIDTH                                      0x1
+#define OMAP54XX_IVA_STATDEP_MASK                                       (1 << 2)
+
+/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L3INIT_DYNDEP_SHIFT                                    7
+#define OMAP54XX_L3INIT_DYNDEP_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_DYNDEP_MASK                                     (1 << 7)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3INIT_STATDEP_SHIFT                                   7
+#define OMAP54XX_L3INIT_STATDEP_WIDTH                                   0x1
+#define OMAP54XX_L3INIT_STATDEP_MASK                                    (1 << 7)
+
+/*
+ * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
+ * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT                                   5
+#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN1_DYNDEP_MASK                                    (1 << 5)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN1_STATDEP_SHIFT                                  5
+#define OMAP54XX_L3MAIN1_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN1_STATDEP_MASK                                   (1 << 5)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
+ * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
+ */
+#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT                                   6
+#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_L3MAIN2_DYNDEP_MASK                                    (1 << 6)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
+ * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
+ * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L3MAIN2_STATDEP_SHIFT                                  6
+#define OMAP54XX_L3MAIN2_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_L3MAIN2_STATDEP_MASK                                   (1 << 6)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_L4CFG_DYNDEP_SHIFT                                     12
+#define OMAP54XX_L4CFG_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4CFG_DYNDEP_MASK                                      (1 << 12)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4CFG_STATDEP_SHIFT                                    12
+#define OMAP54XX_L4CFG_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4CFG_STATDEP_MASK                                     (1 << 12)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP */
+#define OMAP54XX_L4PER_DYNDEP_SHIFT                                     13
+#define OMAP54XX_L4PER_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4PER_DYNDEP_MASK                                      (1 << 13)
+
+/*
+ * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
+ * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
+ * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4PER_STATDEP_SHIFT                                    13
+#define OMAP54XX_L4PER_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4PER_STATDEP_MASK                                     (1 << 13)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define OMAP54XX_L4SEC_DYNDEP_SHIFT                                     14
+#define OMAP54XX_L4SEC_DYNDEP_WIDTH                                     0x1
+#define OMAP54XX_L4SEC_DYNDEP_MASK                                      (1 << 14)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP
+ */
+#define OMAP54XX_L4SEC_STATDEP_SHIFT                                    14
+#define OMAP54XX_L4SEC_STATDEP_WIDTH                                    0x1
+#define OMAP54XX_L4SEC_STATDEP_MASK                                     (1 << 14)
+
+/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT                                   21
+#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_MIPIEXT_DYNDEP_MASK                                    (1 << 21)
+
+/* Used by CM_MPU_STATICDEP */
+#define OMAP54XX_MIPIEXT_STATDEP_SHIFT                                  21
+#define OMAP54XX_MIPIEXT_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_MIPIEXT_STATDEP_MASK                                   (1 << 21)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT                              8
+#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH                              0x3
+#define OMAP54XX_MODFREQDIV_EXPONENT_MASK                               (0x7 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT                              0
+#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH                              0x7
+#define OMAP54XX_MODFREQDIV_MANTISSA_MASK                               (0x7f << 0)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
+ * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
+ * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
+ * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
+ * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
+ * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
+ * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
+ * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
+ * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
+ * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
+ * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
+ * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
+ * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
+ * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
+ * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
+ * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
+ * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
+ * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
+ * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
+ * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
+ * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define OMAP54XX_MODULEMODE_SHIFT                                       0
+#define OMAP54XX_MODULEMODE_WIDTH                                       0x2
+#define OMAP54XX_MODULEMODE_MASK                                        (0x3 << 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_MPU_DYNDEP_SHIFT                                       19
+#define OMAP54XX_MPU_DYNDEP_WIDTH                                       0x1
+#define OMAP54XX_MPU_DYNDEP_MASK                                        (1 << 19)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT                              11
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK                               (1 << 11)
+
+/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT                          8
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH                          0x1
+#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK                           (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT                              9
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK                               (1 << 9)
+
+/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_CLK32K_MASK                                  (1 << 8)
+
+/* Used by CM_CAM_ISS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK                                 (1 << 8)
+
+/*
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
+ */
+#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_DBCLK_MASK                                   (1 << 8)
+
+/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK                                 (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT                                 8
+#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH                                 0x1
+#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK                                  (1 << 8)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT                                  8
+#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK0_MASK                                   (1 << 8)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT                                  9
+#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK1_MASK                                   (1 << 9)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT                                  10
+#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH                                  0x1
+#define OMAP54XX_OPTFCLKEN_FCLK2_MASK                                   (1 << 10)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT                            15
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK                             (1 << 15)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                        13
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK                         (1 << 13)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                        14
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK                         (1 << 14)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT                        7
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH                        0x1
+#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK                         (1 << 7)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                         11
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK                          (1 << 11)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                         12
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK                          (1 << 12)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT                         6
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH                         0x1
+#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK                          (1 << 6)
+
+/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT                             8
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH                             0x1
+#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK                              (1 << 8)
+
+/* Used by CM_L3INIT_SATA_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT                                8
+#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK                                 (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK                               (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT                               9
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH                               0x1
+#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK                                (1 << 9)
+
+/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT                            11
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK                             (1 << 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT                                10
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH                                0x1
+#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK                                 (1 << 10)
+
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT                              8
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH                              0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK                               (1 << 8)
+
+/* Used by CM_MIPIEXT_LLI_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT                           9
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH                           0x1
+#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK                            (1 << 9)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK                             (1 << 8)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK                             (1 << 9)
+
+/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK                             (1 << 10)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT                            8
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK                             (1 << 8)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT                            9
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK                             (1 << 9)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT                            10
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH                            0x1
+#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK                             (1 << 10)
+
+/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                           0
+#define OMAP54XX_OUTPUT_WIDTH                                           0x20
+#define OMAP54XX_OUTPUT_MASK                                            (0xffffffff << 0)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_PAD_CLKS_GATE_SHIFT                                    8
+#define OMAP54XX_PAD_CLKS_GATE_WIDTH                                    0x1
+#define OMAP54XX_PAD_CLKS_GATE_MASK                                     (1 << 8)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE1_COMPLETED_SHIFT                                 0
+#define OMAP54XX_PHASE1_COMPLETED_WIDTH                                 0x1
+#define OMAP54XX_PHASE1_COMPLETED_MASK                                  (1 << 0)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2A_COMPLETED_SHIFT                                1
+#define OMAP54XX_PHASE2A_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2A_COMPLETED_MASK                                 (1 << 1)
+
+/* Used by CM_RESTORE_ST */
+#define OMAP54XX_PHASE2B_COMPLETED_SHIFT                                2
+#define OMAP54XX_PHASE2B_COMPLETED_WIDTH                                0x1
+#define OMAP54XX_PHASE2B_COMPLETED_MASK                                 (1 << 2)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define OMAP54XX_PRESCAL_SHIFT                                          0
+#define OMAP54XX_PRESCAL_WIDTH                                          0x6
+#define OMAP54XX_PRESCAL_MASK                                           (0x3f << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_R_RTL_SHIFT                                            11
+#define OMAP54XX_R_RTL_WIDTH                                            0x5
+#define OMAP54XX_R_RTL_MASK                                             (0x1f << 11)
+
+/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OMAP54XX_SAR_MODE_SHIFT                                         4
+#define OMAP54XX_SAR_MODE_WIDTH                                         0x1
+#define OMAP54XX_SAR_MODE_MASK                                          (1 << 4)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_SCHEME_SHIFT                                           30
+#define OMAP54XX_SCHEME_WIDTH                                           0x2
+#define OMAP54XX_SCHEME_MASK                                            (0x3 << 30)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP54XX_SDMA_DYNDEP_SHIFT                                      11
+#define OMAP54XX_SDMA_DYNDEP_WIDTH                                      0x1
+#define OMAP54XX_SDMA_DYNDEP_MASK                                       (1 << 11)
+
+/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
+#define OMAP54XX_SDMA_STATDEP_SHIFT                                     11
+#define OMAP54XX_SDMA_STATDEP_WIDTH                                     0x1
+#define OMAP54XX_SDMA_STATDEP_MASK                                      (1 << 11)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL0_SHIFT                                             0
+#define OMAP54XX_SEL0_WIDTH                                             0x7
+#define OMAP54XX_SEL0_MASK                                              (0x7f << 0)
+
+/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL0_0_7_SHIFT                                         0
+#define OMAP54XX_SEL0_0_7_WIDTH                                         0x8
+#define OMAP54XX_SEL0_0_7_MASK                                          (0xff << 0)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL1_SHIFT                                             8
+#define OMAP54XX_SEL1_WIDTH                                             0x7
+#define OMAP54XX_SEL1_MASK                                              (0x7f << 8)
+
+/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT                              8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK                               (0xff << 8)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL2_SHIFT                                             16
+#define OMAP54XX_SEL2_WIDTH                                             0x7
+#define OMAP54XX_SEL2_MASK                                              (0x7f << 16)
+
+/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT                              16
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK                               (0xff << 16)
+
+/* Used by CM_CORE_AON_DEBUG_CFG */
+#define OMAP54XX_SEL3_SHIFT                                             24
+#define OMAP54XX_SEL3_WIDTH                                             0x7
+#define OMAP54XX_SEL3_MASK                                              (0x7f << 24)
+
+/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT                              24
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH                              0x8
+#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK                               (0xff << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT                                10
+#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH                                0x1
+#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK                                 (1 << 10)
+
+/*
+ * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
+ * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
+ * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
+ * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
+ * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
+ */
+#define OMAP54XX_STBYST_SHIFT                                           18
+#define OMAP54XX_STBYST_WIDTH                                           0x1
+#define OMAP54XX_STBYST_MASK                                            (1 << 18)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLK_SHIFT                                      0
+#define OMAP54XX_ST_DPLL_CLK_WIDTH                                      0x1
+#define OMAP54XX_ST_DPLL_CLK_MASK                                       (1 << 0)
+
+/*
+ * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
+ * CM_CLKDCOLDO_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT                                9
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH                                0x1
+#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK                                 (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_INIT_SHIFT                                     4
+#define OMAP54XX_ST_DPLL_INIT_WIDTH                                     0x1
+#define OMAP54XX_ST_DPLL_INIT_MASK                                      (1 << 4)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
+ * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
+ */
+#define OMAP54XX_ST_DPLL_MODE_SHIFT                                     1
+#define OMAP54XX_ST_DPLL_MODE_WIDTH                                     0x3
+#define OMAP54XX_ST_DPLL_MODE_MASK                                      (0x7 << 1)
+
+/* Used by CM_CLKSEL_SYS */
+#define OMAP54XX_SYS_CLKSEL_SHIFT                                       0
+#define OMAP54XX_SYS_CLKSEL_WIDTH                                       0x3
+#define OMAP54XX_SYS_CLKSEL_MASK                                        (0x7 << 0)
+
+/*
+ * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
+ */
+#define OMAP54XX_WINDOWSIZE_SHIFT                                       24
+#define OMAP54XX_WINDOWSIZE_WIDTH                                       0x4
+#define OMAP54XX_WINDOWSIZE_MASK                                        (0xf << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define OMAP54XX_WKUPAON_DYNDEP_SHIFT                                   15
+#define OMAP54XX_WKUPAON_DYNDEP_WIDTH                                   0x1
+#define OMAP54XX_WKUPAON_DYNDEP_MASK                                    (1 << 15)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define OMAP54XX_WKUPAON_STATDEP_SHIFT                                  15
+#define OMAP54XX_WKUPAON_STATDEP_WIDTH                                  0x1
+#define OMAP54XX_WKUPAON_STATDEP_MASK                                   (1 << 15)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_X_MAJOR_SHIFT                                          8
+#define OMAP54XX_X_MAJOR_WIDTH                                          0x3
+#define OMAP54XX_X_MAJOR_MASK                                           (0x7 << 8)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define OMAP54XX_Y_MINOR_SHIFT                                          0
+#define OMAP54XX_Y_MINOR_WIDTH                                          0x6
+#define OMAP54XX_Y_MINOR_MASK                                           (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index 1bc00dc4876c..5ae8fe39d6ee 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM1 base address */
 #define OMAP4430_CM1_BASE               0x4a004000
 
@@ -217,9 +219,4 @@
 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 
-/* Function prototypes */
-extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h
new file mode 100644
index 000000000000..90b3348e6672
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_54xx.h
@@ -0,0 +1,213 @@
+/*
+ * OMAP54xx CM1 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_54XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM1 base address */
+#define OMAP54XX_CM_CORE_AON_BASE               0x4a004000
+
+#define OMAP54XX_CM_CORE_AON_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
+
+/* CM_CORE_AON instances */
+#define OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_CM_CORE_AON_CKGEN_INST         0x0100
+#define OMAP54XX_CM_CORE_AON_MPU_INST           0x0300
+#define OMAP54XX_CM_CORE_AON_DSP_INST           0x0400
+#define OMAP54XX_CM_CORE_AON_ABE_INST           0x0500
+#define OMAP54XX_CM_CORE_AON_RESTORE_INST       0x0e00
+#define OMAP54XX_CM_CORE_AON_INSTR_INST         0x0f00
+
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS     0x0000
+#define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS     0x0000
+
+/* CM_CORE_AON */
+
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET                    0x0000
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET        0x0040
+#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL               OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET                   0x0080
+#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET                   0x0084
+#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET          0x0090
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET          0x0094
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET          0x0098
+#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET         0x009c
+#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET  0x00a0
+#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET          0x00a4
+#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET          0x00a8
+#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET      0x00ac
+#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET    0x00b0
+#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET          0x00b4
+#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET          0x00b8
+#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET         0x00bc
+#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET          0x00c0
+#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET          0x00c4
+#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET          0x00c8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET       0x00cc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET      0x00d0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET      0x00d4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET      0x00d8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET      0x00dc
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET        0x00e0
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET        0x00e4
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET       0x00e8
+#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET        0x00ec
+#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET      0x00f0
+
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_CLKSEL_CORE_OFFSET                          0x0000
+#define OMAP54XX_CM_CLKSEL_CORE                                 OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_ABE_OFFSET                           0x0008
+#define OMAP54XX_CM_CLKSEL_ABE                                  OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_DLL_CTRL_OFFSET                             0x0010
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET                    0x0020
+#define OMAP54XX_CM_CLKMODE_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET                     0x0024
+#define OMAP54XX_CM_IDLEST_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET                   0x0028
+#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET                     0x002c
+#define OMAP54XX_CM_CLKSEL_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET                     0x0030
+#define OMAP54XX_CM_DIV_M2_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET                     0x0034
+#define OMAP54XX_CM_DIV_M3_DPLL_CORE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET                    0x0038
+#define OMAP54XX_CM_DIV_H11_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET                    0x003c
+#define OMAP54XX_CM_DIV_H12_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET                    0x0040
+#define OMAP54XX_CM_DIV_H13_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET                    0x0044
+#define OMAP54XX_CM_DIV_H14_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET             0x0048
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET             0x004c
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET                    0x0050
+#define OMAP54XX_CM_DIV_H21_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET                    0x0054
+#define OMAP54XX_CM_DIV_H22_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET                    0x0058
+#define OMAP54XX_CM_DIV_H23_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET                    0x005c
+#define OMAP54XX_CM_DIV_H24_DPLL_CORE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET                     0x0060
+#define OMAP54XX_CM_CLKMODE_DPLL_MPU                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET                      0x0064
+#define OMAP54XX_CM_IDLEST_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET                    0x0068
+#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET                      0x006c
+#define OMAP54XX_CM_CLKSEL_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET                      0x0070
+#define OMAP54XX_CM_DIV_M2_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET              0x0088
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET              0x008c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET                      0x009c
+#define OMAP54XX_CM_BYPCLK_DPLL_MPU                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET                     0x00a0
+#define OMAP54XX_CM_CLKMODE_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET                      0x00a4
+#define OMAP54XX_CM_IDLEST_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET                    0x00a8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET                      0x00ac
+#define OMAP54XX_CM_CLKSEL_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET                     0x00b8
+#define OMAP54XX_CM_DIV_H11_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8)
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET                     0x00bc
+#define OMAP54XX_CM_DIV_H12_DPLL_IVA                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET              0x00c8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET              0x00cc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET                      0x00dc
+#define OMAP54XX_CM_BYPCLK_DPLL_IVA                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET                     0x00e0
+#define OMAP54XX_CM_CLKMODE_DPLL_ABE                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET                      0x00e4
+#define OMAP54XX_CM_IDLEST_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET                    0x00e8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET                      0x00ec
+#define OMAP54XX_CM_CLKSEL_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET                      0x00f0
+#define OMAP54XX_CM_DIV_M2_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET                      0x00f4
+#define OMAP54XX_CM_DIV_M3_DPLL_ABE                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET              0x0108
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET              0x010c
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET                  0x0160
+#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET                  0x0164
+#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET                      0x0170
+#define OMAP54XX_CM_RESTORE_ST_OFFSET                           0x0180
+
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_MPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_MPU_MPU_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL                     OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028)
+
+/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSP_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSP_DSP_CLKCTRL                             OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020)
+
+/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */
+#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET                   0x0020
+#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020)
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_ABE_AESS_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028)
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET                    0x0030
+#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030)
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET                     0x0038
+#define OMAP54XX_CM_ABE_DMIC_CLKCTRL                            OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038)
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET                    0x0040
+#define OMAP54XX_CM_ABE_MCASP_CLKCTRL                           OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040)
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET                   0x0048
+#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048)
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET                   0x0050
+#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050)
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET                   0x0058
+#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058)
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET                 0x0060
+#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL                        OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060)
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET                   0x0068
+#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068)
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET                   0x0070
+#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070)
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET                   0x0078
+#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078)
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET                   0x0080
+#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL                          OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080)
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET                0x0088
+#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL                       OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index b9de72da1a8e..ee5136d7cdda 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -25,6 +25,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H
 
+#include "cm_44xx_54xx.h"
+
 /* CM2 base address */
 #define OMAP4430_CM2_BASE               0x4a008000
 
@@ -449,9 +451,4 @@
 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET           0x0020
 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL               OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
 
-/* Function prototypes */
-extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
 #endif
diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h
new file mode 100644
index 000000000000..2683231b299b
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_54xx.h
@@ -0,0 +1,389 @@
+/*
+ * OMAP54xx CM2 instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H
+
+#include "cm_44xx_54xx.h"
+
+/* CM2 base address */
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+
+#define OMAP54XX_CM_CORE_REGADDR(inst, reg)                             \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
+
+/* CM_CORE instances */
+#define OMAP54XX_CM_CORE_OCP_SOCKET_INST        0x0000
+#define OMAP54XX_CM_CORE_CKGEN_INST             0x0100
+#define OMAP54XX_CM_CORE_COREAON_INST           0x0600
+#define OMAP54XX_CM_CORE_CORE_INST              0x0700
+#define OMAP54XX_CM_CORE_IVA_INST               0x1200
+#define OMAP54XX_CM_CORE_CAM_INST               0x1300
+#define OMAP54XX_CM_CORE_DSS_INST               0x1400
+#define OMAP54XX_CM_CORE_GPU_INST               0x1500
+#define OMAP54XX_CM_CORE_L3INIT_INST            0x1600
+#define OMAP54XX_CM_CORE_CUSTEFUSE_INST         0x1700
+#define OMAP54XX_CM_CORE_RESTORE_INST           0x1e00
+#define OMAP54XX_CM_CORE_INSTR_INST             0x1f00
+
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS         0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS            0x0000
+#define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS            0x0100
+#define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS                0x0200
+#define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS                0x0300
+#define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS               0x0400
+#define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS                0x0500
+#define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS              0x0600
+#define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS            0x0700
+#define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS            0x0800
+#define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS              0x0900
+#define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS              0x0a80
+#define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS                 0x0000
+#define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS           0x0000
+#define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS     0x0000
+
+/* CM_CORE */
+
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define OMAP54XX_REVISION_CM_CORE_OFFSET                        0x0000
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET            0x0040
+#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET                       0x0080
+#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET                       0x0084
+
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET                     0x0004
+#define OMAP54XX_CM_CLKSEL_USB_60MHZ                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004)
+#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET                     0x0040
+#define OMAP54XX_CM_CLKMODE_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040)
+#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET                      0x0044
+#define OMAP54XX_CM_IDLEST_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET                    0x0048
+#define OMAP54XX_CM_AUTOIDLE_DPLL_PER                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048)
+#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET                      0x004c
+#define OMAP54XX_CM_CLKSEL_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c)
+#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET                      0x0050
+#define OMAP54XX_CM_DIV_M2_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050)
+#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET                      0x0054
+#define OMAP54XX_CM_DIV_M3_DPLL_PER                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054)
+#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET                     0x0058
+#define OMAP54XX_CM_DIV_H11_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058)
+#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET                     0x005c
+#define OMAP54XX_CM_DIV_H12_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c)
+#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET                     0x0060
+#define OMAP54XX_CM_DIV_H13_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060)
+#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET                     0x0064
+#define OMAP54XX_CM_DIV_H14_DPLL_PER                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET              0x0068
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET              0x006c
+#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET                     0x0080
+#define OMAP54XX_CM_CLKMODE_DPLL_USB                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080)
+#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET                      0x0084
+#define OMAP54XX_CM_IDLEST_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET                    0x0088
+#define OMAP54XX_CM_AUTOIDLE_DPLL_USB                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088)
+#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET                      0x008c
+#define OMAP54XX_CM_CLKSEL_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c)
+#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET                      0x0090
+#define OMAP54XX_CM_DIV_M2_DPLL_USB                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET              0x00a8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET              0x00ac
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET                   0x00b4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET                 0x00c0
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET                  0x00c4
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET                0x00c8
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET                  0x00cc
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET                  0x00d0
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET          0x00e8
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET          0x00ec
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET               0x00f4
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4)
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET                 0x0100
+#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100)
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET                  0x0104
+#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104)
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET                0x0108
+#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108)
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET                  0x010c
+#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c)
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET                  0x0110
+#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110)
+#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET          0x0128
+#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET          0x012c
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET               0x0134
+#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134)
+
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET      0x0028
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET       0x0030
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL              OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030)
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET     0x0038
+#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038)
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET         0x0040
+#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL                OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040)
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0050
+#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050)
+
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET                   0x0008
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET            0x0020
+#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020)
+#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET                    0x0100
+#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET                   0x0108
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET            0x0120
+#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120)
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET                 0x0128
+#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128)
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET             0x0130
+#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130)
+#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET                        0x0200
+#define OMAP54XX_CM_IPU_STATICDEP_OFFSET                        0x0204
+#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET                       0x0208
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET                      0x0220
+#define OMAP54XX_CM_IPU_IPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220)
+#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET                        0x0300
+#define OMAP54XX_CM_DMA_STATICDEP_OFFSET                        0x0304
+#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET                       0x0308
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET               0x0320
+#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320)
+#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET                       0x0400
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET                     0x0420
+#define OMAP54XX_CM_EMIF_DMM_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420)
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET             0x0428
+#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428)
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET                   0x0430
+#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430)
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET                   0x0438
+#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438)
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET                0x0440
+#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440)
+#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET                        0x0500
+#define OMAP54XX_CM_C2C_STATICDEP_OFFSET                        0x0504
+#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET                       0x0508
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET                      0x0520
+#define OMAP54XX_CM_C2C_C2C_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520)
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET                0x0528
+#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528)
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET               0x0530
+#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530)
+#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET                      0x0600
+#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET                     0x0608
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET                 0x0620
+#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620)
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET               0x0628
+#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628)
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET                0x0630
+#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630)
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET                0x0638
+#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638)
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET               0x0640
+#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640)
+#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET                    0x0700
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET            0x0720
+#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720)
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET             0x0728
+#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728)
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET           0x0740
+#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740)
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET            0x0748
+#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748)
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET  0x0750
+#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750)
+#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET                    0x0800
+#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET                    0x0804
+#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET                   0x0808
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET                  0x0820
+#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820)
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET           0x0828
+#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828)
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET                 0x0830
+#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830)
+#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET                      0x0900
+#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET                     0x0908
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET                0x0928
+#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928)
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET                0x0930
+#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930)
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET                 0x0938
+#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938)
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET                 0x0940
+#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940)
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET                 0x0948
+#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948)
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET                 0x0950
+#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950)
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET                    0x0958
+#define OMAP54XX_CM_L4PER_ELM_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958)
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET                  0x0960
+#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960)
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET                  0x0968
+#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968)
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET                  0x0970
+#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970)
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET                  0x0978
+#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978)
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET                  0x0980
+#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980)
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET                  0x0988
+#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988)
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET                   0x09a0
+#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0)
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET                   0x09a8
+#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8)
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET                   0x09b0
+#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0)
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET                   0x09b8
+#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8)
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET                 0x09c0
+#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0)
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET                 0x09f0
+#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0)
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET                 0x09f8
+#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8)
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET                 0x0a00
+#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00)
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET                 0x0a08
+#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL                        OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08)
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET                  0x0a10
+#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10)
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET                  0x0a18
+#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18)
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET                   0x0a20
+#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20)
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET                   0x0a28
+#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28)
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET                  0x0a40
+#define OMAP54XX_CM_L4PER_UART1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40)
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET                  0x0a48
+#define OMAP54XX_CM_L4PER_UART2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48)
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET                  0x0a50
+#define OMAP54XX_CM_L4PER_UART3_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50)
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET                  0x0a58
+#define OMAP54XX_CM_L4PER_UART4_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58)
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET                   0x0a60
+#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60)
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET                   0x0a68
+#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68)
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET                  0x0a70
+#define OMAP54XX_CM_L4PER_UART5_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70)
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET                  0x0a78
+#define OMAP54XX_CM_L4PER_UART6_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78)
+#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET                      0x0a80
+#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET                      0x0a84
+#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET                     0x0a88
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET                   0x0aa0
+#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0)
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET                   0x0aa8
+#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8)
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET                0x0ab0
+#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0)
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET                   0x0ab8
+#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8)
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET                    0x0ac0
+#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL                           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0)
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET                0x0ac8
+#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL                       OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8)
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET             0x0ad8
+#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL                    OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8)
+
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_IVA_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_IVA_IVA_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020)
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET                      0x0028
+#define OMAP54XX_CM_IVA_SL2_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028)
+
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_CAM_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_CAM_ISS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020)
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET                     0x0028
+#define OMAP54XX_CM_CAM_FDIF_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028)
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET                      0x0030
+#define OMAP54XX_CM_CAM_CAL_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030)
+
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_DSS_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_DSS_DSS_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020)
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET                     0x0030
+#define OMAP54XX_CM_DSS_BB2D_CLKCTRL                            OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030)
+
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_GPU_STATICDEP_OFFSET                        0x0004
+#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET                      0x0020
+#define OMAP54XX_CM_GPU_GPU_CLKCTRL                             OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020)
+
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET                     0x0004
+#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET                    0x0008
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET                  0x0028
+#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028)
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET                  0x0030
+#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030)
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET                   0x0038
+#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL                          OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038)
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL                      OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040)
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET          0x0048
+#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL                 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048)
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET           0x0058
+#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL                  OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058)
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET            0x0068
+#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068)
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET        0x0078
+#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL               OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078)
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET                  0x0088
+#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL                         OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088)
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET              0x00e0
+#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET              0x00e8
+#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL                     OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET            0x00f0
+#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL                   OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0)
+
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET    0x0020
+#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL           OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+
+#endif
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 64f4bafe7bd9..9d1f4fcdebbb 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -383,7 +383,7 @@ extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
 extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
                                         u16 clkctrl_offs);
 extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
diff --git a/arch/arm/mach-omap2/cm_44xx_54xx.h b/arch/arm/mach-omap2/cm_44xx_54xx.h
new file mode 100644
index 000000000000..cbb211690321
--- /dev/null
+++ b/arch/arm/mach-omap2/cm_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx CM1/CM2 function prototypes
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_44XX_55XX_H
+
+/* CM1 Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* CM2 Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d555cf2459e1..72cab3f4f16d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -96,6 +96,7 @@ void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
 void am33xx_init_early(void);
+void am43xx_init_early(void);
 void omap4430_init_early(void);
 void omap5_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
@@ -237,8 +238,8 @@ extern void omap_do_wfi(void);
 
 #ifdef CONFIG_SMP
 /* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern void omap_secondary_startup_4460(void);
+extern void omap4_secondary_startup(void);
+extern void omap4460_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 2adb2683f074..31e0dfe4a4ea 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -249,6 +249,7 @@ void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
+                     soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
                      0;
 
         if (!offset) {
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index e6c328128a0a..f7d7c2ef1b40 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -358,6 +358,18 @@
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
+/* AM33XX PWMSS Control register */
+#define AM33XX_PWMSS_TBCLK_CLKCTRL                      0x664
+
+/* AM33XX  PWMSS Control bitfields */
+#define AM33XX_PWMSS0_TBCLKEN_SHIFT                     0
+#define AM33XX_PWMSS1_TBCLKEN_SHIFT                     1
+#define AM33XX_PWMSS2_TBCLKEN_SHIFT                     2
+
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE              0x604
+#define AM33XX_SGX_MASK                 BIT(29)
+
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 4269fc145698..aef96e45cb20 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -15,12 +15,13 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/gpio.h>
 #include <linux/slab.h>
 #include <linux/of.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/omap4-keypad.h>
-#include <linux/platform_data/omap_ocp2scp.h>
-#include <linux/usb/omap_control_usb.h>
+#include <linux/wl12xx.h>
+#include <linux/platform_data/mailbox-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
@@ -37,7 +38,6 @@
 #include "mux.h"
 #include "control.h"
 #include "devices.h"
-#include "dma.h"
 
 #define L3_MODULES_MAX_LEN 12
 #define L3_MODULES 3
@@ -253,49 +253,6 @@ static inline void omap_init_camera(void)
 #endif
 }
 
-#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
-static struct omap_control_usb_platform_data omap4_control_usb_pdata = {
-        .type = 1,
-};
-
-struct resource omap4_control_usb_res[] = {
-        {
-                .name   = "control_dev_conf",
-                .start  = 0x4a002300,
-                .end    = 0x4a002303,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "otghs_control",
-                .start  = 0x4a00233c,
-                .end    = 0x4a00233f,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device omap4_control_usb = {
-        .name = "omap-control-usb",
-        .id = -1,
-        .dev = {
-                .platform_data = &omap4_control_usb_pdata,
-        },
-        .num_resources = 2,
-        .resource = omap4_control_usb_res,
-};
-
-static inline void __init omap_init_control_usb(void)
-{
-        if (!cpu_is_omap44xx())
-                return;
-
-        if (platform_device_register(&omap4_control_usb))
-                pr_err("Error registering omap_control_usb device\n");
-}
-
-#else
-static inline void omap_init_control_usb(void) { }
-#endif /* CONFIG_OMAP_CONTROL_USB */
-
 int __init omap4_keyboard_init(struct omap4_keypad_platform_data
                         *sdp4430_keypad_data, struct omap_board_data *bdata)
 {
@@ -327,25 +284,31 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
         return 0;
 }
 
-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+#if defined(CONFIG_OMAP2PLUS_MBOX) || defined(CONFIG_OMAP2PLUS_MBOX_MODULE)
 static inline void __init omap_init_mbox(void)
 {
         struct omap_hwmod *oh;
         struct platform_device *pdev;
+        struct omap_mbox_pdata *pdata;
 
         oh = omap_hwmod_lookup("mailbox");
         if (!oh) {
                 pr_err("%s: unable to find hwmod\n", __func__);
                 return;
         }
+        if (!oh->dev_attr) {
+                pr_err("%s: hwmod doesn't have valid attrs\n", __func__);
+                return;
+        }
 
-        pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0);
+        pdata = (struct omap_mbox_pdata *)oh->dev_attr;
+        pdev = omap_device_build("omap-mailbox", -1, oh, pdata, sizeof(*pdata));
         WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
                                                 __func__, PTR_ERR(pdev));
 }
 #else
 static inline void omap_init_mbox(void) { }
-#endif /* CONFIG_OMAP_MBOX_FWK */
+#endif /* CONFIG_OMAP2PLUS_MBOX */
 
 static inline void omap_init_sti(void) {}
 
@@ -374,10 +337,8 @@ static void __init omap_init_mcpdm(void)
         struct platform_device *pdev;
 
         oh = omap_hwmod_lookup("mcpdm");
-        if (!oh) {
-                printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+        if (!oh)
                 return;
-        }
 
         pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
         WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
@@ -395,10 +356,8 @@ static void __init omap_init_dmic(void)
         struct platform_device *pdev;
 
         oh = omap_hwmod_lookup("dmic");
-        if (!oh) {
-                pr_err("Could not look up dmic hw_mod\n");
+        if (!oh)
                 return;
-        }
 
         pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
         WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
@@ -421,10 +380,8 @@ static void __init omap_init_hdmi_audio(void)
         struct platform_device *pdev;
 
         oh = omap_hwmod_lookup("dss_hdmi");
-        if (!oh) {
-                printk(KERN_ERR "Could not look up dss_hdmi hw_mod\n");
+        if (!oh)
                 return;
-        }
 
         pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
         WARN(IS_ERR(pdev),
@@ -557,80 +514,38 @@ static void omap_init_vout(void)
 static inline void omap_init_vout(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_OCP2SCP) || defined(CONFIG_OMAP_OCP2SCP_MODULE)
-static int count_ocp2scp_devices(struct omap_ocp2scp_dev *ocp2scp_dev)
-{
-        int cnt = 0;
+#if IS_ENABLED(CONFIG_WL12XX)
 
-        while (ocp2scp_dev->drv_name != NULL) {
-                cnt++;
-                ocp2scp_dev++;
-        }
-
-        return cnt;
-}
+static struct wl12xx_platform_data wl12xx __initdata;
 
-static void __init omap_init_ocp2scp(void)
+void __init omap_init_wl12xx_of(void)
 {
-        struct omap_hwmod       *oh;
-        struct platform_device  *pdev;
-        int                     bus_id = -1, dev_cnt = 0, i;
-        struct omap_ocp2scp_dev *ocp2scp_dev;
-        const char              *oh_name, *name;
-        struct omap_ocp2scp_platform_data *pdata;
-
-        if (!cpu_is_omap44xx())
-                return;
-
-        oh_name = "ocp2scp_usb_phy";
-        name    = "omap-ocp2scp";
-
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("%s: could not find omap_hwmod for %s\n", __func__,
-                                                                oh_name);
-                return;
-        }
+        int ret;
 
-        pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-        if (!pdata) {
-                pr_err("%s: No memory for ocp2scp pdata\n", __func__);
+        if (!of_have_populated_dt())
                 return;
-        }
 
-        ocp2scp_dev = oh->dev_attr;
-        dev_cnt = count_ocp2scp_devices(ocp2scp_dev);
-
-        if (!dev_cnt) {
-                pr_err("%s: No devices connected to ocp2scp\n", __func__);
-                kfree(pdata);
+        if (of_machine_is_compatible("ti,omap4-sdp")) {
+                wl12xx.board_ref_clock = WL12XX_REFCLOCK_26;
+                wl12xx.board_tcxo_clock = WL12XX_TCXOCLOCK_26;
+                wl12xx.irq = gpio_to_irq(53);
+        } else if (of_machine_is_compatible("ti,omap4-panda")) {
+                wl12xx.board_ref_clock = WL12XX_REFCLOCK_38;
+                wl12xx.irq = gpio_to_irq(53);
+        } else {
                 return;
         }
 
-        pdata->devices = kzalloc(sizeof(struct omap_ocp2scp_dev *)
-                                        * dev_cnt, GFP_KERNEL);
-        if (!pdata->devices) {
-                pr_err("%s: No memory for ocp2scp pdata devices\n", __func__);
-                kfree(pdata);
-                return;
-        }
-
-        for (i = 0; i < dev_cnt; i++, ocp2scp_dev++)
-                pdata->devices[i] = ocp2scp_dev;
-
-        pdata->dev_cnt  = dev_cnt;
-
-        pdev = omap_device_build(name, bus_id, oh, pdata, sizeof(*pdata));
-        if (IS_ERR(pdev)) {
-                pr_err("Could not build omap_device for %s %s\n",
-                                                name, oh_name);
-                kfree(pdata->devices);
-                kfree(pdata);
+        ret = wl12xx_set_platform_data(&wl12xx);
+        if (ret) {
+                pr_err("error setting wl12xx data: %d\n", ret);
                 return;
         }
 }
 #else
-static inline void omap_init_ocp2scp(void) { }
+static inline void omap_init_wl12xx_of(void)
+{
+}
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -651,17 +566,18 @@ static int __init omap2_init_devices(void)
         omap_init_mbox();
         /* If dtb is there, the devices will be created dynamically */
         if (!of_have_populated_dt()) {
-                omap_init_control_usb();
                 omap_init_dmic();
                 omap_init_mcpdm();
                 omap_init_mcspi();
                 omap_init_sham();
                 omap_init_aes();
+        } else {
+                /* These can be removed when bindings are done */
+                omap_init_wl12xx_of();
         }
         omap_init_sti();
         omap_init_rng();
         omap_init_vout();
-        omap_init_ocp2scp();
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
deleted file mode 100644
index 65f80cacf178..000000000000
--- a/arch/arm/mach-omap2/dma.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  OMAP2PLUS DMA channel definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __OMAP2PLUS_DMA_CHANNEL_H
-#define __OMAP2PLUS_DMA_CHANNEL_H
-
-
-/* DMA channels for 24xx */
-#define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
-#define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
-#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
-#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
-#define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
-#define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
-#define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
-#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
-#define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
-#define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
-#define OMAP24XX_DMA_UART1_RX           50      /* S_DMA_49 */
-#define OMAP24XX_DMA_UART2_TX           51      /* S_DMA_50 */
-#define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
-#define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
-#define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
-#define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
-#define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-
-#define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
-#define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
-
-/* Only for AM35xx */
-#define AM35XX_DMA_UART4_TX             54
-#define AM35XX_DMA_UART4_RX             55
-
-#endif /* __OMAP2PLUS_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index d9c27195caf0..662c7fd633cc 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -43,44 +43,6 @@ static struct platform_device gpmc_nand_device = {
         .resource       = gpmc_nand_resource,
 };
 
-static int omap2_nand_gpmc_retime(
-                                struct omap_nand_platform_data *gpmc_nand_data,
-                                struct gpmc_timings *gpmc_t)
-{
-        struct gpmc_timings t;
-        int err;
-
-        memset(&t, 0, sizeof(t));
-        t.sync_clk = gpmc_t->sync_clk;
-        t.cs_on = gpmc_t->cs_on;
-        t.adv_on = gpmc_t->adv_on;
-
-        /* Read */
-        t.adv_rd_off = gpmc_t->adv_rd_off;
-        t.oe_on  = t.adv_on;
-        t.access = gpmc_t->access;
-        t.oe_off = gpmc_t->oe_off;
-        t.cs_rd_off = gpmc_t->cs_rd_off;
-        t.rd_cycle = gpmc_t->rd_cycle;
-
-        /* Write */
-        t.adv_wr_off = gpmc_t->adv_wr_off;
-        t.we_on  = t.oe_on;
-        if (cpu_is_omap34xx()) {
-                t.wr_data_mux_bus = gpmc_t->wr_data_mux_bus;
-                t.wr_access = gpmc_t->wr_access;
-        }
-        t.we_off = gpmc_t->we_off;
-        t.cs_wr_off = gpmc_t->cs_wr_off;
-        t.wr_cycle = gpmc_t->wr_cycle;
-
-        err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
-        if (err)
-                return err;
-
-        return 0;
-}
-
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
         /* support only OMAP3 class */
@@ -131,7 +93,7 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                                 gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT);
 
         if (gpmc_t) {
-                err = omap2_nand_gpmc_retime(gpmc_nand_data, gpmc_t);
+                err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t);
                 if (err < 0) {
                         dev_err(dev, "Unable to set gpmc timings: %d\n", err);
                         return err;
@@ -140,8 +102,6 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                 if (gpmc_nand_data->of_node) {
                         gpmc_read_settings_dt(gpmc_nand_data->of_node, &s);
                 } else {
-                        s.device_nand = true;
-
                         /* Enable RD PIN Monitoring Reg */
                         if (gpmc_nand_data->dev_ready) {
                                 s.wait_on_read = true;
@@ -149,6 +109,8 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data,
                         }
                 }
 
+                s.device_nand = true;
+
                 if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
                         s.device_width = GPMC_DEVWIDTH_16BIT;
                 else
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 6c4da1254f53..1c7969e965d7 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -30,6 +30,7 @@
 #include <linux/of_mtd.h>
 #include <linux/of_device.h>
 #include <linux/mtd/nand.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/platform_data/mtd-nand-omap2.h>
 
@@ -155,6 +156,7 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 /* Define chip-selects as reserved by default until probe completes */
 static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
+static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 static unsigned int gpmc_nr_waitpins;
 static struct device *gpmc_dev;
 static int gpmc_irq;
@@ -521,8 +523,10 @@ static int gpmc_cs_remap(int cs, u32 base)
         int ret;
         u32 old_base, size;
 
-        if (cs > GPMC_CS_NUM)
+        if (cs > gpmc_cs_num) {
+                pr_err("%s: requested chip-select is disabled\n", __func__);
                 return -ENODEV;
+        }
         gpmc_cs_get_memconf(cs, &old_base, &size);
         if (base == old_base)
                 return 0;
@@ -545,9 +549,10 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
         struct resource *res = &gpmc_cs_mem[cs];
         int r = -1;
 
-        if (cs > GPMC_CS_NUM)
+        if (cs > gpmc_cs_num) {
+                pr_err("%s: requested chip-select is disabled\n", __func__);
                 return -ENODEV;
-
+        }
         size = gpmc_mem_align(size);
         if (size > (1 << GPMC_SECTION_SHIFT))
                 return -ENOMEM;
@@ -582,7 +587,7 @@ EXPORT_SYMBOL(gpmc_cs_request);
 void gpmc_cs_free(int cs)
 {
         spin_lock(&gpmc_mem_lock);
-        if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) {
+        if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
                 BUG();
                 spin_unlock(&gpmc_mem_lock);
@@ -777,7 +782,7 @@ static void gpmc_mem_exit(void)
 {
         int cs;
 
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+        for (cs = 0; cs < gpmc_cs_num; cs++) {
                 if (!gpmc_cs_mem_enabled(cs))
                         continue;
                 gpmc_cs_delete_mem(cs);
@@ -798,7 +803,7 @@ static void gpmc_mem_init(void)
         gpmc_mem_root.end = GPMC_MEM_END;
 
         /* Reserve all regions that has been set up by bootloader */
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+        for (cs = 0; cs < gpmc_cs_num; cs++) {
                 u32 base, size;
 
                 if (!gpmc_cs_mem_enabled(cs))
@@ -1245,7 +1250,6 @@ void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
 
         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
-        p->device_nand = of_property_read_bool(np, "gpmc,device-nand");
         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
 
@@ -1345,6 +1349,13 @@ static const char * const nand_ecc_opts[] = {
         [OMAP_ECC_BCH8_CODE_HW]                 = "bch8",
 };
 
+static const char * const nand_xfer_types[] = {
+        [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
+        [NAND_OMAP_POLLED]                      = "polled",
+        [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
+        [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
+};
+
 static int gpmc_probe_nand_child(struct platform_device *pdev,
                                  struct device_node *child)
 {
@@ -1374,6 +1385,13 @@ static int gpmc_probe_nand_child(struct platform_device *pdev,
                                 break;
                         }
 
+        if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
+                for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
+                        if (!strcasecmp(s, nand_xfer_types[val])) {
+                                gpmc_nand_data->xfer_type = val;
+                                break;
+                        }
+
         val = of_get_nand_bus_width(child);
         if (val == 16)
                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
@@ -1513,6 +1531,20 @@ static int gpmc_probe_dt(struct platform_device *pdev)
         if (!of_id)
                 return 0;
 
+        ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
+                                   &gpmc_cs_num);
+        if (ret < 0) {
+                pr_err("%s: number of chip-selects not defined\n", __func__);
+                return ret;
+        } else if (gpmc_cs_num < 1) {
+                pr_err("%s: all chip-selects are disabled\n", __func__);
+                return -EINVAL;
+        } else if (gpmc_cs_num > GPMC_CS_NUM) {
+                pr_err("%s: number of supported chip-selects cannot be > %d\n",
+                                         __func__, GPMC_CS_NUM);
+                return -EINVAL;
+        }
+
         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
                                    &gpmc_nr_waitpins);
         if (ret < 0) {
@@ -1577,7 +1609,8 @@ static int gpmc_probe(struct platform_device *pdev)
                 return PTR_ERR(gpmc_l3_clk);
         }
 
-        clk_prepare_enable(gpmc_l3_clk);
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
 
         gpmc_dev = &pdev->dev;
 
@@ -1610,12 +1643,14 @@ static int gpmc_probe(struct platform_device *pdev)
         /* Now the GPMC is initialised, unreserve the chip-selects */
         gpmc_cs_map = 0;
 
-        if (!pdev->dev.of_node)
+        if (!pdev->dev.of_node) {
+                gpmc_cs_num      = GPMC_CS_NUM;
                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
+        }
 
         rc = gpmc_probe_dt(pdev);
         if (rc < 0) {
-                clk_disable_unprepare(gpmc_l3_clk);
+                pm_runtime_put_sync(&pdev->dev);
                 clk_put(gpmc_l3_clk);
                 dev_err(gpmc_dev, "failed to probe DT parameters\n");
                 return rc;
@@ -1628,10 +1663,30 @@ static int gpmc_remove(struct platform_device *pdev)
 {
         gpmc_free_irq();
         gpmc_mem_exit();
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
         gpmc_dev = NULL;
         return 0;
 }
 
+#ifdef CONFIG_PM_SLEEP
+static int gpmc_suspend(struct device *dev)
+{
+        omap3_gpmc_save_context();
+        pm_runtime_put_sync(dev);
+        return 0;
+}
+
+static int gpmc_resume(struct device *dev)
+{
+        pm_runtime_get_sync(dev);
+        omap3_gpmc_restore_context();
+        return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
+
 static struct platform_driver gpmc_driver = {
         .probe          = gpmc_probe,
         .remove         = gpmc_remove,
@@ -1639,6 +1694,7 @@ static struct platform_driver gpmc_driver = {
                 .name   = DEVICE_NAME,
                 .owner  = THIS_MODULE,
                 .of_match_table = of_match_ptr(gpmc_dt_ids),
+                .pm     = &gpmc_pm_ops,
         },
 };
 
@@ -1701,7 +1757,6 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev)
         return IRQ_HANDLED;
 }
 
-#ifdef CONFIG_ARCH_OMAP3
 static struct omap3_gpmc_regs gpmc_context;
 
 void omap3_gpmc_save_context(void)
@@ -1715,7 +1770,7 @@ void omap3_gpmc_save_context(void)
         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
-        for (i = 0; i < GPMC_CS_NUM; i++) {
+        for (i = 0; i < gpmc_cs_num; i++) {
                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
                 if (gpmc_context.cs_context[i].is_valid) {
                         gpmc_context.cs_context[i].config1 =
@@ -1747,7 +1802,7 @@ void omap3_gpmc_restore_context(void)
         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
-        for (i = 0; i < GPMC_CS_NUM; i++) {
+        for (i = 0; i < gpmc_cs_num; i++) {
                 if (gpmc_context.cs_context[i].is_valid) {
                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
                                 gpmc_context.cs_context[i].config1);
@@ -1766,4 +1821,3 @@ void omap3_gpmc_restore_context(void)
                 }
         }
 }
-#endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2ef1f8714fcf..07d4c7b35754 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -29,7 +29,6 @@
 
 static u16 control_pbias_offset;
 static u16 control_devconf1_offset;
-static u16 control_mmc1;
 
 #define HSMMC_NAME_LEN  9
 
@@ -121,57 +120,6 @@ static void omap_hsmmc1_after_set_reg(struct device *dev, int slot,
         }
 }
 
-static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
-                                  int power_on, int vdd)
-{
-        u32 reg;
-
-        /*
-         * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
-         * card with Vcc regulator (from twl4030 or whatever).  OMAP has both
-         * 1.8V and 3.0V modes, controlled by the PBIAS register.
-         */
-        reg = omap4_ctrl_pad_readl(control_pbias_offset);
-        reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-                OMAP4_MMC1_PWRDNZ_MASK |
-                OMAP4_MMC1_PBIASLITE_VMODE_MASK);
-        omap4_ctrl_pad_writel(reg, control_pbias_offset);
-}
-
-static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
-                                 int power_on, int vdd)
-{
-        u32 reg;
-        unsigned long timeout;
-
-        if (power_on) {
-                reg = omap4_ctrl_pad_readl(control_pbias_offset);
-                reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
-                if ((1 << vdd) <= MMC_VDD_165_195)
-                        reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-                else
-                        reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
-                reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
-                        OMAP4_MMC1_PWRDNZ_MASK);
-                omap4_ctrl_pad_writel(reg, control_pbias_offset);
-
-                timeout = jiffies + msecs_to_jiffies(5);
-                do {
-                        reg = omap4_ctrl_pad_readl(control_pbias_offset);
-                        if (!(reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK))
-                                break;
-                        usleep_range(100, 200);
-                } while (!time_after(jiffies, timeout));
-
-                if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
-                        pr_err("Pbias Voltage is not same as LDO\n");
-                        /* Caution : On VMODE_ERROR Power Down MMC IO */
-                        reg &= ~(OMAP4_MMC1_PWRDNZ_MASK);
-                        omap4_ctrl_pad_writel(reg, control_pbias_offset);
-                }
-        }
-}
-
 static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
 {
         u32 reg;
@@ -317,11 +265,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         mmc->slots[0].pm_caps = c->pm_caps;
         mmc->slots[0].internal_clock = !c->ext_clock;
         mmc->max_freq = c->max_freq;
-        if (cpu_is_omap44xx())
-                mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
-        else
-                mmc->reg_offset = 0;
-
+        mmc->reg_offset = 0;
         mmc->get_context_loss_count = hsmmc_get_context_loss;
 
         mmc->slots[0].switch_pin = c->gpio_cd;
@@ -368,24 +312,14 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         if (!soc_is_am35xx())
                 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
 
-        if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
-                mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
-
         switch (c->mmc) {
         case 1:
                 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
                         /* on-chip level shifting via PBIAS0/PBIAS1 */
-                        if (cpu_is_omap44xx()) {
-                                mmc->slots[0].before_set_reg =
-                                                omap4_hsmmc1_before_set_reg;
-                                mmc->slots[0].after_set_reg =
-                                                omap4_hsmmc1_after_set_reg;
-                        } else {
-                                mmc->slots[0].before_set_reg =
-                                                omap_hsmmc1_before_set_reg;
-                                mmc->slots[0].after_set_reg =
-                                                omap_hsmmc1_after_set_reg;
-                        }
+                        mmc->slots[0].before_set_reg =
+                                        omap_hsmmc1_before_set_reg;
+                        mmc->slots[0].after_set_reg =
+                                        omap_hsmmc1_after_set_reg;
                 }
 
                 if (soc_is_am35xx())
@@ -563,34 +497,17 @@ free_mmc:
 
 void __init omap_hsmmc_init(struct omap2_hsmmc_info *controllers)
 {
-        u32 reg;
-
         if (omap_hsmmc_done)
                 return;
 
         omap_hsmmc_done = 1;
 
-        if (!cpu_is_omap44xx()) {
-                if (cpu_is_omap2430()) {
-                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-                } else {
-                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-                }
+        if (cpu_is_omap2430()) {
+                control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+                control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
         } else {
-                control_pbias_offset =
-                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
-                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
-                reg = omap4_ctrl_pad_readl(control_mmc1);
-                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
-                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
-                reg |= (OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK |
-                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
-                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
-                omap4_ctrl_pad_writel(reg, control_mmc1);
+                control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+                control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
         }
 
         for (; controllers->mmc; controllers++)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1272c41d4749..2dc62a25f2c3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -55,7 +55,7 @@ int omap_type(void)
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-        } else if (soc_is_am33xx()) {
+        } else if (soc_is_am33xx() || soc_is_am43xx()) {
                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
@@ -209,6 +209,8 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = "TI816X";
         } else if (soc_is_am335x()) {
                 cpu_name =  "AM335X";
+        } else if (soc_is_am437x()) {
+                cpu_name =  "AM437x";
         } else if (cpu_is_ti814x()) {
                 cpu_name = "TI814X";
         } else if (omap3_has_iva() && omap3_has_sgx()) {
@@ -302,6 +304,19 @@ void __init ti81xx_check_features(void)
         omap3_cpuinfo();
 }
 
+void __init am33xx_check_features(void)
+{
+        u32 status;
+
+        omap_features = OMAP3_HAS_NEON;
+
+        status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+        if (status & AM33XX_SGX_MASK)
+                omap_features |= OMAP3_HAS_SGX;
+
+        omap3_cpuinfo();
+}
+
 void __init omap3xxx_check_revision(void)
 {
         const char *cpu_rev;
@@ -405,11 +420,18 @@ void __init omap3xxx_check_revision(void)
                         cpu_rev = "1.0";
                         break;
                 case 1:
-                /* FALLTHROUGH */
-                default:
                         omap_revision = TI8168_REV_ES1_1;
                         cpu_rev = "1.1";
                         break;
+                case 2:
+                        omap_revision = TI8168_REV_ES2_0;
+                        cpu_rev = "2.0";
+                        break;
+                case 3:
+                        /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8168_REV_ES2_1;
+                        cpu_rev = "2.1";
                 }
                 break;
         case 0xb944:
@@ -430,6 +452,10 @@ void __init omap3xxx_check_revision(void)
                         break;
                 }
                 break;
+        case 0xb98c:
+                omap_revision = AM437X_REV_ES1_0;
+                cpu_rev = "1.0";
+                break;
         case 0xb8f2:
                 switch (rev) {
                 case 0:
@@ -601,7 +627,7 @@ void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 
 #ifdef CONFIG_SOC_BUS
 
-static const char const *omap_types[] = {
+static const char * const omap_types[] = {
         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 09abf99e9e57..fe3253a100e7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -202,7 +202,7 @@ static struct map_desc omapti81xx_io_desc[] __initdata = {
 };
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 static struct map_desc omapam33xx_io_desc[] __initdata = {
         {
                 .virtual        = L4_34XX_VIRT,
@@ -318,7 +318,7 @@ void __init ti81xx_map_io(void)
 }
 #endif
 
-#ifdef CONFIG_SOC_AM33XX
+#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 void __init am33xx_map_io(void)
 {
         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
@@ -576,8 +576,7 @@ void __init am33xx_init_early(void)
         omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
         omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
         omap3xxx_check_revision();
-        ti81xx_check_features();
-        am33xx_voltagedomains_init();
+        am33xx_check_features();
         am33xx_powerdomains_init();
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
@@ -586,6 +585,19 @@ void __init am33xx_init_early(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+void __init am43xx_init_early(void)
+{
+        omap2_set_globals_tap(AM335X_CLASS,
+                              AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
+        omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+                                  NULL);
+        omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
+        omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
+        omap3xxx_check_revision();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
@@ -631,7 +643,13 @@ void __init omap5_init_early(void)
         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
         omap_prm_base_init();
         omap_cm_base_init();
+        omap44xx_prm_init();
         omap5xxx_check_revision();
+        omap54xx_voltagedomains_init();
+        omap54xx_powerdomains_init();
+        omap54xx_clockdomains_init();
+        omap54xx_hwmod_init();
+        omap_hwmod_init_postsetup();
 }
 #endif
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
deleted file mode 100644
index 0b080267b7f6..000000000000
--- a/arch/arm/mach-omap2/mailbox.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- * Mailbox reservation modules for OMAP2/3
- *
- * Copyright (C) 2006-2009 Nokia Corporation
- * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *        and  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/pm_runtime.h>
-
-#include <plat/mailbox.h>
-
-#include "soc.h"
-
-#define MAILBOX_REVISION                0x000
-#define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
-#define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
-#define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
-#define MAILBOX_IRQSTATUS(u)            (0x100 + 8 * (u))
-#define MAILBOX_IRQENABLE(u)            (0x104 + 8 * (u))
-
-#define OMAP4_MAILBOX_IRQSTATUS(u)      (0x104 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u)      (0x108 + 0x10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u)  (0x10c + 0x10 * (u))
-
-#define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
-#define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
-
-#define MBOX_REG_SIZE                   0x120
-
-#define OMAP4_MBOX_REG_SIZE             0x130
-
-#define MBOX_NR_REGS                    (MBOX_REG_SIZE / sizeof(u32))
-#define OMAP4_MBOX_NR_REGS              (OMAP4_MBOX_REG_SIZE / sizeof(u32))
-
-static void __iomem *mbox_base;
-
-struct omap_mbox2_fifo {
-        unsigned long msg;
-        unsigned long fifo_stat;
-        unsigned long msg_stat;
-};
-
-struct omap_mbox2_priv {
-        struct omap_mbox2_fifo tx_fifo;
-        struct omap_mbox2_fifo rx_fifo;
-        unsigned long irqenable;
-        unsigned long irqstatus;
-        u32 newmsg_bit;
-        u32 notfull_bit;
-        u32 ctx[OMAP4_MBOX_NR_REGS];
-        unsigned long irqdisable;
-};
-
-static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
-                                  omap_mbox_type_t irq);
-
-static inline unsigned int mbox_read_reg(size_t ofs)
-{
-        return __raw_readl(mbox_base + ofs);
-}
-
-static inline void mbox_write_reg(u32 val, size_t ofs)
-{
-        __raw_writel(val, mbox_base + ofs);
-}
-
-/* Mailbox H/W preparations */
-static int omap2_mbox_startup(struct omap_mbox *mbox)
-{
-        u32 l;
-
-        pm_runtime_enable(mbox->dev->parent);
-        pm_runtime_get_sync(mbox->dev->parent);
-
-        l = mbox_read_reg(MAILBOX_REVISION);
-        pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
-
-        return 0;
-}
-
-static void omap2_mbox_shutdown(struct omap_mbox *mbox)
-{
-        pm_runtime_put_sync(mbox->dev->parent);
-        pm_runtime_disable(mbox->dev->parent);
-}
-
-/* Mailbox FIFO handle functions */
-static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
-        return (mbox_msg_t) mbox_read_reg(fifo->msg);
-}
-
-static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-        mbox_write_reg(msg, fifo->msg);
-}
-
-static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
-        return (mbox_read_reg(fifo->msg_stat) == 0);
-}
-
-static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
-{
-        struct omap_mbox2_fifo *fifo =
-                &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
-        return mbox_read_reg(fifo->fifo_stat);
-}
-
-/* Mailbox IRQ handle functions */
-static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-
-        l = mbox_read_reg(p->irqenable);
-        l |= bit;
-        mbox_write_reg(l, p->irqenable);
-}
-
-static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-
-        if (!cpu_is_omap44xx())
-                bit = mbox_read_reg(p->irqdisable) & ~bit;
-
-        mbox_write_reg(bit, p->irqdisable);
-}
-
-static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-
-        mbox_write_reg(bit, p->irqstatus);
-
-        /* Flush posted write for irq status to avoid spurious interrupts */
-        mbox_read_reg(p->irqstatus);
-}
-
-static int omap2_mbox_is_irq(struct omap_mbox *mbox,
-                omap_mbox_type_t irq)
-{
-        struct omap_mbox2_priv *p = mbox->priv;
-        u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
-        u32 enable = mbox_read_reg(p->irqenable);
-        u32 status = mbox_read_reg(p->irqstatus);
-
-        return (int)(enable & status & bit);
-}
-
-static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
-{
-        int i;
-        struct omap_mbox2_priv *p = mbox->priv;
-        int nr_regs;
-        if (cpu_is_omap44xx())
-                nr_regs = OMAP4_MBOX_NR_REGS;
-        else
-                nr_regs = MBOX_NR_REGS;
-        for (i = 0; i < nr_regs; i++) {
-                p->ctx[i] = mbox_read_reg(i * sizeof(u32));
-
-                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
-                        i, p->ctx[i]);
-        }
-}
-
-static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
-{
-        int i;
-        struct omap_mbox2_priv *p = mbox->priv;
-        int nr_regs;
-        if (cpu_is_omap44xx())
-                nr_regs = OMAP4_MBOX_NR_REGS;
-        else
-                nr_regs = MBOX_NR_REGS;
-        for (i = 0; i < nr_regs; i++) {
-                mbox_write_reg(p->ctx[i], i * sizeof(u32));
-
-                dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
-                        i, p->ctx[i]);
-        }
-}
-
-static struct omap_mbox_ops omap2_mbox_ops = {
-        .type           = OMAP_MBOX_TYPE2,
-        .startup        = omap2_mbox_startup,
-        .shutdown       = omap2_mbox_shutdown,
-        .fifo_read      = omap2_mbox_fifo_read,
-        .fifo_write     = omap2_mbox_fifo_write,
-        .fifo_empty     = omap2_mbox_fifo_empty,
-        .fifo_full      = omap2_mbox_fifo_full,
-        .enable_irq     = omap2_mbox_enable_irq,
-        .disable_irq    = omap2_mbox_disable_irq,
-        .ack_irq        = omap2_mbox_ack_irq,
-        .is_irq         = omap2_mbox_is_irq,
-        .save_ctx       = omap2_mbox_save_ctx,
-        .restore_ctx    = omap2_mbox_restore_ctx,
-};
-
-/*
- * MAILBOX 0: ARM -> DSP,
- * MAILBOX 1: ARM <- DSP.
- * MAILBOX 2: ARM -> IVA,
- * MAILBOX 3: ARM <- IVA.
- */
-
-/* FIXME: the following structs should be filled automatically by the user id */
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP2)
-/* DSP */
-static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(0),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(0),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(1),
-                .msg_stat       = MAILBOX_MSGSTATUS(1),
-        },
-        .irqenable      = MAILBOX_IRQENABLE(0),
-        .irqstatus      = MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
-        .irqdisable     = MAILBOX_IRQENABLE(0),
-};
-
-struct omap_mbox mbox_dsp_info = {
-        .name   = "dsp",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_dsp_priv,
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3)
-struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
-#endif
-
-#if defined(CONFIG_SOC_OMAP2420)
-/* IVA */
-static struct omap_mbox2_priv omap2_mbox_iva_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(2),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(2),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(3),
-                .msg_stat       = MAILBOX_MSGSTATUS(3),
-        },
-        .irqenable      = MAILBOX_IRQENABLE(3),
-        .irqstatus      = MAILBOX_IRQSTATUS(3),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(2),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(3),
-        .irqdisable     = MAILBOX_IRQENABLE(3),
-};
-
-static struct omap_mbox mbox_iva_info = {
-        .name   = "iva",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_iva_priv,
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2
-struct omap_mbox *omap2_mboxes[] = {
-        &mbox_dsp_info,
-#ifdef CONFIG_SOC_OMAP2420
-        &mbox_iva_info,
-#endif
-        NULL
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP4)
-/* OMAP4 */
-static struct omap_mbox2_priv omap2_mbox_1_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(0),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(0),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(1),
-                .msg_stat       = MAILBOX_MSGSTATUS(1),
-        },
-        .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
-        .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(0),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(1),
-        .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
-};
-
-struct omap_mbox mbox_1_info = {
-        .name   = "mailbox-1",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_1_priv,
-};
-
-static struct omap_mbox2_priv omap2_mbox_2_priv = {
-        .tx_fifo = {
-                .msg            = MAILBOX_MESSAGE(3),
-                .fifo_stat      = MAILBOX_FIFOSTATUS(3),
-        },
-        .rx_fifo = {
-                .msg            = MAILBOX_MESSAGE(2),
-                .msg_stat       = MAILBOX_MSGSTATUS(2),
-        },
-        .irqenable      = OMAP4_MAILBOX_IRQENABLE(0),
-        .irqstatus      = OMAP4_MAILBOX_IRQSTATUS(0),
-        .notfull_bit    = MAILBOX_IRQ_NOTFULL(3),
-        .newmsg_bit     = MAILBOX_IRQ_NEWMSG(2),
-        .irqdisable     = OMAP4_MAILBOX_IRQENABLE_CLR(0),
-};
-
-struct omap_mbox mbox_2_info = {
-        .name   = "mailbox-2",
-        .ops    = &omap2_mbox_ops,
-        .priv   = &omap2_mbox_2_priv,
-};
-
-struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
-#endif
-
-static int omap2_mbox_probe(struct platform_device *pdev)
-{
-        struct resource *mem;
-        int ret;
-        struct omap_mbox **list;
-
-        if (false)
-                ;
-#if defined(CONFIG_ARCH_OMAP3)
-        else if (cpu_is_omap34xx()) {
-                list = omap3_mboxes;
-
-                list[0]->irq = platform_get_irq(pdev, 0);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP2)
-        else if (cpu_is_omap2430()) {
-                list = omap2_mboxes;
-
-                list[0]->irq = platform_get_irq(pdev, 0);
-        } else if (cpu_is_omap2420()) {
-                list = omap2_mboxes;
-
-                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
-                list[1]->irq = platform_get_irq_byname(pdev, "iva");
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        else if (cpu_is_omap44xx()) {
-                list = omap4_mboxes;
-
-                list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
-        }
-#endif
-        else {
-                pr_err("%s: platform not supported\n", __func__);
-                return -ENODEV;
-        }
-
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        mbox_base = ioremap(mem->start, resource_size(mem));
-        if (!mbox_base)
-                return -ENOMEM;
-
-        ret = omap_mbox_register(&pdev->dev, list);
-        if (ret) {
-                iounmap(mbox_base);
-                return ret;
-        }
-
-        return 0;
-}
-
-static int omap2_mbox_remove(struct platform_device *pdev)
-{
-        omap_mbox_unregister();
-        iounmap(mbox_base);
-        return 0;
-}
-
-static struct platform_driver omap2_mbox_driver = {
-        .probe = omap2_mbox_probe,
-        .remove = omap2_mbox_remove,
-        .driver = {
-                .name = "omap-mailbox",
-        },
-};
-
-static int __init omap2_mbox_init(void)
-{
-        return platform_driver_register(&omap2_mbox_driver);
-}
-
-static void __exit omap2_mbox_exit(void)
-{
-        platform_driver_unregister(&omap2_mbox_driver);
-}
-
-module_init(omap2_mbox_init);
-module_exit(omap2_mbox_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
-MODULE_AUTHOR("Paul Mundt");
-MODULE_ALIAS("platform:omap2-mailbox");
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index fdb22f14021f..5d2080ef7923 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -10,7 +10,6 @@
 #include "mux2420.h"
 #include "mux2430.h"
 #include "mux34xx.h"
-#include "mux44xx.h"
 
 #define OMAP_MUX_TERMINATOR     0xffff
 
@@ -64,8 +63,6 @@
 
 /* Flags for omapX_mux_init */
 #define OMAP_PACKAGE_MASK               0xffff
-#define OMAP_PACKAGE_CBS                8               /* 547-pin 0.40 0.40 */
-#define OMAP_PACKAGE_CBL                7               /* 547-pin 0.40 0.40 */
 #define OMAP_PACKAGE_CBP                6               /* 515-pin 0.40 0.50 */
 #define OMAP_PACKAGE_CUS                5               /* 423-pin 0.65 */
 #define OMAP_PACKAGE_CBB                4               /* 515-pin 0.40 0.50 */
diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c
deleted file mode 100644
index f5a74daab2ff..000000000000
--- a/arch/arm/mach-omap2/mux44xx.c
+++ /dev/null
@@ -1,1356 +0,0 @@
-/*
- * OMAP44xx ES1.0 pin mux definition
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- *
- * - Based on mux34xx.c done by Tony Lindgren <tony@atomide.com>
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/init.h>
-
-#include "mux.h"
-
-#ifdef CONFIG_OMAP_MUX
-
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .gpio           = (g),                                          \
-        .muxnames       = { m0, m1, m2, m3, m4, m5, m6, m7 },           \
-}
-
-#else
-
-#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)  \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .gpio           = (g),                                          \
-}
-
-#endif
-
-#define _OMAP4_BALLENTRY(M0, bb, bt)                            \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .balls          = { bb, bt },                                   \
-}
-
-/*
- * Superset of all mux modes for omap4 ES1.0
- */
-static struct omap_mux __initdata omap4_core_muxmodes[] = {
-        _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4",
-                        "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5",
-                        "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6",
-                        "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7",
-                        "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-                        "gpio_32", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-                        "gpio_33", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-                        "gpio_34", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-                        "gpio_35", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-                        "gpio_36", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-                        "gpio_37", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-                        "gpio_38", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-                        "gpio_39", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-                        "gpio_40", "venc_656_data0", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1",
-                        "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2",
-                        "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3",
-                        "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4",
-                        "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5",
-                        "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6",
-                        "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7",
-                        "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0",
-                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1",
-                        "gpio_49", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50",
-                        "sys_ndmareq0", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6",
-                        "gpio_51", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7",
-                        "gpio_52", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir",
-                        "c2c_dataout4", "gpio_53", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54",
-                        "sys_ndmareq1", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-                        "sys_ndmareq2", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-                        "gpio_56", "sys_ndmareq3", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL,
-                        "gpio_59", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5",
-                        "gpio_60", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL,
-                        "gpio_61", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2",
-                        "gpio_62", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen",
-                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0",
-                        "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1",
-                        "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0",
-                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1",
-                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL,
-                        "gpio_65", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL,
-                        "gpio_66", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL,
-                        "gpio_83", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk",
-                        "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk",
-                        NULL, "hw_dbg20", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp",
-                        "hsi1_cadata", "mcbsp4_clkr", "gpio_85",
-                        "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir",
-                        "hsi1_caflag", "mcbsp4_fsr", "gpio_86",
-                        "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt",
-                        "hsi1_acready", "mcbsp4_fsx", "gpio_87",
-                        "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-                        "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
-                        "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
-                        "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-                        "usbb1_mm_txen", "hw_dbg27", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4",
-                        "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92",
-                        "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5",
-                        "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93",
-                        "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6",
-                        "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94",
-                        "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7",
-                        "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95",
-                        "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL,
-                        "gpio_96", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL,
-                        NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL,
-                        "gpio_98", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL,
-                        "gpio_99", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19",
-                        "gpio_100", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx",
-                        "gpio_101", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18",
-                        "gpio_102", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17",
-                        "gpio_103", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16",
-                        "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15",
-                        "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL,
-                        "gpio_106", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL,
-                        "gpio_107", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL,
-                        "gpio_108", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL,
-                        "gpio_109", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk",
-                        "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm",
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi",
-                        "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo",
-                        "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0",
-                        "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx",
-                        "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr",
-                        "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2",
-                        "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3",
-                        "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data",
-                        "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data",
-                        "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx",
-                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx",
-                        NULL, NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-                        "gpio_119", "usbb2_mm_txse0", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-                        "gpio_120", "usbb2_mm_txdat", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-                        NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-                        "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL,
-                        "gpio_123", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL,
-                        "gpio_124", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL,
-                        "gpio_125", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL,
-                        "gpio_126", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb",
-                        "gpio_127", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL,
-                        "gpio_128", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL,
-                        "gpio_129", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL,
-                        "gpio_135", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL,
-                        "gpio_136", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL,
-                        "gpio_138", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts",
-                        "slimbus2_clock", "gpio_139", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts",
-                        "slimbus2_data", "gpio_140", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx",
-                        NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL,
-                        "gpio_142", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx",
-                        "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx",
-                        "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-                        "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-                        "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-                        "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-                        "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-                        "gpio_149", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-                        "gpio_150", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL,
-                        "gpio_151", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL,
-                        "gpio_152", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL,
-                        "gpio_153", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL,
-                        "gpio_154", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL,
-                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL,
-                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk",
-                        "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157",
-                        "hsi2_cawake", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-                        "hsi2_cadata", "dispc2_data23", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-                        "hsi2_caflag", "dispc2_data22", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-                        "hsi2_acready", "dispc2_data21", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-                        "hsi2_acwake", "dispc2_data20", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-                        "hsi2_acdata", "dispc2_data19", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-                        "hsi2_acflag", "dispc2_data18", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-                        "hsi2_caready", "dispc2_data15", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-                        "mcspi3_somi", "dispc2_data14", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-                        "mcspi3_cs0", "dispc2_data13", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-                        "mcspi3_simo", "dispc2_data12", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-                        "mcspi3_clk", "dispc2_data11", NULL, "reserved"),
-        _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL,
-                        "gpio_169", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL,
-                        NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL,
-                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL,
-                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL,
-                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL,
-                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL,
-                        "gpio_0", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL,
-                        "gpio_1", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL,
-                        "gpi_175", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL,
-                        "gpi_176", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL,
-                        "gpi_177", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL,
-                        "gpi_178", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL,
-                        "gpi_2", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL,
-                        "gpi_3", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx",
-                        "uart2_rx", "gpio_179", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx",
-                        "uart2_tx", "gpio_180", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL,
-                        "gpio_181", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL,
-                        "gpio_182", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL,
-                        NULL, "hw_dbg0", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL,
-                        NULL, "hw_dbg1", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-                        "gpio_14", NULL, "dispc2_data10", "hw_dbg3",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-                        "gpio_15", NULL, "dispc2_data9", "hw_dbg4",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-                        "hw_dbg5", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-                        "dispc2_data17", "hw_dbg6", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-                        "dispc2_hsync", "hw_dbg7", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-                        "hw_dbg8", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
-                        "dispc2_vsync", "hw_dbg9", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-                        "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-                        "hw_dbg11", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-                        "hw_dbg12", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-                        "hw_dbg13", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-                        "hw_dbg14", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-                        "hw_dbg15", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-                        "hw_dbg16", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-                        "hw_dbg17", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-                        "hw_dbg18", "reserved"),
-        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-                        "hw_dbg19", "reserved"),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBL package
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_core_cbl_ball[] = {
-        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL),
-        _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL),
-        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL),
-        _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbl_ball  NULL
-#endif
-
-/*
- * Signals different on ES2.0 compared to superset
- */
-static struct omap_mux __initdata omap4_es2_core_subset[] = {
-        _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15",
-                        "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14",
-                        "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13",
-                        "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12",
-                        "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11",
-                        "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10",
-                        "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9",
-                        "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8",
-                        "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0",
-                        "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0",
-                        "gpio_48", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8",
-                        "c2c_dataout7", "gpio_52", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55",
-                        "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL,
-                        "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL),
-        _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen",
-                        "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0",
-                        "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1",
-                        "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0",
-                        "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1",
-                        "c2c_dataout1", "gpio_104", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0",
-                        "hsi1_acwake", "mcbsp4_clkx", "gpio_88",
-                        "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1",
-                        "hsi1_acdata", "mcbsp4_dx", "gpio_89",
-                        "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2",
-                        "hsi1_acflag", "mcbsp4_dr", "gpio_90",
-                        "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3",
-                        "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3",
-                        "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL,
-                        "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL,
-                        "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock",
-                        "abe_mcasp_axr", "gpio_121", NULL,
-                        "dmtimer11_pwm_evt", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data",
-                        "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk",
-                        "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo",
-                        "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi",
-                        "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL,
-                        "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1",
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL,
-                        "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL,
-                        "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk",
-                        "kpd_col6", "gpio_151", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd",
-                        "kpd_col7", "gpio_152", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0",
-                        "kpd_row6", "gpio_153", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3",
-                        "kpd_row7", "gpio_154", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8",
-                        "gpio_155", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8",
-                        "gpio_156", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp",
-                        "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158",
-                        "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir",
-                        "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159",
-                        "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt",
-                        "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160",
-                        "hsi2_acready", "dispc2_data21", NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0",
-                        "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161",
-                        "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1",
-                        "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162",
-                        "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2",
-                        "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163",
-                        "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3",
-                        "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164",
-                        "hsi2_caready", "dispc2_data15", "rfbi_data15",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4",
-                        "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165",
-                        "mcspi3_somi", "dispc2_data14", "rfbi_data14",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5",
-                        "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166",
-                        "mcspi3_cs0", "dispc2_data13", "rfbi_data13",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6",
-                        "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167",
-                        "mcspi3_simo", "dispc2_data12", "rfbi_data12",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7",
-                        "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168",
-                        "mcspi3_clk", "dispc2_data11", "rfbi_data11",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL,
-                        "gpio_171", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL,
-                        "gpio_172", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL,
-                        "gpio_173", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL,
-                        "gpio_174", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL,
-                        "gpio_175", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL,
-                        "gpio_176", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL,
-                        "gpio_177", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL,
-                        "gpio_178", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx",
-                        "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx",
-                        "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL,
-                        "gpio_13", NULL, "dispc2_fid", "hw_dbg2",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL,
-                        "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL,
-                        "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL,
-                        "gpio_16", "rfbi_te_vsync0", "dispc2_data16",
-                        "hw_dbg5", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0",
-                        "uart3_tx_irtx", "gpio_17", "rfbi_hsync0",
-                        "dispc2_data17", "hw_dbg6", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1",
-                        "uart3_rx_irrx", "gpio_18", "rfbi_cs0",
-                        "dispc2_hsync", "hw_dbg7", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2",
-                        "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk",
-                        "hw_dbg8", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3",
-                        "uart3_cts_rctx", "gpio_20", "rfbi_we",
-                        "dispc2_vsync", "hw_dbg9", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4",
-                        NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10",
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5",
-                        NULL, "gpio_22", "rfbi_data8", "dispc2_data8",
-                        "hw_dbg11", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6",
-                        NULL, "gpio_23", "rfbi_data7", "dispc2_data7",
-                        "hw_dbg12", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7",
-                        NULL, "gpio_24", "rfbi_data6", "dispc2_data6",
-                        "hw_dbg13", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure",
-                        "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5",
-                        "hw_dbg14", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator",
-                        NULL, "gpio_26", "rfbi_data4", "dispc2_data4",
-                        "hw_dbg15", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt",
-                        "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3",
-                        "hw_dbg16", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt",
-                        "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2",
-                        "hw_dbg17", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt",
-                        "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1",
-                        "hw_dbg18", "safe_mode"),
-        _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt",
-                        "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0",
-                        "hw_dbg19", "safe_mode"),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBS package
- * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBS)
-static struct omap_ball __initdata omap4_core_cbs_ball[] = {
-        _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL),
-        _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL),
-        _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL),
-        _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL),
-        _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL),
-        _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL),
-        _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL),
-        _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL),
-        _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL),
-        _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL),
-        _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL),
-        _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL),
-        _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL),
-        _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL),
-        _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL),
-        _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL),
-        _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL),
-        _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL),
-        _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL),
-        _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL),
-        _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL),
-        _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL),
-        _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL),
-        _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL),
-        _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL),
-        _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL),
-        _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL),
-        _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL),
-        _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL),
-        _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL),
-        _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL),
-        _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL),
-        _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL),
-        _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL),
-        _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL),
-        _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL),
-        _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL),
-        _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL),
-        _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL),
-        _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL),
-        _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL),
-        _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL),
-        _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL),
-        _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL),
-        _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL),
-        _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL),
-        _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL),
-        _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL),
-        _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL),
-        _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL),
-        _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL),
-        _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL),
-        _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL),
-        _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL),
-        _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL),
-        _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL),
-        _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL),
-        _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL),
-        _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL),
-        _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL),
-        _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL),
-        _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL),
-        _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL),
-        _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_core_cbs_ball  NULL
-#endif
-
-/*
- * Superset of all mux modes for omap4
- */
-static struct omap_mux __initdata omap4_wkup_muxmodes[] = {
-        _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL,
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4",
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL,
-                        "c2c_wakereqin", NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL,
-                        "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req",
-                        "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req",
-                        "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req",
-                        "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout",
-                        NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out",
-                        NULL, "gpio_wk7", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL,
-                        "gpio_wk8", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL,
-                        NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL,
-                        NULL, "gpio_wk29", NULL, NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL,
-                        "gpio_wk9", "c2c_wakereqout", NULL, NULL,
-                        "safe_mode"),
-        _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL,
-                        "gpio_wk10", NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL,
-                        NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL,
-                        NULL, NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL,
-                        NULL, NULL, NULL, "safe_mode"),
-        _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL,
-                        NULL, NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-
-/*
- * Balls for 44XX CBL & CBS package - wakeup partition
- * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top),
- *                                0.40mm Ball Pitch (Bottom)
- */
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS)                \
-                && defined(CONFIG_OMAP_PACKAGE_CBL)
-static struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = {
-        _OMAP4_BALLENTRY(SIM_IO, "h4", NULL),
-        _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL),
-        _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL),
-        _OMAP4_BALLENTRY(SIM_CD, "j1", NULL),
-        _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL),
-        _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL),
-        _OMAP4_BALLENTRY(SR_SDA, "af9", NULL),
-        _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL),
-        _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL),
-        _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL),
-        _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL),
-        _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL),
-        _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL),
-        _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL),
-        _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL),
-        _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL),
-        _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL),
-        _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL),
-        _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL),
-        _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL),
-        _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL),
-        _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#else
-#define omap4_wkup_cbl_cbs_ball  NULL
-#endif
-
-int __init omap4_mux_init(struct omap_board_mux *board_subset,
-        struct omap_board_mux *board_wkup_subset, int flags)
-{
-        struct omap_ball *package_balls_core;
-        struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball;
-        struct omap_mux *core_muxmodes;
-        struct omap_mux *core_subset = NULL;
-        int ret;
-
-        switch (flags & OMAP_PACKAGE_MASK) {
-        case OMAP_PACKAGE_CBL:
-                pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__);
-                package_balls_core = omap4_core_cbl_ball;
-                core_muxmodes = omap4_core_muxmodes;
-                break;
-        case OMAP_PACKAGE_CBS:
-                pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__);
-                package_balls_core = omap4_core_cbs_ball;
-                core_muxmodes = omap4_core_muxmodes;
-                core_subset = omap4_es2_core_subset;
-                break;
-        default:
-                pr_err("%s: Unknown omap package, mux disabled\n", __func__);
-                return -EINVAL;
-        }
-
-        ret = omap_mux_init("core",
-                            OMAP_MUX_GPIO_IN_MODE3,
-                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE,
-                            OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE,
-                            core_muxmodes, core_subset, board_subset,
-                            package_balls_core);
-        if (ret)
-                return ret;
-
-        ret = omap_mux_init("wkup",
-                            OMAP_MUX_GPIO_IN_MODE3,
-                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE,
-                            OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE,
-                            omap4_wkup_muxmodes, NULL, board_wkup_subset,
-                            package_balls_wkup);
-
-        return ret;
-}
-
diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h
deleted file mode 100644
index c635026cd7e9..000000000000
--- a/arch/arm/mach-omap2/mux44xx.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- * OMAP44xx MUX registers and bitfields
- *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
- *
- * Benoit Cousson (b-cousson@ti.com)
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H
-
-#define OMAP4_MUX(M0, mux_value)                                        \
-{                                                                       \
-        .reg_offset     = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET),        \
-        .value          = (mux_value),                                  \
-}
-
-/* ctrl_module_pad_core base address */
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE                    0x4a100000
-
-/* ctrl_module_pad_core registers offset */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET                   0x0040
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET                   0x0042
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET                   0x0044
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET                   0x0046
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET                   0x0048
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET                   0x004a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET                   0x004c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET                   0x004e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET                   0x0050
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET                   0x0052
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET                  0x0054
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET                  0x0056
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET                  0x0058
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET                  0x005a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET                  0x005c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET                  0x005e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET                   0x0060
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET                   0x0062
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET                   0x0064
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET                   0x0066
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET                   0x0068
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET                   0x006a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET                   0x006c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET                   0x006e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET                   0x0070
-#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET                   0x0072
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET                  0x0074
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET                  0x0076
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET                  0x0078
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET                  0x007a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET                   0x007c
-#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET                   0x007e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET              0x0080
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET                   0x0082
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET                   0x0084
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET              0x0086
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET                  0x0088
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET                 0x008a
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET                 0x008c
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET                 0x008e
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET                 0x0090
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET                 0x0092
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET                 0x0094
-#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET                 0x0096
-#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET                   0x0098
-#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET                   0x009a
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET               0x009c
-#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET               0x009e
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET                  0x00a0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET                  0x00a2
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET                  0x00a4
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET                  0x00a6
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET                  0x00a8
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET                  0x00aa
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET                  0x00ac
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET                  0x00ae
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET                  0x00b0
-#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET                  0x00b2
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET                  0x00b4
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET                  0x00b6
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET                  0x00b8
-#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET                  0x00ba
-#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET                0x00bc
-#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET                 0x00be
-#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET            0x00c0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET          0x00c2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET          0x00c4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET          0x00c6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET          0x00c8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET         0x00ca
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET         0x00cc
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET         0x00ce
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET         0x00d0
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET         0x00d2
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET         0x00d4
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET         0x00d6
-#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET         0x00d8
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET            0x00da
-#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET          0x00dc
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET             0x00de
-#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET             0x00e0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET                 0x00e2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET                 0x00e4
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET                0x00e6
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET                0x00e8
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET                0x00ea
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET                0x00ec
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET                0x00ee
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET                0x00f0
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET                0x00f2
-#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET                0x00f4
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET            0x00f6
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET              0x00f8
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET              0x00fa
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET             0x00fc
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET            0x00fe
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET              0x0100
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET              0x0102
-#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET             0x0104
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET            0x0106
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET            0x0108
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET              0x010a
-#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET             0x010c
-#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET                   0x010e
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET              0x0110
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET              0x0112
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET              0x0114
-#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET              0x0116
-#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET                  0x0118
-#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET                  0x011a
-#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET                   0x011c
-#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET                   0x011e
-#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET                    0x0120
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET                   0x0122
-#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET                   0x0124
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET                   0x0126
-#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET                   0x0128
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET                   0x012a
-#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET                   0x012c
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET                   0x012e
-#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET                   0x0130
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET                 0x0132
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET                0x0134
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET                0x0136
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET                 0x0138
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET                 0x013a
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET                 0x013c
-#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET                 0x013e
-#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET             0x0140
-#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET               0x0142
-#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET              0x0144
-#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET              0x0146
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET                 0x0148
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET                 0x014a
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET                0x014c
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET                0x014e
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET                0x0150
-#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET                0x0152
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET                 0x0154
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET                0x0156
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET                0x0158
-#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET                 0x015a
-#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET                   0x015c
-#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET                   0x015e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET          0x0160
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET          0x0162
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET          0x0164
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET          0x0166
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET         0x0168
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET         0x016a
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET         0x016c
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET         0x016e
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET         0x0170
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET         0x0172
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET         0x0174
-#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET         0x0176
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET            0x0178
-#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET          0x017a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET                 0x017c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET                 0x017e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET                 0x0180
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET                 0x0182
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET                 0x0184
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET                 0x0186
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET                 0x0188
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET                 0x018a
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET                 0x018c
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET                 0x018e
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET                 0x0190
-#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET                 0x0192
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET               0x0194
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET               0x0196
-#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET               0x0198
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET              0x019a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET              0x019c
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET                  0x019e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET                  0x01a0
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET                  0x01a2
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET                  0x01a4
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET                  0x01a6
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET                  0x01a8
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET                  0x01aa
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET                  0x01ac
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET                   0x01ae
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET                   0x01b0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET                   0x01b2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET                   0x01b4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET                   0x01b6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET                   0x01b8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET                   0x01ba
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET                   0x01bc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET                   0x01be
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET                   0x01c0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET                  0x01c2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET                  0x01c4
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET                  0x01c6
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET                  0x01c8
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET                  0x01ca
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET                  0x01cc
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET                  0x01ce
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET                  0x01d0
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET                  0x01d2
-#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET                  0x01d4
-
-/* ES2.0 only */
-#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET                 0x008e
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET                  0x0090
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET                  0x0092
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET                  0x0094
-#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET                  0x0096
-
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET                   0x017c
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET                   0x017e
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET                   0x0180
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET                   0x0182
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET                   0x0184
-#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET                   0x0186
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET                   0x0188
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET                   0x018a
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET                   0x018c
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET                   0x018e
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET                   0x0190
-#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET                   0x0192
-
-
-#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE                     \
-                (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET         \
-                 - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2)
-
-/* ctrl_module_pad_wkup base address */
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE                    0x4a31e000
-
-/* ctrl_module_pad_wkup registers offset */
-#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET                     0x0040
-#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET                    0x0042
-#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET                  0x0044
-#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET                     0x0046
-#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET                0x0048
-#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET                     0x004a
-#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET                     0x004c
-#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET               0x004e
-#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET             0x0050
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET             0x0052
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET              0x0054
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET              0x0056
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET              0x0058
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET              0x005a
-#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET              0x005c
-#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET                    0x005e
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET              0x0060
-#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET               0x0062
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET                0x0064
-#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET        0x0066
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET                  0x0068
-#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET                  0x006a
-#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET                 0x006c
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET                   0x006e
-#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET                  0x0070
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET              0x0072
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET                   0x0074
-#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET                   0x0076
-
-#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE                     \
-                (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET          \
-                 - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2)
-
-#endif
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 0ea09faf327b..4ea308114165 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -49,7 +49,7 @@ END(omap5_secondary_startup)
  * The primary core will update this flag using a hardware
  * register AuxCoreBoot0.
  */
-ENTRY(omap_secondary_startup)
+ENTRY(omap4_secondary_startup)
 hold:   ldr     r12,=0x103
         dsb
         smc     #0                      @ read from AuxCoreBoot0
@@ -64,9 +64,9 @@ hold:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-ENDPROC(omap_secondary_startup)
+ENDPROC(omap4_secondary_startup)
 
-ENTRY(omap_secondary_startup_4460)
+ENTRY(omap4460_secondary_startup)
 hold_2: ldr     r12,=0x103
         dsb
         smc     #0                      @ read from AuxCoreBoot0
@@ -101,4 +101,4 @@ hold_2:	ldr	r12,=0x103
          * should now contain the SVC stack for this core
          */
         b       secondary_startup
-ENDPROC(omap_secondary_startup_4460)
+ENDPROC(omap4460_secondary_startup)
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e80327b6c81f..f993a4188701 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -71,10 +71,43 @@ struct omap4_cpu_pm_info {
         void (*secondary_startup)(void);
 };
 
+/**
+ * struct cpu_pm_ops - CPU pm operations
+ * @finish_suspend:     CPU suspend finisher function pointer
+ * @resume:             CPU resume function pointer
+ * @scu_prepare:        CPU Snoop Control program function pointer
+ *
+ * Structure holds functions pointer for CPU low power operations like
+ * suspend, resume and scu programming.
+ */
+struct cpu_pm_ops {
+        int (*finish_suspend)(unsigned long cpu_state);
+        void (*resume)(void);
+        void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
+};
+
 static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
 static struct powerdomain *mpuss_pd;
 static void __iomem *sar_base;
 
+static int default_finish_suspend(unsigned long cpu_state)
+{
+        omap_do_wfi();
+        return 0;
+}
+
+static void dummy_cpu_resume(void)
+{}
+
+static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{}
+
+struct cpu_pm_ops omap_pm_ops = {
+        .finish_suspend         = default_finish_suspend,
+        .resume                 = dummy_cpu_resume,
+        .scu_prepare            = dummy_scu_prepare,
+};
+
 /*
  * Program the wakeup routine address for the CPU0 and CPU1
  * used for OFF or DORMANT wakeup.
@@ -158,11 +191,12 @@ static void save_l2x0_context(void)
 {
         u32 val;
         void __iomem *l2x0_base = omap4_get_l2cache_base();
-
-        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
-        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        if (l2x0_base) {
+                val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+                __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+                val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+                __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+        }
 }
 #else
 static void save_l2x0_context(void)
@@ -225,14 +259,17 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
 
         cpu_clear_prev_logic_pwrst(cpu);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
-        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
-        scu_pwrst_prepare(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+        omap_pm_ops.scu_prepare(cpu, power_state);
         l2x0_pwrst_prepare(cpu, save_state);
 
         /*
          * Call low level function  with targeted low power state.
          */
-        cpu_suspend(save_state, omap4_finish_suspend);
+        if (save_state)
+                cpu_suspend(save_state, omap_pm_ops.finish_suspend);
+        else
+                omap_pm_ops.finish_suspend(save_state);
 
         /*
          * Restore the CPUx power state to ON otherwise CPUx
@@ -268,14 +305,14 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
         pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
         pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
         set_cpu_wakeup_addr(cpu, virt_to_phys(pm_info->secondary_startup));
-        scu_pwrst_prepare(cpu, power_state);
+        omap_pm_ops.scu_prepare(cpu, power_state);
 
         /*
          * CPU never retuns back if targeted power state is OFF mode.
          * CPU ONLINE follows normal CPU ONLINE ptah via
-         * omap_secondary_startup().
+         * omap4_secondary_startup().
          */
-        omap4_finish_suspend(cpu_state);
+        omap_pm_ops.finish_suspend(cpu_state);
 
         pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
         return 0;
@@ -319,9 +356,9 @@ int __init omap4_mpuss_init(void)
         pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
         pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
         if (cpu_is_omap446x())
-                pm_info->secondary_startup = omap_secondary_startup_4460;
+                pm_info->secondary_startup = omap4460_secondary_startup;
         else
-                pm_info->secondary_startup = omap_secondary_startup;
+                pm_info->secondary_startup = omap4_secondary_startup;
 
         pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
         if (!pm_info->pwrdm) {
@@ -352,6 +389,12 @@ int __init omap4_mpuss_init(void)
 
         save_l2x0_context();
 
+        if (cpu_is_omap44xx()) {
+                omap_pm_ops.finish_suspend = omap4_finish_suspend;
+                omap_pm_ops.resume = omap4_cpu_resume;
+                omap_pm_ops.scu_prepare = scu_pwrst_prepare;
+        }
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 2a551f997aea..98a11463a843 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -87,7 +87,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 
         /*
          * Update the AuxCoreBoot0 with boot state for secondary core.
-         * omap_secondary_startup() routine will hold the secondary core till
+         * omap4_secondary_startup() routine will hold the secondary core till
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
@@ -200,7 +200,7 @@ static void __init omap4_smp_init_cpus(void)
 
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
-        void *startup_addr = omap_secondary_startup;
+        void *startup_addr = omap4_secondary_startup;
         void __iomem *base = omap_get_wakeupgen_base();
 
         /*
@@ -211,7 +211,7 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
                 scu_enable(scu_base);
 
         if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
+                startup_addr = omap4460_secondary_startup;
                 pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
         }
 
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 13b27ffaf45e..38cd3a69cff3 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -339,19 +339,3 @@ int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
         return 0;
 }
 #endif
-
-/**
- * omap44xx_restart - trigger a software restart of the SoC
- * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
- * @cmd: passed from the userspace program rebooting the system (if provided)
- *
- * Resets the SoC.  For @cmd, see the 'reboot' syscall in
- * kernel/sys.c.  No return value.
- */
-void omap44xx_restart(char mode, const char *cmd)
-{
-        /* XXX Should save 'cmd' into scratchpad for use after reboot */
-        omap4_prminst_global_warm_sw_reset(); /* never returns */
-        while (1);
-}
-
diff --git a/arch/arm/mach-omap2/omap4-restart.c b/arch/arm/mach-omap2/omap4-restart.c
new file mode 100644
index 000000000000..f90e02e11898
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-restart.c
@@ -0,0 +1,27 @@
+/*
+ * omap4-restart.c - Common to OMAP4 and OMAP5
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/types.h>
+#include "prminst44xx.h"
+
+/**
+ * omap44xx_restart - trigger a software restart of the SoC
+ * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
+ * @cmd: passed from the userspace program rebooting the system (if provided)
+ *
+ * Resets the SoC.  For @cmd, see the 'reboot' syscall in
+ * kernel/sys.c.  No return value.
+ */
+void omap44xx_restart(char mode, const char *cmd)
+{
+        /* XXX Should save 'cmd' into scratchpad for use after reboot */
+        omap4_prminst_global_warm_sw_reset(); /* never returns */
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c
index e6d230700b2b..5cc92874be7e 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -170,9 +170,6 @@ static int omap_device_build_from_dt(struct platform_device *pdev)
                         r->name = dev_name(&pdev->dev);
         }
 
-        if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
-                omap_device_disable_idle_on_suspend(pdev);
-
         pdev->dev.pm_domain = &omap_device_pm_domain;
 
 odbfd_exit1:
@@ -591,11 +588,6 @@ static int _od_runtime_suspend(struct device *dev)
         return ret;
 }
 
-static int _od_runtime_idle(struct device *dev)
-{
-        return pm_generic_runtime_idle(dev);
-}
-
 static int _od_runtime_resume(struct device *dev)
 {
         struct platform_device *pdev = to_platform_device(dev);
@@ -621,8 +613,7 @@ static int _od_suspend_noirq(struct device *dev)
 
         if (!ret && !pm_runtime_status_suspended(dev)) {
                 if (pm_generic_runtime_suspend(dev) == 0) {
-                        if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
-                                omap_device_idle(pdev);
+                        omap_device_idle(pdev);
                         od->flags |= OMAP_DEVICE_SUSPENDED;
                 }
         }
@@ -638,8 +629,7 @@ static int _od_resume_noirq(struct device *dev)
         if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
             !pm_runtime_status_suspended(dev)) {
                 od->flags &= ~OMAP_DEVICE_SUSPENDED;
-                if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
-                        omap_device_enable(pdev);
+                omap_device_enable(pdev);
                 pm_generic_runtime_resume(dev);
         }
 
@@ -653,7 +643,7 @@ static int _od_resume_noirq(struct device *dev)
 struct dev_pm_domain omap_device_pm_domain = {
         .ops = {
                 SET_RUNTIME_PM_OPS(_od_runtime_suspend, _od_runtime_resume,
-                                   _od_runtime_idle)
+                                   NULL)
                 USE_PLATFORM_PM_SLEEP_OPS
                 .suspend_noirq = _od_suspend_noirq,
                 .resume_noirq = _od_resume_noirq,
diff --git a/arch/arm/mach-omap2/omap_device.h b/arch/arm/mach-omap2/omap_device.h
index 044c31d50e5b..17ca1aec2710 100644
--- a/arch/arm/mach-omap2/omap_device.h
+++ b/arch/arm/mach-omap2/omap_device.h
@@ -38,7 +38,6 @@ extern struct dev_pm_domain omap_device_pm_domain;
 
 /* omap_device.flags values */
 #define OMAP_DEVICE_SUSPENDED           BIT(0)
-#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND  BIT(1)
 
 /**
  * struct omap_device - omap_device wrapper for platform_devices
@@ -101,13 +100,4 @@ static inline struct omap_device *to_omap_device(struct platform_device *pdev)
 {
         return pdev ? pdev->archdata.od : NULL;
 }
-
-static inline
-void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
-{
-        struct omap_device *od = to_omap_device(pdev);
-
-        od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
-
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..aab33fd814c0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
 extern int omap2430_hwmod_init(void);
 extern int omap3xxx_hwmod_init(void);
 extern int omap44xx_hwmod_init(void);
+extern int omap54xx_hwmod_init(void);
 extern int am33xx_hwmod_init(void);
 
 extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 5137cc84b504..d8b9d60f854f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,6 +16,7 @@
 #include <linux/i2c-omap.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -166,6 +167,18 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 };
 
 /* mailbox */
+static struct omap_mbox_dev_info omap2420_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1, .irq_id = 0, .usr_id = 0 },
+        { .name = "iva", .tx_id = 2, .rx_id = 3, .irq_id = 1, .usr_id = 3 },
+};
+
+static struct omap_mbox_pdata omap2420_mailbox_attrs = {
+        .num_users      = 4,
+        .num_fifos      = 6,
+        .info_cnt       = ARRAY_SIZE(omap2420_mailbox_info),
+        .info           = omap2420_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
         { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
         { .name = "iva", .irq = 34 + OMAP_INTC_START, },
@@ -186,6 +199,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
+        .dev_attr       = &omap2420_mailbox_attrs,
 };
 
 /*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4ce999ee3ee9..5b9083461dc5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -17,6 +17,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/omap-dma.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod.h"
@@ -170,6 +171,17 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 
 /* mailbox */
+static struct omap_mbox_dev_info omap2430_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+
+static struct omap_mbox_pdata omap2430_mailbox_attrs = {
+        .num_users      = 4,
+        .num_fifos      = 6,
+        .info_cnt       = ARRAY_SIZE(omap2430_mailbox_info),
+        .info           = omap2430_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
         { .irq = 26 + OMAP_INTC_START, },
         { .irq = -1 },
@@ -189,6 +201,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
                 },
         },
+        .dev_attr       = &omap2430_mailbox_attrs,
 };
 
 /* mcspi3 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 534974e08add..5da7a42a6d90 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -17,7 +17,6 @@
 #include "hdq1w.h"
 
 #include "omap_hwmod_common_data.h"
-#include "dma.h"
 
 /* UART */
 
@@ -89,32 +88,32 @@ struct omap_hwmod_class omap2_venc_hwmod_class = {
 
 /* Common DMA request line data */
 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+        { .name = "rx", .dma_req = 50, },
+        { .name = "tx", .dma_req = 49, },
         { .dma_req = -1 }
 };
 
 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+        { .name = "rx", .dma_req = 52, },
+        { .name = "tx", .dma_req = 51, },
         { .dma_req = -1 }
 };
 
 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
-        { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+        { .name = "rx", .dma_req = 54, },
+        { .name = "tx", .dma_req = 53, },
         { .dma_req = -1 }
 };
 
 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+        { .name = "tx", .dma_req = 27 },
+        { .name = "rx", .dma_req = 28 },
         { .dma_req = -1 }
 };
 
 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
-        { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+        { .name = "tx", .dma_req = 29 },
+        { .name = "rx", .dma_req = 30 },
         { .dma_req = -1 }
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 075f7cc51026..28bbd56346a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -35,29 +35,6 @@
  */
 
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
-        .name           = "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod am33xx_emif_fw_hwmod = {
-        .name           = "emif_fw",
-        .class          = &am33xx_emif_fw_hwmod_class,
-        .clkdm_name     = "l4fw_clkdm",
-        .main_clk       = "l4fw_gclk",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
-/*
  * 'emif' class
  * instance(s): emif
  */
@@ -70,18 +47,12 @@ static struct omap_hwmod_class am33xx_emif_hwmod_class = {
         .sysc           = &am33xx_emif_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
-        { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 /* emif */
 static struct omap_hwmod am33xx_emif_hwmod = {
         .name           = "emif",
         .class          = &am33xx_emif_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_emif_irqs,
         .main_clk       = "dpll_ddr_m2_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -99,19 +70,11 @@ static struct omap_hwmod_class am33xx_l3_hwmod_class = {
         .name           = "l3",
 };
 
-/* l3_main (l3_fast) */
-static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
-        { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
-        { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_l3_main_hwmod = {
         .name           = "l3_main",
         .class          = &am33xx_l3_hwmod_class,
         .clkdm_name     = "l3_clkdm",
         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_l3_main_irqs,
         .main_clk       = "l3_gclk",
         .prcm           = {
                 .omap4  = {
@@ -196,20 +159,6 @@ static struct omap_hwmod am33xx_l4_wkup_hwmod = {
         },
 };
 
-/* l4_fw */
-static struct omap_hwmod am33xx_l4_fw_hwmod = {
-        .name           = "l4_fw",
-        .class          = &am33xx_l4_hwmod_class,
-        .clkdm_name     = "l4fw_clkdm",
-        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .prcm           = {
-                .omap4  = {
-                        .clkctrl_offs   = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
-                        .modulemode     = MODULEMODE_SWCTRL,
-                },
-        },
-};
-
 /*
  * 'mpu' class
  */
@@ -217,21 +166,11 @@ static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
         .name   = "mpu",
 };
 
-/* mpu */
-static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
-        { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
-        { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
-        { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
-        { .name = "bench", .irq = 3 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &am33xx_mpu_hwmod_class,
         .clkdm_name     = "mpu_clkdm",
         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_mpu_irqs,
         .main_clk       = "dpll_mpu_m2_ck",
         .prcm           = {
                 .omap4  = {
@@ -253,11 +192,6 @@ static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
         { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
 };
 
-static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
-        { .name = "txev", .irq = 78 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 /* wkup_m3  */
 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
         .name           = "wkup_m3",
@@ -265,7 +199,6 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
         .clkdm_name     = "l4_wkup_aon_clkdm",
         /* Keep hardreset asserted */
         .flags          = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
-        .mpu_irqs       = am33xx_wkup_m3_irqs,
         .main_clk       = "dpll_core_m4_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -291,25 +224,12 @@ static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
         { .name = "pruss", .rst_shift = 1 },
 };
 
-static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
-        { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
-        { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
-        { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
-        { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
-        { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
-        { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
-        { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
-        { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 /* pru-icss */
 /* Pseudo hwmod for reset control purpose only */
 static struct omap_hwmod am33xx_pruss_hwmod = {
         .name           = "pruss",
         .class          = &am33xx_pruss_hwmod_class,
         .clkdm_name     = "pruss_ocp_clkdm",
-        .mpu_irqs       = am33xx_pruss_irqs,
         .main_clk       = "pruss_ocp_gclk",
         .prcm           = {
                 .omap4  = {
@@ -329,24 +249,19 @@ static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 };
 
 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
-        { .name = "gfx", .rst_shift = 0 },
-};
-
-static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
-        { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
-        { .irq = -1 },
+        { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 };
 
 static struct omap_hwmod am33xx_gfx_hwmod = {
         .name           = "gfx",
         .class          = &am33xx_gfx_hwmod_class,
         .clkdm_name     = "gfx_l3_clkdm",
-        .mpu_irqs       = am33xx_gfx_irqs,
         .main_clk       = "gfx_fck_div_ck",
         .prcm           = {
                 .omap4  = {
                         .clkctrl_offs   = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
                         .rstctrl_offs   = AM33XX_RM_GFX_RSTCTRL_OFFSET,
+                        .rstst_offs     = AM33XX_RM_GFX_RSTST_OFFSET,
                         .modulemode     = MODULEMODE_SWCTRL,
                 },
         },
@@ -387,16 +302,10 @@ static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
         .sysc           = &am33xx_adc_tsc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
-        { .irq = 16 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
         .name           = "adc_tsc",
         .class          = &am33xx_adc_tsc_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_adc_tsc_irqs,
         .main_clk       = "adc_tsc_fck",
         .prcm           = {
                 .omap4  = {
@@ -515,23 +424,10 @@ static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
         .sysc           = &am33xx_aes0_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
-        { .irq = 103 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 6, },
-        { .name = "rx", .dma_req = 5, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_aes0_hwmod = {
         .name           = "aes",
         .class          = &am33xx_aes0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_aes0_irqs,
-        .sdma_reqs      = am33xx_aes0_edma_reqs,
         .main_clk       = "aes0_fck",
         .prcm           = {
                 .omap4  = {
@@ -554,22 +450,10 @@ static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
         .sysc           = &am33xx_sha0_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
-        { .irq = 109 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
-        { .name = "rx", .dma_req = 36, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_sha0_hwmod = {
         .name           = "sham",
         .class          = &am33xx_sha0_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_sha0_irqs,
-        .sdma_reqs      = am33xx_sha0_edma_reqs,
         .main_clk       = "l3_gclk",
         .prcm           = {
                 .omap4  = {
@@ -604,16 +488,10 @@ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 };
 
 /* smartreflex0 */
-static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
-        { .irq = 120 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
         .name           = "smartreflex0",
         .class          = &am33xx_smartreflex_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_smartreflex0_irqs,
         .main_clk       = "smartreflex0_fck",
         .prcm           = {
                 .omap4  = {
@@ -624,16 +502,10 @@ static struct omap_hwmod am33xx_smartreflex0_hwmod = {
 };
 
 /* smartreflex1 */
-static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
-        { .irq = 121 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
         .name           = "smartreflex1",
         .class          = &am33xx_smartreflex_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_smartreflex1_irqs,
         .main_clk       = "smartreflex1_fck",
         .prcm           = {
                 .omap4  = {
@@ -650,17 +522,11 @@ static struct omap_hwmod_class am33xx_control_hwmod_class = {
         .name           = "control",
 };
 
-static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
-        { .irq = 8 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_control_hwmod = {
         .name           = "control",
         .class          = &am33xx_control_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_control_irqs,
         .main_clk       = "dpll_core_m4_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -690,20 +556,11 @@ static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
         .sysc           = &am33xx_cpgmac_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
-        { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
-        { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
-        { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
-        { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
         .name           = "cpgmac0",
         .class          = &am33xx_cpgmac0_hwmod_class,
         .clkdm_name     = "cpsw_125mhz_clkdm",
         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
-        .mpu_irqs       = am33xx_cpgmac0_irqs,
         .main_clk       = "cpsw_125mhz_gclk",
         .prcm           = {
                 .omap4  = {
@@ -735,17 +592,10 @@ static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 };
 
 /* dcan0 */
-static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
-        { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
-        { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_dcan0_hwmod = {
         .name           = "d_can0",
         .class          = &am33xx_dcan_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_dcan0_irqs,
         .main_clk       = "dcan0_fck",
         .prcm           = {
                 .omap4  = {
@@ -756,16 +606,10 @@ static struct omap_hwmod am33xx_dcan0_hwmod = {
 };
 
 /* dcan1 */
-static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
-        { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
-        { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
 static struct omap_hwmod am33xx_dcan1_hwmod = {
         .name           = "d_can1",
         .class          = &am33xx_dcan_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_dcan1_irqs,
         .main_clk       = "dcan1_fck",
         .prcm           = {
                 .omap4  = {
@@ -792,16 +636,10 @@ static struct omap_hwmod_class am33xx_elm_hwmod_class = {
         .sysc           = &am33xx_elm_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
-        { .irq = 4 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_elm_hwmod = {
         .name           = "elm",
         .class          = &am33xx_elm_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_elm_irqs,
         .main_clk       = "l4ls_gclk",
         .prcm           = {
                 .omap4  = {
@@ -854,45 +692,26 @@ static struct omap_hwmod am33xx_epwmss0_hwmod = {
 };
 
 /* ecap0 */
-static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
-        { .irq = 31 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap0_hwmod = {
         .name           = "ecap0",
         .class          = &am33xx_ecap_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap0_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* eqep0 */
-static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
-        { .irq = 79 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep0_hwmod = {
         .name           = "eqep0",
         .class          = &am33xx_eqep_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep0_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* ehrpwm0 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
-        { .name = "int", .irq = 86 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
         .name           = "ehrpwm0",
         .class          = &am33xx_ehrpwm_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm0_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
@@ -911,45 +730,26 @@ static struct omap_hwmod am33xx_epwmss1_hwmod = {
 };
 
 /* ecap1 */
-static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
-        { .irq = 47 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap1_hwmod = {
         .name           = "ecap1",
         .class          = &am33xx_ecap_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap1_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* eqep1 */
-static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
-        { .irq = 88 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep1_hwmod = {
         .name           = "eqep1",
         .class          = &am33xx_eqep_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep1_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* ehrpwm1 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
-        { .name = "int", .irq = 87 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
         .name           = "ehrpwm1",
         .class          = &am33xx_ehrpwm_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm1_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
@@ -968,45 +768,26 @@ static struct omap_hwmod am33xx_epwmss2_hwmod = {
 };
 
 /* ecap2 */
-static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
-        { .irq = 61 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ecap2_hwmod = {
         .name           = "ecap2",
         .class          = &am33xx_ecap_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ecap2_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* eqep2 */
-static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
-        { .irq = 89 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_eqep2_hwmod = {
         .name           = "eqep2",
         .class          = &am33xx_eqep_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_eqep2_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
 /* ehrpwm2 */
-static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
-        { .name = "int", .irq = 39 + OMAP_INTC_START, },
-        { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
         .name           = "ehrpwm2",
         .class          = &am33xx_ehrpwm_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_ehrpwm2_irqs,
         .main_clk       = "l4ls_gclk",
 };
 
@@ -1041,17 +822,11 @@ static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio0_dbclk" },
 };
 
-static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
-        { .irq = 96 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_gpio0_hwmod = {
         .name           = "gpio1",
         .class          = &am33xx_gpio_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio0_irqs,
         .main_clk       = "dpll_core_m4_div2_ck",
         .prcm           = {
                 .omap4  = {
@@ -1065,11 +840,6 @@ static struct omap_hwmod am33xx_gpio0_hwmod = {
 };
 
 /* gpio1 */
-static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
-        { .irq = 98 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1079,7 +849,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
         .class          = &am33xx_gpio_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio1_irqs,
         .main_clk       = "l4ls_gclk",
         .prcm           = {
                 .omap4  = {
@@ -1093,11 +862,6 @@ static struct omap_hwmod am33xx_gpio1_hwmod = {
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
-        { .irq = 32 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1107,7 +871,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
         .class          = &am33xx_gpio_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio2_irqs,
         .main_clk       = "l4ls_gclk",
         .prcm           = {
                 .omap4  = {
@@ -1121,11 +884,6 @@ static struct omap_hwmod am33xx_gpio2_hwmod = {
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
-        { .irq = 62 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1135,7 +893,6 @@ static struct omap_hwmod am33xx_gpio3_hwmod = {
         .class          = &am33xx_gpio_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = am33xx_gpio3_irqs,
         .main_clk       = "l4ls_gclk",
         .prcm           = {
                 .omap4  = {
@@ -1164,17 +921,11 @@ static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
         .sysc           = &gpmc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
-        { .irq = 100 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &am33xx_gpmc_hwmod_class,
         .clkdm_name     = "l3s_clkdm",
         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
-        .mpu_irqs       = am33xx_gpmc_irqs,
         .main_clk       = "l3s_gclk",
         .prcm           = {
                 .omap4  = {
@@ -1208,23 +959,10 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
-        { .irq = 70 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_i2c1_hwmod = {
         .name           = "i2c1",
         .class          = &i2c_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = i2c1_mpu_irqs,
-        .sdma_reqs      = i2c1_edma_reqs,
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
         .prcm           = {
@@ -1237,23 +975,10 @@ static struct omap_hwmod am33xx_i2c1_hwmod = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
-        { .irq = 71 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_i2c2_hwmod = {
         .name           = "i2c2",
         .class          = &i2c_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = i2c2_mpu_irqs,
-        .sdma_reqs      = i2c2_edma_reqs,
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
@@ -1266,23 +991,10 @@ static struct omap_hwmod am33xx_i2c2_hwmod = {
 };
 
 /* i2c3 */
-static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
-        { .name = "tx", .dma_req = 0, },
-        { .name = "rx", .dma_req = 0, },
-        { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
-        { .irq = 30 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_i2c3_hwmod = {
         .name           = "i2c3",
         .class          = &i2c_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = i2c3_mpu_irqs,
-        .sdma_reqs      = i2c3_edma_reqs,
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
@@ -1309,16 +1021,10 @@ static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
         .sysc           = &lcdc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
-        { .irq = 36 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_lcdc_hwmod = {
         .name           = "lcdc",
         .class          = &am33xx_lcdc_hwmod_class,
         .clkdm_name     = "lcdc_clkdm",
-        .mpu_irqs       = am33xx_lcdc_irqs,
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
         .main_clk       = "lcd_gclk",
         .prcm           = {
@@ -1348,16 +1054,10 @@ static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
         .sysc   = &am33xx_mailbox_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
-        { .irq = 77 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &am33xx_mailbox_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mailbox_irqs,
         .main_clk       = "l4ls_gclk",
         .prcm = {
                 .omap4 = {
@@ -1384,24 +1084,10 @@ static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 };
 
 /* mcasp0 */
-static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
-        { .name = "ax", .irq = 80 + OMAP_INTC_START, },
-        { .name = "ar", .irq = 81 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 8, },
-        { .name = "rx", .dma_req = 9, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_mcasp0_hwmod = {
         .name           = "mcasp0",
         .class          = &am33xx_mcasp_hwmod_class,
         .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mcasp0_irqs,
-        .sdma_reqs      = am33xx_mcasp0_edma_reqs,
         .main_clk       = "mcasp0_fck",
         .prcm           = {
                 .omap4  = {
@@ -1412,24 +1098,10 @@ static struct omap_hwmod am33xx_mcasp0_hwmod = {
 };
 
 /* mcasp1 */
-static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
-        { .name = "ax", .irq = 82 + OMAP_INTC_START, },
-        { .name = "ar", .irq = 83 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 10, },
-        { .name = "rx", .dma_req = 11, },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_mcasp1_hwmod = {
         .name           = "mcasp1",
         .class          = &am33xx_mcasp_hwmod_class,
         .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mcasp1_irqs,
-        .sdma_reqs      = am33xx_mcasp1_edma_reqs,
         .main_clk       = "mcasp1_fck",
         .prcm           = {
                 .omap4  = {
@@ -1457,17 +1129,6 @@ static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 };
 
 /* mmc0 */
-static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
-        { .irq = 64 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
-        { .name = "tx", .dma_req = 24, },
-        { .name = "rx", .dma_req = 25, },
-        { .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1476,8 +1137,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
         .name           = "mmc1",
         .class          = &am33xx_mmc_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mmc0_irqs,
-        .sdma_reqs      = am33xx_mmc0_edma_reqs,
         .main_clk       = "mmc_clk",
         .prcm           = {
                 .omap4  = {
@@ -1489,17 +1148,6 @@ static struct omap_hwmod am33xx_mmc0_hwmod = {
 };
 
 /* mmc1 */
-static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
-        { .irq = 28 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 2, },
-        { .name = "rx", .dma_req = 3, },
-        { .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1508,8 +1156,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
         .name           = "mmc2",
         .class          = &am33xx_mmc_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_mmc1_irqs,
-        .sdma_reqs      = am33xx_mmc1_edma_reqs,
         .main_clk       = "mmc_clk",
         .prcm           = {
                 .omap4  = {
@@ -1521,17 +1167,6 @@ static struct omap_hwmod am33xx_mmc1_hwmod = {
 };
 
 /* mmc2 */
-static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
-        { .irq = 29 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
-        { .name = "tx", .dma_req = 64, },
-        { .name = "rx", .dma_req = 65, },
-        { .dma_req = -1 }
-};
-
 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
@@ -1539,8 +1174,6 @@ static struct omap_hwmod am33xx_mmc2_hwmod = {
         .name           = "mmc3",
         .class          = &am33xx_mmc_hwmod_class,
         .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_mmc2_irqs,
-        .sdma_reqs      = am33xx_mmc2_edma_reqs,
         .main_clk       = "mmc_clk",
         .prcm           = {
                 .omap4  = {
@@ -1569,17 +1202,10 @@ static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
         .sysc           = &am33xx_rtc_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
-        { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
-        { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_rtc_hwmod = {
         .name           = "rtc",
         .class          = &am33xx_rtc_hwmod_class,
         .clkdm_name     = "l4_rtc_clkdm",
-        .mpu_irqs       = am33xx_rtc_irqs,
         .main_clk       = "clk_32768_ck",
         .prcm           = {
                 .omap4  = {
@@ -1608,19 +1234,6 @@ static struct omap_hwmod_class am33xx_spi_hwmod_class = {
 };
 
 /* spi0 */
-static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
-        { .irq = 65 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
-        { .name = "rx0", .dma_req = 17 },
-        { .name = "tx0", .dma_req = 16 },
-        { .name = "rx1", .dma_req = 19 },
-        { .name = "tx1", .dma_req = 18 },
-        { .dma_req = -1 }
-};
-
 static struct omap2_mcspi_dev_attr mcspi_attrib = {
         .num_chipselect = 2,
 };
@@ -1628,8 +1241,6 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
         .name           = "spi0",
         .class          = &am33xx_spi_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_spi0_irqs,
-        .sdma_reqs      = am33xx_mcspi0_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -1641,25 +1252,10 @@ static struct omap_hwmod am33xx_spi0_hwmod = {
 };
 
 /* spi1 */
-static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
-        { .irq = 125 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
-static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
-        { .name = "rx0", .dma_req = 43 },
-        { .name = "tx0", .dma_req = 42 },
-        { .name = "rx1", .dma_req = 45 },
-        { .name = "tx1", .dma_req = 44 },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod am33xx_spi1_hwmod = {
         .name           = "spi1",
         .class          = &am33xx_spi_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_spi1_irqs,
-        .sdma_reqs      = am33xx_mcspi1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -1725,16 +1321,10 @@ static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
         .sysc           = &am33xx_timer1ms_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
-        { .irq = 67 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer1_hwmod = {
         .name           = "timer1",
         .class          = &am33xx_timer1ms_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = am33xx_timer1_irqs,
         .main_clk       = "timer1_fck",
         .prcm           = {
                 .omap4  = {
@@ -1744,16 +1334,10 @@ static struct omap_hwmod am33xx_timer1_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
-        { .irq = 68 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer2_hwmod = {
         .name           = "timer2",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer2_irqs,
         .main_clk       = "timer2_fck",
         .prcm           = {
                 .omap4  = {
@@ -1763,16 +1347,10 @@ static struct omap_hwmod am33xx_timer2_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
-        { .irq = 69 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer3_hwmod = {
         .name           = "timer3",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer3_irqs,
         .main_clk       = "timer3_fck",
         .prcm           = {
                 .omap4  = {
@@ -1782,16 +1360,10 @@ static struct omap_hwmod am33xx_timer3_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
-        { .irq = 92 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer4_hwmod = {
         .name           = "timer4",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer4_irqs,
         .main_clk       = "timer4_fck",
         .prcm           = {
                 .omap4  = {
@@ -1801,16 +1373,10 @@ static struct omap_hwmod am33xx_timer4_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
-        { .irq = 93 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer5_hwmod = {
         .name           = "timer5",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer5_irqs,
         .main_clk       = "timer5_fck",
         .prcm           = {
                 .omap4  = {
@@ -1820,16 +1386,10 @@ static struct omap_hwmod am33xx_timer5_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
-        { .irq = 94 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer6_hwmod = {
         .name           = "timer6",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer6_irqs,
         .main_clk       = "timer6_fck",
         .prcm           = {
                 .omap4  = {
@@ -1839,16 +1399,10 @@ static struct omap_hwmod am33xx_timer6_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
-        { .irq = 95 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_timer7_hwmod = {
         .name           = "timer7",
         .class          = &am33xx_timer_hwmod_class,
         .clkdm_name     = "l4ls_clkdm",
-        .mpu_irqs       = am33xx_timer7_irqs,
         .main_clk       = "timer7_fck",
         .prcm           = {
                 .omap4  = {
@@ -1863,18 +1417,10 @@ static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
         .name           = "tpcc",
 };
 
-static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
-        { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
-        { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
-        { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tpcc_hwmod = {
         .name           = "tpcc",
         .class          = &am33xx_tpcc_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tpcc_irqs,
         .main_clk       = "l3_gclk",
         .prcm           = {
                 .omap4  = {
@@ -1900,16 +1446,10 @@ static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
 };
 
 /* tptc0 */
-static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
-        { .irq = 112 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc0_hwmod = {
         .name           = "tptc0",
         .class          = &am33xx_tptc_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc0_irqs,
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
         .main_clk       = "l3_gclk",
         .prcm           = {
@@ -1921,16 +1461,10 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
 };
 
 /* tptc1 */
-static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
-        { .irq = 113 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc1_hwmod = {
         .name           = "tptc1",
         .class          = &am33xx_tptc_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc1_irqs,
         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
         .main_clk       = "l3_gclk",
         .prcm           = {
@@ -1942,16 +1476,10 @@ static struct omap_hwmod am33xx_tptc1_hwmod = {
 };
 
 /* tptc2 */
-static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
-        { .irq = 114 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_tptc2_hwmod = {
         .name           = "tptc2",
         .class          = &am33xx_tptc_hwmod_class,
         .clkdm_name     = "l3_clkdm",
-        .mpu_irqs       = am33xx_tptc2_irqs,
         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
         .main_clk       = "l3_gclk",
         .prcm           = {
@@ -1980,24 +1508,11 @@ static struct omap_hwmod_class uart_class = {
 };
 
 /* uart1 */
-static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
-        { .name = "tx", .dma_req = 26, },
-        { .name = "rx", .dma_req = 27, },
-        { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
-        { .irq = 72 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart1_hwmod = {
         .name           = "uart1",
         .class          = &uart_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart1_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
         .prcm           = {
                 .omap4  = {
@@ -2007,18 +1522,11 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
-        { .irq = 73 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart2_hwmod = {
         .name           = "uart2",
         .class          = &uart_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart2_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -2029,24 +1537,11 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
 };
 
 /* uart3 */
-static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
-        { .name = "tx", .dma_req = 30, },
-        { .name = "rx", .dma_req = 31, },
-        { .dma_req = -1 }
-};
-
-static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
-        { .irq = 74 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart3_hwmod = {
         .name           = "uart3",
         .class          = &uart_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart3_irqs,
-        .sdma_reqs      = uart3_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -2056,18 +1551,11 @@ static struct omap_hwmod am33xx_uart3_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
-        { .irq = 44 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart4_hwmod = {
         .name           = "uart4",
         .class          = &uart_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart4_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -2077,18 +1565,11 @@ static struct omap_hwmod am33xx_uart4_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
-        { .irq = 45 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart5_hwmod = {
         .name           = "uart5",
         .class          = &uart_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart5_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -2098,18 +1579,11 @@ static struct omap_hwmod am33xx_uart5_hwmod = {
         },
 };
 
-static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
-        { .irq = 46 + OMAP_INTC_START, },
-        { .irq = -1 },
-};
-
 static struct omap_hwmod am33xx_uart6_hwmod = {
         .name           = "uart6",
         .class          = &uart_class,
         .clkdm_name     = "l4ls_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = am33xx_uart6_irqs,
-        .sdma_reqs      = uart1_edma_reqs,
         .main_clk       = "dpll_per_m2_div4_ck",
         .prcm           = {
                 .omap4  = {
@@ -2173,18 +1647,10 @@ static struct omap_hwmod_class am33xx_usbotg_class = {
         .sysc           = &am33xx_usbhsotg_sysc,
 };
 
-static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
-        { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
-        { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
-        { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
-        { .irq = -1, },
-};
-
 static struct omap_hwmod am33xx_usbss_hwmod = {
         .name           = "usb_otg_hs",
         .class          = &am33xx_usbotg_class,
         .clkdm_name     = "l3s_clkdm",
-        .mpu_irqs       = am33xx_usbss_mpu_irqs,
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
         .main_clk       = "usbotg_fck",
         .prcm           = {
@@ -2200,14 +1666,6 @@ static struct omap_hwmod am33xx_usbss_hwmod = {
  * Interfaces
  */
 
-/* l4 fw -> emif fw */
-static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
-        .master         = &am33xx_l4_fw_hwmod,
-        .slave          = &am33xx_emif_fw_hwmod,
-        .clk            = "l4fw_gclk",
-        .user           = OCP_USER_MPU,
-};
-
 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
         {
                 .pa_start       = 0x4c000000,
@@ -2265,14 +1723,6 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-/* l3 s -> l4 fw */
-static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_l4_fw_hwmod,
-        .clk            = "l3s_gclk",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3 main -> l3 instr */
 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
         .master         = &am33xx_l3_main_hwmod,
@@ -2322,261 +1772,114 @@ static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
 };
 
 /* l4 wkup -> wkup m3 */
-static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
-        {
-                .name           = "umem",
-                .pa_start       = 0x44d00000,
-                .pa_end         = 0x44d00000 + SZ_16K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "dmem",
-                .pa_start       = 0x44d80000,
-                .pa_end         = 0x44d80000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_wkup_m3_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_wkup_m3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 hs -> pru-icss */
-static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
-        {
-                .pa_start       = 0x4a300000,
-                .pa_end         = 0x4a300000 + SZ_512K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
         .master         = &am33xx_l4_hs_hwmod,
         .slave          = &am33xx_pruss_hwmod,
         .clk            = "dpll_core_m4_ck",
-        .addr           = am33xx_pruss_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l3 main -> gfx */
-static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
-        {
-                .pa_start       = 0x56000000,
-                .pa_end         = 0x56000000 + SZ_16M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
         .master         = &am33xx_l3_main_hwmod,
         .slave          = &am33xx_gfx_hwmod,
         .clk            = "dpll_core_m4_ck",
-        .addr           = am33xx_gfx_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 wkup -> smartreflex0 */
-static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
-        {
-                .pa_start       = 0x44e37000,
-                .pa_end         = 0x44e37000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_smartreflex0_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_smartreflex0_addrs,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 wkup -> smartreflex1 */
-static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
-        {
-                .pa_start       = 0x44e39000,
-                .pa_end         = 0x44e39000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_smartreflex1_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_smartreflex1_addrs,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 wkup -> control */
-static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
-        {
-                .pa_start       = 0x44e10000,
-                .pa_end         = 0x44e10000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_control_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_control_addrs,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 wkup -> rtc */
-static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
-        {
-                .pa_start       = 0x44e3e000,
-                .pa_end         = 0x44e3e000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_rtc_hwmod,
         .clk            = "clkdiv32k_ick",
-        .addr           = am33xx_rtc_addrs,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per/ls -> DCAN0 */
-static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
-        {
-                .pa_start       = 0x481CC000,
-                .pa_end         = 0x481CC000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_dcan0_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_dcan0_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> DCAN1 */
-static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
-        {
-                .pa_start       = 0x481D0000,
-                .pa_end         = 0x481D0000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_dcan1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_dcan1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> GPIO2 */
-static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4804C000,
-                .pa_end         = 0x4804C000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_gpio1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> gpio3 */
-static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x481AC000,
-                .pa_end         = 0x481AC000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_gpio2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* l4 per/ls -> gpio4 */
-static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x481AE000,
-                .pa_end         = 0x481AE000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_gpio3_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_gpio3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
 /* L4 WKUP -> I2C1 */
-static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
-        {
-                .pa_start       = 0x44E0B000,
-                .pa_end         = 0x44E0B000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_i2c1_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_i2c1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* L4 WKUP -> GPIO1 */
-static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
-        {
-                .pa_start       = 0x44E07000,
-                .pa_end         = 0x44E07000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_gpio0_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_gpio0_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2598,41 +1901,16 @@ static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
-        /* cpsw ss */
-        {
-                .pa_start       = 0x4a100000,
-                .pa_end         = 0x4a100000 + SZ_2K - 1,
-        },
-        /* cpsw wr */
-        {
-                .pa_start       = 0x4a101200,
-                .pa_end         = 0x4a101200 + SZ_256 - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
         .master         = &am33xx_l4_hs_hwmod,
         .slave          = &am33xx_cpgmac0_hwmod,
         .clk            = "cpsw_125mhz_gclk",
-        .addr           = am33xx_cpgmac0_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
-        {
-                .pa_start       = 0x4A101000,
-                .pa_end         = 0x4A101000 + SZ_256 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
         .master         = &am33xx_cpgmac0_hwmod,
         .slave          = &am33xx_mdio_hwmod,
-        .addr           = am33xx_mdio_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -2670,51 +1948,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
-        {
-                .pa_start       = 0x48300100,
-                .pa_end         = 0x48300100 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
         .master         = &am33xx_epwmss0_hwmod,
         .slave          = &am33xx_ecap0_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap0_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
-        {
-                .pa_start       = 0x48300180,
-                .pa_end         = 0x48300180 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
         .master         = &am33xx_epwmss0_hwmod,
         .slave          = &am33xx_eqep0_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep0_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
-        {
-                .pa_start       = 0x48300200,
-                .pa_end         = 0x48300200 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
         .master         = &am33xx_epwmss0_hwmod,
         .slave          = &am33xx_ehrpwm0_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm0_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -2736,51 +1987,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
-        {
-                .pa_start       = 0x48302100,
-                .pa_end         = 0x48302100 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
         .master         = &am33xx_epwmss1_hwmod,
         .slave          = &am33xx_ecap1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
-        {
-                .pa_start       = 0x48302180,
-                .pa_end         = 0x48302180 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
         .master         = &am33xx_epwmss1_hwmod,
         .slave          = &am33xx_eqep1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
-        {
-                .pa_start       = 0x48302200,
-                .pa_end         = 0x48302200 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
         .master         = &am33xx_epwmss1_hwmod,
         .slave          = &am33xx_ehrpwm1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -2801,51 +2025,24 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
-        {
-                .pa_start       = 0x48304100,
-                .pa_end         = 0x48304100 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
         .master         = &am33xx_epwmss2_hwmod,
         .slave          = &am33xx_ecap2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ecap2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
-        {
-                .pa_start       = 0x48304180,
-                .pa_end         = 0x48304180 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
         .master         = &am33xx_epwmss2_hwmod,
         .slave          = &am33xx_eqep2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_eqep2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
-        {
-                .pa_start       = 0x48304200,
-                .pa_end         = 0x48304200 + SZ_128 - 1,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
         .master         = &am33xx_epwmss2_hwmod,
         .slave          = &am33xx_ehrpwm2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_ehrpwm2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -2868,37 +2065,17 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
 };
 
 /* i2c2 */
-static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
-        {
-                .pa_start       = 0x4802A000,
-                .pa_end         = 0x4802A000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_i2c2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_i2c2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
-        {
-                .pa_start       = 0x4819C000,
-                .pa_end         = 0x4819C000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_i2c3_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_i2c3_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -2938,20 +2115,10 @@ static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
 };
 
 /* l4 ls -> spinlock */
-static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
-        {
-                .pa_start       = 0x480Ca000,
-                .pa_end         = 0x480Ca000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_spinlock_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_spinlock_addrs,
         .user           = OCP_USER_MPU,
 };
 
@@ -2973,24 +2140,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l3 s -> mcasp0 data */
-static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
-        {
-                .pa_start       = 0x46000000,
-                .pa_end         = 0x46000000 + SZ_4M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mcasp0_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_mcasp0_data_addr_space,
-        .user           = OCP_USER_SDMA,
-};
-
 /* l4 ls -> mcasp1 */
 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
         {
@@ -3009,24 +2158,6 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
         .user           = OCP_USER_MPU,
 };
 
-/* l3 s -> mcasp1 data */
-static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
-        {
-                .pa_start       = 0x46400000,
-                .pa_end         = 0x46400000 + SZ_4M - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
-        .master         = &am33xx_l3_s_hwmod,
-        .slave          = &am33xx_mcasp1_hwmod,
-        .clk            = "l3s_gclk",
-        .addr           = am33xx_mcasp1_data_addr_space,
-        .user           = OCP_USER_SDMA,
-};
-
 /* l4 ls -> mmc0 */
 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
         {
@@ -3082,182 +2213,82 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
 };
 
 /* l4 ls -> mcspi0 */
-static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
-        {
-                .pa_start       = 0x48030000,
-                .pa_end         = 0x48030000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_spi0_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcspi0_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> mcspi1 */
-static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
-        {
-                .pa_start       = 0x481A0000,
-                .pa_end         = 0x481A0000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_spi1_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_mcspi1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 wkup -> timer1 */
-static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
-        {
-                .pa_start       = 0x44E31000,
-                .pa_end         = 0x44E31000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_timer1_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_timer1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer2 */
-static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
-        {
-                .pa_start       = 0x48040000,
-                .pa_end         = 0x48040000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer3 */
-static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
-        {
-                .pa_start       = 0x48042000,
-                .pa_end         = 0x48042000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer3_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer3_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer4 */
-static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
-        {
-                .pa_start       = 0x48044000,
-                .pa_end         = 0x48044000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer4_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer4_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer5 */
-static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
-        {
-                .pa_start       = 0x48046000,
-                .pa_end         = 0x48046000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer5_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer5_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer6 */
-static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
-        {
-                .pa_start       = 0x48048000,
-                .pa_end         = 0x48048000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer6_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer6_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 per -> timer7 */
-static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
-        {
-                .pa_start       = 0x4804A000,
-                .pa_end         = 0x4804A000 + SZ_1K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_timer7_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_timer7_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l3 main -> tpcc */
-static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
-        {
-                .pa_start       = 0x49000000,
-                .pa_end         = 0x49000000 + SZ_32K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
         .master         = &am33xx_l3_main_hwmod,
         .slave          = &am33xx_tpcc_hwmod,
         .clk            = "l3_gclk",
-        .addr           = am33xx_tpcc_addr_space,
         .user           = OCP_USER_MPU,
 };
 
@@ -3316,160 +2347,67 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
 };
 
 /* l4 wkup -> uart1 */
-static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
-        {
-                .pa_start       = 0x44E09000,
-                .pa_end         = 0x44E09000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_uart1_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_uart1_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> uart2 */
-static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
-        {
-                .pa_start       = 0x48022000,
-                .pa_end         = 0x48022000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_uart2_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart2_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> uart3 */
-static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
-        {
-                .pa_start       = 0x48024000,
-                .pa_end         = 0x48024000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_uart3_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart3_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> uart4 */
-static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
-        {
-                .pa_start       = 0x481A6000,
-                .pa_end         = 0x481A6000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_uart4_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart4_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> uart5 */
-static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
-        {
-                .pa_start       = 0x481A8000,
-                .pa_end         = 0x481A8000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_uart5_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart5_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 ls -> uart6 */
-static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
-        {
-                .pa_start       = 0x481aa000,
-                .pa_end         = 0x481aa000 + SZ_8K - 1,
-                .flags          = ADDR_TYPE_RT,
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
         .master         = &am33xx_l4_ls_hwmod,
         .slave          = &am33xx_uart6_hwmod,
         .clk            = "l4ls_gclk",
-        .addr           = am33xx_uart6_addr_space,
         .user           = OCP_USER_MPU,
 };
 
 /* l4 wkup -> wd_timer1 */
-static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
-        {
-                .pa_start       = 0x44e35000,
-                .pa_end         = 0x44e35000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
         .master         = &am33xx_l4_wkup_hwmod,
         .slave          = &am33xx_wd_timer1_hwmod,
         .clk            = "dpll_core_m4_div2_ck",
-        .addr           = am33xx_wd_timer1_addrs,
         .user           = OCP_USER_MPU,
 };
 
 /* usbss */
 /* l3 s -> USBSS interface */
-static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
-        {
-                .name           = "usbss",
-                .pa_start       = 0x47400000,
-                .pa_end         = 0x47400000 + SZ_4K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "musb0",
-                .pa_start       = 0x47401000,
-                .pa_end         = 0x47401000 + SZ_2K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "musb1",
-                .pa_start       = 0x47401800,
-                .pa_end         = 0x47401800 + SZ_2K - 1,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
         .master         = &am33xx_l3_s_hwmod,
         .slave          = &am33xx_usbss_hwmod,
         .clk            = "l3s_gclk",
-        .addr           = am33xx_usbss_addr_space,
         .user           = OCP_USER_MPU,
         .flags          = OCPIF_SWSUP_IDLE,
 };
@@ -3518,13 +2456,11 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
 };
 
 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
-        &am33xx_l4_fw__emif_fw,
         &am33xx_l3_main__emif,
         &am33xx_mpu__l3_main,
         &am33xx_mpu__prcm,
         &am33xx_l3_s__l4_ls,
         &am33xx_l3_s__l4_wkup,
-        &am33xx_l3_s__l4_fw,
         &am33xx_l3_main__l4_hs,
         &am33xx_l3_main__l3_s,
         &am33xx_l3_main__l3_instr,
@@ -3554,9 +2490,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
         &am33xx_l4_per__i2c3,
         &am33xx_l4_per__mailbox,
         &am33xx_l4_ls__mcasp0,
-        &am33xx_l3_s__mcasp0_data,
         &am33xx_l4_ls__mcasp1,
-        &am33xx_l3_s__mcasp1_data,
         &am33xx_l4_ls__mmc0,
         &am33xx_l4_ls__mmc1,
         &am33xx_l3_s__mmc2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 31c7126eb3bb..f7a3df2fb579 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,6 +25,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <linux/platform_data/iommu-omap.h>
+#include <linux/platform_data/mailbox-omap.h>
 #include <plat/dmtimer.h>
 
 #include "am35xx.h"
@@ -35,7 +36,6 @@
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 
-#include "dma.h"
 #include "i2c.h"
 #include "mmc.h"
 #include "wd_timer.h"
@@ -548,8 +548,8 @@ static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 };
 
 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
-        { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+        { .name = "rx", .dma_req = 82, },
+        { .name = "tx", .dma_req = 81, },
         { .dma_req = -1 }
 };
 
@@ -577,8 +577,8 @@ static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 };
 
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
-        { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
-        { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+        { .name = "rx", .dma_req = 55, },
+        { .name = "tx", .dma_req = 54, },
         { .dma_req = -1 }
 };
 
@@ -857,8 +857,8 @@ static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 };
 
 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
-        { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+        { .name = "tx", .dma_req = 25 },
+        { .name = "rx", .dma_req = 26 },
         { .dma_req = -1 }
 };
 
@@ -1505,6 +1505,17 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
         .sysc = &omap3xxx_mailbox_sysc,
 };
 
+static struct omap_mbox_dev_info omap3xxx_mailbox_info[] = {
+        { .name = "dsp", .tx_id = 0, .rx_id = 1 },
+};
+
+static struct omap_mbox_pdata omap3xxx_mailbox_attrs = {
+        .num_users      = 2,
+        .num_fifos      = 2,
+        .info_cnt       = ARRAY_SIZE(omap3xxx_mailbox_info),
+        .info           = omap3xxx_mailbox_info,
+};
+
 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
         { .irq = 26 + OMAP_INTC_START, },
         { .irq = -1 },
@@ -1524,6 +1535,7 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
                 },
         },
+        .dev_attr       = &omap3xxx_mailbox_attrs,
 };
 
 /*
@@ -3581,7 +3593,7 @@ static struct omap_hwmod_irq_info omap3_sham_mpu_irqs[] = {
 };
 
 static struct omap_hwmod_dma_info omap3_sham_sdma_reqs[] = {
-        { .name = "rx", .dma_req = OMAP34XX_DMA_SHA1MD5_RX, },
+        { .name = "rx", .dma_req = 69, },
         { .dma_req = -1 }
 };
 
@@ -3642,8 +3654,8 @@ static struct omap_hwmod_class omap3xxx_aes_class = {
 };
 
 static struct omap_hwmod_dma_info omap3_aes_sdma_reqs[] = {
-        { .name = "tx", .dma_req = OMAP34XX_DMA_AES2_TX, },
-        { .name = "rx", .dma_req = OMAP34XX_DMA_AES2_RX, },
+        { .name = "tx", .dma_req = 65, },
+        { .name = "rx", .dma_req = 66, },
         { .dma_req = -1 }
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 848b6dc67590..d04b5e60fdbe 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -12,6 +12,8 @@
  * with the public linux-omap@vger.kernel.org mailing list and the
  * authors above to ensure that the autogeneration scripts are kept
  * up-to-date with the file contents.
+ * Note that this file is currently not in sync with autogeneration scripts.
+ * The above note to be removed, once it is synced up.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +23,6 @@
 #include <linux/io.h>
 #include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
-#include <linux/platform_data/omap_ocp2scp.h>
 #include <linux/i2c-omap.h>
 
 #include <linux/omap-dma.h>
@@ -52,27 +53,6 @@
  */
 
 /*
- * 'c2c_target_fw' class
- * instance(s): c2c_target_fw
- */
-static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
-        .name   = "c2c_target_fw",
-};
-
-/* c2c_target_fw */
-static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
-        .name           = "c2c_target_fw",
-        .class          = &omap44xx_c2c_target_fw_hwmod_class,
-        .clkdm_name     = "d2d_clkdm",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
-                },
-        },
-};
-
-/*
  * 'dmm' class
  * instance(s): dmm
  */
@@ -81,16 +61,10 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
 };
 
 /* dmm */
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
-        { .irq = 113 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_dmm_hwmod = {
         .name           = "dmm",
         .class          = &omap44xx_dmm_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
-        .mpu_irqs       = omap44xx_dmm_irqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
@@ -100,27 +74,6 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
 };
 
 /*
- * 'emif_fw' class
- * instance(s): emif_fw
- */
-static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
-        .name   = "emif_fw",
-};
-
-/* emif_fw */
-static struct omap_hwmod omap44xx_emif_fw_hwmod = {
-        .name           = "emif_fw",
-        .class          = &omap44xx_emif_fw_hwmod_class,
-        .clkdm_name     = "l3_emif_clkdm",
-        .prcm = {
-                .omap4 = {
-                        .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
-                        .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
-                },
-        },
-};
-
-/*
  * 'l3' class
  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  */
@@ -143,17 +96,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 };
 
 /* l3_main_1 */
-static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
-        { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
-        { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
         .name           = "l3_main_1",
         .class          = &omap44xx_l3_hwmod_class,
         .clkdm_name     = "l3_1_clkdm",
-        .mpu_irqs       = omap44xx_l3_main_1_irqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
@@ -326,29 +272,10 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 };
 
 /* aess */
-static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
-        { .irq = 99 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
-        { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
-        { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_aess_hwmod = {
         .name           = "aess",
         .class          = &omap44xx_aess_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_aess_irqs,
-        .sdma_reqs      = omap44xx_aess_sdma_reqs,
         .main_clk       = "aess_fclk",
         .prcm = {
                 .omap4 = {
@@ -371,22 +298,10 @@ static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 };
 
 /* c2c */
-static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
-        { .irq = 88 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
-        { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_c2c_hwmod = {
         .name           = "c2c",
         .class          = &omap44xx_c2c_hwmod_class,
         .clkdm_name     = "d2d_clkdm",
-        .mpu_irqs       = omap44xx_c2c_irqs,
-        .sdma_reqs      = omap44xx_c2c_sdma_reqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
@@ -449,16 +364,10 @@ static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 };
 
 /* ctrl_module_core */
-static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
-        { .irq = 8 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
         .name           = "ctrl_module_core",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
-        .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
         .prcm = {
                 .omap4 = {
                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
@@ -601,22 +510,10 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 };
 
 /* dmic */
-static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
-        { .irq = 114 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
-        { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_dmic_hwmod = {
         .name           = "dmic",
         .class          = &omap44xx_dmic_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_dmic_irqs,
-        .sdma_reqs      = omap44xx_dmic_sdma_reqs,
         .main_clk       = "func_dmic_abe_gfclk",
         .prcm = {
                 .omap4 = {
@@ -637,11 +534,6 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 };
 
 /* dsp */
-static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
-        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
         { .name = "dsp", .rst_shift = 0 },
 };
@@ -650,7 +542,6 @@ static struct omap_hwmod omap44xx_dsp_hwmod = {
         .name           = "dsp",
         .class          = &omap44xx_dsp_hwmod_class,
         .clkdm_name     = "tesla_clkdm",
-        .mpu_irqs       = omap44xx_dsp_irqs,
         .rst_lines      = omap44xx_dsp_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
         .main_clk       = "dpll_iva_m4x2_ck",
@@ -992,16 +883,10 @@ static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 };
 
 /* elm */
-static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
-        { .irq = 4 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_elm_hwmod = {
         .name           = "elm",
         .class          = &omap44xx_elm_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_elm_irqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
@@ -1025,17 +910,11 @@ static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 };
 
 /* emif1 */
-static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
-        { .irq = 110 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_emif1_hwmod = {
         .name           = "emif1",
         .class          = &omap44xx_emif_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_emif1_irqs,
         .main_clk       = "ddrphy_ck",
         .prcm = {
                 .omap4 = {
@@ -1047,17 +926,11 @@ static struct omap_hwmod omap44xx_emif1_hwmod = {
 };
 
 /* emif2 */
-static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
-        { .irq = 111 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_emif2_hwmod = {
         .name           = "emif2",
         .class          = &omap44xx_emif_hwmod_class,
         .clkdm_name     = "l3_emif_clkdm",
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_emif2_irqs,
         .main_clk       = "ddrphy_ck",
         .prcm = {
                 .omap4 = {
@@ -1098,16 +971,10 @@ static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
 };
 
 /* fdif */
-static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
-        { .irq = 69 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_fdif_hwmod = {
         .name           = "fdif",
         .class          = &omap44xx_fdif_hwmod_class,
         .clkdm_name     = "iss_clkdm",
-        .mpu_irqs       = omap44xx_fdif_irqs,
         .main_clk       = "fdif_fck",
         .prcm = {
                 .omap4 = {
@@ -1148,11 +1015,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
 };
 
 /* gpio1 */
-static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
-        { .irq = 29 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio1_dbclk" },
 };
@@ -1161,7 +1023,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
         .name           = "gpio1",
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_gpio1_irqs,
         .main_clk       = "l4_wkup_clk_mux_ck",
         .prcm = {
                 .omap4 = {
@@ -1176,11 +1037,6 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
 };
 
 /* gpio2 */
-static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
-        { .irq = 30 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio2_dbclk" },
 };
@@ -1190,7 +1046,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio2_irqs,
         .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
@@ -1205,11 +1060,6 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
 };
 
 /* gpio3 */
-static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
-        { .irq = 31 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio3_dbclk" },
 };
@@ -1219,7 +1069,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio3_irqs,
         .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
@@ -1234,11 +1083,6 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
 };
 
 /* gpio4 */
-static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
-        { .irq = 32 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio4_dbclk" },
 };
@@ -1248,7 +1092,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio4_irqs,
         .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
@@ -1263,11 +1106,6 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
 };
 
 /* gpio5 */
-static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
-        { .irq = 33 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio5_dbclk" },
 };
@@ -1277,7 +1115,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio5_irqs,
         .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
@@ -1292,11 +1129,6 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
 };
 
 /* gpio6 */
-static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
-        { .irq = 34 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
         { .role = "dbclk", .clk = "gpio6_dbclk" },
 };
@@ -1306,7 +1138,6 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
         .class          = &omap44xx_gpio_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
-        .mpu_irqs       = omap44xx_gpio6_irqs,
         .main_clk       = "l4_div_ck",
         .prcm = {
                 .omap4 = {
@@ -1341,16 +1172,6 @@ static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
 };
 
 /* gpmc */
-static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
-        { .irq = 20 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
-        { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &omap44xx_gpmc_hwmod_class,
@@ -1364,8 +1185,6 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
          * HWMOD_INIT_NO_RESET should be removed ASAP.
          */
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_gpmc_irqs,
-        .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
@@ -1396,16 +1215,10 @@ static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
 };
 
 /* gpu */
-static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
-        { .irq = 21 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_gpu_hwmod = {
         .name           = "gpu",
         .class          = &omap44xx_gpu_hwmod_class,
         .clkdm_name     = "l3_gfx_clkdm",
-        .mpu_irqs       = omap44xx_gpu_irqs,
         .main_clk       = "sgx_clk_mux",
         .prcm = {
                 .omap4 = {
@@ -1436,17 +1249,11 @@ static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
 };
 
 /* hdq1w */
-static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
-        { .irq = 58 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
         .name           = "hdq1w",
         .class          = &omap44xx_hdq1w_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
-        .mpu_irqs       = omap44xx_hdq1w_irqs,
         .main_clk       = "func_12m_fclk",
         .prcm = {
                 .omap4 = {
@@ -1482,18 +1289,10 @@ static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
 };
 
 /* hsi */
-static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
-        { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_hsi_hwmod = {
         .name           = "hsi",
         .class          = &omap44xx_hsi_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_hsi_irqs,
         .main_clk       = "hsi_fck",
         .prcm = {
                 .omap4 = {
@@ -1533,24 +1332,11 @@ static struct omap_i2c_dev_attr i2c_dev_attr = {
 };
 
 /* i2c1 */
-static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
-        { .irq = 56 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c1_hwmod = {
         .name           = "i2c1",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c1_irqs,
-        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
         .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
@@ -1563,24 +1349,11 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
 };
 
 /* i2c2 */
-static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
-        { .irq = 57 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c2_hwmod = {
         .name           = "i2c2",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c2_irqs,
-        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
         .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
@@ -1593,24 +1366,11 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
 };
 
 /* i2c3 */
-static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
-        { .irq = 61 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c3_hwmod = {
         .name           = "i2c3",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c3_irqs,
-        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
         .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
@@ -1623,24 +1383,11 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
 };
 
 /* i2c4 */
-static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
-        { .irq = 62 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_i2c4_hwmod = {
         .name           = "i2c4",
         .class          = &omap44xx_i2c_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_i2c4_irqs,
-        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
         .main_clk       = "func_96m_fclk",
         .prcm = {
                 .omap4 = {
@@ -1662,11 +1409,6 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
 };
 
 /* ipu */
-static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
-        { .irq = 100 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "cpu0", .rst_shift = 0 },
         { .name = "cpu1", .rst_shift = 1 },
@@ -1676,7 +1418,6 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
         .name           = "ipu",
         .class          = &omap44xx_ipu_hwmod_class,
         .clkdm_name     = "ducati_clkdm",
-        .mpu_irqs       = omap44xx_ipu_irqs,
         .rst_lines      = omap44xx_ipu_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
         .main_clk       = "ducati_clk_mux_ck",
@@ -1721,19 +1462,6 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
 };
 
 /* iss */
-static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
-        { .irq = 24 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
-        { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
-        { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
-        { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
-        { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
 };
@@ -1742,8 +1470,6 @@ static struct omap_hwmod omap44xx_iss_hwmod = {
         .name           = "iss",
         .class          = &omap44xx_iss_hwmod_class,
         .clkdm_name     = "iss_clkdm",
-        .mpu_irqs       = omap44xx_iss_irqs,
-        .sdma_reqs      = omap44xx_iss_sdma_reqs,
         .main_clk       = "ducati_clk_mux_ck",
         .prcm = {
                 .omap4 = {
@@ -1766,13 +1492,6 @@ static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
 };
 
 /* iva */
-static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
-        { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
-        { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
-        { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
         { .name = "seq0", .rst_shift = 0 },
         { .name = "seq1", .rst_shift = 1 },
@@ -1783,7 +1502,6 @@ static struct omap_hwmod omap44xx_iva_hwmod = {
         .name           = "iva",
         .class          = &omap44xx_iva_hwmod_class,
         .clkdm_name     = "ivahd_clkdm",
-        .mpu_irqs       = omap44xx_iva_irqs,
         .rst_lines      = omap44xx_iva_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
         .main_clk       = "dpll_iva_m5x2_ck",
@@ -1820,16 +1538,10 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
 };
 
 /* kbd */
-static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
-        { .irq = 120 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_kbd_hwmod = {
         .name           = "kbd",
         .class          = &omap44xx_kbd_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_kbd_irqs,
         .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
@@ -1861,16 +1573,10 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
 };
 
 /* mailbox */
-static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
-        { .irq = 26 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_mailbox_hwmod = {
         .name           = "mailbox",
         .class          = &omap44xx_mailbox_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
-        .mpu_irqs       = omap44xx_mailbox_irqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
@@ -1903,24 +1609,10 @@ static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
 };
 
 /* mcasp */
-static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
-        { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
-        { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
-        { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
-        { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mcasp_hwmod = {
         .name           = "mcasp",
         .class          = &omap44xx_mcasp_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcasp_irqs,
-        .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
         .main_clk       = "func_mcasp_abe_gfclk",
         .prcm = {
                 .omap4 = {
@@ -1951,17 +1643,6 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
 };
 
 /* mcbsp1 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
-        { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
@@ -1971,8 +1652,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
         .name           = "mcbsp1",
         .class          = &omap44xx_mcbsp_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp1_irqs,
-        .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
         .main_clk       = "func_mcbsp1_gfclk",
         .prcm = {
                 .omap4 = {
@@ -1986,17 +1665,6 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
 };
 
 /* mcbsp2 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
-        { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
@@ -2006,8 +1674,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
         .name           = "mcbsp2",
         .class          = &omap44xx_mcbsp_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp2_irqs,
-        .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
         .main_clk       = "func_mcbsp2_gfclk",
         .prcm = {
                 .omap4 = {
@@ -2021,17 +1687,6 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
 };
 
 /* mcbsp3 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
-        { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
@@ -2041,8 +1696,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
         .name           = "mcbsp3",
         .class          = &omap44xx_mcbsp_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp3_irqs,
-        .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
         .main_clk       = "func_mcbsp3_gfclk",
         .prcm = {
                 .omap4 = {
@@ -2056,17 +1709,6 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
 };
 
 /* mcbsp4 */
-static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
-        { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
         { .role = "pad_fck", .clk = "pad_clks_ck" },
         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
@@ -2076,8 +1718,6 @@ static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
         .name           = "mcbsp4",
         .class          = &omap44xx_mcbsp_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcbsp4_irqs,
-        .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
         .main_clk       = "per_mcbsp4_gfclk",
         .prcm = {
                 .omap4 = {
@@ -2112,17 +1752,6 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
 };
 
 /* mcpdm */
-static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
-        { .irq = 112 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
-        { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
-        { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
         .name           = "mcpdm",
         .class          = &omap44xx_mcpdm_hwmod_class,
@@ -2139,8 +1768,6 @@ static struct omap_hwmod omap44xx_mcpdm_hwmod = {
          * results 'slow motion' audio playback.
          */
         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
-        .mpu_irqs       = omap44xx_mcpdm_irqs,
-        .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
         .main_clk       = "pad_clks_ck",
         .prcm = {
                 .omap4 = {
@@ -2174,11 +1801,6 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
 };
 
 /* mcspi1 */
-static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
-        { .irq = 65 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
@@ -2200,7 +1822,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
         .name           = "mcspi1",
         .class          = &omap44xx_mcspi_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi1_irqs,
         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2214,11 +1835,6 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
 };
 
 /* mcspi2 */
-static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
-        { .irq = 66 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
@@ -2236,7 +1852,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
         .name           = "mcspi2",
         .class          = &omap44xx_mcspi_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi2_irqs,
         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2250,11 +1865,6 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
 };
 
 /* mcspi3 */
-static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
-        { .irq = 91 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
@@ -2272,7 +1882,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
         .name           = "mcspi3",
         .class          = &omap44xx_mcspi_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi3_irqs,
         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2286,11 +1895,6 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
 };
 
 /* mcspi4 */
-static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
-        { .irq = 48 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
@@ -2306,7 +1910,6 @@ static struct omap_hwmod omap44xx_mcspi4_hwmod = {
         .name           = "mcspi4",
         .class          = &omap44xx_mcspi_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mcspi4_irqs,
         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2342,11 +1945,6 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
 };
 
 /* mmc1 */
-static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
-        { .irq = 83 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
@@ -2362,7 +1960,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
         .name           = "mmc1",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_mmc1_irqs,
         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
         .main_clk       = "hsmmc1_fclk",
         .prcm = {
@@ -2376,11 +1973,6 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
 };
 
 /* mmc2 */
-static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
-        { .irq = 86 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
@@ -2391,7 +1983,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
         .name           = "mmc2",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_mmc2_irqs,
         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
         .main_clk       = "hsmmc2_fclk",
         .prcm = {
@@ -2404,11 +1995,6 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
 };
 
 /* mmc3 */
-static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
-        { .irq = 94 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
@@ -2419,7 +2005,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
         .name           = "mmc3",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc3_irqs,
         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2432,11 +2017,6 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
 };
 
 /* mmc4 */
-static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
-        { .irq = 96 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
@@ -2447,7 +2027,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
         .name           = "mmc4",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc4_irqs,
         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2460,11 +2039,6 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
 };
 
 /* mmc5 */
-static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
-        { .irq = 59 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
@@ -2475,7 +2049,6 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
         .name           = "mmc5",
         .class          = &omap44xx_mmc_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_mmc5_irqs,
         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
@@ -2517,11 +2090,6 @@ static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
 };
 
 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
-        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
         { .name = "mmu_cache", .rst_shift = 2 },
 };
@@ -2548,7 +2116,6 @@ static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
         .name           = "mmu_ipu",
         .class          = &omap44xx_mmu_hwmod_class,
         .clkdm_name     = "ducati_clkdm",
-        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
         .rst_lines      = omap44xx_mmu_ipu_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
         .main_clk       = "ducati_clk_mux_ck",
@@ -2572,11 +2139,6 @@ static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
 };
 
 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
-static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
-        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
         { .name = "mmu_cache", .rst_shift = 1 },
 };
@@ -2603,7 +2165,6 @@ static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
         .name           = "mmu_dsp",
         .class          = &omap44xx_mmu_hwmod_class,
         .clkdm_name     = "tesla_clkdm",
-        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
         .rst_lines      = omap44xx_mmu_dsp_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
         .main_clk       = "dpll_iva_m4x2_ck",
@@ -2628,21 +2189,11 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 };
 
 /* mpu */
-static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
-        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
-        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
-        { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
-        { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
-        { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_mpu_hwmod = {
         .name           = "mpu",
         .class          = &omap44xx_mpu_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
-        .mpu_irqs       = omap44xx_mpu_irqs,
         .main_clk       = "dpll_mpu_m2_ck",
         .prcm = {
                 .omap4 = {
@@ -2695,25 +2246,6 @@ static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
         .sysc   = &omap44xx_ocp2scp_sysc,
 };
 
-/* ocp2scp dev_attr */
-static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
-        {
-                .name           = "usb_phy",
-                .start          = 0x4a0ad080,
-                .end            = 0x4a0ae000,
-                .flags          = IORESOURCE_MEM,
-        },
-        { }
-};
-
-static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
-        {
-                .drv_name       = "omap-usb2",
-                .res            = omap44xx_usb_phy_and_pll_addrs,
-        },
-        { }
-};
-
 /* ocp2scp_usb_phy */
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
@@ -2737,7 +2269,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .dev_attr       = ocp2scp_dev_attr,
 };
 
 /*
@@ -2788,11 +2319,6 @@ static struct omap_hwmod omap44xx_cm_core_hwmod = {
 };
 
 /* prm */
-static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
-        { .irq = 11 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
         { .name = "rst_global_warm_sw", .rst_shift = 0 },
         { .name = "rst_global_cold_sw", .rst_shift = 1 },
@@ -2801,7 +2327,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 static struct omap_hwmod omap44xx_prm_hwmod = {
         .name           = "prm",
         .class          = &omap44xx_prcm_hwmod_class,
-        .mpu_irqs       = omap44xx_prm_irqs,
         .rst_lines      = omap44xx_prm_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 };
@@ -2872,23 +2397,6 @@ static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
 };
 
 /* slimbus1 */
-static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
-        { .irq = 97 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
@@ -2900,8 +2408,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
         .name           = "slimbus1",
         .class          = &omap44xx_slimbus_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_slimbus1_irqs,
-        .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
@@ -2914,23 +2420,6 @@ static struct omap_hwmod omap44xx_slimbus1_hwmod = {
 };
 
 /* slimbus2 */
-static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
-        { .irq = 98 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
-        { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
-        { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
@@ -2941,8 +2430,6 @@ static struct omap_hwmod omap44xx_slimbus2_hwmod = {
         .name           = "slimbus2",
         .class          = &omap44xx_slimbus_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_slimbus2_irqs,
-        .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
@@ -2985,16 +2472,10 @@ static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
         .sensor_voltdm_name   = "core",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
-        { .irq = 19 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
         .name           = "smartreflex_core",
         .class          = &omap44xx_smartreflex_hwmod_class,
         .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_core_irqs,
 
         .main_clk       = "smartreflex_core_fck",
         .prcm = {
@@ -3012,16 +2493,10 @@ static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
         .sensor_voltdm_name     = "iva",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
-        { .irq = 102 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
         .name           = "smartreflex_iva",
         .class          = &omap44xx_smartreflex_hwmod_class,
         .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
         .main_clk       = "smartreflex_iva_fck",
         .prcm = {
                 .omap4 = {
@@ -3038,16 +2513,10 @@ static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
         .sensor_voltdm_name     = "mpu",
 };
 
-static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
-        { .irq = 18 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
         .name           = "smartreflex_mpu",
         .class          = &omap44xx_smartreflex_hwmod_class,
         .clkdm_name     = "l4_ao_clkdm",
-        .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
         .main_clk       = "smartreflex_mpu_fck",
         .prcm = {
                 .omap4 = {
@@ -3155,17 +2624,11 @@ static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
 };
 
 /* timer1 */
-static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
-        { .irq = 37 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer1_hwmod = {
         .name           = "timer1",
         .class          = &omap44xx_timer_1ms_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer1_irqs,
         .main_clk       = "dmt1_clk_mux",
         .prcm = {
                 .omap4 = {
@@ -3178,17 +2641,11 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
 };
 
 /* timer2 */
-static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
-        { .irq = 38 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer2_hwmod = {
         .name           = "timer2",
         .class          = &omap44xx_timer_1ms_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer2_irqs,
         .main_clk       = "cm2_dm2_mux",
         .prcm = {
                 .omap4 = {
@@ -3200,16 +2657,10 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
 };
 
 /* timer3 */
-static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
-        { .irq = 39 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer3_hwmod = {
         .name           = "timer3",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer3_irqs,
         .main_clk       = "cm2_dm3_mux",
         .prcm = {
                 .omap4 = {
@@ -3221,16 +2672,10 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
 };
 
 /* timer4 */
-static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
-        { .irq = 40 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer4_hwmod = {
         .name           = "timer4",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer4_irqs,
         .main_clk       = "cm2_dm4_mux",
         .prcm = {
                 .omap4 = {
@@ -3242,16 +2687,10 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
 };
 
 /* timer5 */
-static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
-        { .irq = 41 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer5_hwmod = {
         .name           = "timer5",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer5_irqs,
         .main_clk       = "timer5_sync_mux",
         .prcm = {
                 .omap4 = {
@@ -3264,16 +2703,10 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
 };
 
 /* timer6 */
-static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
-        { .irq = 42 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer6_hwmod = {
         .name           = "timer6",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer6_irqs,
         .main_clk       = "timer6_sync_mux",
         .prcm = {
                 .omap4 = {
@@ -3286,16 +2719,10 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
 };
 
 /* timer7 */
-static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
-        { .irq = 43 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer7_hwmod = {
         .name           = "timer7",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer7_irqs,
         .main_clk       = "timer7_sync_mux",
         .prcm = {
                 .omap4 = {
@@ -3308,16 +2735,10 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
 };
 
 /* timer8 */
-static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
-        { .irq = 44 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer8_hwmod = {
         .name           = "timer8",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_timer8_irqs,
         .main_clk       = "timer8_sync_mux",
         .prcm = {
                 .omap4 = {
@@ -3330,16 +2751,10 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
 };
 
 /* timer9 */
-static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
-        { .irq = 45 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer9_hwmod = {
         .name           = "timer9",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer9_irqs,
         .main_clk       = "cm2_dm9_mux",
         .prcm = {
                 .omap4 = {
@@ -3352,17 +2767,11 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
 };
 
 /* timer10 */
-static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
-        { .irq = 46 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer10_hwmod = {
         .name           = "timer10",
         .class          = &omap44xx_timer_1ms_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
-        .mpu_irqs       = omap44xx_timer10_irqs,
         .main_clk       = "cm2_dm10_mux",
         .prcm = {
                 .omap4 = {
@@ -3375,16 +2784,10 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
 };
 
 /* timer11 */
-static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
-        { .irq = 47 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_timer11_hwmod = {
         .name           = "timer11",
         .class          = &omap44xx_timer_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
-        .mpu_irqs       = omap44xx_timer11_irqs,
         .main_clk       = "cm2_dm11_mux",
         .prcm = {
                 .omap4 = {
@@ -3419,24 +2822,11 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 };
 
 /* uart1 */
-static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
-        { .irq = 72 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart1_hwmod = {
         .name           = "uart1",
         .class          = &omap44xx_uart_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart1_irqs,
-        .sdma_reqs      = omap44xx_uart1_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
@@ -3448,24 +2838,11 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
 };
 
 /* uart2 */
-static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
-        { .irq = 73 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart2_hwmod = {
         .name           = "uart2",
         .class          = &omap44xx_uart_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart2_irqs,
-        .sdma_reqs      = omap44xx_uart2_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
@@ -3477,25 +2854,12 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
 };
 
 /* uart3 */
-static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
-        { .irq = 74 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart3_hwmod = {
         .name           = "uart3",
         .class          = &omap44xx_uart_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
                                 HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart3_irqs,
-        .sdma_reqs      = omap44xx_uart3_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
@@ -3507,24 +2871,11 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
 };
 
 /* uart4 */
-static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
-        { .irq = 70 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
-static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
-        { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
-        { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
-        { .dma_req = -1 }
-};
-
 static struct omap_hwmod omap44xx_uart4_hwmod = {
         .name           = "uart4",
         .class          = &omap44xx_uart_hwmod_class,
         .clkdm_name     = "l4_per_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE_ACT,
-        .mpu_irqs       = omap44xx_uart4_irqs,
-        .sdma_reqs      = omap44xx_uart4_sdma_reqs,
         .main_clk       = "func_48m_fclk",
         .prcm = {
                 .omap4 = {
@@ -3563,17 +2914,10 @@ static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
 };
 
 /* usb_host_fs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
-        { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
-        { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
         .name           = "usb_host_fs",
         .class          = &omap44xx_usb_host_fs_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_usb_host_fs_irqs,
         .main_clk       = "usb_host_fs_fck",
         .prcm = {
                 .omap4 = {
@@ -3607,12 +2951,6 @@ static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
 };
 
 /* usb_host_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
-        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
-        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
         .name           = "usb_host_hs",
         .class          = &omap44xx_usb_host_hs_hwmod_class,
@@ -3625,7 +2963,6 @@ static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
 
         /*
          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
@@ -3700,12 +3037,6 @@ static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
 };
 
 /* usb_otg_hs */
-static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
-        { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
-        { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
 };
@@ -3715,7 +3046,6 @@ static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
         .class          = &omap44xx_usb_otg_hs_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
-        .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
         .main_clk       = "usb_otg_hs_ick",
         .prcm = {
                 .omap4 = {
@@ -3749,16 +3079,10 @@ static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
         .sysc   = &omap44xx_usb_tll_hs_sysc,
 };
 
-static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
-        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
         .name           = "usb_tll_hs",
         .class          = &omap44xx_usb_tll_hs_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
-        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
         .main_clk       = "usb_tll_hs_ick",
         .prcm = {
                 .omap4 = {
@@ -3794,16 +3118,10 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 };
 
 /* wd_timer2 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
-        { .irq = 80 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
         .name           = "wd_timer2",
         .class          = &omap44xx_wd_timer_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
-        .mpu_irqs       = omap44xx_wd_timer2_irqs,
         .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
@@ -3815,16 +3133,10 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 };
 
 /* wd_timer3 */
-static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
-        { .irq = 36 + OMAP44XX_IRQ_GIC_START },
-        { .irq = -1 }
-};
-
 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
         .name           = "wd_timer3",
         .class          = &omap44xx_wd_timer_hwmod_class,
         .clkdm_name     = "abe_clkdm",
-        .mpu_irqs       = omap44xx_wd_timer3_irqs,
         .main_clk       = "sys_32k_ck",
         .prcm = {
                 .omap4 = {
@@ -3840,32 +3152,6 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
  * interfaces
  */
 
-static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a204000,
-                .pa_end         = 0x4a2040ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* c2c -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
-        .master         = &omap44xx_c2c_hwmod,
-        .slave          = &omap44xx_c2c_target_fw_hwmod,
-        .clk            = "div_core_ck",
-        .addr           = omap44xx_c2c_target_fw_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* l4_cfg -> c2c_target_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_c2c_target_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* l3_main_1 -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
         .master         = &omap44xx_l3_main_1_hwmod,
@@ -3874,55 +3160,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
-        {
-                .pa_start       = 0x4e000000,
-                .pa_end         = 0x4e0007ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* mpu -> dmm */
 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
         .master         = &omap44xx_mpu_hwmod,
         .slave          = &omap44xx_dmm_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_dmm_addrs,
-        .user           = OCP_USER_MPU,
-};
-
-/* c2c -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
-        .master         = &omap44xx_c2c_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "div_core_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* dmm -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
-        .master         = &omap44xx_dmm_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
-        {
-                .pa_start       = 0x4a20c000,
-                .pa_end         = 0x4a20c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* l4_cfg -> emif_fw */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
-        .master         = &omap44xx_l4_cfg_hwmod,
-        .slave          = &omap44xx_emif_fw_hwmod,
-        .clk            = "l4_div_ck",
-        .addr           = omap44xx_emif_fw_addrs,
         .user           = OCP_USER_MPU,
 };
 
@@ -3998,32 +3240,14 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
-        {
-                .pa_start       = 0x44000000,
-                .pa_end         = 0x44000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
         .master         = &omap44xx_mpu_hwmod,
         .slave          = &omap44xx_l3_main_1_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_1_addrs,
         .user           = OCP_USER_MPU,
 };
 
-/* c2c_target_fw -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
-        .master         = &omap44xx_c2c_target_fw_hwmod,
-        .slave          = &omap44xx_l3_main_2_hwmod,
-        .clk            = "l3_div_ck",
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 /* debugss -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
         .master         = &omap44xx_debugss_hwmod,
@@ -4088,21 +3312,11 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
-        {
-                .pa_start       = 0x44800000,
-                .pa_end         = 0x44801fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l3_main_1 -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
         .master         = &omap44xx_l3_main_1_hwmod,
         .slave          = &omap44xx_l3_main_2_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_2_addrs,
         .user           = OCP_USER_MPU,
 };
 
@@ -4138,21 +3352,11 @@ static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
-        {
-                .pa_start       = 0x45000000,
-                .pa_end         = 0x45000fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l3_main_1 -> l3_main_3 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
         .master         = &omap44xx_l3_main_1_hwmod,
         .slave          = &omap44xx_l3_main_3_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_l3_main_3_addrs,
         .user           = OCP_USER_MPU,
 };
 
@@ -4236,21 +3440,11 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
-        {
-                .pa_start       = 0x4a102000,
-                .pa_end         = 0x4a10207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> ocp_wp_noc */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_ocp_wp_noc_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_ocp_wp_noc_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4340,21 +3534,11 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
-        {
-                .pa_start       = 0x4a304000,
-                .pa_end         = 0x4a30401f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> counter_32k */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_counter_32k_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_counter_32k_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4430,21 +3614,11 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
-        {
-                .pa_start       = 0x54160000,
-                .pa_end         = 0x54167fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l3_instr -> debugss */
 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
         .master         = &omap44xx_l3_instr_hwmod,
         .slave          = &omap44xx_debugss_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_debugss_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -4466,41 +3640,19 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x4012e000,
-                .pa_end         = 0x4012e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> dmic */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_dmic_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x4902e000,
-                .pa_end         = 0x4902e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> dmic (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_dmic_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_dmic_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
@@ -4798,42 +3950,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
-        {
-                .pa_start       = 0x4c000000,
-                .pa_end         = 0x4c0000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* emif_fw -> emif1 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
-        .master         = &omap44xx_emif_fw_hwmod,
-        .slave          = &omap44xx_emif1_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_emif1_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
-        {
-                .pa_start       = 0x4d000000,
-                .pa_end         = 0x4d0000ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
-/* emif_fw -> emif2 */
-static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
-        .master         = &omap44xx_emif_fw_hwmod,
-        .slave          = &omap44xx_emif2_hwmod,
-        .clk            = "l3_div_ck",
-        .addr           = omap44xx_emif2_addrs,
-        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
         {
                 .pa_start       = 0x4a10a000,
@@ -4852,129 +3968,59 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
-        {
-                .pa_start       = 0x4a310000,
-                .pa_end         = 0x4a3101ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> gpio1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_gpio1_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_gpio1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
-        {
-                .pa_start       = 0x48055000,
-                .pa_end         = 0x480551ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> gpio2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_gpio2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
-        {
-                .pa_start       = 0x48057000,
-                .pa_end         = 0x480571ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> gpio3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_gpio3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
-        {
-                .pa_start       = 0x48059000,
-                .pa_end         = 0x480591ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> gpio4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_gpio4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
-        {
-                .pa_start       = 0x4805b000,
-                .pa_end         = 0x4805b1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> gpio5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_gpio5_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
-        {
-                .pa_start       = 0x4805d000,
-                .pa_end         = 0x4805d1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> gpio6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_gpio6_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_gpio6_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
-        {
-                .pa_start       = 0x50000000,
-                .pa_end         = 0x500003ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l3_main_2 -> gpmc */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_gpmc_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_gpmc_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5032,75 +4078,35 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
-        {
-                .pa_start       = 0x48070000,
-                .pa_end         = 0x480700ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> i2c1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_i2c1_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
-        {
-                .pa_start       = 0x48072000,
-                .pa_end         = 0x480720ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> i2c2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_i2c2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
-        {
-                .pa_start       = 0x48060000,
-                .pa_end         = 0x480600ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> i2c3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_i2c3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
-        {
-                .pa_start       = 0x48350000,
-                .pa_end         = 0x483500ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> i2c4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_i2c4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_i2c4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5138,39 +4144,19 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
         .user           = OCP_USER_IVA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
-        {
-                .pa_start       = 0x5a000000,
-                .pa_end         = 0x5a07ffff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l3_main_2 -> iva */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_iva_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_iva_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
-        {
-                .pa_start       = 0x4a31c000,
-                .pa_end         = 0x4a31c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> kbd */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_kbd_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_kbd_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5228,335 +4214,147 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40122000,
-                .pa_end         = 0x401220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp1_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49022000,
-                .pa_end         = 0x490220ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp1 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp1_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp1_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40124000,
-                .pa_end         = 0x401240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp2_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49024000,
-                .pa_end         = 0x490240ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp2 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp2_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp2_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40126000,
-                .pa_end         = 0x401260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp3_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49026000,
-                .pa_end         = 0x490260ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcbsp3 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcbsp3_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcbsp3_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
-        {
-                .pa_start       = 0x48096000,
-                .pa_end         = 0x480960ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mcbsp4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mcbsp4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcbsp4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
-        {
-                .name           = "mpu",
-                .pa_start       = 0x40132000,
-                .pa_end         = 0x4013207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcpdm */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcpdm_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
-        {
-                .name           = "dma",
-                .pa_start       = 0x49032000,
-                .pa_end         = 0x4903207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> mcpdm (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_mcpdm_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_mcpdm_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
-        {
-                .pa_start       = 0x48098000,
-                .pa_end         = 0x480981ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mcspi1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mcspi1_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
-        {
-                .pa_start       = 0x4809a000,
-                .pa_end         = 0x4809a1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mcspi2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mcspi2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
-        {
-                .pa_start       = 0x480b8000,
-                .pa_end         = 0x480b81ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mcspi3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mcspi3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
-        {
-                .pa_start       = 0x480ba000,
-                .pa_end         = 0x480ba1ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mcspi4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mcspi4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mcspi4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
-        {
-                .pa_start       = 0x4809c000,
-                .pa_end         = 0x4809c3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mmc1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mmc1_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
-        {
-                .pa_start       = 0x480b4000,
-                .pa_end         = 0x480b43ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mmc2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mmc2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
-        {
-                .pa_start       = 0x480ad000,
-                .pa_end         = 0x480ad3ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mmc3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mmc3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
-        {
-                .pa_start       = 0x480d1000,
-                .pa_end         = 0x480d13ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mmc4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mmc4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
-        {
-                .pa_start       = 0x480d5000,
-                .pa_end         = 0x480d53ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> mmc5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_mmc5_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_mmc5_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5568,111 +4366,51 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
-        {
-                .pa_start       = 0x4a0ad000,
-                .pa_end         = 0x4a0ad01f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
-        {
-                .pa_start       = 0x48243000,
-                .pa_end         = 0x48243fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* mpu_private -> prcm_mpu */
 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
         .master         = &omap44xx_mpu_private_hwmod,
         .slave          = &omap44xx_prcm_mpu_hwmod,
         .clk            = "l3_div_ck",
-        .addr           = omap44xx_prcm_mpu_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
-        {
-                .pa_start       = 0x4a004000,
-                .pa_end         = 0x4a004fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> cm_core_aon */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_cm_core_aon_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_cm_core_aon_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
-        {
-                .pa_start       = 0x4a008000,
-                .pa_end         = 0x4a009fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> cm_core */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_cm_core_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_cm_core_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
-        {
-                .pa_start       = 0x4a306000,
-                .pa_end         = 0x4a307fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> prm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_prm_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_prm_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
-        {
-                .pa_start       = 0x4a30a000,
-                .pa_end         = 0x4a30a7ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> scrm */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_scrm_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_scrm_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5810,447 +4548,195 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
-        {
-                .pa_start       = 0x4a318000,
-                .pa_end         = 0x4a31807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> timer1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_timer1_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_timer1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
-        {
-                .pa_start       = 0x48032000,
-                .pa_end         = 0x4803207f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
-        {
-                .pa_start       = 0x48034000,
-                .pa_end         = 0x4803407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
-        {
-                .pa_start       = 0x48036000,
-                .pa_end         = 0x4803607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
-        {
-                .pa_start       = 0x40138000,
-                .pa_end         = 0x4013807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer5 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer5_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
-        {
-                .pa_start       = 0x49038000,
-                .pa_end         = 0x4903807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer5 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer5_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer5_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
-        {
-                .pa_start       = 0x4013a000,
-                .pa_end         = 0x4013a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer6 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer6_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903a000,
-                .pa_end         = 0x4903a07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer6 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer6_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer6_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
-        {
-                .pa_start       = 0x4013c000,
-                .pa_end         = 0x4013c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer7 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer7_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903c000,
-                .pa_end         = 0x4903c07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer7 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer7_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer7_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
-        {
-                .pa_start       = 0x4013e000,
-                .pa_end         = 0x4013e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer8 */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer8_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_addrs,
         .user           = OCP_USER_MPU,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
-        {
-                .pa_start       = 0x4903e000,
-                .pa_end         = 0x4903e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_abe -> timer8 (dma) */
 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
         .master         = &omap44xx_l4_abe_hwmod,
         .slave          = &omap44xx_timer8_hwmod,
         .clk            = "ocp_abe_iclk",
-        .addr           = omap44xx_timer8_dma_addrs,
         .user           = OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
-        {
-                .pa_start       = 0x4803e000,
-                .pa_end         = 0x4803e07f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer9 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer9_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer9_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
-        {
-                .pa_start       = 0x48086000,
-                .pa_end         = 0x4808607f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer10 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer10_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer10_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
-        {
-                .pa_start       = 0x48088000,
-                .pa_end         = 0x4808807f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> timer11 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_timer11_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_timer11_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
-        {
-                .pa_start       = 0x4806a000,
-                .pa_end         = 0x4806a0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> uart1 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_uart1_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart1_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
-        {
-                .pa_start       = 0x4806c000,
-                .pa_end         = 0x4806c0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> uart2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_uart2_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
-        {
-                .pa_start       = 0x48020000,
-                .pa_end         = 0x480200ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> uart3 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_uart3_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart3_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
-        {
-                .pa_start       = 0x4806e000,
-                .pa_end         = 0x4806e0ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_per -> uart4 */
 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
         .master         = &omap44xx_l4_per_hwmod,
         .slave          = &omap44xx_uart4_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_uart4_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
-        {
-                .pa_start       = 0x4a0a9000,
-                .pa_end         = 0x4a0a93ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> usb_host_fs */
 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_host_fs_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_host_fs_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
-        {
-                .name           = "uhh",
-                .pa_start       = 0x4a064000,
-                .pa_end         = 0x4a0647ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {
-                .name           = "ohci",
-                .pa_start       = 0x4a064800,
-                .pa_end         = 0x4a064bff,
-        },
-        {
-                .name           = "ehci",
-                .pa_start       = 0x4a064c00,
-                .pa_end         = 0x4a064fff,
-        },
-        {}
-};
-
 /* l4_cfg -> usb_host_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_host_hs_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_host_hs_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
-        {
-                .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab7ff,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_cfg -> usb_otg_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_otg_hs_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_otg_hs_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
-        {
-                .name           = "tll",
-                .pa_start       = 0x4a062000,
-                .pa_end         = 0x4a063fff,
-                .flags          = ADDR_TYPE_RT
-        },
-        {}
-};
-
 /* l4_cfg -> usb_tll_hs */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_usb_tll_hs_hwmod,
         .clk            = "l4_div_ck",
-        .addr           = omap44xx_usb_tll_hs_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
-static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
-        {
-                .pa_start       = 0x4a314000,
-                .pa_end         = 0x4a31407f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
-
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
         .master         = &omap44xx_l4_wkup_hwmod,
         .slave          = &omap44xx_wd_timer2_hwmod,
         .clk            = "l4_wkup_clk_mux_ck",
-        .addr           = omap44xx_wd_timer2_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -6290,14 +4776,25 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
         .user           = OCP_USER_SDMA,
 };
 
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_emif1_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
+        .master         = &omap44xx_mpu_hwmod,
+        .slave          = &omap44xx_emif2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
-        &omap44xx_c2c__c2c_target_fw,
-        &omap44xx_l4_cfg__c2c_target_fw,
         &omap44xx_l3_main_1__dmm,
         &omap44xx_mpu__dmm,
-        &omap44xx_c2c__emif_fw,
-        &omap44xx_dmm__emif_fw,
-        &omap44xx_l4_cfg__emif_fw,
         &omap44xx_iva__l3_instr,
         &omap44xx_l3_main_3__l3_instr,
         &omap44xx_ocp_wp_noc__l3_instr,
@@ -6308,7 +4805,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_mmc1__l3_main_1,
         &omap44xx_mmc2__l3_main_1,
         &omap44xx_mpu__l3_main_1,
-        &omap44xx_c2c_target_fw__l3_main_2,
         &omap44xx_debugss__l3_main_2,
         &omap44xx_dma_system__l3_main_2,
         &omap44xx_fdif__l3_main_2,
@@ -6364,8 +4860,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l3_main_2__dss_venc,
         &omap44xx_l4_per__dss_venc,
         &omap44xx_l4_per__elm,
-        &omap44xx_emif_fw__emif1,
-        &omap44xx_emif_fw__emif2,
         &omap44xx_l4_cfg__fdif,
         &omap44xx_l4_wkup__gpio1,
         &omap44xx_l4_per__gpio2,
@@ -6450,6 +4944,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_wkup__wd_timer2,
         &omap44xx_l4_abe__wd_timer3,
         &omap44xx_l4_abe__wd_timer3_dma,
+        &omap44xx_mpu__emif1,
+        &omap44xx_mpu__emif2,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..f37ae96b70a1
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2150 @@
+/*
+ * Hardware modules present on the OMAP54xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_54xx.h"
+#include "cm2_54xx.h"
+#include "prm54xx.h"
+#include "prm-regbits-54xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all OMAP5 interrupts external to MPUSS */
+#define OMAP54XX_IRQ_GIC_START  32
+
+/* Base offset for all OMAP5 dma requests */
+#define OMAP54XX_DMA_REQ_START  1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
+        .name   = "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod omap54xx_dmm_hwmod = {
+        .name           = "dmm",
+        .class          = &omap54xx_dmm_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
+ */
+static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
+        .name   = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod omap54xx_l3_instr_hwmod = {
+        .name           = "l3_instr",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
+        .name           = "l3_main_1",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main1_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
+        .name           = "l3_main_2",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3main2_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l3_main_3 */
+static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
+        .name           = "l3_main_3",
+        .class          = &omap54xx_l3_hwmod_class,
+        .clkdm_name     = "l3instr_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
+ */
+static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
+        .name   = "l4",
+};
+
+/* l4_abe */
+static struct omap_hwmod omap54xx_l4_abe_hwmod = {
+        .name           = "l4_abe",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/* l4_cfg */
+static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
+        .name           = "l4_cfg",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l4_per */
+static struct omap_hwmod omap54xx_l4_per_hwmod = {
+        .name           = "l4_per",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/* l4_wkup */
+static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
+        .name           = "l4_wkup",
+        .class          = &omap54xx_l4_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
+        .name   = "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod omap54xx_mpu_private_hwmod = {
+        .name           = "mpu_private",
+        .class          = &omap54xx_mpu_bus_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+};
+
+/*
+ * 'counter' class
+ * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_SIDLEMODE,
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
+        .name   = "counter",
+        .sysc   = &omap54xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod omap54xx_counter_32k_hwmod = {
+        .name           = "counter_32k",
+        .class          = &omap54xx_counter_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'dma' class
+ * dma controller for data exchange between memory to memory (i.e. internal or
+ * external memory) and gp peripherals to memory or memory to gp peripherals
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x002c,
+        .syss_offs      = 0x0028,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
+        .name   = "dma",
+        .sysc   = &omap54xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+        .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+                          IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+        .lch_count      = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
+        { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
+        { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
+        { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
+        { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap54xx_dma_system_hwmod = {
+        .name           = "dma_system",
+        .class          = &omap54xx_dma_hwmod_class,
+        .clkdm_name     = "dma_clkdm",
+        .mpu_irqs       = omap54xx_dma_system_irqs,
+        .main_clk       = "l3_iclk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+                },
+        },
+        .dev_attr       = &dma_dev_attr,
+};
+
+/*
+ * 'dmic' class
+ * digital microphone controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
+        .name   = "dmic",
+        .sysc   = &omap54xx_dmic_sysc,
+};
+
+/* dmic */
+static struct omap_hwmod omap54xx_dmic_hwmod = {
+        .name           = "dmic",
+        .class          = &omap54xx_dmic_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "dmic_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'emif' class
+ * external memory interface no1 (wrapper)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
+        .rev_offs       = 0x0000,
+};
+
+static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
+        .name   = "emif",
+        .sysc   = &omap54xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod omap54xx_emif1_hwmod = {
+        .name           = "emif1",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/* emif2 */
+static struct omap_hwmod omap54xx_emif2_hwmod = {
+        .name           = "emif2",
+        .class          = &omap54xx_emif_hwmod_class,
+        .clkdm_name     = "emif_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_core_h11x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0114,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
+        .name   = "gpio",
+        .sysc   = &omap54xx_gpio_sysc,
+        .rev    = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+        .bank_width     = 32,
+        .dbck_flag      = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio1_hwmod = {
+        .name           = "gpio1",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "wkupaon_iclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio2_hwmod = {
+        .name           = "gpio2",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio3_hwmod = {
+        .name           = "gpio3",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio4_hwmod = {
+        .name           = "gpio4",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio5_hwmod = {
+        .name           = "gpio5",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio5_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio6_hwmod = {
+        .name           = "gpio6",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio6_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio7_hwmod = {
+        .name           = "gpio7",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio7_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio7_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+        { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod omap54xx_gpio8_hwmod = {
+        .name           = "gpio8",
+        .class          = &omap54xx_gpio_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "l4_root_clk_div",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = gpio8_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(gpio8_opt_clks),
+        .dev_attr       = &gpio_dev_attr,
+};
+
+/*
+ * 'i2c' class
+ * multimaster high-speed i2c controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0090,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
+        .name   = "i2c",
+        .sysc   = &omap54xx_i2c_sysc,
+        .reset  = &omap_i2c_reset,
+        .rev    = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+        .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod omap54xx_i2c1_hwmod = {
+        .name           = "i2c1",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod omap54xx_i2c2_hwmod = {
+        .name           = "i2c2",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod omap54xx_i2c3_hwmod = {
+        .name           = "i2c3",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod omap54xx_i2c4_hwmod = {
+        .name           = "i2c4",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod omap54xx_i2c5_hwmod = {
+        .name           = "i2c5",
+        .class          = &omap54xx_i2c_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &i2c_dev_attr,
+};
+
+/*
+ * 'kbd' class
+ * keyboard controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
+        .name   = "kbd",
+        .sysc   = &omap54xx_kbd_sysc,
+};
+
+/* kbd */
+static struct omap_hwmod omap54xx_kbd_hwmod = {
+        .name           = "kbd",
+        .class          = &omap54xx_kbd_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
+        .name   = "mcbsp",
+        .sysc   = &omap54xx_mcbsp_sysc,
+        .rev    = MCBSP_CONFIG_TYPE4,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp1_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp2_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
+        { .role = "pad_fck", .clk = "pad_clks_ck" },
+        { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
+};
+
+static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap54xx_mcbsp_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "mcbsp3_gfclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mcbsp3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
+};
+
+/*
+ * 'mcpdm' class
+ * multi channel pdm controller (proprietary interface with phoenix power
+ * ic)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
+        .name   = "mcpdm",
+        .sysc   = &omap54xx_mcpdm_sysc,
+};
+
+/* mcpdm */
+static struct omap_hwmod omap54xx_mcpdm_hwmod = {
+        .name           = "mcpdm",
+        .class          = &omap54xx_mcpdm_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        /*
+         * It's suspected that the McPDM requires an off-chip main
+         * functional clock, controlled via I2C.  This IP block is
+         * currently reset very early during boot, before I2C is
+         * available, so it doesn't seem that we have any choice in
+         * the kernel other than to avoid resetting it.  XXX This is
+         * really a hardware issue workaround: every IP block should
+         * be able to source its main functional clock from either
+         * on-chip or off-chip sources.  McPDM seems to be the only
+         * current exception.
+         */
+
+        .flags          = HWMOD_EXT_OPT_MAIN_CLK,
+        .main_clk       = "pad_clks_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
+        .name   = "mcspi",
+        .sysc   = &omap54xx_mcspi_sysc,
+        .rev    = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+        .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap54xx_mcspi1_hwmod = {
+        .name           = "mcspi1",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi2_hwmod = {
+        .name           = "mcspi2",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+        .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap54xx_mcspi3_hwmod = {
+        .name           = "mcspi3",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+        .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap54xx_mcspi4_hwmod = {
+        .name           = "mcspi4",
+        .class          = &omap54xx_mcspi_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .dev_attr       = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
+        .name   = "mmc",
+        .sysc   = &omap54xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+        { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap54xx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc1_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mmc1_opt_clks),
+        .dev_attr       = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod omap54xx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .main_clk       = "mmc2_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc3 */
+static struct omap_hwmod omap54xx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc4 */
+static struct omap_hwmod omap54xx_mmc4_hwmod = {
+        .name           = "mmc4",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* mmc5 */
+static struct omap_hwmod omap54xx_mmc5_hwmod = {
+        .name           = "mmc5",
+        .class          = &omap54xx_mmc_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_96m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'mpu' class
+ * mpu sub-system
+ */
+
+static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
+        .name   = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod omap54xx_mpu_hwmod = {
+        .name           = "mpu",
+        .class          = &omap54xx_mpu_hwmod_class,
+        .clkdm_name     = "mpu_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "dpll_mpu_m2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
+                },
+        },
+};
+
+/*
+ * 'timer' class
+ * general purpose timer module with accurate 1ms tick
+ * This class contains several variants: ['timer_1ms', 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+        .clockact       = CLOCKACT_TEST_ICLK,
+};
+
+static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
+        .name   = "timer",
+        .sysc   = &omap54xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod omap54xx_timer1_hwmod = {
+        .name           = "timer1",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "timer1_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer2 */
+static struct omap_hwmod omap54xx_timer2_hwmod = {
+        .name           = "timer2",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer2_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer3 */
+static struct omap_hwmod omap54xx_timer3_hwmod = {
+        .name           = "timer3",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer3_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer4 */
+static struct omap_hwmod omap54xx_timer4_hwmod = {
+        .name           = "timer4",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer4_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer5 */
+static struct omap_hwmod omap54xx_timer5_hwmod = {
+        .name           = "timer5",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer5_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer6 */
+static struct omap_hwmod omap54xx_timer6_hwmod = {
+        .name           = "timer6",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer6_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer7 */
+static struct omap_hwmod omap54xx_timer7_hwmod = {
+        .name           = "timer7",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer7_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer8 */
+static struct omap_hwmod omap54xx_timer8_hwmod = {
+        .name           = "timer8",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "abe_clkdm",
+        .main_clk       = "timer8_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer9 */
+static struct omap_hwmod omap54xx_timer9_hwmod = {
+        .name           = "timer9",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer9_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer10 */
+static struct omap_hwmod omap54xx_timer10_hwmod = {
+        .name           = "timer10",
+        .class          = &omap54xx_timer_1ms_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer10_gfclk_mux",
+        .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* timer11 */
+static struct omap_hwmod omap54xx_timer11_hwmod = {
+        .name           = "timer11",
+        .class          = &omap54xx_timer_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "timer11_gfclk_mux",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'uart' class
+ * universal asynchronous receiver/transmitter (uart)
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
+        .rev_offs       = 0x0050,
+        .sysc_offs      = 0x0054,
+        .syss_offs      = 0x0058,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
+        .name   = "uart",
+        .sysc   = &omap54xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod omap54xx_uart1_hwmod = {
+        .name           = "uart1",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart2 */
+static struct omap_hwmod omap54xx_uart2_hwmod = {
+        .name           = "uart2",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart3 */
+static struct omap_hwmod omap54xx_uart3_hwmod = {
+        .name           = "uart3",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart4 */
+static struct omap_hwmod omap54xx_uart4_hwmod = {
+        .name           = "uart4",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart5 */
+static struct omap_hwmod omap54xx_uart5_hwmod = {
+        .name           = "uart5",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/* uart6 */
+static struct omap_hwmod omap54xx_uart6_hwmod = {
+        .name           = "uart6",
+        .class          = &omap54xx_uart_hwmod_class,
+        .clkdm_name     = "l4per_clkdm",
+        .main_clk       = "func_48m_fclk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+/*
+ * 'usb_otg_ss' class
+ * 2.0 super speed (usb_otg_ss) controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
+        .name   = "usb_otg_ss",
+        .sysc   = &omap54xx_usb_otg_ss_sysc,
+};
+
+/* usb_otg_ss */
+static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
+        { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
+};
+
+static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
+        .name           = "usb_otg_ss",
+        .class          = &omap54xx_usb_otg_ss_hwmod_class,
+        .clkdm_name     = "l3init_clkdm",
+        .flags          = HWMOD_SWSUP_SIDLE,
+        .main_clk       = "dpll_core_h13x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .opt_clks       = usb_otg_ss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(usb_otg_ss_opt_clks),
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
+        .name           = "wd_timer",
+        .sysc           = &omap54xx_wd_timer_sysc,
+        .pre_shutdown   = &omap2_wd_timer_disable,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
+        .name           = "wd_timer2",
+        .class          = &omap54xx_wd_timer_hwmod_class,
+        .clkdm_name     = "wkupaon_clkdm",
+        .main_clk       = "sys_32k_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+};
+
+
+/*
+ * Interfaces
+ */
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_dmm_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_SDMA,
+};
+
+/* l3_main_3 -> l3_instr */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
+        .master         = &omap54xx_l3_main_3_hwmod,
+        .slave          = &omap54xx_l3_instr_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l3_main_1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU,
+};
+
+/* l3_main_2 -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_l3_main_3_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> l4_abe */
+static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_l4_abe_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_cfg_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l4_per */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_l4_per_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
+        .master         = &omap54xx_l3_main_1_hwmod,
+        .slave          = &omap54xx_l4_wkup_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_mpu_private_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_counter_32k_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
+        {
+                .pa_start       = 0x4a056000,
+                .pa_end         = 0x4a056fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_dma_system_hwmod,
+        .clk            = "l4_root_clk_div",
+        .addr           = omap54xx_dma_system_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> dmic */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_dmic_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif1_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
+        .master         = &omap54xx_mpu_hwmod,
+        .slave          = &omap54xx_emif2_hwmod,
+        .clk            = "dpll_core_h11x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_gpio1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio7_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> gpio8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_gpio8_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> i2c5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_i2c5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> kbd */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_kbd_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp1_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp2_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcbsp3_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> mcpdm */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_mcpdm_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mcspi4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc1_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc2_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> mmc5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_mmc5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_mpu_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_timer1_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_abe -> timer5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer5_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer6_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer7 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer7_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_abe -> timer8 */
+static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
+        .master         = &omap54xx_l4_abe_hwmod,
+        .slave          = &omap54xx_timer8_hwmod,
+        .clk            = "abe_iclk",
+        .user           = OCP_USER_MPU,
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer9_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer10 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer10_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> timer11 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_timer11_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart1 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart1_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart2_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart3 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart3_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart4 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart4_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart5 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart5_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per -> uart6 */
+static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
+        .master         = &omap54xx_l4_per_hwmod,
+        .slave          = &omap54xx_uart6_hwmod,
+        .clk            = "l4_root_clk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> usb_otg_ss */
+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
+        .master         = &omap54xx_l4_cfg_hwmod,
+        .slave          = &omap54xx_usb_otg_ss_hwmod,
+        .clk            = "dpll_core_h13x2_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
+        .master         = &omap54xx_l4_wkup_hwmod,
+        .slave          = &omap54xx_wd_timer2_hwmod,
+        .clk            = "wkupaon_iclk_mux",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
+        &omap54xx_l3_main_1__dmm,
+        &omap54xx_l3_main_3__l3_instr,
+        &omap54xx_l3_main_2__l3_main_1,
+        &omap54xx_l4_cfg__l3_main_1,
+        &omap54xx_mpu__l3_main_1,
+        &omap54xx_l3_main_1__l3_main_2,
+        &omap54xx_l4_cfg__l3_main_2,
+        &omap54xx_l3_main_1__l3_main_3,
+        &omap54xx_l3_main_2__l3_main_3,
+        &omap54xx_l4_cfg__l3_main_3,
+        &omap54xx_l3_main_1__l4_abe,
+        &omap54xx_mpu__l4_abe,
+        &omap54xx_l3_main_1__l4_cfg,
+        &omap54xx_l3_main_2__l4_per,
+        &omap54xx_l3_main_1__l4_wkup,
+        &omap54xx_mpu__mpu_private,
+        &omap54xx_l4_wkup__counter_32k,
+        &omap54xx_l4_cfg__dma_system,
+        &omap54xx_l4_abe__dmic,
+        &omap54xx_mpu__emif1,
+        &omap54xx_mpu__emif2,
+        &omap54xx_l4_wkup__gpio1,
+        &omap54xx_l4_per__gpio2,
+        &omap54xx_l4_per__gpio3,
+        &omap54xx_l4_per__gpio4,
+        &omap54xx_l4_per__gpio5,
+        &omap54xx_l4_per__gpio6,
+        &omap54xx_l4_per__gpio7,
+        &omap54xx_l4_per__gpio8,
+        &omap54xx_l4_per__i2c1,
+        &omap54xx_l4_per__i2c2,
+        &omap54xx_l4_per__i2c3,
+        &omap54xx_l4_per__i2c4,
+        &omap54xx_l4_per__i2c5,
+        &omap54xx_l4_wkup__kbd,
+        &omap54xx_l4_abe__mcbsp1,
+        &omap54xx_l4_abe__mcbsp2,
+        &omap54xx_l4_abe__mcbsp3,
+        &omap54xx_l4_abe__mcpdm,
+        &omap54xx_l4_per__mcspi1,
+        &omap54xx_l4_per__mcspi2,
+        &omap54xx_l4_per__mcspi3,
+        &omap54xx_l4_per__mcspi4,
+        &omap54xx_l4_per__mmc1,
+        &omap54xx_l4_per__mmc2,
+        &omap54xx_l4_per__mmc3,
+        &omap54xx_l4_per__mmc4,
+        &omap54xx_l4_per__mmc5,
+        &omap54xx_l4_cfg__mpu,
+        &omap54xx_l4_wkup__timer1,
+        &omap54xx_l4_per__timer2,
+        &omap54xx_l4_per__timer3,
+        &omap54xx_l4_per__timer4,
+        &omap54xx_l4_abe__timer5,
+        &omap54xx_l4_abe__timer6,
+        &omap54xx_l4_abe__timer7,
+        &omap54xx_l4_abe__timer8,
+        &omap54xx_l4_per__timer9,
+        &omap54xx_l4_per__timer10,
+        &omap54xx_l4_per__timer11,
+        &omap54xx_l4_per__uart1,
+        &omap54xx_l4_per__uart2,
+        &omap54xx_l4_per__uart3,
+        &omap54xx_l4_per__uart4,
+        &omap54xx_l4_per__uart5,
+        &omap54xx_l4_per__uart6,
+        &omap54xx_l4_cfg__usb_otg_ss,
+        &omap54xx_l4_wkup__wd_timer2,
+        NULL,
+};
+
+int __init omap54xx_hwmod_init(void)
+{
+        omap_hwmod_init();
+        return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
+}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c01859398b54..5a2d8034c8de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        if (omap3_has_iva())
-                omap3_iva_idle();
+        /*
+         * We need to idle iva2_pwrdm even on am3703 with no iva2.
+         */
+        omap3_iva_idle();
 
         omap3_d2d_idle();
 }
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index a251f87fa2a2..82f0698933d8 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,7 +1,7 @@
 /*
- * OMAP4 Power Management Routines
+ * OMAP4+ Power Management Routines
  *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
+ * Copyright (C) 2010-2013 Texas Instruments, Inc.
  * Rajendra Nayak <rnayak@ti.com>
  * Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
@@ -135,16 +135,16 @@ static void omap_default_idle(void)
 }
 
 /**
- * omap4_pm_init - Init routine for OMAP4 PM
+ * omap4_init_static_deps - Add OMAP4 static dependencies
  *
- * Initializes all powerdomain and clockdomain target states
- * and all PRCM settings.
+ * Add needed static clockdomain dependencies on OMAP4 devices.
+ * Return: 0 on success or 'err' on failures
  */
-int __init omap4_pm_init(void)
+static inline int omap4_init_static_deps(void)
 {
-        int ret;
         struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
         struct clockdomain *ducati_clkdm, *l3_2_clkdm;
+        int ret = 0;
 
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -163,7 +163,7 @@ int __init omap4_pm_init(void)
         ret = pwrdm_for_each(pwrdms_setup, NULL);
         if (ret) {
                 pr_err("Failed to setup powerdomains\n");
-                goto err2;
+                return ret;
         }
 
         /*
@@ -171,6 +171,10 @@ int __init omap4_pm_init(void)
          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
          * expected. The hardware recommendation is to enable static
          * dependencies for these to avoid system lock ups or random crashes.
+         * The L4 wakeup depedency is added to workaround the OCP sync hardware
+         * BUG with 32K synctimer which lead to incorrect timer value read
+         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
+         * are part of L4 wakeup clockdomain.
          */
         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
@@ -179,7 +183,7 @@ int __init omap4_pm_init(void)
         ducati_clkdm = clkdm_lookup("ducati_clkdm");
         if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
                 (!l3_2_clkdm) || (!ducati_clkdm))
-                goto err2;
+                return -EINVAL;
 
         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
@@ -188,9 +192,42 @@ int __init omap4_pm_init(void)
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {
                 pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+/**
+ * omap4_pm_init - Init routine for OMAP4+ devices
+ *
+ * Initializes all powerdomain and clockdomain target states
+ * and all PRCM settings.
+ * Return: Returns the error code returned by called functions.
+ */
+int __init omap4_pm_init(void)
+{
+        int ret = 0;
+
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+
+        pr_info("Power Management for TI OMAP4+ devices.\n");
+
+        ret = pwrdm_for_each(pwrdms_setup, NULL);
+        if (ret) {
+                pr_err("Failed to setup powerdomains.\n");
                 goto err2;
         }
 
+        if (cpu_is_omap44xx()) {
+                ret = omap4_init_static_deps();
+                if (ret)
+                        goto err2;
+        }
+
         ret = omap4_mpuss_init();
         if (ret) {
                 pr_err("Failed to initialise OMAP4 MPUSS\n");
@@ -206,7 +243,8 @@ int __init omap4_pm_init(void)
         /* Overwrite the default cpu_do_idle() */
         arm_pm_idle = omap_default_idle;
 
-        omap4_idle_init();
+        if (cpu_is_omap44xx())
+                omap4_idle_init();
 
 err2:
         return ret;
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 86babd740d41..e233dfcbc186 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -102,6 +102,10 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
         if (_pwrdm_lookup(pwrdm->name))
                 return -EEXIST;
 
+        if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
+                if (!arch_pwrdm->pwrdm_has_voltdm())
+                        goto skip_voltdm;
+
         voltdm = voltdm_lookup(pwrdm->voltdm.name);
         if (!voltdm) {
                 pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
@@ -111,6 +115,7 @@ static int _pwrdm_register(struct powerdomain *pwrdm)
         pwrdm->voltdm.ptr = voltdm;
         INIT_LIST_HEAD(&pwrdm->voltdm_node);
         voltdm_add_pwrdm(voltdm, pwrdm);
+skip_voltdm:
         spin_lock_init(&pwrdm->_lock);
 
         list_add(&pwrdm->node, &pwrdm_list);
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 140c36074fed..e4d7bd6f94b8 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -166,6 +166,7 @@ struct powerdomain {
  * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
  * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
  * @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm: Check if a voltdm association is needed
  *
  * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
  * chips, a powerdomain's power state is not allowed to directly
@@ -196,6 +197,7 @@ struct pwrdm_ops {
         int     (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
         int     (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
         int     (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+        int     (*pwrdm_has_voltdm)(void);
 };
 
 int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
@@ -253,6 +255,7 @@ extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
 extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
+extern void omap54xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index f0e14e9efe5a..e2d4bd804523 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,54 @@ static struct powerdomain dpll5_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain device_81xx_pwrdm = {
+        .name             = "device_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEVICE_MOD,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain active_816x_pwrdm = {
+        .name             = "active_pwrdm",
+        .prcm_offs        = TI816X_PRM_ACTIVE_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain default_816x_pwrdm = {
+        .name             = "default_pwrdm",
+        .prcm_offs        = TI81XX_PRM_DEFAULT_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
+static struct powerdomain ivahd0_816x_pwrdm = {
+        .name             = "ivahd0_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD0_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd1_816x_pwrdm = {
+        .name             = "ivahd1_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD1_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain ivahd2_816x_pwrdm = {
+        .name             = "ivahd2_pwrdm",
+        .prcm_offs        = TI816X_PRM_IVAHD2_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
+static struct powerdomain sgx_816x_pwrdm = {
+        .name             = "sgx_pwrdm",
+        .prcm_offs        = TI816X_PRM_SGX_MOD,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .voltdm           = { .name = "core" },
+};
+
 /* As powerdomains are added or removed above, this list must also be changed */
 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
         &wkup_omap2_pwrdm,
@@ -393,6 +441,17 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
         NULL
 };
 
+static struct powerdomain *powerdomains_ti81xx[] __initdata = {
+        &device_81xx_pwrdm,
+        &active_816x_pwrdm,
+        &default_816x_pwrdm,
+        &ivahd0_816x_pwrdm,
+        &ivahd1_816x_pwrdm,
+        &ivahd2_816x_pwrdm,
+        &sgx_816x_pwrdm,
+        NULL
+};
+
 void __init omap3xxx_powerdomains_init(void)
 {
         unsigned int rev;
@@ -406,6 +465,9 @@ void __init omap3xxx_powerdomains_init(void)
 
         if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
                 pwrdm_register_pwrdms(powerdomains_am35x);
+        } else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1
+                        || rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) {
+                pwrdm_register_pwrdms(powerdomains_ti81xx);
         } else {
                 pwrdm_register_pwrdms(powerdomains_omap3430_common);
 
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
new file mode 100644
index 000000000000..81f8a7cc26ee
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -0,0 +1,331 @@
+/*
+ * OMAP54XX Power domains framework
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-54xx.h"
+#include "prm54xx.h"
+#include "prcm_mpu54xx.h"
+
+/* core_54xx_pwrdm: CORE power domain */
+static struct powerdomain core_54xx_pwrdm = {
+        .name             = "core_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CORE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 5,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
+                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
+                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
+                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
+                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* abe_54xx_pwrdm: Audio back end power domain */
+static struct powerdomain abe_54xx_pwrdm = {
+        .name             = "abe_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_ABE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* aessmem */
+                [1] = PWRSTS_OFF_RET,   /* periphmem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_54xx_pwrdm = {
+        .name             = "coreaon_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_COREAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+};
+
+/* dss_54xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_54xx_pwrdm = {
+        .name             = "dss_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_DSS_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dss_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_54xx_pwrdm = {
+        .name             = "cpu0_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
+        },
+};
+
+/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_54xx_pwrdm = {
+        .name             = "cpu1_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
+        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
+        },
+};
+
+/* emu_54xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_54xx_pwrdm = {
+        .name             = "emu_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_EMU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* emu_bank */
+        },
+};
+
+/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_54xx_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .voltdm           = { .name = "mpu" },
+        .prcm_offs        = OMAP54XX_PRM_MPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
+                [1] = PWRSTS_OFF_RET,   /* mpu_ram */
+        },
+};
+
+/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_54xx_pwrdm = {
+        .name             = "custefuse_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CUSTEFUSE_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp_54xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp_54xx_pwrdm = {
+        .name             = "dsp_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_DSP_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 3,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
+                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
+                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_54xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_54xx_pwrdm = {
+        .name             = "cam_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_CAM_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* cam_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
+static struct powerdomain l3init_54xx_pwrdm = {
+        .name             = "l3init_pwrdm",
+        .voltdm           = { .name = "core" },
+        .prcm_offs        = OMAP54XX_PRM_L3INIT_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF_RET,
+        .banks            = 2,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
+                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_54xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_54xx_pwrdm = {
+        .name             = "gpu_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_GPU_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_54xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_54xx_pwrdm = {
+        .name             = "wkupaon_pwrdm",
+        .voltdm           = { .name = "wkup" },
+        .prcm_offs        = OMAP54XX_PRM_WKUPAON_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret = {
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_ON,        /* wkup_bank */
+        },
+};
+
+/* iva_54xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_54xx_pwrdm = {
+        .name             = "iva_pwrdm",
+        .voltdm           = { .name = "mm" },
+        .prcm_offs        = OMAP54XX_PRM_IVA_INST,
+        .prcm_partition   = OMAP54XX_PRM_PARTITION,
+        .pwrsts           = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret = PWRSTS_OFF,
+        .banks            = 4,
+        .pwrsts_mem_ret = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .pwrsts_mem_on  = {
+                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
+                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
+                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
+                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
+        },
+        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_omap54xx[] __initdata = {
+        &core_54xx_pwrdm,
+        &abe_54xx_pwrdm,
+        &coreaon_54xx_pwrdm,
+        &dss_54xx_pwrdm,
+        &cpu0_54xx_pwrdm,
+        &cpu1_54xx_pwrdm,
+        &emu_54xx_pwrdm,
+        &mpu_54xx_pwrdm,
+        &custefuse_54xx_pwrdm,
+        &dsp_54xx_pwrdm,
+        &cam_54xx_pwrdm,
+        &l3init_54xx_pwrdm,
+        &gpu_54xx_pwrdm,
+        &wkupaon_54xx_pwrdm,
+        &iva_54xx_pwrdm,
+        NULL
+};
+
+void __init omap54xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_omap54xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index c7d355fafd24..ff1ac4a82a04 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -48,6 +48,17 @@
 #define OMAP3430_NEON_MOD                               0xb00
 #define OMAP3430ES2_USBHOST_MOD                         0xc00
 
+/*
+ * TI81XX PRM module offsets
+ */
+#define TI81XX_PRM_DEVICE_MOD                   0x0000
+#define TI816X_PRM_ACTIVE_MOD                   0x0a00
+#define TI81XX_PRM_DEFAULT_MOD                  0x0b00
+#define TI816X_PRM_IVAHD0_MOD                   0x0c00
+#define TI816X_PRM_IVAHD1_MOD                   0x0d00
+#define TI816X_PRM_IVAHD2_MOD                   0x0e00
+#define TI816X_PRM_SGX_MOD                              0x0f00
+
 /* 24XX register bits shared between CM & PRM registers */
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index 7334ffb9d2c1..f429cdd5a118 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -32,6 +32,12 @@
 #define OMAP4430_SCRM_PARTITION                 4
 #define OMAP4430_PRCM_MPU_PARTITION             5
 
+#define OMAP54XX_PRM_PARTITION                  1
+#define OMAP54XX_CM_CORE_AON_PARTITION          2
+#define OMAP54XX_CM_CORE_PARTITION              3
+#define OMAP54XX_SCRM_PARTITION                 4
+#define OMAP54XX_PRCM_MPU_PARTITION             5
+
 /*
  * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
  * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 884af7bb4afd..059bd4f49035 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -25,12 +25,9 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 
+#include "prcm_mpu_44xx_54xx.h"
 #include "common.h"
 
-# ifndef __ASSEMBLER__
-extern void __iomem *prcm_mpu_base;
-# endif
-
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
 
 #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg)                            \
@@ -98,13 +95,4 @@ extern void __iomem *prcm_mpu_base;
 #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET          0x0018
 #define OMAP4430_CM_CPU1_CLKSTCTRL              OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
-                                            s16 idx);
-extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prcm_mpu54xx.h b/arch/arm/mach-omap2/prcm_mpu54xx.h
new file mode 100644
index 000000000000..bc2ce3288315
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu54xx.h
@@ -0,0 +1,87 @@
+/*
+ * OMAP54xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU54XX_H
+
+#include "prcm_mpu_44xx_54xx.h"
+#include "common.h"
+
+#define OMAP54XX_PRCM_MPU_BASE                  0x48243000
+
+#define OMAP54XX_PRCM_MPU_REGADDR(inst, reg)                            \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* PRCM_MPU instances */
+#define OMAP54XX_PRCM_MPU_OCP_SOCKET_INST       0x0000
+#define OMAP54XX_PRCM_MPU_DEVICE_INST           0x0200
+#define OMAP54XX_PRCM_MPU_PRM_C0_INST           0x0400
+#define OMAP54XX_PRCM_MPU_CM_C0_INST            0x0600
+#define OMAP54XX_PRCM_MPU_PRM_C1_INST           0x0800
+#define OMAP54XX_PRCM_MPU_CM_C1_INST            0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRCM_MPU_CM_C0_CPU0_CDOFFS     0x0000
+#define OMAP54XX_PRCM_MPU_CM_C1_CPU1_CDOFFS     0x0000
+
+
+/*
+ * PRCM_MPU
+ *
+ * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global)
+ * point of view the PRCM_MPU is a single entity. It shares the same
+ * programming model as the global PRCM and thus can be assimilate as two new
+ * MOD inside the PRCM
+ */
+
+/* PRCM_MPU.PRCM_MPU_OCP_SOCKET register offsets */
+#define OMAP54XX_REVISION_PRCM_MPU_OFFSET                       0x0000
+
+/* PRCM_MPU.PRCM_MPU_DEVICE register offsets */
+#define OMAP54XX_PRCM_MPU_PRM_RSTST_OFFSET                      0x0000
+#define OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET                0x0004
+#define OMAP54XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET          0x0010
+#define OMAP54XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+
+/* PRCM_MPU.PRCM_MPU_PRM_C0 register offsets */
+#define OMAP54XX_PM_CPU0_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU0_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU0_CPU0_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU0_CPU0_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET                    0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C0 register offsets */
+#define OMAP54XX_CM_CPU0_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU0_CPU0_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C0_INST, 0x0020)
+
+/* PRCM_MPU.PRCM_MPU_PRM_C1 register offsets */
+#define OMAP54XX_PM_CPU1_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CPU1_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_CPU1_CPU1_RSTCTRL_OFFSET                    0x0010
+#define OMAP54XX_RM_CPU1_CPU1_RSTST_OFFSET                      0x0014
+#define OMAP54XX_RM_CPU1_CPU1_CONTEXT_OFFSET                    0x0024
+
+/* PRCM_MPU.PRCM_MPU_CM_C1 register offsets */
+#define OMAP54XX_CM_CPU1_CLKSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL_OFFSET                    0x0020
+#define OMAP54XX_CM_CPU1_CPU1_CLKCTRL                           OMAP54XX_PRCM_MPU_REGADDR(OMAP54XX_PRCM_MPU_CM_C1_INST, 0x0020)
+
+#endif
diff --git a/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
new file mode 100644
index 000000000000..ca149e70bed0
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu_44xx_54xx.h
@@ -0,0 +1,36 @@
+/*
+ * OMAP44xx and OMAP54xx PRCM MPU function prototypes
+ *
+ * Copyright (C) 2010, 2013 Texas Instruments, Inc.
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU_44XX_54XX_H
+
+#ifndef __ASSEMBLER__
+extern void __iomem *prcm_mpu_base;
+
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+                                            s16 idx);
+extern void __init omap2_set_globals_prcm_mpu(void __iomem *prcm_mpu);
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
new file mode 100644
index 000000000000..be31b21aa9c6
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-54xx.h
@@ -0,0 +1,2701 @@
+/*
+ * OMAP54xx Power Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_ACT_SHIFT                                               1
+#define OMAP54XX_ABBOFF_ACT_WIDTH                                               0x1
+#define OMAP54XX_ABBOFF_ACT_MASK                                                (1 << 1)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ABBOFF_SLEEP_SHIFT                                             2
+#define OMAP54XX_ABBOFF_SLEEP_WIDTH                                             0x1
+#define OMAP54XX_ABBOFF_SLEEP_MASK                                              (1 << 2)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_ABB_MM_DONE_EN_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_EN_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_EN_MASK                                            (1 << 31)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_ABB_MM_DONE_ST_SHIFT                                           31
+#define OMAP54XX_ABB_MM_DONE_ST_WIDTH                                           0x1
+#define OMAP54XX_ABB_MM_DONE_ST_MASK                                            (1 << 31)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_EN_MASK                                           (1 << 7)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT                                          7
+#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH                                          0x1
+#define OMAP54XX_ABB_MPU_DONE_ST_MASK                                           (1 << 7)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT                                           2
+#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH                                           0x1
+#define OMAP54XX_ACTIVE_FBB_SEL_MASK                                            (1 << 2)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_AESSMEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_AESSMEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_AESSMEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_AESSMEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_AESSMEM_STATEST_SHIFT                                          4
+#define OMAP54XX_AESSMEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_AESSMEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_AIPOFF_SHIFT                                                   8
+#define OMAP54XX_AIPOFF_WIDTH                                                   0x1
+#define OMAP54XX_AIPOFF_MASK                                                    (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT                                     0
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH                                     0x2
+#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK                                      (0x3 << 0)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT                                       4
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH                                       0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK                                        (0x3 << 4)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT                                      2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH                                      0x2
+#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK                                       (0x3 << 2)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_RA_ERR_SHIFT                                              1
+#define OMAP54XX_BYPS_RA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_RA_ERR_MASK                                               (1 << 1)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_SA_ERR_SHIFT                                              0
+#define OMAP54XX_BYPS_SA_ERR_WIDTH                                              0x1
+#define OMAP54XX_BYPS_SA_ERR_MASK                                               (1 << 0)
+
+/* Used by PRM_VC_BYPASS_ERRST */
+#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT                                         2
+#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH                                         0x1
+#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK                                          (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_C2C_RST_SHIFT                                                  10
+#define OMAP54XX_C2C_RST_WIDTH                                                  0x1
+#define OMAP54XX_C2C_RST_MASK                                                   (1 << 10)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_CAM_PWRSTST */
+#define OMAP54XX_CAM_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_CAM_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_CAM_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_CLKREQCTRL */
+#define OMAP54XX_CLKREQ_COND_SHIFT                                              0
+#define OMAP54XX_CLKREQ_COND_WIDTH                                              0x3
+#define OMAP54XX_CLKREQ_COND_MASK                                               (0x7 << 0)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT                                         16
+#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_CMDRA_VDD_CORE_L_MASK                                          (0xff << 16)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT                                           16
+#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_CMDRA_VDD_MM_L_MASK                                            (0xff << 16)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT                                          16
+#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_CMDRA_VDD_MPU_L_MASK                                           (0xff << 16)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_CMD_VDD_CORE_L_SHIFT                                           28
+#define OMAP54XX_CMD_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_CMD_VDD_CORE_L_MASK                                            (1 << 28)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_CMD_VDD_MM_L_SHIFT                                             28
+#define OMAP54XX_CMD_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_CMD_VDD_MM_L_MASK                                              (1 << 28)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_CMD_VDD_MPU_L_SHIFT                                            28
+#define OMAP54XX_CMD_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_CMD_VDD_MPU_L_MASK                                             (1 << 28)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT                                      18
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK                                       (0x3 << 18)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT                                     9
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH                                     0x1
+#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK                                      (1 << 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT                                      6
+#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH                                      0x2
+#define OMAP54XX_CORE_OCMRAM_STATEST_MASK                                       (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT                                  16
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK                                   (0x3 << 16)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT                                 8
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH                                 0x1
+#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK                                  (1 << 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT                                  4
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH                                  0x2
+#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK                                   (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_CUSTOM_SHIFT                                                   6
+#define OMAP54XX_CUSTOM_WIDTH                                                   0x2
+#define OMAP54XX_CUSTOM_MASK                                                    (0x3 << 6)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_DATA_SHIFT                                                     16
+#define OMAP54XX_DATA_WIDTH                                                     0x8
+#define OMAP54XX_DATA_MASK                                                      (0xff << 16)
+
+/* Used by PRM_DEBUG_CORE_RET_TRANS */
+#define OMAP54XX_PRM_DEBUG_OUT_SHIFT                                            0
+#define OMAP54XX_PRM_DEBUG_OUT_WIDTH                                            0x1c
+#define OMAP54XX_PRM_DEBUG_OUT_MASK                                             (0xfffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_9_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_9_WIDTH                                            0xa
+#define OMAP54XX_DEBUG_OUT_0_9_MASK                                             (0x3ff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_6_SHIFT                                            0
+#define OMAP54XX_DEBUG_OUT_0_6_WIDTH                                            0x7
+#define OMAP54XX_DEBUG_OUT_0_6_MASK                                             (0x7f << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_31_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_31_WIDTH                                           0x20
+#define OMAP54XX_DEBUG_OUT_0_31_MASK                                            (0xffffffff << 0)
+
+/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
+#define OMAP54XX_DEBUG_OUT_0_11_SHIFT                                           0
+#define OMAP54XX_DEBUG_OUT_0_11_WIDTH                                           0xc
+#define OMAP54XX_DEBUG_OUT_0_11_MASK                                            (0xfff << 0)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT                                        0
+#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH                                        0x1
+#define OMAP54XX_DEVICE_OFF_ENABLE_MASK                                         (1 << 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_DFILTEREN_SHIFT                                                6
+#define OMAP54XX_DFILTEREN_WIDTH                                                0x1
+#define OMAP54XX_DFILTEREN_MASK                                                 (1 << 6)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT                                        4
+#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK                                        (1 << 0)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT                                       0
+#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH                                       0x1
+#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK                                        (1 << 0)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK                                         (1 << 2)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT                                        2
+#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK                                         (1 << 2)
+
+/* Used by PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK                                         (1 << 1)
+
+/* Used by PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT                                        1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK                                         (1 << 1)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_EN_MASK                                         (1 << 3)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT                                        3
+#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH                                        0x1
+#define OMAP54XX_DPLL_PER_RECAL_ST_MASK                                         (1 << 3)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT                                         20
+#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_ONSTATE_MASK                                          (0x3 << 20)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT                                        10
+#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_DSP_EDMA_RETSTATE_MASK                                         (1 << 10)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_EDMA_STATEST_SHIFT                                         8
+#define OMAP54XX_DSP_EDMA_STATEST_WIDTH                                         0x2
+#define OMAP54XX_DSP_EDMA_STATEST_MASK                                          (0x3 << 8)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_ONSTATE_SHIFT                                           16
+#define OMAP54XX_DSP_L1_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_ONSTATE_MASK                                            (0x3 << 16)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L1_RETSTATE_SHIFT                                          8
+#define OMAP54XX_DSP_L1_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L1_RETSTATE_MASK                                           (1 << 8)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L1_STATEST_SHIFT                                           4
+#define OMAP54XX_DSP_L1_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L1_STATEST_MASK                                            (0x3 << 4)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_DSP_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_ONSTATE_MASK                                            (0x3 << 18)
+
+/* Used by PM_DSP_PWRSTCTRL */
+#define OMAP54XX_DSP_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_DSP_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_DSP_L2_RETSTATE_MASK                                           (1 << 9)
+
+/* Used by PM_DSP_PWRSTST */
+#define OMAP54XX_DSP_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_DSP_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_DSP_L2_STATEST_MASK                                            (0x3 << 6)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_DSS_MEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define OMAP54XX_DSS_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_DSS_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_DSS_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT                                    8
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK                                     (1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT                                    9
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH                                    0x1
+#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK                                     (1 << 9)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT                                         16
+#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_ONSTATE_MASK                                          (0x3 << 16)
+
+/* Used by PM_EMU_PWRSTST */
+#define OMAP54XX_EMU_BANK_STATEST_SHIFT                                         4
+#define OMAP54XX_EMU_BANK_STATEST_WIDTH                                         0x2
+#define OMAP54XX_EMU_BANK_STATEST_MASK                                          (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
+ * PRM_SRAM_WKUP_SETUP
+ */
+#define OMAP54XX_ENABLE_RTA_SHIFT                                               0
+#define OMAP54XX_ENABLE_RTA_WIDTH                                               0x1
+#define OMAP54XX_ENABLE_RTA_MASK                                                (1 << 0)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC1_SHIFT                                                  3
+#define OMAP54XX_ENFUNC1_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC1_MASK                                                   (1 << 3)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC2_SHIFT                                                  4
+#define OMAP54XX_ENFUNC2_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC2_MASK                                                   (1 << 4)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC3_SHIFT                                                  5
+#define OMAP54XX_ENFUNC3_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC3_MASK                                                   (1 << 5)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC4_SHIFT                                                  6
+#define OMAP54XX_ENFUNC4_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC4_MASK                                                   (1 << 6)
+
+/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
+#define OMAP54XX_ENFUNC5_SHIFT                                                  7
+#define OMAP54XX_ENFUNC5_WIDTH                                                  0x1
+#define OMAP54XX_ENFUNC5_MASK                                                   (1 << 7)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERRORGAIN_SHIFT                                                16
+#define OMAP54XX_ERRORGAIN_WIDTH                                                0x8
+#define OMAP54XX_ERRORGAIN_MASK                                                 (0xff << 16)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_ERROROFFSET_SHIFT                                              24
+#define OMAP54XX_ERROROFFSET_WIDTH                                              0x8
+#define OMAP54XX_ERROROFFSET_MASK                                               (0xff << 24)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT                                        5
+#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH                                        0x1
+#define OMAP54XX_EXTERNAL_WARM_RST_MASK                                         (1 << 5)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_FORCEUPDATE_SHIFT                                              1
+#define OMAP54XX_FORCEUPDATE_WIDTH                                              0x1
+#define OMAP54XX_FORCEUPDATE_MASK                                               (1 << 1)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_FORCEUPDATEWAIT_SHIFT                                          8
+#define OMAP54XX_FORCEUPDATEWAIT_WIDTH                                          0x18
+#define OMAP54XX_FORCEUPDATEWAIT_MASK                                           (0xffffff << 8)
+
+/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
+#define OMAP54XX_FORCEWKUP_EN_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_EN_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_EN_MASK                                              (1 << 10)
+
+/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
+#define OMAP54XX_FORCEWKUP_ST_SHIFT                                             10
+#define OMAP54XX_FORCEWKUP_ST_WIDTH                                             0x1
+#define OMAP54XX_FORCEWKUP_ST_MASK                                              (1 << 10)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_FUNC_SHIFT                                                     16
+#define OMAP54XX_FUNC_WIDTH                                                     0xc
+#define OMAP54XX_FUNC_MASK                                                      (0xfff << 16)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_COLD_RST_SHIFT                                          0
+#define OMAP54XX_GLOBAL_COLD_RST_WIDTH                                          0x1
+#define OMAP54XX_GLOBAL_COLD_RST_MASK                                           (1 << 0)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT                                       1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH                                       0x1
+#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK                                        (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_GLOBAL_WUEN_SHIFT                                              16
+#define OMAP54XX_GLOBAL_WUEN_WIDTH                                              0x1
+#define OMAP54XX_GLOBAL_WUEN_MASK                                               (1 << 16)
+
+/* Used by PM_GPU_PWRSTCTRL */
+#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_GPU_PWRSTST */
+#define OMAP54XX_GPU_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_GPU_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_GPU_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMCODE_SHIFT                                                  0
+#define OMAP54XX_HSMCODE_WIDTH                                                  0x3
+#define OMAP54XX_HSMCODE_MASK                                                   (0x7 << 0)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_HSMODEEN_SHIFT                                                 3
+#define OMAP54XX_HSMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_HSMODEEN_MASK                                                  (1 << 3)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLH_SHIFT                                                   16
+#define OMAP54XX_HSSCLH_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLH_MASK                                                    (0xff << 16)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_HSSCLL_SHIFT                                                   24
+#define OMAP54XX_HSSCLL_WIDTH                                                   0x8
+#define OMAP54XX_HSSCLL_MASK                                                    (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT                                          16
+#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_ONSTATE_MASK                                           (0x3 << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT                                         8
+#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_HWA_MEM_RETSTATE_MASK                                          (1 << 8)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_HWA_MEM_STATEST_SHIFT                                          4
+#define OMAP54XX_HWA_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_HWA_MEM_STATEST_MASK                                           (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_ICEPICK_RST_SHIFT                                              9
+#define OMAP54XX_ICEPICK_RST_WIDTH                                              0x1
+#define OMAP54XX_ICEPICK_RST_MASK                                               (1 << 9)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVDD_SHIFT                                                  2
+#define OMAP54XX_INITVDD_WIDTH                                                  0x1
+#define OMAP54XX_INITVDD_MASK                                                   (1 << 2)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_INITVOLTAGE_SHIFT                                              8
+#define OMAP54XX_INITVOLTAGE_WIDTH                                              0x8
+#define OMAP54XX_INITVOLTAGE_MASK                                               (0xff << 8)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
+ * PRM_VOLTST_MM, PRM_VOLTST_MPU
+ */
+#define OMAP54XX_INTRANSITION_SHIFT                                             20
+#define OMAP54XX_INTRANSITION_WIDTH                                             0x1
+#define OMAP54XX_INTRANSITION_MASK                                              (1 << 20)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_IO_EN_SHIFT                                                    9
+#define OMAP54XX_IO_EN_WIDTH                                                    0x1
+#define OMAP54XX_IO_EN_MASK                                                     (1 << 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_IO_ON_STATUS_SHIFT                                             5
+#define OMAP54XX_IO_ON_STATUS_WIDTH                                             0x1
+#define OMAP54XX_IO_ON_STATUS_MASK                                              (1 << 5)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_IO_ST_SHIFT                                                    9
+#define OMAP54XX_IO_ST_WIDTH                                                    0x1
+#define OMAP54XX_IO_ST_MASK                                                     (1 << 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK                                         (0x3 << 20)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK                                        (1 << 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT                                        8
+#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_IPU_L2RAM_STATEST_MASK                                         (0x3 << 8)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT                                     22
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK                                      (0x3 << 22)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT                                    11
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK                                     (1 << 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT                                     10
+#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH                                     0x2
+#define OMAP54XX_IPU_UNICACHE_STATEST_MASK                                      (0x3 << 10)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT                                          0
+#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH                                          0x1
+#define OMAP54XX_ISOCLK_OVERRIDE_MASK                                           (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOCLK_STATUS_SHIFT                                            1
+#define OMAP54XX_ISOCLK_STATUS_WIDTH                                            0x1
+#define OMAP54XX_ISOCLK_STATUS_MASK                                             (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_ISOOVR_EXTEND_SHIFT                                            4
+#define OMAP54XX_ISOOVR_EXTEND_WIDTH                                            0x1
+#define OMAP54XX_ISOOVR_EXTEND_MASK                                             (1 << 4)
+
+/* Used by PRM_IO_COUNT */
+#define OMAP54XX_ISO_2_ON_TIME_SHIFT                                            0
+#define OMAP54XX_ISO_2_ON_TIME_WIDTH                                            0x8
+#define OMAP54XX_ISO_2_ON_TIME_MASK                                             (0xff << 0)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT                                     16
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK                                      (0x3 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT                                    8
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK                                     (1 << 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT                                     4
+#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK1_STATEST_MASK                                      (0x3 << 4)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT                                     18
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK                                      (0x3 << 18)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT                                    9
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH                                    0x1
+#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK                                     (1 << 9)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT                                     6
+#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH                                     0x2
+#define OMAP54XX_L3INIT_BANK2_STATEST_MASK                                      (0x3 << 6)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT                                    24
+#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH                                    0x2
+#define OMAP54XX_LASTPOWERSTATEENTERED_MASK                                     (0x3 << 24)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_LLI_RST_SHIFT                                                  14
+#define OMAP54XX_LLI_RST_WIDTH                                                  0x1
+#define OMAP54XX_LLI_RST_MASK                                                   (1 << 14)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
+ * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOGICRETSTATE_SHIFT                                            2
+#define OMAP54XX_LOGICRETSTATE_WIDTH                                            0x1
+#define OMAP54XX_LOGICRETSTATE_MASK                                             (1 << 2)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_LOGICSTATEST_SHIFT                                             2
+#define OMAP54XX_LOGICSTATEST_WIDTH                                             0x1
+#define OMAP54XX_LOGICSTATEST_MASK                                              (1 << 2)
+
+/*
+ * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
+ * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
+ * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
+ * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
+ * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
+ * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
+ * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
+ * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
+ * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
+ * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
+ * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
+ * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
+ * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
+ * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
+ * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
+ * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
+ * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
+ * RM_WKUPAON_WD_TIMER2_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT                                          0
+#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_DFF_MASK                                           (1 << 0)
+
+/*
+ * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
+ * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
+ * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
+ * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
+ * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
+ * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
+ * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
+ * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
+ * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
+ * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
+ * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
+ * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
+ * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
+ * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
+ */
+#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT                                          1
+#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH                                          0x1
+#define OMAP54XX_LOSTCONTEXT_RFF_MASK                                           (1 << 1)
+
+/* Used by RM_ABE_AESS_CONTEXT */
+#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_AESSMEM_MASK                                           (1 << 8)
+
+/* Used by RM_CAM_CAL_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAL_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
+#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_CAM_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT                                   9
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH                                   0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK                                    (1 << 9)
+
+/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT                               8
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH                               0x1
+#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK                                (1 << 8)
+
+/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT                                      8
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH                                      0x1
+#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK                                       (1 << 8)
+
+/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT                                  8
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH                                  0x1
+#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK                                   (1 << 8)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT                                         10
+#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK                                          (1 << 10)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT                                           8
+#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L1_MASK                                            (1 << 8)
+
+/* Used by RM_DSP_DSP_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_DSP_L2_MASK                                            (1 << 9)
+
+/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_DSS_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_EMU_BANK_MASK                                          (1 << 8)
+
+/* Used by RM_GPU_GPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_GPU_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_HWA_MEM_MASK                                           (1 << 10)
+
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT                                        9
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK                                         (1 << 9)
+
+/* Used by RM_IPU_IPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK                                      (1 << 8)
+
+/*
+ * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
+ * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT                                     8
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH                                     0x1
+#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK                                      (1 << 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT                                           9
+#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH                                           0x1
+#define OMAP54XX_LOSTMEM_MPU_L2_MASK                                            (1 << 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT                                          10
+#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_MPU_RAM_MASK                                           (1 << 10)
+
+/*
+ * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
+ * RM_L4SEC_FPKA_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT                                 8
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH                                 0x1
+#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK                                  (1 << 8)
+
+/*
+ * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
+ * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK                                         (1 << 8)
+
+/*
+ * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
+ * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
+ * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
+ */
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT                                    8
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH                                    0x1
+#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK                                     (1 << 8)
+
+/* Used by RM_IVA_SL2_CONTEXT */
+#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT                                          8
+#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH                                          0x1
+#define OMAP54XX_LOSTMEM_SL2_MEM_MASK                                           (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT                                         8
+#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK                                          (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT                                         9
+#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH                                         0x1
+#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK                                          (1 << 9)
+
+/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
+#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT                                        8
+#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH                                        0x1
+#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK                                         (1 << 8)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT                                      4
+#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH                                      0x1
+#define OMAP54XX_LOWPOWERSTATECHANGE_MASK                                       (1 << 4)
+
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_MODE_SHIFT                                                     0
+#define OMAP54XX_MODE_WIDTH                                                     0x2
+#define OMAP54XX_MODE_MASK                                                      (0x3 << 0)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT                                       9
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH                                       0x1
+#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK                                        (1 << 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT                                           8
+#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH                                           0x1
+#define OMAP54XX_MODEM_WAKE_IRQ_MASK                                            (1 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_ONSTATE_SHIFT                                           18
+#define OMAP54XX_MPU_L2_ONSTATE_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_ONSTATE_MASK                                            (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_L2_RETSTATE_SHIFT                                          9
+#define OMAP54XX_MPU_L2_RETSTATE_WIDTH                                          0x1
+#define OMAP54XX_MPU_L2_RETSTATE_MASK                                           (1 << 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_L2_STATEST_SHIFT                                           6
+#define OMAP54XX_MPU_L2_STATEST_WIDTH                                           0x2
+#define OMAP54XX_MPU_L2_STATEST_MASK                                            (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT                                          20
+#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_ONSTATE_MASK                                           (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT                                         10
+#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_MPU_RAM_RETSTATE_MASK                                          (1 << 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define OMAP54XX_MPU_RAM_STATEST_SHIFT                                          8
+#define OMAP54XX_MPU_RAM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_MPU_RAM_STATEST_MASK                                           (0x3 << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT                                    2
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH                                    0x1
+#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK                                     (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_MPU_WDT_RST_SHIFT                                              3
+#define OMAP54XX_MPU_WDT_RST_WIDTH                                              0x1
+#define OMAP54XX_MPU_WDT_RST_MASK                                               (1 << 3)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_NOCAP_SHIFT                                                    4
+#define OMAP54XX_NOCAP_WIDTH                                                    0x1
+#define OMAP54XX_NOCAP_MASK                                                     (1 << 4)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT                                    24
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK                                     (0x3 << 24)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT                                   12
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH                                   0x1
+#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK                                    (1 << 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT                                    12
+#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH                                    0x2
+#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK                                     (0x3 << 12)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_OFF_SHIFT                                                      0
+#define OMAP54XX_OFF_WIDTH                                                      0x8
+#define OMAP54XX_OFF_MASK                                                       (0xff << 0)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ON_SHIFT                                                       24
+#define OMAP54XX_ON_WIDTH                                                       0x8
+#define OMAP54XX_ON_MASK                                                        (0xff << 24)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_ONLP_SHIFT                                                     16
+#define OMAP54XX_ONLP_WIDTH                                                     0x8
+#define OMAP54XX_ONLP_MASK                                                      (0xff << 16)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_CHANGE_SHIFT                                               2
+#define OMAP54XX_OPP_CHANGE_WIDTH                                               0x1
+#define OMAP54XX_OPP_CHANGE_MASK                                                (1 << 2)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT                                      25
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH                                      0x1
+#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK                                       (1 << 25)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_OPP_SEL_SHIFT                                                  0
+#define OMAP54XX_OPP_SEL_WIDTH                                                  0x2
+#define OMAP54XX_OPP_SEL_MASK                                                   (0x3 << 0)
+
+/* Used by PRM_DEBUG_OUT */
+#define OMAP54XX_OUTPUT_SHIFT                                                   0
+#define OMAP54XX_OUTPUT_WIDTH                                                   0x20
+#define OMAP54XX_OUTPUT_MASK                                                    (0xffffffff << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_PCHARGECNT_VALUE_SHIFT                                         0
+#define OMAP54XX_PCHARGECNT_VALUE_WIDTH                                         0x6
+#define OMAP54XX_PCHARGECNT_VALUE_MASK                                          (0x3f << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PCHARGE_TIME_SHIFT                                             0
+#define OMAP54XX_PCHARGE_TIME_WIDTH                                             0x8
+#define OMAP54XX_PCHARGE_TIME_MASK                                              (0xff << 0)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT                                        20
+#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_ONSTATE_MASK                                         (0x3 << 20)
+
+/* Used by PM_ABE_PWRSTCTRL */
+#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT                                       10
+#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH                                       0x1
+#define OMAP54XX_PERIPHMEM_RETSTATE_MASK                                        (1 << 10)
+
+/* Used by PM_ABE_PWRSTST */
+#define OMAP54XX_PERIPHMEM_STATEST_SHIFT                                        8
+#define OMAP54XX_PERIPHMEM_STATEST_WIDTH                                        0x2
+#define OMAP54XX_PERIPHMEM_STATEST_MASK                                         (0x3 << 8)
+
+/* Used by PRM_PHASE1_CNDP */
+#define OMAP54XX_PHASE1_CNDP_SHIFT                                              0
+#define OMAP54XX_PHASE1_CNDP_WIDTH                                              0x20
+#define OMAP54XX_PHASE1_CNDP_MASK                                               (0xffffffff << 0)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define OMAP54XX_PHASE2A_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2A_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2A_CNDP_MASK                                              (0xffffffff << 0)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define OMAP54XX_PHASE2B_CNDP_SHIFT                                             0
+#define OMAP54XX_PHASE2B_CNDP_WIDTH                                             0x20
+#define OMAP54XX_PHASE2B_CNDP_MASK                                              (0xffffffff << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT                                    8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH                                    0x8
+#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK                                     (0xff << 8)
+
+/*
+ * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
+ * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
+ * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define OMAP54XX_POWERSTATE_SHIFT                                               0
+#define OMAP54XX_POWERSTATE_WIDTH                                               0x2
+#define OMAP54XX_POWERSTATE_MASK                                                (0x3 << 0)
+
+/*
+ * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
+ * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
+ */
+#define OMAP54XX_POWERSTATEST_SHIFT                                             0
+#define OMAP54XX_POWERSTATEST_WIDTH                                             0x2
+#define OMAP54XX_POWERSTATEST_MASK                                              (0x3 << 0)
+
+/* Used by PRM_PWRREQCTRL */
+#define OMAP54XX_PWRREQ_COND_SHIFT                                              0
+#define OMAP54XX_PWRREQ_COND_WIDTH                                              0x2
+#define OMAP54XX_PWRREQ_COND_MASK                                               (0x3 << 0)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT                                         27
+#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH                                         0x1
+#define OMAP54XX_RACEN_VDD_CORE_L_MASK                                          (1 << 27)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RACEN_VDD_MM_L_SHIFT                                           27
+#define OMAP54XX_RACEN_VDD_MM_L_WIDTH                                           0x1
+#define OMAP54XX_RACEN_VDD_MM_L_MASK                                            (1 << 27)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT                                          27
+#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH                                          0x1
+#define OMAP54XX_RACEN_VDD_MPU_L_MASK                                           (1 << 27)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAC_VDD_CORE_L_SHIFT                                           26
+#define OMAP54XX_RAC_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAC_VDD_CORE_L_MASK                                            (1 << 26)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAC_VDD_MM_L_SHIFT                                             26
+#define OMAP54XX_RAC_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAC_VDD_MM_L_MASK                                              (1 << 26)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAC_VDD_MPU_L_SHIFT                                            26
+#define OMAP54XX_RAC_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAC_VDD_MPU_L_MASK                                             (1 << 26)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT                                          16
+#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH                                          0x6
+#define OMAP54XX_RAMP_DOWN_COUNT_MASK                                           (0x3f << 16)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT                                        24
+#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH                                        0x2
+#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK                                         (0x3 << 24)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_COUNT_SHIFT                                            0
+#define OMAP54XX_RAMP_UP_COUNT_WIDTH                                            0x6
+#define OMAP54XX_RAMP_UP_COUNT_MASK                                             (0x3f << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT                                          8
+#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH                                          0x2
+#define OMAP54XX_RAMP_UP_PRESCAL_MASK                                           (0x3 << 8)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_RAV_VDD_CORE_L_SHIFT                                           25
+#define OMAP54XX_RAV_VDD_CORE_L_WIDTH                                           0x1
+#define OMAP54XX_RAV_VDD_CORE_L_MASK                                            (1 << 25)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_RAV_VDD_MM_L_SHIFT                                             25
+#define OMAP54XX_RAV_VDD_MM_L_WIDTH                                             0x1
+#define OMAP54XX_RAV_VDD_MM_L_MASK                                              (1 << 25)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_RAV_VDD_MPU_L_SHIFT                                            25
+#define OMAP54XX_RAV_VDD_MPU_L_WIDTH                                            0x1
+#define OMAP54XX_RAV_VDD_MPU_L_MASK                                             (1 << 25)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_REGADDR_SHIFT                                                  8
+#define OMAP54XX_REGADDR_WIDTH                                                  0x8
+#define OMAP54XX_REGADDR_MASK                                                   (0xff << 8)
+
+/*
+ * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
+ * PRM_VC_VAL_CMD_VDD_MPU_L
+ */
+#define OMAP54XX_RET_SHIFT                                                      8
+#define OMAP54XX_RET_WIDTH                                                      0x8
+#define OMAP54XX_RET_MASK                                                       (0xff << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_RETMODE_ENABLE_SHIFT                                           0
+#define OMAP54XX_RETMODE_ENABLE_WIDTH                                           0x1
+#define OMAP54XX_RETMODE_ENABLE_MASK                                            (1 << 0)
+
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME1_SHIFT                                                 0
+#define OMAP54XX_RSTTIME1_WIDTH                                                 0xa
+#define OMAP54XX_RSTTIME1_MASK                                                  (0x3ff << 0)
+
+/* Used by PRM_RSTTIME */
+#define OMAP54XX_RSTTIME2_SHIFT                                                 10
+#define OMAP54XX_RSTTIME2_WIDTH                                                 0x5
+#define OMAP54XX_RSTTIME2_MASK                                                  (0x1f << 10)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU0_SHIFT                                                 0
+#define OMAP54XX_RST_CPU0_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU0_MASK                                                  (1 << 0)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_CPU1_SHIFT                                                 1
+#define OMAP54XX_RST_CPU1_WIDTH                                                 0x1
+#define OMAP54XX_RST_CPU1_MASK                                                  (1 << 1)
+
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_SHIFT                                                  0
+#define OMAP54XX_RST_DSP_WIDTH                                                  0x1
+#define OMAP54XX_RST_DSP_MASK                                                   (1 << 0)
+
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_SHIFT                                              2
+#define OMAP54XX_RST_DSP_EMU_WIDTH                                              0x1
+#define OMAP54XX_RST_DSP_EMU_MASK                                               (1 << 2)
+
+/* Used by RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT                                          3
+#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH                                          0x1
+#define OMAP54XX_RST_DSP_EMU_REQ_MASK                                           (1 << 3)
+
+/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
+#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT                                        1
+#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_DSP_MMU_CACHE_MASK                                         (1 << 1)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU0_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_CPU0_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU0_MASK                                        (1 << 3)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_EMULATION_CPU1_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_CPU1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_CPU1_MASK                                        (1 << 4)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT                                       3
+#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ1_MASK                                        (1 << 3)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT                                       4
+#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH                                       0x1
+#define OMAP54XX_RST_EMULATION_SEQ2_MASK                                        (1 << 4)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT                                       1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK                                        (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT                                       0
+#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH                                       0x1
+#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK                                        (1 << 0)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK                                       (1 << 5)
+
+/* Used by RM_IPU_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK                                       (1 << 6)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT                                      5
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK                                       (1 << 5)
+
+/* Used by RM_IVA_RSTST */
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT                                      6
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH                                      0x1
+#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK                                       (1 << 6)
+
+/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
+#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT                                        2
+#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH                                        0x1
+#define OMAP54XX_RST_IPU_MMU_CACHE_MASK                                         (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_LOGIC_SHIFT                                                2
+#define OMAP54XX_RST_LOGIC_WIDTH                                                0x1
+#define OMAP54XX_RST_LOGIC_MASK                                                 (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ1_SHIFT                                                 0
+#define OMAP54XX_RST_SEQ1_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ1_MASK                                                  (1 << 0)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define OMAP54XX_RST_SEQ2_SHIFT                                                 1
+#define OMAP54XX_RST_SEQ2_WIDTH                                                 0x1
+#define OMAP54XX_RST_SEQ2_MASK                                                  (1 << 1)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_R_RTL_SHIFT                                                    11
+#define OMAP54XX_R_RTL_WIDTH                                                    0x5
+#define OMAP54XX_R_RTL_MASK                                                     (0x1f << 11)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SA_VDD_CORE_L_SHIFT                                            0
+#define OMAP54XX_SA_VDD_CORE_L_WIDTH                                            0x7
+#define OMAP54XX_SA_VDD_CORE_L_MASK                                             (0x7f << 0)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SA_VDD_MM_L_SHIFT                                              0
+#define OMAP54XX_SA_VDD_MM_L_WIDTH                                              0x7
+#define OMAP54XX_SA_VDD_MM_L_MASK                                               (0x7f << 0)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SA_VDD_MPU_L_SHIFT                                             0
+#define OMAP54XX_SA_VDD_MPU_L_WIDTH                                             0x7
+#define OMAP54XX_SA_VDD_MPU_L_MASK                                              (0x7f << 0)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_SCHEME_SHIFT                                                   30
+#define OMAP54XX_SCHEME_WIDTH                                                   0x2
+#define OMAP54XX_SCHEME_MASK                                                    (0x3 << 30)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLH_SHIFT                                                     0
+#define OMAP54XX_SCLH_WIDTH                                                     0x8
+#define OMAP54XX_SCLH_MASK                                                      (0xff << 0)
+
+/* Used by PRM_VC_CFG_I2C_CLK */
+#define OMAP54XX_SCLL_SHIFT                                                     8
+#define OMAP54XX_SCLL_WIDTH                                                     0x8
+#define OMAP54XX_SCLL_MASK                                                      (0xff << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_SECURE_WDT_RST_SHIFT                                           4
+#define OMAP54XX_SECURE_WDT_RST_WIDTH                                           0x1
+#define OMAP54XX_SECURE_WDT_RST_MASK                                            (1 << 4)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT                                        24
+#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH                                        0x1
+#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK                                         (1 << 24)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT                                          24
+#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH                                          0x1
+#define OMAP54XX_SEL_SA_VDD_MM_L_MASK                                           (1 << 24)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT                                         24
+#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH                                         0x1
+#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK                                          (1 << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT                                          18
+#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_ONSTATE_MASK                                           (0x3 << 18)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT                                         9
+#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH                                         0x1
+#define OMAP54XX_SL2_MEM_RETSTATE_MASK                                          (1 << 9)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_SL2_MEM_STATEST_SHIFT                                          6
+#define OMAP54XX_SL2_MEM_STATEST_WIDTH                                          0x2
+#define OMAP54XX_SL2_MEM_STATEST_MASK                                           (0x3 << 6)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_SLAVEADDR_SHIFT                                                0
+#define OMAP54XX_SLAVEADDR_WIDTH                                                0x7
+#define OMAP54XX_SLAVEADDR_MASK                                                 (0x7f << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_SLPCNT_VALUE_SHIFT                                             16
+#define OMAP54XX_SLPCNT_VALUE_WIDTH                                             0x8
+#define OMAP54XX_SLPCNT_VALUE_MASK                                              (0xff << 16)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMAX_MASK                                           (0xffff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT                                          8
+#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH                                          0x10
+#define OMAP54XX_SMPSWAITTIMEMIN_MASK                                           (0xffff << 8)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT                                         1
+#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_RA_ERR_CORE_MASK                                          (1 << 1)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT                                           1
+#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_RA_ERR_MM_MASK                                            (1 << 1)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT                                          1
+#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_RA_ERR_MPU_MASK                                           (1 << 1)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT                                         0
+#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_SMPS_SA_ERR_CORE_MASK                                          (1 << 0)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT                                           0
+#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_SMPS_SA_ERR_MM_MASK                                            (1 << 0)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT                                          0
+#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_SMPS_SA_ERR_MPU_MASK                                           (1 << 0)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT                                    2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK                                     (1 << 2)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT                                      2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK                                       (1 << 2)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT                                     2
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK                                      (1 << 2)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2EN_SHIFT                                                    0
+#define OMAP54XX_SR2EN_WIDTH                                                    0x1
+#define OMAP54XX_SR2EN_MASK                                                     (1 << 0)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_IN_TRANSITION_SHIFT                                        6
+#define OMAP54XX_SR2_IN_TRANSITION_WIDTH                                        0x1
+#define OMAP54XX_SR2_IN_TRANSITION_MASK                                         (1 << 6)
+
+/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
+#define OMAP54XX_SR2_STATUS_SHIFT                                               3
+#define OMAP54XX_SR2_STATUS_WIDTH                                               0x2
+#define OMAP54XX_SR2_STATUS_MASK                                                (0x3 << 3)
+
+/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
+#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_SR2_WTCNT_VALUE_MASK                                           (0xff << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAMLDO_STATUS_SHIFT                                           8
+#define OMAP54XX_SRAMLDO_STATUS_WIDTH                                           0x1
+#define OMAP54XX_SRAMLDO_STATUS_MASK                                            (1 << 8)
+
+/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
+#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT                                       9
+#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH                                       0x1
+#define OMAP54XX_SRAM_IN_TRANSITION_MASK                                        (1 << 9)
+
+/* Used by PRM_VC_CFG_I2C_MODE */
+#define OMAP54XX_SRMODEEN_SHIFT                                                 4
+#define OMAP54XX_SRMODEEN_WIDTH                                                 0x1
+#define OMAP54XX_SRMODEEN_MASK                                                  (1 << 4)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_COUNT_SHIFT                                             0
+#define OMAP54XX_STABLE_COUNT_WIDTH                                             0x6
+#define OMAP54XX_STABLE_COUNT_MASK                                              (0x3f << 0)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define OMAP54XX_STABLE_PRESCAL_SHIFT                                           8
+#define OMAP54XX_STABLE_PRESCAL_WIDTH                                           0x2
+#define OMAP54XX_STABLE_PRESCAL_MASK                                            (0x3 << 8)
+
+/* Used by PRM_BANDGAP_SETUP */
+#define OMAP54XX_STARTUP_COUNT_SHIFT                                            0
+#define OMAP54XX_STARTUP_COUNT_WIDTH                                            0x8
+#define OMAP54XX_STARTUP_COUNT_MASK                                             (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT                                      24
+#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH                                      0x8
+#define OMAP54XX_STARTUP_COUNT_24_31_MASK                                       (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT                                         20
+#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_ONSTATE_MASK                                          (0x3 << 20)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT                                        10
+#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM1_MEM_RETSTATE_MASK                                         (1 << 10)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM1_MEM_STATEST_SHIFT                                         8
+#define OMAP54XX_TCM1_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM1_MEM_STATEST_MASK                                          (0x3 << 8)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT                                         22
+#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_ONSTATE_MASK                                          (0x3 << 22)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT                                        11
+#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH                                        0x1
+#define OMAP54XX_TCM2_MEM_RETSTATE_MASK                                         (1 << 11)
+
+/* Used by PM_IVA_PWRSTST */
+#define OMAP54XX_TCM2_MEM_STATEST_SHIFT                                         10
+#define OMAP54XX_TCM2_MEM_STATEST_WIDTH                                         0x2
+#define OMAP54XX_TCM2_MEM_STATEST_MASK                                          (0x3 << 10)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_TIMEOUT_SHIFT                                                  0
+#define OMAP54XX_TIMEOUT_WIDTH                                                  0x10
+#define OMAP54XX_TIMEOUT_MASK                                                   (0xffff << 0)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_TIMEOUTEN_SHIFT                                                3
+#define OMAP54XX_TIMEOUTEN_WIDTH                                                0x1
+#define OMAP54XX_TIMEOUTEN_MASK                                                 (1 << 3)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_TRANSITION_EN_SHIFT                                            8
+#define OMAP54XX_TRANSITION_EN_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_EN_MASK                                             (1 << 8)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_TRANSITION_ST_SHIFT                                            8
+#define OMAP54XX_TRANSITION_ST_WIDTH                                            0x1
+#define OMAP54XX_TRANSITION_ST_MASK                                             (1 << 8)
+
+/* Used by PRM_DEBUG_TRANS_CFG */
+#define OMAP54XX_TRIGGER_CLEAR_SHIFT                                            2
+#define OMAP54XX_TRIGGER_CLEAR_WIDTH                                            0x1
+#define OMAP54XX_TRIGGER_CLEAR_MASK                                             (1 << 2)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_CORE_RST_SHIFT                                           13
+#define OMAP54XX_TSHUT_CORE_RST_WIDTH                                           0x1
+#define OMAP54XX_TSHUT_CORE_RST_MASK                                            (1 << 13)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MM_RST_SHIFT                                             12
+#define OMAP54XX_TSHUT_MM_RST_WIDTH                                             0x1
+#define OMAP54XX_TSHUT_MM_RST_MASK                                              (1 << 12)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_TSHUT_MPU_RST_SHIFT                                            11
+#define OMAP54XX_TSHUT_MPU_RST_WIDTH                                            0x1
+#define OMAP54XX_TSHUT_MPU_RST_MASK                                             (1 << 11)
+
+/* Used by PRM_VC_VAL_BYPASS */
+#define OMAP54XX_VALID_SHIFT                                                    24
+#define OMAP54XX_VALID_WIDTH                                                    0x1
+#define OMAP54XX_VALID_MASK                                                     (1 << 24)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_BYPASSACK_EN_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_EN_MASK                                           (1 << 14)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_BYPASSACK_ST_SHIFT                                          14
+#define OMAP54XX_VC_BYPASSACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_BYPASSACK_ST_MASK                                           (1 << 14)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_EN_MASK                                          (1 << 22)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT                                         22
+#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH                                         0x1
+#define OMAP54XX_VC_CORE_VPACK_ST_MASK                                          (1 << 22)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_MM_VPACK_EN_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_EN_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_EN_MASK                                            (1 << 30)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_MM_VPACK_ST_SHIFT                                           30
+#define OMAP54XX_VC_MM_VPACK_ST_WIDTH                                           0x1
+#define OMAP54XX_VC_MM_VPACK_ST_MASK                                            (1 << 30)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_EN_MASK                                           (1 << 6)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT                                          6
+#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH                                          0x1
+#define OMAP54XX_VC_MPU_VPACK_ST_MASK                                           (1 << 6)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_RAERR_EN_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_EN_MASK                                               (1 << 12)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_RAERR_ST_SHIFT                                              12
+#define OMAP54XX_VC_RAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_RAERR_ST_MASK                                               (1 << 12)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_SAERR_EN_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_EN_MASK                                               (1 << 11)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_SAERR_ST_SHIFT                                              11
+#define OMAP54XX_VC_SAERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_SAERR_ST_MASK                                               (1 << 11)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VC_TOERR_EN_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_EN_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_EN_MASK                                               (1 << 13)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VC_TOERR_ST_SHIFT                                              13
+#define OMAP54XX_VC_TOERR_ST_WIDTH                                              0x1
+#define OMAP54XX_VC_TOERR_ST_MASK                                               (1 << 13)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMAX_SHIFT                                                   24
+#define OMAP54XX_VDDMAX_WIDTH                                                   0x8
+#define OMAP54XX_VDDMAX_MASK                                                    (0xff << 24)
+
+/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
+#define OMAP54XX_VDDMIN_SHIFT                                                   16
+#define OMAP54XX_VDDMIN_WIDTH                                                   0x8
+#define OMAP54XX_VDDMIN_MASK                                                    (0xff << 16)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT                                     12
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH                                     0x1
+#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK                                      (1 << 12)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT                                    8
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH                                    0x1
+#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK                                     (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT                                       14
+#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH                                       0x1
+#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK                                        (1 << 14)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MM_PRESENCE_SHIFT                                          9
+#define OMAP54XX_VDD_MM_PRESENCE_WIDTH                                          0x1
+#define OMAP54XX_VDD_MM_PRESENCE_MASK                                           (1 << 9)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT                                      7
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH                                      0x1
+#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK                                       (1 << 7)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT                                      13
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH                                      0x1
+#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK                                       (1 << 13)
+
+/* Used by PRM_VOLTCTRL */
+#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT                                         8
+#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH                                         0x1
+#define OMAP54XX_VDD_MPU_PRESENCE_MASK                                          (1 << 8)
+
+/* Used by PRM_RSTST */
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT                                     6
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH                                     0x1
+#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK                                      (1 << 6)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT                                         4
+#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_RA_ERR_CORE_MASK                                          (1 << 4)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT                                           4
+#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_RA_ERR_MM_MASK                                            (1 << 4)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT                                          4
+#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_RA_ERR_MPU_MASK                                           (1 << 4)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT                                         3
+#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH                                         0x1
+#define OMAP54XX_VFSM_SA_ERR_CORE_MASK                                          (1 << 3)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT                                           3
+#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH                                           0x1
+#define OMAP54XX_VFSM_SA_ERR_MM_MASK                                            (1 << 3)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT                                          3
+#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH                                          0x1
+#define OMAP54XX_VFSM_SA_ERR_MPU_MASK                                           (1 << 3)
+
+/* Used by PRM_VC_CORE_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT                                    5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH                                    0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK                                     (1 << 5)
+
+/* Used by PRM_VC_MM_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT                                      5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH                                      0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK                                       (1 << 5)
+
+/* Used by PRM_VC_MPU_ERRST */
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT                                     5
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH                                     0x1
+#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK                                      (1 << 5)
+
+/* Used by PRM_VC_SMPS_CORE_CONFIG */
+#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT                                         8
+#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH                                         0x8
+#define OMAP54XX_VOLRA_VDD_CORE_L_MASK                                          (0xff << 8)
+
+/* Used by PRM_VC_SMPS_MM_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT                                           8
+#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH                                           0x8
+#define OMAP54XX_VOLRA_VDD_MM_L_MASK                                            (0xff << 8)
+
+/* Used by PRM_VC_SMPS_MPU_CONFIG */
+#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT                                          8
+#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH                                          0x8
+#define OMAP54XX_VOLRA_VDD_MPU_L_MASK                                           (0xff << 8)
+
+/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
+#define OMAP54XX_VOLTSTATEST_SHIFT                                              0
+#define OMAP54XX_VOLTSTATEST_WIDTH                                              0x2
+#define OMAP54XX_VOLTSTATEST_MASK                                               (0x3 << 0)
+
+/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
+#define OMAP54XX_VPENABLE_SHIFT                                                 0
+#define OMAP54XX_VPENABLE_WIDTH                                                 0x1
+#define OMAP54XX_VPENABLE_MASK                                                  (1 << 0)
+
+/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
+#define OMAP54XX_VPINIDLE_SHIFT                                                 0
+#define OMAP54XX_VPINIDLE_WIDTH                                                 0x1
+#define OMAP54XX_VPINIDLE_MASK                                                  (1 << 0)
+
+/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
+#define OMAP54XX_VPVOLTAGE_SHIFT                                                0
+#define OMAP54XX_VPVOLTAGE_WIDTH                                                0x8
+#define OMAP54XX_VPVOLTAGE_MASK                                                 (0xff << 0)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK                                        (1 << 20)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT                                       20
+#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK                                        (1 << 20)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK                                         (1 << 18)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT                                        18
+#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK                                         (1 << 18)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_EN_MASK                                         (1 << 17)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT                                        17
+#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_CORE_MINVDD_ST_MASK                                         (1 << 17)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK                                      (1 << 19)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT                                     19
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK                                      (1 << 19)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK                                  (1 << 16)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT                                 16
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH                                 0x1
+#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK                                  (1 << 16)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK                                      (1 << 21)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT                                     21
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH                                     0x1
+#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK                                      (1 << 21)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_EN_MASK                                          (1 << 28)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT                                         28
+#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MM_EQVALUE_ST_MASK                                          (1 << 28)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_EN_MASK                                           (1 << 26)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT                                          26
+#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MAXVDD_ST_MASK                                           (1 << 26)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_EN_MASK                                           (1 << 25)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT                                          25
+#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH                                          0x1
+#define OMAP54XX_VP_MM_MINVDD_ST_MASK                                           (1 << 25)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK                                        (1 << 27)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT                                       27
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK                                        (1 << 27)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK                                    (1 << 24)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT                                   24
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH                                   0x1
+#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK                                    (1 << 24)
+
+/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK                                        (1 << 29)
+
+/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
+#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT                                       29
+#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH                                       0x1
+#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK                                        (1 << 29)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT                                        4
+#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH                                        0x1
+#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK                                         (1 << 4)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK                                          (1 << 2)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT                                         2
+#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK                                          (1 << 2)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_EN_MASK                                          (1 << 1)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT                                         1
+#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH                                         0x1
+#define OMAP54XX_VP_MPU_MINVDD_ST_MASK                                          (1 << 1)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK                                       (1 << 3)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT                                      3
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK                                       (1 << 3)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK                                   (1 << 0)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT                                  0
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH                                  0x1
+#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK                                   (1 << 0)
+
+/* Used by PRM_IRQENABLE_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK                                       (1 << 5)
+
+/* Used by PRM_IRQSTATUS_MPU_2 */
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT                                      5
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH                                      0x1
+#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK                                       (1 << 5)
+
+/* Used by PRM_SRAM_COUNT */
+#define OMAP54XX_VSETUPCNT_VALUE_SHIFT                                          8
+#define OMAP54XX_VSETUPCNT_VALUE_WIDTH                                          0x8
+#define OMAP54XX_VSETUPCNT_VALUE_MASK                                           (0xff << 8)
+
+/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
+#define OMAP54XX_VSTEPMAX_SHIFT                                                 0
+#define OMAP54XX_VSTEPMAX_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMAX_MASK                                                  (0xff << 0)
+
+/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
+#define OMAP54XX_VSTEPMIN_SHIFT                                                 0
+#define OMAP54XX_VSTEPMIN_WIDTH                                                 0x8
+#define OMAP54XX_VSTEPMIN_MASK                                                  (0xff << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK                                         (1 << 2)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK                                         (1 << 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT                                     6
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK                                      (1 << 6)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT                                     2
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK                                      (1 << 2)
+
+/* Used by PM_ABE_DMIC_WKDEP */
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT                                       6
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK                                        (1 << 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT                                       5
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK                                        (1 << 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT                                       4
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK                                        (1 << 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT                                      7
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK                                       (1 << 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT                                       10
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK                                        (1 << 10)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT                                       9
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK                                        (1 << 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT                                       8
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK                                        (1 << 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT                                      11
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK                                       (1 << 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT                                       17
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK                                        (1 << 17)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT                                       16
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK                                        (1 << 16)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT                                       15
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK                                        (1 << 15)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT                                      18
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK                                       (1 << 18)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT                                   6
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK                                    (1 << 6)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT                                     19
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK                                      (1 << 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT                                      14
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK                                       (1 << 14)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT                                      13
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK                                       (1 << 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT                                      12
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK                                       (1 << 12)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT                                      6
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK                                       (1 << 6)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK                                       (1 << 1)
+
+/* Used by PM_L3INIT_HSI_WKDEP */
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT                                    7
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK                                     (1 << 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT                                     1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK                                      (1 << 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_L4PER_I2C5_WKDEP */
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT                                     0
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH                                     0x1
+#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK                                      (1 << 0)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT                                          0
+#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH                                          0x1
+#define OMAP54XX_WKUPDEP_KBD_MPU_MASK                                           (1 << 0)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK                                     (1 << 6)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK                                    (1 << 7)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK                                     (1 << 2)
+
+/* Used by PM_ABE_MCASP_WKDEP */
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_MCBSP3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT                                    6
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK                                     (1 << 6)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT                                   7
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK                                    (1 << 7)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT                                    2
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK                                     (1 << 2)
+
+/* Used by PM_ABE_MCPDM_WKDEP */
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT                                      3
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK                                       (1 << 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK                                          (1 << 2)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT                                         2
+#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK                                          (1 << 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT                                         1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK                                          (1 << 1)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_L4PER_MMC5_WKDEP */
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT                                        3
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK                                         (1 << 3)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT                                         0
+#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH                                         0x1
+#define OMAP54XX_WKUPDEP_SATA_MPU_MASK                                          (1 << 0)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT                                 6
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK                                  (1 << 6)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT                                7
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH                                0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK                                 (1 << 7)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT                                 2
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK                                  (1 << 2)
+
+/* Used by PM_ABE_SLIMBUS1_WKDEP */
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT                                 0
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH                                 0x1
+#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK                                  (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT                             1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK                              (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT                             0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH                             0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK                              (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT                               0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH                               0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK                                (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT                              0
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH                              0x1
+#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK                               (1 << 0)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT                                      1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK                                       (1 << 1)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER5_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER6_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER7_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT                                       2
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK                                        (1 << 2)
+
+/* Used by PM_ABE_TIMER8_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT                                       1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK                                        (1 << 1)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT                                       0
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK                                        (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART1_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART2_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT                                        2
+#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_DSP_MASK                                         (1 << 2)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT                                        1
+#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_IPU_MASK                                         (1 << 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART3_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART4_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART5_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT                                        0
+#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH                                        0x1
+#define OMAP54XX_WKUPDEP_UART6_MPU_MASK                                         (1 << 0)
+
+/* Used by PM_L4PER_UART6_WKDEP */
+#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT                                       3
+#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH                                       0x1
+#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK                                        (1 << 3)
+
+/* Used by PM_L3INIT_UNIPRO2_WKDEP */
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT                                      0
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH                                      0x1
+#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK                                       (1 << 0)
+
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT                                  1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK                                   (1 << 1)
+
+/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT                                  0
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH                                  0x1
+#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK                                   (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT                                   1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK                                    (1 << 1)
+
+/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT                                   0
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH                                   0x1
+#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK                                    (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK                                     (1 << 0)
+
+/* Used by PM_ABE_WD_TIMER3_WKDEP */
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT                                    0
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH                                    0x1
+#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK                                     (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_CTRL_SHIFT                                               8
+#define OMAP54XX_WUCLK_CTRL_WIDTH                                               0x1
+#define OMAP54XX_WUCLK_CTRL_MASK                                                (1 << 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define OMAP54XX_WUCLK_STATUS_SHIFT                                             9
+#define OMAP54XX_WUCLK_STATUS_WIDTH                                             0x1
+#define OMAP54XX_WUCLK_STATUS_MASK                                              (1 << 9)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_X_MAJOR_SHIFT                                                  8
+#define OMAP54XX_X_MAJOR_WIDTH                                                  0x3
+#define OMAP54XX_X_MAJOR_MASK                                                   (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define OMAP54XX_Y_MINOR_SHIFT                                                  0
+#define OMAP54XX_Y_MINOR_WIDTH                                                  0x6
+#define OMAP54XX_Y_MINOR_MASK                                                   (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 44c0d7216aa7..720440737744 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -320,6 +320,12 @@ static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
         return 0;
 }
 
+static int am33xx_check_vcvp(void)
+{
+        /* No VC/VP on am33xx devices */
+        return 0;
+}
+
 struct pwrdm_ops am33xx_pwrdm_operations = {
         .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
         .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
@@ -335,4 +341,5 @@ struct pwrdm_ops am33xx_pwrdm_operations = {
         .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
         .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+        .pwrdm_has_voltdm               = am33xx_check_vcvp,
 };
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 8ee1fbdec561..7db2422faa16 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -25,6 +25,7 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H
 
+#include "prm44xx_54xx.h"
 #include "prcm-common.h"
 #include "prm.h"
 
@@ -744,36 +745,4 @@
 #define OMAP4_PRM_VC_ERRST_OFFSET                       0x00f8
 #define OMAP4430_PRM_VC_ERRST                           OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
 
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
-extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
-extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-
-/* OMAP4-specific VP functions */
-u32 omap4_prm_vp_check_txdone(u8 vp_id);
-void omap4_prm_vp_clear_txdone(u8 vp_id);
-
-/*
- * OMAP4 access functions for voltage controller (VC) and
- * voltage proccessor (VP) in the PRM.
- */
-extern u32 omap4_prm_vcvp_read(u8 offset);
-extern void omap4_prm_vcvp_write(u32 val, u8 offset);
-extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
-
-extern void omap44xx_prm_reconfigure_io_chain(void);
-
-/* PRM interrupt-related functions */
-extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
-extern void omap44xx_prm_ocp_barrier(void);
-extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
-extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
-
-extern int __init omap44xx_prm_init(void);
-extern u32 omap44xx_prm_get_reset_sources(void);
-
-# endif
-
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h
new file mode 100644
index 000000000000..7cd22abb8f15
--- /dev/null
+++ b/arch/arm/mach-omap2/prm44xx_54xx.h
@@ -0,0 +1,58 @@
+/*
+ * OMAP44xx and 54xx PRM common functions
+ *
+ * Copyright (C) 2009-2013 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010 Nokia Corporation
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM44XX_54XX_H
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* OMAP4/OMAP5-specific VP functions */
+u32 omap4_prm_vp_check_txdone(u8 vp_id);
+void omap4_prm_vp_clear_txdone(u8 vp_id);
+
+/*
+ * OMAP4/OMAP5 access functions for voltage controller (VC) and
+ * voltage proccessor (VP) in the PRM.
+ */
+extern u32 omap4_prm_vcvp_read(u8 offset);
+extern void omap4_prm_vcvp_write(u32 val, u8 offset);
+extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+extern int __init omap44xx_prm_init(void);
+extern u32 omap44xx_prm_get_reset_sources(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h
new file mode 100644
index 000000000000..e4411010309c
--- /dev/null
+++ b/arch/arm/mach-omap2/prm54xx.h
@@ -0,0 +1,421 @@
+/*
+ * OMAP54xx PRM instance offset macros
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM54XX_H
+
+#include "prm44xx_54xx.h"
+#include "prcm-common.h"
+#include "prm.h"
+
+#define OMAP54XX_PRM_BASE               0x4ae06000
+
+#define OMAP54XX_PRM_REGADDR(inst, reg)                         \
+        OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define OMAP54XX_PRM_OCP_SOCKET_INST    0x0000
+#define OMAP54XX_PRM_CKGEN_INST         0x0100
+#define OMAP54XX_PRM_MPU_INST           0x0300
+#define OMAP54XX_PRM_DSP_INST           0x0400
+#define OMAP54XX_PRM_ABE_INST           0x0500
+#define OMAP54XX_PRM_COREAON_INST       0x0600
+#define OMAP54XX_PRM_CORE_INST          0x0700
+#define OMAP54XX_PRM_IVA_INST           0x1200
+#define OMAP54XX_PRM_CAM_INST           0x1300
+#define OMAP54XX_PRM_DSS_INST           0x1400
+#define OMAP54XX_PRM_GPU_INST           0x1500
+#define OMAP54XX_PRM_L3INIT_INST        0x1600
+#define OMAP54XX_PRM_CUSTEFUSE_INST     0x1700
+#define OMAP54XX_PRM_WKUPAON_INST       0x1800
+#define OMAP54XX_PRM_WKUPAON_CM_INST    0x1900
+#define OMAP54XX_PRM_EMU_INST           0x1a00
+#define OMAP54XX_PRM_EMU_CM_INST        0x1b00
+#define OMAP54XX_PRM_DEVICE_INST        0x1c00
+#define OMAP54XX_PRM_INSTR_INST         0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS  0x0000
+#define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS          0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define OMAP54XX_REVISION_PRM_OFFSET                            0x0000
+#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET                       0x0010
+#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET                     0x0014
+#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET                       0x0018
+#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET                     0x001c
+#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET                       0x0020
+#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET                       0x0028
+#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET                       0x0030
+#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET                       0x0038
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET                0x0040
+#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define OMAP54XX_PRM_DEBUG_OUT_OFFSET                           0x0084
+#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET                     0x0090
+#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET                     0x0094
+#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET                0x0098
+#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET                 0x009c
+#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET                  0x00a0
+#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET              0x00a4
+
+/* PRM.CKGEN_PRM register offsets */
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET                   0x0000
+#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000)
+#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET                       0x0008
+#define OMAP54XX_CM_CLKSEL_WKUPAON                              OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008)
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET                   0x000c
+#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF                          OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c)
+#define OMAP54XX_CM_CLKSEL_SYS_OFFSET                           0x0010
+#define OMAP54XX_CM_CLKSEL_SYS                                  OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010)
+
+/* PRM.MPU_PRM register offsets */
+#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_MPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET                      0x0024
+
+/* PRM.DSP_PRM register offsets */
+#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSP_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_DSP_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET                      0x0024
+
+/* PRM.ABE_PRM register offsets */
+#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_ABE_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET                      0x0030
+#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET                    0x0034
+#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET                       0x0038
+#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET                     0x003c
+#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET                      0x0040
+#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET                    0x0044
+#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET                     0x0048
+#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET                   0x004c
+#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET                     0x0050
+#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET                   0x0054
+#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET                     0x0058
+#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET                   0x005c
+#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET                   0x0060
+#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET                 0x0064
+#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET                     0x0068
+#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET                   0x006c
+#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET                     0x0070
+#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET                   0x0074
+#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET                     0x0078
+#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET                   0x007c
+#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET                     0x0080
+#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET                   0x0084
+#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET                  0x0088
+#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET                0x008c
+
+/* PRM.COREAON_PRM register offsets */
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET        0x0028
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET      0x002c
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET         0x0030
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET       0x0034
+#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET       0x0038
+#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET     0x003c
+
+/* PRM.CORE_PRM register offsets */
+#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET                       0x0000
+#define OMAP54XX_PM_CORE_PWRSTST_OFFSET                         0x0004
+#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET            0x0024
+#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET            0x0124
+#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET                 0x012c
+#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET             0x0134
+#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET                          0x0210
+#define OMAP54XX_RM_IPU_RSTST_OFFSET                            0x0214
+#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET                      0x0224
+#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET               0x0324
+#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET                     0x0424
+#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET             0x042c
+#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET                   0x0434
+#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET                   0x043c
+#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET                0x0444
+#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET                      0x0524
+#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET                0x052c
+#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET               0x0534
+#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET                 0x0624
+#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET               0x062c
+#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET                0x0634
+#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET                0x063c
+#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET               0x0644
+#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET            0x0724
+#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET             0x072c
+#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET           0x0744
+#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET                  0x0824
+#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET           0x082c
+#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET                 0x0834
+#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET                  0x0928
+#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET                0x092c
+#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET                  0x0930
+#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET                0x0934
+#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET                   0x0938
+#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET                 0x093c
+#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET                   0x0940
+#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET                 0x0944
+#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET                   0x0948
+#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET                 0x094c
+#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET                   0x0950
+#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET                 0x0954
+#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET                    0x095c
+#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET                    0x0960
+#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET                  0x0964
+#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET                    0x0968
+#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET                  0x096c
+#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET                    0x0970
+#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET                  0x0974
+#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET                    0x0978
+#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET                  0x097c
+#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET                    0x0980
+#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET                  0x0984
+#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET                  0x098c
+#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET                     0x09a0
+#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET                   0x09a4
+#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET                     0x09a8
+#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET                   0x09ac
+#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET                     0x09b0
+#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET                   0x09b4
+#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET                     0x09b8
+#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET                   0x09bc
+#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET                 0x09c0
+#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET                   0x09f0
+#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET                 0x09f4
+#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET                   0x09f8
+#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET                 0x09fc
+#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET                   0x0a00
+#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET                 0x0a04
+#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET                   0x0a08
+#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET                 0x0a0c
+#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET                    0x0a10
+#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET                  0x0a14
+#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET                    0x0a18
+#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET                  0x0a1c
+#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET                     0x0a20
+#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET                   0x0a24
+#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET                     0x0a28
+#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET                   0x0a2c
+#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET                    0x0a40
+#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET                  0x0a44
+#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET                    0x0a48
+#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET                  0x0a4c
+#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET                    0x0a50
+#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET                  0x0a54
+#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET                  0x0a58
+#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET                    0x0a5c
+#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET                     0x0a60
+#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET                   0x0a64
+#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET                     0x0a68
+#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET                   0x0a6c
+#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET                    0x0a70
+#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET                  0x0a74
+#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET                    0x0a78
+#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET                  0x0a7c
+#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET                   0x0aa4
+#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET                   0x0aac
+#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET                0x0ab4
+#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET                   0x0abc
+#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET                    0x0ac4
+#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET                0x0acc
+#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET             0x0adc
+
+/* PRM.IVA_PRM register offsets */
+#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_IVA_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET                          0x0010
+#define OMAP54XX_RM_IVA_RSTST_OFFSET                            0x0014
+#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET                      0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_CAM_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET                     0x002c
+#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET                      0x0034
+
+/* PRM.DSS_PRM register offsets */
+#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_DSS_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET                        0x0020
+#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET                      0x0024
+#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET                     0x0034
+
+/* PRM.GPU_PRM register offsets */
+#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_GPU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET                      0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET                     0x0000
+#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET                       0x0004
+#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET                    0x0028
+#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET                  0x002c
+#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET                    0x0030
+#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET                  0x0034
+#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET                     0x0038
+#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET                   0x003c
+#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET             0x0058
+#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET           0x005c
+#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET              0x0068
+#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET            0x006c
+#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET        0x007c
+#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET                    0x0088
+#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET                  0x008c
+#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET              0x00e4
+#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET              0x00ec
+#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET              0x00f0
+#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET            0x00f4
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET                  0x0000
+#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET                    0x0004
+#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET    0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET              0x0024
+#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET            0x002c
+#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET              0x0030
+#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET            0x0034
+#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET                  0x0038
+#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET                0x003c
+#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET                 0x0040
+#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET               0x0044
+#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET                0x0048
+#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET              0x004c
+#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET          0x0054
+#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET              0x0064
+#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET                    0x0078
+#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET                  0x007c
+
+/* PRM.WKUPAON_CM register offsets */
+#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET                    0x0000
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET              0x0020
+#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET            0x0028
+#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET            0x0030
+#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET                0x0038
+#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL                       OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET               0x0040
+#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL                      OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET              0x0048
+#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET          0x0050
+#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL                 OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET              0x0060
+#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET                  0x0078
+#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET                 0x0090
+#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL                        OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET            0x0098
+#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL                   OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098)
+
+/* PRM.EMU_PRM register offsets */
+#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_PM_EMU_PWRSTST_OFFSET                          0x0004
+#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET                  0x0024
+
+/* PRM.EMU_CM register offsets */
+#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET                        0x0000
+#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET                       0x0008
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET                  0x0020
+#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL                         OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020)
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET              0x0028
+#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL                     OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028)
+
+/* PRM.DEVICE_PRM register offsets */
+#define OMAP54XX_PRM_RSTCTRL_OFFSET                             0x0000
+#define OMAP54XX_PRM_RSTST_OFFSET                               0x0004
+#define OMAP54XX_PRM_RSTTIME_OFFSET                             0x0008
+#define OMAP54XX_PRM_CLKREQCTRL_OFFSET                          0x000c
+#define OMAP54XX_PRM_VOLTCTRL_OFFSET                            0x0010
+#define OMAP54XX_PRM_PWRREQCTRL_OFFSET                          0x0014
+#define OMAP54XX_PRM_PSCON_COUNT_OFFSET                         0x0018
+#define OMAP54XX_PRM_IO_COUNT_OFFSET                            0x001c
+#define OMAP54XX_PRM_IO_PMCTRL_OFFSET                           0x0020
+#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET                 0x0024
+#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET                  0x0028
+#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET                   0x002c
+#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET                    0x0030
+#define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET            0x0034
+#define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET             0x0038
+#define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET              0x003c
+#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET                      0x0040
+#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET                      0x0044
+#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET                    0x0048
+#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET                     0x004c
+#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET                    0x0050
+#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET                    0x0054
+#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET                       0x0058
+#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET                       0x005c
+#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET                     0x0060
+#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET                      0x0064
+#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET                     0x0068
+#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET                     0x006c
+#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET                        0x0070
+#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET                        0x0074
+#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET                      0x0078
+#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET                       0x007c
+#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET                      0x0080
+#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET                      0x0084
+#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET                 0x0088
+#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET                   0x008c
+#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET                  0x0090
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET               0x0094
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET                 0x0098
+#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET                0x009c
+#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET                       0x00a0
+#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET                       0x00a4
+#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET                         0x00a8
+#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET                        0x00ac
+#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET                     0x00b0
+#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET                     0x00b4
+#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET                      0x00b8
+#define OMAP54XX_PRM_SRAM_COUNT_OFFSET                          0x00bc
+#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET                     0x00c0
+#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET                     0x00c4
+#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET                      0x00c8
+#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET                      0x00cc
+#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET                       0x00d0
+#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET                       0x00d4
+#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET                        0x00d8
+#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET                    0x00dc
+#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET                     0x00e0
+#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET                     0x00e4
+#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET                      0x00e8
+#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET                       0x00ec
+#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET                     0x00f0
+#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET                         0x00f4
+#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET                        0x00f8
+#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET                        0x00fc
+#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET                       0x0100
+#define OMAP54XX_PRM_VOLTST_MPU_OFFSET                          0x0110
+#define OMAP54XX_PRM_VOLTST_MM_OFFSET                           0x0114
+
+#endif
diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h
new file mode 100644
index 000000000000..57e86c8f8239
--- /dev/null
+++ b/arch/arm/mach-omap2/scrm54xx.h
@@ -0,0 +1,231 @@
+/*
+ * OMAP54XX SCRM registers and bitfields
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H
+
+#define OMAP5_SCRM_BASE         0x4ae0a000
+
+#define OMAP54XX_SCRM_REGADDR(reg)                              \
+        OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg))
+
+/* SCRM */
+
+/* SCRM.SCRM register offsets */
+#define OMAP5_SCRM_REVISION_SCRM_OFFSET         0x0000
+#define OMAP5_SCRM_REVISION_SCRM                OMAP54XX_SCRM_REGADDR(0x0000)
+#define OMAP5_SCRM_CLKSETUPTIME_OFFSET          0x0100
+#define OMAP5_SCRM_CLKSETUPTIME                 OMAP54XX_SCRM_REGADDR(0x0100)
+#define OMAP5_SCRM_PMICSETUPTIME_OFFSET         0x0104
+#define OMAP5_SCRM_PMICSETUPTIME                OMAP54XX_SCRM_REGADDR(0x0104)
+#define OMAP5_SCRM_ALTCLKSRC_OFFSET             0x0110
+#define OMAP5_SCRM_ALTCLKSRC                    OMAP54XX_SCRM_REGADDR(0x0110)
+#define OMAP5_SCRM_MODEMCLKM_OFFSET             0x0118
+#define OMAP5_SCRM_MODEMCLKM                    OMAP54XX_SCRM_REGADDR(0x0118)
+#define OMAP5_SCRM_D2DCLKM_OFFSET               0x011c
+#define OMAP5_SCRM_D2DCLKM                      OMAP54XX_SCRM_REGADDR(0x011c)
+#define OMAP5_SCRM_EXTCLKREQ_OFFSET             0x0200
+#define OMAP5_SCRM_EXTCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0200)
+#define OMAP5_SCRM_ACCCLKREQ_OFFSET             0x0204
+#define OMAP5_SCRM_ACCCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0204)
+#define OMAP5_SCRM_PWRREQ_OFFSET                0x0208
+#define OMAP5_SCRM_PWRREQ                       OMAP54XX_SCRM_REGADDR(0x0208)
+#define OMAP5_SCRM_AUXCLKREQ0_OFFSET            0x0210
+#define OMAP5_SCRM_AUXCLKREQ0                   OMAP54XX_SCRM_REGADDR(0x0210)
+#define OMAP5_SCRM_AUXCLKREQ1_OFFSET            0x0214
+#define OMAP5_SCRM_AUXCLKREQ1                   OMAP54XX_SCRM_REGADDR(0x0214)
+#define OMAP5_SCRM_AUXCLKREQ2_OFFSET            0x0218
+#define OMAP5_SCRM_AUXCLKREQ2                   OMAP54XX_SCRM_REGADDR(0x0218)
+#define OMAP5_SCRM_AUXCLKREQ3_OFFSET            0x021c
+#define OMAP5_SCRM_AUXCLKREQ3                   OMAP54XX_SCRM_REGADDR(0x021c)
+#define OMAP5_SCRM_AUXCLKREQ4_OFFSET            0x0220
+#define OMAP5_SCRM_AUXCLKREQ4                   OMAP54XX_SCRM_REGADDR(0x0220)
+#define OMAP5_SCRM_AUXCLKREQ5_OFFSET            0x0224
+#define OMAP5_SCRM_AUXCLKREQ5                   OMAP54XX_SCRM_REGADDR(0x0224)
+#define OMAP5_SCRM_D2DCLKREQ_OFFSET             0x0234
+#define OMAP5_SCRM_D2DCLKREQ                    OMAP54XX_SCRM_REGADDR(0x0234)
+#define OMAP5_SCRM_AUXCLK0_OFFSET               0x0310
+#define OMAP5_SCRM_AUXCLK0                      OMAP54XX_SCRM_REGADDR(0x0310)
+#define OMAP5_SCRM_AUXCLK1_OFFSET               0x0314
+#define OMAP5_SCRM_AUXCLK1                      OMAP54XX_SCRM_REGADDR(0x0314)
+#define OMAP5_SCRM_AUXCLK2_OFFSET               0x0318
+#define OMAP5_SCRM_AUXCLK2                      OMAP54XX_SCRM_REGADDR(0x0318)
+#define OMAP5_SCRM_AUXCLK3_OFFSET               0x031c
+#define OMAP5_SCRM_AUXCLK3                      OMAP54XX_SCRM_REGADDR(0x031c)
+#define OMAP5_SCRM_AUXCLK4_OFFSET               0x0320
+#define OMAP5_SCRM_AUXCLK4                      OMAP54XX_SCRM_REGADDR(0x0320)
+#define OMAP5_SCRM_AUXCLK5_OFFSET               0x0324
+#define OMAP5_SCRM_AUXCLK5                      OMAP54XX_SCRM_REGADDR(0x0324)
+#define OMAP5_SCRM_RSTTIME_OFFSET               0x0400
+#define OMAP5_SCRM_RSTTIME                      OMAP54XX_SCRM_REGADDR(0x0400)
+#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET          0x0418
+#define OMAP5_SCRM_MODEMRSTCTRL                 OMAP54XX_SCRM_REGADDR(0x0418)
+#define OMAP5_SCRM_D2DRSTCTRL_OFFSET            0x041c
+#define OMAP5_SCRM_D2DRSTCTRL                   OMAP54XX_SCRM_REGADDR(0x041c)
+#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET       0x0420
+#define OMAP5_SCRM_EXTPWRONRSTCTRL              OMAP54XX_SCRM_REGADDR(0x0420)
+#define OMAP5_SCRM_EXTWARMRSTST_OFFSET          0x0510
+#define OMAP5_SCRM_EXTWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0510)
+#define OMAP5_SCRM_APEWARMRSTST_OFFSET          0x0514
+#define OMAP5_SCRM_APEWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x0514)
+#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET        0x0518
+#define OMAP5_SCRM_MODEMWARMRSTST               OMAP54XX_SCRM_REGADDR(0x0518)
+#define OMAP5_SCRM_D2DWARMRSTST_OFFSET          0x051c
+#define OMAP5_SCRM_D2DWARMRSTST                 OMAP54XX_SCRM_REGADDR(0x051c)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5, D2DCLKREQ
+ */
+#define OMAP5_ACCURACY_SHIFT                    1
+#define OMAP5_ACCURACY_WIDTH                    0x1
+#define OMAP5_ACCURACY_MASK                     (1 << 1)
+
+/* Used by APEWARMRSTST */
+#define OMAP5_APEWARMRSTST_SHIFT                1
+#define OMAP5_APEWARMRSTST_WIDTH                0x1
+#define OMAP5_APEWARMRSTST_MASK                 (1 << 1)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_CLKDIV_SHIFT                      16
+#define OMAP5_CLKDIV_WIDTH                      0x4
+#define OMAP5_CLKDIV_MASK                       (0xf << 16)
+
+/* Used by D2DCLKM, MODEMCLKM */
+#define OMAP5_CLK_32KHZ_SHIFT                   0
+#define OMAP5_CLK_32KHZ_WIDTH                   0x1
+#define OMAP5_CLK_32KHZ_MASK                    (1 << 0)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_COLDRST_SHIFT                     0
+#define OMAP5_COLDRST_WIDTH                     0x1
+#define OMAP5_COLDRST_MASK                      (1 << 0)
+
+/* Used by D2DWARMRSTST */
+#define OMAP5_D2DWARMRSTST_SHIFT                3
+#define OMAP5_D2DWARMRSTST_WIDTH                0x1
+#define OMAP5_D2DWARMRSTST_MASK                 (1 << 3)
+
+/* Used by AUXCLK0 */
+#define OMAP5_DISABLECLK_SHIFT                  9
+#define OMAP5_DISABLECLK_WIDTH                  0x1
+#define OMAP5_DISABLECLK_MASK                   (1 << 9)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_DOWNTIME_SHIFT                    16
+#define OMAP5_DOWNTIME_WIDTH                    0x6
+#define OMAP5_DOWNTIME_MASK                     (0x3f << 16)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_ENABLE_SHIFT                      8
+#define OMAP5_ENABLE_WIDTH                      0x1
+#define OMAP5_ENABLE_MASK                       (1 << 8)
+
+/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */
+#define OMAP5_ENABLE_0_0_SHIFT                  0
+#define OMAP5_ENABLE_0_0_WIDTH                  0x1
+#define OMAP5_ENABLE_0_0_MASK                   (1 << 0)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_EXT_SHIFT                  3
+#define OMAP5_ENABLE_EXT_WIDTH                  0x1
+#define OMAP5_ENABLE_EXT_MASK                   (1 << 3)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_ENABLE_INT_SHIFT                  2
+#define OMAP5_ENABLE_INT_WIDTH                  0x1
+#define OMAP5_ENABLE_INT_MASK                   (1 << 2)
+
+/* Used by EXTWARMRSTST */
+#define OMAP5_EXTWARMRSTST_SHIFT                0
+#define OMAP5_EXTWARMRSTST_WIDTH                0x1
+#define OMAP5_EXTWARMRSTST_MASK                 (1 << 0)
+
+/*
+ * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4,
+ * AUXCLKREQ5
+ */
+#define OMAP5_MAPPING_SHIFT                     2
+#define OMAP5_MAPPING_WIDTH                     0x3
+#define OMAP5_MAPPING_MASK                      (0x7 << 2)
+
+/* Used by ALTCLKSRC */
+#define OMAP5_MODE_SHIFT                        0
+#define OMAP5_MODE_WIDTH                        0x2
+#define OMAP5_MODE_MASK                         (0x3 << 0)
+
+/* Used by MODEMWARMRSTST */
+#define OMAP5_MODEMWARMRSTST_SHIFT              2
+#define OMAP5_MODEMWARMRSTST_WIDTH              0x1
+#define OMAP5_MODEMWARMRSTST_MASK               (1 << 2)
+
+/*
+ * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5,
+ * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5,
+ * D2DCLKREQ, EXTCLKREQ, PWRREQ
+ */
+#define OMAP5_POLARITY_SHIFT                    0
+#define OMAP5_POLARITY_WIDTH                    0x1
+#define OMAP5_POLARITY_MASK                     (1 << 0)
+
+/* Used by EXTPWRONRSTCTRL */
+#define OMAP5_PWRONRST_SHIFT                    1
+#define OMAP5_PWRONRST_WIDTH                    0x1
+#define OMAP5_PWRONRST_MASK                     (1 << 1)
+
+/* Used by REVISION_SCRM */
+#define OMAP5_REV_SHIFT                         0
+#define OMAP5_REV_WIDTH                         0x8
+#define OMAP5_REV_MASK                          (0xff << 0)
+
+/* Used by RSTTIME */
+#define OMAP5_RSTTIME_SHIFT                     0
+#define OMAP5_RSTTIME_WIDTH                     0x4
+#define OMAP5_RSTTIME_MASK                      (0xf << 0)
+
+/* Used by CLKSETUPTIME */
+#define OMAP5_SETUPTIME_SHIFT                   0
+#define OMAP5_SETUPTIME_WIDTH                   0xc
+#define OMAP5_SETUPTIME_MASK                    (0xfff << 0)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_SLEEPTIME_SHIFT                   0
+#define OMAP5_SLEEPTIME_WIDTH                   0x6
+#define OMAP5_SLEEPTIME_MASK                    (0x3f << 0)
+
+/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */
+#define OMAP5_SRCSELECT_SHIFT                   1
+#define OMAP5_SRCSELECT_WIDTH                   0x2
+#define OMAP5_SRCSELECT_MASK                    (0x3 << 1)
+
+/* Used by D2DCLKM */
+#define OMAP5_SYSCLK_SHIFT                      1
+#define OMAP5_SYSCLK_WIDTH                      0x1
+#define OMAP5_SYSCLK_MASK                       (1 << 1)
+
+/* Used by PMICSETUPTIME */
+#define OMAP5_WAKEUPTIME_SHIFT                  16
+#define OMAP5_WAKEUPTIME_WIDTH                  0x6
+#define OMAP5_WAKEUPTIME_MASK                   (0x3f << 16)
+
+/* Used by D2DRSTCTRL, MODEMRSTCTRL */
+#define OMAP5_WARMRST_SHIFT                     1
+#define OMAP5_WARMRST_WIDTH                     0x1
+#define OMAP5_WARMRST_MASK                      (1 << 1)
+
+#endif
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index f6601563aa69..3a674de6cb63 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -63,7 +63,6 @@ struct omap_uart_state {
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
 static u8 console_uart_id = -1;
-static u8 no_console_suspend;
 static u8 uart_debug;
 
 #define DEFAULT_RXDMA_POLLRATE          1       /* RX DMA polling rate (us) */
@@ -176,6 +175,9 @@ static char *cmdline_find_option(char *str)
 
 static int __init omap_serial_early_init(void)
 {
+        if (of_have_populated_dt())
+                return -ENODEV;
+
         do {
                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
                 struct omap_hwmod *oh;
@@ -207,9 +209,6 @@ static int __init omap_serial_early_init(void)
                                         uart_name, uart->num);
                         }
 
-                        if (cmdline_find_option("no_console_suspend"))
-                                no_console_suspend = true;
-
                         /*
                          * omap-uart can be used for earlyprintk logs
                          * So if omap-uart is used as console then prevent
@@ -292,9 +291,6 @@ void __init omap_serial_init_port(struct omap_board_data *bdata,
                 return;
         }
 
-        if ((console_uart_id == bdata->id) && no_console_suspend)
-                omap_device_disable_idle_on_suspend(pdev);
-
         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 
         if (console_uart_id == bdata->id) {
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index aee3c8940a30..7a42e1960c3b 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -26,14 +26,14 @@ static int sr_class3_enable(struct omap_sr *sr)
         }
 
         omap_vp_enable(sr->voltdm);
-        return sr_enable(sr->voltdm, volt);
+        return sr_enable(sr, volt);
 }
 
 static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-        sr_disable_errgen(sr->voltdm);
+        sr_disable_errgen(sr);
         omap_vp_disable(sr->voltdm);
-        sr_disable(sr->voltdm);
+        sr_disable(sr);
         if (is_volt_reset)
                 voltdm_reset(sr->voltdm);
 
@@ -42,7 +42,7 @@ static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 
 static int sr_class3_configure(struct omap_sr *sr)
 {
-        return sr_configure_errgen(sr->voltdm);
+        return sr_configure_errgen(sr);
 }
 
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 197cc16870d9..8c616e436bc7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -96,6 +96,15 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_AM43XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am43xx
+# endif
+#endif
+
 /*
  * Omap device type i.e. EMU/HS/TST/GP/BAD
  */
@@ -187,6 +196,7 @@ IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
 IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
+IS_AM_CLASS(43xx, 0x43)
 
 IS_TI_CLASS(81xx, 0x81)
 
@@ -202,6 +212,7 @@ IS_OMAP_SUBCLASS(543x, 0x543)
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
 IS_AM_SUBCLASS(335x, 0x335)
+IS_AM_SUBCLASS(437x, 0x437)
 
 #define cpu_is_omap24xx()               0
 #define cpu_is_omap242x()               0
@@ -214,6 +225,8 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define soc_is_am35xx()                 0
 #define soc_is_am33xx()                 0
 #define soc_is_am335x()                 0
+#define soc_is_am43xx()                 0
+#define soc_is_am437x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
@@ -341,6 +354,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define soc_is_am335x()                is_am335x()
 #endif
 
+#ifdef  CONFIG_SOC_AM43XX
+# undef soc_is_am43xx
+# undef soc_is_am437x
+# define soc_is_am43xx()                is_am43xx()
+# define soc_is_am437x()                is_am437x()
+#endif
+
 # if defined(CONFIG_ARCH_OMAP4)
 # undef cpu_is_omap44xx
 # undef cpu_is_omap443x
@@ -383,6 +403,8 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define TI816X_CLASS            0x81600034
 #define TI8168_REV_ES1_0        TI816X_CLASS
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (0x1 << 8))
+#define TI8168_REV_ES2_0        (TI816X_CLASS | (0x2 << 8))
+#define TI8168_REV_ES2_1        (TI816X_CLASS | (0x3 << 8))
 
 #define TI814X_CLASS            0x81400034
 #define TI8148_REV_ES1_0        TI814X_CLASS
@@ -398,6 +420,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM335X_REV_ES2_0        (AM335X_CLASS | (0x1 << 8))
 #define AM335X_REV_ES2_1        (AM335X_CLASS | (0x2 << 8))
 
+#define AM437X_CLASS            0x43700000
+#define AM437X_REV_ES1_0        AM437X_CLASS
+
 #define OMAP443X_CLASS          0x44300044
 #define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
 #define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
@@ -424,6 +449,7 @@ void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
+void am33xx_check_features(void);
 void omap4xxx_check_features(void);
 
 /*
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 0ff0f068bea8..4bd096836235 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -119,6 +119,9 @@ static void __init omap_detect_sram(void)
                 if (soc_is_am33xx()) {
                         omap_sram_start = AM33XX_SRAM_PA;
                         omap_sram_size = 0x10000; /* 64K */
+                } else if (soc_is_am43xx()) {
+                        omap_sram_start = AM33XX_SRAM_PA;
+                        omap_sram_size = SZ_256K;
                 } else if (cpu_is_omap34xx()) {
                         omap_sram_start = OMAP3_SRAM_PA;
                         omap_sram_size = 0x10000; /* 64K */
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index f8b23b8040d9..3bdb0fb02028 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -582,7 +582,7 @@ OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
                         2, "timer_sys_ck", NULL);
 #endif /* CONFIG_ARCH_OMAP2 */
 
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
                         2, "timer_sys_ck", NULL);
 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 51e138cc5398..c05898fbd634 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -140,6 +140,7 @@ static struct regulator_init_data omap3_vdac_idata = {
 
 static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
         REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dpi.0"),
         REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi.0"),
 };
 
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index aa27d7f5cbb7..2eb19d4d0aa1 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,6 +28,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/usb/phy.h>
+#include <linux/usb/nop-usb-xceiv.h>
 
 #include "soc.h"
 #include "omap_device.h"
@@ -188,125 +189,6 @@ static void __init setup_ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
         return;
 }
 
-static
-void __init setup_4430ehci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case OMAP_EHCI_PORT_MODE_PHY:
-                omap_mux_init_signal("usbb1_ulpiphy_stp",
-                        OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("usbb1_ulpiphy_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpiphy_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_EHCI_PORT_MODE_TLL:
-                omap_mux_init_signal("usbb1_ulpitll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("usbb1_ulpitll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_ulpitll_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                        break;
-        }
-        switch (port_mode[1]) {
-        case OMAP_EHCI_PORT_MODE_PHY:
-                omap_mux_init_signal("usbb2_ulpiphy_stp",
-                        OMAP_PIN_OUTPUT);
-                omap_mux_init_signal("usbb2_ulpiphy_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpiphy_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_EHCI_PORT_MODE_TLL:
-                omap_mux_init_signal("usbb2_ulpitll_stp",
-                        OMAP_PIN_INPUT_PULLUP);
-                omap_mux_init_signal("usbb2_ulpitll_clk",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dir",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_nxt",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat1",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat2",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat3",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat4",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat5",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat6",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_ulpitll_dat7",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                        break;
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                        break;
-        }
-}
-
 static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 {
         switch (port_mode[0]) {
@@ -404,78 +286,6 @@ static void __init setup_ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
         }
 }
 
-static
-void __init setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
-{
-        switch (port_mode[0]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_mm_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("usbb1_mm_txen",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("usbb1_mm_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb1_mm_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                break;
-        }
-
-        switch (port_mode[1]) {
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_rxdp",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_mm_rxdm",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-        case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
-        case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_rxrcv",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-        case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
-                omap_mux_init_signal("usbb2_mm_txen",
-                        OMAP_PIN_INPUT_PULLDOWN);
-
-
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
-        case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
-                omap_mux_init_signal("usbb2_mm_txdat",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                omap_mux_init_signal("usbb2_mm_txse0",
-                        OMAP_PIN_INPUT_PULLDOWN);
-                break;
-
-        case OMAP_USBHS_PORT_MODE_UNUSED:
-        default:
-                break;
-        }
-}
-
 void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
 {
         struct omap_hwmod       *uhh_hwm, *tll_hwm;
@@ -489,9 +299,6 @@ void __init usbhs_init(struct usbhs_omap_platform_data *pdata)
                 if (omap_rev() <= OMAP3430_REV_ES2_1)
                         pdata->single_ulpi_bypass = true;
 
-        } else if (cpu_is_omap44xx()) {
-                setup_4430ehci_io_mux(pdata->port_mode);
-                setup_4430ohci_io_mux(pdata->port_mode);
         }
 
         uhh_hwm = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
@@ -560,7 +367,8 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
         struct regulator_init_data *reg_data;
         struct fixed_voltage_config *config;
         struct platform_device *pdev;
-        int ret;
+        struct platform_device_info pdevinfo;
+        int ret = -ENOMEM;
 
         supplies = kzalloc(sizeof(*supplies), GFP_KERNEL);
         if (!supplies)
@@ -571,7 +379,7 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
 
         reg_data = kzalloc(sizeof(*reg_data), GFP_KERNEL);
         if (!reg_data)
-                return -ENOMEM;
+                goto err_data;
 
         reg_data->constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS;
         reg_data->consumer_supplies = supplies;
@@ -580,39 +388,53 @@ static int usbhs_add_regulator(char *name, char *dev_id, char *dev_supply,
         config = kmemdup(&hsusb_reg_config, sizeof(hsusb_reg_config),
                         GFP_KERNEL);
         if (!config)
-                return -ENOMEM;
+                goto err_config;
+
+        config->supply_name = kstrdup(name, GFP_KERNEL);
+        if (!config->supply_name)
+                goto err_supplyname;
 
-        config->supply_name = name;
         config->gpio = gpio;
         config->enable_high = polarity;
         config->init_data = reg_data;
 
         /* create a regulator device */
-        pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-        if (!pdev)
-                return -ENOMEM;
+        memset(&pdevinfo, 0, sizeof(pdevinfo));
+        pdevinfo.name = reg_name;
+        pdevinfo.id = PLATFORM_DEVID_AUTO;
+        pdevinfo.data = config;
+        pdevinfo.size_data = sizeof(*config);
 
-        pdev->id = PLATFORM_DEVID_AUTO;
-        pdev->name = reg_name;
-        pdev->dev.platform_data = config;
+        pdev = platform_device_register_full(&pdevinfo);
+        if (IS_ERR(pdev)) {
+                ret = PTR_ERR(pdev);
+                pr_err("%s: Failed registering regulator %s for %s : %d\n",
+                                __func__, name, dev_id, ret);
+                goto err_register;
+        }
 
-        ret = platform_device_register(pdev);
-        if (ret)
-                pr_err("%s: Failed registering regulator %s for %s\n",
-                                __func__, name, dev_id);
+        return 0;
 
+err_register:
+        kfree(config->supply_name);
+err_supplyname:
+        kfree(config);
+err_config:
+        kfree(reg_data);
+err_data:
+        kfree(supplies);
         return ret;
 }
 
+#define MAX_STR 20
+
 int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 {
-        char *rail_name;
-        int i, len;
+        char rail_name[MAX_STR];
+        int i;
         struct platform_device *pdev;
         char *phy_id;
-
-        /* the phy_id will be something like "nop_usb_xceiv.1" */
-        len = strlen(nop_name) + 3; /* 3 -> ".1" and NULL terminator */
+        struct platform_device_info pdevinfo;
 
         for (i = 0; i < num_phys; i++) {
 
@@ -627,25 +449,26 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
                         !gpio_is_valid(phy->vcc_gpio))
                         continue;
 
-                /* create a NOP PHY device */
-                pdev = kzalloc(sizeof(*pdev), GFP_KERNEL);
-                if (!pdev)
+                phy_id = kmalloc(MAX_STR, GFP_KERNEL);
+                if (!phy_id) {
+                        pr_err("%s: kmalloc() failed\n", __func__);
                         return -ENOMEM;
+                }
 
-                pdev->id = phy->port;
-                pdev->name = nop_name;
-                pdev->dev.platform_data = phy->platform_data;
-
-                phy_id = kmalloc(len, GFP_KERNEL);
-                if (!phy_id)
-                        return -ENOMEM;
-
-                scnprintf(phy_id, len, "nop_usb_xceiv.%d\n",
-                                        pdev->id);
-
-                if (platform_device_register(pdev)) {
-                        pr_err("%s: Failed to register device %s\n",
-                                __func__,  phy_id);
+                /* create a NOP PHY device */
+                memset(&pdevinfo, 0, sizeof(pdevinfo));
+                pdevinfo.name = nop_name;
+                pdevinfo.id = phy->port;
+                pdevinfo.data = phy->platform_data;
+                pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data);
+
+                scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d",
+                                        phy->port);
+                pdev = platform_device_register_full(&pdevinfo);
+                if (IS_ERR(pdev)) {
+                        pr_err("%s: Failed to register device %s : %ld\n",
+                                __func__,  phy_id, PTR_ERR(pdev));
+                        kfree(phy_id);
                         continue;
                 }
 
@@ -653,26 +476,15 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
 
                 /* Do we need RESET regulator ? */
                 if (gpio_is_valid(phy->reset_gpio)) {
-
-                        rail_name = kmalloc(13, GFP_KERNEL);
-                        if (!rail_name)
-                                return -ENOMEM;
-
-                        scnprintf(rail_name, 13, "hsusb%d_reset", phy->port);
-
+                        scnprintf(rail_name, MAX_STR,
+                                        "hsusb%d_reset", phy->port);
                         usbhs_add_regulator(rail_name, phy_id, "reset",
                                                 phy->reset_gpio, 1);
                 }
 
                 /* Do we need VCC regulator ? */
                 if (gpio_is_valid(phy->vcc_gpio)) {
-
-                        rail_name = kmalloc(13, GFP_KERNEL);
-                        if (!rail_name)
-                                return -ENOMEM;
-
-                        scnprintf(rail_name, 13, "hsusb%d_vcc", phy->port);
-
+                        scnprintf(rail_name, MAX_STR, "hsusb%d_vcc", phy->port);
                         usbhs_add_regulator(rail_name, phy_id, "vcc",
                                         phy->vcc_gpio, phy->vcc_polarity);
                 }
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 3242a554ad6b..8c4de2708cf2 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -85,9 +85,6 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
         musb_plat.mode = board_data->mode;
         musb_plat.extvbus = board_data->extvbus;
 
-        if (cpu_is_omap44xx())
-                musb_plat.has_mailbox = true;
-
         if (soc_is_am35xx()) {
                 oh_name = "am35x_otg_hs";
                 name = "musb-am35x";
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index a0ce4f10ff13..f7f2879b31b0 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -169,8 +169,8 @@ int omap_voltage_late_init(void);
 
 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
-extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
+extern void omap54xx_voltagedomains_init(void);
 
 struct voltagedomain *voltdm_lookup(const char *name);
 void voltdm_init(struct voltagedomain **voltdm_list);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
deleted file mode 100644
index 965458dc0cb9..000000000000
--- a/arch/arm/mach-omap2/voltagedomains33xx_data.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * AM33XX voltage domain data
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include "voltage.h"
-
-static struct voltagedomain am33xx_voltdm_mpu = {
-        .name           = "mpu",
-};
-
-static struct voltagedomain am33xx_voltdm_core = {
-        .name           = "core",
-};
-
-static struct voltagedomain am33xx_voltdm_rtc = {
-        .name           = "rtc",
-};
-
-static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
-        &am33xx_voltdm_mpu,
-        &am33xx_voltdm_core,
-        &am33xx_voltdm_rtc,
-        NULL,
-};
-
-void __init am33xx_voltagedomains_init(void)
-{
-        voltdm_init(voltagedomains_am33xx);
-}
diff --git a/arch/arm/mach-omap2/voltagedomains54xx_data.c b/arch/arm/mach-omap2/voltagedomains54xx_data.c
new file mode 100644
index 000000000000..33d22b87252d
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains54xx_data.c
@@ -0,0 +1,92 @@
+/*
+ * OMAP5 Voltage Management Routines
+ *
+ * Based on voltagedomains44xx_data.c
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+
+#include "common.h"
+
+#include "prm54xx.h"
+#include "voltage.h"
+#include "omap_opp_data.h"
+#include "vc.h"
+#include "vp.h"
+
+static const struct omap_vfsm_instance omap5_vdd_mpu_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_mm_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET,
+};
+
+static const struct omap_vfsm_instance omap5_vdd_core_vfsm = {
+        .voltsetup_reg = OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET,
+};
+
+static struct voltagedomain omap5_voltdm_mpu = {
+        .name = "mpu",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_mpu,
+        .vfsm = &omap5_vdd_mpu_vfsm,
+        .vp = &omap4_vp_mpu,
+};
+
+static struct voltagedomain omap5_voltdm_mm = {
+        .name = "mm",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_iva,
+        .vfsm = &omap5_vdd_mm_vfsm,
+        .vp = &omap4_vp_iva,
+};
+
+static struct voltagedomain omap5_voltdm_core = {
+        .name = "core",
+        .scalable = true,
+        .read = omap4_prm_vcvp_read,
+        .write = omap4_prm_vcvp_write,
+        .rmw = omap4_prm_vcvp_rmw,
+        .vc = &omap4_vc_core,
+        .vfsm = &omap5_vdd_core_vfsm,
+        .vp = &omap4_vp_core,
+};
+
+static struct voltagedomain omap5_voltdm_wkup = {
+        .name = "wkup",
+};
+
+static struct voltagedomain *voltagedomains_omap5[] __initdata = {
+        &omap5_voltdm_mpu,
+        &omap5_voltdm_mm,
+        &omap5_voltdm_core,
+        &omap5_voltdm_wkup,
+        NULL,
+};
+
+static const char *sys_clk_name __initdata = "sys_clkin";
+
+void __init omap54xx_voltagedomains_init(void)
+{
+        struct voltagedomain *voltdm;
+        int i;
+
+        for (i = 0; voltdm = voltagedomains_omap5[i], voltdm; i++)
+                voltdm->sys_clk.name = sys_clk_name;
+
+        voltdm_init(voltagedomains_omap5);
+};
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 13bae78b215a..b1022f4315f7 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -4,7 +4,6 @@ config ARCH_PICOXCELL
         select ARM_PATCH_PHYS_VIRT
         select ARM_VIC
         select CPU_V6K
-        select DW_APB_TIMER
         select DW_APB_TIMER_OF
         select GENERIC_CLOCKEVENTS
         select HAVE_TCM
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441ad1d18..b13f51bc35cf 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -8,20 +8,13 @@
  * All enquiries to support@picochip.com
  */
 #include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/irqchip.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include "common.h"
-
 #define PHYS_TO_IO(x)                   (((x) & 0x00ffffff) | 0xfe000000)
 #define PICOXCELL_PERIPH_BASE           0x80000000
 #define PICOXCELL_PERIPH_LENGTH         SZ_4M
@@ -86,9 +79,6 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
         .map_io         = picoxcell_map_io,
-        .nr_irqs        = NR_IRQS_LEGACY,
-        .init_irq       = irqchip_init,
-        .init_time      = dw_apb_timer_init,
         .init_machine   = picoxcell_init_machine,
         .dt_compat      = picoxcell_dt_match,
         .restart        = picoxcell_wdt_restart,
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
deleted file mode 100644
index 481b42a4ef15..000000000000
--- a/arch/arm/mach-picoxcell/common.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support@picochip.com
- */
-#ifndef __PICOXCELL_COMMON_H__
-#define __PICOXCELL_COMMON_H__
-
-#include <asm/mach/time.h>
-
-extern void dw_apb_timer_init(void);
-
-#endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 4f94cd87972a..2c70f74fed5d 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <linux/irqchip.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -17,16 +16,6 @@
 #include <linux/of_platform.h>
 #include "common.h"
 
-static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
-        { .compatible = "simple-bus", },
-        {},
-};
-
-void __init sirfsoc_mach_init(void)
-{
-        of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
-}
-
 void __init sirfsoc_init_late(void)
 {
         sirfsoc_pm_init();
@@ -55,9 +44,7 @@ DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
         .nr_irqs        = 128,
         .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = sirfsoc_init_time,
-        .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = atlas6_dt_match,
         .restart        = sirfsoc_restart,
@@ -66,18 +53,16 @@ MACHINE_END
 
 #ifdef CONFIG_ARCH_PRIMA2
 static const char *prima2_dt_match[] __initdata = {
-       "sirf,prima2",
-       NULL
+        "sirf,prima2",
+        NULL
 };
 
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
         .nr_irqs        = 128,
         .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = sirfsoc_init_time,
         .dma_zone_size  = SZ_256M,
-        .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = prima2_dt_match,
         .restart        = sirfsoc_restart,
@@ -94,9 +79,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
         /* Maintainer: Barry Song <baohua.song@csr.com> */
         .smp            = smp_ops(sirfsoc_smp_ops),
         .map_io         = sirfsoc_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = sirfsoc_init_time,
-        .init_machine   = sirfsoc_mach_init,
         .init_late      = sirfsoc_init_late,
         .dt_compat      = marco_dt_match,
         .restart        = sirfsoc_restart,
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c180bf01..02cc34388b05 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -9,7 +9,7 @@
 #include <linux/kernel.h>
 #include <linux/suspend.h>
 #include <linux/slab.h>
-#include <linux/module.h>
+#include <linux/export.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_device.h>
@@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, pwrc_ids);
-        if (!np)
-                panic("unable to find compatible pwrc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf pwrc node in dtb\n");
+                return -ENOENT;
+        }
 
         /*
          * pwrc behind rtciobrg is not located in memory space
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019ca0a48..d5e0cbc934c0 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void)
         struct device_node *np;
 
         np = of_find_matching_node(NULL, rstc_ids);
-        if (!np)
-                panic("unable to find compatible rstc node in dtb\n");
+        if (!np) {
+                pr_err("unable to find compatible sirf rstc node in dtb\n");
+                return -ENOENT;
+        }
 
         sirfsoc_rstc_base = of_iomap(np, 0);
         if (!sirfsoc_rstc_base)
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100dbf5a2e..a8427115ee07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -615,12 +615,14 @@ endmenu
 config PXA25x
         bool
         select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA21x/25x/26x variants
 
 config PXA27x
         bool
         select CPU_XSCALE
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA27x variants
 
@@ -633,6 +635,7 @@ config CPU_PXA26x
 config PXA3xx
         bool
         select CPU_XSC3
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Select code specific to PXA3xx variants
 
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 446563a7d1ad..f6726bb4eb95 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -833,21 +833,25 @@ static inline void em_x270_init_ac97(void) {}
 #endif
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int em_x270_module_matrix_keys[] = {
+static const unsigned int em_x270_module_matrix_keys[] = {
         KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B),
         KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT),
         KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D),
 };
 
+static struct matrix_keymap_data em_x270_matrix_keymap_data = {
+        .keymap                 = em_x270_module_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(em_x270_module_matrix_keys),
+};
+
 struct pxa27x_keypad_platform_data em_x270_module_keypad_info = {
         /* code map for the matrix keys */
         .matrix_key_rows        = 3,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = em_x270_module_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(em_x270_module_matrix_keys),
+        .matrix_keymap_data     = &em_x270_matrix_keymap_data,
 };
 
-static unsigned int em_x270_exeda_matrix_keys[] = {
+static const unsigned int em_x270_exeda_matrix_keys[] = {
         KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL),
         KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE),
         KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL),
@@ -889,12 +893,16 @@ static unsigned int em_x270_exeda_matrix_keys[] = {
         KEY(7, 6, 0), KEY(7, 7, 0),
 };
 
+static struct matrix_keymap_data em_x270_exeda_matrix_keymap_data = {
+        .keymap                 = em_x270_exeda_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(em_x270_exeda_matrix_keys),
+};
+
 struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = {
         /* code map for the matrix keys */
         .matrix_key_rows        = 8,
         .matrix_key_cols        = 8,
-        .matrix_key_map         = em_x270_exeda_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(em_x270_exeda_matrix_keys),
+        .matrix_keymap_data     = &em_x270_exeda_matrix_keymap_data,
 };
 
 static void __init em_x270_init_keypad(void)
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index dca10709be8f..fe2eb8394dff 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -392,7 +392,7 @@ static unsigned long e6_pin_config[] __initdata = {
 
 /* KEYPAD */
 #ifdef CONFIG_MACH_EZX_A780
-static unsigned int a780_key_map[] = {
+static const unsigned int a780_key_map[] = {
         KEY(0, 0, KEY_SEND),
         KEY(0, 1, KEY_BACK),
         KEY(0, 2, KEY_END),
@@ -424,11 +424,15 @@ static unsigned int a780_key_map[] = {
         KEY(4, 4, KEY_DOWN),
 };
 
+static struct matrix_keymap_data a780_matrix_keymap_data = {
+        .keymap                 = a780_key_map,
+        .keymap_size            = ARRAY_SIZE(a780_key_map),
+};
+
 static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
         .matrix_key_rows = 5,
         .matrix_key_cols = 5,
-        .matrix_key_map = a780_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(a780_key_map),
+        .matrix_keymap_data = &a780_matrix_keymap_data,
 
         .direct_key_map = { KEY_CAMERA },
         .direct_key_num = 1,
@@ -438,7 +442,7 @@ static struct pxa27x_keypad_platform_data a780_keypad_platform_data = {
 #endif /* CONFIG_MACH_EZX_A780 */
 
 #ifdef CONFIG_MACH_EZX_E680
-static unsigned int e680_key_map[] = {
+static const unsigned int e680_key_map[] = {
         KEY(0, 0, KEY_UP),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_RESERVED),
@@ -455,11 +459,15 @@ static unsigned int e680_key_map[] = {
         KEY(2, 3, KEY_KPENTER),
 };
 
+static struct matrix_keymap_data e680_matrix_keymap_data = {
+        .keymap                 = e680_key_map,
+        .keymap_size            = ARRAY_SIZE(e680_key_map),
+};
+
 static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
         .matrix_key_rows = 3,
         .matrix_key_cols = 4,
-        .matrix_key_map = e680_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(e680_key_map),
+        .matrix_keymap_data = &e680_matrix_keymap_data,
 
         .direct_key_map = {
                 KEY_CAMERA,
@@ -476,7 +484,7 @@ static struct pxa27x_keypad_platform_data e680_keypad_platform_data = {
 #endif /* CONFIG_MACH_EZX_E680 */
 
 #ifdef CONFIG_MACH_EZX_A1200
-static unsigned int a1200_key_map[] = {
+static const unsigned int a1200_key_map[] = {
         KEY(0, 0, KEY_RESERVED),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_PAGEDOWN),
@@ -513,18 +521,22 @@ static unsigned int a1200_key_map[] = {
         KEY(4, 5, KEY_RESERVED),
 };
 
+static struct matrix_keymap_data a1200_matrix_keymap_data = {
+        .keymap                 = a1200_key_map,
+        .keymap_size            = ARRAY_SIZE(a1200_key_map),
+};
+
 static struct pxa27x_keypad_platform_data a1200_keypad_platform_data = {
         .matrix_key_rows = 5,
         .matrix_key_cols = 6,
-        .matrix_key_map = a1200_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(a1200_key_map),
+        .matrix_keymap_data = &a1200_matrix_keymap_data,
 
         .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_A1200 */
 
 #ifdef CONFIG_MACH_EZX_E6
-static unsigned int e6_key_map[] = {
+static const unsigned int e6_key_map[] = {
         KEY(0, 0, KEY_RESERVED),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_PAGEDOWN),
@@ -561,18 +573,22 @@ static unsigned int e6_key_map[] = {
         KEY(4, 5, KEY_PREVIOUSSONG),
 };
 
+static struct matrix_keymap_data e6_keymap_data = {
+        .keymap                 = e6_key_map,
+        .keymap_size            = ARRAY_SIZE(e6_key_map),
+};
+
 static struct pxa27x_keypad_platform_data e6_keypad_platform_data = {
         .matrix_key_rows = 5,
         .matrix_key_cols = 6,
-        .matrix_key_map = e6_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(e6_key_map),
+        .matrix_keymap_data = &e6_keymap_data,
 
         .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_E6 */
 
 #ifdef CONFIG_MACH_EZX_A910
-static unsigned int a910_key_map[] = {
+static const unsigned int a910_key_map[] = {
         KEY(0, 0, KEY_NUMERIC_6),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_PAGEDOWN),
@@ -609,18 +625,22 @@ static unsigned int a910_key_map[] = {
         KEY(4, 5, KEY_RESERVED),
 };
 
+static struct matrix_keymap_data a910_matrix_keymap_data = {
+        .keymap                 = a910_key_map,
+        .keymap_size            = ARRAY_SIZE(a910_key_map),
+};
+
 static struct pxa27x_keypad_platform_data a910_keypad_platform_data = {
         .matrix_key_rows = 5,
         .matrix_key_cols = 6,
-        .matrix_key_map = a910_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(a910_key_map),
+        .matrix_keymap_data = &a910_matrix_keymap_data,
 
         .debounce_interval = 30,
 };
 #endif /* CONFIG_MACH_EZX_A910 */
 
 #ifdef CONFIG_MACH_EZX_E2
-static unsigned int e2_key_map[] = {
+static const unsigned int e2_key_map[] = {
         KEY(0, 0, KEY_NUMERIC_6),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_NUMERIC_9),
@@ -657,11 +677,15 @@ static unsigned int e2_key_map[] = {
         KEY(4, 5, KEY_RESERVED),
 };
 
+static struct matrix_keymap_data e2_matrix_keymap_data = {
+        .keymap                 = e2_key_map,
+        .keymap_size            = ARRAY_SIZE(e2_key_map),
+};
+
 static struct pxa27x_keypad_platform_data e2_keypad_platform_data = {
         .matrix_key_rows = 5,
         .matrix_key_cols = 6,
-        .matrix_key_map = e2_key_map,
-        .matrix_key_map_size = ARRAY_SIZE(e2_key_map),
+        .matrix_keymap_data = &e2_matrix_keymap_data,
 
         .debounce_interval = 30,
 };
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index e848c4607baf..5d665588c7eb 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -222,7 +222,7 @@ static inline void littleton_init_spi(void) {}
 #endif
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int littleton_matrix_key_map[] = {
+static const unsigned int littleton_matrix_key_map[] = {
         /* KEY(row, col, key_code) */
         KEY(1, 3, KEY_0), KEY(0, 0, KEY_1), KEY(1, 0, KEY_2), KEY(2, 0, KEY_3),
         KEY(0, 1, KEY_4), KEY(1, 1, KEY_5), KEY(2, 1, KEY_6), KEY(0, 2, KEY_7),
@@ -249,11 +249,15 @@ static unsigned int littleton_matrix_key_map[] = {
         KEY(3, 1, KEY_F23),     /* soft2 */
 };
 
+static struct matrix_keymap_data littleton_matrix_keymap_data = {
+        .keymap                 = littleton_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(littleton_matrix_key_map),
+};
+
 static struct pxa27x_keypad_platform_data littleton_keypad_info = {
         .matrix_key_rows        = 6,
         .matrix_key_cols        = 5,
-        .matrix_key_map         = littleton_matrix_key_map,
-        .matrix_key_map_size    = ARRAY_SIZE(littleton_matrix_key_map),
+        .matrix_keymap_data     = &littleton_matrix_keymap_data,
 
         .enable_rotary0         = 1,
         .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 7a12c1ba90ff..d2c652318376 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -498,7 +498,7 @@ static struct pxaohci_platform_data mainstone_ohci_platform_data = {
 };
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int mainstone_matrix_keys[] = {
+static const unsigned int mainstone_matrix_keys[] = {
         KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
         KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
         KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
@@ -527,11 +527,15 @@ static unsigned int mainstone_matrix_keys[] = {
         KEY(4, 6, KEY_SELECT),
 };
 
+static struct matrix_keymap_data mainstone_matrix_keymap_data = {
+        .keymap                 = mainstone_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(mainstone_matrix_keys),
+};
+
 struct pxa27x_keypad_platform_data mainstone_keypad_info = {
         .matrix_key_rows        = 6,
         .matrix_key_cols        = 7,
-        .matrix_key_map         = mainstone_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(mainstone_matrix_keys),
+        .matrix_keymap_data     = &mainstone_matrix_keymap_data,
 
         .enable_rotary0         = 1,
         .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f8979b943cbf..654b0ac84dea 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -222,7 +222,7 @@ static struct pxafb_mach_info mioa701_pxafb_info = {
 /*
  * Keyboard configuration
  */
-static unsigned int mioa701_matrix_keys[] = {
+static const unsigned int mioa701_matrix_keys[] = {
         KEY(0, 0, KEY_UP),
         KEY(0, 1, KEY_RIGHT),
         KEY(0, 2, KEY_MEDIA),
@@ -233,11 +233,16 @@ static unsigned int mioa701_matrix_keys[] = {
         KEY(2, 1, KEY_PHONE),   /* Phone Green key */
         KEY(2, 2, KEY_CAMERA)   /* Camera key */
 };
+
+static struct matrix_keymap_data mioa701_matrix_keymap_data = {
+        .keymap                 = mioa701_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(mioa701_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data mioa701_keypad_info = {
         .matrix_key_rows = 3,
         .matrix_key_cols = 3,
-        .matrix_key_map = mioa701_matrix_keys,
-        .matrix_key_map_size = ARRAY_SIZE(mioa701_matrix_keys),
+        .matrix_keymap_data = &mioa701_matrix_keymap_data,
 };
 
 /*
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 909b713e5789..cf210b11ffcc 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -173,7 +173,7 @@ static inline void palmld_nor_init(void) {}
  * GPIO keyboard
  ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmld_matrix_keys[] = {
+static const unsigned int palmld_matrix_keys[] = {
         KEY(0, 1, KEY_F2),
         KEY(0, 2, KEY_UP),
 
@@ -190,11 +190,15 @@ static unsigned int palmld_matrix_keys[] = {
         KEY(3, 2, KEY_LEFT),
 };
 
+static struct matrix_keymap_data palmld_matrix_keymap_data = {
+        .keymap                 = palmld_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmld_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = {
         .matrix_key_rows        = 4,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = palmld_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(palmld_matrix_keys),
+        .matrix_keymap_data     = &palmld_matrix_keymap_data,
 
         .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5033fd07968f..3ed9b029428b 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -108,7 +108,7 @@ static unsigned long palmt5_pin_config[] __initdata = {
  * GPIO keyboard
  ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmt5_matrix_keys[] = {
+static const unsigned int palmt5_matrix_keys[] = {
         KEY(0, 0, KEY_POWER),
         KEY(0, 1, KEY_F1),
         KEY(0, 2, KEY_ENTER),
@@ -124,11 +124,15 @@ static unsigned int palmt5_matrix_keys[] = {
         KEY(3, 2, KEY_LEFT),
 };
 
+static struct matrix_keymap_data palmt5_matrix_keymap_data = {
+        .keymap                 = palmt5_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmt5_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = {
         .matrix_key_rows        = 4,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = palmt5_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(palmt5_matrix_keys),
+        .matrix_keymap_data     = &palmt5_matrix_keymap_data,
 
         .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d82a50b4a803..d8b937c870de 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -168,7 +168,7 @@ static unsigned long centro685_pin_config[] __initdata = {
  * GPIO keyboard
  ******************************************************************************/
 #if IS_ENABLED(CONFIG_KEYBOARD_PXA27x)
-static unsigned int treo680_matrix_keys[] = {
+static const unsigned int treo680_matrix_keys[] = {
         KEY(0, 0, KEY_F8),              /* Red/Off/Power */
         KEY(0, 1, KEY_LEFT),
         KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
@@ -227,7 +227,7 @@ static unsigned int treo680_matrix_keys[] = {
         KEY(7, 5, KEY_I),
 };
 
-static unsigned int centro_matrix_keys[] = {
+static const unsigned int centro_matrix_keys[] = {
         KEY(0, 0, KEY_F9),              /* Home */
         KEY(0, 1, KEY_LEFT),
         KEY(0, 2, KEY_LEFTCTRL),        /* Alternate */
@@ -286,11 +286,20 @@ static unsigned int centro_matrix_keys[] = {
         KEY(7, 5, KEY_I),
 };
 
+static struct matrix_keymap_data treo680_matrix_keymap_data = {
+        .keymap                 = treo680_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(treo680_matrix_keys),
+};
+
+static struct matrix_keymap_data centro_matrix_keymap_data = {
+        .keymap                 = centro_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(centro_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data treo680_keypad_pdata = {
         .matrix_key_rows        = 8,
         .matrix_key_cols        = 7,
-        .matrix_key_map         = treo680_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(treo680_matrix_keys),
+        .matrix_keymap_data     = &treo680_matrix_keymap_data,
         .direct_key_map         = { KEY_CONNECT },
         .direct_key_num         = 1,
 
@@ -301,10 +310,8 @@ static void __init palmtreo_kpc_init(void)
 {
         static struct pxa27x_keypad_platform_data *data = &treo680_keypad_pdata;
 
-        if (machine_is_centro()) {
-                data->matrix_key_map = centro_matrix_keys;
-                data->matrix_key_map_size = ARRAY_SIZE(centro_matrix_keys);
-        }
+        if (machine_is_centro())
+                data->matrix_keymap_data = &centro_matrix_keymap_data;
 
         pxa_set_keypad_info(&treo680_keypad_pdata);
 }
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 627c93a7364c..83f830dd8ad8 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -176,7 +176,7 @@ static inline void palmtx_nor_init(void) {}
  * GPIO keyboard
  ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmtx_matrix_keys[] = {
+static const unsigned int palmtx_matrix_keys[] = {
         KEY(0, 0, KEY_POWER),
         KEY(0, 1, KEY_F1),
         KEY(0, 2, KEY_ENTER),
@@ -192,11 +192,15 @@ static unsigned int palmtx_matrix_keys[] = {
         KEY(3, 2, KEY_LEFT),
 };
 
+static struct matrix_keymap_data palmtx_matrix_keymap_data = {
+        .keymap                 = palmtx_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmtx_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data palmtx_keypad_platform_data = {
         .matrix_key_rows        = 4,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = palmtx_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(palmtx_matrix_keys),
+        .matrix_keymap_data     = &palmtx_matrix_keymap_data,
 
         .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 18b7fcd98592..1a35ddf218da 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -140,7 +140,7 @@ static unsigned long palmz72_pin_config[] __initdata = {
  * GPIO keyboard
  ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int palmz72_matrix_keys[] = {
+static const unsigned int palmz72_matrix_keys[] = {
         KEY(0, 0, KEY_POWER),
         KEY(0, 1, KEY_F1),
         KEY(0, 2, KEY_ENTER),
@@ -156,11 +156,15 @@ static unsigned int palmz72_matrix_keys[] = {
         KEY(3, 2, KEY_LEFT),
 };
 
+static struct matrix_keymap_data almz72_matrix_keymap_data = {
+        .keymap                 = palmz72_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(palmz72_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data palmz72_keypad_platform_data = {
         .matrix_key_rows        = 4,
         .matrix_key_cols        = 3,
-        .matrix_key_map         = palmz72_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(palmz72_matrix_keys),
+        .matrix_keymap_data     = &almz72_matrix_keymap_data,
 
         .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f55979c09a5f..4680efe55345 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -106,7 +106,7 @@ static struct platform_device smc91x_device = {
 };
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int tavorevb_matrix_key_map[] = {
+static const unsigned int tavorevb_matrix_key_map[] = {
         /* KEY(row, col, key_code) */
         KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C),
         KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G),
@@ -147,11 +147,15 @@ static unsigned int tavorevb_matrix_key_map[] = {
         KEY(3, 3, KEY_F23),     /* soft2 */
 };
 
+static struct matrix_keymap_data tavorevb_matrix_keymap_data = {
+        .keymap         = tavorevb_matrix_key_map,
+        .keymap_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
+};
+
 static struct pxa27x_keypad_platform_data tavorevb_keypad_info = {
         .matrix_key_rows        = 7,
         .matrix_key_cols        = 7,
-        .matrix_key_map         = tavorevb_matrix_key_map,
-        .matrix_key_map_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
+        .matrix_keymap_data     = &tavorevb_matrix_keymap_data,
         .debounce_interval      = 30,
 };
 
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 989903a7e467..2513d8f4931f 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -345,7 +345,7 @@ static inline void z2_leds_init(void) {}
  * GPIO keyboard
  ******************************************************************************/
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int z2_matrix_keys[] = {
+static const unsigned int z2_matrix_keys[] = {
         KEY(0, 0, KEY_OPTION),
         KEY(1, 0, KEY_UP),
         KEY(2, 0, KEY_DOWN),
@@ -405,11 +405,15 @@ static unsigned int z2_matrix_keys[] = {
         KEY(5, 7, KEY_DOT),
 };
 
+static struct matrix_keymap_data z2_matrix_keymap_data = {
+        .keymap                 = z2_matrix_keys,
+        .keymap_size            = ARRAY_SIZE(z2_matrix_keys),
+};
+
 static struct pxa27x_keypad_platform_data z2_keypad_platform_data = {
         .matrix_key_rows        = 7,
         .matrix_key_cols        = 8,
-        .matrix_key_map         = z2_matrix_keys,
-        .matrix_key_map_size    = ARRAY_SIZE(z2_matrix_keys),
+        .matrix_keymap_data     = &z2_matrix_keymap_data,
 
         .debounce_interval      = 30,
 };
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 1f00d650ac27..36cf7cf95ec1 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -263,7 +263,7 @@ static inline void zylonite_init_mmc(void) {}
 #endif
 
 #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
-static unsigned int zylonite_matrix_key_map[] = {
+static const unsigned int zylonite_matrix_key_map[] = {
         /* KEY(row, col, key_code) */
         KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_C), KEY(0, 5, KEY_D),
         KEY(1, 0, KEY_E), KEY(1, 1, KEY_F), KEY(1, 2, KEY_G), KEY(1, 5, KEY_H),
@@ -306,11 +306,15 @@ static unsigned int zylonite_matrix_key_map[] = {
         KEY(0, 3, KEY_AUX),     /* contact */
 };
 
+static struct matrix_keymap_data zylonite_matrix_keymap_data = {
+        .keymap                 = zylonite_matrix_key_map,
+        .keymap_size            = ARRAY_SIZE(zylonite_matrix_key_map),
+};
+
 static struct pxa27x_keypad_platform_data zylonite_keypad_info = {
         .matrix_key_rows        = 8,
         .matrix_key_cols        = 8,
-        .matrix_key_map         = zylonite_matrix_key_map,
-        .matrix_key_map_size    = ARRAY_SIZE(zylonite_matrix_key_map),
+        .matrix_keymap_data     = &zylonite_matrix_keymap_data,
 
         .enable_rotary0         = 1,
         .rotary0_up_key         = KEY_UP,
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 000000000000..25ee12b21f01
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_ROCKCHIP
+        bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
+        select PINCTRL
+        select PINCTRL_ROCKCHIP
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_GIC
+        select CACHE_L2X0
+        select HAVE_ARM_TWD if LOCAL_TIMERS
+        select HAVE_SMP
+        select LOCAL_TIMERS if SMP
+        select COMMON_CLK
+        select GENERIC_CLOCKEVENTS
+        select DW_APB_TIMER_OF
+        help
+          Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
+          containing the RK2928, RK30xx and RK31xx series.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 000000000000..1547d4fc920a
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
new file mode 100644
index 000000000000..724d2d81f976
--- /dev/null
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -0,0 +1,52 @@
+/*
+ * Device Tree support for Rockchip SoCs
+ *
+ * Copyright (c) 2013 MundoReader S.L.
+ * Author: Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/irqchip.h>
+#include <linux/dw_apb_timer.h>
+#include <linux/clk-provider.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+static void __init rockchip_timer_init(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+}
+
+static void __init rockchip_dt_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const rockchip_board_dt_compat[] = {
+        "rockchip,rk2928",
+        "rockchip,rk3066a",
+        "rockchip,rk3066b",
+        "rockchip,rk3188",
+        NULL,
+};
+
+DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+        .init_machine   = rockchip_dt_init,
+        .init_time      = rockchip_timer_init,
+        .dt_compat      = rockchip_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index f2f7088bfd22..6d9252e081ce 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -28,9 +28,10 @@ config CPU_S3C2410
         select CPU_ARM920T
         select CPU_LLSERIAL_S3C2410
         select S3C2410_CLOCK
-        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
+        select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
         select S3C2410_PM if PM
         select SAMSUNG_HRT
+        select SAMSUNG_WDT_RESET
         help
           Support for S3C2410 and S3C2410A family from the S3C24XX line
           of Samsung Mobile CPUs.
@@ -81,6 +82,7 @@ config CPU_S3C2442
 config CPU_S3C244X
         def_bool y
         depends on CPU_S3C2440 || CPU_S3C2442
+        select SAMSUNG_WDT_RESET
 
 config CPU_S3C2443
         bool "SAMSUNG S3C2443"
@@ -204,27 +206,38 @@ config S3C24XX_GPIO_EXTRA128
           Add an extra 128 gpio numbers to the available GPIO pool. This is
           available for boards that need extra gpios for external devices.
 
+config S3C24XX_PLL
+        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
+        depends on ARM_S3C24XX
+        help
+          Compile in support for changing the PLL frequency from the
+          S3C24XX series CPUfreq driver. The PLL takes time to settle
+          after a frequency change, so by default it is not enabled.
+
+          This also means that the PLL tables for the selected CPU(s) will
+          be built which may increase the size of the kernel image.
+
 # cpu frequency items common between s3c2410 and s3c2440/s3c2442
 
 config S3C2410_IOTIMING
         bool
-        depends on CPU_FREQ_S3C24XX
+        depends on ARM_S3C24XX_CPUFREQ
         help
           Internal node to select io timing code that is common to the s3c2410
           and s3c2440/s3c2442 cpu frequency support.
 
 config S3C2410_CPUFREQ_UTILS
-        bool
-        depends on CPU_FREQ_S3C24XX
-        help
-          Internal node to select timing code that is common to the s3c2410
-          and s3c2440/s3c244 cpu frequency support.
+       bool
+       depends on ARM_S3C24XX_CPUFREQ
+       help
+         Internal node to select timing code that is common to the s3c2410
+         and s3c2440/s3c244 cpu frequency support.
 
 # cpu frequency support common to s3c2412, s3c2413 and s3c2442
 
 config S3C2412_IOTIMING
         bool
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        depends on ARM_S3C24XX_CPUFREQ && (CPU_S3C2412 || CPU_S3C2443)
         help
           Intel node to select io timing code that is common to the s3c2412
           and the s3c2443.
@@ -233,16 +246,9 @@ config S3C2412_IOTIMING
 
 if CPU_S3C2410
 
-config S3C2410_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2410
-
 config S3C2410_PLL
         bool
-        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        depends on ARM_S3C2410_CPUFREQ && S3C24XX_PLL
         default y
         help
           Select the PLL table for the S3C2410
@@ -278,7 +284,7 @@ config ARCH_BAST
         bool "Simtec Electronics BAST (EB2410ITX)"
         select ISA
         select MACH_BAST_IDE
-        select S3C2410_IOTIMING if S3C2410_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
         select S3C24XX_DCLK
         select S3C24XX_SIMTEC_NOR
         select S3C24XX_SIMTEC_PM if PM
@@ -385,14 +391,6 @@ config CPU_S3C2412_ONLY
                    !CPU_S3C2442 && !CPU_S3C2443
         default y
 
-config S3C2412_CPUFREQ
-        bool
-        depends on CPU_FREQ_S3C24XX
-        default y
-        select S3C2412_IOTIMING
-        help
-          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
-
 config S3C2412_DMA
         bool
         help
@@ -490,18 +488,22 @@ config MACH_SMDK2416
         help
           Say Y here if you are using an SMDK2416
 
+config MACH_S3C2416_DT
+        bool "Samsung S3C2416 machine using devicetree"
+        select CLKSRC_OF
+        select USE_OF
+        select PINCTRL
+        select PINCTRL_S3C24XX
+        help
+          Machine support for Samsung S3C2416 machines with device tree enabled.
+          Select this if a fdt blob is available for the S3C2416 SoC based board.
+          Note: This is under development and not all peripherals can be supported
+          with this machine file.
+
 endif   # CPU_S3C2416
 
 if CPU_S3C2440
 
-config S3C2440_CPUFREQ
-        bool "S3C2440/S3C2442 CPU Frequency scaling support"
-        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
-        default y
-        select S3C2410_CPUFREQ_UTILS
-        help
-          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
-
 config S3C2440_DMA
         bool
         help
@@ -521,15 +523,15 @@ config S3C2440_XTAL_16934400
 
 config S3C2440_PLL_12000000
         bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
-        default y if CPU_FREQ_S3C24XX_PLL
+        depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if S3C24XX_PLL
         help
           PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
 
 config S3C2440_PLL_16934400
         bool
-        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
-        default y if CPU_FREQ_S3C24XX_PLL
+        depends on ARM_S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if S3C24XX_PLL
         help
           PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
 
@@ -583,7 +585,7 @@ config MACH_NEXCODER_2440
 
 config MACH_OSIRIS
         bool "Simtec IM2440D20 (OSIRIS) module"
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
         select S3C2440_XTAL_12000000
         select S3C24XX_DCLK
         select S3C24XX_GPIO_EXTRA128
@@ -655,7 +657,7 @@ config MACH_RX1950
         bool "HP iPAQ rx1950"
         select I2C
         select PM_H1940 if PM
-        select S3C2410_IOTIMING if S3C2440_CPUFREQ
+        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
         select S3C2440_XTAL_16934400
         select S3C24XX_DCLK
         select S3C24XX_PWM
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 6f46ecfc8396..7f54e5b954ca 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -17,13 +17,11 @@ obj-				:=
 obj-y                           += common.o
 
 obj-$(CONFIG_CPU_S3C2410)       += s3c2410.o
-obj-$(CONFIG_S3C2410_CPUFREQ)   += cpufreq-s3c2410.o
 obj-$(CONFIG_S3C2410_DMA)       += dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
 
 obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
-obj-$(CONFIG_S3C2412_CPUFREQ)   += cpufreq-s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
@@ -34,7 +32,6 @@ obj-$(CONFIG_S3C2416_PM)	+= pm-s3c2416.o
 obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
-obj-$(CONFIG_S3C2440_CPUFREQ)   += cpufreq-s3c2440.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
@@ -59,9 +56,6 @@ obj-$(CONFIG_S3C2412_IOTIMING)	+= iotiming-s3c2412.o
 obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
 
-obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpufreq.o
-obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpufreq-debugfs.o
-
 #
 # machine support
 # following is ordered alphabetically by option text.
@@ -85,6 +79,7 @@ obj-$(CONFIG_MACH_SMDK2413)		+= mach-smdk2413.o
 obj-$(CONFIG_MACH_VSTMS)                += mach-vstms.o
 
 obj-$(CONFIG_MACH_SMDK2416)             += mach-smdk2416.o
+obj-$(CONFIG_MACH_S3C2416_DT)           += mach-s3c2416-dt.o
 
 obj-$(CONFIG_MACH_ANUBIS)               += mach-anubis.o
 obj-$(CONFIG_MACH_AT2440EVB)            += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c b/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
deleted file mode 100644
index 9b7b4289d66c..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-debugfs.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2009 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX CPU Frequency scaling - debugfs status support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/err.h>
-
-#include <plat/cpu-freq-core.h>
-
-static struct dentry *dbgfs_root;
-static struct dentry *dbgfs_file_io;
-static struct dentry *dbgfs_file_info;
-static struct dentry *dbgfs_file_board;
-
-#define print_ns(x) ((x) / 10), ((x) % 10)
-
-static void show_max(struct seq_file *seq, struct s3c_freq *f)
-{
-        seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
-                   f->fclk, f->hclk, f->pclk, f->armclk);
-}
-
-static int board_show(struct seq_file *seq, void *p)
-{
-        struct s3c_cpufreq_config *cfg;
-        struct s3c_cpufreq_board *brd;
-
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-
-        brd = cfg->board;
-        if (!brd) {
-                seq_printf(seq, "no board definition set?\n");
-                return 0;
-        }
-
-        seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
-        seq_printf(seq, "auto_io=%u\n", brd->auto_io);
-        seq_printf(seq, "need_io=%u\n", brd->need_io);
-
-        show_max(seq, &brd->max);
-
-
-        return 0;
-}
-
-static int fops_board_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, board_show, NULL);
-}
-
-static const struct file_operations fops_board = {
-        .open           = fops_board_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-
-static int info_show(struct seq_file *seq, void *p)
-{
-        struct s3c_cpufreq_config *cfg;
-
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-
-        seq_printf(seq, "  FCLK %ld Hz\n", cfg->freq.fclk);
-        seq_printf(seq, "  HCLK %ld Hz (%lu.%lu ns)\n",
-                   cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
-        seq_printf(seq, "  PCLK %ld Hz\n", cfg->freq.hclk);
-        seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
-        seq_printf(seq, "\n");
-
-        show_max(seq, &cfg->max);
-
-        seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
-                   cfg->divs.h_divisor, cfg->divs.p_divisor,
-                   cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
-        seq_printf(seq, "\n");
-
-        seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
-
-        return 0;
-}
-
-static int fops_info_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, info_show, NULL);
-}
-
-static const struct file_operations fops_info = {
-        .open           = fops_info_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-
-static int io_show(struct seq_file *seq, void *p)
-{
-        void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
-        struct s3c_cpufreq_config *cfg;
-        struct s3c_iotimings *iot;
-        union s3c_iobank *iob;
-        int bank;
-
-        cfg = s3c_cpufreq_getconfig();
-        if (!cfg) {
-                seq_printf(seq, "no configuration registered\n");
-                return 0;
-        }
-
-        show_bank = cfg->info->debug_io_show;
-        if (!show_bank) {
-                seq_printf(seq, "no code to show bank timing\n");
-                return 0;
-        }
-
-        iot = s3c_cpufreq_getiotimings();
-        if (!iot) {
-                seq_printf(seq, "no io timings registered\n");
-                return 0;
-        }
-
-        seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
-
-        for (bank = 0; bank < MAX_BANKS; bank++) {
-                iob = &iot->bank[bank];
-
-                seq_printf(seq, "bank %d: ", bank);
-
-                if (!iob->io_2410) {
-                        seq_printf(seq, "nothing set\n");
-                        continue;
-                }
-
-                show_bank(seq, cfg, iob);
-        }
-
-        return 0;
-}
-
-static int fops_io_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, io_show, NULL);
-}
-
-static const struct file_operations fops_io = {
-        .open           = fops_io_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .owner          = THIS_MODULE,
-};
-
-
-static int __init s3c_freq_debugfs_init(void)
-{
-        dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
-        if (IS_ERR(dbgfs_root)) {
-                printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
-                return PTR_ERR(dbgfs_root);
-        }
-
-        dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
-                                            NULL, &fops_io);
-
-        dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
-                                              NULL, &fops_info);
-
-        dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
-                                               NULL, &fops_board);
-
-        return 0;
-}
-
-late_initcall(s3c_freq_debugfs_init);
-
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
deleted file mode 100644
index cfa0dd8723ec..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2410.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Copyright (c) 2006-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-
-/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
-
-static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        u32 clkdiv = 0;
-
-        if (cfg->divs.h_divisor == 2)
-                clkdiv |= S3C2410_CLKDIVN_HDIVN;
-
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2410_CLKDIVN_PDIVN;
-
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-}
-
-static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long hclk, fclk, pclk;
-        unsigned int hdiv, pdiv;
-        unsigned long hclk_max;
-
-        fclk = cfg->freq.fclk;
-        hclk_max = cfg->max.hclk;
-
-        cfg->freq.armclk = fclk;
-
-        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
-                      __func__, fclk, hclk_max);
-
-        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
-        hclk = fclk / hdiv;
-
-        if (hclk > cfg->max.hclk) {
-                s3c_freq_dbg("%s: hclk too big\n", __func__);
-                return -EINVAL;
-        }
-
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-        pclk = hclk / pdiv;
-
-        if (pclk > cfg->max.pclk) {
-                s3c_freq_dbg("%s: pclk too big\n", __func__);
-                return -EINVAL;
-        }
-
-        pdiv *= hdiv;
-
-        /* record the result */
-        cfg->divs.p_divisor = pdiv;
-        cfg->divs.h_divisor = hdiv;
-
-        return 0;
-}
-
-static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
-        .max            = {
-                .fclk   = 200000000,
-                .hclk   = 100000000,
-                .pclk   =  50000000,
-        },
-
-        /* transition latency is about 5ms worst-case, so
-         * set 10ms to be sure */
-        .latency        = 10000000,
-
-        .locktime_m     = 150,
-        .locktime_u     = 150,
-        .locktime_bits  = 12,
-
-        .need_pll       = 1,
-
-        .name           = "s3c2410",
-        .calc_iotiming  = s3c2410_iotiming_calc,
-        .set_iotiming   = s3c2410_iotiming_set,
-        .get_iotiming   = s3c2410_iotiming_get,
-        .resume_clocks  = s3c2410_setup_clocks,
-
-        .set_fvco       = s3c2410_set_fvco,
-        .set_refresh    = s3c2410_cpufreq_setrefresh,
-        .set_divs       = s3c2410_cpufreq_setdivs,
-        .calc_divs      = s3c2410_cpufreq_calcdivs,
-
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
-};
-
-static int s3c2410_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
-}
-
-static struct subsys_interface s3c2410_cpufreq_interface = {
-        .name           = "s3c2410_cpufreq",
-        .subsys         = &s3c2410_subsys,
-        .add_dev        = s3c2410_cpufreq_add,
-};
-
-static int __init s3c2410_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2410_cpufreq_interface);
-}
-arch_initcall(s3c2410_cpufreq_init);
-
-static int s3c2410a_cpufreq_add(struct device *dev,
-                                struct subsys_interface *sif)
-{
-        /* alter the maximum freq settings for S3C2410A. If a board knows
-         * it only has a maximum of 200, then it should register its own
-         * limits. */
-
-        s3c2410_cpufreq_info.max.fclk = 266000000;
-        s3c2410_cpufreq_info.max.hclk = 133000000;
-        s3c2410_cpufreq_info.max.pclk =  66500000;
-        s3c2410_cpufreq_info.name = "s3c2410a";
-
-        return s3c2410_cpufreq_add(dev, sif);
-}
-
-static struct subsys_interface s3c2410a_cpufreq_interface = {
-        .name           = "s3c2410a_cpufreq",
-        .subsys         = &s3c2410a_subsys,
-        .add_dev        = s3c2410a_cpufreq_add,
-};
-
-static int __init s3c2410a_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2410a_cpufreq_interface);
-}
-arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
deleted file mode 100644
index 8bf0f3a77476..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2412.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2412 CPU Frequency scalling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-
-#include "s3c2412.h"
-
-/* our clock resources. */
-static struct clk *xtal;
-static struct clk *fclk;
-static struct clk *hclk;
-static struct clk *armclk;
-
-/* HDIV: 1, 2, 3, 4, 6, 8 */
-
-static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned int hdiv, pdiv, armdiv, dvs;
-        unsigned long hclk, fclk, armclk, armdiv_clk;
-        unsigned long hclk_max;
-
-        fclk = cfg->freq.fclk;
-        armclk = cfg->freq.armclk;
-        hclk_max = cfg->max.hclk;
-
-        /* We can't run hclk above armclk as at the best we have to
-         * have armclk and hclk in dvs mode. */
-
-        if (hclk_max > armclk)
-                hclk_max = armclk;
-
-        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
-                     __func__, fclk, armclk, hclk_max);
-        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
-                     __func__, cfg->freq.fclk, cfg->freq.armclk,
-                     cfg->freq.hclk, cfg->freq.pclk);
-
-        armdiv = fclk / armclk;
-
-        if (armdiv < 1)
-                armdiv = 1;
-        if (armdiv > 2)
-                armdiv = 2;
-
-        cfg->divs.arm_divisor = armdiv;
-        armdiv_clk = fclk / armdiv;
-
-        hdiv = armdiv_clk / hclk_max;
-        if (hdiv < 1)
-                hdiv = 1;
-
-        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
-
-        /* set dvs depending on whether we reached armclk or not. */
-        cfg->divs.dvs = dvs = armclk < armdiv_clk;
-
-        /* update the actual armclk we achieved. */
-        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
-
-        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
-                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
-
-        if (hdiv > 4)
-                goto invalid;
-
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-
-        if ((hclk / pdiv) > cfg->max.pclk)
-                pdiv++;
-
-        cfg->freq.pclk = hclk / pdiv;
-
-        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
-
-        if (pdiv > 2)
-                goto invalid;
-
-        pdiv *= hdiv;
-
-        /* store the result, and then return */
-
-        cfg->divs.h_divisor = hdiv * armdiv;
-        cfg->divs.p_divisor = pdiv * armdiv;
-
-        return 0;
-
-invalid:
-        return -EINVAL;
-}
-
-static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long clkdiv;
-        unsigned long olddiv;
-
-        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
-
-        /* clear off current clock info */
-
-        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
-        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
-        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
-
-        if (cfg->divs.arm_divisor == 2)
-                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
-
-        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
-
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2412_CLKDIVN_PDIVN;
-
-        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-
-        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
-}
-
-static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
-        struct s3c_cpufreq_board *board = cfg->board;
-        unsigned long refresh;
-
-        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
-                     board->refresh, cfg->freq.hclk);
-
-        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
-         * by 10 each to ensure that we do not overflow 32 bit numbers. This
-         * should work for HCLK up to 133MHz and refresh period up to 30usec.
-         */
-
-        refresh = (board->refresh / 10);
-        refresh *= (cfg->freq.hclk / 100);
-        refresh /= (1 * 1000 * 1000);   /* 10^6 */
-
-        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
-        __raw_writel(refresh, S3C2412_REFRESH);
-}
-
-/* set the default cpu frequency information, based on an 200MHz part
- * as we have no other way of detecting the speed rating in software.
- */
-
-static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
-        .max            = {
-                .fclk   = 200000000,
-                .hclk   = 100000000,
-                .pclk   =  50000000,
-        },
-
-        .latency        = 5000000, /* 5ms */
-
-        .locktime_m     = 150,
-        .locktime_u     = 150,
-        .locktime_bits  = 16,
-
-        .name           = "s3c2412",
-        .set_refresh    = s3c2412_cpufreq_setrefresh,
-        .set_divs       = s3c2412_cpufreq_setdivs,
-        .calc_divs      = s3c2412_cpufreq_calcdivs,
-
-        .calc_iotiming  = s3c2412_iotiming_calc,
-        .set_iotiming   = s3c2412_iotiming_set,
-        .get_iotiming   = s3c2412_iotiming_get,
-
-        .resume_clocks  = s3c2412_setup_clocks,
-
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
-};
-
-static int s3c2412_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        unsigned long fclk_rate;
-
-        hclk = clk_get(NULL, "hclk");
-        if (IS_ERR(hclk)) {
-                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
-                return -ENOENT;
-        }
-
-        fclk = clk_get(NULL, "fclk");
-        if (IS_ERR(fclk)) {
-                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
-                goto err_fclk;
-        }
-
-        fclk_rate = clk_get_rate(fclk);
-        if (fclk_rate > 200000000) {
-                printk(KERN_INFO
-                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
-                       __func__, fclk_rate / 1000000);
-                s3c2412_cpufreq_info.max.fclk = 266000000;
-                s3c2412_cpufreq_info.max.hclk = 133000000;
-                s3c2412_cpufreq_info.max.pclk =  66000000;
-        }
-
-        armclk = clk_get(NULL, "armclk");
-        if (IS_ERR(armclk)) {
-                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
-                goto err_armclk;
-        }
-
-        xtal = clk_get(NULL, "xtal");
-        if (IS_ERR(xtal)) {
-                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
-                goto err_xtal;
-        }
-
-        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
-
-err_xtal:
-        clk_put(armclk);
-err_armclk:
-        clk_put(fclk);
-err_fclk:
-        clk_put(hclk);
-
-        return -ENOENT;
-}
-
-static struct subsys_interface s3c2412_cpufreq_interface = {
-        .name           = "s3c2412_cpufreq",
-        .subsys         = &s3c2412_subsys,
-        .add_dev        = s3c2412_cpufreq_add,
-};
-
-static int s3c2412_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2412_cpufreq_interface);
-}
-arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c b/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
deleted file mode 100644
index 72b2cc8a5a85..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq-s3c2440.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * Copyright (c) 2006-2009 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *      Vincent Sanders <vince@simtec.co.uk>
- *
- * S3C2440/S3C2442 CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/cpu-freq-core.h>
-#include <plat/clock.h>
-
-static struct clk *xtal;
-static struct clk *fclk;
-static struct clk *hclk;
-static struct clk *armclk;
-
-/* HDIV: 1, 2, 3, 4, 6, 8 */
-
-static inline int within_khz(unsigned long a, unsigned long b)
-{
-        long diff = a - b;
-
-        return (diff >= -1000 && diff <= 1000);
-}
-
-/**
- * s3c2440_cpufreq_calcdivs - calculate divider settings
- * @cfg: The cpu frequency settings.
- *
- * Calcualte the divider values for the given frequency settings
- * specified in @cfg. The values are stored in @cfg for later use
- * by the relevant set routine if the request settings can be reached.
- */
-int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned int hdiv, pdiv;
-        unsigned long hclk, fclk, armclk;
-        unsigned long hclk_max;
-
-        fclk = cfg->freq.fclk;
-        armclk = cfg->freq.armclk;
-        hclk_max = cfg->max.hclk;
-
-        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
-                     __func__, fclk, armclk, hclk_max);
-
-        if (armclk > fclk) {
-                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
-                armclk = fclk;
-        }
-
-        /* if we are in DVS, we need HCLK to be <= ARMCLK */
-        if (armclk < fclk && armclk < hclk_max)
-                hclk_max = armclk;
-
-        for (hdiv = 1; hdiv < 9; hdiv++) {
-                if (hdiv == 5 || hdiv == 7)
-                        hdiv++;
-
-                hclk = (fclk / hdiv);
-                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
-                        break;
-        }
-
-        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
-
-        if (hdiv > 8)
-                goto invalid;
-
-        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
-
-        if ((hclk / pdiv) > cfg->max.pclk)
-                pdiv++;
-
-        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
-
-        if (pdiv > 2)
-                goto invalid;
-
-        pdiv *= hdiv;
-
-        /* calculate a valid armclk */
-
-        if (armclk < hclk)
-                armclk = hclk;
-
-        /* if we're running armclk lower than fclk, this really means
-         * that the system should go into dvs mode, which means that
-         * armclk is connected to hclk. */
-        if (armclk < fclk) {
-                cfg->divs.dvs = 1;
-                armclk = hclk;
-        } else
-                cfg->divs.dvs = 0;
-
-        cfg->freq.armclk = armclk;
-
-        /* store the result, and then return */
-
-        cfg->divs.h_divisor = hdiv;
-        cfg->divs.p_divisor = pdiv;
-
-        return 0;
-
- invalid:
-        return -EINVAL;
-}
-
-#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
-                           S3C2440_CAMDIVN_HCLK4_HALF)
-
-/**
- * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
- * @cfg: The cpu frequency settings.
- *
- * Set the divisors from the settings in @cfg, which where generated
- * during the calculation phase by s3c2440_cpufreq_calcdivs().
- */
-static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long clkdiv, camdiv;
-
-        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
-                     cfg->divs.h_divisor, cfg->divs.p_divisor);
-
-        clkdiv = __raw_readl(S3C2410_CLKDIVN);
-        camdiv = __raw_readl(S3C2440_CAMDIVN);
-
-        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
-        camdiv &= ~CAMDIVN_HCLK_HALF;
-
-        switch (cfg->divs.h_divisor) {
-        case 1:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
-                break;
-
-        case 2:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
-                break;
-
-        case 6:
-                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
-        case 3:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
-                break;
-
-        case 8:
-                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
-        case 4:
-                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
-                break;
-
-        default:
-                BUG();  /* we don't expect to get here. */
-        }
-
-        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
-                clkdiv |= S3C2440_CLKDIVN_PDIVN;
-
-        /* todo - set pclk. */
-
-        /* Write the divisors first with hclk intentionally halved so that
-         * when we write clkdiv we will under-frequency instead of over. We
-         * then make a short delay and remove the hclk halving if necessary.
-         */
-
-        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-
-        ndelay(20);
-        __raw_writel(camdiv, S3C2440_CAMDIVN);
-
-        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
-}
-
-static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
-                        int *divs,
-                        struct cpufreq_frequency_table *table,
-                        size_t table_size)
-{
-        unsigned long freq;
-        int index = 0;
-        int div;
-
-        for (div = *divs; div > 0; div = *divs++) {
-                freq = fclk / div;
-
-                if (freq > max_hclk && div != 1)
-                        continue;
-
-                freq /= 1000; /* table is in kHz */
-                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
-                if (index < 0)
-                        break;
-        }
-
-        return index;
-}
-
-static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
-
-static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
-                                     struct cpufreq_frequency_table *table,
-                                     size_t table_size)
-{
-        int ret;
-
-        WARN_ON(cfg->info == NULL);
-        WARN_ON(cfg->board == NULL);
-
-        ret = run_freq_for(cfg->info->max.hclk,
-                           cfg->info->max.fclk,
-                           hclk_divs,
-                           table, table_size);
-
-        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
-
-        return ret;
-}
-
-struct s3c_cpufreq_info s3c2440_cpufreq_info = {
-        .max            = {
-                .fclk   = 400000000,
-                .hclk   = 133333333,
-                .pclk   =  66666666,
-        },
-
-        .locktime_m     = 300,
-        .locktime_u     = 300,
-        .locktime_bits  = 16,
-
-        .name           = "s3c244x",
-        .calc_iotiming  = s3c2410_iotiming_calc,
-        .set_iotiming   = s3c2410_iotiming_set,
-        .get_iotiming   = s3c2410_iotiming_get,
-        .set_fvco       = s3c2410_set_fvco,
-
-        .set_refresh    = s3c2410_cpufreq_setrefresh,
-        .set_divs       = s3c2440_cpufreq_setdivs,
-        .calc_divs      = s3c2440_cpufreq_calcdivs,
-        .calc_freqtable = s3c2440_cpufreq_calctable,
-
-        .resume_clocks  = s3c244x_setup_clocks,
-
-        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
-};
-
-static int s3c2440_cpufreq_add(struct device *dev,
-                               struct subsys_interface *sif)
-{
-        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
-        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
-        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
-        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
-
-        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
-                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
-                return -ENOENT;
-        }
-
-        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
-}
-
-static struct subsys_interface s3c2440_cpufreq_interface = {
-        .name           = "s3c2440_cpufreq",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_cpufreq_add,
-};
-
-static int s3c2440_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2440_cpufreq_interface);
-}
-
-/* arch_initcall adds the clocks we need, so use subsys_initcall. */
-subsys_initcall(s3c2440_cpufreq_init);
-
-static struct subsys_interface s3c2442_cpufreq_interface = {
-        .name           = "s3c2442_cpufreq",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c2440_cpufreq_add,
-};
-
-static int s3c2442_cpufreq_init(void)
-{
-        return subsys_interface_register(&s3c2442_cpufreq_interface);
-}
-subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index ddd8280e3875..2a0aa5684e72 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -60,5 +60,5 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
  */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+        __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
 }
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
deleted file mode 100644
index 3c0e78ede0da..000000000000
--- a/arch/arm/mach-s3c24xx/cpufreq.c
+++ /dev/null
@@ -1,711 +0,0 @@
-/*
- * Copyright (c) 2006-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24XX CPU Frequency scaling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/cpufreq.h>
-#include <linux/cpu.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/sysfs.h>
-#include <linux/slab.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/cpu-freq-core.h>
-
-#include <mach/regs-clock.h>
-
-/* note, cpufreq support deals in kHz, no Hz */
-
-static struct cpufreq_driver s3c24xx_driver;
-static struct s3c_cpufreq_config cpu_cur;
-static struct s3c_iotimings s3c24xx_iotiming;
-static struct cpufreq_frequency_table *pll_reg;
-static unsigned int last_target = ~0;
-static unsigned int ftab_size;
-static struct cpufreq_frequency_table *ftab;
-
-static struct clk *_clk_mpll;
-static struct clk *_clk_xtal;
-static struct clk *clk_fclk;
-static struct clk *clk_hclk;
-static struct clk *clk_pclk;
-static struct clk *clk_arm;
-
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
-struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
-{
-        return &cpu_cur;
-}
-
-struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
-{
-        return &s3c24xx_iotiming;
-}
-#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
-
-static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long fclk, pclk, hclk, armclk;
-
-        cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
-        cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
-        cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
-        cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
-
-        cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
-        cfg->pll.frequency = fclk;
-
-        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
-
-        cfg->divs.h_divisor = fclk / hclk;
-        cfg->divs.p_divisor = fclk / pclk;
-}
-
-static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
-{
-        unsigned long pll = cfg->pll.frequency;
-
-        cfg->freq.fclk = pll;
-        cfg->freq.hclk = pll / cfg->divs.h_divisor;
-        cfg->freq.pclk = pll / cfg->divs.p_divisor;
-
-        /* convert hclk into 10ths of nanoseconds for io calcs */
-        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
-}
-
-static inline int closer(unsigned int target, unsigned int n, unsigned int c)
-{
-        int diff_cur = abs(target - c);
-        int diff_new = abs(target - n);
-
-        return (diff_new < diff_cur);
-}
-
-static void s3c_cpufreq_show(const char *pfx,
-                                 struct s3c_cpufreq_config *cfg)
-{
-        s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
-                     pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
-                     cfg->freq.hclk, cfg->divs.h_divisor,
-                     cfg->freq.pclk, cfg->divs.p_divisor);
-}
-
-/* functions to wrapper the driver info calls to do the cpu specific work */
-
-static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
-{
-        if (cfg->info->set_iotiming)
-                (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
-}
-
-static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
-{
-        if (cfg->info->calc_iotiming)
-                return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
-
-        return 0;
-}
-
-static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_refresh)(cfg);
-}
-
-static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_divs)(cfg);
-}
-
-static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
-{
-        return (cfg->info->calc_divs)(cfg);
-}
-
-static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
-{
-        (cfg->info->set_fvco)(cfg);
-}
-
-static inline void s3c_cpufreq_resume_clocks(void)
-{
-        cpu_cur.info->resume_clocks();
-}
-
-static inline void s3c_cpufreq_updateclk(struct clk *clk,
-                                         unsigned int freq)
-{
-        clk_set_rate(clk, freq);
-}
-
-static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
-                                 unsigned int target_freq,
-                                 struct cpufreq_frequency_table *pll)
-{
-        struct s3c_cpufreq_freqs freqs;
-        struct s3c_cpufreq_config cpu_new;
-        unsigned long flags;
-
-        cpu_new = cpu_cur;  /* copy new from current */
-
-        s3c_cpufreq_show("cur", &cpu_cur);
-
-        /* TODO - check for DMA currently outstanding */
-
-        cpu_new.pll = pll ? *pll : cpu_cur.pll;
-
-        if (pll)
-                freqs.pll_changing = 1;
-
-        /* update our frequencies */
-
-        cpu_new.freq.armclk = target_freq;
-        cpu_new.freq.fclk = cpu_new.pll.frequency;
-
-        if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
-                printk(KERN_ERR "no divisors for %d\n", target_freq);
-                goto err_notpossible;
-        }
-
-        s3c_freq_dbg("%s: got divs\n", __func__);
-
-        s3c_cpufreq_calc(&cpu_new);
-
-        s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
-
-        if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
-                if (s3c_cpufreq_calcio(&cpu_new) < 0) {
-                        printk(KERN_ERR "%s: no IO timings\n", __func__);
-                        goto err_notpossible;
-                }
-        }
-
-        s3c_cpufreq_show("new", &cpu_new);
-
-        /* setup our cpufreq parameters */
-
-        freqs.old = cpu_cur.freq;
-        freqs.new = cpu_new.freq;
-
-        freqs.freqs.old = cpu_cur.freq.armclk / 1000;
-        freqs.freqs.new = cpu_new.freq.armclk / 1000;
-
-        /* update f/h/p clock settings before we issue the change
-         * notification, so that drivers do not need to do anything
-         * special if they want to recalculate on CPUFREQ_PRECHANGE. */
-
-        s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
-        s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
-        s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
-        s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
-
-        /* start the frequency change */
-        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_PRECHANGE);
-
-        /* If hclk is staying the same, then we do not need to
-         * re-write the IO or the refresh timings whilst we are changing
-         * speed. */
-
-        local_irq_save(flags);
-
-        /* is our memory clock slowing down? */
-        if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
-                s3c_cpufreq_setrefresh(&cpu_new);
-                s3c_cpufreq_setio(&cpu_new);
-        }
-
-        if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
-                /* not changing PLL, just set the divisors */
-
-                s3c_cpufreq_setdivs(&cpu_new);
-        } else {
-                if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
-                        /* slow the cpu down, then set divisors */
-
-                        s3c_cpufreq_setfvco(&cpu_new);
-                        s3c_cpufreq_setdivs(&cpu_new);
-                } else {
-                        /* set the divisors, then speed up */
-
-                        s3c_cpufreq_setdivs(&cpu_new);
-                        s3c_cpufreq_setfvco(&cpu_new);
-                }
-        }
-
-        /* did our memory clock speed up */
-        if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
-                s3c_cpufreq_setrefresh(&cpu_new);
-                s3c_cpufreq_setio(&cpu_new);
-        }
-
-        /* update our current settings */
-        cpu_cur = cpu_new;
-
-        local_irq_restore(flags);
-
-        /* notify everyone we've done this */
-        cpufreq_notify_transition(policy, &freqs.freqs, CPUFREQ_POSTCHANGE);
-
-        s3c_freq_dbg("%s: finished\n", __func__);
-        return 0;
-
- err_notpossible:
-        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
-        return -EINVAL;
-}
-
-/* s3c_cpufreq_target
- *
- * called by the cpufreq core to adjust the frequency that the CPU
- * is currently running at.
- */
-
-static int s3c_cpufreq_target(struct cpufreq_policy *policy,
-                              unsigned int target_freq,
-                              unsigned int relation)
-{
-        struct cpufreq_frequency_table *pll;
-        unsigned int index;
-
-        /* avoid repeated calls which cause a needless amout of duplicated
-         * logging output (and CPU time as the calculation process is
-         * done) */
-        if (target_freq == last_target)
-                return 0;
-
-        last_target = target_freq;
-
-        s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
-                     __func__, policy, target_freq, relation);
-
-        if (ftab) {
-                if (cpufreq_frequency_table_target(policy, ftab,
-                                                   target_freq, relation,
-                                                   &index)) {
-                        s3c_freq_dbg("%s: table failed\n", __func__);
-                        return -EINVAL;
-                }
-
-                s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
-                             target_freq, index, ftab[index].frequency);
-                target_freq = ftab[index].frequency;
-        }
-
-        target_freq *= 1000;  /* convert target to Hz */
-
-        /* find the settings for our new frequency */
-
-        if (!pll_reg || cpu_cur.lock_pll) {
-                /* either we've not got any PLL values, or we've locked
-                 * to the current one. */
-                pll = NULL;
-        } else {
-                struct cpufreq_policy tmp_policy;
-                int ret;
-
-                /* we keep the cpu pll table in Hz, to ensure we get an
-                 * accurate value for the PLL output. */
-
-                tmp_policy.min = policy->min * 1000;
-                tmp_policy.max = policy->max * 1000;
-                tmp_policy.cpu = policy->cpu;
-
-                /* cpufreq_frequency_table_target uses a pointer to 'index'
-                 * which is the number of the table entry, not the value of
-                 * the table entry's index field. */
-
-                ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
-                                                     target_freq, relation,
-                                                     &index);
-
-                if (ret < 0) {
-                        printk(KERN_ERR "%s: no PLL available\n", __func__);
-                        goto err_notpossible;
-                }
-
-                pll = pll_reg + index;
-
-                s3c_freq_dbg("%s: target %u => %u\n",
-                             __func__, target_freq, pll->frequency);
-
-                target_freq = pll->frequency;
-        }
-
-        return s3c_cpufreq_settarget(policy, target_freq, pll);
-
- err_notpossible:
-        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
-        return -EINVAL;
-}
-
-static unsigned int s3c_cpufreq_get(unsigned int cpu)
-{
-        return clk_get_rate(clk_arm) / 1000;
-}
-
-struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
-{
-        struct clk *clk;
-
-        clk = clk_get(dev, name);
-        if (IS_ERR(clk))
-                printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
-
-        return clk;
-}
-
-static int s3c_cpufreq_init(struct cpufreq_policy *policy)
-{
-        printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        policy->cur = s3c_cpufreq_get(0);
-        policy->min = policy->cpuinfo.min_freq = 0;
-        policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
-        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-
-        /* feed the latency information from the cpu driver */
-        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
-
-        if (ftab)
-                cpufreq_frequency_table_cpuinfo(policy, ftab);
-
-        return 0;
-}
-
-static __init int s3c_cpufreq_initclks(void)
-{
-        _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
-        _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
-        clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
-        clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
-        clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
-        clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
-
-        if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
-            IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
-                printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
-                return -ENOENT;
-        }
-
-        printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
-               clk_get_rate(clk_fclk) / 1000,
-               clk_get_rate(clk_hclk) / 1000,
-               clk_get_rate(clk_pclk) / 1000,
-               clk_get_rate(clk_arm) / 1000);
-
-        return 0;
-}
-
-static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        return 0;
-}
-
-#ifdef CONFIG_PM
-static struct cpufreq_frequency_table suspend_pll;
-static unsigned int suspend_freq;
-
-static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
-{
-        suspend_pll.frequency = clk_get_rate(_clk_mpll);
-        suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
-        suspend_freq = s3c_cpufreq_get(0) * 1000;
-
-        return 0;
-}
-
-static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
-{
-        int ret;
-
-        s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
-
-        last_target = ~0;       /* invalidate last_target setting */
-
-        /* first, find out what speed we resumed at. */
-        s3c_cpufreq_resume_clocks();
-
-        /* whilst we will be called later on, we try and re-set the
-         * cpu frequencies as soon as possible so that we do not end
-         * up resuming devices and then immediately having to re-set
-         * a number of settings once these devices have restarted.
-         *
-         * as a note, it is expected devices are not used until they
-         * have been un-suspended and at that time they should have
-         * used the updated clock settings.
-         */
-
-        ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
-        if (ret) {
-                printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
-                return ret;
-        }
-
-        return 0;
-}
-#else
-#define s3c_cpufreq_resume NULL
-#define s3c_cpufreq_suspend NULL
-#endif
-
-static struct cpufreq_driver s3c24xx_driver = {
-        .flags          = CPUFREQ_STICKY,
-        .verify         = s3c_cpufreq_verify,
-        .target         = s3c_cpufreq_target,
-        .get            = s3c_cpufreq_get,
-        .init           = s3c_cpufreq_init,
-        .suspend        = s3c_cpufreq_suspend,
-        .resume         = s3c_cpufreq_resume,
-        .name           = "s3c24xx",
-};
-
-
-int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
-{
-        if (!info || !info->name) {
-                printk(KERN_ERR "%s: failed to pass valid information\n",
-                       __func__);
-                return -EINVAL;
-        }
-
-        printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
-               info->name);
-
-        /* check our driver info has valid data */
-
-        BUG_ON(info->set_refresh == NULL);
-        BUG_ON(info->set_divs == NULL);
-        BUG_ON(info->calc_divs == NULL);
-
-        /* info->set_fvco is optional, depending on whether there
-         * is a need to set the clock code. */
-
-        cpu_cur.info = info;
-
-        /* Note, driver registering should probably update locktime */
-
-        return 0;
-}
-
-int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
-{
-        struct s3c_cpufreq_board *ours;
-
-        if (!board) {
-                printk(KERN_INFO "%s: no board data\n", __func__);
-                return -EINVAL;
-        }
-
-        /* Copy the board information so that each board can make this
-         * initdata. */
-
-        ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
-        if (ours == NULL) {
-                printk(KERN_ERR "%s: no memory\n", __func__);
-                return -ENOMEM;
-        }
-
-        *ours = *board;
-        cpu_cur.board = ours;
-
-        return 0;
-}
-
-int __init s3c_cpufreq_auto_io(void)
-{
-        int ret;
-
-        if (!cpu_cur.info->get_iotiming) {
-                printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
-                return -ENOENT;
-        }
-
-        printk(KERN_INFO "%s: working out IO settings\n", __func__);
-
-        ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
-        if (ret)
-                printk(KERN_ERR "%s: failed to get timings\n", __func__);
-
-        return ret;
-}
-
-/* if one or is zero, then return the other, otherwise return the min */
-#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
-
-/**
- * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
- * @dst: The destination structure
- * @a: One argument.
- * @b: The other argument.
- *
- * Create a minimum of each frequency entry in the 'struct s3c_freq',
- * unless the entry is zero when it is ignored and the non-zero argument
- * used.
- */
-static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
-                                 struct s3c_freq *a, struct s3c_freq *b)
-{
-        dst->fclk = do_min(a->fclk, b->fclk);
-        dst->hclk = do_min(a->hclk, b->hclk);
-        dst->pclk = do_min(a->pclk, b->pclk);
-        dst->armclk = do_min(a->armclk, b->armclk);
-}
-
-static inline u32 calc_locktime(u32 freq, u32 time_us)
-{
-        u32 result;
-
-        result = freq * time_us;
-        result = DIV_ROUND_UP(result, 1000 * 1000);
-
-        return result;
-}
-
-static void s3c_cpufreq_update_loctkime(void)
-{
-        unsigned int bits = cpu_cur.info->locktime_bits;
-        u32 rate = (u32)clk_get_rate(_clk_xtal);
-        u32 val;
-
-        if (bits == 0) {
-                WARN_ON(1);
-                return;
-        }
-
-        val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
-        val |= calc_locktime(rate, cpu_cur.info->locktime_m);
-
-        printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
-        __raw_writel(val, S3C2410_LOCKTIME);
-}
-
-static int s3c_cpufreq_build_freq(void)
-{
-        int size, ret;
-
-        if (!cpu_cur.info->calc_freqtable)
-                return -EINVAL;
-
-        kfree(ftab);
-        ftab = NULL;
-
-        size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
-        size++;
-
-        ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
-        if (!ftab) {
-                printk(KERN_ERR "%s: no memory for tables\n", __func__);
-                return -ENOMEM;
-        }
-
-        ftab_size = size;
-
-        ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
-        s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
-
-        return 0;
-}
-
-static int __init s3c_cpufreq_initcall(void)
-{
-        int ret = 0;
-
-        if (cpu_cur.info && cpu_cur.board) {
-                ret = s3c_cpufreq_initclks();
-                if (ret)
-                        goto out;
-
-                /* get current settings */
-                s3c_cpufreq_getcur(&cpu_cur);
-                s3c_cpufreq_show("cur", &cpu_cur);
-
-                if (cpu_cur.board->auto_io) {
-                        ret = s3c_cpufreq_auto_io();
-                        if (ret) {
-                                printk(KERN_ERR "%s: failed to get io timing\n",
-                                       __func__);
-                                goto out;
-                        }
-                }
-
-                if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
-                        printk(KERN_ERR "%s: no IO support registered\n",
-                               __func__);
-                        ret = -EINVAL;
-                        goto out;
-                }
-
-                if (!cpu_cur.info->need_pll)
-                        cpu_cur.lock_pll = 1;
-
-                s3c_cpufreq_update_loctkime();
-
-                s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
-                                     &cpu_cur.info->max);
-
-                if (cpu_cur.info->calc_freqtable)
-                        s3c_cpufreq_build_freq();
-
-                ret = cpufreq_register_driver(&s3c24xx_driver);
-        }
-
- out:
-        return ret;
-}
-
-late_initcall(s3c_cpufreq_initcall);
-
-/**
- * s3c_plltab_register - register CPU PLL table.
- * @plls: The list of PLL entries.
- * @plls_no: The size of the PLL entries @plls.
- *
- * Register the given set of PLLs with the system.
- */
-int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
-                               unsigned int plls_no)
-{
-        struct cpufreq_frequency_table *vals;
-        unsigned int size;
-
-        size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
-
-        vals = kmalloc(size, GFP_KERNEL);
-        if (vals) {
-                memcpy(vals, plls, size);
-                pll_reg = vals;
-
-                /* write a terminating entry, we don't store it in the
-                 * table that is stored in the kernel */
-                vals += plls_no;
-                vals->frequency = CPUFREQ_TABLE_END;
-
-                printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
-        } else
-                printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
-
-        return vals ? 0 : -ENOMEM;
-}
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index ab1700ec8e64..b7e094671522 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -35,121 +35,95 @@ static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
         [DMACH_XD0] = {
                 .name           = "xdreq0",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ0),
         },
         [DMACH_XD1] = {
                 .name           = "xdreq1",
                 .channels       = MAP(S3C2412_DMAREQSEL_XDREQ1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_XDREQ1),
         },
         [DMACH_SDI] = {
                 .name           = "sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_SDI),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SDI),
         },
-        [DMACH_SPI0] = {
-                .name           = "spi0",
+        [DMACH_SPI0_RX] = {
+                .name           = "spi0-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI0RX),
+        },
+        [DMACH_SPI0_TX] = {
+                .name           = "spi0-tx",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI0TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI0RX),
         },
-        [DMACH_SPI1] = {
-                .name           = "spi1",
+        [DMACH_SPI1_RX] = {
+                .name           = "spi1-rx",
+                .channels       = MAP(S3C2412_DMAREQSEL_SPI1RX),
+        },
+        [DMACH_SPI1_TX] = {
+                .name           = "spi1-tx",
                 .channels       = MAP(S3C2412_DMAREQSEL_SPI1TX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_SPI1RX),
         },
         [DMACH_UART0] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_0),
         },
         [DMACH_UART1] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_0),
         },
         [DMACH_UART2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_0),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_0),
         },
         [DMACH_UART0_SRC2] = {
                 .name           = "uart0",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART0_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART0_1),
         },
         [DMACH_UART1_SRC2] = {
                 .name           = "uart1",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART1_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART1_1),
         },
         [DMACH_UART2_SRC2] = {
                 .name           = "uart2",
                 .channels       = MAP(S3C2412_DMAREQSEL_UART2_1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_UART2_1),
         },
         [DMACH_TIMER] = {
                 .name           = "timer",
                 .channels       = MAP(S3C2412_DMAREQSEL_TIMER),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_TIMER),
         },
         [DMACH_I2S_IN] = {
                 .name           = "i2s-sdi",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2SRX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2SRX),
         },
         [DMACH_I2S_OUT] = {
                 .name           = "i2s-sdo",
                 .channels       = MAP(S3C2412_DMAREQSEL_I2STX),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_I2STX),
         },
         [DMACH_USB_EP1] = {
                 .name           = "usb-ep1",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP1),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP1),
         },
         [DMACH_USB_EP2] = {
                 .name           = "usb-ep2",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP2),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP2),
         },
         [DMACH_USB_EP3] = {
                 .name           = "usb-ep3",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP3),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP3),
         },
         [DMACH_USB_EP4] = {
                 .name           = "usb-ep4",
                 .channels       = MAP(S3C2412_DMAREQSEL_USBEP4),
-                .channels_rx    = MAP(S3C2412_DMAREQSEL_USBEP4),
         },
 };
 
-static void s3c2412_dma_direction(struct s3c2410_dma_chan *chan,
-                                  struct s3c24xx_dma_map *map,
-                                  enum dma_data_direction dir)
-{
-        unsigned long chsel;
-
-        if (dir == DMA_FROM_DEVICE)
-                chsel = map->channels_rx[0];
-        else
-                chsel = map->channels[0];
-
-        chsel &= ~DMA_CH_VALID;
-        chsel |= S3C2412_DMAREQSEL_HW;
-
-        writel(chsel, chan->regs + S3C2412_DMA_DMAREQSEL);
-}
-
 static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
                                struct s3c24xx_dma_map *map)
 {
-        s3c2412_dma_direction(chan, map, chan->source);
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2412_DMAREQSEL_HW,
+               chan->regs + S3C2412_DMA_DMAREQSEL);
 }
 
 static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
         .select         = s3c2412_dma_select,
-        .direction      = s3c2412_dma_direction,
         .dcon_mask      = 0,
         .map            = s3c2412_dma_mappings,
         .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 5fe3539dc2b5..95b9f759fe97 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -128,7 +128,8 @@ static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
 static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
                                struct s3c24xx_dma_map *map)
 {
-        writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
+        unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
+        writel(chsel | S3C2443_DMAREQSEL_HW,
                chan->regs + S3C2443_DMA_DMAREQSEL);
 }
 
diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c
index aab64909e9a3..4a65cba3295d 100644
--- a/arch/arm/mach-s3c24xx/dma.c
+++ b/arch/arm/mach-s3c24xx/dma.c
@@ -1159,9 +1159,6 @@ int s3c2410_dma_devconfig(enum dma_ch channel,
                 return -EINVAL;
         }
 
-        if (dma_sel.direction != NULL)
-                (dma_sel.direction)(chan, chan->map, source);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.h b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
index 548ced42cbb7..548ced42cbb7 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.h
+++ b/arch/arm/mach-s3c24xx/include/mach/s3c2412.h
diff --git a/arch/arm/mach-s3c24xx/include/mach/uncompress.h b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
index 8b283f847daa..7d2ce205dce8 100644
--- a/arch/arm/mach-s3c24xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c24xx/include/mach/uncompress.h
@@ -49,6 +49,9 @@ static void arch_detect_cpu(void)
                 fifo_mask = S3C2410_UFSTAT_TXMASK;
                 fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
         }
+
+        uart_base = (volatile u8 *) S3C_PA_UART +
+                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
index 663436d9db01..bd064c05c473 100644
--- a/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/iotiming-s3c2412.c
@@ -31,7 +31,7 @@
 #include <plat/cpu-freq-core.h>
 #include <plat/clock.h>
 
-#include "s3c2412.h"
+#include <mach/s3c2412.h>
 
 #define print_ns(x) ((x) / 10), ((x) % 10)
 
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
new file mode 100644
index 000000000000..f50454a34f72
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -0,0 +1,91 @@
+/*
+ * Samsung's S3C2416 flattened device tree enabled machine
+ *
+ * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
+ *
+ * based on mach-exynos/mach-exynos4-dt.c
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <mach/map.h>
+
+#include <plat/cpu.h>
+#include <plat/pm.h>
+#include <plat/regs-serial.h>
+
+#include "common.h"
+
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the S3C2416 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
+                                "s3c2440-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
+                                "s3c2440-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
+                                "s3c2440-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
+                                "s3c2440-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
+                                "s3c-sdhci.0", NULL),
+        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
+                                "s3c-sdhci.1", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
+                                "s3c2440-i2c.0", NULL),
+        {},
+};
+
+static void __init s3c2416_dt_map_io(void)
+{
+        s3c24xx_init_io(NULL, 0);
+        s3c24xx_init_clocks(12000000);
+}
+
+static void __init s3c2416_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                s3c2416_auxdata_lookup, NULL);
+
+        s3c_pm_init();
+}
+
+static char const *s3c2416_dt_compat[] __initdata = {
+        "samsung,s3c2416",
+        "samsung,s3c2450",
+        NULL
+};
+
+DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
+        /* Maintainer: Heiko Stuebner <heiko@sntech.de> */
+        .dt_compat      = s3c2416_dt_compat,
+        .map_io         = s3c2416_dt_map_io,
+        .init_irq       = irqchip_init,
+        .init_machine   = s3c2416_dt_machine_init,
+         .init_time     = clocksource_of_init,
+        .restart        = s3c2416_restart,
+MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index dcf3420a3271..5e37d368594b 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -33,36 +33,36 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table pll_vals_12MHz[] = {
-    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
-    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
-    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
-    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
-    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
-    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
-    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
-    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
-    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
-    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
-    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
-    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
-    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
-    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
-    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
-    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
-    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
-    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
-    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
-    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
-    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
-    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+    { .frequency = 34000000,  .driver_data = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .driver_data = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .driver_data = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .driver_data = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .driver_data = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .driver_data = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .driver_data = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .driver_data = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .driver_data = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1),  },
 
     /* 2410A extras */
 
-    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
-    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
-    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
-    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
-    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+    { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1),  },
 };
 
 static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 673781758319..a19460e6e7b0 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -21,33 +21,33 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
-        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
-        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
-        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
-        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
-        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
-        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
-        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
-        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
-        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
-        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
-        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
-        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
-        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
-        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
-        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
-        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
-        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
-        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
-        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
-        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
-        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
-        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
-        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
-        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
-        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
-        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
-        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+        { .frequency = 75000000,        .driver_data = PLLVAL(0x75, 3, 3),  },  /* FVco 600.000000 */
+        { .frequency = 80000000,        .driver_data = PLLVAL(0x98, 4, 3),  },  /* FVco 640.000000 */
+        { .frequency = 90000000,        .driver_data = PLLVAL(0x70, 2, 3),  },  /* FVco 720.000000 */
+        { .frequency = 100000000,       .driver_data = PLLVAL(0x5c, 1, 3),  },  /* FVco 800.000000 */
+        { .frequency = 110000000,       .driver_data = PLLVAL(0x66, 1, 3),  },  /* FVco 880.000000 */
+        { .frequency = 120000000,       .driver_data = PLLVAL(0x70, 1, 3),  },  /* FVco 960.000000 */
+        { .frequency = 150000000,       .driver_data = PLLVAL(0x75, 3, 2),  },  /* FVco 600.000000 */
+        { .frequency = 160000000,       .driver_data = PLLVAL(0x98, 4, 2),  },  /* FVco 640.000000 */
+        { .frequency = 170000000,       .driver_data = PLLVAL(0x4d, 1, 2),  },  /* FVco 680.000000 */
+        { .frequency = 180000000,       .driver_data = PLLVAL(0x70, 2, 2),  },  /* FVco 720.000000 */
+        { .frequency = 190000000,       .driver_data = PLLVAL(0x57, 1, 2),  },  /* FVco 760.000000 */
+        { .frequency = 200000000,       .driver_data = PLLVAL(0x5c, 1, 2),  },  /* FVco 800.000000 */
+        { .frequency = 210000000,       .driver_data = PLLVAL(0x84, 2, 2),  },  /* FVco 840.000000 */
+        { .frequency = 220000000,       .driver_data = PLLVAL(0x66, 1, 2),  },  /* FVco 880.000000 */
+        { .frequency = 230000000,       .driver_data = PLLVAL(0x6b, 1, 2),  },  /* FVco 920.000000 */
+        { .frequency = 240000000,       .driver_data = PLLVAL(0x70, 1, 2),  },  /* FVco 960.000000 */
+        { .frequency = 300000000,       .driver_data = PLLVAL(0x75, 3, 1),  },  /* FVco 600.000000 */
+        { .frequency = 310000000,       .driver_data = PLLVAL(0x93, 4, 1),  },  /* FVco 620.000000 */
+        { .frequency = 320000000,       .driver_data = PLLVAL(0x98, 4, 1),  },  /* FVco 640.000000 */
+        { .frequency = 330000000,       .driver_data = PLLVAL(0x66, 2, 1),  },  /* FVco 660.000000 */
+        { .frequency = 340000000,       .driver_data = PLLVAL(0x4d, 1, 1),  },  /* FVco 680.000000 */
+        { .frequency = 350000000,       .driver_data = PLLVAL(0xa7, 4, 1),  },  /* FVco 700.000000 */
+        { .frequency = 360000000,       .driver_data = PLLVAL(0x70, 2, 1),  },  /* FVco 720.000000 */
+        { .frequency = 370000000,       .driver_data = PLLVAL(0xb1, 4, 1),  },  /* FVco 740.000000 */
+        { .frequency = 380000000,       .driver_data = PLLVAL(0x57, 1, 1),  },  /* FVco 760.000000 */
+        { .frequency = 390000000,       .driver_data = PLLVAL(0x7a, 2, 1),  },  /* FVco 780.000000 */
+        { .frequency = 400000000,       .driver_data = PLLVAL(0x5c, 1, 1),  },  /* FVco 800.000000 */
 };
 
 static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index debfa106289b..1191b2905625 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -21,61 +21,61 @@
 #include <plat/cpu-freq-core.h>
 
 static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
-        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
-        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
-        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
-        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
-        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
-        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
-        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
-        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
-        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
-        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
-        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
-        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
-        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
-        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
-        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
-        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
-        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
-        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
-        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
-        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
-        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
-        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
-        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
-        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
-        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
-        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
-        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
-        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
-        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
-        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
-        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
-        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
-        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
-        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
-        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
-        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
-        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
-        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
-        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
-        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
-        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
-        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
-        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
-        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
-        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
-        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
-        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
-        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
-        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
-        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
-        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
-        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
-        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
-        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
-        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+        { .frequency = 78019200,        .driver_data = PLLVAL(121, 5, 3),       },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .driver_data = PLLVAL(131, 5, 3),       },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .driver_data = PLLVAL(141, 5, 3),       },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .driver_data = PLLVAL(151, 5, 3),       },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .driver_data = PLLVAL(185, 6, 3),       },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .driver_data = PLLVAL(171, 5, 3),       },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .driver_data = PLLVAL(127, 3, 3),       },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .driver_data = PLLVAL(134, 3, 3),       },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .driver_data = PLLVAL(141, 3, 3),       },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .driver_data = PLLVAL(148, 3, 3),       },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .driver_data = PLLVAL(155, 3, 3),       },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .driver_data = PLLVAL(163, 3, 3),       },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .driver_data = PLLVAL(187, 9, 2),       },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .driver_data = PLLVAL(121, 5, 2),       },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .driver_data = PLLVAL(126, 5, 2),       },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .driver_data = PLLVAL(131, 5, 2),       },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .driver_data = PLLVAL(177, 7, 2),       },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .driver_data = PLLVAL(141, 5, 2),       },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .driver_data = PLLVAL(124, 4, 2),       },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .driver_data = PLLVAL(151, 5, 2),       },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .driver_data = PLLVAL(109, 3, 2),       },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .driver_data = PLLVAL(185, 6, 2),       },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .driver_data = PLLVAL(141, 4, 2),       },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .driver_data = PLLVAL(171, 5, 2),       },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .driver_data = PLLVAL(97, 2, 2),        },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .driver_data = PLLVAL(127, 3, 2),       },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .driver_data = PLLVAL(158, 4, 2),       },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .driver_data = PLLVAL(134, 3, 2),       },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .driver_data = PLLVAL(167, 4, 2),       },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .driver_data = PLLVAL(141, 3, 2),       },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .driver_data = PLLVAL(114, 2, 2),       },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .driver_data = PLLVAL(148, 3, 2),       },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .driver_data = PLLVAL(120, 2, 2),       },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .driver_data = PLLVAL(155, 3, 2),       },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .driver_data = PLLVAL(92, 1, 2),        },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .driver_data = PLLVAL(163, 3, 2),       },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .driver_data = PLLVAL(131, 2, 2),       },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .driver_data = PLLVAL(187, 9, 1),       },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .driver_data = PLLVAL(191, 9, 1),       },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .driver_data = PLLVAL(121, 5, 1),       },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .driver_data = PLLVAL(86, 3, 1),        },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .driver_data = PLLVAL(126, 5, 1),       },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .driver_data = PLLVAL(109, 4, 1),       },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .driver_data = PLLVAL(131, 5, 1),       },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .driver_data = PLLVAL(93, 3, 1),        },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .driver_data = PLLVAL(177, 7, 1),       },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .driver_data = PLLVAL(118, 4, 1),       },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .driver_data = PLLVAL(141, 5, 1),       },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .driver_data = PLLVAL(165, 6, 1),       },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .driver_data = PLLVAL(124, 4, 1),       },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .driver_data = PLLVAL(126, 4, 1),       },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .driver_data = PLLVAL(151, 5, 1),       },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .driver_data = PLLVAL(177, 6, 1),       },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .driver_data = PLLVAL(109, 3, 1),       },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .driver_data = PLLVAL(87, 2, 1),        },      /* FVco 804.384000 */
 };
 
 static int s3c2440_plls169344_add(struct device *dev,
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index d850ea5adac2..ff384acc65b2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -138,6 +138,7 @@ void __init s3c2410_init_clocks(int xtal)
         s3c2410_baseclk_add();
         s3c24xx_register_clock(&s3c2410_armclk);
         clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 struct bus_type s3c2410_subsys = {
@@ -201,7 +202,7 @@ void s3c2410_restart(char mode, const char *cmd)
                 soft_restart(0);
         }
 
-        arch_wdt_reset();
+        samsung_wdt_reset();
 
         /* we'll take a jump through zero as a poor second */
         soft_restart(0);
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 2a35edb67354..d0423e2544c1 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -133,6 +133,7 @@ void __init s3c244x_init_clocks(int xtal)
         s3c24xx_register_baseclocks(xtal);
         s3c244x_setup_clocks();
         s3c2410_baseclk_add();
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
@@ -202,7 +203,7 @@ void s3c244x_restart(char mode, const char *cmd)
         if (mode == 's')
                 soft_restart(0);
 
-        arch_wdt_reset();
+        samsung_wdt_reset();
 
         /* we'll take a jump through zero as a poor second */
         soft_restart(0);
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 0b9c0ba44834..1aed6f4be1ce 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -183,6 +183,12 @@ core_initcall(s3c64xx_dev_init);
 
 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 {
+        /*
+         * FIXME: there is no better place to put this at the moment
+         * (samsung_wdt_reset_init needs clocks)
+         */
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
         /* initialise the pair of VICs */
@@ -378,7 +384,7 @@ arch_initcall(s3c64xx_init_irq_eint);
 void s3c64xx_restart(char mode, const char *cmd)
 {
         if (mode != 's')
-                arch_wdt_reset();
+                samsung_wdt_reset();
 
         /* if all else fails, or mode was for soft, jump to 0 */
         soft_restart(0);
diff --git a/arch/arm/mach-s3c64xx/include/mach/uncompress.h b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
index c6a82a20bf2a..1c956738b42d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/uncompress.h
+++ b/arch/arm/mach-s3c64xx/include/mach/uncompress.h
@@ -23,6 +23,9 @@ static void arch_detect_cpu(void)
         /* we do not need to do any cpu detection here at the moment. */
         fifo_mask = S3C2440_UFSTAT_TXMASK;
         fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+
+        uart_base = (volatile u8 *)S3C_PA_UART +
+                (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index 8ae5800e807f..76d0053bf564 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -173,6 +173,8 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
         s5p_init_cpu(S5P64X0_SYS_ID);
 
         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
+
 }
 
 void __init s5p6440_map_io(void)
@@ -440,7 +442,7 @@ arch_initcall(s5p64x0_init_irq_eint);
 void s5p64x0_restart(char mode, const char *cmd)
 {
         if (mode != 's')
-                arch_wdt_reset();
+                samsung_wdt_reset();
 
         soft_restart(0);
 }
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index 19e0d64d78c5..bbcc3f669ee3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -14,171 +14,21 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <mach/map.h>
+#include <plat/uncompress.h>
 
-/*
- * cannot use commonly <plat/uncompress.h>
- * because uart base of S5P6440 and S5P6450 is different
- */
-
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-unsigned int fifo_mask;
-unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
-
-unsigned long uart_base;
-
-static __inline__ void get_uart_base(void)
+static void arch_detect_cpu(void)
 {
         unsigned int chipid;
 
         chipid = *(const volatile unsigned int __force *) 0xE0100118;
 
-        uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
-
         if ((chipid & 0xff000) == 0x50000)
-                uart_base += 0xEC800000;
+                uart_base = (volatile u8 *)S5P6450_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
         else
-                uart_base += 0xEC000000;
-}
-
-static __inline__ void uart_wr(unsigned int reg, unsigned int val)
-{
-        volatile unsigned int *ptr;
-
-        get_uart_base();
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-
-static __inline__ unsigned int uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-
-        get_uart_base();
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
-}
-
-/*
- * we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
- */
-
-static void putc(int ch)
-{
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        level &= fifo_mask;
-
-                        if (level < fifo_max)
-                                break;
-                }
-
-        } else {
-                /* not using fifos */
-
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
-        }
+                uart_base = (volatile u8 *)S5P6440_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d, ad)                     \
-        do {                                                    \
-                *((volatile unsigned int __force *)(ad)) = (d); \
-        } while (0)
-
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-        while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
-static inline void arch_enable_uart_fifo(void)
-{
-        u32 fifocon = uart_rd(S3C2410_UFCON);
-
-        if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
-                fifocon |= S3C2410_UFCON_RESETBOTH;
-                uart_wr(S3C2410_UFCON, fifocon);
-
-                /* wait for fifo reset to complete */
-                while (1) {
-                        fifocon = uart_rd(S3C2410_UFCON);
-                        if (!(fifocon & S3C2410_UFCON_RESETBOTH))
-                                break;
-                }
-        }
-}
-#else
-#define arch_enable_uart_fifo() do { } while(0)
-#endif
-
-static void arch_decomp_setup(void)
-{
-        /*
-         * we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-
-        arch_detect_cpu();
-
-        /*
-         * Enable the UART FIFOs if they where not enabled and our
-         * configuration says we should turn them on.
-         */
-
-        arch_enable_uart_fifo();
-}
-
-
-
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S3C2440_UFSTAT_TXMASK;
+        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index cc6e561c9958..511031564d35 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -178,6 +178,7 @@ void __init s5pc100_init_clocks(int xtal)
         s5p_register_clocks(xtal);
         s5pc100_register_clocks();
         s5pc100_setup_clocks();
+        samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 }
 
 void __init s5pc100_init_irq(void)
@@ -219,7 +220,7 @@ void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 void s5pc100_restart(char mode, const char *cmd)
 {
         if (mode != 's')
-                arch_wdt_reset();
+                samsung_wdt_reset();
 
         soft_restart(0);
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
index 01ccf535e76c..720e1339425c 100644
--- a/arch/arm/mach-s5pc100/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -23,6 +23,8 @@ static void arch_detect_cpu(void)
         /* we do not need to do any cpu detection here at the moment. */
         fifo_mask = S3C2440_UFSTAT_TXMASK;
         fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+
+        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/uncompress.h b/arch/arm/mach-s5pv210/include/mach/uncompress.h
index ef977ea8546d..231cb07de058 100644
--- a/arch/arm/mach-s5pv210/include/mach/uncompress.h
+++ b/arch/arm/mach-s5pv210/include/mach/uncompress.h
@@ -21,6 +21,8 @@ static void arch_detect_cpu(void)
         /* we do not need to do any cpu detection here at the moment. */
         fifo_mask = S5PV210_UFSTAT_TXMASK;
         fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
+
+        uart_base = (volatile u8 *)S5P_PA_UART(CONFIG_S3C_LOWLEVEL_UART_PORT);
 }
 
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 1a517e2fe449..3912ce91fee4 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -23,7 +23,7 @@ config ARCH_R8A73A4
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
@@ -36,10 +36,13 @@ config ARCH_R8A7740
         select RENESAS_INTC_IRQPIN
 
 config ARCH_R8A7778
-        bool "R-Car M1 (R8A77780)"
+        bool "R-Car M1A (R8A77781)"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select CPU_V7
         select SH_CLK_CPG
         select ARM_GIC
+        select USB_ARCH_HAS_EHCI
+        select USB_ARCH_HAS_OHCI
 
 config ARCH_R8A7779
         bool "R-Car H1 (R8A77790)"
@@ -56,7 +59,7 @@ config ARCH_R8A7790
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
         select CPU_V7
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select SH_CLK_CPG
         select RENESAS_IRQC
 
@@ -68,27 +71,6 @@ config ARCH_EMEV2
 
 comment "SH-Mobile Board Type"
 
-config MACH_AP4EVB
-        bool "AP4EVB board"
-        depends on ARCH_SH7372
-        select ARCH_REQUIRE_GPIOLIB
-        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select SH_LCD_MIPI_DSI
-        select SND_SOC_AK4642 if SND_SIMPLE_CARD
-
-choice
-        prompt "AP4EVB LCD panel selection"
-        default AP4EVB_QHD
-        depends on MACH_AP4EVB
-
-config AP4EVB_QHD
-        bool "MIPI-DSI QHD (960x540)"
-
-config AP4EVB_WVGA
-        bool "Parallel WVGA (800x480)"
-
-endchoice
-
 config MACH_AG5EVM
         bool "AG5EVM board"
         depends on ARCH_SH73A0
@@ -115,19 +97,27 @@ config MACH_KOTA2
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
-config MACH_BONITO
-        bool "bonito board"
+config MACH_ARMADILLO800EVA
+        bool "Armadillo-800 EVA board"
         depends on ARCH_R8A7740
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_WM8978 if SND_SIMPLE_CARD
+        select USE_OF
 
-config MACH_ARMADILLO800EVA
-        bool "Armadillo-800 EVA board"
+config MACH_ARMADILLO800EVA_REFERENCE
+        bool "Armadillo-800 EVA board - Reference Device Tree Implementation"
         depends on ARCH_R8A7740
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_WM8978 if SND_SIMPLE_CARD
         select USE_OF
+        ---help---
+           Use reference implementation of Aramdillo800 EVA board support
+           which makes a greater use of device tree at the expense
+           of not supporting a number of devices.
+
+           This is intended to aid developers
 
 config MACH_BOCKW
         bool "BOCK-W platform"
@@ -169,6 +159,8 @@ config MACH_KZM9D
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_OPP
         select ARCH_REQUIRE_GPIOLIB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
@@ -194,37 +186,6 @@ config CPU_HAS_INTEVT
         bool
         default y
 
-menu "Memory configuration"
-
-config MEMORY_START
-        hex "Physical memory start address"
-        default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
-                                MACH_MACKEREL || MACH_BONITO || \
-                                MACH_ARMADILLO800EVA || MACH_APE6EVM || \
-                                MACH_LAGER
-        default "0x41000000" if MACH_KOTA2
-        default "0x00000000"
-        ---help---
-          Tweak this only when porting to a new machine which does not
-          already have a defconfig. Changing it from the known correct
-          value on any of the known systems will only lead to disaster.
-
-config MEMORY_SIZE
-        hex "Physical memory size"
-        default "0x80000000" if MACH_LAGER
-        default "0x40000000" if MACH_APE6EVM
-        default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
-                                MACH_ARMADILLO800EVA
-        default "0x1e000000" if MACH_KOTA2
-        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
-        default "0x04000000"
-        help
-          This sets the default memory size assumed by your kernel. It can
-          be overridden as normal by the 'mem=' argument on the kernel command
-          line.
-
-endmenu
-
 menu "Timer and clock configuration"
 
 config SHMOBILE_TIMER_HZ
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 068f1dadc46b..6165a517f580 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -35,17 +35,16 @@ obj-$(CONFIG_ARCH_R8A7779)	+= pm-r8a7779.o
 obj-$(CONFIG_ARCH_SH73A0)       += pm-sh73a0.o
 
 # Board objects
-obj-$(CONFIG_MACH_AP4EVB)       += board-ap4evb.o
 obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
 obj-$(CONFIG_MACH_APE6EVM)      += board-ape6evm.o
 obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
-obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
 obj-$(CONFIG_MACH_ARMADILLO800EVA)      += board-armadillo800eva.o
+obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE)    += board-armadillo800eva-reference.o
 obj-$(CONFIG_MACH_KZM9D)        += board-kzm9d.o
 obj-$(CONFIG_MACH_KZM9G)        += board-kzm9g.o
 obj-$(CONFIG_MACH_KZM9G_REFERENCE)      += board-kzm9g-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd99338d..84c6868580f0 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,6 +1,20 @@
-__ZRELADDR      := $(shell /bin/bash -c 'printf "0x%08x" \
-                     $$[$(CONFIG_MEMORY_START) + 0x8000]')
+# per-board load address for uImage
+loadaddr-y      :=
+loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000
+loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
+loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
+loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
+loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
+loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
+loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
+loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
+loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
+loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
+loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
+loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
+loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
 
+__ZRELADDR      := $(sort $(loadaddr-y))
    zreladdr-y   += $(__ZRELADDR)
 
 # Unsupported legacy stuff
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
deleted file mode 100644
index 45f78cadec1d..000000000000
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ /dev/null
@@ -1,1332 +0,0 @@
-/*
- * AP4EVB board support
- *
- * Copyright (C) 2010  Magnus Damm
- * Copyright (C) 2008  Yoshihiro Shimoda
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/clk.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/mfd/tmio.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/sh_mobile_sdhi.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mmc/sh_mmcif.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/io.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/sh_intc.h>
-#include <linux/sh_clk.h>
-#include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/leds.h>
-#include <linux/input/sh_keysc.h>
-#include <linux/usb/r8a66597.h>
-#include <linux/pm_clock.h>
-#include <linux/dma-mapping.h>
-
-#include <media/sh_mobile_ceu.h>
-#include <media/sh_mobile_csi2.h>
-#include <media/soc_camera.h>
-
-#include <sound/sh_fsi.h>
-#include <sound/simple_card.h>
-
-#include <video/sh_mobile_hdmi.h>
-#include <video/sh_mobile_lcdc.h>
-#include <video/sh_mipi_dsi.h>
-
-#include <mach/common.h>
-#include <mach/irqs.h>
-#include <mach/sh7372.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-
-#include "sh-gpio.h"
-
-/*
- * Address      Interface               BusWidth        note
- * ------------------------------------------------------------------
- * 0x0000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = ON
- * 0x0800_0000  user area               -
- * 0x1000_0000  NOR Flash ROM (MCP)     16bit           SW7 : bit1 = OFF
- * 0x1400_0000  Ether (LAN9220)         16bit
- * 0x1600_0000  user area               -               cannot use with NAND
- * 0x1800_0000  user area               -
- * 0x1A00_0000  -
- * 0x4000_0000  LPDDR2-SDRAM (POP)      32bit
- */
-
-/*
- * NOR Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NOR Flash ROM
- *  bit1 | bit1  bit2 | bit1 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    Area 0
- *  OFF  | ON     OFF | OFF  |    Area 4
- */
-
-/*
- * NAND Flash ROM
- *
- *  SW1  |     SW2    | SW7  | NAND Flash ROM
- *  bit1 | bit1  bit2 | bit2 | Memory allocation
- * ------+------------+------+------------------
- *  OFF  | ON     OFF | ON   |    FCE 0
- *  OFF  | ON     OFF | OFF  |    FCE 1
- */
-
-/*
- * SMSC 9220
- *
- *  SW1         SMSC 9220
- * -----------------------
- *  ON          access disable
- *  OFF         access enable
- */
-
-/*
- * LCD / IRQ / KEYSC / IrDA
- *
- * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
- * LCD = 2nd LCDC (WVGA)
- *
- *              |               SW43                    |
- * SW3          |       ON              |       OFF     |
- * -------------+-----------------------+---------------+
- * ON           | KEY / IrDA            | LCD           |
- * OFF          | KEY / IrDA / IRQ      | IRQ           |
- *
- *
- * QHD / WVGA display
- *
- * You can choice display type on menuconfig.
- * Then, check above dip-switch.
- */
-
-/*
- * USB
- *
- * J7 : 1-2  MAX3355E VBUS
- *      2-3  DC 5.0V
- *
- * S39: bit2: off
- */
-
-/*
- * FSI/FSMI
- *
- * SW41 :  ON : SH-Mobile AP4 Audio Mode
- *      : OFF : Bluetooth Audio Mode
- *
- * it needs amixer settings for playing
- *
- * amixer set "Headphone Enable" on
- */
-
-/*
- * MMC0/SDHI1 (CN7)
- *
- * J22 : select card voltage
- *       1-2 pin : 1.8v
- *       2-3 pin : 3.3v
- *
- *        SW1  |             SW33
- *             | bit1 | bit2 | bit3 | bit4
- * ------------+------+------+------+-------
- * MMC0   OFF  |  OFF |  ON  |  ON  |  X
- * SDHI1  OFF  |  ON  |   X  |  OFF | ON
- *
- * voltage lebel
- * CN7 : 1.8v
- * CN12: 3.3v
- */
-
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply fixed1v8_power_consumers[] =
-{
-        /* J22 default position: 1.8V */
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
-        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
-};
-
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
-        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
-        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
-};
-
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-
-/* MTD */
-static struct mtd_partition nor_flash_partitions[] = {
-        {
-                .name           = "loader",
-                .offset         = 0x00000000,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "bootenv",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 512 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel_ro",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-        {
-                .name           = "kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 8 * 1024 * 1024,
-        },
-        {
-                .name           = "data",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 2,
-        .parts          = nor_flash_partitions,
-        .nr_parts       = ARRAY_SIZE(nor_flash_partitions),
-};
-
-static struct resource nor_flash_resources[] = {
-        [0]     = {
-                .start  = 0x20000000, /* CS0 shadow instead of regular CS0 */
-                .end    = 0x28000000 - 1, /* needed by USB MASK ROM boot */
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device nor_flash_device = {
-        .name           = "physmap-flash",
-        .dev            = {
-                .platform_data  = &nor_flash_data,
-        },
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-        .resource       = nor_flash_resources,
-};
-
-/* SMSC 9220 */
-static struct resource smc911x_resources[] = {
-        {
-                .start  = 0x14000000,
-                .end    = 0x16000000 - 1,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = evt2irq(0x02c0) /* IRQ6A */,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_info = {
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-
-static struct platform_device smc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smc911x_resources),
-        .resource       = smc911x_resources,
-        .dev            = {
-                .platform_data = &smsc911x_info,
-        },
-};
-
-/*
- * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO 41).
- */
-static int slot_cn7_get_cd(struct platform_device *pdev)
-{
-        return !gpio_get_value(41);
-}
-/* MERAM */
-static struct sh_mobile_meram_info meram_info = {
-        .addr_mode      = SH_MOBILE_MERAM_MODE1,
-};
-
-static struct resource meram_resources[] = {
-        [0] = {
-                .name   = "regs",
-                .start  = 0xe8000000,
-                .end    = 0xe807ffff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .name   = "meram",
-                .start  = 0xe8080000,
-                .end    = 0xe81fffff,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device meram_device = {
-        .name           = "sh_mobile_meram",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(meram_resources),
-        .resource       = meram_resources,
-        .dev            = {
-                .platform_data = &meram_info,
-        },
-};
-
-/* SH_MMCIF */
-static struct resource sh_mmcif_resources[] = {
-        [0] = {
-                .name   = "MMCIF",
-                .start  = 0xE6BD0000,
-                .end    = 0xE6BD00FF,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* MMC ERR */
-                .start  = evt2irq(0x1ac0),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* MMC NOR */
-                .start  = evt2irq(0x1ae0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct sh_mmcif_plat_data sh_mmcif_plat = {
-        .sup_pclk       = 0,
-        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
-        .caps           = MMC_CAP_4_BIT_DATA |
-                          MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_NEEDS_POLL,
-        .get_cd         = slot_cn7_get_cd,
-        .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
-        .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
-};
-
-static struct platform_device sh_mmcif_device = {
-        .name           = "sh_mmcif",
-        .id             = 0,
-        .dev            = {
-                .dma_mask               = NULL,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &sh_mmcif_plat,
-        },
-        .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
-        .resource       = sh_mmcif_resources,
-};
-
-/* SDHI0 */
-static struct sh_mobile_sdhi_info sdhi0_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
-        .tmio_caps      = MMC_CAP_SDIO_IRQ,
-};
-
-static struct resource sdhi0_resources[] = {
-        [0] = {
-                .name   = "SDHI0",
-                .start  = 0xe6850000,
-                .end    = 0xe68500ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device sdhi0_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi0_resources),
-        .resource       = sdhi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &sdhi0_info,
-        },
-};
-
-/* SDHI1 */
-static struct sh_mobile_sdhi_info sdhi1_info = {
-        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
-        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
-        .tmio_ocr_mask  = MMC_VDD_165_195,
-        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
-        .tmio_caps      = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
-        .get_cd         = slot_cn7_get_cd,
-};
-
-static struct resource sdhi1_resources[] = {
-        [0] = {
-                .name   = "SDHI1",
-                .start  = 0xe6860000,
-                .end    = 0xe68600ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device sdhi1_device = {
-        .name           = "sh_mobile_sdhi",
-        .num_resources  = ARRAY_SIZE(sdhi1_resources),
-        .resource       = sdhi1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sdhi1_info,
-        },
-};
-
-/* USB1 */
-static void usb1_host_port_power(int port, int power)
-{
-        if (!power) /* only power-on supported for now */
-                return;
-
-        /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-        __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
-}
-
-static struct r8a66597_platdata usb1_host_data = {
-        .on_chip        = 1,
-        .port_power     = usb1_host_port_power,
-};
-
-static struct resource usb1_host_resources[] = {
-        [0] = {
-                .name   = "USBHS",
-                .start  = 0xE68B0000,
-                .end    = 0xE68B00E6 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device usb1_host_device = {
-        .name   = "r8a66597_hcd",
-        .id     = 1,
-        .dev = {
-                .dma_mask               = NULL,         /*  not use dma */
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &usb1_host_data,
-        },
-        .num_resources  = ARRAY_SIZE(usb1_host_resources),
-        .resource       = usb1_host_resources,
-};
-
-/*
- * QHD display
- */
-#ifdef CONFIG_AP4EVB_QHD
-
-/* KEYSC (Needs SW43 set to ON) */
-static struct sh_keysc_info keysc_info = {
-        .mode           = SH_KEYSC_MODE_1,
-        .scan_timing    = 3,
-        .delay          = 2500,
-        .keycodes = {
-                KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
-                KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
-                KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
-                KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
-                KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
-        },
-};
-
-static struct resource keysc_resources[] = {
-        [0] = {
-                .name   = "KEYSC",
-                .start  = 0xe61b0000,
-                .end    = 0xe61b0063,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0be0), /* KEYSC_KEY */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device keysc_device = {
-        .name           = "sh_keysc",
-        .id             = 0, /* "keysc0" clock */
-        .num_resources  = ARRAY_SIZE(keysc_resources),
-        .resource       = keysc_resources,
-        .dev    = {
-                .platform_data  = &keysc_info,
-        },
-};
-
-/* MIPI-DSI */
-static int sh_mipi_set_dot_clock(struct platform_device *pdev,
-                                 void __iomem *base,
-                                 int enable)
-{
-        struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
-
-        if (IS_ERR(pck))
-                return PTR_ERR(pck);
-
-        if (enable) {
-                /*
-                 * DSIPCLK      = 24MHz
-                 * D-PHY        = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
-                 * HsByteCLK    = D-PHY/8 = 39MHz
-                 *
-                 *  X * Y * FPS =
-                 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
-                 */
-                clk_set_rate(pck, clk_round_rate(pck, 24000000));
-                clk_enable(pck);
-        } else {
-                clk_disable(pck);
-        }
-
-        clk_put(pck);
-
-        return 0;
-}
-
-static struct resource mipidsi0_resources[] = {
-        [0] = {
-                .start  = 0xffc60000,
-                .end    = 0xffc63073,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xffc68000,
-                .end    = 0xffc680ef,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct sh_mipi_dsi_info mipidsi0_info = {
-        .data_format    = MIPI_RGB888,
-        .channel        = LCDC_CHAN_MAINLCD,
-        .lane           = 2,
-        .vsynw_offset   = 17,
-        .phyctrl        = 0x6 << 8,
-        .flags          = SH_MIPI_DSI_SYNC_PULSES_MODE |
-                          SH_MIPI_DSI_HSbyteCLK,
-        .set_dot_clock  = sh_mipi_set_dot_clock,
-};
-
-static struct platform_device mipidsi0_device = {
-        .name           = "sh-mipi-dsi",
-        .num_resources  = ARRAY_SIZE(mipidsi0_resources),
-        .resource       = mipidsi0_resources,
-        .id             = 0,
-        .dev    = {
-                .platform_data  = &mipidsi0_info,
-        },
-};
-
-static struct platform_device *qhd_devices[] __initdata = {
-        &mipidsi0_device,
-        &keysc_device,
-};
-#endif /* CONFIG_AP4EVB_QHD */
-
-/* LCDC0 */
-static const struct fb_videomode ap4evb_lcdc_modes[] = {
-        {
-#ifdef CONFIG_AP4EVB_QHD
-                .name           = "R63302(QHD)",
-                .xres           = 544,
-                .yres           = 961,
-                .left_margin    = 72,
-                .right_margin   = 600,
-                .hsync_len      = 16,
-                .upper_margin   = 8,
-                .lower_margin   = 8,
-                .vsync_len      = 2,
-                .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
-#else
-                .name           = "WVGA Panel",
-                .xres           = 800,
-                .yres           = 480,
-                .left_margin    = 220,
-                .right_margin   = 110,
-                .hsync_len      = 70,
-                .upper_margin   = 20,
-                .lower_margin   = 5,
-                .vsync_len      = 5,
-                .sync           = 0,
-#endif
-        },
-};
-
-static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x40,
-        },
-        .icb[1] = {
-                .meram_size     = 0x40,
-        },
-};
-
-static struct sh_mobile_lcdc_info lcdc_info = {
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .lcd_modes = ap4evb_lcdc_modes,
-                .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
-                .meram_cfg = &lcd_meram_cfg,
-#ifdef CONFIG_AP4EVB_QHD
-                .tx_dev = &mipidsi0_device,
-#endif
-        }
-};
-
-static struct resource lcdc_resources[] = {
-        [0] = {
-                .name   = "LCDC",
-                .start  = 0xfe940000, /* P4-only space */
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device lcdc_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc_resources),
-        .resource       = lcdc_resources,
-        .dev    = {
-                .platform_data  = &lcdc_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-
-/* FSI */
-#define IRQ_FSI         evt2irq(0x1840)
-static struct sh_fsi_platform_info fsi_info = {
-        .port_b = {
-                .flags          = SH_FSI_CLK_CPG |
-                                  SH_FSI_FMT_SPDIF,
-        },
-};
-
-static struct resource fsi_resources[] = {
-        [0] = {
-                .name   = "FSI",
-                .start  = 0xFE3C0000,
-                .end    = 0xFE3C0400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_FSI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device fsi_device = {
-        .name           = "sh_fsi2",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(fsi_resources),
-        .resource       = fsi_resources,
-        .dev    = {
-                .platform_data  = &fsi_info,
-        },
-};
-
-static struct asoc_simple_card_info fsi2_ak4643_info = {
-        .name           = "AK4643",
-        .card           = "FSI2A-AK4643",
-        .codec          = "ak4642-codec.0-0013",
-        .platform       = "sh_fsi2",
-        .daifmt         = SND_SOC_DAIFMT_LEFT_J,
-        .cpu_dai = {
-                .name   = "fsia-dai",
-                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
-        },
-        .codec_dai = {
-                .name   = "ak4642-hifi",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
-                .sysclk = 11289600,
-        },
-};
-
-static struct platform_device fsi_ak4643_device = {
-        .name   = "asoc-simple-card",
-        .dev    = {
-                .platform_data  = &fsi2_ak4643_info,
-        },
-};
-
-/* LCDC1 */
-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
-                                unsigned long *parent_freq);
-
-static struct sh_mobile_hdmi_info hdmi_info = {
-        .flags = HDMI_SND_SRC_SPDIF,
-        .clk_optimize_parent = ap4evb_clk_optimize,
-};
-
-static struct resource hdmi_resources[] = {
-        [0] = {
-                .name   = "HDMI",
-                .start  = 0xe6be0000,
-                .end    = 0xe6be00ff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
-                .start  = evt2irq(0x17e0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device hdmi_device = {
-        .name           = "sh-mobile-hdmi",
-        .num_resources  = ARRAY_SIZE(hdmi_resources),
-        .resource       = hdmi_resources,
-        .id             = -1,
-        .dev    = {
-                .platform_data  = &hdmi_info,
-        },
-};
-
-static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
-                                unsigned long *parent_freq)
-{
-        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
-        long error;
-
-        if (IS_ERR(hdmi_ick)) {
-                int ret = PTR_ERR(hdmi_ick);
-                pr_err("Cannot get HDMI ICK: %d\n", ret);
-                return ret;
-        }
-
-        error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
-
-        clk_put(hdmi_ick);
-
-        return error;
-}
-
-static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
-        .icb[0] = {
-                .meram_size     = 0x100,
-        },
-        .icb[1] = {
-                .meram_size     = 0x100,
-        },
-};
-
-static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
-        .clock_source = LCDC_CLK_EXTERNAL,
-        .meram_dev = &meram_info,
-        .ch[0] = {
-                .chan = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type = RGB24,
-                .clock_divider = 1,
-                .flags = LCDC_FLAGS_DWPOL,
-                .meram_cfg = &hdmi_meram_cfg,
-                .tx_dev = &hdmi_device,
-        }
-};
-
-static struct resource lcdc1_resources[] = {
-        [0] = {
-                .name   = "LCDC1",
-                .start  = 0xfe944000,
-                .end    = 0xfe947fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x1780),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device lcdc1_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .num_resources  = ARRAY_SIZE(lcdc1_resources),
-        .resource       = lcdc1_resources,
-        .id             = 1,
-        .dev    = {
-                .platform_data  = &sh_mobile_lcdc1_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-
-static struct asoc_simple_card_info fsi2_hdmi_info = {
-        .name           = "HDMI",
-        .card           = "FSI2B-HDMI",
-        .codec          = "sh-mobile-hdmi",
-        .platform       = "sh_fsi2",
-        .cpu_dai = {
-                .name   = "fsib-dai",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
-        },
-        .codec_dai = {
-                .name   = "sh_mobile_hdmi-hifi",
-        },
-};
-
-static struct platform_device fsi_hdmi_device = {
-        .name   = "asoc-simple-card",
-        .id     = 1,
-        .dev    = {
-                .platform_data  = &fsi2_hdmi_info,
-        },
-};
-
-static struct gpio_led ap4evb_leds[] = {
-        {
-                .name                   = "led4",
-                .gpio                   = 185,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led2",
-                .gpio                   = 186,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led3",
-                .gpio                   = 187,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        },
-        {
-                .name                   = "led1",
-                .gpio                   = 188,
-                .default_state  = LEDS_GPIO_DEFSTATE_ON,
-        }
-};
-
-static struct gpio_led_platform_data ap4evb_leds_pdata = {
-        .num_leds = ARRAY_SIZE(ap4evb_leds),
-        .leds = ap4evb_leds,
-};
-
-static struct platform_device leds_device = {
-        .name = "leds-gpio",
-        .id = 0,
-        .dev = {
-                .platform_data  = &ap4evb_leds_pdata,
-        },
-};
-
-static struct i2c_board_info imx074_info = {
-        I2C_BOARD_INFO("imx074", 0x1a),
-};
-
-static struct soc_camera_link imx074_link = {
-        .bus_id         = 0,
-        .board_info     = &imx074_info,
-        .i2c_adapter_id = 0,
-        .module_name    = "imx074",
-};
-
-static struct platform_device ap4evb_camera = {
-        .name   = "soc-camera-pdrv",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &imx074_link,
-        },
-};
-
-static struct sh_csi2_client_config csi2_clients[] = {
-        {
-                .phy            = SH_CSI2_PHY_MAIN,
-                .lanes          = 0,            /* default: 2 lanes */
-                .channel        = 0,
-                .pdev           = &ap4evb_camera,
-        },
-};
-
-static struct sh_csi2_pdata csi2_info = {
-        .type           = SH_CSI2C,
-        .clients        = csi2_clients,
-        .num_clients    = ARRAY_SIZE(csi2_clients),
-        .flags          = SH_CSI2_ECC | SH_CSI2_CRC,
-};
-
-static struct resource csi2_resources[] = {
-        [0] = {
-                .name   = "CSI2",
-                .start  = 0xffc90000,
-                .end    = 0xffc90fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x17a0),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct sh_mobile_ceu_companion csi2 = {
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(csi2_resources),
-        .resource       = csi2_resources,
-        .platform_data  = &csi2_info,
-};
-
-static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
-        .flags = SH_CEU_FLAG_USE_8BIT_BUS,
-        .max_width = 8188,
-        .max_height = 8188,
-        .csi2 = &csi2,
-};
-
-static struct resource ceu_resources[] = {
-        [0] = {
-                .name   = "CEU",
-                .start  = 0xfe910000,
-                .end    = 0xfe91009f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x880),
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* place holder for contiguous memory */
-        },
-};
-
-static struct platform_device ceu_device = {
-        .name           = "sh_mobile_ceu",
-        .id             = 0, /* "ceu0" clock */
-        .num_resources  = ARRAY_SIZE(ceu_resources),
-        .resource       = ceu_resources,
-        .dev    = {
-                .platform_data          = &sh_mobile_ceu_info,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-};
-
-static struct platform_device *ap4evb_devices[] __initdata = {
-        &leds_device,
-        &nor_flash_device,
-        &smc911x_device,
-        &sdhi0_device,
-        &sdhi1_device,
-        &usb1_host_device,
-        &fsi_device,
-        &fsi_ak4643_device,
-        &fsi_hdmi_device,
-        &sh_mmcif_device,
-        &hdmi_device,
-        &lcdc_device,
-        &lcdc1_device,
-        &ceu_device,
-        &ap4evb_camera,
-        &meram_device,
-};
-
-static void __init hdmi_init_pm_clock(void)
-{
-        struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
-        int ret;
-        long rate;
-
-        if (IS_ERR(hdmi_ick)) {
-                ret = PTR_ERR(hdmi_ick);
-                pr_err("Cannot get HDMI ICK: %d\n", ret);
-                goto out;
-        }
-
-        ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
-        if (ret < 0) {
-                pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
-                goto out;
-        }
-
-        pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
-
-        rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
-        if (rate < 0) {
-                pr_err("Cannot get suitable rate: %ld\n", rate);
-                ret = rate;
-                goto out;
-        }
-
-        ret = clk_set_rate(&sh7372_pllc2_clk, rate);
-        if (ret < 0) {
-                pr_err("Cannot set rate %ld: %d\n", rate, ret);
-                goto out;
-        }
-
-        pr_debug("PLLC2 set frequency %lu\n", rate);
-
-        ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
-        if (ret < 0)
-                pr_err("Cannot set HDMI parent: %d\n", ret);
-
-out:
-        if (!IS_ERR(hdmi_ick))
-                clk_put(hdmi_ick);
-}
-
-/* TouchScreen */
-#ifdef CONFIG_AP4EVB_QHD
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT  123
-#else /* WVGA */
-# define GPIO_TSC_IRQ   GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT  40
-#endif
-
-#define IRQ28   evt2irq(0x3380) /* IRQ28A */
-#define IRQ7    evt2irq(0x02e0) /* IRQ7A */
-static int ts_get_pendown_state(void)
-{
-        int val;
-
-        gpio_free(GPIO_TSC_IRQ);
-
-        gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
-
-        val = gpio_get_value(GPIO_TSC_PORT);
-
-        gpio_request(GPIO_TSC_IRQ, NULL);
-
-        return !val;
-}
-
-static int ts_init(void)
-{
-        gpio_request(GPIO_TSC_IRQ, NULL);
-
-        return 0;
-}
-
-static struct tsc2007_platform_data tsc2007_info = {
-        .model                  = 2007,
-        .x_plate_ohms           = 180,
-        .get_pendown_state      = ts_get_pendown_state,
-        .init_platform_hw       = ts_init,
-};
-
-static struct i2c_board_info tsc_device = {
-        I2C_BOARD_INFO("tsc2007", 0x48),
-        .type           = "tsc2007",
-        .platform_data  = &tsc2007_info,
-        /*.irq is selected on ap4evb_init */
-};
-
-/* I2C */
-static struct i2c_board_info i2c0_devices[] = {
-        {
-                I2C_BOARD_INFO("ak4643", 0x13),
-        },
-};
-
-static struct i2c_board_info i2c1_devices[] = {
-        {
-                I2C_BOARD_INFO("r2025sd", 0x32),
-        },
-};
-
-
-static const struct pinctrl_map ap4evb_pinctrl_map[] = {
-        /* MMCIF */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_data8_0", "mmc0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
-                                  "mmc0_ctrl_0", "mmc0"),
-        /* SDHI0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_data4", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_ctrl", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_cd", "sdhi0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
-                                  "sdhi0_wp", "sdhi0"),
-        /* SDHI1 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_data4", "sdhi1"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
-                                  "sdhi1_ctrl", "sdhi1"),
-};
-
-#define GPIO_PORT9CR    IOMEM(0xE6051009)
-#define GPIO_PORT10CR   IOMEM(0xE605100A)
-#define USCCR1          IOMEM(0xE6058144)
-static void __init ap4evb_init(void)
-{
-        struct pm_domain_device domain_devices[] = {
-                { "A4LC", &lcdc1_device, },
-                { "A4LC", &lcdc_device, },
-                { "A4MP", &fsi_device, },
-                { "A3SP", &sh_mmcif_device, },
-                { "A3SP", &sdhi0_device, },
-                { "A3SP", &sdhi1_device, },
-                { "A4R", &ceu_device, },
-        };
-        u32 srcr4;
-        struct clk *clk;
-
-        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
-                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
-        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
-                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
-        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        /* External clock source */
-        clk_set_rate(&sh7372_dv_clki_clk, 27000000);
-
-        pinctrl_register_mappings(ap4evb_pinctrl_map,
-                                  ARRAY_SIZE(ap4evb_pinctrl_map));
-        sh7372_pinmux_init();
-
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
-        /* enable Debug switch (S6) */
-        gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
-        gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
-
-        /* USB enable */
-        gpio_request(GPIO_FN_VBUS0_1,    NULL);
-        gpio_request(GPIO_FN_IDIN_1_18,  NULL);
-        gpio_request(GPIO_FN_PWEN_1_115, NULL);
-        gpio_request(GPIO_FN_OVCN_1_114, NULL);
-        gpio_request(GPIO_FN_EXTLP_1,    NULL);
-        gpio_request(GPIO_FN_OVCN2_1,    NULL);
-
-        /* setup USB phy */
-        __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
-
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
-        gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
-
-        gpio_request(9, NULL);
-        gpio_request(10, NULL);
-        gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
-        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
-
-        /* card detect pin for MMC slot (CN7) */
-        gpio_request_one(41, GPIOF_IN, NULL);
-
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
-        __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
-
-        /* set SPU2 clock to 119.6 MHz */
-        clk = clk_get(NULL, "spu_clk");
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, clk_round_rate(clk, 119600000));
-                clk_put(clk);
-        }
-
-        /*
-         * set irq priority, to avoid sound chopping
-         * when NFS rootfs is used
-         *  FSI(3) > SMSC911X(2)
-         */
-        intc_set_priority(IRQ_FSI, 3);
-
-        i2c_register_board_info(0, i2c0_devices,
-                                ARRAY_SIZE(i2c0_devices));
-
-        i2c_register_board_info(1, i2c1_devices,
-                                ARRAY_SIZE(i2c1_devices));
-
-#ifdef CONFIG_AP4EVB_QHD
-
-        /*
-         * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
-         * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
-         */
-
-        /* enable KEYSC */
-        gpio_request(GPIO_FN_KEYOUT0, NULL);
-        gpio_request(GPIO_FN_KEYOUT1, NULL);
-        gpio_request(GPIO_FN_KEYOUT2, NULL);
-        gpio_request(GPIO_FN_KEYOUT3, NULL);
-        gpio_request(GPIO_FN_KEYOUT4, NULL);
-        gpio_request(GPIO_FN_KEYIN0_136, NULL);
-        gpio_request(GPIO_FN_KEYIN1_135, NULL);
-        gpio_request(GPIO_FN_KEYIN2_134, NULL);
-        gpio_request(GPIO_FN_KEYIN3_133, NULL);
-        gpio_request(GPIO_FN_KEYIN4,     NULL);
-
-        /* enable TouchScreen */
-        irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
-
-        tsc_device.irq = IRQ28;
-        i2c_register_board_info(1, &tsc_device, 1);
-
-        /* LCDC0 */
-        lcdc_info.clock_source                  = LCDC_CLK_PERIPHERAL;
-        lcdc_info.ch[0].interface_type          = RGB24;
-        lcdc_info.ch[0].clock_divider           = 1;
-        lcdc_info.ch[0].flags                   = LCDC_FLAGS_DWPOL;
-        lcdc_info.ch[0].panel_cfg.width         = 44;
-        lcdc_info.ch[0].panel_cfg.height        = 79;
-
-        platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
-
-#else
-        /*
-         * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
-         * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
-         */
-
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
-        gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
-        gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
-
-        lcdc_info.clock_source                  = LCDC_CLK_BUS;
-        lcdc_info.ch[0].interface_type          = RGB18;
-        lcdc_info.ch[0].clock_divider           = 3;
-        lcdc_info.ch[0].flags                   = 0;
-        lcdc_info.ch[0].panel_cfg.width         = 152;
-        lcdc_info.ch[0].panel_cfg.height        = 91;
-
-        /* enable TouchScreen */
-        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
-
-        tsc_device.irq = IRQ7;
-        i2c_register_board_info(0, &tsc_device, 1);
-#endif /* CONFIG_AP4EVB_QHD */
-
-        /* CEU */
-
-        /*
-         * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
-         * becomes available
-         */
-
-        /* MIPI-CSI stuff */
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-
-        clk = clk_get(NULL, "vck1_clk");
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, clk_round_rate(clk, 13000000));
-                clk_enable(clk);
-                clk_put(clk);
-        }
-
-        sh7372_add_standard_devices();
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
-        /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 IOMEM(0xe61580bc)
-        srcr4 = __raw_readl(SRCR4);
-        __raw_writel(srcr4 | (1 << 13), SRCR4);
-        udelay(50);
-        __raw_writel(srcr4 & ~(1 << 13), SRCR4);
-
-        platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
-
-        rmobile_add_devices_to_domains(domain_devices,
-                                       ARRAY_SIZE(domain_devices));
-
-        hdmi_init_pm_clock();
-        sh7372_pm_init();
-        pm_clk_add(&fsi_device.dev, "spu2");
-        pm_clk_add(&lcdc1_device.dev, "hdmi");
-}
-
-MACHINE_START(AP4EVB, "ap4evb")
-        .map_io         = sh7372_map_io,
-        .init_early     = sh7372_add_early_devices,
-        .init_irq       = sh7372_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = ap4evb_init,
-        .init_late      = sh7372_pm_init_late,
-        .init_time      = sh7372_earlytimer_init,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 55b8c9fef954..5eb0caa6a7d0 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -26,6 +26,7 @@
 #include <linux/platform_device.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
+#include <linux/sh_clk.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
@@ -65,7 +66,21 @@ static const struct pinctrl_map ape6evm_pinctrl_map[] = {
 
 static void __init ape6evm_add_standard_devices(void)
 {
+
+        struct clk *parent;
+        struct clk *mp;
+
         r8a73a4_clock_init();
+
+        /* MP clock parent = extal2 */
+        parent      = clk_get(NULL, "extal2");
+        mp          = clk_get(NULL, "mp");
+        BUG_ON(IS_ERR(parent) || IS_ERR(mp));
+
+        clk_set_parent(mp, parent);
+        clk_put(parent);
+        clk_put(mp);
+
         pinctrl_register_mappings(ape6evm_pinctrl_map,
                                   ARRAY_SIZE(ape6evm_pinctrl_map));
         r8a73a4_pinmux_init();
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
new file mode 100644
index 000000000000..03b85fec2ddb
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -0,0 +1,213 @@
+/*
+ * armadillo 800 eva board support
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/pinctrl/machine.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+
+/*
+ * CON1         Camera Module
+ * CON2         Extension Bus
+ * CON3         HDMI Output
+ * CON4         Composite Video Output
+ * CON5         H-UDI JTAG
+ * CON6         ARM JTAG
+ * CON7         SD1
+ * CON8         SD2
+ * CON9         RTC BackUp
+ * CON10        Monaural Mic Input
+ * CON11        Stereo Headphone Output
+ * CON12        Audio Line Output(L)
+ * CON13        Audio Line Output(R)
+ * CON14        AWL13 Module
+ * CON15        Extension
+ * CON16        LCD1
+ * CON17        LCD2
+ * CON19        Power Input
+ * CON20        USB1
+ * CON21        USB2
+ * CON22        Serial
+ * CON23        LAN
+ * CON24        USB3
+ * LED1         Camera LED(Yellow)
+ * LED2         Power LED (Green)
+ * ED3-LED6     User LED(Yellow)
+ * LED7         LAN link LED(Green)
+ * LED8         LAN activity LED(Yellow)
+ */
+
+/*
+ * DipSwitch
+ *
+ *                    SW1
+ *
+ * -12345678-+---------------+----------------------------
+ *  1        | boot          | hermit
+ *  0        | boot          | OS auto boot
+ * -12345678-+---------------+----------------------------
+ *   00      | boot device   | eMMC
+ *   10      | boot device   | SDHI0 (CON7)
+ *   01      | boot device   | -
+ *   11      | boot device   | Extension Buss (CS0)
+ * -12345678-+---------------+----------------------------
+ *     0     | Extension Bus | D8-D15 disable, eMMC enable
+ *     1     | Extension Bus | D8-D15 enable,  eMMC disable
+ * -12345678-+---------------+----------------------------
+ *      0    | SDHI1         | COM8 disable, COM14 enable
+ *      1    | SDHI1         | COM8 enable,  COM14 disable
+ * -12345678-+---------------+----------------------------
+ *       0   | USB0          | COM20 enable,  COM24 disable
+ *       1   | USB0          | COM20 disable, COM24 enable
+ * -12345678-+---------------+----------------------------
+ *        00 | JTAG          | SH-X2
+ *        10 | JTAG          | ARM
+ *        01 | JTAG          | -
+ *        11 | JTAG          | Boundary Scan
+ *-----------+---------------+----------------------------
+ */
+
+/*
+ * FSI-WM8978
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "Headphone" 50
+ *
+ * this command is required when capture.
+ *
+ * # amixer set "Input PGA" 15
+ * # amixer set "Left Input Mixer MicP" on
+ * # amixer set "Left Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicN" on
+ * # amixer set "Right Input Mixer MicP" on
+ */
+
+/*
+ * USB function
+ *
+ * When you use USB Function,
+ * set SW1.6 ON, and connect cable to CN24.
+ *
+ * USBF needs workaround on R8A7740 chip.
+ * These are a little bit complex.
+ * see
+ *      usbhsf_power_ctrl()
+ */
+
+static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
+};
+
+static void __init eva_clock_init(void)
+{
+        struct clk *system      = clk_get(NULL, "system_clk");
+        struct clk *xtal1       = clk_get(NULL, "extal1");
+        struct clk *usb24s      = clk_get(NULL, "usb24s");
+        struct clk *fsibck      = clk_get(NULL, "fsibck");
+
+        if (IS_ERR(system)      ||
+            IS_ERR(xtal1)       ||
+            IS_ERR(usb24s)      ||
+            IS_ERR(fsibck)) {
+                pr_err("armadillo800eva board clock init failed\n");
+                goto clock_error;
+        }
+
+        /* armadillo 800 eva extal1 is 24MHz */
+        clk_set_rate(xtal1, 24000000);
+
+        /* usb24s use extal1 (= system) clock (= 24MHz) */
+        clk_set_parent(usb24s, system);
+
+        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
+        clk_set_rate(fsibck, 12288000);
+
+clock_error:
+        if (!IS_ERR(system))
+                clk_put(system);
+        if (!IS_ERR(xtal1))
+                clk_put(xtal1);
+        if (!IS_ERR(usb24s))
+                clk_put(usb24s);
+        if (!IS_ERR(fsibck))
+                clk_put(fsibck);
+}
+
+/*
+ * board init
+ */
+static void __init eva_init(void)
+{
+
+        r8a7740_clock_init(MD_CK0 | MD_CK2);
+        eva_clock_init();
+
+        pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+        r8a7740_pinmux_init();
+
+        r8a7740_meram_workaround();
+
+        /*
+         * Touchscreen
+         * TODO: Move reset GPIO over to .dts when we can reference it
+         */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+
+        r8a7740_add_standard_devices_dt();
+        r8a7740_pm_init();
+}
+
+#define RESCNT2 IOMEM(0xe6188020)
+static void eva_restart(char mode, const char *cmd)
+{
+        /* Do soft power on reset */
+        writel((1 << 31), RESCNT2);
+}
+
+static const char *eva_boards_compat_dt[] __initdata = {
+        "renesas,armadillo800eva-reference",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
+        .map_io         = r8a7740_map_io,
+        .init_early     = r8a7740_init_delay,
+        .init_irq       = r8a7740_init_irq_of,
+        .init_machine   = eva_init,
+        .init_time      = shmobile_timer_init,
+        .init_late      = shmobile_init_late,
+        .dt_compat      = eva_boards_compat_dt,
+        .restart        = eva_restart,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index b85b2882dbd0..44a621505eeb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -584,7 +584,7 @@ static struct regulator_init_data vcc_sdhi0_init_data = {
 static struct fixed_voltage_config vcc_sdhi0_info = {
         .supply_name = "SDHI0 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT75,
+        .gpio = 75,
         .enable_high = 1,
         .init_data = &vcc_sdhi0_init_data,
 };
@@ -615,7 +615,7 @@ static struct regulator_init_data vccq_sdhi0_init_data = {
 };
 
 static struct gpio vccq_sdhi0_gpios[] = {
-        {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+        {17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
 };
 
 static struct gpio_regulator_state vccq_sdhi0_states[] = {
@@ -626,7 +626,7 @@ static struct gpio_regulator_state vccq_sdhi0_states[] = {
 static struct gpio_regulator_config vccq_sdhi0_info = {
         .supply_name = "vqmmc",
 
-        .enable_gpio = GPIO_PORT74,
+        .enable_gpio = 74,
         .enable_high = 1,
         .enabled_at_boot = 0,
 
@@ -664,7 +664,7 @@ static struct regulator_init_data vcc_sdhi1_init_data = {
 static struct fixed_voltage_config vcc_sdhi1_info = {
         .supply_name = "SDHI1 Vcc",
         .microvolts = 3300000,
-        .gpio = GPIO_PORT16,
+        .gpio = 16,
         .enable_high = 1,
         .init_data = &vcc_sdhi1_init_data,
 };
@@ -693,7 +693,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
-        .cd_gpio        = GPIO_PORT167,
+        .cd_gpio        = 167,
 };
 
 static struct resource sdhi0_resources[] = {
@@ -736,7 +736,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
                           MMC_CAP_POWER_OFF_CARD,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
         /* Port72 cannot generate IRQs, will be used in polling mode. */
-        .cd_gpio        = GPIO_PORT72,
+        .cd_gpio        = 72,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -1046,6 +1046,35 @@ static struct platform_device *eva_devices[] __initdata = {
 };
 
 static const struct pinctrl_map eva_pinctrl_map[] = {
+        /* CEU0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_data_0_7", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_clk_0", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_sync", "ceu0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-r8a7740",
+                                  "ceu0_field", "ceu0"),
+        /* FSIA */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_mclk_out", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_in_1", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-r8a7740",
+                                  "fsia_data_out_0", "fsia"),
+        /* FSIB */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-r8a7740",
+                                  "fsib_mclk_in", "fsib"),
+        /* GETHER */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_mii", "gether"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-eth", "pfc-r8a7740",
+                                  "gether_int", "gether"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-r8a7740",
+                                  "hdmi", "hdmi"),
         /* LCD0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
                                   "lcd0_data24_0", "lcd0"),
@@ -1058,6 +1087,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "mmc0_data8_1", "mmc0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
                                   "mmc0_ctrl_1", "mmc0"),
+        /* SCIFA1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
+                                  "scifa1_data", "scifa1"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_data4", "sdhi0"),
@@ -1065,6 +1097,12 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
                                   "sdhi0_wp", "sdhi0"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
+                                  "intc_irq10", "intc"),
+        /* USBHS */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
+                                  "intc_irq7_1", "intc"),
 };
 
 static void __init eva_clock_init(void)
@@ -1119,40 +1157,14 @@ static void __init eva_init(void)
         r8a7740_pinmux_init();
         r8a7740_meram_workaround();
 
-        /* SCIFA1 */
-        gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
-        gpio_request(GPIO_FN_SCIFA1_TXD, NULL);
-
         /* LCDC0 */
-        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
-
         gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
         gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
 
         /* Touchscreen */
-        gpio_request(GPIO_FN_IRQ10,     NULL); /* TP_INT */
+        gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
 
         /* GETHER */
-        gpio_request(GPIO_FN_ET_CRS,            NULL);
-        gpio_request(GPIO_FN_ET_MDC,            NULL);
-        gpio_request(GPIO_FN_ET_MDIO,           NULL);
-        gpio_request(GPIO_FN_ET_TX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_RX_ER,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ERXD3,          NULL);
-        gpio_request(GPIO_FN_ET_TX_CLK,         NULL);
-        gpio_request(GPIO_FN_ET_TX_EN,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD0,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD1,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD2,          NULL);
-        gpio_request(GPIO_FN_ET_ETXD3,          NULL);
-        gpio_request(GPIO_FN_ET_PHY_INT,        NULL);
-        gpio_request(GPIO_FN_ET_COL,            NULL);
-        gpio_request(GPIO_FN_ET_RX_DV,          NULL);
-        gpio_request(GPIO_FN_ET_RX_CLK,         NULL);
-
         gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
 
         /* USB */
@@ -1163,34 +1175,17 @@ static void __init eva_init(void)
         } else {
                 /* USB Func */
                 /*
-                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
-                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
-                 * USB connection/disconnection (usbhsf_get_vbus()).
-                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
-                 * and select GPIO 209 here
+                 * The USBHS interrupt handlers needs to read the IRQ pin value
+                 * (HI/LOW) to diffentiate USB connection and disconnection
+                 * events (usbhsf_get_vbus()). We thus need to select both the
+                 * intc_irq7_1 pin group and GPIO 209 here.
                  */
-                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
                 gpio_request_one(209, GPIOF_IN, NULL);
 
                 platform_device_register(&usbhsf_device);
                 usb = &usbhsf_device;
         }
 
-        /* CEU0 */
-        gpio_request(GPIO_FN_VIO0_D7,           NULL);
-        gpio_request(GPIO_FN_VIO0_D6,           NULL);
-        gpio_request(GPIO_FN_VIO0_D5,           NULL);
-        gpio_request(GPIO_FN_VIO0_D4,           NULL);
-        gpio_request(GPIO_FN_VIO0_D3,           NULL);
-        gpio_request(GPIO_FN_VIO0_D2,           NULL);
-        gpio_request(GPIO_FN_VIO0_D1,           NULL);
-        gpio_request(GPIO_FN_VIO0_D0,           NULL);
-        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
-        gpio_request(GPIO_FN_VIO0_HD,           NULL);
-        gpio_request(GPIO_FN_VIO0_VD,           NULL);
-        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
-        gpio_request(GPIO_FN_VIO_CKO,           NULL);
-
         /* CON1/CON15 Camera */
         gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL);  /* STANDBY */
         gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
@@ -1198,24 +1193,11 @@ static void __init eva_init(void)
         gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL);  /* CAM_PON */
 
         /* FSI-WM8978 */
-        gpio_request(GPIO_FN_FSIAIBT,           NULL);
-        gpio_request(GPIO_FN_FSIAILR,           NULL);
-        gpio_request(GPIO_FN_FSIAOMC,           NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
-        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
-
         gpio_request(7, NULL);
         gpio_request(8, NULL);
         gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
         gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
 
-        /* FSI-HDMI */
-        gpio_request(GPIO_FN_FSIBCK,            NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
-        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
-
         /*
          * CAUTION
          *
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 38e5e50fb318..d5554646916c 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -18,13 +18,52 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/partitions.h>
+#include <linux/pinctrl/machine.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <asm/mach/arch.h>
 
+/*
+ *      CN9(Upper side) SCIF/RCAN selection
+ *
+ *              1,4     3,6
+ * SW40         SCIF    RCAN
+ * SW41         SCIF    RCAN
+ */
+
+/*
+ * MMC (CN26) pin
+ *
+ * SW6  (D2)    3 pin
+ * SW7  (D5)    ON
+ * SW8  (D3)    3 pin
+ * SW10 (D4)    1 pin
+ * SW12 (CLK)   1 pin
+ * SW13 (D6)    3 pin
+ * SW14 (CMD)   ON
+ * SW15 (D6)    1 pin
+ * SW16 (D0)    ON
+ * SW17 (D1)    ON
+ * SW18 (D7)    3 pin
+ * SW19 (MMC)   1 pin
+ */
+
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct smsc911x_platform_config smsc911x_data = {
         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
@@ -37,17 +76,128 @@ static struct resource smsc911x_resources[] = {
         DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
 };
 
+/* USB */
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+
+/* SDHI */
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
+};
+
+static struct sh_eth_plat_data ether_platform_data __initdata = {
+        .phy            = 0x01,
+        .edmac_endian   = EDMAC_LITTLE_ENDIAN,
+        .register_type  = SH_ETH_REG_FAST_RCAR,
+        .phy_interface  = PHY_INTERFACE_MODE_RMII,
+        /*
+         * Although the LINK signal is available on the board, it's connected to
+         * the link/activity LED output of the PHY, thus the link disappears and
+         * reappears after each packet.  We'd be better off ignoring such signal
+         * and getting the link state from the PHY indirectly.
+         */
+        .no_ether_link  = 1,
+};
+
+/* I2C */
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("rx8581", 0x51),
+        },
+};
+
+/* HSPI*/
+static struct mtd_partition m25p80_spi_flash_partitions[] = {
+        {
+                .name   = "data(spi)",
+                .size   = 0x0100000,
+                .offset = 0,
+        },
+};
+
+static struct flash_platform_data spi_flash_data = {
+        .name           = "m25p80",
+        .type           = "s25fl008k",
+        .parts          = m25p80_spi_flash_partitions,
+        .nr_parts       = ARRAY_SIZE(m25p80_spi_flash_partitions),
+};
+
+static struct spi_board_info spi_board_info[] __initdata = {
+        {
+                .modalias       = "m25p80",
+                .max_speed_hz   = 104000000,
+                .chip_select    = 0,
+                .bus_num        = 0,
+                .mode           = SPI_MODE_0,
+                .platform_data  = &spi_flash_data,
+        },
+};
+
+/* MMC */
+static struct sh_mmcif_plat_data sh_mmcif_plat = {
+        .sup_pclk       = 0,
+        .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
+        .caps           = MMC_CAP_4_BIT_DATA |
+                          MMC_CAP_8_BIT_DATA |
+                          MMC_CAP_NEEDS_POLL,
+};
+
+static const struct pinctrl_map bockw_pinctrl_map[] = {
+        /* Ether */
+        PIN_MAP_MUX_GROUP_DEFAULT("r8a777x-ether", "pfc-r8a7778",
+                                  "ether_rmii", "ether"),
+        /* HSPI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7778",
+                                  "hspi0_a", "hspi0"),
+        /* MMC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
+                                  "mmc_data8", "mmc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif", "pfc-r8a7778",
+                                  "mmc_ctrl", "mmc"),
+        /* SCIF0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_data_a", "scif0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
+                                  "scif0_ctrl", "scif0"),
+        /* USB */
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb0", "usb0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform", "pfc-r8a7778",
+                                  "usb1", "usb1"),
+        /* SDHI0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
+                                  "sdhi0", "sdhi0"),
+};
+
+#define FPGA    0x18200000
 #define IRQ0MR  0x30
+#define PFC     0xfffc0000
+#define PUPR4   0x110
 static void __init bockw_init(void)
 {
-        void __iomem *fpga;
+        void __iomem *base;
 
         r8a7778_clock_init();
         r8a7778_init_irq_extpin(1);
         r8a7778_add_standard_devices();
+        r8a7778_add_usb_phy_device(&usb_phy_platform_data);
+        r8a7778_add_ether_device(&ether_platform_data);
+        r8a7778_add_i2c_device(0);
+        r8a7778_add_hspi_device(0);
+        r8a7778_add_mmc_device(&sh_mmcif_plat);
 
-        fpga = ioremap_nocache(0x18200000, SZ_1M);
-        if (fpga) {
+        i2c_register_board_info(0, i2c0_devices,
+                                ARRAY_SIZE(i2c0_devices));
+        spi_register_board_info(spi_board_info,
+                                ARRAY_SIZE(spi_board_info));
+        pinctrl_register_mappings(bockw_pinctrl_map,
+                                  ARRAY_SIZE(bockw_pinctrl_map));
+        r8a7778_pinmux_init();
+
+        /* for SMSC */
+        base = ioremap_nocache(FPGA, SZ_1M);
+        if (base) {
                 /*
                  * CAUTION
                  *
@@ -55,16 +205,33 @@ static void __init bockw_init(void)
                  * it should be cared in the future
                  * Now, it is assuming IRQ0 was used only from SMSC.
                  */
-                u16 val = ioread16(fpga + IRQ0MR);
+                u16 val = ioread16(base + IRQ0MR);
                 val &= ~(1 << 4); /* enable SMSC911x */
-                iowrite16(val, fpga + IRQ0MR);
-                iounmap(fpga);
+                iowrite16(val, base + IRQ0MR);
+                iounmap(base);
+
+                regulator_register_fixed(0, dummy_supplies,
+                                         ARRAY_SIZE(dummy_supplies));
 
                 platform_device_register_resndata(
                         &platform_bus, "smsc911x", -1,
                         smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
                         &smsc911x_data, sizeof(smsc911x_data));
         }
+
+        /* for SDHI */
+        base = ioremap_nocache(PFC, 0x200);
+        if (base) {
+                /*
+                 * FIXME
+                 *
+                 * SDHI CD/WP pin needs pull-up
+                 */
+                iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
+                iounmap(base);
+
+                r8a7778_sdhi_init(0, &sdhi0_info);
+        }
 }
 
 static const char *bockw_boards_compat_dt[] __initdata = {
@@ -78,4 +245,5 @@ DT_MACHINE_START(BOCKW_DT, "bockw")
         .init_machine   = bockw_init,
         .init_time      = shmobile_timer_init,
         .dt_compat      = bockw_boards_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
deleted file mode 100644
index 70d992c540ae..000000000000
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/*
- * bonito board support
- *
- * Copyright (C) 2011 Renesas Solutions Corp.
- * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/pinctrl/machine.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/fixed.h>
-#include <linux/regulator/machine.h>
-#include <linux/smsc911x.h>
-#include <linux/videodev2.h>
-#include <mach/common.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <mach/r8a7740.h>
-#include <mach/irqs.h>
-#include <video/sh_mobile_lcdc.h>
-
-/*
- * CS   Address         device                  note
- *----------------------------------------------------------------
- * 0    0x0000_0000     NOR Flash (64MB)        SW12 : bit3 = OFF
- * 2    0x0800_0000     ExtNOR (64MB)           SW12 : bit3 = OFF
- * 4                    -
- * 5A                   -
- * 5B   0x1600_0000     SRAM (8MB)
- * 6    0x1800_0000     FPGA (64K)
- *      0x1801_0000     Ether (4KB)
- *      0x1801_1000     USB (4KB)
- */
-
-/*
- * SW12
- *
- *      bit1                    bit2                    bit3
- *----------------------------------------------------------------------------
- * ON   NOR WriteProtect        NAND WriteProtect       CS0 ExtNOR / CS2 NOR
- * OFF  NOR Not WriteProtect    NAND Not WriteProtect   CS0 NOR    / CS2 ExtNOR
- */
-
-/*
- * SCIFA5 (CN42)
- *
- * S38.3 = ON
- * S39.6 = ON
- * S43.1 = ON
- */
-
-/*
- * LCDC0 (CN3/CN4/CN7)
- *
- * S38.1 = OFF
- * S38.2 = OFF
- */
-
-/* Dummy supplies, where voltage doesn't matter */
-static struct regulator_consumer_supply dummy_supplies[] = {
-        REGULATOR_SUPPLY("vddvario", "smsc911x"),
-        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
-};
-
-/*
- * FPGA
- */
-#define IRQSR0          0x0020
-#define IRQSR1          0x0022
-#define IRQMR0          0x0030
-#define IRQMR1          0x0032
-#define BUSSWMR1        0x0070
-#define BUSSWMR2        0x0072
-#define BUSSWMR3        0x0074
-#define BUSSWMR4        0x0076
-
-#define LCDCR           0x10B4
-#define DEVRSTCR1       0x10D0
-#define DEVRSTCR2       0x10D2
-#define A1MDSR          0x10E0
-#define BVERR           0x1100
-
-/* FPGA IRQ */
-#define FPGA_IRQ_BASE           (512)
-#define FPGA_IRQ0               (FPGA_IRQ_BASE)
-#define FPGA_IRQ1               (FPGA_IRQ_BASE + 16)
-#define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
-static u16 bonito_fpga_read(u32 offset)
-{
-        return __raw_readw(IOMEM(0xf0003000) + offset);
-}
-
-static void bonito_fpga_write(u32 offset, u16 val)
-{
-        __raw_writew(val, IOMEM(0xf0003000) + offset);
-}
-
-static void bonito_fpga_irq_disable(struct irq_data *data)
-{
-        unsigned int irq = data->irq;
-        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
-        int shift = irq % 16;
-
-        bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
-}
-
-static void bonito_fpga_irq_enable(struct irq_data *data)
-{
-        unsigned int irq = data->irq;
-        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
-        int shift = irq % 16;
-
-        bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
-}
-
-static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
-        .name           = "bonito FPGA",
-        .irq_mask       = bonito_fpga_irq_disable,
-        .irq_unmask     = bonito_fpga_irq_enable,
-};
-
-static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
-{
-        u32 val =  bonito_fpga_read(IRQSR1) << 16 |
-                   bonito_fpga_read(IRQSR0);
-        u32 mask = bonito_fpga_read(IRQMR1) << 16 |
-                   bonito_fpga_read(IRQMR0);
-
-        int i;
-
-        val &= ~mask;
-
-        for (i = 0; i < 32; i++) {
-                if (!(val & (1 << i)))
-                        continue;
-
-                generic_handle_irq(FPGA_IRQ_BASE + i);
-        }
-}
-
-static void bonito_fpga_init(void)
-{
-        int i;
-
-        bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
-        bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
-
-        /* Device reset */
-        bonito_fpga_write(DEVRSTCR1,
-                   (1 << 2));   /* Eth */
-
-        /* FPGA irq require special handling */
-        for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
-                irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
-                                              handle_level_irq, "level");
-                set_irq_flags(i, IRQF_VALID); /* yuck */
-        }
-
-        irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
-        irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
-}
-
-/*
-* PMIC settings
-*
-* FIXME
-*
-* bonito board needs some settings by pmic which use i2c access.
-* pmic settings use device_initcall() here for use it.
-*/
-static __u8 *pmic_settings = NULL;
-static __u8 pmic_do_2A[] = {
-        0x1C, 0x09,
-        0x1A, 0x80,
-        0xff, 0xff,
-};
-
-static int __init pmic_init(void)
-{
-        struct i2c_adapter *a = i2c_get_adapter(0);
-        struct i2c_msg msg;
-        __u8 buf[2];
-        int i, ret;
-
-        if (!pmic_settings)
-                return 0;
-        if (!a)
-                return 0;
-
-        msg.addr        = 0x46;
-        msg.buf         = buf;
-        msg.len         = 2;
-        msg.flags       = 0;
-
-        for (i = 0; ; i += 2) {
-                buf[0] = pmic_settings[i + 0];
-                buf[1] = pmic_settings[i + 1];
-
-                if ((0xff == buf[0]) && (0xff == buf[1]))
-                        break;
-
-                ret = i2c_transfer(a, &msg, 1);
-                if (ret < 0) {
-                        pr_err("i2c transfer fail\n");
-                        break;
-                }
-        }
-
-        return 0;
-}
-device_initcall(pmic_init);
-
-/*
- * LCDC0
- */
-static const struct fb_videomode lcdc0_mode = {
-        .name           = "WVGA Panel",
-        .xres           = 800,
-        .yres           = 480,
-        .left_margin    = 88,
-        .right_margin   = 40,
-        .hsync_len      = 128,
-        .upper_margin   = 20,
-        .lower_margin   = 5,
-        .vsync_len      = 5,
-        .sync           = 0,
-};
-
-static struct sh_mobile_lcdc_info lcdc0_info = {
-        .clock_source   = LCDC_CLK_BUS,
-        .ch[0] = {
-                .chan                   = LCDC_CHAN_MAINLCD,
-                .fourcc = V4L2_PIX_FMT_RGB565,
-                .interface_type         = RGB24,
-                .clock_divider          = 5,
-                .flags                  = 0,
-                .lcd_modes              = &lcdc0_mode,
-                .num_modes              = 1,
-                .panel_cfg = {
-                        .width  = 152,
-                        .height = 91,
-                },
-        },
-};
-
-static struct resource lcdc0_resources[] = {
-        [0] = {
-                .name   = "LCDC0",
-                .start  = 0xfe940000,
-                .end    = 0xfe943fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0x0580),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device lcdc0_device = {
-        .name           = "sh_mobile_lcdc_fb",
-        .id             = 0,
-        .resource       = lcdc0_resources,
-        .num_resources  = ARRAY_SIZE(lcdc0_resources),
-        .dev    = {
-                .platform_data  = &lcdc0_info,
-                .coherent_dma_mask = ~0,
-        },
-};
-
-static const struct pinctrl_map lcdc0_pinctrl_map[] = {
-        /* LCD0 */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_data24_1", "lcd0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_lclk_1", "lcd0"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
-                                  "lcd0_sync", "lcd0"),
-};
-
-/*
- * SMSC 9221
- */
-static struct resource smsc_resources[] = {
-        [0] = {
-                .start          = 0x18010000,
-                .end            = 0x18011000 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = FPGA_ETH_IRQ,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct smsc911x_platform_config smsc_platdata = {
-        .flags          = SMSC911X_USE_16BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-
-static struct platform_device smsc_device = {
-        .name           = "smsc911x",
-        .dev  = {
-                .platform_data = &smsc_platdata,
-        },
-        .resource       = smsc_resources,
-        .num_resources  = ARRAY_SIZE(smsc_resources),
-};
-
-/*
- * core board devices
- */
-static struct platform_device *bonito_core_devices[] __initdata = {
-};
-
-/*
- * base board devices
- */
-static struct platform_device *bonito_base_devices[] __initdata = {
-        &lcdc0_device,
-        &smsc_device,
-};
-
-/*
- * map I/O
- */
-static struct map_desc bonito_io_desc[] __initdata = {
-        /*
-         * for FPGA (0x1800000-0x19ffffff)
-         * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
-         */
-        {
-                .virtual        = 0xf0003000,
-                .pfn            = __phys_to_pfn(0x18000000),
-                .length         = PAGE_SIZE * 2,
-                .type           = MT_DEVICE_NONSHARED
-        }
-};
-
-static void __init bonito_map_io(void)
-{
-        r8a7740_map_io();
-        iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
-}
-
-/*
- * board init
- */
-#define BIT_ON(sw, bit)         (sw & (1 << bit))
-#define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
-
-#define VCCQ1CR         IOMEM(0xE6058140)
-#define VCCQ1LCDCR      IOMEM(0xE6058186)
-
-static void __init bonito_init(void)
-{
-        u16 val;
-
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
-
-        r8a7740_pinmux_init();
-        bonito_fpga_init();
-
-        pmic_settings = pmic_do_2A;
-
-        /*
-         * core board settings
-         */
-
-#ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
-        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
-#endif
-
-        r8a7740_add_standard_devices();
-
-        platform_add_devices(bonito_core_devices,
-                             ARRAY_SIZE(bonito_core_devices));
-
-        /*
-         * base board settings
-         */
-        gpio_request_one(176, GPIOF_IN, NULL);
-        if (!gpio_get_value(176)) {
-                u16 bsw2;
-                u16 bsw3;
-                u16 bsw4;
-
-                /*
-                 * FPGA
-                 */
-                gpio_request(GPIO_FN_CS5B,              NULL);
-                gpio_request(GPIO_FN_CS6A,              NULL);
-                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
-                gpio_request(GPIO_FN_IRQ10,             NULL);
-
-                val = bonito_fpga_read(BVERR);
-                pr_info("bonito version: cpu %02x, base %02x\n",
-                        ((val >> 8) & 0xFF),
-                        ((val >> 0) & 0xFF));
-
-                bsw2 = bonito_fpga_read(BUSSWMR2);
-                bsw3 = bonito_fpga_read(BUSSWMR3);
-                bsw4 = bonito_fpga_read(BUSSWMR4);
-
-                /*
-                 * SCIFA5 (CN42)
-                 */
-                if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
-                    BIT_OFF(bsw3, 9) && /* S39.6 = ON */
-                    BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
-                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
-                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
-                }
-
-                /*
-                 * LCDC0 (CN3)
-                 */
-                if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
-                    BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
-                        pinctrl_register_mappings(lcdc0_pinctrl_map,
-                                                  ARRAY_SIZE(lcdc0_pinctrl_map));
-                        gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
-
-                        gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
-                                         NULL); /* LCDDON */
-
-                        /* backlight on */
-                        bonito_fpga_write(LCDCR, 1);
-
-                        /*  drivability Max */
-                        __raw_writew(0x00FF , VCCQ1LCDCR);
-                        __raw_writew(0xFFFF , VCCQ1CR);
-                }
-
-                platform_add_devices(bonito_base_devices,
-                                     ARRAY_SIZE(bonito_base_devices));
-        }
-}
-
-static void __init bonito_earlytimer_init(void)
-{
-        u16 val;
-        u8 md_ck = 0;
-
-        /* read MD_CK value */
-        val = bonito_fpga_read(A1MDSR);
-        if (val & (1 << 10))
-                md_ck |= MD_CK2;
-        if (val & (1 << 9))
-                md_ck |= MD_CK1;
-        if (val & (1 << 8))
-                md_ck |= MD_CK0;
-
-        r8a7740_clock_init(md_ck);
-        shmobile_earlytimer_init();
-}
-
-static void __init bonito_add_early_devices(void)
-{
-        r8a7740_add_early_devices();
-}
-
-MACHINE_START(BONITO, "bonito")
-        .map_io         = bonito_map_io,
-        .init_early     = bonito_add_early_devices,
-        .init_irq       = r8a7740_init_irq,
-        .handle_irq     = shmobile_handle_irq_intc,
-        .init_machine   = bonito_init,
-        .init_late      = shmobile_init_late,
-        .init_time      = bonito_earlytimer_init,
-MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index c016ccd92433..4368000e1127 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -56,7 +56,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
 
 static struct platform_device smsc91x_device = {
         .name   = "smsc911x",
-        .id     = 0,
+        .id     = -1,
         .dev    = {
                   .platform_data = &smsc911x_platdata,
                 },
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index aefa50d385b7..44055fe8a45c 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -79,7 +79,6 @@ static void __init kzm_init(void)
         sh73a0_pinmux_init();
 
         /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
         gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
 
         gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index e6b775a10aad..165483c9bee2 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -29,6 +29,7 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/as3711.h>
 #include <linux/mfd/tmio.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
@@ -606,6 +607,140 @@ static struct platform_device fsi_ak4648_device = {
 };
 
 /* I2C */
+
+/* StepDown1 is used to supply 1.315V to the CPU */
+static struct regulator_init_data as3711_sd1 = {
+        .constraints = {
+                .name = "1.315V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1315000,
+                .max_uV = 1335000,
+        },
+};
+
+/* StepDown2 is used to supply 1.8V to the CPU and to the board */
+static struct regulator_init_data as3711_sd2 = {
+        .constraints = {
+                .name = "1.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1800000,
+                .max_uV = 1800000,
+        },
+};
+
+/*
+ * StepDown3 is switched in parallel with StepDown2, seems to be off,
+ * according to read-back pre-set register values
+ */
+
+/* StepDown4 is used to supply 1.215V to the CPU and to the board */
+static struct regulator_init_data as3711_sd4 = {
+        .constraints = {
+                .name = "1.215V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1215000,
+                .max_uV = 1235000,
+        },
+};
+
+/* LDO1 is unused and unconnected */
+
+/* LDO2 is used to supply 2.8V to the CPU */
+static struct regulator_init_data as3711_ldo2 = {
+        .constraints = {
+                .name = "2.8V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO3 is used to supply 3.0V to the CPU */
+static struct regulator_init_data as3711_ldo3 = {
+        .constraints = {
+                .name = "3.0V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 3000000,
+                .max_uV = 3000000,
+        },
+};
+
+/* LDO4 is used to supply 2.8V to the board */
+static struct regulator_init_data as3711_ldo4 = {
+        .constraints = {
+                .name = "2.8V",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO5 is switched parallel to LDO4, also set to 2.8V */
+static struct regulator_init_data as3711_ldo5 = {
+        .constraints = {
+                .name = "2.8V #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 2800000,
+                .max_uV = 2800000,
+        },
+};
+
+/* LDO6 is unused and unconnected */
+
+/* LDO7 is used to supply 1.15V to the CPU */
+static struct regulator_init_data as3711_ldo7 = {
+        .constraints = {
+                .name = "1.15V CPU",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+
+/* LDO8 is switched parallel to LDO7, also set to 1.15V */
+static struct regulator_init_data as3711_ldo8 = {
+        .constraints = {
+                .name = "1.15V CPU #2",
+                .boot_on = 1,
+                .always_on = 1,
+                .min_uV = 1150000,
+                .max_uV = 1150000,
+        },
+};
+
+static struct as3711_platform_data as3711_pdata = {
+        .regulator      = {
+                .init_data      = {
+                        [AS3711_REGULATOR_SD_1] = &as3711_sd1,
+                        [AS3711_REGULATOR_SD_2] = &as3711_sd2,
+                        [AS3711_REGULATOR_SD_4] = &as3711_sd4,
+                        [AS3711_REGULATOR_LDO_2] = &as3711_ldo2,
+                        [AS3711_REGULATOR_LDO_3] = &as3711_ldo3,
+                        [AS3711_REGULATOR_LDO_4] = &as3711_ldo4,
+                        [AS3711_REGULATOR_LDO_5] = &as3711_ldo5,
+                        [AS3711_REGULATOR_LDO_7] = &as3711_ldo7,
+                        [AS3711_REGULATOR_LDO_8] = &as3711_ldo8,
+                },
+        },
+        .backlight      = {
+                .su2_fb = "sh_mobile_lcdc_fb.0",
+                .su2_max_uA = 36000,
+                .su2_feedback = AS3711_SU2_CURR_AUTO,
+                .su2_fbprot = AS3711_SU2_GPIO4,
+                .su2_auto_curr1 = true,
+                .su2_auto_curr2 = true,
+                .su2_auto_curr3 = true,
+        },
+};
+
 static struct pcf857x_platform_data pcf8575_pdata = {
         .gpio_base      = GPIO_PCF8575_BASE,
 };
@@ -625,6 +760,11 @@ static struct i2c_board_info i2c0_devices[] = {
                 I2C_BOARD_INFO("adxl34x", 0x1d),
                 .irq = irq_pin(26), /* IRQ26 */
         },
+        {
+                I2C_BOARD_INFO("as3711", 0x40),
+                .irq = intcs_evt2irq(0x3300), /* IRQ24 */
+                .platform_data = &as3711_pdata,
+        },
 };
 
 static struct i2c_board_info i2c1_devices[] = {
@@ -663,13 +803,13 @@ static unsigned long pin_pullup_conf[] = {
 
 static const struct pinctrl_map kzm_pinctrl_map[] = {
         /* FSIA (AK4648) */
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_mclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_sclk_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_in", "fsia"),
-        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2", "pfc-sh73a0",
                                   "fsia_data_out", "fsia"),
         /* I2C3 */
         PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
@@ -715,59 +855,6 @@ static const struct pinctrl_map kzm_pinctrl_map[] = {
                                   "usb_vbus", "usb"),
 };
 
-/*
- * FIXME
- *
- * This is quick hack for enabling LCDC backlight
- */
-static int __init as3711_enable_lcdc_backlight(void)
-{
-        struct i2c_adapter *a = i2c_get_adapter(0);
-        struct i2c_msg msg;
-        int i, ret;
-        __u8 magic[] = {
-                0x40, 0x2a,
-                0x43, 0x3c,
-                0x44, 0x3c,
-                0x45, 0x3c,
-                0x54, 0x03,
-                0x51, 0x00,
-                0x51, 0x01,
-                0xff, 0x00, /* wait */
-                0x43, 0xf0,
-                0x44, 0xf0,
-                0x45, 0xf0,
-        };
-
-        if (!of_machine_is_compatible("renesas,kzm9g"))
-                return 0;
-
-        if (!a)
-                return 0;
-
-        msg.addr        = 0x40;
-        msg.len         = 2;
-        msg.flags       = 0;
-
-        for (i = 0; i < ARRAY_SIZE(magic); i += 2) {
-                msg.buf = magic + i;
-
-                if (0xff == msg.buf[0]) {
-                        udelay(500);
-                        continue;
-                }
-
-                ret = i2c_transfer(a, &msg, 1);
-                if (ret < 0) {
-                        pr_err("i2c transfer fail\n");
-                        break;
-                }
-        }
-
-        return 0;
-}
-device_initcall(as3711_enable_lcdc_backlight);
-
 static void __init kzm_init(void)
 {
         regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
@@ -788,9 +875,6 @@ static void __init kzm_init(void)
         /* Touchscreen */
         gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 
-        /* enable SD */
-        gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
-
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index f587187a8603..d73e21d3ea8a 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -18,19 +18,83 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/irqchip.h>
 #include <linux/kernel.h>
+#include <linux/leds.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 #include <mach/r8a7790.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
+/* LEDS */
+static struct gpio_led lager_leds[] = {
+        {
+                .name           = "led8",
+                .gpio           = RCAR_GP_PIN(5, 17),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led7",
+                .gpio           = RCAR_GP_PIN(4, 23),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }, {
+                .name           = "led6",
+                .gpio           = RCAR_GP_PIN(4, 22),
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+};
+
+static __initdata struct gpio_led_platform_data lager_leds_pdata = {
+        .leds           = lager_leds,
+        .num_leds       = ARRAY_SIZE(lager_leds),
+};
+
+/* GPIO KEY */
+#define GPIO_KEY(c, g, d, ...) \
+        { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+
+static __initdata struct gpio_keys_button gpio_buttons[] = {
+        GPIO_KEY(KEY_4,         RCAR_GP_PIN(1, 28),     "SW2-pin4"),
+        GPIO_KEY(KEY_3,         RCAR_GP_PIN(1, 26),     "SW2-pin3"),
+        GPIO_KEY(KEY_2,         RCAR_GP_PIN(1, 24),     "SW2-pin2"),
+        GPIO_KEY(KEY_1,         RCAR_GP_PIN(1, 14),     "SW2-pin1"),
+};
+
+static __initdata struct gpio_keys_platform_data lager_keys_pdata = {
+        .buttons        = gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(gpio_buttons),
+};
+
+static const struct pinctrl_map lager_pinctrl_map[] = {
+        /* SCIF0 (CN19: DEBUG SERIAL0) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
+                                  "scif0_data", "scif0"),
+        /* SCIF1 (CN20: DEBUG SERIAL1) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
+                                  "scif1_data", "scif1"),
+};
+
 static void __init lager_add_standard_devices(void)
 {
         r8a7790_clock_init();
+
+        pinctrl_register_mappings(lager_pinctrl_map,
+                                  ARRAY_SIZE(lager_pinctrl_map));
+        r8a7790_pinmux_init();
+
         r8a7790_add_standard_devices();
+        platform_device_register_data(&platform_bus, "leds-gpio", -1,
+                                      &lager_leds_pdata,
+                                      sizeof(lager_leds_pdata));
+        platform_device_register_data(&platform_bus, "gpio-keys", -1,
+                                      &lager_keys_pdata,
+                                      sizeof(lager_keys_pdata));
 }
 
 static const char *lager_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index fa3407da682a..85f51a849a50 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -1309,6 +1309,49 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 static const struct pinctrl_map mackerel_pinctrl_map[] = {
+        /* ADXL34X */
+        PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
+                                  "intc_irq21", "intc"),
+        /* CEU */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_data_0_7", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_clk_0", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_sync", "ceu"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
+                                  "ceu_field", "ceu"),
+        /* FLCTL */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_data", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ce0", "flctl"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
+                                  "flctl_ctrl", "flctl"),
+        /* FSIA (AK4643) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_sclk_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_in", "fsia"),
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
+                                  "fsia_data_out", "fsia"),
+        /* FSIB (HDMI) */
+        PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
+                                  "fsib_mclk_in", "fsib"),
+        /* HDMI */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
+                                  "hdmi", "hdmi"),
+        /* LCDC */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_data24", "lcd"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
+                                  "lcd_sync", "lcd"),
+        /* SCIFA0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
+                                  "scifa0_data", "scifa0"),
+        /* SCIFA2 (GT-720F GPS module) */
+        PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
+                                  "scifa2_data", "scifa2"),
         /* SDHI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_data4", "sdhi0"),
@@ -1316,6 +1359,8 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi0_ctrl", "sdhi0"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
                                   "sdhi0_wp", "sdhi0"),
+        PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+                                  "intc_irq26_1", "intc"),
         /* SDHI1 */
 #if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
@@ -1334,6 +1379,25 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
                                   "sdhi2_data4", "sdhi2"),
         PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
                                   "sdhi2_ctrl", "sdhi2"),
+        /* SMSC911X */
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "bsc_cs5a", "bsc"),
+        PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
+                                  "intc_irq6_0", "intc"),
+        /* ST1232 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
+                                  "intc_irq7_0", "intc"),
+        /* TCA6416 */
+        PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
+                                  "intc_irq9_0", "intc"),
+        /* USBHS0 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
+                                  "usb0_vbus", "usb0"),
+        /* USBHS1 */
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_vbus", "usb1"),
+        PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
+                                  "usb1_otg_id_0", "usb1"),
 };
 
 #define GPIO_PORT9CR    IOMEM(0xE6051009)
@@ -1377,61 +1441,18 @@ static void __init mackerel_init(void)
                                   ARRAY_SIZE(mackerel_pinctrl_map));
         sh7372_pinmux_init();
 
-        /* enable SCIFA0 */
-        gpio_request(GPIO_FN_SCIFA0_TXD, NULL);
-        gpio_request(GPIO_FN_SCIFA0_RXD, NULL);
-
-        /* enable SMSC911X */
-        gpio_request(GPIO_FN_CS5A,      NULL);
-        gpio_request(GPIO_FN_IRQ6_39,   NULL);
-
-        /* LCDC */
-        gpio_request(GPIO_FN_LCDD23,   NULL);
-        gpio_request(GPIO_FN_LCDD22,   NULL);
-        gpio_request(GPIO_FN_LCDD21,   NULL);
-        gpio_request(GPIO_FN_LCDD20,   NULL);
-        gpio_request(GPIO_FN_LCDD19,   NULL);
-        gpio_request(GPIO_FN_LCDD18,   NULL);
-        gpio_request(GPIO_FN_LCDD17,   NULL);
-        gpio_request(GPIO_FN_LCDD16,   NULL);
-        gpio_request(GPIO_FN_LCDD15,   NULL);
-        gpio_request(GPIO_FN_LCDD14,   NULL);
-        gpio_request(GPIO_FN_LCDD13,   NULL);
-        gpio_request(GPIO_FN_LCDD12,   NULL);
-        gpio_request(GPIO_FN_LCDD11,   NULL);
-        gpio_request(GPIO_FN_LCDD10,   NULL);
-        gpio_request(GPIO_FN_LCDD9,    NULL);
-        gpio_request(GPIO_FN_LCDD8,    NULL);
-        gpio_request(GPIO_FN_LCDD7,    NULL);
-        gpio_request(GPIO_FN_LCDD6,    NULL);
-        gpio_request(GPIO_FN_LCDD5,    NULL);
-        gpio_request(GPIO_FN_LCDD4,    NULL);
-        gpio_request(GPIO_FN_LCDD3,    NULL);
-        gpio_request(GPIO_FN_LCDD2,    NULL);
-        gpio_request(GPIO_FN_LCDD1,    NULL);
-        gpio_request(GPIO_FN_LCDD0,    NULL);
-        gpio_request(GPIO_FN_LCDDISP,  NULL);
-        gpio_request(GPIO_FN_LCDDCK,   NULL);
-
         /* backlight, off by default */
         gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
 
         gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
 
         /* USBHS0 */
-        gpio_request(GPIO_FN_VBUS0_0, NULL);
         gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
         /* USBHS1 */
-        gpio_request(GPIO_FN_VBUS0_1, NULL);
         gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
-        gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
-        /* enable FSI2 port A (ak4643) */
-        gpio_request(GPIO_FN_FSIAIBT,   NULL);
-        gpio_request(GPIO_FN_FSIAILR,   NULL);
-        gpio_request(GPIO_FN_FSIAISLD,  NULL);
-        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+        /* FSI2 port A (ak4643) */
         gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
 
         gpio_request(9,  NULL);
@@ -1441,8 +1462,7 @@ static void __init mackerel_init(void)
 
         intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
-        /* setup FSI2 port B (HDMI) */
-        gpio_request(GPIO_FN_FSIBCK, NULL);
+        /* FSI2 port B (HDMI) */
         __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
 
         /* set SPU2 clock to 119.6 MHz */
@@ -1452,68 +1472,15 @@ static void __init mackerel_init(void)
                 clk_put(clk);
         }
 
-        /* enable Keypad */
-        gpio_request(GPIO_FN_IRQ9_42,   NULL);
+        /* Keypad */
         irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
-        /* enable Touchscreen */
-        gpio_request(GPIO_FN_IRQ7_40,   NULL);
+        /* Touchscreen */
         irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
-        /* enable Accelerometer */
-        gpio_request(GPIO_FN_IRQ21,     NULL);
+        /* Accelerometer */
         irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
-        /* SDHI0 PORT172 card-detect IRQ26 */
-        gpio_request(GPIO_FN_IRQ26_172, NULL);
-
-        /* FLCTL */
-        gpio_request(GPIO_FN_D0_NAF0, NULL);
-        gpio_request(GPIO_FN_D1_NAF1, NULL);
-        gpio_request(GPIO_FN_D2_NAF2, NULL);
-        gpio_request(GPIO_FN_D3_NAF3, NULL);
-        gpio_request(GPIO_FN_D4_NAF4, NULL);
-        gpio_request(GPIO_FN_D5_NAF5, NULL);
-        gpio_request(GPIO_FN_D6_NAF6, NULL);
-        gpio_request(GPIO_FN_D7_NAF7, NULL);
-        gpio_request(GPIO_FN_D8_NAF8, NULL);
-        gpio_request(GPIO_FN_D9_NAF9, NULL);
-        gpio_request(GPIO_FN_D10_NAF10, NULL);
-        gpio_request(GPIO_FN_D11_NAF11, NULL);
-        gpio_request(GPIO_FN_D12_NAF12, NULL);
-        gpio_request(GPIO_FN_D13_NAF13, NULL);
-        gpio_request(GPIO_FN_D14_NAF14, NULL);
-        gpio_request(GPIO_FN_D15_NAF15, NULL);
-        gpio_request(GPIO_FN_FCE0, NULL);
-        gpio_request(GPIO_FN_WE0_FWE, NULL);
-        gpio_request(GPIO_FN_FRB, NULL);
-        gpio_request(GPIO_FN_A4_FOE, NULL);
-        gpio_request(GPIO_FN_A5_FCDE, NULL);
-        gpio_request(GPIO_FN_RD_FSC, NULL);
-
-        /* enable GPS module (GT-720F) */
-        gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
-        gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
-
-        /* CEU */
-        gpio_request(GPIO_FN_VIO_CLK, NULL);
-        gpio_request(GPIO_FN_VIO_VD, NULL);
-        gpio_request(GPIO_FN_VIO_HD, NULL);
-        gpio_request(GPIO_FN_VIO_FIELD, NULL);
-        gpio_request(GPIO_FN_VIO_CKO, NULL);
-        gpio_request(GPIO_FN_VIO_D7, NULL);
-        gpio_request(GPIO_FN_VIO_D6, NULL);
-        gpio_request(GPIO_FN_VIO_D5, NULL);
-        gpio_request(GPIO_FN_VIO_D4, NULL);
-        gpio_request(GPIO_FN_VIO_D3, NULL);
-        gpio_request(GPIO_FN_VIO_D2, NULL);
-        gpio_request(GPIO_FN_VIO_D1, NULL);
-        gpio_request(GPIO_FN_VIO_D0, NULL);
-
-        /* HDMI */
-        gpio_request(GPIO_FN_HDMI_HPD, NULL);
-        gpio_request(GPIO_FN_HDMI_CEC, NULL);
-
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index b9594e911ce7..a7d1010505bf 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -28,6 +28,7 @@
 #include <linux/leds.h>
 #include <linux/dma-mapping.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
@@ -36,10 +37,6 @@
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ehci_pdriver.h>
-#include <linux/usb/ohci_pdriver.h>
-#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
 #include <mach/common.h>
@@ -60,6 +57,8 @@ static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vdd33a", "smsc911x"),
 };
 
+static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
+
 /* SMSC LAN89218 */
 static struct resource smsc911x_resources[] = {
         [0] = {
@@ -68,7 +67,7 @@ static struct resource smsc911x_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = gic_iid(0x3c), /* IRQ 1 */
+                .start          = irq_pin(1), /* IRQ 1 */
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -149,39 +148,19 @@ static struct platform_device hspi_device = {
         .num_resources  = ARRAY_SIZE(hspi_resources),
 };
 
-/* USB PHY */
-static struct resource usb_phy_resources[] = {
-        [0] = {
-                .start          = 0xffe70000,
-                .end            = 0xffe70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start          = 0xfff70000,
-                .end            = 0xfff70900 - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device usb_phy_device = {
-        .name           = "rcar_usb_phy",
-        .resource       = usb_phy_resources,
-        .num_resources  = ARRAY_SIZE(usb_phy_resources),
-};
-
 /* LEDS */
 static struct gpio_led marzen_leds[] = {
         {
                 .name           = "led2",
-                .gpio           = 157,
+                .gpio           = RCAR_GP_PIN(4, 29),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led3",
-                .gpio           = 158,
+                .gpio           = RCAR_GP_PIN(4, 30),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         }, {
                 .name           = "led4",
-                .gpio           = 159,
+                .gpio           = RCAR_GP_PIN(4, 31),
                 .default_state  = LEDS_GPIO_DEFSTATE_ON,
         },
 };
@@ -204,161 +183,9 @@ static struct platform_device *marzen_devices[] __initdata = {
         &sdhi0_device,
         &thermal_device,
         &hspi_device,
-        &usb_phy_device,
         &leds_device,
 };
 
-/* USB */
-static struct usb_phy *phy;
-static int usb_power_on(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return PTR_ERR(phy);
-
-        pm_runtime_enable(&pdev->dev);
-        pm_runtime_get_sync(&pdev->dev);
-
-        usb_phy_init(phy);
-
-        return 0;
-}
-
-static void usb_power_off(struct platform_device *pdev)
-{
-        if (IS_ERR(phy))
-                return;
-
-        usb_phy_shutdown(phy);
-
-        pm_runtime_put_sync(&pdev->dev);
-        pm_runtime_disable(&pdev->dev);
-}
-
-static struct usb_ehci_pdata ehcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-
-static struct resource ehci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70000,
-                .end    = 0xffe70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ehci0_device = {
-        .name   = "ehci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci0_resources),
-        .resource       = ehci0_resources,
-};
-
-static struct resource ehci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70000,
-                .end    = 0xfff70400 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ehci1_device = {
-        .name   = "ehci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ehcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ehci1_resources),
-        .resource       = ehci1_resources,
-};
-
-static struct usb_ohci_pdata ohcix_pdata = {
-        .power_on       = usb_power_on,
-        .power_off      = usb_power_off,
-        .power_suspend  = usb_power_off,
-};
-
-static struct resource ohci0_resources[] = {
-        [0] = {
-                .start  = 0xffe70400,
-                .end    = 0xffe70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4c),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci0_device = {
-        .name   = "ohci-platform",
-        .id     = 0,
-        .dev    = {
-                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci0_resources),
-        .resource       = ohci0_resources,
-};
-
-static struct resource ohci1_resources[] = {
-        [0] = {
-                .start  = 0xfff70400,
-                .end    = 0xfff70800 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x4d),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci1_device = {
-        .name   = "ohci-platform",
-        .id     = 1,
-        .dev    = {
-                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
-                .coherent_dma_mask      = 0xffffffff,
-                .platform_data          = &ohcix_pdata,
-        },
-        .num_resources  = ARRAY_SIZE(ohci1_resources),
-        .resource       = ohci1_resources,
-};
-
-static struct platform_device *marzen_late_devices[] __initdata = {
-        &ehci0_device,
-        &ehci1_device,
-        &ohci0_device,
-        &ohci1_device,
-};
-
-void __init marzen_init_late(void)
-{
-        /* get usb phy */
-        phy = usb_get_phy(USB_PHY_TYPE_USB2);
-
-        shmobile_init_late();
-        platform_add_devices(marzen_late_devices,
-                             ARRAY_SIZE(marzen_late_devices));
-}
-
 static const struct pinctrl_map marzen_pinctrl_map[] = {
         /* HSPI0 */
         PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
@@ -404,8 +231,10 @@ static void __init marzen_init(void)
         pinctrl_register_mappings(marzen_pinctrl_map,
                                   ARRAY_SIZE(marzen_pinctrl_map));
         r8a7779_pinmux_init();
+        r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
 
         r8a7779_add_standard_devices();
+        r8a7779_add_usb_phy_device(&usb_phy_platform_data);
         platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
 }
 
@@ -416,6 +245,6 @@ MACHINE_START(MARZEN, "marzen")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = r8a7779_init_irq,
         .init_machine   = marzen_init,
-        .init_late      = marzen_init_late,
+        .init_late      = r8a7779_init_late,
         .init_time      = r8a7779_earlytimer_init,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index e710c00c3822..5f7fe628b8a1 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -22,15 +22,44 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x270
 
-#define MPCKCR 0xe6150080
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR5 0xe6150144
 
+#define FRQCRA          0xE6150000
+#define FRQCRB          0xE6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000C
+#define VCLKCR3         0xE615001C
+#define VCLKCR4         0xE6150014
+#define VCLKCR5         0xE6150034
+#define ZBCKCR          0xE6150010
+#define SD0CKCR         0xE6150074
+#define SD1CKCR         0xE6150078
+#define SD2CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define FSIACKCR        0xE6150018
+#define FSIBCKCR        0xE6150090
+#define MPCKCR          0xe6150080
+#define SPUVCKCR        0xE6150094
+#define HSICKCR         0xE615026C
+#define M4CKCR          0xE6150098
+#define PLLECR          0xE61500D0
+#define PLL1CR          0xE6150028
+#define PLL2CR          0xE615002C
+#define PLL2SCR         0xE61501F4
+#define PLL2HCR         0xE61501E4
+#define CKSCR           0xE61500C0
+
+#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
@@ -51,29 +80,327 @@ static struct clk extal2_clk = {
         .mapping        = &cpg_mapping,
 };
 
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
+};
+
+SH_CLK_RATIO(div2,      1, 2);
+SH_CLK_RATIO(div4,      1, 4);
+
+SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
+SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
+SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
+
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
+/*
+ *              PLL clocks
+ */
+static struct clk *pll_parent_main[] = {
+        [0] = &main_clk,
+        [1] = &main_div2_clk
+};
+
+static struct clk *pll_parent_main_extal[8] = {
+        [0] = &main_div2_clk,
+        [1] = &extal2_div2_clk,
+        [3] = &extal2_div4_clk,
+        [4] = &main_clk,
+        [5] = &extal2_clk,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+
+        if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
+                mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
+
+        return clk->parent->rate * mult;
+}
+
+static int pll_set_parent(struct clk *clk, struct clk *parent)
+{
+        u32 val;
+        int i, ret;
+
+        if (!clk->parent_table || !clk->parent_num)
+                return -EINVAL;
+
+        /* Search the parent */
+        for (i = 0; i < clk->parent_num; i++)
+                if (clk->parent_table[i] == parent)
+                        break;
+
+        if (i == clk->parent_num)
+                return -ENODEV;
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        val = ioread32(clk->mapped_reg) &
+                ~(((1 << clk->src_width) - 1) << clk->src_shift);
+
+        iowrite32(val | i << clk->src_shift, clk->mapped_reg);
+
+        return 0;
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+        .set_parent     = pll_set_parent,
+};
+
+#define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
+        static struct clk name = {                      \
+                .ops            = &pll_clk_ops,         \
+                .flags          = CLK_ENABLE_ON_INIT,   \
+                .parent         = p,                    \
+                .parent_table   = pt,                   \
+                .parent_num     = ARRAY_SIZE(pt),       \
+                .src_width      = w,                    \
+                .src_shift      = s,                    \
+                .enable_reg     = (void __iomem *)reg,  \
+                .enable_bit     = e,                    \
+                .mapping        = &cpg_mapping,         \
+        }
+
+PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
+PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
+PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
+PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
+
+SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
+
 static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
+        &extal1_div2_clk,
         &extal2_clk,
+        &extal2_div2_clk,
+        &extal2_div4_clk,
+        &main_clk,
+        &main_div2_clk,
+        &fsiack_clk,
+        &fsibck_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll2_clk,
+        &pll2s_clk,
+        &pll2h_clk,
+};
+
+/* DIV4 */
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = ioread32(CPG_MAP(FRQCRB));
+        value |= (1 << 31);
+        iowrite32(value, CPG_MAP(FRQCRB));
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors       = divisors,
+        .nr_divisors    = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick           = div4_kick,
+};
+
+enum {
+        DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
+        DIV4_ZX, DIV4_ZS, DIV4_HP,
+        DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
+        [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
+        [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
+        [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
+        [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 };
 
 enum {
+        DIV6_ZB,
+        DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
+        DIV6_NR };
+
+static struct clk *div6_parents[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [3] = &extal2_clk,
+        [4] = &main_div2_clk,
+        [6] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsiack_clk,
+};
+
+static struct clk *fsib_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &fsibck_clk,
+};
+
+static struct clk *mp_parents[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2s_clk,
+        [2] = &extal2_clk,
+        [3] = &extal2_clk,
+};
+
+static struct clk *m4_parents[2] = {
+        [0] = &pll2s_clk,
+};
+
+static struct clk *hsi_parents[4] = {
+        [0] = &pll2h_clk,
+        [1] = &pll1_div2_clk,
+        [3] = &pll2s_clk,
+};
+
+/*** FIXME ***
+ * SH_CLK_DIV6_EXT() macro doesn't care .mapping
+ * but, it is necessary on R-Car (= ioremap() base CPG)
+ * The difference between
+ * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
+ * is only .mapping
+ */
+#define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
+                            _num_parents, _src_shift, _src_width)       \
+{                                                                       \
+        .enable_reg     = (void __iomem *)_reg,                         \
+        .enable_bit     = 0, /* unused */                               \
+        .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
+        .div_mask       = SH_CLK_DIV6_MSK,                              \
+        .parent_table   = _parents,                                     \
+        .parent_num     = _num_parents,                                 \
+        .src_shift      = _src_shift,                                   \
+        .src_width      = _src_width,                                   \
+        .mapping        = &cpg_mapping,                                 \
+}
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+                                div6_parents, 2, 7, 1),
+        [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
+                                div6_parents, 2, 6, 2),
+        [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
+                                div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
+                                fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
+                                fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+        [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+        /* pll2s will be selected always for M4 */
+        [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
+                                m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
+        [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
+                                hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
+        [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
+                                mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
+};
+
+/* MSTP */
+enum {
         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP305,
         MSTP522,
         MSTP_NR
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
-        [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
-        [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
-        [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
-        [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
-        [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
+        [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
+        [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main clock */
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
+
+        /* pll clock */
+        CLKDEV_CON_ID("pll1",                   &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
+        CLKDEV_CON_ID("pll2",                   &pll2_clk),
+        CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
+        CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
+        CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
+        CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
+        CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
+        CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
+        CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
+        CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
+        CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
+        CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
+        CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
+        CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -81,6 +408,16 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
 
         /* for DT */
         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -88,22 +425,40 @@ static struct clk_lookup lookups[] = {
 
 void __init r8a73a4_clock_init(void)
 {
-        void __iomem *cpg_base, *reg;
+        void __iomem *reg;
         int k, ret = 0;
+        u32 ckscr;
+
+        reg = ioremap_nocache(CKSCR, PAGE_SIZE);
+        BUG_ON(!reg);
+        ckscr = ioread32(reg);
+        iounmap(reg);
 
-        /* fix MPCLK to EXTAL2 for now.
-         * this is needed until more detailed clock topology is supported
-         */
-        cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
-        BUG_ON(!cpg_base);
-        reg = cpg_base + (MPCKCR - CPG_BASE);
-        iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
-        iounmap(cpg_base);
+        switch ((ckscr >> 28) & 0x3) {
+        case 0:
+                main_clk.parent = &extal1_clk;
+                break;
+        case 1:
+                main_clk.parent = &extal1_div2_clk;
+                break;
+        case 2:
+                main_clk.parent = &extal2_clk;
+                break;
+        case 3:
+                main_clk.parent = &extal2_div2_clk;
+                break;
+        }
 
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index c0d39aa6de50..7fd32d604e34 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -266,7 +266,7 @@ static struct clk fsiack_clk = {
 static struct clk fsibck_clk = {
 };
 
-struct clk *main_clks[] = {
+static struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
         &extal2_clk,
@@ -317,7 +317,7 @@ enum {
         DIV4_NR
 };
 
-struct clk div4_clks[DIV4_NR] = {
+static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
         [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
@@ -461,7 +461,7 @@ enum {
 
         MSTP329, MSTP328, MSTP323, MSTP320,
         MSTP314, MSTP313, MSTP312,
-        MSTP309,
+        MSTP309, MSTP304,
 
         MSTP416, MSTP415, MSTP407, MSTP406,
 
@@ -499,6 +499,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3, 12, 0), /* MMC */
         [MSTP309] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR3,  9, 0), /* GEther */
+        [MSTP304] = SH_CLK_MSTP32(&div4_clks[DIV4_CP],  SMSTPCR3,  4, 0), /* TPU0 */
 
         [MSTP416] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 16, 0), /* USBHOST */
         [MSTP415] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR4, 15, 0), /* SDHI2 */
@@ -551,6 +552,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
         CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
@@ -584,6 +586,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
         CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
         CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+        CLKDEV_DEV_ID("e6c20000.i2c",           &mstp_clks[MSTP323]),
         CLKDEV_DEV_ID("renesas_usbhs",          &mstp_clks[MSTP320]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0",       &mstp_clks[MSTP314]),
         CLKDEV_DEV_ID("e6850000.sdhi",          &mstp_clks[MSTP314]),
@@ -592,6 +595,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("e6bd0000.mmcif",         &mstp_clks[MSTP312]),
         CLKDEV_DEV_ID("sh-eth",                 &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("renesas_tpu_pwm",        &mstp_clks[MSTP304]),
 
         CLKDEV_DEV_ID("sh_mobile_sdhi.2",       &mstp_clks[MSTP415]),
         CLKDEV_DEV_ID("e6870000.sdhi",          &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index cd6855290b1f..53798e5037d7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -23,9 +23,23 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
+ *     19      18      12      11                      (HMz)   (MHz)   (MHz)
+ *----------------------------------------------------------------------------
+ *     1       0       0       0       x21     x21     38.00   800     800
+ *     1       0       0       1       x24     x24     33.33   800     800
+ *     1       0       1       0       x28     x28     28.50   800     800
+ *     1       0       1       1       x32     x32     25.00   800     800
+ *     1       1       0       1       x24     x21     33.33   800     700
+ *     1       1       1       0       x28     x21     28.50   800     600
+ *     1       1       1       1       x32     x24     25.00   800     600
+ */
+
 #include <linux/io.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
 #define MSTPCR0         IOMEM(0xffc80030)
@@ -37,6 +51,9 @@
 #define MSTPCR4         IOMEM(0xffc80050)
 #define MSTPCR5         IOMEM(0xffc80054)
 #define MSTPCR6         IOMEM(0xffc80058)
+#define MODEMR          0xFFCC0020
+
+#define MD(nr)  BIT(nr)
 
 /* ioremap() through clock mapping mandatory to avoid
  * collision with ARM coherent DMA virtual memory range.
@@ -47,37 +64,94 @@ static struct clk_mapping cpg_mapping = {
         .len    = 0x80,
 };
 
-static struct clk clkp = {
-        .rate   = 62500000, /* FIXME: shortcut */
-        .flags  = CLK_ENABLE_ON_INIT,
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7778_clock_init() */
         .mapping = &cpg_mapping,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7778_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
+SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
+SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
+
 static struct clk *main_clks[] = {
-        &clkp,
+        &extal_clk,
+        &plla_clk,
+        &pllb_clk,
+        &i_clk,
+        &s_clk,
+        &s1_clk,
+        &s3_clk,
+        &s4_clk,
+        &b_clk,
+        &out_clk,
+        &p_clk,
+        &g_clk,
+        &z_clk,
 };
 
 enum {
+        MSTP331,
+        MSTP323, MSTP322, MSTP321,
         MSTP114,
-        MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP100,
+        MSTP030,
+        MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
         MSTP016, MSTP015,
+        MSTP007,
         MSTP_NR };
 
 static struct clk mstp_clks[MSTP_NR] = {
-        [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
-        [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
-        [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
-        [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
-        [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
-        [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
-        [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
-        [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
-        [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
+        [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
+        [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
+        [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
+        [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
+        [MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1,  0, 0), /* USB0/1 */
+        [MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
+        [MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
+        [MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
+        [MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
+        [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0,  7, 0), /* HSPI */
 };
 
 static struct clk_lookup lookups[] = {
+        /* main */
+        CLKDEV_CON_ID("shyway_clk",     &s_clk),
+        CLKDEV_CON_ID("peripheral_clk", &p_clk),
+
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
+        CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
+        CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
+        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
+        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
+        CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
+        CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
@@ -86,12 +160,93 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
+        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
+        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
+        CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
 };
 
 void __init r8a7778_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
+        case MD(19):
+                extal_clk.rate = 38000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        case MD(19) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
+                break;
+        case MD(19) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
+                break;
+        case MD(19) | MD(18) | MD(11):
+                extal_clk.rate = 33333333;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12):
+                extal_clk.rate = 28500000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
+                break;
+        case MD(19) | MD(18) | MD(12) | MD(11):
+                extal_clk.rate = 25000000;
+                SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
+                SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
+                break;
+        default:
+                BUG();
+        }
+
+        if (mode & MD(1)) {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        } else {
+                SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
+                SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
+                SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
+                SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
+                SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
+                SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
+                if (mode & MD(2)) {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
+                } else {
+                        SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
+                        SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
+                }
+        }
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 31d5cd4d9787..9daeb8c37483 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -112,7 +112,7 @@ static struct clk *main_clks[] = {
 };
 
 enum { MSTP323, MSTP322, MSTP321, MSTP320,
-        MSTP115, MSTP114,
+        MSTP116, MSTP115, MSTP114,
         MSTP103, MSTP101, MSTP100,
         MSTP030,
         MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
@@ -125,6 +125,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
         [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
         [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
+        [MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */
         [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
         [MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */
         [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */
@@ -161,6 +162,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
 
         /* MSTP32 clocks */
+        CLKDEV_DEV_ID("rcar-pcie", &mstp_clks[MSTP116]), /* PCIe */
         CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
         CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index bad9bf2e34d6..5d71313df52d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -22,48 +22,228 @@
 #include <linux/kernel.h>
 #include <linux/sh_clk.h>
 #include <linux/clkdev.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 
+/*
+ *   MD         EXTAL           PLL0    PLL1    PLL3
+ * 14 13 19     (MHz)           *1      *1
+ *---------------------------------------------------
+ * 0  0  0      15 x 1          x172/2  x208/2  x106
+ * 0  0  1      15 x 1          x172/2  x208/2  x88
+ * 0  1  0      20 x 1          x130/2  x156/2  x80
+ * 0  1  1      20 x 1          x130/2  x156/2  x66
+ * 1  0  0      26 / 2          x200/2  x240/2  x122
+ * 1  0  1      26 / 2          x200/2  x240/2  x102
+ * 1  1  0      30 / 2          x172/2  x208/2  x106
+ * 1  1  1      30 / 2          x172/2  x208/2  x88
+ *
+ * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
+ *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
+ */
+
+#define MD(nr)  (1 << nr)
+
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
 
 #define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
 #define SMSTPCR7 0xe615014c
 
+#define MODEMR          0xE6160060
+#define SDCKCR          0xE6150074
+#define SD2CKCR         0xE6150078
+#define SD3CKCR         0xE615007C
+#define MMC0CKCR        0xE6150240
+#define MMC1CKCR        0xE6150244
+#define SSPCKCR         0xE6150248
+#define SSPRSCKCR       0xE615024C
+
 static struct clk_mapping cpg_mapping = {
         .phys   = CPG_BASE,
         .len    = CPG_LEN,
 };
 
-static struct clk p_clk = {
-        .rate   = 65000000, /* shortcut for now */
+static struct clk extal_clk = {
+        /* .rate will be updated on r8a7790_clock_init() */
         .mapping        = &cpg_mapping,
 };
 
-static struct clk mp_clk = {
-        .rate   = 52000000,  /* shortcut for now */
-        .mapping        = &cpg_mapping,
+static struct sh_clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+
+static struct clk main_clk = {
+        /* .parent will be set r8a73a4_clock_init */
+        .ops    = &followparent_clk_ops,
 };
 
+/*
+ * clock ratio of these clock will be updated
+ * on r8a7790_clock_init()
+ */
+SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
+SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
+
+/* fixed ratio clock */
+SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
+SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
+
+SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
+SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
+SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
+SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
+SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
+SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
+SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
+SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
+
+SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
+SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
+SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
+
 static struct clk *main_clks[] = {
+        &extal_clk,
+        &extal_div2_clk,
+        &main_clk,
+        &pll1_clk,
+        &pll1_div2_clk,
+        &pll3_clk,
+        &lb_clk,
+        &qspi_clk,
+        &zg_clk,
+        &zx_clk,
+        &zs_clk,
+        &hp_clk,
+        &i_clk,
+        &b_clk,
         &p_clk,
+        &cl_clk,
+        &m2_clk,
+        &imp_clk,
+        &rclk_clk,
+        &oscclk_clk,
+        &zb3_clk,
+        &zb3d2_clk,
+        &ddr_clk,
         &mp_clk,
+        &cp_clk,
+};
+
+/* SDHI (DIV4) clock */
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum {
+        DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
+};
+
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
+        [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
+        [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
+};
+
+/* DIV6 clocks */
+enum {
+        DIV6_SD2, DIV6_SD3,
+        DIV6_MMC0, DIV6_MMC1,
+        DIV6_SSP, DIV6_SSPRS,
+        DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+        [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
+        [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
+        [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
+        [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
+        [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
+};
+
+/* MSTP */
+enum {
+        MSTP721, MSTP720,
+        MSTP717, MSTP716,
+        MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
+        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
+        MSTP_NR
 };
 
-enum { MSTP721, MSTP720,
-        MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
 static struct clk mstp_clks[MSTP_NR] = {
         [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
         [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
+        [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
+        [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
+        [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
+        [MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
+        [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
+        [MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
         [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
         [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
         [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
         [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
         [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
         [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
+        [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
+        [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
 };
 
 static struct clk_lookup lookups[] = {
+
+        /* main clocks */
+        CLKDEV_CON_ID("extal",          &extal_clk),
+        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
+        CLKDEV_CON_ID("main",           &main_clk),
+        CLKDEV_CON_ID("pll1",           &pll1_clk),
+        CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
+        CLKDEV_CON_ID("pll3",           &pll3_clk),
+        CLKDEV_CON_ID("zg",             &zg_clk),
+        CLKDEV_CON_ID("zx",             &zx_clk),
+        CLKDEV_CON_ID("zs",             &zs_clk),
+        CLKDEV_CON_ID("hp",             &hp_clk),
+        CLKDEV_CON_ID("i",              &i_clk),
+        CLKDEV_CON_ID("b",              &b_clk),
+        CLKDEV_CON_ID("lb",             &lb_clk),
+        CLKDEV_CON_ID("p",              &p_clk),
+        CLKDEV_CON_ID("cl",             &cl_clk),
+        CLKDEV_CON_ID("m2",             &m2_clk),
+        CLKDEV_CON_ID("imp",            &imp_clk),
+        CLKDEV_CON_ID("rclk",           &rclk_clk),
+        CLKDEV_CON_ID("oscclk",         &oscclk_clk),
+        CLKDEV_CON_ID("zb3",            &zb3_clk),
+        CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
+        CLKDEV_CON_ID("ddr",            &ddr_clk),
+        CLKDEV_CON_ID("mp",             &mp_clk),
+        CLKDEV_CON_ID("qspi",           &qspi_clk),
+        CLKDEV_CON_ID("cp",             &cp_clk),
+
+        /* DIV4 */
+        CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
+
+        /* DIV6 */
+        CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
+        CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
+
+        /* MSTP */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
@@ -72,16 +252,77 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
+        CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
+        CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
+        CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
+        CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
+        CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
+        CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
+        CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
+        CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
+        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 };
 
+#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
+        extal_clk.rate  = e * 1000 * 1000;                      \
+        main_clk.parent = m;                                    \
+        SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
+        if (mode & MD(19))                                      \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
+        else                                                    \
+                SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
+
+
 void __init r8a7790_clock_init(void)
 {
+        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode;
         int k, ret = 0;
 
+        BUG_ON(!modemr);
+        mode = ioread32(modemr);
+        iounmap(modemr);
+
+        switch (mode & (MD(14) | MD(13))) {
+        case 0:
+                R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
+                break;
+        case MD(13):
+                R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
+                break;
+        case MD(14):
+                R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
+                break;
+        case MD(13) | MD(14):
+                R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
+                break;
+        }
+
+        if (mode & (MD(18)))
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
+        else
+                SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
+
+        if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
+        else
+                SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
         if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+        if (!ret)
                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7e105932c09d..5390c6bbbc02 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -142,15 +142,15 @@ static void pllc2_table_rebuild(struct clk *clk)
         /* Initialise PLLC2 frequency table */
         for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
                 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
-                pllc2_freq_table[i].index = i;
+                pllc2_freq_table[i].driver_data = i;
         }
 
         /* This is a special entry - switching PLL off makes it a repeater */
         pllc2_freq_table[i].frequency = clk->parent->rate;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
 
         pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
-        pllc2_freq_table[i].index = i;
+        pllc2_freq_table[i].driver_data = i;
 }
 
 static unsigned long pllc2_recalc(struct clk *clk)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 784fbaa4cc55..d9fd0336b910 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -228,6 +228,11 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 
 static struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
+        /*
+         * ZG clock is dividing PLL0 frequency to supply SGX. Make sure not to
+         * exceed maximum frequencies of 201.5MHz for VDD_DVFS=1.175 and
+         * 239.2MHz for VDD_DVFS=1.315V.
+         */
         [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
         [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
@@ -252,6 +257,101 @@ static struct clk twd_clk = {
         .ops = &twd_clk_ops,
 };
 
+static struct sh_clk_ops zclk_ops, kicker_ops;
+static const struct sh_clk_ops *div4_clk_ops;
+
+static int zclk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret;
+
+        if (!clk->parent || !__clk_get(clk->parent))
+                return -ENODEV;
+
+        if (readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        if (rate == clk_get_rate(clk->parent)) {
+                /* 1:1 - switch off divider */
+                __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB);
+                /* nullify the divider to prepare for the next time */
+                ret = div4_clk_ops->set_rate(clk, rate / 2);
+                if (!ret)
+                        ret = frqcr_kick();
+                if (ret > 0)
+                        ret = 0;
+        } else {
+                /* Enable the divider */
+                __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB);
+
+                ret = frqcr_kick();
+                if (ret >= 0)
+                        /*
+                         * set the divider - call the DIV4 method, it will kick
+                         * FRQCRB too
+                         */
+                        ret = div4_clk_ops->set_rate(clk, rate);
+                if (ret < 0)
+                        goto esetrate;
+        }
+
+esetrate:
+        __clk_put(clk->parent);
+        return ret;
+}
+
+static long zclk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div_freq = div4_clk_ops->round_rate(clk, rate),
+                parent_freq = clk_get_rate(clk->parent);
+
+        if (rate > div_freq && abs(parent_freq - rate) < rate - div_freq)
+                return parent_freq;
+
+        return div_freq;
+}
+
+static unsigned long zclk_recalc(struct clk *clk)
+{
+        /*
+         * Must recalculate frequencies in case PLL0 has been changed, even if
+         * the divisor is unused ATM!
+         */
+        unsigned long div_freq = div4_clk_ops->recalc(clk);
+
+        if (__raw_readl(FRQCRB) & (1 << 28))
+                return div_freq;
+
+        return clk_get_rate(clk->parent);
+}
+
+static int kicker_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (__raw_readl(FRQCRB) & (1 << 31))
+                return -EBUSY;
+
+        return div4_clk_ops->set_rate(clk, rate);
+}
+
+static void div4_clk_extend(void)
+{
+        int i;
+
+        div4_clk_ops = div4_clks[0].ops;
+
+        /* Add a kicker-busy check before changing the rate */
+        kicker_ops = *div4_clk_ops;
+        /* We extend the DIV4 clock with a 1:1 pass-through case */
+        zclk_ops = *div4_clk_ops;
+
+        kicker_ops.set_rate = kicker_set_rate;
+        zclk_ops.set_rate = zclk_set_rate;
+        zclk_ops.round_rate = zclk_round_rate;
+        zclk_ops.recalc = zclk_recalc;
+
+        for (i = 0; i < DIV4_NR; i++)
+                div4_clks[i].ops = i == DIV4_Z ? &zclk_ops : &kicker_ops;
+}
+
 enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
         DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
         DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -450,7 +550,7 @@ static struct clk *late_main_clks[] = {
 };
 
 enum { MSTP001,
-        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
+        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP112, MSTP100,
         MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
         MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
@@ -471,6 +571,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
         [MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP112] = MSTP(&div4_clks[DIV4_ZG], SMSTPCR1, 12, 0), /* SGX */
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
@@ -513,6 +614,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("r_clk", &r_clk),
         CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
 
+        /* DIV4 clocks */
+        CLKDEV_DEV_ID("cpufreq-cpu0", &div4_clks[DIV4_Z]),
+
         /* DIV6 clocks */
         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
@@ -604,8 +708,11 @@ void __init sh73a0_clock_init(void)
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
-        if (!ret)
+        if (!ret) {
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+                if (!ret)
+                        div4_clk_extend();
+        }
 
         if (!ret)
                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 7d113f898e7f..6f9865467258 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -25,31 +25,24 @@
 
         __CPUINIT
 /*
- * Reset vector for secondary CPUs.
+ * Boot code for secondary CPUs.
  *
  * First we turn on L1 cache coherency for our CPU. Then we jump to
  * shmobile_invalidate_start that invalidates the cache and hands over control
  * to the common ARM startup code.
- * This function will be mapped to address 0 by the SBAR register.
- * A normal branch is out of range here so we need a long jump. We jump to
- * the physical address as the MMU is still turned off.
  */
-        .align  12
-ENTRY(shmobile_secondary_vector_scu)
-        mrc     p15, 0, r0, c0, c0, 5   @ read MIPDR
-        and     r0, r0, #3              @ mask out cpu ID
-        lsl     r0, r0, #3              @ we will shift by cpu_id * 8 bits
-        ldr     r1, 2f
-        ldr     r1, [r1]                @ SCU base address
-        ldr     r2, [r1, #8]            @ SCU Power Status Register
+ENTRY(shmobile_boot_scu)
+                                        @ r0 = SCU base address
+        mrc     p15, 0, r1, c0, c0, 5   @ read MIPDR
+        and     r1, r1, #3              @ mask out cpu ID
+        lsl     r1, r1, #3              @ we will shift by cpu_id * 8 bits
+        ldr     r2, [r0, #8]            @ SCU Power Status Register
         mov     r3, #3
-        bic     r2, r2, r3, lsl r0      @ Clear bits of our CPU (Run Mode)
-        str     r2, [r1, #8]            @ write back
+        bic     r2, r2, r3, lsl r1      @ Clear bits of our CPU (Run Mode)
+        str     r2, [r0, #8]            @ write back
 
-        ldr     pc, 1f
-1:      .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-2:      .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(shmobile_secondary_vector_scu)
+        b       shmobile_invalidate_start
+ENDPROC(shmobile_boot_scu)
 
         .text
         .globl  shmobile_scu_base
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 96001fd49b6c..559d1ce5f57e 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -27,7 +27,14 @@ ENDPROC(shmobile_invalidate_start)
  * We need _long_ jump to the physical address.
  */
         .align  12
-ENTRY(shmobile_secondary_vector)
+ENTRY(shmobile_boot_vector)
+        ldr     r0, 2f
         ldr     pc, 1f
-1:      .long   shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
-ENDPROC(shmobile_secondary_vector)
+ENDPROC(shmobile_boot_vector)
+
+        .globl  shmobile_boot_fn
+shmobile_boot_fn:
+1:      .space  4
+        .globl  shmobile_boot_arg
+shmobile_boot_arg:
+2:      .space  4
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 76ac61292e48..03e56074928c 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -24,16 +24,16 @@ struct clk name = {			\
 }
 
 #define SH_FIXED_RATIO_CLK(name, p, r)          \
-static SH_FIXED_RATIO_CLKg(name, p, r);
+static SH_FIXED_RATIO_CLKg(name, p, r)
 
 #define SH_FIXED_RATIO_CLK_SET(name, p, m, d)   \
         SH_CLK_RATIO(name, m, d);               \
-        SH_FIXED_RATIO_CLK(name, p, name);
+        SH_FIXED_RATIO_CLK(name, p, name)
 
 #define SH_CLK_SET_RATIO(p, m, d)       \
-{                       \
+do {                    \
         (p)->mul = m;   \
         (p)->div = d;   \
-}
+} while (0)
 
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 4634a5d4b63f..e818f029d8e3 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -7,8 +7,10 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                          unsigned int mult, unsigned int div);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
-extern void shmobile_secondary_vector(void);
-extern void shmobile_secondary_vector_scu(void);
+extern void shmobile_boot_vector(void);
+extern unsigned long shmobile_boot_fn;
+extern unsigned long shmobile_boot_arg;
+extern void shmobile_boot_scu(void);
 struct clk;
 extern int shmobile_clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
deleted file mode 100644
index 9f134dfeffdc..000000000000
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-LIST "partner-jet-setup.txt"
-LIST "(C) Copyright 2010 Renesas Solutions Corp"
-LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
-
-LIST "RWT Setting"
-EW 0xE6020004, 0xA500
-EW 0xE6030004, 0xA500
-
-LIST "GPIO Setting"
-EB 0xE6051013, 0xA2
-
-LIST "CPG"
-ED 0xE61500C0, 0x00000002
-
-WAIT 1, 0xFE40009C
-
-LIST "FRQCR"
-ED 0xE6150000, 0x2D1305C3
-ED 0xE61500E0, 0x9E40358E
-ED 0xE6150004, 0x80331050
-
-WAIT 1, 0xFE40009C
-
-ED 0xE61500E4, 0x00002000
-
-WAIT 1, 0xFE40009C
-
-LIST "PLL"
-ED 0xE6150028, 0x00004000
-
-WAIT 1, 0xFE40009C
-
-ED 0xE615002C, 0x93000040
-
-WAIT 1, 0xFE40009C
-
-LIST "SUB/USBClk"
-ED 0xE6150080, 0x00000180
-
-LIST "BSC"
-ED 0xFEC10000, 0x00E0001B
-
-LIST "SBSC1"
-ED 0xFE400354, 0x01AD8000
-ED 0xFE400354, 0x01AD8001
-
-WAIT 5, 0xFE40009C
-
-ED 0xFE400008, 0xBCC90151
-ED 0xFE400040, 0x41774113
-ED 0xFE400044, 0x2712E229
-ED 0xFE400048, 0x20C18505
-ED 0xFE40004C, 0x00110209
-ED 0xFE400010, 0x00000087
-
-WAIT 30, 0xFE40009C
-
-ED 0xFE400084, 0x0000003F
-EB 0xFE500000, 0x00
-
-WAIT 5, 0xFE40009C
-
-ED 0xFE400084, 0x0000FF0A
-EB 0xFE500000, 0x00
-
-WAIT 1, 0xFE40009C
-
-ED 0xFE400084, 0x00002201
-EB 0xFE500000, 0x00
-ED 0xFE400084, 0x00000302
-EB 0xFE500000, 0x00
-EB 0xFE5C0000, 0x00
-ED 0xFE400008, 0xBCC90159
-ED 0xFE40008C, 0x88800004
-ED 0xFE400094, 0x00000004
-ED 0xFE400028, 0xA55A0032
-ED 0xFE40002C, 0xA55A000C
-ED 0xFE400020, 0xA55A2048
-ED 0xFE400008, 0xBCC90959
-
-LIST "Change CPGA setting"
-ED 0xE61500E0, 0x9E40352E
-ED 0xE6150004, 0x80331050
-
-WAIT 1, 0xFE40009C
-
-ED 0xFE400354, 0x01AD8002
-
-LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0xe1
-EW 0xE6C40000, 0x0000
-EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h
index b2074e2acb15..d241bfd6926d 100644
--- a/arch/arm/mach-shmobile/include/mach/irqs.h
+++ b/arch/arm/mach-shmobile/include/mach/irqs.h
@@ -16,4 +16,9 @@
 #define IRQPIN_BASE             2000
 #define irq_pin(nr)             ((nr) + IRQPIN_BASE)
 
+/* GPIO IRQ */
+#define _GPIO_IRQ_BASE          2500
+#define GPIO_IRQ_BASE(x)        (_GPIO_IRQ_BASE + (32 * x))
+#define GPIO_IRQ(x, y)          (_GPIO_IRQ_BASE + (32 * x) + y)
+
 #endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
deleted file mode 100644
index 0ffbe8155c76..000000000000
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_MEMORY_H
-#define __ASM_MACH_MEMORY_H
-
-#define PLAT_PHYS_OFFSET        UL(CONFIG_MEMORY_START)
-#define MEM_SIZE        UL(CONFIG_MEMORY_SIZE)
-
-#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
deleted file mode 100644
index db59fdbda860..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef MMC_AP4EB_H
-#define MMC_AP4EB_H
-
-#define PORT185CR      (void __iomem *)0xe60520b9
-#define PORT186CR      (void __iomem *)0xe60520ba
-#define PORT187CR      (void __iomem *)0xe60520bb
-#define PORT188CR      (void __iomem *)0xe60520bc
-
-#define PORTR191_160DR (void __iomem *)0xe6056014
-
-static inline void mmc_init_progress(void)
-{
-       /* Initialise LEDS1-4
-        * registers: PORT185CR-PORT188CR (LED1-LED4 Control)
-        * value:     0x10 - enable output
-        */
-       __raw_writeb(0x10, PORT185CR);
-       __raw_writeb(0x10, PORT186CR);
-       __raw_writeb(0x10, PORT187CR);
-       __raw_writeb(0x10, PORT188CR);
-}
-
-static inline void mmc_update_progress(int n)
-{
-        __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) |
-                     (1 << (25 + n)), PORTR191_160DR);
-}
-
-#endif /* MMC_AP4EB_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
index 21a59db638bb..e979b8fc1da2 100644
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ b/arch/arm/mach-shmobile/include/mach/mmc.h
@@ -7,9 +7,7 @@
  *
  **************************************************/
 
-#ifdef CONFIG_MACH_AP4EVB
-#include "mach/mmc-ap4eb.h"
-#elif defined(CONFIG_MACH_MACKEREL)
+#ifdef CONFIG_MACH_MACKEREL
 #include "mach/mmc-mackerel.h"
 #else
 #error "unsupported board."
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index abdc4d4efa28..b34d19b5ca5c 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -28,494 +28,6 @@
 #define MD_CK1  (1 << 1)
 #define MD_CK0  (1 << 0)
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
-        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
-
-        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
-        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
-
-        GPIO_PORT210, GPIO_PORT211,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
-        GPIO_FN_IRQ1,
-        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
-        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
-        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
-        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
-        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
-        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
-        GPIO_FN_IRQ8,
-        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
-        GPIO_FN_IRQ10,
-        GPIO_FN_IRQ11,
-        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
-        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
-        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
-        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
-        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
-        GPIO_FN_IRQ17,
-        GPIO_FN_IRQ18,
-        GPIO_FN_IRQ19,
-        GPIO_FN_IRQ20,
-        GPIO_FN_IRQ21,
-        GPIO_FN_IRQ22,
-        GPIO_FN_IRQ23,
-        GPIO_FN_IRQ24,
-        GPIO_FN_IRQ25,
-        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
-        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
-        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
-        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
-        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
-        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
-        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
-        GPIO_FN_DBGMD21,
-
-        /* FSI-A */
-        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
-        GPIO_FN_FSIAISLD_PORT5,
-        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
-        GPIO_FN_FSIASPDIF_PORT18,
-        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
-        GPIO_FN_FSIAIBT,
-
-        /* FSI-B */
-        GPIO_FN_FSIBCK,
-
-        /* FMSI */
-        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
-        GPIO_FN_FMSISLD_PORT6,
-        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
-        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOCK,
-
-        /* SCIFA0 */
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
-        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_TXD,
-
-        /* SCIFA1 */
-        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
-        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
-        GPIO_FN_SCIFA1_RTS,
-
-        /* SCIFA2 */
-        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN_SCIFA2_SCK_PORT199,
-        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
-        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
-
-        /* SCIFA3 */
-        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
-        GPIO_FN_SCIFA3_SCK_PORT116,
-        GPIO_FN_SCIFA3_CTS_PORT117,
-        GPIO_FN_SCIFA3_RXD_PORT174,
-        GPIO_FN_SCIFA3_TXD_PORT175,
-
-        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
-        GPIO_FN_SCIFA3_SCK_PORT158,
-        GPIO_FN_SCIFA3_CTS_PORT162,
-        GPIO_FN_SCIFA3_RXD_PORT159,
-        GPIO_FN_SCIFA3_TXD_PORT160,
-
-        /* SCIFA4 */
-        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
-        GPIO_FN_SCIFA4_TXD_PORT13,
-
-        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
-        GPIO_FN_SCIFA4_TXD_PORT203,
-
-        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
-        GPIO_FN_SCIFA4_TXD_PORT93,
-
-        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN_SCIFA4_SCK_PORT205,
-
-        /* SCIFA5 */
-        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
-        GPIO_FN_SCIFA5_RXD_PORT10,
-
-        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
-        GPIO_FN_SCIFA5_TXD_PORT208,
-
-        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
-        GPIO_FN_SCIFA5_RXD_PORT92,
-
-        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN_SCIFA5_SCK_PORT206,
-
-        /* SCIFA6 */
-        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
-
-        /* SCIFA7 */
-        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
-
-        /* SCIFAB */
-        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
-        GPIO_FN_SCIFB_RXD_PORT191,
-        GPIO_FN_SCIFB_TXD_PORT192,
-        GPIO_FN_SCIFB_RTS_PORT186,
-        GPIO_FN_SCIFB_CTS_PORT187,
-
-        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
-        GPIO_FN_SCIFB_RXD_PORT3,
-        GPIO_FN_SCIFB_TXD_PORT4,
-        GPIO_FN_SCIFB_RTS_PORT172,
-        GPIO_FN_SCIFB_CTS_PORT173,
-
-        /* LCD0 */
-        GPIO_FN_LCDC0_SELECT,
-
-        /* LCD1 */
-        GPIO_FN_LCDC1_SELECT,
-
-        /* RSPI */
-        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
-        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
-        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
-        GPIO_FN_RSPI_CK_A,
-
-        /* VIO CKO */
-        GPIO_FN_VIO_CKO1,
-        GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_CKO_1,
-        GPIO_FN_VIO_CKO,
-
-        /* VIO0 */
-        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
-        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
-        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
-        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
-        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
-        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
-
-        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
-        GPIO_FN_VIO0_D14_PORT25,
-        GPIO_FN_VIO0_D15_PORT24,
-
-        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
-        GPIO_FN_VIO0_D14_PORT95,
-        GPIO_FN_VIO0_D15_PORT96,
-
-        /* VIO1 */
-        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
-        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
-        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
-        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
-
-        /* TPU0 */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO3,
-        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
-        GPIO_FN_TPU0TO2_PORT202,
-
-        /* SSP1 0 */
-        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
-        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
-        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
-        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
-
-        /* SSP1 1 */
-        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
-        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
-        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
-
-        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
-        GPIO_FN_STP1_IPEN_PORT187,
-
-        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
-        GPIO_FN_STP1_IPEN_PORT193,
-
-        /* SIM */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
-        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
-        GPIO_FN_SIM_D_PORT199,
-
-        /* MSIOF2 */
-        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
-        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_RSCK,
-
-        /* KEYSC */
-        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
-        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
-
-        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
-        GPIO_FN_KEYIN1_PORT44,
-        GPIO_FN_KEYIN2_PORT45,
-        GPIO_FN_KEYIN3_PORT46,
-
-        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
-        GPIO_FN_KEYIN1_PORT57,
-        GPIO_FN_KEYIN2_PORT56,
-        GPIO_FN_KEYIN3_PORT55,
-
-        /* VOU */
-        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
-        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
-        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
-        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
-        GPIO_FN_DV_CLK,
-        GPIO_FN_DV_VSYNC,
-        GPIO_FN_DV_HSYNC,
-
-        /* MEMC */
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
-        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
-
-        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
-        GPIO_FN_MEMC_ADV,
-        GPIO_FN_MEMC_WAIT,
-        GPIO_FN_MEMC_BUSCLK,
-
-        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
-        GPIO_FN_MEMC_DREQ0,
-        GPIO_FN_MEMC_DREQ1,
-        GPIO_FN_MEMC_A0,
-
-        /* MSIOF0 */
-        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
-        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
-
-        /* MSIOF1 */
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
-        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
-        GPIO_FN_MSIOF1_TSYNC_PORT120,
-        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
-
-        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
-        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
-        GPIO_FN_MSIOF1_RXD_PORT75,
-        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN_GPO0,   GPIO_FN_GPI0,
-        GPIO_FN_GPO1,   GPIO_FN_GPI1,
-
-        /* USB0 */
-        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
-
-        /* USB1 */
-        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
-
-        /* BBIF1 */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
-
-        /* BBIF2 */
-        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
-        GPIO_FN_BBIF2_RXD2_PORT60,
-        GPIO_FN_BBIF2_TSYNC2_PORT6,
-        GPIO_FN_BBIF2_TSCK2_PORT59,
-
-        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
-        GPIO_FN_BBIF2_TXD2_PORT183,
-        GPIO_FN_BBIF2_TSCK2_PORT89,
-        GPIO_FN_BBIF2_TSYNC2_PORT184,
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5B,   GPIO_FN_CS6A,
-        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
-        GPIO_FN_CS5A_PORT19,
-        GPIO_FN_IOIS16, /* ? */
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A4_FOE,         /* share with FLCTL */
-        GPIO_FN_A5_FCDE,        /* share with FLCTL */
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
-        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
-        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
-        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
-        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
-        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
-
-        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
-        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
-        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
-        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
-
-        GPIO_FN_WE0_FWE,        /* share with FLCTL */
-        GPIO_FN_WE1,
-        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
-        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
-        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
-        GPIO_FN_RD_FSC,         /* share with FLCTL */
-        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
-        GPIO_FN_WAIT_PORT90,
-
-        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
-
-        /* ATAPI */
-        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
-        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
-        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
-        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
-        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
-        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
-        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
-        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
-        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
-        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
-
-        /* RMII */
-        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
-        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
-        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
-        GPIO_FN_RMII_REF50CK,   /* for RMII */
-        GPIO_FN_RMII_REF125CK,  /* for GMII */
-
-        /* GEther */
-        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
-        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
-        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
-        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
-        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
-        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
-        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
-        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
-        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
-        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
-        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
-        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
-        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
-        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
-
-        /* DMA0 */
-        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
-
-        /* DMA1 */
-        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
-
-        /* SYSC */
-        GPIO_FN_RESETOUTS,
-        GPIO_FN_RESETP_PULLUP,
-        GPIO_FN_RESETP_PLAIN,
-
-        /* HDMI */
-        GPIO_FN_HDMI_HPD,
-        GPIO_FN_HDMI_CEC,
-
-        /* SDENC */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-
-        /* IRREM */
-        GPIO_FN_IROUT,
-
-        /* DEBUG */
-        GPIO_FN_EDEBGREQ_PULLDOWN,
-        GPIO_FN_EDEBGREQ_PULLUP,
-
-        GPIO_FN_TRACEAUD_FROM_VIO,
-        GPIO_FN_TRACEAUD_FROM_LCDC0,
-        GPIO_FN_TRACEAUD_FROM_MEMC,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
@@ -533,10 +45,13 @@ enum {
 };
 
 extern void r8a7740_meram_workaround(void);
+extern void r8a7740_init_delay(void);
 extern void r8a7740_init_irq(void);
+extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
 extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_add_standard_devices_dt(void);
 extern void r8a7740_clock_init(u8 md_ck);
 extern void r8a7740_pinmux_init(void);
 extern void r8a7740_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index 951149e6bcca..851d027a2f06 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,15 +18,26 @@
 #ifndef __ASM_R8A7778_H__
 #define __ASM_R8A7778_H__
 
+#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 
 extern void r8a7778_add_standard_devices(void);
 extern void r8a7778_add_standard_devices_dt(void);
 extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7778_add_i2c_device(int id);
+extern void r8a7778_add_hspi_device(int id);
+extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
+
+extern void r8a7778_init_late(void);
 extern void r8a7778_init_delay(void);
 extern void r8a7778_init_irq(void);
 extern void r8a7778_init_irq_dt(void);
 extern void r8a7778_clock_init(void);
 extern void r8a7778_init_irq_extpin(int irlm);
+extern void r8a7778_pinmux_init(void);
+extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
 
 #endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 188b295938a5..fc47073c7ba9 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,6 +4,7 @@
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
 #include <linux/sh_eth.h>
+#include <linux/platform_data/usb-rcar-phy.h>
 
 struct platform_device;
 
@@ -33,6 +34,8 @@ extern void r8a7779_add_early_devices(void);
 extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_add_standard_devices_dt(void);
 extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
+extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
+extern void r8a7779_init_late(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index fd7cba024c39..854a9f0ca040 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -15,397 +15,6 @@
 #include <linux/pm_domain.h>
 #include <mach/pm-rmobile.h>
 
-/*
- * Pin Function Controller:
- *      GPIO_FN_xx - GPIO used to select pin function
- *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
- */
-enum {
-        /* PORT */
-        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
-        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
-
-        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
-        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
-
-        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
-        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
-
-        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
-        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
-
-        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
-        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
-
-        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
-        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
-
-        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
-        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
-
-        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
-        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
-
-        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
-        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
-
-        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
-        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
-
-        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
-        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
-
-        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
-        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
-
-        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
-        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
-
-        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
-        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
-
-        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
-        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
-
-        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
-        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
-
-        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
-        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
-
-        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
-        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
-
-        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
-        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
-
-        GPIO_PORT190,
-
-        /* IRQ */
-        GPIO_FN_IRQ0_6,         /* PORT   6 */
-        GPIO_FN_IRQ0_162,       /* PORT 162 */
-        GPIO_FN_IRQ1,           /* PORT  12 */
-        GPIO_FN_IRQ2_4,         /* PORT   4 */
-        GPIO_FN_IRQ2_5,         /* PORT   5 */
-        GPIO_FN_IRQ3_8,         /* PORT   8 */
-        GPIO_FN_IRQ3_16,        /* PORT  16 */
-        GPIO_FN_IRQ4_17,        /* PORT  17 */
-        GPIO_FN_IRQ4_163,       /* PORT 163 */
-        GPIO_FN_IRQ5,           /* PORT  18 */
-        GPIO_FN_IRQ6_39,        /* PORT  39 */
-        GPIO_FN_IRQ6_164,       /* PORT 164 */
-        GPIO_FN_IRQ7_40,        /* PORT  40 */
-        GPIO_FN_IRQ7_167,       /* PORT 167 */
-        GPIO_FN_IRQ8_41,        /* PORT  41 */
-        GPIO_FN_IRQ8_168,       /* PORT 168 */
-        GPIO_FN_IRQ9_42,        /* PORT  42 */
-        GPIO_FN_IRQ9_169,       /* PORT 169 */
-        GPIO_FN_IRQ10,          /* PORT  65 */
-        GPIO_FN_IRQ11,          /* PORT  67 */
-        GPIO_FN_IRQ12_80,       /* PORT  80 */
-        GPIO_FN_IRQ12_137,      /* PORT 137 */
-        GPIO_FN_IRQ13_81,       /* PORT  81 */
-        GPIO_FN_IRQ13_145,      /* PORT 145 */
-        GPIO_FN_IRQ14_82,       /* PORT  82 */
-        GPIO_FN_IRQ14_146,      /* PORT 146 */
-        GPIO_FN_IRQ15_83,       /* PORT  83 */
-        GPIO_FN_IRQ15_147,      /* PORT 147 */
-        GPIO_FN_IRQ16_84,       /* PORT  84 */
-        GPIO_FN_IRQ16_170,      /* PORT 170 */
-        GPIO_FN_IRQ17,          /* PORT  85 */
-        GPIO_FN_IRQ18,          /* PORT  86 */
-        GPIO_FN_IRQ19,          /* PORT  87 */
-        GPIO_FN_IRQ20,          /* PORT  92 */
-        GPIO_FN_IRQ21,          /* PORT  93 */
-        GPIO_FN_IRQ22,          /* PORT  94 */
-        GPIO_FN_IRQ23,          /* PORT  95 */
-        GPIO_FN_IRQ24,          /* PORT 112 */
-        GPIO_FN_IRQ25,          /* PORT 119 */
-        GPIO_FN_IRQ26_121,      /* PORT 121 */
-        GPIO_FN_IRQ26_172,      /* PORT 172 */
-        GPIO_FN_IRQ27_122,      /* PORT 122 */
-        GPIO_FN_IRQ27_180,      /* PORT 180 */
-        GPIO_FN_IRQ28_123,      /* PORT 123 */
-        GPIO_FN_IRQ28_181,      /* PORT 181 */
-        GPIO_FN_IRQ29_129,      /* PORT 129 */
-        GPIO_FN_IRQ29_182,      /* PORT 182 */
-        GPIO_FN_IRQ30_130,      /* PORT 130 */
-        GPIO_FN_IRQ30_183,      /* PORT 183 */
-        GPIO_FN_IRQ31_138,      /* PORT 138 */
-        GPIO_FN_IRQ31_184,      /* PORT 184 */
-
-        /*
-         * MSIOF0       (PORT 36, 37, 38, 39
-         *                    40, 41, 42, 43, 44, 45)
-         */
-        GPIO_FN_MSIOF0_TSYNC,   GPIO_FN_MSIOF0_TSCK,
-        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_RSCK,
-        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_MCK0,
-        GPIO_FN_MSIOF0_MCK1,    GPIO_FN_MSIOF0_SS1,
-        GPIO_FN_MSIOF0_SS2,     GPIO_FN_MSIOF0_TXD,
-
-        /*
-         * MSIOF1       (PORT 39, 40, 41, 42, 43, 44
-         *                    84, 85, 86, 87, 88, 89, 90, 91, 92, 93)
-         */
-        GPIO_FN_MSIOF1_TSCK_39, GPIO_FN_MSIOF1_TSYNC_40,
-        GPIO_FN_MSIOF1_TSCK_88, GPIO_FN_MSIOF1_TSYNC_89,
-        GPIO_FN_MSIOF1_TXD_41,  GPIO_FN_MSIOF1_RXD_42,
-        GPIO_FN_MSIOF1_TXD_90,  GPIO_FN_MSIOF1_RXD_91,
-        GPIO_FN_MSIOF1_SS1_43,  GPIO_FN_MSIOF1_SS2_44,
-        GPIO_FN_MSIOF1_SS1_92,  GPIO_FN_MSIOF1_SS2_93,
-        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
-        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
-
-        /*
-         * MSIOF2       (PORT 134, 135, 136, 137, 138, 139
-         *                    148, 149, 150, 151)
-         */
-        GPIO_FN_MSIOF2_RSCK,    GPIO_FN_MSIOF2_RSYNC,
-        GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_MCK1,
-        GPIO_FN_MSIOF2_SS1,     GPIO_FN_MSIOF2_SS2,
-        GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_TSCK,
-        GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TXD,
-
-        /* MSIOF3       (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TSYNC,
-        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_TXD,
-        GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
-        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BB_RX_FLOW_N,
-
-        /* MSIOF4       (PORT 0, 1, 2, 3) */
-        GPIO_FN_BBIF2_TSCK1,    GPIO_FN_BBIF2_TSYNC1,
-        GPIO_FN_BBIF2_TXD1,     GPIO_FN_BBIF2_RXD,
-
-        /* FSI          (PORT 4, 5, 6, 7, 8, 9, 10, 11, 15) */
-        GPIO_FN_FSIACK,         GPIO_FN_FSIBCK,
-        GPIO_FN_FSIAILR,        GPIO_FN_FSIAIBT,
-        GPIO_FN_FSIAISLD,       GPIO_FN_FSIAOMC,
-        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
-        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIASPDIF_11,
-        GPIO_FN_FSIASPDIF_15,
-
-        /* FMSI         (PORT 12, 13, 14, 15, 16, 17, 18, 65) */
-        GPIO_FN_FMSOCK,         GPIO_FN_FMSOOLR,
-        GPIO_FN_FMSIOLR,        GPIO_FN_FMSOOBT,
-        GPIO_FN_FMSIOBT,        GPIO_FN_FMSOSLD,
-        GPIO_FN_FMSOILR,        GPIO_FN_FMSIILR,
-        GPIO_FN_FMSOIBT,        GPIO_FN_FMSIIBT,
-        GPIO_FN_FMSISLD,        GPIO_FN_FMSICK,
-
-        /* SCIFA0       (PORT 152, 153, 156, 157, 158) */
-        GPIO_FN_SCIFA0_TXD,     GPIO_FN_SCIFA0_RXD,
-        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_RTS,
-        GPIO_FN_SCIFA0_CTS,
-
-        /* SCIFA1       (PORT 154, 155, 159, 160, 161) */
-        GPIO_FN_SCIFA1_TXD,     GPIO_FN_SCIFA1_RXD,
-        GPIO_FN_SCIFA1_SCK,     GPIO_FN_SCIFA1_RTS,
-        GPIO_FN_SCIFA1_CTS,
-
-        /* SCIFA2       (PORT 94, 95, 96, 97, 98) */
-        GPIO_FN_SCIFA2_CTS1,    GPIO_FN_SCIFA2_RTS1,
-        GPIO_FN_SCIFA2_TXD1,    GPIO_FN_SCIFA2_RXD1,
-        GPIO_FN_SCIFA2_SCK1,
-
-        /* SCIFA3       (PORT 43, 44,
-                             140, 141, 142, 143, 144) */
-        GPIO_FN_SCIFA3_CTS_43,  GPIO_FN_SCIFA3_CTS_140,
-        GPIO_FN_SCIFA3_RTS_44,  GPIO_FN_SCIFA3_RTS_141,
-        GPIO_FN_SCIFA3_SCK,     GPIO_FN_SCIFA3_TXD,
-        GPIO_FN_SCIFA3_RXD,
-
-        /* SCIFA4       (PORT 5, 6) */
-        GPIO_FN_SCIFA4_RXD,     GPIO_FN_SCIFA4_TXD,
-
-        /* SCIFA5       (PORT 8, 12) */
-        GPIO_FN_SCIFA5_RXD,     GPIO_FN_SCIFA5_TXD,
-
-        /* SCIFB        (PORT 162, 163, 164, 165, 166) */
-        GPIO_FN_SCIFB_SCK,      GPIO_FN_SCIFB_RTS,
-        GPIO_FN_SCIFB_CTS,      GPIO_FN_SCIFB_TXD,
-        GPIO_FN_SCIFB_RXD,
-
-        /*
-         * CEU          (PORT 16, 17,
-         *                    100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
-         *                    110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
-         *                    120)
-         */
-        GPIO_FN_VIO_HD,         GPIO_FN_VIO_CKO1,       GPIO_FN_VIO_CKO2,
-        GPIO_FN_VIO_VD,         GPIO_FN_VIO_CLK,        GPIO_FN_VIO_FIELD,
-        GPIO_FN_VIO_CKO,
-        GPIO_FN_VIO_D0,         GPIO_FN_VIO_D1,         GPIO_FN_VIO_D2,
-        GPIO_FN_VIO_D3,         GPIO_FN_VIO_D4,         GPIO_FN_VIO_D5,
-        GPIO_FN_VIO_D6,         GPIO_FN_VIO_D7,         GPIO_FN_VIO_D8,
-        GPIO_FN_VIO_D9,         GPIO_FN_VIO_D10,        GPIO_FN_VIO_D11,
-        GPIO_FN_VIO_D12,        GPIO_FN_VIO_D13,        GPIO_FN_VIO_D14,
-        GPIO_FN_VIO_D15,
-
-        /* USB0         (PORT 113, 114, 115, 116, 117, 167) */
-        GPIO_FN_IDIN_0,         GPIO_FN_EXTLP_0,
-        GPIO_FN_OVCN2_0,        GPIO_FN_PWEN_0,
-        GPIO_FN_OVCN_0,         GPIO_FN_VBUS0_0,
-
-        /* USB1         (PORT 18, 113, 114, 115, 116, 117, 138, 162, 168) */
-        GPIO_FN_IDIN_1_18,      GPIO_FN_IDIN_1_113,
-        GPIO_FN_PWEN_1_115,     GPIO_FN_PWEN_1_138,
-        GPIO_FN_OVCN_1_114,     GPIO_FN_OVCN_1_162,
-        GPIO_FN_EXTLP_1,        GPIO_FN_OVCN2_1,
-        GPIO_FN_VBUS0_1,
-
-        /* GPIO         (PORT 41, 42, 43, 44) */
-        GPIO_FN_GPI0,   GPIO_FN_GPI1,   GPIO_FN_GPO0,   GPIO_FN_GPO1,
-
-        /*
-         * BSC          (PORT 19,
-         *                    20, 21, 22, 25, 26, 27, 28, 29,
-         *                    30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
-         *                    40, 41, 42, 43, 44, 45,
-         *                    62, 63, 64, 65, 66, 67,
-         *                    71, 72, 74, 75)
-         */
-        GPIO_FN_BS,     GPIO_FN_WE1,
-        GPIO_FN_CKO,    GPIO_FN_WAIT,   GPIO_FN_RDWR,
-
-        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
-        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
-        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
-        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
-        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
-        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
-        GPIO_FN_A26,
-
-        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
-        GPIO_FN_CS5A,   GPIO_FN_CS5B,   GPIO_FN_CS6A,
-
-        /*
-         * BSC/FLCTL            (PORT 23, 24,
-         *                            46, 47, 48, 49,
-         *                            50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
-         *                            60, 61, 69, 70)
-         */
-        GPIO_FN_RD_FSC,         GPIO_FN_WE0_FWE,
-        GPIO_FN_A4_FOE,         GPIO_FN_A5_FCDE,
-        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        GPIO_FN_D2_NAF2,
-        GPIO_FN_D3_NAF3,        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,
-        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        GPIO_FN_D8_NAF8,
-        GPIO_FN_D9_NAF9,        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,
-        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      GPIO_FN_D14_NAF14,
-        GPIO_FN_D15_NAF15,
-
-        /* SPU2         (PORT 65) */
-        GPIO_FN_VINT_I,
-
-        /* FLCTL        (PORT 66, 68, 73) */
-        GPIO_FN_FCE1,   GPIO_FN_FCE0,   GPIO_FN_FRB,
-
-        /* HSI          (PORT 76, 77, 78, 79, 80, 81, 82, 83) */
-        GPIO_FN_GP_RX_FLAG,     GPIO_FN_GP_RX_DATA,     GPIO_FN_GP_TX_READY,
-        GPIO_FN_GP_RX_WAKE,     GPIO_FN_MP_TX_FLAG,     GPIO_FN_MP_TX_DATA,
-        GPIO_FN_MP_RX_READY,    GPIO_FN_MP_TX_WAKE,
-
-        /*
-         * MFI          (PORT 76, 77, 78, 79,
-         *                    80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
-         *                    90, 91, 92, 93, 94, 95, 96, 97, 98, 99)
-         */
-        GPIO_FN_MFIv6,  /* see MSEL4CR 6 */
-        GPIO_FN_MFIv4,  /* see MSEL4CR 6 */
-
-        GPIO_FN_MEMC_CS0,               GPIO_FN_MEMC_BUSCLK_MEMC_A0,
-        GPIO_FN_MEMC_CS1_MEMC_A1,       GPIO_FN_MEMC_ADV_MEMC_DREQ0,
-        GPIO_FN_MEMC_WAIT_MEMC_DREQ1,   GPIO_FN_MEMC_NOE,
-        GPIO_FN_MEMC_NWE,               GPIO_FN_MEMC_INT,
-
-        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
-        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
-        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
-        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
-        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
-        GPIO_FN_MEMC_AD15,
-
-        /* SIM          (PORT 94, 95, 98) */
-        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,        GPIO_FN_SIM_D,
-
-        /* TPU          (PORT 93, 99, 112, 160, 161) */
-        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
-        GPIO_FN_TPU0TO2_93,     GPIO_FN_TPU0TO2_99,
-        GPIO_FN_TPU0TO3,
-
-        /* I2C2         (PORT 110, 111) */
-        GPIO_FN_I2C_SCL2,       GPIO_FN_I2C_SDA2,
-
-        /* I2C3(1)      (PORT 114, 115) */
-        GPIO_FN_I2C_SCL3,       GPIO_FN_I2C_SDA3,
-
-        /* I2C3(2)      (PORT 137, 145) */
-        GPIO_FN_I2C_SCL3S,      GPIO_FN_I2C_SDA3S,
-
-        /* I2C4(2)      (PORT 116, 117) */
-        GPIO_FN_I2C_SCL4,       GPIO_FN_I2C_SDA4,
-
-        /* I2C4(2)      (PORT 146, 147) */
-        GPIO_FN_I2C_SCL4S,      GPIO_FN_I2C_SDA4S,
-
-        /*
-         * KEYSC        (PORT 121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136)
-         */
-        GPIO_FN_KEYOUT0,        GPIO_FN_KEYIN0_121,     GPIO_FN_KEYIN0_136,
-        GPIO_FN_KEYOUT1,        GPIO_FN_KEYIN1_122,     GPIO_FN_KEYIN1_135,
-        GPIO_FN_KEYOUT2,        GPIO_FN_KEYIN2_123,     GPIO_FN_KEYIN2_134,
-        GPIO_FN_KEYOUT3,        GPIO_FN_KEYIN3_124,     GPIO_FN_KEYIN3_133,
-        GPIO_FN_KEYOUT4,        GPIO_FN_KEYIN4,
-        GPIO_FN_KEYOUT5,        GPIO_FN_KEYIN5,
-        GPIO_FN_KEYOUT6,        GPIO_FN_KEYIN6,
-        GPIO_FN_KEYOUT7,        GPIO_FN_KEYIN7,
-
-        /*
-         * LCDC         (PORT      121, 122, 123, 124, 125, 126, 127, 128, 129,
-         *                    130, 131, 132, 133, 134, 135, 136, 137, 138, 139,
-         *                    140, 141, 142, 143, 144, 145, 146, 147, 148, 149,
-         *                    150, 151)
-         */
-        GPIO_FN_LCDC0_SELECT, /* LCDC 0 */
-        GPIO_FN_LCDC1_SELECT, /* LCDC 1 */
-        GPIO_FN_LCDHSYN,        GPIO_FN_LCDCS,  GPIO_FN_LCDVSYN,
-        GPIO_FN_LCDDCK,         GPIO_FN_LCDWR,  GPIO_FN_LCDRD,
-        GPIO_FN_LCDDISP,        GPIO_FN_LCDRS,  GPIO_FN_LCDLCLK,
-        GPIO_FN_LCDDON,
-
-        GPIO_FN_LCDD0,  GPIO_FN_LCDD1,  GPIO_FN_LCDD2,  GPIO_FN_LCDD3,
-        GPIO_FN_LCDD4,  GPIO_FN_LCDD5,  GPIO_FN_LCDD6,  GPIO_FN_LCDD7,
-        GPIO_FN_LCDD8,  GPIO_FN_LCDD9,  GPIO_FN_LCDD10, GPIO_FN_LCDD11,
-        GPIO_FN_LCDD12, GPIO_FN_LCDD13, GPIO_FN_LCDD14, GPIO_FN_LCDD15,
-        GPIO_FN_LCDD16, GPIO_FN_LCDD17, GPIO_FN_LCDD18, GPIO_FN_LCDD19,
-        GPIO_FN_LCDD20, GPIO_FN_LCDD21, GPIO_FN_LCDD22, GPIO_FN_LCDD23,
-
-        /* IRDA         (PORT 139, 140, 141, 142) */
-        GPIO_FN_IRDA_OUT,       GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_FIRSEL,
-        GPIO_FN_IROUT_139,      GPIO_FN_IROUT_140,
-
-        /* TSIF1        (PORT 156, 157, 158, 159) */
-        GPIO_FN_TS0_1SELECT, /* TSIF0 - 1 select */
-        GPIO_FN_TS0_2SELECT, /* TSIF0 - 2 select */
-        GPIO_FN_TS1_1SELECT, /* TSIF1 - 1 select */
-        GPIO_FN_TS1_2SELECT, /* TSIF1 - 2 select */
-
-        GPIO_FN_TS_SPSYNC1,     GPIO_FN_TS_SDAT1,
-        GPIO_FN_TS_SDEN1,       GPIO_FN_TS_SCK1,
-
-        /* TSIF2        (PORT 137, 145, 146, 147) */
-        GPIO_FN_TS_SPSYNC2,     GPIO_FN_TS_SDAT2,
-        GPIO_FN_TS_SDEN2,       GPIO_FN_TS_SCK2,
-
-        /* HDMI         (PORT 169, 170) */
-        GPIO_FN_HDMI_HPD,       GPIO_FN_HDMI_CEC,
-
-        /* SDENC        see MSEL4CR 19 */
-        GPIO_FN_SDENC_CPG,
-        GPIO_FN_SDENC_DV_CLKI,
-};
-
 /* DMA slave IDs */
 enum {
         SHDMA_SLAVE_INVALID,
@@ -466,6 +75,8 @@ extern void sh7372_intcs_resume(void);
 extern void sh7372_intca_suspend(void);
 extern void sh7372_intca_resume(void);
 
+extern unsigned long sh7372_cpu_resume;
+
 #ifdef CONFIG_PM
 extern void __init sh7372_init_pm_domains(void);
 #else
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 9320aff0a20f..f2d8744c1f14 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -10,11 +10,9 @@
  *
  **************************************************/
 
-#ifdef CONFIG_MACH_AP4EVB
-#define MACH_TYPE       MACH_TYPE_AP4EVB
-#include "mach/head-ap4evb.txt"
-#elif defined(CONFIG_MACH_MACKEREL)
+#ifdef CONFIG_MACH_MACKEREL
 #define MACH_TYPE       MACH_TYPE_MACKEREL
+#define MEMORY_START    0x40000000
 #include "mach/head-mackerel.txt"
 #else
 #error "unsupported board."
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index b741c8409a5a..8871f7717dc8 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -20,19 +20,15 @@
 
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
 
-void __init r8a7740_init_irq(void)
+static void __init r8a7740_init_irq_common(void)
 {
-        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
-        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
         void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
         void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
         void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
 
-        /* initialize the Generic Interrupt Controller PL390 r0p0 */
-        gic_init(0, 29, gic_dist_base, gic_cpu_base);
-
         /* route signals to GIC */
         iowrite32(0x0, pfc_inta_ctrl);
 
@@ -54,3 +50,19 @@ void __init r8a7740_init_irq(void)
         iounmap(intc_msk_base);
         iounmap(pfc_inta_ctrl);
 }
+
+void __init r8a7740_init_irq_of(void)
+{
+        irqchip_init();
+        r8a7740_init_irq_common();
+}
+
+void __init r8a7740_init_irq(void)
+{
+        void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
+        void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
+
+        /* initialize the Generic Interrupt Controller PL390 r0p0 */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+        r8a7740_init_irq_common();
+}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index dec9293bb90d..0de75fd394b9 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on)
 
 static void sh7372_pm_setup_smfram(void)
 {
+        /* pass physical address of cpu_resume() to assembly resume code */
+        sh7372_cpu_resume = virt_to_phys(cpu_resume);
+
         memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
 }
 #else
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 326a4ab0bd5f..00c5a707238b 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -70,29 +70,15 @@ void __init r8a7740_map_io(void)
 }
 
 /* PFC */
-static struct resource r8a7740_pfc_resources[] = {
-        [0] = {
-                .start  = 0xe6050000,
-                .end    = 0xe6057fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0xe605800c,
-                .end    = 0xe605802b,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device r8a7740_pfc_device = {
-        .name           = "pfc-r8a7740",
-        .id             = -1,
-        .resource       = r8a7740_pfc_resources,
-        .num_resources  = ARRAY_SIZE(r8a7740_pfc_resources),
+static const struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xe6050000, 0x8000),
+        DEFINE_RES_MEM(0xe605800c, 0x0020),
 };
 
 void __init r8a7740_pinmux_init(void)
 {
-        platform_device_register(&r8a7740_pfc_device);
+        platform_device_register_simple("pfc-r8a7740", -1, pfc_resources,
+                                        ARRAY_SIZE(pfc_resources));
 }
 
 static struct renesas_intc_irqpin_config irqpin0_platform_data = {
@@ -531,11 +517,7 @@ static struct platform_device ipmmu_device = {
         .num_resources  = ARRAY_SIZE(ipmmu_resources),
 };
 
-static struct platform_device *r8a7740_early_devices[] __initdata = {
-        &irqpin0_device,
-        &irqpin1_device,
-        &irqpin2_device,
-        &irqpin3_device,
+static struct platform_device *r8a7740_devices_dt[] __initdata = {
         &scif0_device,
         &scif1_device,
         &scif2_device,
@@ -546,6 +528,13 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
         &scif7_device,
         &scifb_device,
         &cmt10_device,
+};
+
+static struct platform_device *r8a7740_early_devices[] __initdata = {
+        &irqpin0_device,
+        &irqpin1_device,
+        &irqpin2_device,
+        &irqpin3_device,
         &tmu00_device,
         &tmu01_device,
         &tmu02_device,
@@ -965,6 +954,8 @@ void __init r8a7740_add_standard_devices(void)
         /* add devices */
         platform_add_devices(r8a7740_early_devices,
                             ARRAY_SIZE(r8a7740_early_devices));
+        platform_add_devices(r8a7740_devices_dt,
+                            ARRAY_SIZE(r8a7740_devices_dt));
         platform_add_devices(r8a7740_late_devices,
                              ARRAY_SIZE(r8a7740_late_devices));
 
@@ -986,6 +977,8 @@ void __init r8a7740_add_early_devices(void)
 {
         early_platform_add_devices(r8a7740_early_devices,
                                    ARRAY_SIZE(r8a7740_early_devices));
+        early_platform_add_devices(r8a7740_devices_dt,
+                                   ARRAY_SIZE(r8a7740_devices_dt));
 
         /* setup early console here as well */
         shmobile_setup_console();
@@ -993,33 +986,29 @@ void __init r8a7740_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init r8a7740_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-
-        early_platform_add_devices(r8a7740_early_devices,
-                                   ARRAY_SIZE(r8a7740_early_devices));
-
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
-
 static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
         { }
 };
 
 void __init r8a7740_add_standard_devices_dt(void)
 {
-        /* clocks are setup late during boot in the case of DT */
-        r8a7740_clock_init(0);
-
-        platform_add_devices(r8a7740_early_devices,
-                            ARRAY_SIZE(r8a7740_early_devices));
-
+        platform_add_devices(r8a7740_devices_dt,
+                            ARRAY_SIZE(r8a7740_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              r8a7740_auxdata_lookup, NULL);
 }
 
+void __init r8a7740_init_delay(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+};
+
+static void __init r8a7740_generic_init(void)
+{
+        r8a7740_clock_init(0);
+        r8a7740_add_standard_devices_dt();
+}
+
 static const char *r8a7740_boards_compat_dt[] __initdata = {
         "renesas,r8a7740",
         NULL,
@@ -1027,9 +1016,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
         .map_io         = r8a7740_map_io,
-        .init_early     = r8a7740_add_early_devices_dt,
-        .init_irq       = r8a7740_init_irq,
-        .init_machine   = r8a7740_add_standard_devices_dt,
+        .init_early     = r8a7740_init_delay,
+        .init_irq       = r8a7740_init_irq_of,
+        .init_machine   = r8a7740_generic_init,
+        .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
 
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 30b4a336308f..80c20392ad7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -24,11 +24,18 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
 #include <linux/platform_device.h>
 #include <linux/irqchip.h>
 #include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
+#include <linux/pm_runtime.h>
+#include <linux/usb/phy.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/dma-mapping.h>
 #include <mach/irqs.h>
 #include <mach/r8a7778.h>
 #include <mach/common.h>
@@ -80,12 +87,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
         .clocksource_rating     = 200,
 };
 
-/* Ether */
-static struct resource ether_resources[] = {
-        DEFINE_RES_MEM(0xfde00000, 0x400),
-        DEFINE_RES_IRQ(gic_iid(0x89)),
-};
-
 #define r8a7778_register_tmu(idx)                       \
         platform_device_register_resndata(              \
                 &platform_bus, "sh_tmu", idx,           \
@@ -94,6 +95,244 @@ static struct resource ether_resources[] = {
                 &sh_tmu##idx##_platform_data,           \
                 sizeof(sh_tmu##idx##_platform_data))
 
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70800, 0x100),
+        DEFINE_RES_MEM(0xffe76000, 0x100),
+};
+
+void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* USB */
+static struct usb_phy *phy;
+
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+
+        usb_phy_init(phy);
+
+        return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+
+        usb_phy_shutdown(phy);
+
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+
+        return 0;
+}
+
+static struct usb_ehci_pdata ehci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+
+static struct resource ehci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+static struct usb_ohci_pdata ohci_pdata __initdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+
+static struct resource ohci_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe70400, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x4c)),
+};
+
+#define USB_PLATFORM_INFO(hci)                                  \
+static struct platform_device_info hci##_info __initdata = {    \
+        .parent         = &platform_bus,                        \
+        .name           = #hci "-platform",                     \
+        .id             = -1,                                   \
+        .res            = hci##_resources,                      \
+        .num_res        = ARRAY_SIZE(hci##_resources),          \
+        .data           = &hci##_pdata,                         \
+        .size_data      = sizeof(hci##_pdata),                  \
+        .dma_mask       = DMA_BIT_MASK(32),                     \
+}
+
+USB_PLATFORM_INFO(ehci);
+USB_PLATFORM_INFO(ohci);
+
+/* Ether */
+static struct resource ether_resources[] = {
+        DEFINE_RES_MEM(0xfde00000, 0x400),
+        DEFINE_RES_IRQ(gic_iid(0x89)),
+};
+
+void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
+                                          ether_resources,
+                                          ARRAY_SIZE(ether_resources),
+                                          pdata, sizeof(*pdata));
+}
+
+/* PFC/GPIO */
+static struct resource pfc_resources[] = {
+        DEFINE_RES_MEM(0xfffc0000, 0x118),
+};
+
+#define R8A7778_GPIO(idx)                                               \
+static struct resource r8a7778_gpio##idx##_resources[] = {              \
+        DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30),              \
+        DEFINE_RES_IRQ(gic_iid(0x87)),                                  \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = {    \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = GPIO_IRQ_BASE(idx),                           \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7778",                                \
+}
+
+R8A7778_GPIO(0);
+R8A7778_GPIO(1);
+R8A7778_GPIO(2);
+R8A7778_GPIO(3);
+R8A7778_GPIO(4);
+
+#define r8a7778_register_gpio(idx)                              \
+        platform_device_register_resndata(                      \
+                &platform_bus, "gpio_rcar", idx,                \
+                r8a7778_gpio##idx##_resources,                  \
+                ARRAY_SIZE(r8a7778_gpio##idx##_resources),      \
+                &r8a7778_gpio##idx##_platform_data,             \
+                sizeof(r8a7778_gpio##idx##_platform_data))
+
+void __init r8a7778_pinmux_init(void)
+{
+        platform_device_register_simple(
+                "pfc-r8a7778", -1,
+                pfc_resources,
+                ARRAY_SIZE(pfc_resources));
+
+        r8a7778_register_gpio(0);
+        r8a7778_register_gpio(1);
+        r8a7778_register_gpio(2);
+        r8a7778_register_gpio(3);
+        r8a7778_register_gpio(4);
+};
+
+/* SDHI */
+static struct resource sdhi_resources[] = {
+        /* SDHI0 */
+        DEFINE_RES_MEM(0xFFE4C000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x77)),
+        /* SDHI1 */
+        DEFINE_RES_MEM(0xFFE4D000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x78)),
+        /* SDHI2 */
+        DEFINE_RES_MEM(0xFFE4F000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x76)),
+};
+
+void __init r8a7778_sdhi_init(int id,
+                              struct sh_mobile_sdhi_info *info)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_resndata(
+                &platform_bus, "sh_mobile_sdhi", id,
+                sdhi_resources + (2 * id), 2,
+                info, sizeof(*info));
+}
+
+/* I2C */
+static struct resource i2c_resources[] __initdata = {
+        /* I2C0 */
+        DEFINE_RES_MEM(0xffc70000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x63)),
+        /* I2C1 */
+        DEFINE_RES_MEM(0xffc71000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6e)),
+        /* I2C2 */
+        DEFINE_RES_MEM(0xffc72000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6c)),
+        /* I2C3 */
+        DEFINE_RES_MEM(0xffc73000, 0x1000),
+        DEFINE_RES_IRQ(gic_iid(0x6d)),
+};
+
+void __init r8a7778_add_i2c_device(int id)
+{
+        BUG_ON(id < 0 || id > 3);
+
+        platform_device_register_simple(
+                "i2c-rcar", id,
+                i2c_resources + (2 * id), 2);
+}
+
+/* HSPI */
+static struct resource hspi_resources[] __initdata = {
+        /* HSPI0 */
+        DEFINE_RES_MEM(0xfffc7000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x5f)),
+        /* HSPI1 */
+        DEFINE_RES_MEM(0xfffc8000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x74)),
+        /* HSPI2 */
+        DEFINE_RES_MEM(0xfffc6000, 0x18),
+        DEFINE_RES_IRQ(gic_iid(0x75)),
+};
+
+void __init r8a7778_add_hspi_device(int id)
+{
+        BUG_ON(id < 0 || id > 2);
+
+        platform_device_register_simple(
+                "sh-hspi", id,
+                hspi_resources + (2 * id), 2);
+}
+
+/* MMC */
+static struct resource mmc_resources[] __initdata = {
+        DEFINE_RES_MEM(0xffe4e000, 0x100),
+        DEFINE_RES_IRQ(gic_iid(0x5d)),
+};
+
+void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info)
+{
+        platform_device_register_resndata(
+                &platform_bus, "sh_mmcif", -1,
+                mmc_resources, ARRAY_SIZE(mmc_resources),
+                info, sizeof(*info));
+}
+
 void __init r8a7778_add_standard_devices(void)
 {
         int i;
@@ -118,12 +357,12 @@ void __init r8a7778_add_standard_devices(void)
         r8a7778_register_tmu(1);
 }
 
-void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
+void __init r8a7778_init_late(void)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
-                                          ether_resources,
-                                          ARRAY_SIZE(ether_resources),
-                                          pdata, sizeof(*pdata));
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+        platform_device_register_full(&ehci_info);
+        platform_device_register_full(&ohci_info);
 }
 
 static struct renesas_intc_irqpin_config irqpin_platform_data = {
@@ -239,6 +478,7 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
         .init_machine   = r8a7778_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
         .dt_compat      = r8a7778_compat_dt,
+        .init_late      = r8a7778_init_late,
 MACHINE_END
 
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index b0b394842ea5..398687761f50 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -32,6 +32,11 @@
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <linux/dma-mapping.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
+#include <linux/pm_runtime.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/r8a7779.h>
@@ -65,11 +70,7 @@ void __init r8a7779_map_io(void)
 }
 
 static struct resource r8a7779_pfc_resources[] = {
-        [0] = {
-                .start  = 0xfffc0000,
-                .end    = 0xfffc023b,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfffc0000, 0x023c),
 };
 
 static struct platform_device r8a7779_pfc_device = {
@@ -81,15 +82,8 @@ static struct platform_device r8a7779_pfc_device = {
 
 #define R8A7779_GPIO(idx, npins) \
 static struct resource r8a7779_gpio##idx##_resources[] = {              \
-        [0] = {                                                         \
-                .start  = 0xffc40000 + 0x1000 * (idx),                  \
-                .end    = 0xffc4002b + 0x1000 * (idx),                  \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        [1] = {                                                         \
-                .start  = gic_iid(0xad + (idx)),                        \
-                .flags  = IORESOURCE_IRQ,                               \
-        }                                                               \
+        DEFINE_RES_MEM(0xffc40000 + (0x1000 * (idx)), 0x002c),          \
+        DEFINE_RES_IRQ(gic_iid(0xad + (idx))),                          \
 };                                                                      \
                                                                         \
 static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = {    \
@@ -394,6 +388,165 @@ static struct platform_device sata_device = {
         },
 };
 
+/* USB PHY */
+static struct resource usb_phy_resources[] __initdata = {
+        [0] = {
+                .start          = 0xffe70800,
+                .end            = 0xffe70900 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+/* USB */
+static struct usb_phy *phy;
+
+static int usb_power_on(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return PTR_ERR(phy);
+
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
+
+        usb_phy_init(phy);
+
+        return 0;
+}
+
+static void usb_power_off(struct platform_device *pdev)
+{
+        if (IS_ERR(phy))
+                return;
+
+        usb_phy_shutdown(phy);
+
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+}
+
+static int ehci_init_internal_buffer(struct usb_hcd *hcd)
+{
+        /*
+         * Below are recommended values from the datasheet;
+         * see [USB :: Setting of EHCI Internal Buffer].
+         */
+        /* EHCI IP internal buffer setting */
+        iowrite32(0x00ff0040, hcd->regs + 0x0094);
+        /* EHCI IP internal buffer enable */
+        iowrite32(0x00000001, hcd->regs + 0x009C);
+
+        return 0;
+}
+
+static struct usb_ehci_pdata ehcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+        .pre_setup      = ehci_init_internal_buffer,
+};
+
+static struct resource ehci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70000,
+                .end    = 0xffe70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ehci0_device = {
+        .name   = "ehci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ehci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci0_resources),
+        .resource       = ehci0_resources,
+};
+
+static struct resource ehci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70000,
+                .end    = 0xfff70400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ehci1_device = {
+        .name   = "ehci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ehci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ehcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ehci1_resources),
+        .resource       = ehci1_resources,
+};
+
+static struct usb_ohci_pdata ohcix_pdata = {
+        .power_on       = usb_power_on,
+        .power_off      = usb_power_off,
+        .power_suspend  = usb_power_off,
+};
+
+static struct resource ohci0_resources[] = {
+        [0] = {
+                .start  = 0xffe70400,
+                .end    = 0xffe70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4c),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ohci0_device = {
+        .name   = "ohci-platform",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ohci0_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci0_resources),
+        .resource       = ohci0_resources,
+};
+
+static struct resource ohci1_resources[] = {
+        [0] = {
+                .start  = 0xfff70400,
+                .end    = 0xfff70800 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_iid(0x4d),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ohci1_device = {
+        .name   = "ohci-platform",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ohci1_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &ohcix_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(ohci1_resources),
+        .resource       = ohci1_resources,
+};
+
 /* Ether */
 static struct resource ether_resources[] = {
         {
@@ -417,7 +570,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = {
         &tmu01_device,
 };
 
-static struct platform_device *r8a7779_late_devices[] __initdata = {
+static struct platform_device *r8a7779_standard_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
         &i2c2_device,
@@ -437,18 +590,26 @@ void __init r8a7779_add_standard_devices(void)
 
         platform_add_devices(r8a7779_devices_dt,
                             ARRAY_SIZE(r8a7779_devices_dt));
-        platform_add_devices(r8a7779_late_devices,
-                            ARRAY_SIZE(r8a7779_late_devices));
+        platform_add_devices(r8a7779_standard_devices,
+                            ARRAY_SIZE(r8a7779_standard_devices));
 }
 
 void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
 {
-        platform_device_register_resndata(&platform_bus, "sh_eth", -1,
+        platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1,
                                           ether_resources,
                                           ARRAY_SIZE(ether_resources),
                                           pdata, sizeof(*pdata));
 }
 
+void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
+{
+        platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
+                                          usb_phy_resources,
+                                          ARRAY_SIZE(usb_phy_resources),
+                                          pdata, sizeof(*pdata));
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak r8a7779_register_twd(void) { }
 
@@ -481,6 +642,23 @@ void __init r8a7779_add_early_devices(void)
          */
 }
 
+static struct platform_device *r8a7779_late_devices[] __initdata = {
+        &ehci0_device,
+        &ehci1_device,
+        &ohci0_device,
+        &ohci1_device,
+};
+
+void __init r8a7779_init_late(void)
+{
+        /* get USB PHY */
+        phy = usb_get_phy(USB_PHY_TYPE_USB2);
+
+        shmobile_init_late();
+        platform_add_devices(r8a7779_late_devices,
+                             ARRAY_SIZE(r8a7779_late_devices));
+}
+
 #ifdef CONFIG_USE_OF
 void __init r8a7779_init_delay(void)
 {
@@ -514,6 +692,7 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
         .init_irq       = r8a7779_init_irq_dt,
         .init_machine   = r8a7779_add_standard_devices_dt,
         .init_time      = shmobile_timer_init,
+        .init_late      = r8a7779_init_late,
         .dt_compat      = r8a7779_compat_dt,
 MACHINE_END
 #endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 49de2d56f86d..28f94752b8ff 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -23,21 +23,55 @@
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_data/irq-renesas-irqc.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r8a7790.h>
 #include <asm/mach/arch.h>
 
-static const struct resource pfc_resources[] = {
+static struct resource pfc_resources[] __initdata = {
         DEFINE_RES_MEM(0xe6060000, 0x250),
-        DEFINE_RES_MEM(0xe6050000, 0x5050),
 };
 
+#define R8A7790_GPIO(idx)                                               \
+static struct resource r8a7790_gpio##idx##_resources[] __initdata = {   \
+        DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
+        DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
+};                                                                      \
+                                                                        \
+static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data __initdata = { \
+        .gpio_base      = 32 * (idx),                                   \
+        .irq_base       = 0,                                            \
+        .number_of_pins = 32,                                           \
+        .pctl_name      = "pfc-r8a7790",                                \
+        .has_both_edge_trigger = 1,                                     \
+};                                                                      \
+
+R8A7790_GPIO(0);
+R8A7790_GPIO(1);
+R8A7790_GPIO(2);
+R8A7790_GPIO(3);
+R8A7790_GPIO(4);
+R8A7790_GPIO(5);
+
+#define r8a7790_register_gpio(idx)                                      \
+        platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
+                r8a7790_gpio##idx##_resources,                          \
+                ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
+                &r8a7790_gpio##idx##_platform_data,                     \
+                sizeof(r8a7790_gpio##idx##_platform_data))
+
 void __init r8a7790_pinmux_init(void)
 {
         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
                                         ARRAY_SIZE(pfc_resources));
+        r8a7790_register_gpio(0);
+        r8a7790_register_gpio(1);
+        r8a7790_register_gpio(2);
+        r8a7790_register_gpio(3);
+        r8a7790_register_gpio(4);
+        r8a7790_register_gpio(5);
 }
 
 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
@@ -64,12 +98,20 @@ void __init r8a7790_pinmux_init(void)
 [index] = {                                             \
         SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
         .scbrr_algo_id  = SCBRR_ALGO_2,                 \
-        .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,      \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
+}
+
+#define HSCIF_DATA(index, baseaddr, irq)                \
+[index] = {                                             \
+        SCIF_COMMON(PORT_HSCIF, baseaddr, irq),         \
+        .scbrr_algo_id  = SCBRR_ALGO_6,                 \
+        .scscr = SCSCR_RE | SCSCR_TE,   \
 }
 
-enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
+enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1,
+       HSCIF0, HSCIF1 };
 
-static const struct plat_sci_port scif[] = {
+static struct plat_sci_port scif[] __initdata = {
         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
@@ -78,6 +120,8 @@ static const struct plat_sci_port scif[] = {
         SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
         SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
         SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
+        HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */
+        HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */
 };
 
 static inline void r8a7790_register_scif(int idx)
@@ -86,11 +130,11 @@ static inline void r8a7790_register_scif(int idx)
                                       sizeof(struct plat_sci_port));
 }
 
-static struct renesas_irqc_config irqc0_data = {
+static struct renesas_irqc_config irqc0_data __initdata = {
         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 };
 
-static struct resource irqc0_resources[] = {
+static struct resource irqc0_resources[] __initdata = {
         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
@@ -115,6 +159,8 @@ void __init r8a7790_add_standard_devices(void)
         r8a7790_register_scif(SCIFA2);
         r8a7790_register_scif(SCIF0);
         r8a7790_register_scif(SCIF1);
+        r8a7790_register_scif(HSCIF0);
+        r8a7790_register_scif(HSCIF1);
         r8a7790_register_irqc(0);
 }
 
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 9696f3646864..96e7ca1e4e11 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -288,12 +288,7 @@ static struct sh_timer_config tmu00_platform_data = {
 };
 
 static struct resource tmu00_resources[] = {
-        [0] = {
-                .name   = "TMU00",
-                .start  = 0xfff60008,
-                .end    = 0xfff60013,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
                 .flags  = IORESOURCE_IRQ,
@@ -318,12 +313,7 @@ static struct sh_timer_config tmu01_platform_data = {
 };
 
 static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"),
         [1] = {
                 .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
                 .flags  = IORESOURCE_IRQ,
@@ -341,12 +331,7 @@ static struct platform_device tmu01_device = {
 };
 
 static struct resource i2c0_resources[] = {
-        [0] = {
-                .name   = "IIC0",
-                .start  = 0xe6820000,
-                .end    = 0xe6820425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"),
         [1] = {
                 .start  = gic_spi(167),
                 .end    = gic_spi(170),
@@ -355,12 +340,7 @@ static struct resource i2c0_resources[] = {
 };
 
 static struct resource i2c1_resources[] = {
-        [0] = {
-                .name   = "IIC1",
-                .start  = 0xe6822000,
-                .end    = 0xe6822425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"),
         [1] = {
                 .start  = gic_spi(51),
                 .end    = gic_spi(54),
@@ -369,12 +349,7 @@ static struct resource i2c1_resources[] = {
 };
 
 static struct resource i2c2_resources[] = {
-        [0] = {
-                .name   = "IIC2",
-                .start  = 0xe6824000,
-                .end    = 0xe6824425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"),
         [1] = {
                 .start  = gic_spi(171),
                 .end    = gic_spi(174),
@@ -383,12 +358,7 @@ static struct resource i2c2_resources[] = {
 };
 
 static struct resource i2c3_resources[] = {
-        [0] = {
-                .name   = "IIC3",
-                .start  = 0xe6826000,
-                .end    = 0xe6826425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"),
         [1] = {
                 .start  = gic_spi(183),
                 .end    = gic_spi(186),
@@ -397,12 +367,7 @@ static struct resource i2c3_resources[] = {
 };
 
 static struct resource i2c4_resources[] = {
-        [0] = {
-                .name   = "IIC4",
-                .start  = 0xe6828000,
-                .end    = 0xe6828425 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"),
         [1] = {
                 .start  = gic_spi(187),
                 .end    = gic_spi(190),
@@ -623,12 +588,7 @@ static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
 };
 
 static struct resource sh73a0_dmae_resources[] = {
-        {
-                /* Registers including DMAOR and channels including DMARSx */
-                .start  = 0xfe000020,
-                .end    = 0xfe008a00 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM(0xfe000020, 0x89e0),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(129),
@@ -727,18 +687,10 @@ static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
 
 /* Resource order important! */
 static struct resource sh73a0_mpdma_resources[] = {
-        {
-                /* Channel registers and DMAOR */
-                .start  = 0xec618020,
-                .end    = 0xec61828f,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                /* DMARSx */
-                .start  = 0xec619000,
-                .end    = 0xec61900b,
-                .flags  = IORESOURCE_MEM,
-        },
+        /* Channel registers and DMAOR */
+        DEFINE_RES_MEM(0xec618020, 0x270),
+        /* DMARSx */
+        DEFINE_RES_MEM(0xec619000, 0xc),
         {
                 .name   = "error_irq",
                 .start  = gic_spi(181),
@@ -785,12 +737,7 @@ static struct platform_device pmu_device = {
 
 /* an IPMMU module for ICB */
 static struct resource ipmmu_resources[] = {
-        [0] = {
-                .name   = "IPMMU",
-                .start  = 0xfe951000,
-                .end    = 0xfe9510ff,
-                .flags  = IORESOURCE_MEM,
-        },
+        DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"),
 };
 
 static const char * const ipmmu_dev_names[] = {
@@ -982,11 +929,17 @@ void __init sh73a0_add_standard_devices(void)
                             ARRAY_SIZE(sh73a0_late_devices));
 }
 
+void __init sh73a0_init_delay(void)
+{
+        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
+}
+
 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
 void __init __weak sh73a0_register_twd(void) { }
 
 void __init sh73a0_earlytimer_init(void)
 {
+        sh73a0_init_delay();
         sh73a0_clock_init();
         shmobile_earlytimer_init();
         sh73a0_register_twd();
@@ -1005,17 +958,14 @@ void __init sh73a0_add_early_devices(void)
 
 #ifdef CONFIG_USE_OF
 
-void __init sh73a0_init_delay(void)
-{
-        shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
-}
-
 static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
         {},
 };
 
 void __init sh73a0_add_standard_devices_dt(void)
 {
+        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
+
         /* clocks are setup late during boot in the case of DT */
         sh73a0_clock_init();
 
@@ -1023,6 +973,9 @@ void __init sh73a0_add_standard_devices_dt(void)
                              ARRAY_SIZE(sh73a0_devices_dt));
         of_platform_populate(NULL, of_default_bus_match_table,
                              sh73a0_auxdata_lookup, NULL);
+
+        /* Instantiate cpufreq-cpu0 */
+        platform_device_register_full(&devinfo);
 }
 
 static const char *sh73a0_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index a9df53b69ab8..53f4840e4949 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -40,7 +40,10 @@
         .global sh7372_resume_core_standby_sysc
 sh7372_resume_core_standby_sysc:
         ldr     pc, 1f
-1:      .long   cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+
+        .globl  sh7372_cpu_resume
+sh7372_cpu_resume:
+1:      .space  4
 
 #define SPDCR 0xe6180008
 
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index e38691b4d0dd..80991b35f4ac 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
 {
         scu_enable(shmobile_scu_base);
 
-        /* Tell ROM loader about our vector (in headsmp-scu.S) */
-        emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
+        /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
+        emev2_set_boot_vector(__pa(shmobile_boot_vector));
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
         /* enable cache coherency on booting CPU */
         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index a853bf182ed5..526cfaae81c1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
 {
         scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-scu.S) */
-        __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
+        /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
+        __raw_writel(__pa(shmobile_boot_vector), AVECR);
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
         /* enable cache coherency on booting CPU */
         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 496592b6c763..d613113a04bd 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
 {
         scu_enable(shmobile_scu_base);
 
-        /* Map the reset vector (in headsmp-scu.S) */
+        /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
         __raw_writel(0, APARMBAREA);      /* 4k */
-        __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
+        __raw_writel(__pa(shmobile_boot_vector), SBAR);
+        shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
+        shmobile_boot_arg = (unsigned long)shmobile_scu_base;
 
         /* enable cache coherency on booting CPU */
         scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 566e804d4036..dd86db467521 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -7,11 +7,11 @@ config ARCH_SOCFPGA
         select CLKDEV_LOOKUP
         select COMMON_CLK
         select CPU_V7
-        select DW_APB_TIMER
         select DW_APB_TIMER_OF
         select GENERIC_CLOCKEVENTS
         select GPIO_PL061 if GPIOLIB
         select HAVE_ARM_SCU
         select HAVE_SMP
+        select MFD_SYSCON
         select SPARSE_IRQ
         select USE_OF
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a051359f02..8ea11b472b91 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -14,7 +14,6 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#include <linux/dw_apb_timer.h>
 #include <linux/clk-provider.h>
 #include <linux/irqchip.h>
 #include <linux/of_address.h>
@@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
         .smp            = smp_ops(socfpga_smp_ops),
         .map_io         = socfpga_map_io,
         .init_irq       = socfpga_init_irq,
-        .init_time      = dw_apb_timer_init,
         .init_machine   = socfpga_cyclone5_init,
         .restart        = socfpga_cyclone5_restart,
         .dt_compat      = altera_dt_match,
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c
index 9eaac2c881ea..7ad003001ab7 100644
--- a/arch/arm/mach-spear/spear1310.c
+++ b/arch/arm/mach-spear/spear1310.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr1310: " fmt
 
 #include <linux/amba/pl022.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <linux/pata_arasan_cf_data.h>
 #include <asm/mach/arch.h>
@@ -60,7 +59,6 @@ static void __init spear1310_map_io(void)
 DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree")
         .smp            =       smp_ops(spear13xx_smp_ops),
         .map_io         =       spear1310_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear13xx_timer_init,
         .init_machine   =       spear1310_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index a04a7fe76f71..3fb683424729 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -17,7 +17,6 @@
 #include <linux/amba/serial.h>
 #include <linux/delay.h>
 #include <linux/of_platform.h>
-#include <linux/irqchip.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
 #include <mach/spear.h>
@@ -155,7 +154,6 @@ static const char * const spear1340_dt_board_compat[] = {
 DT_MACHINE_START(SPEAR1340_DT, "ST SPEAr1340 SoC with Flattened Device Tree")
         .smp            =       smp_ops(spear13xx_smp_ops),
         .map_io         =       spear13xx_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear13xx_timer_init,
         .init_machine   =       spear1340_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear300.c b/arch/arm/mach-spear/spear300.c
index bac56e845f7a..b52e48f342f4 100644
--- a/arch/arm/mach-spear/spear300.c
+++ b/arch/arm/mach-spear/spear300.c
@@ -14,7 +14,6 @@
 #define pr_fmt(fmt) "SPEAr300: " fmt
 
 #include <linux/amba/pl08x.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -212,7 +211,6 @@ static void __init spear300_map_io(void)
 
 DT_MACHINE_START(SPEAR300_DT, "ST SPEAr300 SoC with Flattened Device Tree")
         .map_io         =       spear300_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear3xx_timer_init,
         .init_machine   =       spear300_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear310.c b/arch/arm/mach-spear/spear310.c
index 6ffbc63d516d..ed2029db391f 100644
--- a/arch/arm/mach-spear/spear310.c
+++ b/arch/arm/mach-spear/spear310.c
@@ -15,7 +15,6 @@
 
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include "generic.h"
@@ -254,7 +253,6 @@ static void __init spear310_map_io(void)
 
 DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree")
         .map_io         =       spear310_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear3xx_timer_init,
         .init_machine   =       spear310_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear320.c b/arch/arm/mach-spear/spear320.c
index 6eb3eec65f96..bf634b32a930 100644
--- a/arch/arm/mach-spear/spear320.c
+++ b/arch/arm/mach-spear/spear320.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/amba/serial.h>
-#include <linux/irqchip.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -269,7 +268,6 @@ static void __init spear320_map_io(void)
 
 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
         .map_io         =       spear320_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear3xx_timer_init,
         .init_machine   =       spear320_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-spear/spear6xx.c b/arch/arm/mach-spear/spear6xx.c
index ec8eefbbdfad..8b0295a41226 100644
--- a/arch/arm/mach-spear/spear6xx.c
+++ b/arch/arm/mach-spear/spear6xx.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl08x.h>
 #include <linux/clk.h>
 #include <linux/err.h>
-#include <linux/irqchip.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
@@ -423,7 +422,6 @@ static const char *spear600_dt_board_compat[] = {
 
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
         .map_io         =       spear6xx_map_io,
-        .init_irq       =       irqchip_init,
         .init_time      =       spear6xx_timer_init,
         .init_machine   =       spear600_dt_init,
         .restart        =       spear_restart,
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
new file mode 100644
index 000000000000..d04e3bfe1918
--- /dev/null
+++ b/arch/arm/mach-sti/Kconfig
@@ -0,0 +1,45 @@
+menuconfig ARCH_STI
+        bool "STMicroelectronics Consumer Electronics SOCs with Device Trees" if ARCH_MULTI_V7
+        select GENERIC_CLOCKEVENTS
+        select CLKDEV_LOOKUP
+        select ARM_GIC
+        select ARM_GLOBAL_TIMER
+        select PINCTRL
+        select PINCTRL_ST
+        select MFD_SYSCON
+        select MIGHT_HAVE_CACHE_L2X0
+        select HAVE_SMP
+        select HAVE_ARM_SCU if SMP
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_ERRATA_720789
+        select ARM_ERRATA_754322
+        select PL310_ERRATA_753970 if CACHE_PL310
+        select PL310_ERRATA_769419 if CACHE_PL310
+        help
+          Include support for STiH41x SOCs like STiH415/416 using the device tree
+          for discovery
+          More information at Documentation/arm/STiH41x and
+          at Documentation/devicetree
+
+
+if ARCH_STI
+
+config SOC_STIH415
+        bool "STiH415 STMicroelectronics Consumer Electronics family"
+        default y
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH415 parts, primarily targetted at set-top-box
+          and other digital audio/video applications using Flattned Device
+          Trees.
+
+config SOC_STIH416
+        bool "STiH416 STMicroelectronics Consumer Electronics family"
+        default y
+        help
+          This enables support for STMicroelectronics Digital Consumer
+          Electronics family StiH416 parts, primarily targetted at set-top-box
+          and other digital audio/video applications using Flattened Device
+          Trees.
+
+endif
diff --git a/arch/arm/mach-sti/Makefile b/arch/arm/mach-sti/Makefile
new file mode 100644
index 000000000000..acb330916333
--- /dev/null
+++ b/arch/arm/mach-sti/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_STI)          += board-dt.o
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
new file mode 100644
index 000000000000..8fe6f0c46480
--- /dev/null
+++ b/arch/arm/mach-sti/board-dt.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ * Author(s): Srinivas Kandagatla <srinivas.kandagatla@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
+#include <linux/irq.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+
+#include "smp.h"
+
+void __init stih41x_l2x0_init(void)
+{
+        u32 way_size = 0x4;
+        u32 aux_ctrl;
+        /* may be this can be encoded in macros like BIT*() */
+        aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
+                (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
+                (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
+                (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
+
+        l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+}
+
+static void __init stih41x_timer_init(void)
+{
+        of_clk_init(NULL);
+        clocksource_of_init();
+        stih41x_l2x0_init();
+}
+
+static const char *stih41x_dt_match[] __initdata = {
+        "st,stih415",
+        "st,stih416",
+        NULL
+};
+
+DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
+        .init_time      = stih41x_timer_init,
+        .smp            = smp_ops(sti_smp_ops),
+        .dt_compat      = stih41x_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-sti/headsmp.S b/arch/arm/mach-sti/headsmp.S
new file mode 100644
index 000000000000..78ebc7559f53
--- /dev/null
+++ b/arch/arm/mach-sti/headsmp.S
@@ -0,0 +1,44 @@
+/*
+ *  arch/arm/mach-sti/headsmp.S
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        __INIT
+
+/*
+ * ST specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(sti_secondary_startup)
+        mrc     p15, 0, r0, c0, c0, 5
+        and     r0, r0, #15
+        adr     r4, 1f
+        ldmia   r4, {r5, r6}
+        sub     r4, r4, r5
+        add     r6, r6, r4
+pen:    ldr     r7, [r6]
+        cmp     r7, r0
+        bne     pen
+
+        /*
+         * we've been released from the holding pen: secondary_stack
+         * should now contain the SVC stack for this core
+         */
+        b       secondary_startup
+
+1:      .long   .
+        .long   pen_release
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c
new file mode 100644
index 000000000000..977a863468fc
--- /dev/null
+++ b/arch/arm/mach-sti/platsmp.c
@@ -0,0 +1,117 @@
+/*
+ *  arch/arm/mach-sti/platsmp.c
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+#include <asm/smp_scu.h>
+
+#include "smp.h"
+
+static void __cpuinit write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
+        outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit sti_secondary_init(unsigned int cpu)
+{
+        trace_hardirqs_off();
+
+        /*
+         * let the primary processor know we're out of the
+         * pen, then head off into the C entry point
+         */
+        write_pen_release(-1);
+
+        /*
+         * Synchronise with the boot thread.
+         */
+        spin_lock(&boot_lock);
+        spin_unlock(&boot_lock);
+}
+
+int __cpuinit sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        unsigned long timeout;
+
+        /*
+         * set synchronisation state between this boot processor
+         * and the secondary one
+         */
+        spin_lock(&boot_lock);
+
+        /*
+         * The secondary processor is waiting to be released from
+         * the holding pen - release it, then wait for it to flag
+         * that it has been released by resetting pen_release.
+         *
+         * Note that "pen_release" is the hardware CPU ID, whereas
+         * "cpu" is Linux's internal ID.
+         */
+        write_pen_release(cpu_logical_map(cpu));
+
+        /*
+         * Send the secondary CPU a soft interrupt, thereby causing
+         * it to jump to the secondary entrypoint.
+         */
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+        timeout = jiffies + (1 * HZ);
+        while (time_before(jiffies, timeout)) {
+                smp_rmb();
+                if (pen_release == -1)
+                        break;
+
+                udelay(10);
+        }
+
+        /*
+         * now the secondary core is starting up let it run its
+         * calibrations, then wait for it to finish
+         */
+        spin_unlock(&boot_lock);
+
+        return pen_release != -1 ? -ENOSYS : 0;
+}
+
+void __init sti_smp_prepare_cpus(unsigned int max_cpus)
+{
+        void __iomem *scu_base = NULL;
+        struct device_node *np = of_find_compatible_node(
+                                        NULL, NULL, "arm,cortex-a9-scu");
+        if (np) {
+                scu_base = of_iomap(np, 0);
+                scu_enable(scu_base);
+                of_node_put(np);
+        }
+}
+
+struct smp_operations __initdata sti_smp_ops = {
+        .smp_prepare_cpus       = sti_smp_prepare_cpus,
+        .smp_secondary_init     = sti_secondary_init,
+        .smp_boot_secondary     = sti_boot_secondary,
+};
diff --git a/arch/arm/mach-sti/smp.h b/arch/arm/mach-sti/smp.h
new file mode 100644
index 000000000000..1871b72b1a7e
--- /dev/null
+++ b/arch/arm/mach-sti/smp.h
@@ -0,0 +1,17 @@
+/*
+ *  arch/arm/mach-sti/smp.h
+ *
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
+ *              http://www.st.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_STI_SMP_H
+#define __MACH_STI_SMP_H
+
+extern struct smp_operations    sti_smp_ops;
+
+#endif
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 706ce35396b8..84485a10fc3a 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -14,7 +14,6 @@
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
@@ -26,8 +25,6 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 
-#include "sunxi.h"
-
 #define SUN4I_WATCHDOG_CTRL_REG         0x00
 #define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
 #define SUN4I_WATCHDOG_MODE_REG         0x04
@@ -81,20 +78,6 @@ static void sunxi_setup_restart(void)
         arm_pm_restart = of_id->data;
 }
 
-static struct map_desc sunxi_io_desc[] __initdata = {
-        {
-                .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
-                .pfn            = __phys_to_pfn(SUNXI_REGS_PHYS_BASE),
-                .length         = SUNXI_REGS_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-void __init sunxi_map_io(void)
-{
-        iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
-}
-
 static void __init sunxi_timer_init(void)
 {
         sunxi_init_clocks();
@@ -110,14 +93,13 @@ static void __init sunxi_dt_init(void)
 
 static const char * const sunxi_board_dt_compat[] = {
         "allwinner,sun4i-a10",
+        "allwinner,sun5i-a10s",
         "allwinner,sun5i-a13",
         NULL,
 };
 
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
         .init_machine   = sunxi_dt_init,
-        .map_io         = sunxi_map_io,
-        .init_irq       = irqchip_init,
         .init_time      = sunxi_timer_init,
         .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-sunxi/sunxi.h b/arch/arm/mach-sunxi/sunxi.h
deleted file mode 100644
index 33b58712adea..000000000000
--- a/arch/arm/mach-sunxi/sunxi.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Generic definitions for Allwinner SunXi SoCs
- *
- * Copyright (C) 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_SUNXI_H
-#define __MACH_SUNXI_H
-
-#define SUNXI_REGS_PHYS_BASE    0x01c00000
-#define SUNXI_REGS_VIRT_BASE    IOMEM(0xf1c00000)
-#define SUNXI_REGS_SIZE         (SZ_2M + SZ_1M)
-
-#endif /* __MACH_SUNXI_H */
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc36dfe..ef3a8da49b2d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -28,7 +28,6 @@ config ARCH_TEGRA_2x_SOC
         select ARM_ERRATA_754327 if SMP
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA20
@@ -46,7 +45,6 @@ config ARCH_TEGRA_3x_SOC
         select ARM_ERRATA_754322
         select ARM_ERRATA_764369 if SMP
         select ARM_GIC
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA30
@@ -60,10 +58,9 @@ config ARCH_TEGRA_3x_SOC
 
 config ARCH_TEGRA_114_SOC
         bool "Enable support for Tegra114 family"
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select ARM_GIC
         select ARM_L1_CACHE_SHIFT_6
-        select CPU_FREQ_TABLE if CPU_FREQ
         select CPU_V7
         select PINCTRL
         select PINCTRL_TEGRA114
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d011f0ad49c4..98b184efc110 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += tegra114_speedo.o
+obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += sleep-tegra30.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 9f852c6fe5b9..b25153e2ebaa 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -23,12 +23,13 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/irqchip.h>
-#include <linux/clk/tegra.h>
+#include <linux/clk-provider.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
 #include "board.h"
 #include "common.h"
+#include "cpuidle.h"
 #include "fuse.h"
 #include "iomap.h"
 #include "irq.h"
@@ -59,7 +60,7 @@ u32 tegra_uart_config[4] = {
 #ifdef CONFIG_OF
 void __init tegra_dt_init_irq(void)
 {
-        tegra_clocks_init();
+        of_clk_init(NULL);
         tegra_pmc_init();
         tegra_init_irq();
         irqchip_init();
@@ -108,5 +109,6 @@ void __init tegra_init_early(void)
 void __init tegra_init_late(void)
 {
         tegra_init_suspend();
+        tegra_cpuidle_init();
         tegra_powergate_debugfs_init();
 }
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 5900cc44f780..32f8eb3fe344 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,3 +2,4 @@ extern struct smp_operations tegra_smp_ops;
 
 extern int tegra_cpu_kill(unsigned int cpu);
 extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 0cdba8de8c77..706aa4215c36 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -177,7 +177,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
                                     struct cpuidle_driver *drv,
                                     int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
         bool entered_lp2 = false;
 
         if (tegra_pending_sgi())
@@ -193,16 +192,16 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 
         local_fiq_disable();
 
-        tegra_set_cpu_in_lp2(cpu);
+        tegra_set_cpu_in_lp2();
         cpu_pm_enter();
 
-        if (cpu == 0)
+        if (dev->cpu == 0)
                 entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
         else
                 entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
 
         cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
 
         local_fiq_enable();
 
@@ -214,8 +213,5 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
 
 int __init tegra20_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra20_tear_down_cpu;
-#endif
         return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
 }
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 3cf9aca5f3ea..ed2a2a7bae4d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -114,16 +114,15 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
                             struct cpuidle_driver *drv,
                             int index)
 {
-        u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
         bool entered_lp2 = false;
         bool last_cpu;
 
         local_fiq_disable();
 
-        last_cpu = tegra_set_cpu_in_lp2(cpu);
+        last_cpu = tegra_set_cpu_in_lp2();
         cpu_pm_enter();
 
-        if (cpu == 0) {
+        if (dev->cpu == 0) {
                 if (last_cpu)
                         entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
                                                                      index);
@@ -134,7 +133,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
         }
 
         cpu_pm_exit();
-        tegra_clear_cpu_in_lp2(cpu);
+        tegra_clear_cpu_in_lp2();
 
         local_fiq_enable();
 
@@ -146,8 +145,5 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
 
 int __init tegra30_cpuidle_init(void)
 {
-#ifdef CONFIG_PM_SLEEP
-        tegra_tear_down_cpu = tegra30_tear_down_cpu;
-#endif
         return cpuidle_register(&tegra_idle_driver, NULL);
 }
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index 4b744c4661e2..e85973cef037 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,25 +27,20 @@
 #include "fuse.h"
 #include "cpuidle.h"
 
-static int __init tegra_cpuidle_init(void)
+void __init tegra_cpuidle_init(void)
 {
-        int ret;
-
         switch (tegra_chip_id) {
         case TEGRA20:
-                ret = tegra20_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra20_cpuidle_init();
                 break;
         case TEGRA30:
-                ret = tegra30_cpuidle_init();
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra30_cpuidle_init();
                 break;
         case TEGRA114:
-                ret = tegra114_cpuidle_init();
-                break;
-        default:
-                ret = -ENODEV;
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
+                        tegra114_cpuidle_init();
                 break;
         }
-
-        return ret;
 }
-device_initcall(tegra_cpuidle_init);
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index d733f75d0208..9ec2c1ab0fa4 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -17,22 +17,13 @@
 #ifndef __MACH_TEGRA_CPUIDLE_H
 #define __MACH_TEGRA_CPUIDLE_H
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+#ifdef CONFIG_CPU_IDLE
 int tegra20_cpuidle_init(void);
-#else
-static inline int tegra20_cpuidle_init(void) { return -ENODEV; }
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
 int tegra30_cpuidle_init(void);
-#else
-static inline int tegra30_cpuidle_init(void) { return -ENODEV; }
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
 int tegra114_cpuidle_init(void);
+void tegra_cpuidle_init(void);
 #else
-static inline int tegra114_cpuidle_init(void) { return -ENODEV; }
+static inline void tegra_cpuidle_init(void) {}
 #endif
 
 #endif
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 67eab56699bd..7a29bae799a7 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -25,6 +25,7 @@
 #define FLOW_CTRL_WAITEVENT             (2 << 29)
 #define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
 #define FLOW_CTRL_JTAG_RESUME           (1 << 28)
+#define FLOW_CTRL_SCLK_RESUME           (1 << 27)
 #define FLOW_CTRL_HALT_CPU_IRQ          (1 << 10)
 #define FLOW_CTRL_HALT_CPU_FIQ          (1 << 8)
 #define FLOW_CTRL_CPU0_CSR              0x8
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index aacc00d05980..def79683bef6 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -19,16 +19,6 @@
 #ifndef __MACH_TEGRA_FUSE_H
 #define __MACH_TEGRA_FUSE_H
 
-enum tegra_revision {
-        TEGRA_REVISION_UNKNOWN = 0,
-        TEGRA_REVISION_A01,
-        TEGRA_REVISION_A02,
-        TEGRA_REVISION_A03,
-        TEGRA_REVISION_A03p,
-        TEGRA_REVISION_A04,
-        TEGRA_REVISION_MAX,
-};
-
 #define SKU_ID_T20      8
 #define SKU_ID_T25SE    20
 #define SKU_ID_AP25     23
@@ -40,6 +30,17 @@ enum tegra_revision {
 #define TEGRA30         0x30
 #define TEGRA114        0x35
 
+#ifndef __ASSEMBLY__
+enum tegra_revision {
+        TEGRA_REVISION_UNKNOWN = 0,
+        TEGRA_REVISION_A01,
+        TEGRA_REVISION_A02,
+        TEGRA_REVISION_A03,
+        TEGRA_REVISION_A03p,
+        TEGRA_REVISION_A04,
+        TEGRA_REVISION_MAX,
+};
+
 extern int tegra_sku_id;
 extern int tegra_cpu_process_id;
 extern int tegra_core_process_id;
@@ -72,5 +73,6 @@ void tegra114_init_speedo_data(void);
 #else
 static inline void tegra114_init_speedo_data(void) {}
 #endif
+#endif /* __ASSEMBLY__ */
 
 #endif
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index 184914a68d73..a52c10e0a857 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -46,6 +46,17 @@ void __ref tegra_cpu_die(unsigned int cpu)
         BUG();
 }
 
+int tegra_cpu_disable(unsigned int cpu)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+        case TEGRA30:
+                return cpu == 0 ? -EPERM : 0;
+        default:
+                return 0;
+        }
+}
+
 void __init tegra_hotplug_init(void)
 {
         if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
@@ -55,4 +66,6 @@ void __init tegra_hotplug_init(void)
                 tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
         if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
                 tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index fad4226ef710..24db4ac428ae 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -140,8 +140,31 @@ remove_clamps:
 
 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        int ret = 0;
+
         cpu = cpu_logical_map(cpu);
-        return tegra_pmc_cpu_power_on(cpu);
+
+        if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
+                /*
+                 * Warm boot flow
+                 * The flow controller in charge of the power state and
+                 * control for each CPU.
+                 */
+                /* set SCLK as event trigger for flow controller */
+                flowctrl_write_cpu_csr(cpu, 1);
+                flowctrl_write_cpu_halt(cpu,
+                                FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME);
+        } else {
+                /*
+                 * Cold boot flow
+                 * The CPU is powered up by toggling PMC directly. It will
+                 * also initial power state in flow controller. After that,
+                 * the CPU's power state is maintained by flow controller.
+                 */
+                ret = tegra_pmc_cpu_power_on(cpu);
+        }
+
+        return ret;
 }
 
 static int __cpuinit tegra_boot_secondary(unsigned int cpu,
@@ -173,5 +196,6 @@ struct smp_operations tegra_smp_ops __initdata = {
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = tegra_cpu_kill,
         .cpu_die                = tegra_cpu_die,
+        .cpu_disable            = tegra_cpu_disable,
 #endif
 };
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 45cf52c7e528..94e69bee3da5 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -44,6 +44,20 @@
 static DEFINE_SPINLOCK(tegra_lp2_lock);
 void (*tegra_tear_down_cpu)(void);
 
+static void tegra_tear_down_cpu_init(void)
+{
+        switch (tegra_chip_id) {
+        case TEGRA20:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                        tegra_tear_down_cpu = tegra20_tear_down_cpu;
+                break;
+        case TEGRA30:
+                if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
+                        tegra_tear_down_cpu = tegra30_tear_down_cpu;
+                break;
+        }
+}
+
 /*
  * restore_cpu_complex
  *
@@ -91,8 +105,9 @@ static void suspend_cpu_complex(void)
         flowctrl_cpu_suspend_enter(cpu);
 }
 
-void tegra_clear_cpu_in_lp2(int phy_cpu_id)
+void tegra_clear_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
         u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
 
         spin_lock(&tegra_lp2_lock);
@@ -103,8 +118,9 @@ void tegra_clear_cpu_in_lp2(int phy_cpu_id)
         spin_unlock(&tegra_lp2_lock);
 }
 
-bool tegra_set_cpu_in_lp2(int phy_cpu_id)
+bool tegra_set_cpu_in_lp2(void)
 {
+        int phy_cpu_id = cpu_logical_map(smp_processor_id());
         bool last_cpu = false;
         cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
         u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -192,7 +208,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
         suspend_cpu_complex();
         switch (mode) {
         case TEGRA_SUSPEND_LP2:
-                tegra_set_cpu_in_lp2(0);
+                tegra_set_cpu_in_lp2();
                 break;
         default:
                 break;
@@ -202,7 +218,7 @@ static int __cpuinit tegra_suspend_enter(suspend_state_t state)
 
         switch (mode) {
         case TEGRA_SUSPEND_LP2:
-                tegra_clear_cpu_in_lp2(0);
+                tegra_clear_cpu_in_lp2();
                 break;
         default:
                 break;
@@ -224,6 +240,7 @@ void __init tegra_init_suspend(void)
         if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE)
                 return;
 
+        tegra_tear_down_cpu_init();
         tegra_pmc_suspend_init();
 
         suspend_set_ops(&tegra_suspend_ops);
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 778a4aa7c3fa..94c4b9d9077c 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -28,8 +28,8 @@ extern unsigned long l2x0_saved_regs_addr;
 void save_cpu_arch_register(void);
 void restore_cpu_arch_register(void);
 
-void tegra_clear_cpu_in_lp2(int phy_cpu_id);
-bool tegra_set_cpu_in_lp2(int phy_cpu_id);
+void tegra_clear_cpu_in_lp2(void);
+bool tegra_set_cpu_in_lp2(void);
 
 void tegra_idle_lp2_last(void);
 extern void (*tegra_tear_down_cpu)(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 32360e540ce6..eb3fa4aee0e4 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -234,7 +234,7 @@ static const struct of_device_id matches[] __initconst = {
         { }
 };
 
-static void tegra_pmc_parse_dt(void)
+static void __init tegra_pmc_parse_dt(void)
 {
         struct device_node *np;
         u32 prop;
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index e6de88a2ea06..39dc9e7834f3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -22,11 +22,11 @@
 #include <asm/hardware/cache-l2x0.h>
 
 #include "flowctrl.h"
+#include "fuse.h"
 #include "iomap.h"
 #include "reset.h"
 #include "sleep.h"
 
-#define APB_MISC_GP_HIDREV      0x804
 #define PMC_SCRATCH41   0x140
 
 #define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
@@ -38,34 +38,40 @@
  *        CPU boot vector when restarting the a CPU following
  *        an LP2 transition. Also branched to by LP0 and LP1 resume after
  *        re-enabling sdram.
+ *
+ *      r6: SoC ID
  */
 ENTRY(tegra_resume)
         bl      v7_invalidate_l1
 
         cpu_id  r0
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
+        cmp     r6, #TEGRA114
+        beq     no_cpu0_chk
+
         cmp     r0, #0                          @ CPU0?
  THUMB( it      ne )
         bne     cpu_resume                      @ no
+no_cpu0_chk:
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         beq     1f                              @ Yes
         /* Clear the flow controller flags for this CPU. */
-        mov32   r2, TEGRA_FLOW_CTRL_BASE + FLOW_CTRL_CPU0_CSR   @ CPU0 CSR
-        ldr     r1, [r2]
+        cpu_to_csr_reg r1, r0
+        mov32   r2, TEGRA_FLOW_CTRL_BASE
+        ldr     r1, [r2, r1]
         /* Clear event & intr flag */
         orr     r1, r1, \
                 #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        movw    r0, #0x0FFD     @ enable, cluster_switch, immed, & bitmaps
+        movw    r0, #0x3FFD     @ enable, cluster_switch, immed, bitmaps
+                                @ & ext flags for CPU power mgnt
         bic     r1, r1, r0
         str     r1, [r2]
 1:
-#endif
 
+        check_cpu_part_num 0xc09, r8, r9
+        bne     not_ca9
 #ifdef CONFIG_HAVE_ARM_SCU
         /* enable SCU */
         mov32   r0, TEGRA_ARM_PERIF_BASE
@@ -76,6 +82,7 @@ ENTRY(tegra_resume)
 
         /* L2 cache resume & re-enable */
         l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+not_ca9:
 
         b       cpu_resume
 ENDPROC(tegra_resume)
@@ -98,7 +105,7 @@ ENTRY(__tegra_cpu_reset_handler_start)
  * Register usage within the reset handler:
  *
  *      Others: scratch
- *      R6  = SoC ID << 8
+ *      R6  = SoC ID
  *      R7  = CPU present (to the OS) mask
  *      R8  = CPU in LP1 state mask
  *      R9  = CPU in LP2 state mask
@@ -115,12 +122,10 @@ ENTRY(__tegra_cpu_reset_handler)
 
         cpsid   aif, 0x13                       @ SVC mode, interrupts disabled
 
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r6, [r6, #APB_MISC_GP_HIDREV]
-        and     r6, r6, #0xff00
+        tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 t20_check:
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     after_t20_check
 t20_errata:
         # Tegra20 is a Cortex-A9 r1p1
@@ -136,7 +141,7 @@ after_t20_check:
 #endif
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 t30_check:
-        cmp     r6, #(0x30 << 8)
+        cmp     r6, #TEGRA30
         bne     after_t30_check
 t30_errata:
         # Tegra30 is a Cortex-A9 r2p9
@@ -163,7 +168,7 @@ after_errata:
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
         /* Are we on Tegra20? */
-        cmp     r6, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     1f
         /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
         mov32   r5, TEGRA_PMC_BASE
@@ -186,11 +191,14 @@ __is_not_lp2:
 
 #ifdef CONFIG_SMP
         /*
-         * Can only be secondary boot (initial or hotplug) but CPU 0
-         * cannot be here.
+         * Can only be secondary boot (initial or hotplug)
+         * CPU0 can't be here for Tegra20/30
          */
+        cmp     r6, #TEGRA114
+        beq     __no_cpu0_chk
         cmp     r10, #0
         bleq    __die                           @ CPU0 cannot be here
+__no_cpu0_chk:
         ldr     lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
         cmp     lr, #0
         bleq    __die                           @ no secondary startup handler
@@ -210,10 +218,7 @@ __die:
         mov32   r7, TEGRA_CLK_RESET_BASE
 
         /* Are we on Tegra20? */
-        mov32   r6, TEGRA_APB_MISC_BASE
-        ldr     r0, [r6, #APB_MISC_GP_HIDREV]
-        and     r0, r0, #0xff00
-        cmp     r0, #(0x20 << 8)
+        cmp     r6, #TEGRA20
         bne     1f
 
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d29dfcce948d..ada8821b48be 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -19,6 +19,7 @@
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
 
+#include "fuse.h"
 #include "sleep.h"
 #include "flowctrl.h"
 
@@ -43,14 +44,19 @@ ENDPROC(tegra30_hotplug_shutdown)
  *
  * Puts the current CPU in wait-for-event mode on the flow controller
  * and powergates it -- flags (in R0) indicate the request type.
- * Must never be called for CPU 0.
  *
- * corrupts r0-r4, r12
+ * r10 = SoC ID
+ * corrupts r0-r4, r10-r12
  */
 ENTRY(tegra30_cpu_shutdown)
         cpu_id  r3
+        tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
+        cmp     r10, #TEGRA30
+        bne     _no_cpu0_chk    @ It's not Tegra30
+
         cmp     r3, #0
         moveq   pc, lr          @ Must never be called for CPU 0
+_no_cpu0_chk:
 
         ldr     r12, =TEGRA_FLOW_CTRL_VIRT
         cpu_to_csr_reg r1, r3
@@ -65,7 +71,9 @@ ENTRY(tegra30_cpu_shutdown)
         movw    r12, \
                 FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
                 FLOW_CTRL_CSR_ENABLE
-        mov     r4, #(1 << 4)
+        cmp     r10, #TEGRA30
+        moveq   r4, #(1 << 4)                   @ wfe bitmap
+        movne   r4, #(1 << 8)                   @ wfi bitmap
  ARM(   orr     r12, r12, r4, lsl r3    )
  THUMB( lsl     r4, r4, r3              )
  THUMB( orr     r12, r12, r4            )
@@ -79,9 +87,20 @@ delay_1:
         cpsid   a                               @ disable imprecise aborts.
         ldr     r3, [r1]                        @ read CSR
         str     r3, [r1]                        @ clear CSR
+
         tst     r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+        beq     flow_ctrl_setting_for_lp2
+
+        /* flow controller set up for hotplug */
+        mov     r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        b       flow_ctrl_done
+flow_ctrl_setting_for_lp2:
+        /* flow controller set up for LP2 */
+        cmp     r10, #TEGRA30
         moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT       @ For LP2
-        movne   r3, #FLOW_CTRL_WAITEVENT                @ For hotplug
+        movne   r3, #FLOW_CTRL_WAITEVENT
+flow_ctrl_done:
+        cmp     r10, #TEGRA30
         str     r3, [r2]
         ldr     r0, [r2]
         b       wfe_war
@@ -89,7 +108,8 @@ delay_1:
 __cpu_reset_again:
         dsb
         .align 5
-        wfe                                     @ CPU should be power gated here
+        wfeeq                                   @ CPU should be power gated here
+        wfine
 wfe_war:
         b       __cpu_reset_again
 
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 364d84523fba..9daaef26b0f6 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -106,9 +106,11 @@ ENTRY(tegra_shut_off_mmu)
         isb
 #ifdef CONFIG_CACHE_L2X0
         /* Disable L2 cache */
-        mov32   r4, TEGRA_ARM_PERIF_BASE + 0x3000
-        mov     r5, #0
-        str     r5, [r4, #L2X0_CTRL]
+        check_cpu_part_num 0xc09, r9, r10
+        movweq  r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        movteq  r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
+        moveq   r5, #0
+        streq   r5, [r4, #L2X0_CTRL]
 #endif
         mov     pc, r0
 ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 2080fb12ce26..98b7da698f2b 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -25,6 +25,8 @@
                                         + IO_PPSB_VIRT)
 #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
                                         + IO_PPSB_VIRT)
+#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
+                                        + IO_APB_VIRT)
 #define TEGRA_PMC_VIRT  (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
 
 /* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
@@ -70,19 +72,40 @@
         movt    \reg, #:upper16:\val
 .endm
 
+/* Marco to check CPU part num */
+.macro check_cpu_part_num part_num, tmp1, tmp2
+        mrc     p15, 0, \tmp1, c0, c0, 0
+        ubfx    \tmp1, \tmp1, #4, #12
+        mov32   \tmp2, \part_num
+        cmp     \tmp1, \tmp2
+.endm
+
 /* Macro to exit SMP coherency. */
 .macro exit_smp, tmp1, tmp2
         mrc     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         bic     \tmp1, \tmp1, #(1<<6) | (1<<0)  @ clear ACTLR.SMP | ACTLR.FW
         mcr     p15, 0, \tmp1, c1, c0, 1        @ ACTLR
         isb
-        cpu_id  \tmp1
-        mov     \tmp1, \tmp1, lsl #2
-        mov     \tmp2, #0xf
-        mov     \tmp2, \tmp2, lsl \tmp1
-        mov32   \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
-        str     \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
+#ifdef CONFIG_HAVE_ARM_SCU
+        check_cpu_part_num 0xc09, \tmp1, \tmp2
+        mrceq   p15, 0, \tmp1, c0, c0, 5
+        andeq   \tmp1, \tmp1, #0xF
+        moveq   \tmp1, \tmp1, lsl #2
+        moveq   \tmp2, #0xf
+        moveq   \tmp2, \tmp2, lsl \tmp1
+        ldreq   \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
+        streq   \tmp2, [\tmp1]                  @ invalidate SCU tags for CPU
         dsb
+#endif
+.endm
+
+/* Macro to check Tegra revision */
+#define APB_MISC_GP_HIDREV      0x804
+.macro tegra_get_soc_id base, tmp1
+        mov32   \tmp1, \base
+        ldr     \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
+        and     \tmp1, \tmp1, #0xff00
+        mov     \tmp1, \tmp1, lsr #8
 .endm
 
 /* Macro to resume & re-enable L2 cache */
diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c
index 31e69a019bdd..3ae4a7f1a2fb 100644
--- a/arch/arm/mach-tegra/tegra2_emc.c
+++ b/arch/arm/mach-tegra/tegra2_emc.c
@@ -183,7 +183,7 @@ static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
         u32 reg;
 
         for_each_child_of_node(np, iter) {
-                if (of_property_read_u32(np, "nvidia,ram-code", &reg))
+                if (of_property_read_u32(iter, "nvidia,ram-code", &reg))
                         continue;
                 if (reg == tegra_bct_strapping)
                         return of_node_get(iter);
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f597647d431..a85adcd00882 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,46 @@
-if ARCH_U300
-
 menu "ST-Ericsson AB U300/U335 Platform"
 
 comment "ST-Ericsson Mobile Platform Products"
 
-config MACH_U300
-        bool "U300"
+config ARCH_U300
+        bool "ST-Ericsson U300 Series" if ARCH_MULTI_V5
+        depends on MMU
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_PATCH_PHYS_VIRT
+        select ARM_VIC
+        select CLKDEV_LOOKUP
+        select CLKSRC_MMIO
+        select CLKSRC_OF
+        select COMMON_CLK
+        select CPU_ARM926T
+        select GENERIC_CLOCKEVENTS
+        select HAVE_TCM
         select PINCTRL
         select PINCTRL_COH901
         select PINCTRL_U300
+        select SPARSE_IRQ
+        select MFD_SYSCON
+        select USE_OF
+        help
+          Support for ST-Ericsson U300 series mobile platforms.
 
 comment "ST-Ericsson U300/U335 Feature Selections"
 
+config MACH_U300
+        depends on ARCH_U300
+        bool "U300"
+        default y
+
 config U300_DEBUG
+        depends on ARCH_U300
         bool "Debug support for U300"
         depends on PM
         help
                 Debug support for U300 in sysfs, procfs etc.
 
 config MACH_U300_SPIDUMMY
+        depends on ARCH_U300
         bool "SSP/SPI dummy chip"
         select SPI
         select SPI_MASTER
@@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY
                 SPI framework and ARM PL022 support.
 
 endmenu
-
-endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58da396..0f362b64fb87 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m		:=
 obj-n           :=
 obj-            :=
 
-obj-$(CONFIG_SPI_PL022)           += spi.o
 obj-$(CONFIG_MACH_U300_SPIDUMMY)  += dummyspichip.o
-obj-$(CONFIG_I2C_STU300)          += i2c.o
 obj-$(CONFIG_REGULATOR_AB3100)    += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17b2ce4..4f7ac2a11452 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,46 +9,157 @@
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/bitops.h>
-#include <linux/device.h>
-#include <linux/mm.h>
-#include <linux/termios.h>
-#include <linux/dmaengine.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/amba/serial.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/fsmc.h>
 #include <linux/pinctrl/machine.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/dma-mapping.h>
 #include <linux/platform_data/clk-u300.h>
-#include <linux/platform_data/pinctrl-coh901.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/irqchip/arm-vic.h>
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
 
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <asm/mach/map.h>
-#include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#include <mach/hardware.h>
-#include <mach/syscon.h>
-#include <mach/irqs.h>
+/*
+ * These are the large blocks of memory allocated for I/O.
+ * the defines are used for setting up the I/O memory mapping.
+ */
+
+/* NAND Flash CS0 */
+#define U300_NAND_CS0_PHYS_BASE         0x80000000
+/* NFIF */
+#define U300_NAND_IF_PHYS_BASE          0x9f800000
+/* ALE, CLE offset for FSMC NAND */
+#define PLAT_NAND_CLE                   (1 << 16)
+#define PLAT_NAND_ALE                   (1 << 17)
+/* AHB Peripherals */
+#define U300_AHB_PER_PHYS_BASE          0xa0000000
+#define U300_AHB_PER_VIRT_BASE          0xff010000
+/* FAST Peripherals */
+#define U300_FAST_PER_PHYS_BASE         0xc0000000
+#define U300_FAST_PER_VIRT_BASE         0xff020000
+/* SLOW Peripherals */
+#define U300_SLOW_PER_PHYS_BASE         0xc0010000
+#define U300_SLOW_PER_VIRT_BASE         0xff000000
+/* Boot ROM */
+#define U300_BOOTROM_PHYS_BASE          0xffff0000
+#define U300_BOOTROM_VIRT_BASE          0xffff0000
+/* SEMI config base */
+#define U300_SEMI_CONFIG_BASE           0x2FFE0000
+
+/*
+ * AHB peripherals
+ */
+
+/* AHB Peripherals Bridge Controller */
+#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
+/* Vectored Interrupt Controller 0, servicing 32 interrupts */
+#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
+#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
+/* Vectored Interrupt Controller 1, servicing 32 interrupts */
+#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
+#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
+/* Memory Stick Pro (MSPRO) controller */
+#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
+/* EMIF Configuration Area */
+#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
+
+/*
+ * FAST peripherals
+ */
+
+/* FAST bridge control */
+#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
+/* MMC/SD controller */
+#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
+/* PCM I2S0 controller */
+#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
+/* PCM I2S1 controller */
+#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
+/* I2C0 controller */
+#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
+/* I2C1 controller */
+#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
+/* SPI controller */
+#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
+/* Fast UART1 on U335 only */
+#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
+
+/*
+ * SLOW peripherals
+ */
+
+/* SLOW bridge control */
+#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
+/* SYSCON */
+#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
+#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
+/* Watchdog */
+#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
+/* UART0 */
+#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
+/* APP side special timer */
+#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
+#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
+/* Keypad */
+#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
+/* GPIO */
+#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
+/* RTC */
+#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
+/* Bus tracer */
+#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
+/* Event handler (hardware queue) */
+#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
+/* Genric Timer */
+#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
+/* PPM */
+#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
+
+/*
+ * REST peripherals
+ */
+
+/* ISP (image signal processor) */
+#define U300_ISP_BASE                   (0xA0008000)
+/* DMA Controller base */
+#define U300_DMAC_BASE                  (0xC0020000)
+/* MSL Base */
+#define U300_MSL_BASE                   (0xc0022000)
+/* APEX Base */
+#define U300_APEX_BASE                  (0xc0030000)
+/* Video Encoder Base */
+#define U300_VIDEOENC_BASE              (0xc0080000)
+/* XGAM Base */
+#define U300_XGAM_BASE                  (0xd0000000)
+
+/*
+ * SYSCON addresses applicable to the core machine.
+ */
 
-#include "timer.h"
-#include "spi.h"
-#include "i2c.h"
-#include "u300-gpio.h"
+/* Chip ID register 16bit (R/-) */
+#define U300_SYSCON_CIDR                                        (0x400)
+/* SMCR */
+#define U300_SYSCON_SMCR                                        (0x4d0)
+#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
+#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
+#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
+#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
+/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
+#define U300_SYSCON_CSDR                                        (0x4f0)
+#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
+/* PRINT_CONTROL Print Control 16bit (R/-) */
+#define U300_SYSCON_PCR                                         (0x4f8)
+#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
+/* BOOT_CONTROL 16bit (R/-) */
+#define U300_SYSCON_BCR                                         (0x4fc)
+#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
+#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
+#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
+#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
+
+static void __iomem *syscon_base;
 
 /*
  * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -82,365 +193,6 @@ static void __init u300_map_io(void)
         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
 }
 
-/*
- * Declaration of devices found on the U300 board and
- * their respective memory locations.
- */
-
-static struct amba_pl011_data uart0_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART0_RX,
-        .dma_tx_param = (void *) U300_DMA_UART0_TX,
-#endif
-};
-
-/* Slow device at 0x3000 offset */
-static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
-        { IRQ_U300_UART0 }, &uart0_plat_data);
-
-/* The U335 have an additional UART1 on the APP CPU */
-static struct amba_pl011_data uart1_plat_data = {
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_UART1_RX,
-        .dma_tx_param = (void *) U300_DMA_UART1_TX,
-#endif
-};
-
-/* Fast device at 0x7000 offset */
-static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
-        { IRQ_U300_UART1 }, &uart1_plat_data);
-
-/* AHB device at 0x4000 offset */
-static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
-
-/* Fast device at 0x6000 offset */
-static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
-        { IRQ_U300_SPI }, NULL);
-
-/* Fast device at 0x1000 offset */
-#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
-
-static struct mmci_platform_data mmcsd_platform_data = {
-        /*
-         * Do not set ocr_mask or voltage translation function,
-         * we have a regulator we can control instead.
-         */
-        .f_max = 24000000,
-        .gpio_wp = -1,
-        .gpio_cd = U300_GPIO_PIN_MMC_CD,
-        .cd_invert = true,
-        .capabilities = MMC_CAP_MMC_HIGHSPEED |
-        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-#ifdef CONFIG_COH901318
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
-        /* Don't specify a TX channel, this RX channel is bidirectional */
-#endif
-};
-
-static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
-        U300_MMCSD_IRQS, &mmcsd_platform_data);
-
-/*
- * The order of device declaration may be important, since some devices
- * have dependencies on other devices being initialized first.
- */
-static struct amba_device *amba_devs[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-        &pl022_device,
-        &pl172_device,
-        &mmcsd_device,
-};
-
-/* Here follows a list of all hw resources that the platform devices
- * allocate. Note, clock dependencies are not included
- */
-
-static struct resource gpio_resources[] = {
-        {
-                .start = U300_GPIO_BASE,
-                .end   = (U300_GPIO_BASE + SZ_4K - 1),
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "gpio0",
-                .start = IRQ_U300_GPIO_PORT0,
-                .end   = IRQ_U300_GPIO_PORT0,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio1",
-                .start = IRQ_U300_GPIO_PORT1,
-                .end   = IRQ_U300_GPIO_PORT1,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio2",
-                .start = IRQ_U300_GPIO_PORT2,
-                .end   = IRQ_U300_GPIO_PORT2,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio3",
-                .start = IRQ_U300_GPIO_PORT3,
-                .end   = IRQ_U300_GPIO_PORT3,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio4",
-                .start = IRQ_U300_GPIO_PORT4,
-                .end   = IRQ_U300_GPIO_PORT4,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio5",
-                .start = IRQ_U300_GPIO_PORT5,
-                .end   = IRQ_U300_GPIO_PORT5,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "gpio6",
-                .start = IRQ_U300_GPIO_PORT6,
-                .end   = IRQ_U300_GPIO_PORT6,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource keypad_resources[] = {
-        {
-                .start = U300_KEYPAD_BASE,
-                .end   = U300_KEYPAD_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "coh901461-press",
-                .start = IRQ_U300_KEYPAD_KEYBF,
-                .end   = IRQ_U300_KEYPAD_KEYBF,
-                .flags = IORESOURCE_IRQ,
-        },
-        {
-                .name  = "coh901461-release",
-                .start = IRQ_U300_KEYPAD_KEYBR,
-                .end   = IRQ_U300_KEYPAD_KEYBR,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource rtc_resources[] = {
-        {
-                .start = U300_RTC_BASE,
-                .end   = U300_RTC_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_RTC,
-                .end   = IRQ_U300_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-/*
- * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
- * but these are not yet used by the driver.
- */
-static struct resource fsmc_resources[] = {
-        {
-                .name  = "nand_addr",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_cmd",
-                .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
-                .end   = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "nand_data",
-                .start = U300_NAND_CS0_PHYS_BASE,
-                .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .name  = "fsmc_regs",
-                .start = U300_NAND_IF_PHYS_BASE,
-                .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct resource i2c0_resources[] = {
-        {
-                .start = U300_I2C0_BASE,
-                .end   = U300_I2C0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C0,
-                .end   = IRQ_U300_I2C0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource i2c1_resources[] = {
-        {
-                .start = U300_I2C1_BASE,
-                .end   = U300_I2C1_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_I2C1,
-                .end   = IRQ_U300_I2C1,
-                .flags = IORESOURCE_IRQ,
-        },
-
-};
-
-static struct resource wdog_resources[] = {
-        {
-                .start = U300_WDOG_BASE,
-                .end   = U300_WDOG_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_WDOG,
-                .end   = IRQ_U300_WDOG,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-
-static struct resource dma_resource[] = {
-        {
-                .start = U300_DMAC_BASE,
-                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
-                .flags =  IORESOURCE_MEM,
-        },
-        {
-                .start = IRQ_U300_DMA,
-                .end = IRQ_U300_DMA,
-                .flags =  IORESOURCE_IRQ,
-        }
-};
-
-
-static struct resource pinctrl_resources[] = {
-        {
-                .start = U300_SYSCON_BASE,
-                .end   = U300_SYSCON_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device wdog_device = {
-        .name = "coh901327_wdog",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(wdog_resources),
-        .resource = wdog_resources,
-};
-
-static struct platform_device i2c0_device = {
-        .name = "stu300",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(i2c0_resources),
-        .resource = i2c0_resources,
-};
-
-static struct platform_device i2c1_device = {
-        .name = "stu300",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(i2c1_resources),
-        .resource = i2c1_resources,
-};
-
-static struct platform_device pinctrl_device = {
-        .name = "pinctrl-u300",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(pinctrl_resources),
-        .resource = pinctrl_resources,
-};
-
-/*
- * The different variants have a few different versions of the
- * GPIO block, with different number of ports.
- */
-static struct u300_gpio_platform u300_gpio_plat = {
-        .ports = 7,
-        .gpio_base = 0,
-};
-
-static struct platform_device gpio_device = {
-        .name = "u300-gpio",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(gpio_resources),
-        .resource = gpio_resources,
-        .dev = {
-                .platform_data = &u300_gpio_plat,
-        },
-};
-
-static struct platform_device keypad_device = {
-        .name = "keypad",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(keypad_resources),
-        .resource = keypad_resources,
-};
-
-static struct platform_device rtc_device = {
-        .name = "rtc-coh901331",
-        .id = -1,
-        .num_resources = ARRAY_SIZE(rtc_resources),
-        .resource = rtc_resources,
-};
-
-static struct mtd_partition u300_partitions[] = {
-        {
-                .name = "bootrecords",
-                .offset = 0,
-                .size = SZ_128K,
-        },
-        {
-                .name = "free",
-                .offset = SZ_128K,
-                .size = 8064 * SZ_1K,
-        },
-        {
-                .name = "platform",
-                .offset = 8192 * SZ_1K,
-                .size = 253952 * SZ_1K,
-        },
-};
-
-static struct fsmc_nand_platform_data nand_platform_data = {
-        .partitions = u300_partitions,
-        .nr_partitions = ARRAY_SIZE(u300_partitions),
-        .options = NAND_SKIP_BBTSCAN,
-        .width = FSMC_NAND_BW8,
-};
-
-static struct platform_device nand_device = {
-        .name = "fsmc-nand",
-        .id = -1,
-        .resource = fsmc_resources,
-        .num_resources = ARRAY_SIZE(fsmc_resources),
-        .dev = {
-                .platform_data = &nand_platform_data,
-        },
-};
-
-static struct platform_device dma_device = {
-        .name           = "coh901318",
-        .id             = -1,
-        .resource       = dma_resource,
-        .num_resources  = ARRAY_SIZE(dma_resource),
-        .dev = {
-                .coherent_dma_mask = ~0,
-        },
-};
-
 static unsigned long pin_pullup_conf[] = {
         PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
 };
@@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
                                     pin_highz_conf),
 };
 
-/*
- * Notice that AMBA devices are initialized before platform devices.
- *
- */
-static struct platform_device *platform_devs[] __initdata = {
-        &dma_device,
-        &i2c0_device,
-        &i2c1_device,
-        &keypad_device,
-        &rtc_device,
-        &pinctrl_device,
-        &gpio_device,
-        &nand_device,
-        &wdog_device,
-};
-
-/*
- * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
- * together so some interrupts are connected to the first one and some
- * to the second one.
- */
-static void __init u300_init_irq(void)
-{
-        u32 mask[2] = {0, 0};
-        struct clk *clk;
-        int i;
-
-        /* initialize clocking early, we want to clock the INTCON */
-        u300_clk_init(U300_SYSCON_VBASE);
-
-        /* Bootstrap EMIF and SEMI clocks */
-        clk = clk_get_sys("pl172", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-        clk = clk_get_sys("semi", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-
-        /* Clock the interrupt controller */
-        clk = clk_get_sys("intcon", NULL);
-        BUG_ON(IS_ERR(clk));
-        clk_prepare_enable(clk);
-
-        for (i = 0; i < U300_VIC_IRQS_END; i++)
-                set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
-                 mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
-                 mask[1], mask[1]);
-}
-
-
-/*
- * U300 platforms peripheral handling
- */
 struct db_chip {
         u16 chipid;
         const char *name;
@@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void)
         const char unknown[] = "UNKNOWN";
 
         /* Read out and print chip ID */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
+        val = readw(syscon_base + U300_SYSCON_CIDR);
         /* This is in funky bigendian order... */
         val = (val & 0xFFU) << 8 | (val >> 8);
         chip = db_chips;
@@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void)
         }
 }
 
-/*
- * Some devices and their resources require reserved physical memory from
- * the end of the available RAM. This function traverses the list of devices
- * and assigns actual addresses to these.
- */
-static void __init u300_assign_physmem(void)
-{
-        unsigned long curr_start = __pa(high_memory);
-        int i, j;
-
-        for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
-                for (j = 0; j < platform_devs[i]->num_resources; j++) {
-                        struct resource *const res =
-                          &platform_devs[i]->resource[j];
-
-                        if (IORESOURCE_MEM == res->flags &&
-                                     0 == res->start) {
-                                res->start  = curr_start;
-                                res->end   += curr_start;
-                                curr_start += resource_size(res);
-
-                                printk(KERN_INFO "core.c: Mapping RAM " \
-                                       "%#x-%#x to device %s:%s\n",
-                                        res->start, res->end,
-                                       platform_devs[i]->name, res->name);
-                        }
-                }
-        }
-}
-
-static void __init u300_init_machine(void)
-{
-        int i;
-        u16 val;
-
-        /* Check what platform we run and print some status information */
-        u300_init_check_chip();
-
-        /* Initialize SPI device with some board specifics */
-        u300_spi_init(&pl022_device);
-
-        /* Register the AMBA devices in the AMBA bus abstraction layer */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-                struct amba_device *d = amba_devs[i];
-                amba_device_register(d, &iomem_resource);
-        }
-
-        u300_assign_physmem();
-
-        /* Initialize pinmuxing */
-        pinctrl_register_mappings(u300_pinmux_map,
-                                  ARRAY_SIZE(u300_pinmux_map));
-
-        /* Register subdevices on the I2C buses */
-        u300_i2c_register_board_devices();
-
-        /* Register the platform devices */
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-
-        /* Register subdevices on the SPI bus */
-        u300_spi_register_board_devices();
-
-        /* Enable SEMI self refresh */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
-                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
-}
-
 /* Forward declare this function from the watchdog */
 void coh901327_watchdog_reset(void);
 
@@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd)
         while (1);
 }
 
-MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
-        /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
-        .atag_offset    = 0x100,
+/* These are mostly to get the right device names for the clock lookups */
+static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
+                "pinctrl-u300", NULL),
+        OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
+                "u300-gpio", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
+                "coh901327_wdog", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
+                "rtc-coh901331", NULL),
+        OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
+                "coh901318", NULL),
+        OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
+                "fsmc-nand", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
+                "uart0", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
+                "uart1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
+                "pl022", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
+                "stu300.0", NULL),
+        OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
+                "stu300.1", NULL),
+        OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
+                "mmci", NULL),
+        { /* sentinel */ },
+};
+
+static void __init u300_init_irq_dt(void)
+{
+        struct device_node *syscon;
+        struct clk *clk;
+
+        syscon = of_find_node_by_path("/syscon@c0011000");
+        if (!syscon) {
+                pr_crit("could not find syscon node\n");
+                return;
+        }
+        syscon_base = of_iomap(syscon, 0);
+        if (!syscon_base) {
+                pr_crit("could not remap syscon\n");
+                return;
+        }
+        /* initialize clocking early, we want to clock the INTCON */
+        u300_clk_init(syscon_base);
+
+        /* Bootstrap EMIF and SEMI clocks */
+        clk = clk_get_sys("pl172", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        clk = clk_get_sys("semi", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+
+        /* Clock the interrupt controller */
+        clk = clk_get_sys("intcon", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+
+        irqchip_init();
+}
+
+static void __init u300_init_machine_dt(void)
+{
+        u16 val;
+
+        /* Check what platform we run and print some status information */
+        u300_init_check_chip();
+
+        /* Initialize pinmuxing */
+        pinctrl_register_mappings(u300_pinmux_map,
+                                  ARRAY_SIZE(u300_pinmux_map));
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                        u300_auxdata_lookup, NULL);
+
+        /* Enable SEMI self refresh */
+        val = readw(syscon_base + U300_SYSCON_SMCR) |
+                U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
+        writew(val, syscon_base + U300_SYSCON_SMCR);
+}
+
+static const char * u300_board_compat[] = {
+        "stericsson,u300",
+        NULL,
+};
+
+DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
         .map_io         = u300_map_io,
-        .nr_irqs        = 0,
-        .init_irq       = u300_init_irq,
-        .init_time      = u300_timer_init,
-        .init_machine   = u300_init_machine,
+        .init_irq       = u300_init_irq_dt,
+        .init_time      = clocksource_of_init,
+        .init_machine   = u300_init_machine_dt,
         .restart        = u300_restart,
+        .dt_compat      = u300_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb67b5e8..ec0283cf9a32 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi)
         return 0;
 }
 
+static const struct of_device_id pl022_dummy_dt_match[] = {
+        { .compatible = "arm,pl022-dummy" },
+        {},
+};
+
 static struct spi_driver pl022_dummy_driver = {
         .driver = {
                 .name   = "spi-dummy",
                 .owner  = THIS_MODULE,
+                .of_match_table = pl022_dummy_dt_match,
         },
         .probe  = pl022_dummy_probe,
         .remove = pl022_dummy_remove,
 };
 
-static int __init pl022_init_dummy(void)
-{
-        return spi_register_driver(&pl022_dummy_driver);
-}
-
-static void __exit pl022_exit_dummy(void)
-{
-        spi_unregister_driver(&pl022_dummy_driver);
-}
-
-module_init(pl022_init_dummy);
-module_exit(pl022_exit_dummy);
-
+module_spi_driver(pl022_dummy_driver);
 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
 MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
 MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa1316d..000000000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.c
- *
- * Copyright (C) 2009-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/mfd/ab3100.h>
-#include <linux/regulator/machine.h>
-#include <linux/amba/bus.h>
-#include <mach/irqs.h>
-
-/*
- * Initial settings of ab3100 registers.
- * Common for below LDO regulator settings are that
- * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
- * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
- */
-
-/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
-#define LDO_A_SETTING           0x16
-/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_C_SETTING           0x10
-/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
-#define LDO_D_SETTING           0x10
-/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_E_SETTING           0x10
-/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
-#define LDO_E_SLEEP_SETTING     0x00
-/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
-#define LDO_F_SETTING           0xD0
-/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_G_SETTING           0x00
-/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
-#define LDO_H_SETTING           0x18
-/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
-#define LDO_K_SETTING           0x00
-/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
-#define LDO_EXT_SETTING         0x00
-/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
-#define BUCK_SETTING    0x7D
-/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
-#define BUCK_SLEEP_SETTING      0xAC
-
-#ifdef CONFIG_AB3100_CORE
-static struct regulator_consumer_supply supply_ldo_c[] = {
-        {
-                .dev_name = "ab3100-codec",
-                .supply = "vaudio", /* Powers the codec */
-        },
-};
-
-/*
- * This one needs to be a supply so we can turn it off
- * in order to shut down the system.
- */
-static struct regulator_consumer_supply supply_ldo_d[] = {
-        {
-                .supply = "vana15", /* Powers the SoC (CPU etc) */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_g[] = {
-        {
-                .dev_name = "mmci",
-                .supply = "vmmc", /* Powers MMC/SD card */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_h[] = {
-        {
-                .dev_name = "xgam_pdi",
-                .supply = "vdisp", /* Powers camera, display etc */
-        },
-};
-
-static struct regulator_consumer_supply supply_ldo_k[] = {
-        {
-                .dev_name = "irda",
-                .supply = "vir", /* Power IrDA */
-        },
-};
-
-/*
- * This is a placeholder for whoever wish to use the
- * external power.
- */
-static struct regulator_consumer_supply supply_ldo_ext[] = {
-        {
-                .supply = "vext", /* External power */
-        },
-};
-
-/* Preset (hardware defined) voltages for these regulators */
-#define LDO_A_VOLTAGE 2750000
-#define LDO_C_VOLTAGE 2650000
-#define LDO_D_VOLTAGE 2650000
-
-static struct ab3100_platform_data ab3100_plf_data = {
-        .reg_constraints = {
-                /* LDO A routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vrad",
-                                .min_uV = LDO_A_VOLTAGE,
-                                .max_uV = LDO_A_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO C routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_C_VOLTAGE,
-                                .max_uV = LDO_C_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
-                        .consumer_supplies = supply_ldo_c,
-                },
-                /* LDO D routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = LDO_D_VOLTAGE,
-                                .max_uV = LDO_D_VOLTAGE,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
-                                /*
-                                 * Actually this is boot_on but we need
-                                 * to reference count it externally to
-                                 * be able to shut down the system.
-                                 */
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
-                        .consumer_supplies = supply_ldo_d,
-                },
-                /* LDO E routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vio",
-                                .min_uV = 1800000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO F routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vana25",
-                                .min_uV = 2500000,
-                                .max_uV = 2500000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-                /* LDO G routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1500000,
-                                .max_uV = 2850000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
-                        .consumer_supplies = supply_ldo_g,
-                },
-                /* LDO H routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1200000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
-                        .consumer_supplies = supply_ldo_h,
-                },
-                /* LDO K routing and constraints */
-                {
-                        .constraints = {
-                                .min_uV = 1800000,
-                                .max_uV = 2750000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
-                        .consumer_supplies = supply_ldo_k,
-                },
-                /* External regulator interface. No fixed voltage specified.
-                 * If we knew the voltage of the external regulator and it
-                 * was connected on the board, we could add the (fixed)
-                 * voltage for it here.
-                 */
-                {
-                        .constraints = {
-                                .min_uV = 0,
-                                .max_uV = 0,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_STATUS,
-                        },
-                        .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
-                        .consumer_supplies = supply_ldo_ext,
-                },
-                /* Buck converter routing and constraints */
-                {
-                        .constraints = {
-                                .name = "vcore",
-                                .min_uV = 1200000,
-                                .max_uV = 1800000,
-                                .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE,
-                                .always_on = 1,
-                                .boot_on = 1,
-                        },
-                },
-        },
-        .reg_initvals = {
-                LDO_A_SETTING,
-                LDO_C_SETTING,
-                LDO_E_SETTING,
-                LDO_E_SLEEP_SETTING,
-                LDO_F_SETTING,
-                LDO_G_SETTING,
-                LDO_H_SETTING,
-                LDO_K_SETTING,
-                LDO_EXT_SETTING,
-                BUCK_SETTING,
-                BUCK_SLEEP_SETTING,
-                LDO_D_SETTING,
-        },
-};
-#endif
-
-static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
-#ifdef CONFIG_AB3100_CORE
-        {
-                .type = "ab3100",
-                .addr = 0x48,
-                .irq = IRQ_U300_IRQ0_EXT,
-                .platform_data = &ab3100_plf_data,
-        },
-#else
-        { },
-#endif
-};
-
-static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-        {
-                .type = "fwcam",
-                .addr = 0x10,
-        },
-        {
-                .type = "fwcam",
-                .addr = 0x5d,
-        },
-};
-
-void __init u300_i2c_register_board_devices(void)
-{
-        i2c_register_board_info(0, bus0_i2c_board_info,
-                                ARRAY_SIZE(bus0_i2c_board_info));
-        /*
-         * This makes the core shut down all unused regulators
-         * after all the initcalls have completed.
-         */
-        regulator_has_full_constraints();
-        i2c_register_board_info(1, bus1_i2c_board_info,
-                                ARRAY_SIZE(bus1_i2c_board_info));
-}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e5c06d..000000000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * arch/arm/mach-u300/i2c.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Register board i2c devices
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef MACH_U300_I2C_H
-#define MACH_U300_I2C_H
-
-#ifdef CONFIG_I2C_STU300
-void __init u300_i2c_register_board_devices(void);
-#else
-/* Compile out this stuff if no I2C adapter is available */
-static inline void __init u300_i2c_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce0ac2b..000000000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/hardware.h
- */
-#include <asm/sizes.h>
-#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76a6cd3..000000000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/irqs.h
- *
- *
- * Copyright (C) 2006-2012 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * IRQ channel definitions for the U300 platforms.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_IRQS_H
-#define __MACH_IRQS_H
-
-#define IRQ_U300_INTCON0_START          32
-#define IRQ_U300_INTCON1_START          64
-/* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               32
-#define IRQ_U300_IRQ1_EXT               33
-#define IRQ_U300_DMA                    34
-#define IRQ_U300_VIDEO_ENC_0            35
-#define IRQ_U300_VIDEO_ENC_1            36
-#define IRQ_U300_AAIF_RX                37
-#define IRQ_U300_AAIF_TX                38
-#define IRQ_U300_AAIF_VGPIO             39
-#define IRQ_U300_AAIF_WAKEUP            40
-#define IRQ_U300_PCM_I2S0_FRAME         41
-#define IRQ_U300_PCM_I2S0_FIFO          42
-#define IRQ_U300_PCM_I2S1_FRAME         43
-#define IRQ_U300_PCM_I2S1_FIFO          44
-#define IRQ_U300_XGAM_GAMCON            45
-#define IRQ_U300_XGAM_CDI               46
-#define IRQ_U300_XGAM_CDICON            47
-#define IRQ_U300_XGAM_PDI               49
-#define IRQ_U300_XGAM_PDICON            50
-#define IRQ_U300_XGAM_GAMEACC           51
-#define IRQ_U300_XGAM_MCIDCT            52
-#define IRQ_U300_APEX                   53
-#define IRQ_U300_UART0                  54
-#define IRQ_U300_SPI                    55
-#define IRQ_U300_TIMER_APP_OS           56
-#define IRQ_U300_TIMER_APP_DD           57
-#define IRQ_U300_TIMER_APP_GP1          58
-#define IRQ_U300_TIMER_APP_GP2          59
-#define IRQ_U300_TIMER_OS               60
-#define IRQ_U300_TIMER_MS               61
-#define IRQ_U300_KEYPAD_KEYBF           62
-#define IRQ_U300_KEYPAD_KEYBR           63
-/* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             64
-#define IRQ_U300_GPIO_PORT1             65
-#define IRQ_U300_GPIO_PORT2             66
-
-/* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   67
-#define IRQ_U300_EVHIST                 68
-#define IRQ_U300_MSPRO                  69
-#define IRQ_U300_MMCSD_MCIINTR0         70
-#define IRQ_U300_MMCSD_MCIINTR1         71
-#define IRQ_U300_I2C0                   72
-#define IRQ_U300_I2C1                   73
-#define IRQ_U300_RTC                    74
-#define IRQ_U300_NFIF                   75
-#define IRQ_U300_NFIF2                  76
-
-/* The DB3350-specific interrupt lines */
-#define IRQ_U300_ISP_F0                 77
-#define IRQ_U300_ISP_F1                 78
-#define IRQ_U300_ISP_F2                 79
-#define IRQ_U300_ISP_F3                 80
-#define IRQ_U300_ISP_F4                 81
-#define IRQ_U300_GPIO_PORT3             82
-#define IRQ_U300_SYSCON_PLL_LOCK        83
-#define IRQ_U300_UART1                  84
-#define IRQ_U300_GPIO_PORT4             85
-#define IRQ_U300_GPIO_PORT5             86
-#define IRQ_U300_GPIO_PORT6             87
-#define U300_VIC_IRQS_END               88
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0be9774..000000000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/syscon.h
- *
- *
- * Copyright (C) 2008-2012 ST-Ericsson AB
- *
- * Author: Rickard Andersson <rickard.andersson@stericsson.com>
- */
-
-#ifndef __MACH_SYSCON_H
-#define __MACH_SYSCON_H
-
-/*
- * All register defines for SYSCON registers that concerns individual
- * block clocks and reset lines are registered here. This is because
- * we don't want any other file to try to fool around with this stuff.
- */
-
-/* APP side SYSCON registers */
-/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
-/* CLK Control Register 16bit (R/W) */
-#define U300_SYSCON_CCR                                         (0x0000)
-#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
-#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
-#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
-#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
-/* CLK Status Register 16bit (R/W) */
-#define U300_SYSCON_CSR                                         (0x0004)
-#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
-#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
-/* Reset lines for SLOW devices 16bit (R/W) */
-#define U300_SYSCON_RSR                                         (0x0014)
-#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
-#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
-#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
-#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
-#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
-#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
-#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
-#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
-#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
-#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
-/* Reset lines for FAST devices 16bit (R/W) */
-#define U300_SYSCON_RFR                                         (0x0018)
-#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
-#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
-#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
-#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
-#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
-#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
-#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
-#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
-/* Reset lines for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_RRR                                         (0x001c)
-#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
-#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
-#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
-#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
-#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
-#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
-#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
-#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
-#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
-#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
-#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
-#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
-#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
-/* Clock enable for SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CESR                                        (0x0020)
-#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
-#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
-#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
-#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
-#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
-#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
-#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
-#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
-#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CEFR                                        (0x0024)
-#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
-#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
-#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
-#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
-#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
-#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
-/* Clock enable for the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CERR                                        (0x0028)
-#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
-#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
-#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
-#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
-#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
-#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
-#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
-#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
-#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
-#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
-#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
-#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
-#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
-#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
-/* Single block clock enable 16bit (-/W) */
-#define U300_SYSCON_SBCER                                       (0x002c)
-#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
-#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
-#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
-#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
-#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
-#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
-#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
-#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
-#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
-#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
-#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
-#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
-#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
-#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
-#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
-#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
-#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
-#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
-#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
-#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
-#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
-#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
-#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
-#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
-#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
-#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
-#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
-#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
-#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
-#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
-#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
-#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
-#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
-/* Single block clock disable 16bit (-/W) */
-#define U300_SYSCON_SBCDR                                       (0x0030)
-/* Same values as above for SBCER */
-/* Clock force SLOW peripherals 16bit (R/W) */
-#define U300_SYSCON_CFSR                                        (0x003c)
-#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
-#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
-#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
-#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
-#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
-#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
-#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
-#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
-/* Clock force FAST peripherals 16bit (R/W) */
-#define U300_SYSCON_CFFR                                        (0x40)
-/* Values not defined. Define if you want to use them. */
-/* Clock force the rest of the peripherals 16bit (R/W) */
-#define U300_SYSCON_CFRR                                        (0x44)
-#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
-#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
-#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
-#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
-#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
-#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
-#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
-#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
-#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
-#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
-#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
-#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
-#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
-#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
-/* PLL208 Frequency Control 16bit (R/W) */
-#define U300_SYSCON_PFCR                                        (0x48)
-#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
-/* Power Management Control 16bit (R/W) */
-#define U300_SYSCON_PMCR                                        (0x50)
-#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
-#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
-/*
- * All other clocking registers moved to clock.c!
- */
-/* Reset Out 16bit (R/W) */
-#define U300_SYSCON_RCR                                         (0x6c)
-#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
-/* EMIF Slew Rate Control 16bit (R/W) */
-#define U300_SYSCON_SRCLR                                       (0x70)
-#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
-#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
-#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
-/* EMIF Clock Control Register 16bit (R/W) */
-#define U300_SYSCON_ECCR                                        (0x0078)
-#define U300_SYSCON_ECCR_MASK                                   (0x000F)
-#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
-#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
-#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
-#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
-/* Step one for killing the applications system 16bit (-/W) */
-#define U300_SYSCON_KA1R                                        (0x0080)
-#define U300_SYSCON_KA1R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA1R_VALUE                                  (0xFFFF)
-/* Step two for killing the application system 16bit (-/W) */
-#define U300_SYSCON_KA2R                                        (0x0084)
-#define U300_SYSCON_KA2R_MASK                                   (0xFFFF)
-#define U300_SYSCON_KA2R_VALUE                                  (0xFFFF)
-/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
-#define U300_SYSCON_MMF0R                                       (0x90)
-#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
-/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
-#define U300_SYSCON_MMF1R                                       (0x94)
-#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
-#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
-#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
-/* AAIF control register 16 bit (R/W) */
-#define U300_SYSCON_AAIFCR                                      (0x98)
-#define U300_SYSCON_AAIFCR_MASK                                 (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK                       (0x0003)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL                 (0x0000)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING                 (0x0001)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT                 (0x0002)
-#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT                 (0x0003)
-/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
-#define U300_SYSCON_MMCR                                        (0x9C)
-#define U300_SYSCON_MMCR_MASK                                   (0x0003)
-#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
-#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
-/* Pull up/down control (R/W) */
-#define U300_SYSCON_PUCR                                        (0x104)
-#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE                (0x0200)
-#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE            (0x0100)
-#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE                 (0x0080)
-#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE                  (0x0040)
-#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK                      (0x003F)
-/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
-#define U300_SYSCON_S0CCR                                       (0x120)
-#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
-#define U300_SYSCON_S1CCR                                       (0x124)
-#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
-#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
-#define U300_SYSCON_S2CCR                                       (0x128)
-#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
-#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
-#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
-#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
-#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
-#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
-#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
-#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
-#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
-#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
-#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
-#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
-/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
-#define U300_SYSCON_MCR                                         (0x12c)
-#define U300_SYSCON_MCR_FIELD_MASK                              (0x00FF)
-#define U300_SYSCON_MCR_PMGEN_CR_4_MASK                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_4_SPI                          (0x0040)
-#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF                         (0x00C0)
-#define U300_SYSCON_MCR_PMGEN_CR_2_MASK                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO                         (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC                (0x0010)
-#define U300_SYSCON_MCR_PMGEN_CR_2_DSP                          (0x0020)
-#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF                         (0x0030)
-#define U300_SYSCON_MCR_PMGEN_CR_0_MASK                         (0x000C)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1              (0x0000)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2              (0x0004)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3              (0x0008)
-#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM                 (0x000C)
-#define U300_SYSCON_MCR_PM1G_MODE_ENABLE                        (0x0002)
-#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE                       (0x0001)
-/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
-#define U300_SYSCON_PICR                                        (0x0130)
-#define U300_SYSCON_PICR_MASK                                   (0x00FF)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
-#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
-#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
-#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
-#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
-/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
-#define U300_SYSCON_PISR                                        (0x0134)
-#define U300_SYSCON_PISR_MASK                                   (0x000F)
-#define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
-#define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
-#define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
-#define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
-/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
-#define U300_SYSCON_PICLR                                       (0x0138)
-#define U300_SYSCON_PICLR_MASK                                  (0x000F)
-#define U300_SYSCON_PICLR_RWMASK                                (0x0000)
-#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
-#define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
-#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
-#define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
-/* CAMIF_CONTROL 16 bit (-/W) */
-#define U300_SYSCON_CICR                                        (0x013C)
-#define U300_SYSCON_CICR_MASK                                   (0x0FFF)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK              (0x0F00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1             (0x0C00)
-#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0             (0x0300)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK                (0x00F0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1               (0x00C0)
-#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0               (0x0030)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK             (0x000F)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1            (0x000C)
-#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0            (0x0003)
-/* Clock activity observability register 0 */
-#define U300_SYSCON_C0OAR                                       (0x140)
-#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
-#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
-#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
-#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
-#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
-#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
-#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
-#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
-#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
-#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
-#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
-#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
-#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
-#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
-#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
-#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
-#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
-#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
-/* Clock activity observability register 1 */
-#define U300_SYSCON_C1OAR                                       (0x144)
-#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
-#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
-#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
-#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
-#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
-#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
-#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
-#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
-#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
-#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
-#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
-#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
-#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
-#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
-#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
-/* Clock activity observability register 2 */
-#define U300_SYSCON_C2OAR                                       (0x148)
-#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
-#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
-#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
-#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
-#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
-#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
-#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
-#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
-#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
-#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
-#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
-#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
-
-/* Chip ID register 16bit (R/-) */
-#define U300_SYSCON_CIDR                                        (0x400)
-/* Video IRQ clear 16bit (R/W) */
-#define U300_SYSCON_VICR                                        (0x404)
-#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE                (0x0002)
-#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE                (0x0001)
-/* SMCR */
-#define U300_SYSCON_SMCR                                        (0x4d0)
-#define U300_SYSCON_SMCR_FIELD_MASK                             (0x000e)
-#define U300_SYSCON_SMCR_SEMI_SREFACK_IND                       (0x0008)
-#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE                    (0x0004)
-#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE              (0x0002)
-/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
-#define U300_SYSCON_CSDR                                        (0x4f0)
-#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE                        (0x0001)
-/* PRINT_CONTROL Print Control 16bit (R/-) */
-#define U300_SYSCON_PCR                                         (0x4f8)
-#define U300_SYSCON_PCR_SERV_IND                                (0x0001)
-/* BOOT_CONTROL 16bit (R/-) */
-#define U300_SYSCON_BCR                                         (0x4fc)
-#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND              (0x0400)
-#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND              (0x0200)
-#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK                  (0x01FC)
-#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK                      (0x0003)
-
-
-/* CPU clock defines */
-/**
- * CPU high frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_HIGH    208
-/**
- * CPU medium frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_MEDIUM   52
-/**
- * CPU low frequency in MHz
- */
-#define SYSCON_CPU_CLOCK_LOW      13
-
-/* EMIF clock defines */
-/**
- * EMIF high frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_HIGH   104
-/**
- * EMIF medium frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_MEDIUM  52
-/**
- * EMIF low frequency in MHz
- */
-#define SYSCON_EMIF_CLOCK_LOW     13
-
-/* AHB clock defines */
-/**
- * AHB high frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_HIGH     52
-/**
- * AHB medium frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_MEDIUM   26
-/**
- * AHB low frequency in MHz
- */
-#define SYSCON_AHB_CLOCK_LOW       7  /* i.e 13/2=6.5MHz */
-
-enum syscon_busmaster {
-  SYSCON_BM_DMAC,
-  SYSCON_BM_XGAM,
-  SYSCON_BM_VIDEO_ENC
-};
-
-/* Selectr a resistor or a set of resistors */
-enum syscon_pull_up_down {
-  SYSCON_PU_KEY_IN_EN,
-  SYSCON_PU_EMIF_1_8_BIT_EN,
-  SYSCON_PU_EMIF_1_16_BIT_EN,
-  SYSCON_PU_EMIF_1_NFIF_READY_EN,
-  SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
-};
-
-/*
- * Note that this array must match the order of the array "clk_reg"
- * in syscon.c
- */
-enum syscon_clk {
-  SYSCON_CLKCONTROL_SLOW_BRIDGE,
-  SYSCON_CLKCONTROL_UART,
-  SYSCON_CLKCONTROL_BTR,
-  SYSCON_CLKCONTROL_EH,
-  SYSCON_CLKCONTROL_GPIO,
-  SYSCON_CLKCONTROL_KEYPAD,
-  SYSCON_CLKCONTROL_APP_TIMER,
-  SYSCON_CLKCONTROL_ACC_TIMER,
-  SYSCON_CLKCONTROL_FAST_BRIDGE,
-  SYSCON_CLKCONTROL_I2C0,
-  SYSCON_CLKCONTROL_I2C1,
-  SYSCON_CLKCONTROL_I2S0,
-  SYSCON_CLKCONTROL_I2S1,
-  SYSCON_CLKCONTROL_MMC,
-  SYSCON_CLKCONTROL_SPI,
-  SYSCON_CLKCONTROL_I2S0_CORE,
-  SYSCON_CLKCONTROL_I2S1_CORE,
-  SYSCON_CLKCONTROL_UART1,
-  SYSCON_CLKCONTROL_AAIF,
-  SYSCON_CLKCONTROL_AHB,
-  SYSCON_CLKCONTROL_APEX,
-  SYSCON_CLKCONTROL_CPU,
-  SYSCON_CLKCONTROL_DMA,
-  SYSCON_CLKCONTROL_EMIF,
-  SYSCON_CLKCONTROL_NAND_IF,
-  SYSCON_CLKCONTROL_VIDEO_ENC,
-  SYSCON_CLKCONTROL_XGAM,
-  SYSCON_CLKCONTROL_SEMI,
-  SYSCON_CLKCONTROL_AHB_SUBSYS,
-  SYSCON_CLKCONTROL_MSPRO
-};
-
-enum syscon_sysclk_mode {
-  SYSCON_SYSCLK_DISABLED,
-  SYSCON_SYSCLK_M_CLK,
-  SYSCON_SYSCLK_ACC_FSM,
-  SYSCON_SYSCLK_PLL60_48,
-  SYSCON_SYSCLK_PLL60_60,
-  SYSCON_SYSCLK_ACC_PLL208,
-  SYSCON_SYSCLK_APP_PLL13,
-  SYSCON_SYSCLK_APP_FSM,
-  SYSCON_SYSCLK_RTC,
-  SYSCON_SYSCLK_APP_PLL208
-};
-
-enum syscon_sysclk_req {
-  SYSCON_SYSCLKREQ_DISABLED,
-  SYSCON_SYSCLKREQ_ACTIVE_LOW,
-  SYSCON_SYSCLKREQ_MONITOR
-};
-
-enum syscon_clk_mode {
-  SYSCON_CLKMODE_OFF,
-  SYSCON_CLKMODE_DEFAULT,
-  SYSCON_CLKMODE_LOW,
-  SYSCON_CLKMODE_MEDIUM,
-  SYSCON_CLKMODE_HIGH,
-  SYSCON_CLKMODE_PERMANENT,
-  SYSCON_CLKMODE_ON,
-};
-
-enum syscon_call_mode {
-  SYSCON_CLKCALL_NOWAIT,
-  SYSCON_CLKCALL_WAIT,
-};
-
-int syscon_dc_on(bool keep_power_on);
-int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
-                                      bool active);
-bool syscon_get_busmaster_active_state(void);
-int syscon_set_sleep_mask(enum syscon_clk,
-                          bool sleep_ctrl);
-int syscon_config_sysclk(u32 sysclk,
-                         enum syscon_sysclk_mode sysclkmode,
-                         bool inverse,
-                         u32 divisor,
-                         enum syscon_sysclk_req sysclkreq);
-bool syscon_can_turn_off_semi_clock(void);
-
-/* This function is restricted to core.c */
-int syscon_request_normal_power(bool req);
-
-/* This function is restricted to be used by platform_speed.c */
-int syscon_speed_request(enum syscon_call_mode wait_mode,
-                         enum syscon_clk_mode req_clk_mode);
-#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72633f6..000000000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/timex.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform tick rate definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef __MACH_TIMEX_H
-#define __MACH_TIMEX_H
-
-/* This is for the APP OS GP1 (General Purpose 1) timer */
-#define CLOCK_TICK_RATE         1000000
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
deleted file mode 100644
index 0320495efc4d..000000000000
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/u300-regs.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic register address definitions in physical memory and
- * some block definitions for core devices like the timer.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __MACH_U300_REGS_H
-#define __MACH_U300_REGS_H
-
-/*
- * These are the large blocks of memory allocated for I/O.
- * the defines are used for setting up the I/O memory mapping.
- */
-
-/* NAND Flash CS0 */
-#define U300_NAND_CS0_PHYS_BASE         0x80000000
-
-/* NFIF */
-#define U300_NAND_IF_PHYS_BASE          0x9f800000
-
-/* ALE, CLE offset for FSMC NAND */
-#define PLAT_NAND_CLE                   (1 << 16)
-#define PLAT_NAND_ALE                   (1 << 17)
-
-/* AHB Peripherals */
-#define U300_AHB_PER_PHYS_BASE          0xa0000000
-#define U300_AHB_PER_VIRT_BASE          0xff010000
-
-/* FAST Peripherals */
-#define U300_FAST_PER_PHYS_BASE         0xc0000000
-#define U300_FAST_PER_VIRT_BASE         0xff020000
-
-/* SLOW Peripherals */
-#define U300_SLOW_PER_PHYS_BASE         0xc0010000
-#define U300_SLOW_PER_VIRT_BASE         0xff000000
-
-/* Boot ROM */
-#define U300_BOOTROM_PHYS_BASE          0xffff0000
-#define U300_BOOTROM_VIRT_BASE          0xffff0000
-
-/* SEMI config base */
-#define U300_SEMI_CONFIG_BASE           0x2FFE0000
-
-/*
- * AHB peripherals
- */
-
-/* AHB Peripherals Bridge Controller */
-#define U300_AHB_BRIDGE_BASE            (U300_AHB_PER_PHYS_BASE+0x0000)
-
-/* Vectored Interrupt Controller 0, servicing 32 interrupts */
-#define U300_INTCON0_BASE               (U300_AHB_PER_PHYS_BASE+0x1000)
-#define U300_INTCON0_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
-
-/* Vectored Interrupt Controller 1, servicing 32 interrupts */
-#define U300_INTCON1_BASE               (U300_AHB_PER_PHYS_BASE+0x2000)
-#define U300_INTCON1_VBASE              IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
-
-/* Memory Stick Pro (MSPRO) controller */
-#define U300_MSPRO_BASE                 (U300_AHB_PER_PHYS_BASE+0x3000)
-
-/* EMIF Configuration Area */
-#define U300_EMIF_CFG_BASE              (U300_AHB_PER_PHYS_BASE+0x4000)
-
-
-/*
- * FAST peripherals
- */
-
-/* FAST bridge control */
-#define U300_FAST_BRIDGE_BASE           (U300_FAST_PER_PHYS_BASE+0x0000)
-
-/* MMC/SD controller */
-#define U300_MMCSD_BASE                 (U300_FAST_PER_PHYS_BASE+0x1000)
-
-/* PCM I2S0 controller */
-#define U300_PCM_I2S0_BASE              (U300_FAST_PER_PHYS_BASE+0x2000)
-
-/* PCM I2S1 controller */
-#define U300_PCM_I2S1_BASE              (U300_FAST_PER_PHYS_BASE+0x3000)
-
-/* I2C0 controller */
-#define U300_I2C0_BASE                  (U300_FAST_PER_PHYS_BASE+0x4000)
-
-/* I2C1 controller */
-#define U300_I2C1_BASE                  (U300_FAST_PER_PHYS_BASE+0x5000)
-
-/* SPI controller */
-#define U300_SPI_BASE                   (U300_FAST_PER_PHYS_BASE+0x6000)
-
-/* Fast UART1 on U335 only */
-#define U300_UART1_BASE                 (U300_FAST_PER_PHYS_BASE+0x7000)
-
-/*
- * SLOW peripherals
- */
-
-/* SLOW bridge control */
-#define U300_SLOW_BRIDGE_BASE           (U300_SLOW_PER_PHYS_BASE)
-
-/* SYSCON */
-#define U300_SYSCON_BASE                (U300_SLOW_PER_PHYS_BASE+0x1000)
-#define U300_SYSCON_VBASE               IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
-
-/* Watchdog */
-#define U300_WDOG_BASE                  (U300_SLOW_PER_PHYS_BASE+0x2000)
-
-/* UART0 */
-#define U300_UART0_BASE                 (U300_SLOW_PER_PHYS_BASE+0x3000)
-
-/* APP side special timer */
-#define U300_TIMER_APP_BASE             (U300_SLOW_PER_PHYS_BASE+0x4000)
-#define U300_TIMER_APP_VBASE            IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
-
-/* Keypad */
-#define U300_KEYPAD_BASE                (U300_SLOW_PER_PHYS_BASE+0x5000)
-
-/* GPIO */
-#define U300_GPIO_BASE                  (U300_SLOW_PER_PHYS_BASE+0x6000)
-
-/* RTC */
-#define U300_RTC_BASE                   (U300_SLOW_PER_PHYS_BASE+0x7000)
-
-/* Bus tracer */
-#define U300_BUSTR_BASE                 (U300_SLOW_PER_PHYS_BASE+0x8000)
-
-/* Event handler (hardware queue) */
-#define U300_EVHIST_BASE                (U300_SLOW_PER_PHYS_BASE+0x9000)
-
-/* Genric Timer */
-#define U300_TIMER_BASE                 (U300_SLOW_PER_PHYS_BASE+0xa000)
-
-/* PPM */
-#define U300_PPM_BASE                   (U300_SLOW_PER_PHYS_BASE+0xb000)
-
-
-/*
- * REST peripherals
- */
-
-/* ISP (image signal processor) */
-#define U300_ISP_BASE                   (0xA0008000)
-
-/* DMA Controller base */
-#define U300_DMAC_BASE                  (0xC0020000)
-
-/* MSL Base */
-#define U300_MSL_BASE                   (0xc0022000)
-
-/* APEX Base */
-#define U300_APEX_BASE                  (0xc0030000)
-
-/* Video Encoder Base */
-#define U300_VIDEOENC_BASE              (0xc0080000)
-
-/* XGAM Base */
-#define U300_XGAM_BASE                  (0xd0000000)
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e60101b..000000000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/uncompress.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define AMBA_UART_DR    (*(volatile unsigned char *)0xc0013000)
-#define AMBA_UART_LCRH  (*(volatile unsigned char *)0xc001302C)
-#define AMBA_UART_CR    (*(volatile unsigned char *)0xc0013030)
-#define AMBA_UART_FR    (*(volatile unsigned char *)0xc0013018)
-
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-        while (AMBA_UART_FR & (1 << 5))
-                barrier();
-
-        AMBA_UART_DR = c;
-}
-
-static inline void flush(void)
-{
-        while (AMBA_UART_FR & (1 << 3))
-                barrier();
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 9c53f01c62eb..bf40cd478fe9 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -10,11 +10,18 @@
 #include <linux/device.h>
 #include <linux/signal.h>
 #include <linux/err.h>
+#include <linux/of.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
 #include <linux/regulator/consumer.h>
-/* Those are just for writing in syscon */
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/syscon.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
 
 /*
  * Regulators that power the board and chip and which are
@@ -47,13 +54,28 @@ void u300_pm_poweroff(void)
 /*
  * Hog the regulators needed to power up the board.
  */
-static int __init u300_init_boardpower(void)
+static int __init __u300_init_boardpower(struct platform_device *pdev)
 {
+        struct device_node *np = pdev->dev.of_node;
+        struct device_node *syscon_np;
+        struct regmap *regmap;
         int err;
-        u32 val;
 
         pr_info("U300: setting up board power\n");
-        main_power_15 = regulator_get(NULL, "vana15");
+
+        syscon_np = of_parse_phandle(np, "syscon", 0);
+        if (!syscon_np) {
+                pr_crit("U300: no syscon node\n");
+                return -ENODEV;
+        }
+        regmap = syscon_node_to_regmap(syscon_np);
+        if (!regmap) {
+                pr_crit("U300: could not locate syscon regmap\n");
+                return -ENODEV;
+        }
+
+        main_power_15 = regulator_get(&pdev->dev, "vana15");
+
         if (IS_ERR(main_power_15)) {
                 pr_err("could not get vana15");
                 return PTR_ERR(main_power_15);
@@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void)
          * the rest of the U300 power management is implemented.
          */
         pr_info("U300: disable system controller pull-up\n");
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
-        val &= ~U300_SYSCON_PMCR_DCON_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
+        regmap_update_bits(regmap, U300_SYSCON_PMCR,
+                           U300_SYSCON_PMCR_DCON_ENABLE, 0);
 
         /* Register globally exported PM poweroff hook */
         pm_power_off = u300_pm_poweroff;
@@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void)
         return 0;
 }
 
+static int __init s365_board_probe(struct platform_device *pdev)
+{
+        return __u300_init_boardpower(pdev);
+}
+
+static const struct of_device_id s365_board_match[] = {
+        { .compatible = "stericsson,s365" },
+        {},
+};
+
+static struct platform_driver s365_board_driver = {
+        .driver         = {
+                .name   = "s365-board",
+                .owner  = THIS_MODULE,
+                .of_match_table = s365_board_match,
+        },
+};
+
 /*
  * So at module init time we hog the regulator!
  */
-module_init(u300_init_boardpower);
+static int __init u300_init_boardpower(void)
+{
+        return platform_driver_probe(&s365_board_driver,
+                                     s365_board_probe);
+}
+
+device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 910698293d64..000000000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.c
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/device.h>
-#include <linux/amba/bus.h>
-#include <linux/spi/spi.h>
-#include <linux/amba/pl022.h>
-#include <linux/platform_data/dma-coh901318.h>
-#include <linux/err.h>
-
-/*
- * The following is for the actual devices on the SSP/SPI bus
- */
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-static void select_dummy_chip(u32 chipselect)
-{
-        pr_debug("CORE: %s called with CS=0x%x (%s)\n",
-                 __func__,
-                 chipselect,
-                 chipselect ? "unselect chip" : "select chip");
-        /*
-         * Here you would write the chip select value to the GPIO pins if
-         * this was a real chip (but this is a loopback dummy).
-         */
-}
-
-struct pl022_config_chip dummy_chip_info = {
-        /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
-        .com_mode = DMA_TRANSFER,
-        .iface = SSP_INTERFACE_MOTOROLA_SPI,
-        /* We can only act as master but SSP_SLAVE is possible in theory */
-        .hierarchy = SSP_MASTER,
-        /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
-        .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .ctrl_len = SSP_BITS_12,
-        .wait_state = SSP_MWIRE_WAIT_ZERO,
-        .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-        /*
-         * This is where you insert a call to a function to enable CS
-         * (usually GPIO) for a certain chip.
-         */
-        .cs_control = select_dummy_chip,
-};
-#endif
-
-static struct spi_board_info u300_spi_devices[] = {
-#ifdef CONFIG_MACH_U300_SPIDUMMY
-        {
-                /* A dummy chip used for loopback tests */
-                .modalias       = "spi-dummy",
-                /* Really dummy, pass in additional chip config here */
-                .platform_data  = NULL,
-                /* This defines how the controller shall handle the device */
-                .controller_data = &dummy_chip_info,
-                /* .irq - no external IRQ routed from this device */
-                .max_speed_hz   = 1000000,
-                .bus_num        = 0, /* Only one bus on this chip */
-                .chip_select    = 0,
-                /* Means SPI_CS_HIGH, change if e.g low CS */
-                .mode           = SPI_MODE_1 | SPI_LOOP,
-        },
-#endif
-};
-
-static struct pl022_ssp_controller ssp_platform_data = {
-        /* If you have several SPI buses this varies, we have only bus 0 */
-        .bus_id = 0,
-        /*
-         * On the APP CPU GPIO 4, 5 and 6 are connected as generic
-         * chip selects for SPI. (Same on U330, U335 and U365.)
-         * TODO: make sure the GPIO driver can select these properly
-         * and do padmuxing accordingly too.
-         */
-        .num_chipselect = 3,
-#ifdef CONFIG_COH901318
-        .enable_dma = 1,
-        .dma_filter = coh901318_filter_id,
-        .dma_rx_param = (void *) U300_DMA_SPI_RX,
-        .dma_tx_param = (void *) U300_DMA_SPI_TX,
-#else
-        .enable_dma = 0,
-#endif
-};
-
-
-void __init u300_spi_init(struct amba_device *adev)
-{
-        adev->dev.platform_data = &ssp_platform_data;
-}
-
-void __init u300_spi_register_board_devices(void)
-{
-        /* Register any SPI devices */
-        spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
-}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867e240f..000000000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-u300/spi.h
- *
- * Copyright (C) 2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- *
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#ifndef SPI_H
-#define SPI_H
-#include <linux/amba/bus.h>
-
-#ifdef CONFIG_SPI_PL022
-void __init u300_spi_init(struct amba_device *adev);
-void __init u300_spi_register_board_devices(void);
-#else
-/* Compile out SPI support if PL022 is not selected */
-static inline void __init u300_spi_init(struct amba_device *adev)
-{
-}
-static inline void __init u300_spi_register_board_devices(void)
-{
-}
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index d9e73209c9b8..390ae5feb1d0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -18,17 +18,15 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 /* Generic stuff */
 #include <asm/sched_clock.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include "timer.h"
-
 /*
  * APP side special timer registers
  * This timer contains four timers which can fire an interrupt each.
@@ -189,6 +187,8 @@
 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 
+static void __iomem *u300_timer_base;
+
 /*
  * The u300_set_mode() function is always called first, if we
  * have oneshot timer active, the oneshot scheduling function
@@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode,
         case CLOCK_EVT_MODE_PERIODIC:
                 /* Disable interrupts on GPT1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 while we're reprogramming it. */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 /*
                  * Set the periodic mode to a certain number of ticks per
                  * jiffy.
                  */
                 writel(TICKS_PER_JIFFY,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                       u300_timer_base + U300_TIMER_APP_GPT1TC);
                 /*
                  * Set continuous mode, so the timer keeps triggering
                  * interrupts.
                  */
                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                 /* Enable timer interrupts */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Then enable the OS timer again */
                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                 break;
         case CLOCK_EVT_MODE_ONESHOT:
                 /* Just break; here? */
@@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode,
                  */
                 /* Disable interrupts on GPT1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 while we're reprogramming it. */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 /*
                  * Expire far in the future, u300_set_next_event() will be
                  * called soon...
                  */
-                writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+                writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
                 /* We run one shot per tick here! */
                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
                 /* Enable interrupts for this timer */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Enable timer */
                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
                 break;
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 /* Disable interrupts on GP1 */
                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
                 /* Disable GP1 */
                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-                       U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
                 break;
         case CLOCK_EVT_MODE_RESUME:
                 /* Ignore this call */
@@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles,
 {
         /* Disable interrupts on GPT1 */
         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
         /* Disable GP1 while we're reprogramming it. */
         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
+               u300_timer_base + U300_TIMER_APP_DGPT1);
         /* Reset the General Purpose timer 1. */
         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+               u300_timer_base + U300_TIMER_APP_RGPT1);
         /* IRQ in n * cycles */
-        writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
+        writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
         /*
          * We run one shot per tick here! (This is necessary to reconfigure,
          * the timer will tilt if you don't!)
          */
         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
+               u300_timer_base + U300_TIMER_APP_SGPT1M);
         /* Enable timer interrupts */
         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
         /* Then enable the OS timer again */
         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
+               u300_timer_base + U300_TIMER_APP_EGPT1);
         return 0;
 }
 
@@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = &clockevent_u300_1mhz;
         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
+                u300_timer_base + U300_TIMER_APP_GPT1IA);
         evt->event_handler(evt);
         return IRQ_HANDLED;
 }
@@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = {
 
 static u32 notrace u300_read_sched_clock(void)
 {
-        return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+
+static unsigned long u300_read_current_timer(void)
+{
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 }
 
+static struct delay_timer u300_delay_timer;
 
 /*
  * This sets up the system timers, clock source and clock event.
  */
-void __init u300_timer_init(void)
+static void __init u300_timer_init_of(struct device_node *np)
 {
+        struct resource irq_res;
+        int irq;
         struct clk *clk;
         unsigned long rate;
 
+        u300_timer_base = of_iomap(np, 0);
+        if (!u300_timer_base)
+                panic("could not ioremap system timer\n");
+
+        /* Get the IRQ for the GP1 timer */
+        irq = of_irq_to_resource(np, 2, &irq_res);
+        if (irq <= 0)
+                panic("no IRQ for system timer\n");
+
+        pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
+
         /* Clock the interrupt controller */
-        clk = clk_get_sys("apptimer", NULL);
+        clk = of_clk_get(np, 0);
         BUG_ON(IS_ERR(clk));
         clk_prepare_enable(clk);
         rate = clk_get_rate(clk);
 
         setup_sched_clock(u300_read_sched_clock, 32, rate);
 
+        u300_delay_timer.read_current_timer = &u300_read_current_timer;
+        u300_delay_timer.freq = rate;
+        register_current_timer_delay(&u300_delay_timer);
+
         /*
          * Disable the "OS" and "DD" timers - these are designed for Symbian!
          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
          */
         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
+                u300_timer_base + U300_TIMER_APP_CRC);
         writel(U300_TIMER_APP_ROST_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
+                u300_timer_base + U300_TIMER_APP_ROST);
         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
+                u300_timer_base + U300_TIMER_APP_DOST);
         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
+                u300_timer_base + U300_TIMER_APP_RDDT);
         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
+                u300_timer_base + U300_TIMER_APP_DDDT);
 
         /* Reset the General Purpose timer 1. */
         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
+                u300_timer_base + U300_TIMER_APP_RGPT1);
 
         /* Set up the IRQ handler */
-        setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
+        setup_irq(irq, &u300_timer_irq);
 
         /* Reset the General Purpose timer 2 */
         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
+                u300_timer_base + U300_TIMER_APP_RGPT2);
         /* Set this timer to run around forever */
-        writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
+        writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
         /* Set continuous mode so it wraps around */
         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
-               U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
+               u300_timer_base + U300_TIMER_APP_SGPT2M);
         /* Disable timer interrupts */
         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
+                u300_timer_base + U300_TIMER_APP_GPT2IE);
         /* Then enable the GP2 timer to use as a free running us counter */
         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
-                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
+                u300_timer_base + U300_TIMER_APP_EGPT2);
 
         /* Use general purpose timer 2 as clock source */
-        if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+        if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
                 pr_err("timer: failed to initialize U300 clock source\n");
 
@@ -413,3 +437,6 @@ void __init u300_timer_init(void)
          * used by hrtimers!
          */
 }
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+                       u300_timer_init_of);
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index d34287bc34f5..000000000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1 +0,0 @@
-extern void u300_timer_init(void);
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f50772e169..000000000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Individual pin assignments for the B335/S335.
- * Notice that the actual usage of these pins depends on the
- * PAD MUX settings, that is why the same number can potentially
- * appear several times. In the reference design each pin is only
- * used for one purpose. These were determined by inspecting the
- * S365 schematic.
- */
-#define U300_GPIO_PIN_UART_RX           0
-#define U300_GPIO_PIN_UART_TX           1
-#define U300_GPIO_PIN_UART_CTS          2
-#define U300_GPIO_PIN_UART_RTS          3
-#define U300_GPIO_PIN_CAM_MAIN_STANDBY  4 /* Camera MAIN standby */
-#define U300_GPIO_PIN_GPIO05            5 /* Unrouted */
-#define U300_GPIO_PIN_MS_CD             6 /* Memory Stick Card insertion */
-#define U300_GPIO_PIN_GPIO07            7 /* Test point TP2430 */
-
-#define U300_GPIO_PIN_GPIO08            8 /* Test point TP2437 */
-#define U300_GPIO_PIN_GPIO09            9 /* Test point TP2431 */
-#define U300_GPIO_PIN_GPIO10            10 /* Test point TP2432 */
-#define U300_GPIO_PIN_MMC_CLKRET        11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD            12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_CAM_SUB_STANDBY   13 /* Camera SUB standby */
-#define U300_GPIO_PIN_GPIO14            14 /* Test point TP2436 */
-#define U300_GPIO_PIN_GPIO15            15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16            16 /* Test point TP2438 */
-#define U300_GPIO_PIN_PHFSENSE          17 /* Headphone jack sensing */
-#define U300_GPIO_PIN_GPIO18            18 /* Test point TP2439 */
-#define U300_GPIO_PIN_GPIO19            19 /* Routed somewhere */
-#define U300_GPIO_PIN_GPIO20            20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21            21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22            22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23            23 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO24            24 /* Unrouted */
-#define U300_GPIO_PIN_GPIO25            25 /* Unrouted */
-#define U300_GPIO_PIN_GPIO26            26 /* Unrouted */
-#define U300_GPIO_PIN_GPIO27            27 /* Unrouted */
-#define U300_GPIO_PIN_GPIO28            28 /* Unrouted */
-#define U300_GPIO_PIN_GPIO29            29 /* Unrouted */
-#define U300_GPIO_PIN_GPIO30            30 /* Unrouted */
-#define U300_GPIO_PIN_GPIO31            31 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO32            32 /* Unrouted */
-#define U300_GPIO_PIN_GPIO33            33 /* Unrouted */
-#define U300_GPIO_PIN_GPIO34            34 /* Unrouted */
-#define U300_GPIO_PIN_GPIO35            35 /* Unrouted */
-#define U300_GPIO_PIN_GPIO36            36 /* Unrouted */
-#define U300_GPIO_PIN_GPIO37            37 /* Unrouted */
-#define U300_GPIO_PIN_GPIO38            38 /* Unrouted */
-#define U300_GPIO_PIN_GPIO39            39 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO40            40 /* Unrouted */
-#define U300_GPIO_PIN_GPIO41            41 /* Unrouted */
-#define U300_GPIO_PIN_GPIO42            42 /* Unrouted */
-#define U300_GPIO_PIN_GPIO43            43 /* Unrouted */
-#define U300_GPIO_PIN_GPIO44            44 /* Unrouted */
-#define U300_GPIO_PIN_GPIO45            45 /* Unrouted */
-#define U300_GPIO_PIN_GPIO46            46 /* Unrouted */
-#define U300_GPIO_PIN_GPIO47            47 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO48            48 /* Unrouted */
-#define U300_GPIO_PIN_GPIO49            49 /* Unrouted */
-#define U300_GPIO_PIN_GPIO50            50 /* Unrouted */
-#define U300_GPIO_PIN_GPIO51            51 /* Unrouted */
-#define U300_GPIO_PIN_GPIO52            52 /* Unrouted */
-#define U300_GPIO_PIN_GPIO53            53 /* Unrouted */
-#define U300_GPIO_PIN_GPIO54            54 /* Unrouted */
-#define U300_GPIO_PIN_GPIO55            55 /* Unrouted */
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index aba9e5692958..bfe443daf4b0 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -21,28 +21,14 @@
 
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 static struct stedma40_chan_cfg msp0_dma_tx = {
         .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 struct msp_i2s_platform_data msp0_platform_data = {
@@ -53,28 +39,14 @@ struct msp_i2s_platform_data msp0_platform_data = {
 
 static struct stedma40_chan_cfg msp1_dma_rx = {
         .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV30_MSP3,
 };
 
 static struct stedma40_chan_cfg msp1_dma_tx = {
         .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV30_MSP1,
 };
 
 struct msp_i2s_platform_data msp1_platform_data = {
@@ -85,32 +57,16 @@ struct msp_i2s_platform_data msp1_platform_data = {
 
 static struct stedma40_chan_cfg msp2_dma_rx = {
         .high_priority = true,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-
-        /* data_width is set during configuration */
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV14_MSP2,
 };
 
 static struct stedma40_chan_cfg msp2_dma_tx = {
         .high_priority = true,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV14_MSP2,
         .use_fixed_channel = true,
         .phy_channel = 1,
-
-        /* data_width is set during configuration */
 };
 
 static struct platform_device *db8500_add_msp_i2s(struct device *parent,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 947bd9eca079..7936d40a5c37 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -9,6 +9,7 @@
 #include <linux/bug.h>
 #include <linux/string.h>
 #include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
 
 #include <asm/mach-types.h>
@@ -34,6 +35,11 @@ BIAS(in_pd, PIN_INPUT_PULLDOWN);
 BIAS(out_hi, PIN_OUTPUT_HIGH);
 BIAS(out_lo, PIN_OUTPUT_LOW);
 BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
+
+BIAS(abx500_out_lo, PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0));
+BIAS(abx500_in_pd, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 1));
+BIAS(abx500_in_nopull, PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0));
+
 /* These also force them into GPIO mode */
 BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
@@ -42,8 +48,6 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
 BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
 BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
 /* Sleep modes */
-BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_in_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
@@ -54,8 +58,6 @@ BIAS(slpm_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
 BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
-BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|
-        PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
 BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
         PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
 BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|
@@ -97,6 +99,252 @@ BIAS(out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|
 #define DB8500_PIN_STATE(pin, conf, dev, state) \
         PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-db8500", pin, conf)
 
+#define AB8500_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8500_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8500.0", group, func)
+#define AB8500_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8500.0", pin, abx500_##conf)
+
+#define AB8505_MUX_HOG(group, func) \
+        PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_HOG(pin, conf) \
+        PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-ab8505.0", pin, abx500_##conf)
+
+#define AB8505_MUX_STATE(group, func, dev, state) \
+        PIN_MAP_MUX_GROUP(dev, state, "pinctrl-ab8505.0", group, func)
+#define AB8505_PIN_STATE(pin, conf, dev, state) \
+        PIN_MAP_CONFIGS_PIN(dev, state, "pinctrl-ab8505.0", pin, abx500_##conf)
+
+static struct pinctrl_map __initdata ab8500_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8500_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.35", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO1_T10", in_nopull, "regulator.35", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio1_a_1", "gpio", "regulator.35", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO1_T10", in_pd, "regulator.35", PINCTRL_STATE_SLEEP),
+
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO2_T9", in_pd),
+
+        /* Sysclkreq4 */
+        AB8500_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8500_PIN_STATE("GPIO3_U9", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8500_MUX_STATE("gpio3_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8500_PIN_STATE("GPIO3_U9", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+        /* pins 4 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8500_MUX_HOG("gpio4_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO4_W2", in_pd),
+
+        /*
+         * pins 6,7,8 and 9 are muxed in YCBCR0123
+         * configured in INPUT PULL UP
+         */
+        AB8500_MUX_HOG("ycbcr0123_d_1", "ycbcr"),
+        AB8500_PIN_HOG("GPIO6_Y18", in_nopull),
+        AB8500_PIN_HOG("GPIO7_AA20", in_nopull),
+        AB8500_PIN_HOG("GPIO8_W18", in_nopull),
+        AB8500_PIN_HOG("GPIO9_AA19", in_nopull),
+
+        /*
+         * pins 10,11,12 and 13 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO10_U17", in_pd),
+
+        AB8500_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO11_AA18", in_pd),
+
+        AB8500_MUX_HOG("gpio12_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO12_U16", in_pd),
+
+        AB8500_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO13_W17", in_pd),
+
+        /*
+         * pins 14,15 are muxed in PWM1 and PWM2
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+        AB8500_MUX_HOG("pwmout2_d_1", "pwmout"),
+        AB8500_PIN_HOG("GPIO15_B17", in_pd),
+
+        /*
+         * pins 16 is muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio16_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO14_F14", in_pd),
+
+        /*
+         * pins 17,18,19 and 20 are muxed in AUDIO interface 1
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("adi1_d_1", "adi1"),
+        AB8500_PIN_HOG("GPIO17_P5", in_pd),
+        AB8500_PIN_HOG("GPIO18_R5", in_pd),
+        AB8500_PIN_HOG("GPIO19_U5", in_pd),
+        AB8500_PIN_HOG("GPIO20_T5", in_pd),
+
+        /*
+         * pins 21,22 and 23 are muxed in USB UICC
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("usbuicc_d_1", "usbuicc"),
+        AB8500_PIN_HOG("GPIO21_H19", in_pd),
+        AB8500_PIN_HOG("GPIO22_G20", in_pd),
+        AB8500_PIN_HOG("GPIO23_G19", in_pd),
+
+        /*
+         * pins 24,25 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio24_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO24_T14", in_pd),
+
+        AB8500_MUX_HOG("gpio25_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO25_R16", in_pd),
+
+        /*
+         * pins 26 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio26_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO26_M16", out_lo),
+
+        /*
+         * pins 27,28 are muxed in DMIC12
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic12_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO27_J6", in_pd),
+        AB8500_PIN_HOG("GPIO28_K6", in_pd),
+
+        /*
+         * pins 29,30 are muxed in DMIC34
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic34_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO29_G6", in_pd),
+        AB8500_PIN_HOG("GPIO30_H6", in_pd),
+
+        /*
+         * pins 31,32 are muxed in DMIC56
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("dmic56_d_1", "dmic"),
+        AB8500_PIN_HOG("GPIO31_F5", in_pd),
+        AB8500_PIN_HOG("GPIO32_G5", in_pd),
+
+        /*
+         * pins 34 is muxed in EXTCPENA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("extcpena_d_1", "extcpena"),
+        AB8500_PIN_HOG("GPIO34_R17", in_pd),
+
+        /*
+         * pins 35 is muxed in GPIO
+         * configured in OUTPUT LOW
+         */
+        AB8500_MUX_HOG("gpio35_d_1", "gpio"),
+        AB8500_PIN_HOG("GPIO35_W15", in_pd),
+
+        /*
+         * pins 36,37,38 and 39 are muxed in GPIO
+         * configured in INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio36_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO36_A17", in_pd),
+
+        AB8500_MUX_HOG("gpio37_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO37_E15", in_pd),
+
+        AB8500_MUX_HOG("gpio38_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO38_C17", in_pd),
+
+        AB8500_MUX_HOG("gpio39_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO39_E16", in_pd),
+
+        /*
+         * pins 40 and 41 are muxed in MODCSLSDA
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8500_PIN_HOG("GPIO40_T19", in_pd),
+        AB8500_PIN_HOG("GPIO41_U19", in_pd),
+
+        /*
+         * pins 42 is muxed in GPIO
+         * configured INPUT PULL DOWN
+         */
+        AB8500_MUX_HOG("gpio42_a_1", "gpio"),
+        AB8500_PIN_HOG("GPIO42_U2", in_pd),
+};
+
+static struct pinctrl_map __initdata ab8505_pinmap[] = {
+        /* Sysclkreq2 */
+        AB8505_MUX_STATE("sysclkreq2_d_1", "sysclkreq", "regulator.36", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO1_N4", in_nopull, "regulator.36", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq2 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio1_a_1", "gpio", "regulator.36", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO1_N4", in_pd, "regulator.36", PINCTRL_STATE_SLEEP),
+
+        /* pins 2 is muxed in GPIO, configured in INPUT PULL DOWN */
+        AB8505_MUX_HOG("gpio2_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO2_R5", in_pd),
+
+        /* Sysclkreq4 */
+        AB8505_MUX_STATE("sysclkreq4_d_1", "sysclkreq", "regulator.37", PINCTRL_STATE_DEFAULT),
+        AB8505_PIN_STATE("GPIO3_P5", in_nopull, "regulator.37", PINCTRL_STATE_DEFAULT),
+        /* sysclkreq4 disable, mux in gpio configured in input pulldown */
+        AB8505_MUX_STATE("gpio3_a_1", "gpio", "regulator.37", PINCTRL_STATE_SLEEP),
+        AB8505_PIN_STATE("GPIO3_P5", in_pd, "regulator.37", PINCTRL_STATE_SLEEP),
+
+        AB8505_MUX_HOG("gpio10_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO10_B16", in_pd),
+
+        AB8505_MUX_HOG("gpio11_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO11_B17", in_pd),
+
+        AB8505_MUX_HOG("gpio13_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO13_D17", in_nopull),
+
+        AB8505_MUX_HOG("pwmout1_d_1", "pwmout"),
+        AB8505_PIN_HOG("GPIO14_C16", in_pd),
+
+        AB8505_MUX_HOG("adi2_d_1", "adi2"),
+        AB8505_PIN_HOG("GPIO17_P2", in_pd),
+        AB8505_PIN_HOG("GPIO18_N3", in_pd),
+        AB8505_PIN_HOG("GPIO19_T1", in_pd),
+        AB8505_PIN_HOG("GPIO20_P3", in_pd),
+
+        AB8505_MUX_HOG("gpio34_a_1", "gpio"),
+        AB8505_PIN_HOG("GPIO34_H14", in_pd),
+
+        AB8505_MUX_HOG("modsclsda_d_1", "modsclsda"),
+        AB8505_PIN_HOG("GPIO40_J15", in_pd),
+        AB8505_PIN_HOG("GPIO41_J14", in_pd),
+
+        AB8505_MUX_HOG("gpio50_d_1", "gpio"),
+        AB8505_PIN_HOG("GPIO50_L4", in_nopull),
+
+        AB8505_MUX_HOG("resethw_d_1", "resethw"),
+        AB8505_PIN_HOG("GPIO52_D16", in_pd),
+
+        AB8505_MUX_HOG("service_d_1", "service"),
+        AB8505_PIN_HOG("GPIO53_D15", in_pd),
+};
+
 /* Pin control settings */
 static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         /*
@@ -174,17 +422,12 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
         DB8500_PIN_SLEEP("GPIO4_AH6", slpm_in_wkup_pdis, "uart1"),
         DB8500_PIN_SLEEP("GPIO5_AG6", slpm_out_wkup_pdis, "uart1"),
         /* MSP1 for ALSA codec */
-        DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
-        /* MSP1 sleep state */
-        DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
-        DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
+        DB8500_MUX_HOG("msp1txrx_a_1", "msp1"),
+        DB8500_MUX_HOG("msp1_a_1", "msp1"),
+        DB8500_PIN_HOG("GPIO33_AF2", out_lo_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO34_AE1", in_nopull_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO35_AE2", in_nopull_slpm_nowkup),
+        DB8500_PIN_HOG("GPIO36_AG2", in_nopull_slpm_nowkup),
         /* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
         DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
         DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
@@ -821,6 +1064,12 @@ void __init mop500_pinmaps_init(void)
         pinctrl_register_mappings(mop500_pinmap,
                                   ARRAY_SIZE(mop500_pinmap));
         mop500_href_family_pinmaps_init();
+        if (machine_is_u8520())
+                pinctrl_register_mappings(ab8505_pinmap,
+                                          ARRAY_SIZE(ab8505_pinmap));
+        else
+                pinctrl_register_mappings(ab8500_pinmap,
+                                          ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init snowball_pinmaps_init(void)
@@ -831,6 +1080,8 @@ void __init snowball_pinmaps_init(void)
                                   ARRAY_SIZE(snowball_pinmap));
         pinctrl_register_mappings(u8500_pinmap,
                                   ARRAY_SIZE(u8500_pinmap));
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
 
 void __init hrefv60_pinmaps_init(void)
@@ -840,4 +1091,6 @@ void __init hrefv60_pinmaps_init(void)
         pinctrl_register_mappings(hrefv60_pinmap,
                                   ARRAY_SIZE(hrefv60_pinmap));
         mop500_href_family_pinmaps_init();
+        pinctrl_register_mappings(ab8500_pinmap,
+                                  ARRAY_SIZE(ab8500_pinmap));
 }
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index d6b7c8556fa1..0dc44c683427 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -999,7 +999,6 @@ struct ab8500_regulator_platform_data ab8500_regulator_plat_data = {
         .num_ext_regulator      = ARRAY_SIZE(ab8500_ext_regulators),
 };
 
-/* Use the AB8500 init settings for AB8505 as they are the same right now */
 struct ab8500_regulator_platform_data ab8505_regulator_plat_data = {
         .reg_init               = ab8505_reg_init,
         .num_reg_init           = ARRAY_SIZE(ab8505_reg_init),
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef38775a0c1..b3e61a38e5c8 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -34,29 +34,25 @@
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 #endif
 
 struct mmci_platform_data mop500_sdi0_data = {
-        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
+        .f_max          = 100000000,
         .capabilities   = MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_MMC_HIGHSPEED,
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_UHS_SDR12 |
+                                MMC_CAP_UHS_SDR25,
         .gpio_wp        = -1,
         .sigdir         = MCI_ST_FBCLKEN |
                                 MCI_ST_CMDDIREN |
@@ -87,27 +83,22 @@ void mop500_sdi_tc35892_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 #endif
 
 struct mmci_platform_data mop500_sdi1_data = {
         .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -124,28 +115,26 @@ struct mmci_platform_data mop500_sdi1_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type =  DB8500_DMA_DEV28_SD_MM2,
 };
 
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV28_SD_MM2,
 };
 #endif
 
 struct mmci_platform_data mop500_sdi2_data = {
         .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
@@ -162,28 +151,25 @@ struct mmci_platform_data mop500_sdi2_data = {
 #ifdef CONFIG_STE_DMA40
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type =  DB8500_DMA_DEV42_SD_MM4,
 };
 
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV42_SD_MM4,
 };
 #endif
 
 struct mmci_platform_data mop500_sdi4_data = {
-        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 50000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
-                          MMC_CAP_MMC_HIGHSPEED,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_NONREMOVABLE |
+                                MMC_CAP_MMC_HIGHSPEED |
+                                MMC_CAP_ERASE |
+                                MMC_CAP_CMD23,
         .gpio_cd        = -1,
         .gpio_wp        = -1,
 #ifdef CONFIG_STE_DMA40
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 78389de94dde..df5d27a532e9 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -413,47 +413,23 @@ static void mop500_prox_deactivate(struct device *dev)
         regulator_put(prox_regulator);
 }
 
-void mop500_snowball_ethernet_clock_enable(void)
-{
-        struct clk *clk;
-
-        clk = clk_get_sys("fsmc", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-}
-
 static struct cryp_platform_data u8500_cryp1_platform_data = {
                 .mem_to_engine = {
-                                .dir = STEDMA40_MEM_TO_PERIPH,
-                                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-                                .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                                .dir = DMA_MEM_TO_DEV,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
                                 .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                 },
                 .engine_to_mem = {
-                                .dir = STEDMA40_PERIPH_TO_MEM,
-                                .src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
-                                .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                                .dir = DMA_DEV_TO_MEM,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
                                 .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                 }
 };
 
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
-                .dir = STEDMA40_MEM_TO_PERIPH,
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-                .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
-                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                .dir = DMA_MEM_TO_DEV,
+                .dev_type = DB8500_DMA_DEV50_HAC1_TX,
                 .mode = STEDMA40_MODE_LOGICAL,
-                .src_info.psize = STEDMA40_PSIZE_LOG_16,
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 
 static struct hash_platform_data u8500_hash1_platform_data = {
@@ -470,20 +446,14 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
 };
 
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
 };
 #endif
 
@@ -511,56 +481,38 @@ static void __init mop500_spi_init(struct device *parent)
 #ifdef CONFIG_STE_DMA40
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_DEV_TO_MEM,
+        .dev_type = DB8500_DMA_DEV11_UART2,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
-        .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dir = DMA_MEM_TO_DEV,
+        .dev_type = DB8500_DMA_DEV11_UART2,
 };
 #endif
 
@@ -674,7 +626,7 @@ static void __init snowball_init_machine(void)
         mop500_audio_init(parent);
         mop500_uart_init(parent);
 
-        mop500_snowball_ethernet_clock_enable();
+        u8500_cryp1_hash1_init(parent);
 
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 49514b825034..d6fab166cbf1 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
 extern struct amba_pl011_data uart1_plat;
 extern struct amba_pl011_data uart2_plat;
 extern struct pl022_ssp_controller ssp0_plat;
+extern struct stedma40_platform_data dma40_plat_data;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
@@ -104,7 +105,6 @@ void __init mop500_pinmaps_init(void);
 void __init snowball_pinmaps_init(void);
 void __init hrefv60_pinmaps_init(void);
 void mop500_audio_init(struct device *parent);
-void mop500_snowball_ethernet_clock_enable(void);
 
 int __init mop500_uib_init(void);
 void mop500_uib_i2c_add(int busnum, struct i2c_board_info *info,
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index f58615b5c601..82ccf1d98735 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -42,7 +42,8 @@ static int __init ux500_l2x0_init(void)
         if (cpu_is_u8500_family() || cpu_is_ux540_family())
                 l2x0_base = __io_address(U8500_L2CC_BASE);
         else
-                ux500_unknown_soc();
+                /* Non-Ux500 platform */
+                return -ENODEV;
 
         /* Unlock before init */
         ux500_l2x0_unlock();
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52890bc..12eee8167525 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent)
         dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
 
-static int usb_db8500_rx_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8
-};
-
-static int usb_db8500_tx_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8
+static int usb_db8500_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
 };
 
 static const char *db8500_read_soc_id(void)
@@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void)
 
         db8500_add_rtc(parent);
         db8500_add_gpios(parent);
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+        db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
                 platform_devs[i]->dev.parent = parent;
@@ -226,34 +215,13 @@ struct device * __init u8500_init_devices(void)
 }
 
 #ifdef CONFIG_MACH_UX500_DT
-
-/* TODO: Once all pieces are DT:ed, remove completely. */
-static struct device * __init u8500_of_init_devices(void)
-{
-        struct device *parent = db8500_soc_device_init();
-
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
-
-        u8500_dma40_device.dev.parent = parent;
-
-        /*
-         * Devices to be DT:ed:
-         *   u8500_dma40_device  = todo
-         *   db8500_pmu_device   = done
-         *   db8500_prcmu_device = done
-         */
-        platform_device_register(&u8500_dma40_device);
-
-        return parent;
-}
-
 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires call-back bindings. */
         OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
         /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
         OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
@@ -274,11 +242,16 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
                         &db8500_prcmu_pdata),
         OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
+        OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
+        OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
+                        NULL),
         /* Requires device name bindings. */
-        OF_DEV_AUXDATA("stericsson,nmk-pinctrl", U8500_PRCMU_BASE,
+        OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
                 "pinctrl-db8500", NULL),
         /* Requires clock name and DMA bindings. */
         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
@@ -289,6 +262,18 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
                 "ux500-msp-i2s.2", &msp2_platform_data),
         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
                 "ux500-msp-i2s.3", &msp3_platform_data),
+        /* Requires clock name bindings and channel address lookup table. */
+        OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
+        {},
+};
+
+static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
+        /* Requires DMA bindings. */
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
+        OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
+                        &db8500_prcmu_pdata),
         {},
 };
 
@@ -302,24 +287,25 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
 
 static void __init u8500_init_machine(void)
 {
-        struct device *parent = NULL;
+        struct device *parent = db8500_soc_device_init();
 
         /* Pinmaps must be in place before devices register */
         if (of_machine_is_compatible("st-ericsson,mop500"))
                 mop500_pinmaps_init();
         else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
                 snowball_pinmaps_init();
-                mop500_snowball_ethernet_clock_enable();
         } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
                 hrefv60_pinmaps_init();
         else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
                 /* TODO: Add pinmaps for ccu9540 board. */
 
-        /* TODO: Export SoC, USB, cpu-freq and DMA40 */
-        parent = u8500_of_init_devices();
-
-        /* automatically probe child nodes of db8500 device */
-        of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
+        /* automatically probe child nodes of dbx5x0 devices */
+        if (of_machine_is_compatible("st-ericsson,u8540"))
+                of_platform_populate(NULL, u8500_local_bus_nodes,
+                                     u8540_auxdata_lookup, parent);
+        else
+                of_platform_populate(NULL, u8500_local_bus_nodes,
+                                     u8500_auxdata_lookup, parent);
 }
 
 static const char * stericsson_dt_platform_compat[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index b6145ea51641..e6fb0239151b 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -76,13 +76,15 @@ void __init ux500_init_irq(void)
         } else if (cpu_is_u9540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K - 1);
-                u8500_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                u9540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
                                U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
                                U8500_CLKRST6_BASE);
         } else if (cpu_is_u8540()) {
                 prcmu_early_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
                 ux500_pm_init(U8500_PRCMU_BASE, SZ_8K + SZ_4K - 1);
-                u8540_clk_init();
+                u8540_clk_init(U8500_CLKRST1_BASE, U8500_CLKRST2_BASE,
+                               U8500_CLKRST3_BASE, U8500_CLKRST5_BASE,
+                               U8500_CLKRST6_BASE);
         }
 }
 
diff --git a/arch/arm/mach-ux500/db8500-regs.h b/arch/arm/mach-ux500/db8500-regs.h
index b2d7a0b98629..27399553c841 100644
--- a/arch/arm/mach-ux500/db8500-regs.h
+++ b/arch/arm/mach-ux500/db8500-regs.h
@@ -102,7 +102,6 @@
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
 #define U9540_DMC1_BASE         (U8500_PER4_BASE + 0x0A000)
 #define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
-#define U9540_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x6A000)
 #define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 #define U8500_PRCMU_TIMER_3_BASE (U8500_PER4_BASE + 0x07338)
 #define U8500_PRCMU_TIMER_4_BASE (U8500_PER4_BASE + 0x07450)
@@ -184,7 +183,7 @@
 #define U8500_IO_VIRTUAL        0xf0000000
 #define U8500_IO_PHYSICAL       0xa0000000
 /* This is where we map in the ROM to check ASIC IDs */
-#define UX500_VIRT_ROM          0xf0000000
+#define UX500_VIRT_ROM          IOMEM(0xf0000000)
 
 /* This macro is used in assembly, so no cast */
 #define IO_ADDRESS(x)           \
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..516a6f57d159 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
         }
 };
 
-/* Default configuration for physcial memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-        .mode = STEDMA40_MODE_PHYSICAL,
-        .dir = STEDMA40_MEM_TO_MEM,
-
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_PHY_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-        .dir = STEDMA40_MEM_TO_MEM,
-
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
-        /* PrimeCells - run-time configured */
-        [DB8500_DMA_DEV0_SPI0_TX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-        [DB8500_DMA_DEV8_SSP0_TX] = -1,
-        [DB8500_DMA_DEV9_SSP1_TX] = -1,
-        [DB8500_DMA_DEV11_UART2_TX] = -1,
-        [DB8500_DMA_DEV12_UART1_TX] = -1,
-        [DB8500_DMA_DEV13_UART0_TX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-        [DB8500_DMA_DEV33_SPI2_TX] = -1,
-        [DB8500_DMA_DEV35_SPI1_TX] = -1,
-        [DB8500_DMA_DEV40_SPI3_TX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-        [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-        [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
-        /* PrimeCells */
-        [DB8500_DMA_DEV0_SPI0_RX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-        [DB8500_DMA_DEV8_SSP0_RX] = -1,
-        [DB8500_DMA_DEV9_SSP1_RX] = -1,
-        [DB8500_DMA_DEV11_UART2_RX] = -1,
-        [DB8500_DMA_DEV12_UART1_RX] = -1,
-        [DB8500_DMA_DEV13_UART0_RX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-        [DB8500_DMA_DEV33_SPI2_RX] = -1,
-        [DB8500_DMA_DEV35_SPI1_RX] = -1,
-        [DB8500_DMA_DEV40_SPI3_RX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-        [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
-/* Reserved event lines for memcpy only */
-static int dma40_memcpy_event[] = {
-        DB8500_DMA_MEMCPY_TX_0,
-        DB8500_DMA_MEMCPY_TX_1,
-        DB8500_DMA_MEMCPY_TX_2,
-        DB8500_DMA_MEMCPY_TX_3,
-        DB8500_DMA_MEMCPY_TX_4,
-        DB8500_DMA_MEMCPY_TX_5,
-};
-
-static struct stedma40_platform_data dma40_plat_data = {
-        .dev_len = DB8500_DMA_NR_DEV,
-        .dev_rx = dma40_rx_map,
-        .dev_tx = dma40_tx_map,
-        .memcpy = dma40_memcpy_event,
-        .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
-        .memcpy_conf_phy = &dma40_memcpy_conf_phy,
-        .memcpy_conf_log = &dma40_memcpy_conf_log,
+struct stedma40_platform_data dma40_plat_data = {
         .disabled_channels = {-1},
 };
 
@@ -227,7 +106,7 @@ static struct resource db8500_prcmu_res[] = {
         {
                 .name  = "prcmu-tcpm",
                 .start = U8500_PRCMU_TCPM_BASE,
-                .end   = U8500_PRCMU_TCPM_BASE + SZ_4K - 1,
+                .end   = U8500_PRCMU_TCPM_BASE + SZ_32K - 1,
                 .flags = IORESOURCE_MEM,
         },
 };
diff --git a/arch/arm/mach-ux500/id.c b/arch/arm/mach-ux500/id.c
index 0d33d1a06955..392f2fdb37d0 100644
--- a/arch/arm/mach-ux500/id.c
+++ b/arch/arm/mach-ux500/id.c
@@ -21,11 +21,11 @@
 
 struct dbx500_asic_id dbx500_id;
 
-static unsigned int ux500_read_asicid(phys_addr_t addr)
+static unsigned int __init ux500_read_asicid(phys_addr_t addr)
 {
         phys_addr_t base = addr & ~0xfff;
         struct map_desc desc = {
-                .virtual        = UX500_VIRT_ROM,
+                .virtual        = (unsigned long)UX500_VIRT_ROM,
                 .pfn            = __phys_to_pfn(base),
                 .length         = SZ_16K,
                 .type           = MT_DEVICE,
@@ -37,7 +37,7 @@ static unsigned int ux500_read_asicid(phys_addr_t addr)
         local_flush_tlb_all();
         flush_cache_all();
 
-        return readl(IOMEM(UX500_VIRT_ROM + (addr & 0xfff)));
+        return readl(UX500_VIRT_ROM + (addr & 0xfff));
 }
 
 static void ux500_print_soc_info(unsigned int asicid)
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419bea76..0296ae5b0fd9 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
 
 #define DB8500_DMA_NR_DEV 64
 
-enum dma_src_dev_type {
-        DB8500_DMA_DEV0_SPI0_RX = 0,
-        DB8500_DMA_DEV1_SD_MMC0_RX = 1,
-        DB8500_DMA_DEV2_SD_MMC1_RX = 2,
-        DB8500_DMA_DEV3_SD_MMC2_RX = 3,
-        DB8500_DMA_DEV4_I2C1_RX = 4,
-        DB8500_DMA_DEV5_I2C3_RX = 5,
-        DB8500_DMA_DEV6_I2C2_RX = 6,
-        DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
-        DB8500_DMA_DEV8_SSP0_RX = 8,
-        DB8500_DMA_DEV9_SSP1_RX = 9,
-        DB8500_DMA_DEV10_MCDE_RX = 10,
-        DB8500_DMA_DEV11_UART2_RX = 11,
-        DB8500_DMA_DEV12_UART1_RX = 12,
-        DB8500_DMA_DEV13_UART0_RX = 13,
-        DB8500_DMA_DEV14_MSP2_RX = 14,
-        DB8500_DMA_DEV15_I2C0_RX = 15,
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
-        DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
-        DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
-        DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
-        DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
-        DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
-        DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
-        DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
-        DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
-        DB8500_DMA_DEV28_SD_MM2_RX = 28,
-        DB8500_DMA_DEV29_SD_MM0_RX = 29,
-        DB8500_DMA_DEV30_MSP1_RX = 30,
+/*
+ * Unless otherwise specified, all channels numbers are used for
+ * TX & RX, and can be used for either source or destination
+ * channels.
+ */
+enum dma_dev_type {
+        DB8500_DMA_DEV0_SPI0 = 0,
+        DB8500_DMA_DEV1_SD_MMC0 = 1,
+        DB8500_DMA_DEV2_SD_MMC1 = 2,
+        DB8500_DMA_DEV3_SD_MMC2 = 3,
+        DB8500_DMA_DEV4_I2C1 = 4,
+        DB8500_DMA_DEV5_I2C3 = 5,
+        DB8500_DMA_DEV6_I2C2 = 6,
+        DB8500_DMA_DEV7_I2C4 = 7,                       /* Only on V1 and later */
+        DB8500_DMA_DEV8_SSP0 = 8,
+        DB8500_DMA_DEV9_SSP1 = 9,
+        DB8500_DMA_DEV10_MCDE_RX = 10,                  /* RX only */
+        DB8500_DMA_DEV11_UART2 = 11,
+        DB8500_DMA_DEV12_UART1 = 12,
+        DB8500_DMA_DEV13_UART0 = 13,
+        DB8500_DMA_DEV14_MSP2 = 14,
+        DB8500_DMA_DEV15_I2C0 = 15,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
+        DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
+        DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
+        DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
+        DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
+        DB8500_DMA_DEV24_SXA0 = 24,
+        DB8500_DMA_DEV25_SXA1 = 25,
+        DB8500_DMA_DEV26_SXA2 = 26,
+        DB8500_DMA_DEV27_SXA3 = 27,
+        DB8500_DMA_DEV28_SD_MM2 = 28,
+        DB8500_DMA_DEV29_SD_MM0 = 29,
+        DB8500_DMA_DEV30_MSP1 = 30,
         /* On DB8500v2, MSP3 RX replaces MSP1 RX */
-        DB8500_DMA_DEV30_MSP3_RX = 30,
-        DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
-        DB8500_DMA_DEV32_SD_MM1_RX = 32,
-        DB8500_DMA_DEV33_SPI2_RX = 33,
-        DB8500_DMA_DEV34_I2C3_RX2 = 34,
-        DB8500_DMA_DEV35_SPI1_RX = 35,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_RX = 40,
-        DB8500_DMA_DEV41_SD_MM3_RX = 41,
-        DB8500_DMA_DEV42_SD_MM4_RX = 42,
-        DB8500_DMA_DEV43_SD_MM5_RX = 43,
-        DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
-        DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
-        DB8500_DMA_DEV48_CAC1_RX = 48,
-        /* 49, 50 and 51 are not used */
-        DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
-        DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
-        DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
-        DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
-        /* 56, 57, 58, 59 and 60 are not used */
-        DB8500_DMA_DEV61_CAC0_RX = 61,
-        /* 62 and 63 are not used */
-};
-
-enum dma_dest_dev_type {
-        DB8500_DMA_DEV0_SPI0_TX = 0,
-        DB8500_DMA_DEV1_SD_MMC0_TX = 1,
-        DB8500_DMA_DEV2_SD_MMC1_TX = 2,
-        DB8500_DMA_DEV3_SD_MMC2_TX = 3,
-        DB8500_DMA_DEV4_I2C1_TX = 4,
-        DB8500_DMA_DEV5_I2C3_TX = 5,
-        DB8500_DMA_DEV6_I2C2_TX = 6,
-        DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
-        DB8500_DMA_DEV8_SSP0_TX = 8,
-        DB8500_DMA_DEV9_SSP1_TX = 9,
-        /* 10 is not used*/
-        DB8500_DMA_DEV11_UART2_TX = 11,
-        DB8500_DMA_DEV12_UART1_TX = 12,
-        DB8500_DMA_DEV13_UART0_TX = 13,
-        DB8500_DMA_DEV14_MSP2_TX = 14,
-        DB8500_DMA_DEV15_I2C0_TX = 15,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
-        DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
-        DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
-        DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
-        DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
-        DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
-        DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
-        DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
-        DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
-        DB8500_DMA_DEV28_SD_MM2_TX = 28,
-        DB8500_DMA_DEV29_SD_MM0_TX = 29,
-        DB8500_DMA_DEV30_MSP1_TX = 30,
-        DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
-        DB8500_DMA_DEV32_SD_MM1_TX = 32,
-        DB8500_DMA_DEV33_SPI2_TX = 33,
-        DB8500_DMA_DEV34_I2C3_TX2 = 34,
-        DB8500_DMA_DEV35_SPI1_TX = 35,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_TX = 40,
-        DB8500_DMA_DEV41_SD_MM3_TX = 41,
-        DB8500_DMA_DEV42_SD_MM4_TX = 42,
-        DB8500_DMA_DEV43_SD_MM5_TX = 43,
-        DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
-        DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
-        DB8500_DMA_DEV48_CAC1_TX  = 48,
-        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
-        DB8500_DMA_DEV50_HAC1_TX = 50,
-        DB8500_DMA_MEMCPY_TX_0 = 51,
-        DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
-        DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
-        DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
-        DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
-        DB8500_DMA_MEMCPY_TX_1 = 56,
-        DB8500_DMA_MEMCPY_TX_2 = 57,
-        DB8500_DMA_MEMCPY_TX_3 = 58,
-        DB8500_DMA_MEMCPY_TX_4 = 59,
-        DB8500_DMA_MEMCPY_TX_5 = 60,
-        DB8500_DMA_DEV61_CAC0_TX = 61,
-        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
-        DB8500_DMA_DEV63_HAC0_TX = 63,
+        DB8500_DMA_DEV30_MSP3 = 30,
+        DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
+        DB8500_DMA_DEV32_SD_MM1 = 32,
+        DB8500_DMA_DEV33_SPI2 = 33,
+        DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
+        DB8500_DMA_DEV35_SPI1 = 35,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
+        DB8500_DMA_DEV40_SPI3 = 40,
+        DB8500_DMA_DEV41_SD_MM3 = 41,
+        DB8500_DMA_DEV42_SD_MM4 = 42,
+        DB8500_DMA_DEV43_SD_MM5 = 43,
+        DB8500_DMA_DEV44_SXA4 = 44,
+        DB8500_DMA_DEV45_SXA5 = 45,
+        DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
+        DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
+        DB8500_DMA_DEV48_CAC1 = 48,
+        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,          /* TX only */
+        DB8500_DMA_DEV50_HAC1_TX = 50,                  /* TX only */
+        DB8500_DMA_MEMCPY_TX_0 = 51,                    /* TX only */
+        DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
+        DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
+        DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
+        DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
+        /* 56 -> 60 are channels reserved for memcpy only */
+        DB8500_DMA_DEV61_CAC0 = 61,
+        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,          /* TX only */
+        DB8500_DMA_DEV63_HAC0_TX = 63,                  /* TX only */
 };
 
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2dfc72f7cd8a..b7bd8d3a5507 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -14,25 +14,15 @@
 
 #define MUSB_DMA40_RX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
-                .dir = STEDMA40_PERIPH_TO_MEM, \
-                .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dir = DMA_DEV_TO_MEM, \
         }
 
 #define MUSB_DMA40_TX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
-                .dir = STEDMA40_MEM_TO_PERIPH, \
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
+                .dir = DMA_MEM_TO_DEV, \
         }
 
-static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
         = {
         MUSB_DMA40_RX_CH,
         MUSB_DMA40_RX_CH,
@@ -44,7 +34,7 @@ static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
         MUSB_DMA40_RX_CH
 };
 
-static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
+static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS]
         = {
         MUSB_DMA40_TX_CH,
         MUSB_DMA40_TX_CH,
@@ -56,7 +46,7 @@ static struct stedma40_chan_cfg musb_dma_tx_ch[UX500_MUSB_DMA_NUM_TX_CHANNELS]
         MUSB_DMA40_TX_CH,
 };
 
-static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
+static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
         &musb_dma_rx_ch[0],
         &musb_dma_rx_ch[1],
         &musb_dma_rx_ch[2],
@@ -67,7 +57,7 @@ static void *ux500_dma_rx_param_array[UX500_MUSB_DMA_NUM_RX_CHANNELS] = {
         &musb_dma_rx_ch[7]
 };
 
-static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
+static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_RX_TX_CHANNELS] = {
         &musb_dma_tx_ch[0],
         &musb_dma_tx_ch[1],
         &musb_dma_tx_ch[2],
@@ -81,23 +71,11 @@ static void *ux500_dma_tx_param_array[UX500_MUSB_DMA_NUM_TX_CHANNELS] = {
 static struct ux500_musb_board_data musb_board_data = {
         .dma_rx_param_array = ux500_dma_rx_param_array,
         .dma_tx_param_array = ux500_dma_tx_param_array,
-        .num_rx_channels = UX500_MUSB_DMA_NUM_RX_CHANNELS,
-        .num_tx_channels = UX500_MUSB_DMA_NUM_TX_CHANNELS,
         .dma_filter = stedma40_filter,
 };
 
-static u64 ux500_musb_dmamask = DMA_BIT_MASK(32);
-
-static struct musb_hdrc_config musb_hdrc_config = {
-        .multipoint     = true,
-        .dyn_fifo       = true,
-        .num_eps        = 16,
-        .ram_bits       = 16,
-};
-
 static struct musb_hdrc_platform_data musb_platform_data = {
         .mode = MUSB_OTG,
-        .config = &musb_hdrc_config,
         .board_data = &musb_board_data,
 };
 
@@ -118,27 +96,26 @@ struct platform_device ux500_musb_device = {
         .id = 0,
         .dev = {
                 .platform_data = &musb_platform_data,
-                .dma_mask = &ux500_musb_dmamask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
         },
         .num_resources = ARRAY_SIZE(usb_resources),
         .resource = usb_resources,
 };
 
-static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
         u32 idx;
 
-        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
-                musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
+                musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
 
-static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
         u32 idx;
 
-        for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
-                musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+        for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_TX_CHANNELS; idx++)
+                musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 
 void ux500_add_usb(struct device *parent, resource_size_t base, int irq,
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 5907e10c37fd..b8bbabec6310 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
 
+config ARCH_VEXPRESS_DCSCB
+        bool "Dual Cluster System Control Block (DCSCB) support"
+        depends on MCPM
+        select ARM_CCI
+        help
+          Support for the Dual Cluster System Configuration Block (DCSCB).
+          This is needed to provide CPU and cluster power management
+          on RTSM implementing big.LITTLE.
+
 endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 42703e8b4d3b..48ba89a8149f 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
 
 obj-y                                   := v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)       += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)       += dcscb.o      dcscb_setup.o
 obj-$(CONFIG_SMP)                       += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f134cd4a85f1..bde4374ab6d5 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -6,6 +6,8 @@
 
 void vexpress_dt_smp_map_io(void);
 
+bool vexpress_smp_init_ops(void);
+
 extern struct smp_operations    vexpress_smp_ops;
 
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
new file mode 100644
index 000000000000..16d57a8a9d5a
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -0,0 +1,253 @@
+/*
+ * arch/arm/mach-vexpress/dcscb.c - Dual Cluster System Configuration Block
+ *
+ * Created by:  Nicolas Pitre, May 2012
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/of_address.h>
+#include <linux/vexpress.h>
+#include <linux/arm-cci.h>
+
+#include <asm/mcpm.h>
+#include <asm/proc-fns.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+
+
+#define RST_HOLD0       0x0
+#define RST_HOLD1       0x4
+#define SYS_SWRESET     0x8
+#define RST_STAT0       0xc
+#define RST_STAT1       0x10
+#define EAG_CFG_R       0x20
+#define EAG_CFG_W       0x24
+#define KFC_CFG_R       0x28
+#define KFC_CFG_W       0x2c
+#define DCS_CFG_R       0x30
+
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() while its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t dcscb_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static void __iomem *dcscb_base;
+static int dcscb_use_count[4][2];
+static int dcscb_allcpus_mask[2];
+
+static int dcscb_power_up(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int rst_hold, cpumask = (1 << cpu);
+        unsigned int all_mask = dcscb_allcpus_mask[cluster];
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cpu >= 4 || cluster >= 2)
+                return -EINVAL;
+
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&dcscb_lock);
+
+        dcscb_use_count[cpu][cluster]++;
+        if (dcscb_use_count[cpu][cluster] == 1) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                if (rst_hold & (1 << 8)) {
+                        /* remove cluster reset and add individual CPU's reset */
+                        rst_hold &= ~(1 << 8);
+                        rst_hold |= all_mask;
+                }
+                rst_hold &= ~(cpumask | (cpumask << 4));
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+
+        arch_spin_unlock(&dcscb_lock);
+        local_irq_enable();
+
+        return 0;
+}
+
+static void dcscb_power_down(void)
+{
+        unsigned int mpidr, cpu, cluster, rst_hold, cpumask, all_mask;
+        bool last_man = false, skip_wfi = false;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        cpumask = (1 << cpu);
+        all_mask = dcscb_allcpus_mask[cluster];
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+
+        __mcpm_cpu_going_down(cpu, cluster);
+
+        arch_spin_lock(&dcscb_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        dcscb_use_count[cpu][cluster]--;
+        if (dcscb_use_count[cpu][cluster] == 0) {
+                rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4);
+                rst_hold |= cpumask;
+                if (((rst_hold | (rst_hold >> 4)) & all_mask) == all_mask) {
+                        rst_hold |= (1 << 8);
+                        last_man = true;
+                }
+                writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4);
+        } else if (dcscb_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else
+                BUG();
+
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&dcscb_lock);
+
+                /*
+                 * Flush all cache levels for this cluster.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_all();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_all();
+
+                /*
+                 * This is a harmless no-op.  On platforms with a real
+                 * outer cache this might either be needed or not,
+                 * depending on where the outer cache sits.
+                 */
+                outer_flush_all();
+
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+
+                /*
+                 * Disable cluster-level coherency by masking
+                 * incoming snoops and DVM messages:
+                 */
+                cci_disable_port_by_cpu(mpidr);
+
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                arch_spin_unlock(&dcscb_lock);
+
+                /*
+                 * Flush the local CPU cache.
+                 *
+                 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
+                 * a preliminary flush here for those CPUs.  At least, that's
+                 * the theory -- without the extra flush, Linux explodes on
+                 * RTSM (to be investigated).
+                 */
+                flush_cache_louis();
+                set_cr(get_cr() & ~CR_C);
+                flush_cache_louis();
+
+                /* Disable local coherency by clearing the ACTLR "SMP" bit: */
+                set_auxcr(get_auxcr() & ~(1 << 6));
+        }
+
+        __mcpm_cpu_down(cpu, cluster);
+
+        /* Now we are prepared for power-down, do it: */
+        dsb();
+        if (!skip_wfi)
+                wfi();
+
+        /* Not dead at this point?  Let our caller cope. */
+}
+
+static const struct mcpm_platform_ops dcscb_power_ops = {
+        .power_up       = dcscb_power_up,
+        .power_down     = dcscb_power_down,
+};
+
+static void __init dcscb_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= 4 || cluster >= 2);
+        dcscb_use_count[cpu][cluster] = 1;
+}
+
+extern void dcscb_power_up_setup(unsigned int affinity_level);
+
+static int __init dcscb_init(void)
+{
+        struct device_node *node;
+        unsigned int cfg;
+        int ret;
+
+        if (!cci_probed())
+                return -ENODEV;
+
+        node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb");
+        if (!node)
+                return -ENODEV;
+        dcscb_base = of_iomap(node, 0);
+        if (!dcscb_base)
+                return -EADDRNOTAVAIL;
+        cfg = readl_relaxed(dcscb_base + DCS_CFG_R);
+        dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1;
+        dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1;
+        dcscb_usage_count_init();
+
+        ret = mcpm_platform_register(&dcscb_power_ops);
+        if (!ret)
+                ret = mcpm_sync_init(dcscb_power_up_setup);
+        if (ret) {
+                iounmap(dcscb_base);
+                return ret;
+        }
+
+        pr_info("VExpress DCSCB support installed\n");
+
+        /*
+         * Future entries into the kernel can now go
+         * through the cluster entry vectors.
+         */
+        vexpress_flags_set(virt_to_phys(mcpm_entry_point));
+
+        return 0;
+}
+
+early_initcall(dcscb_init);
diff --git a/arch/arm/mach-vexpress/dcscb_setup.S b/arch/arm/mach-vexpress/dcscb_setup.S
new file mode 100644
index 000000000000..4bb7fbe0f621
--- /dev/null
+++ b/arch/arm/mach-vexpress/dcscb_setup.S
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/include/asm/dcscb_setup.S
+ *
+ * Created by:  Dave Martin, 2012-06-22
+ * Copyright:   (C) 2012-2013  Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+
+
+ENTRY(dcscb_power_up_setup)
+
+        cmp     r0, #0                  @ check affinity level
+        beq     2f
+
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ * The ACTLR SMP bit does not need to be set here, because cpu_resume()
+ * already restores that.
+ *
+ * A15/A7 may not require explicit L2 invalidation on reset, dependent
+ * on hardware integration decisions.
+ * For now, this code assumes that L2 is either already invalidated,
+ * or invalidation is not required.
+ */
+
+        b       cci_enable_port_for_self
+
+2:      @ Implementation-specific local CPU setup operations should go here,
+        @ if any.  In this case, there is nothing to do.
+
+        bx      lr
+
+ENDPROC(dcscb_power_up_setup)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index dc1ace55d557..993c9ae5dc5e 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,9 +12,11 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <linux/of_fdt.h>
 #include <linux/vexpress.h>
 
+#include <asm/mcpm.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
 
@@ -203,3 +205,21 @@ struct smp_operations __initdata vexpress_smp_ops = {
         .cpu_die                = vexpress_cpu_die,
 #endif
 };
+
+bool __init vexpress_smp_init_ops(void)
+{
+#ifdef CONFIG_MCPM
+        /*
+         * The best way to detect a multi-cluster configuration at the moment
+         * is to look for the presence of a CCI in the system.
+         * Override the default vexpress_smp_ops if so.
+         */
+        struct device_node *node;
+        node = of_find_compatible_node(NULL, NULL, "arm,cci-400");
+        if (node && of_device_is_available(node)) {
+                mcpm_smp_set_ops();
+                return true;
+        }
+#endif
+        return false;
+}
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 8802030df98d..95a469e23e37 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -9,7 +9,6 @@
 #include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
@@ -456,9 +455,9 @@ static const char * const v2m_dt_match[] __initconst = {
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
         .dt_compat      = v2m_dt_match,
         .smp            = smp_ops(vexpress_smp_ops),
+        .smp_init       = smp_init_ops(vexpress_smp_init_ops),
         .map_io         = v2m_dt_map_io,
         .init_early     = v2m_dt_init_early,
-        .init_irq       = irqchip_init,
         .init_time      = v2m_dt_timer_init,
         .init_machine   = v2m_dt_init,
 MACHINE_END
diff --git a/arch/arm/mach-virt/Kconfig b/arch/arm/mach-virt/Kconfig
index 8958f0d896bc..081d46929436 100644
--- a/arch/arm/mach-virt/Kconfig
+++ b/arch/arm/mach-virt/Kconfig
@@ -2,7 +2,7 @@ config ARCH_VIRT
         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARM_GIC
-        select ARM_ARCH_TIMER
+        select HAVE_ARM_ARCH_TIMER
         select ARM_PSCI
         select HAVE_SMP
         select CPU_V7
diff --git a/arch/arm/mach-virt/Makefile b/arch/arm/mach-virt/Makefile
index 042afc1f8c44..7ddbfa60227f 100644
--- a/arch/arm/mach-virt/Makefile
+++ b/arch/arm/mach-virt/Makefile
@@ -3,4 +3,3 @@
 #
 
 obj-y                                   := virt.o
-obj-$(CONFIG_SMP)                       += platsmp.o
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
deleted file mode 100644
index f4143f5bfa5b..000000000000
--- a/arch/arm/mach-virt/platsmp.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Dummy Virtual Machine - does what it says on the tin.
- *
- * Copyright (C) 2012 ARM Ltd
- * Author: Will Deacon <will.deacon@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/of.h>
-
-#include <asm/psci.h>
-#include <asm/smp_plat.h>
-
-extern void secondary_startup(void);
-
-static void __init virt_smp_init_cpus(void)
-{
-}
-
-static void __init virt_smp_prepare_cpus(unsigned int max_cpus)
-{
-}
-
-static int __cpuinit virt_boot_secondary(unsigned int cpu,
-                                         struct task_struct *idle)
-{
-        if (psci_ops.cpu_on)
-                return psci_ops.cpu_on(cpu_logical_map(cpu),
-                                       __pa(secondary_startup));
-        return -ENODEV;
-}
-
-struct smp_operations __initdata virt_smp_ops = {
-        .smp_init_cpus          = virt_smp_init_cpus,
-        .smp_prepare_cpus       = virt_smp_prepare_cpus,
-        .smp_boot_secondary     = virt_boot_secondary,
-};
diff --git a/arch/arm/mach-virt/virt.c b/arch/arm/mach-virt/virt.c
index 061f283f579e..b184e57d1854 100644
--- a/arch/arm/mach-virt/virt.c
+++ b/arch/arm/mach-virt/virt.c
@@ -18,7 +18,6 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <linux/irqchip.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/smp.h>
@@ -36,11 +35,7 @@ static const char *virt_dt_match[] = {
         NULL
 };
 
-extern struct smp_operations virt_smp_ops;
-
 DT_MACHINE_START(VIRT, "Dummy Virtual Machine")
-        .init_irq       = irqchip_init,
         .init_machine   = virt_init,
-        .smp            = smp_ops(virt_smp_ops),
         .dt_compat      = virt_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c
index f5c33df7a597..f8f2f00856e0 100644
--- a/arch/arm/mach-vt8500/vt8500.c
+++ b/arch/arm/mach-vt8500/vt8500.c
@@ -20,7 +20,6 @@
 
 #include <linux/clocksource.h>
 #include <linux/io.h>
-#include <linux/irqchip.h>
 #include <linux/pm.h>
 
 #include <asm/mach-types.h>
@@ -179,7 +178,6 @@ static const char * const vt8500_dt_compat[] = {
 DT_MACHINE_START(WMT_DT, "VIA/Wondermedia SoC (Device Tree Support)")
         .dt_compat      = vt8500_dt_compat,
         .map_io         = vt8500_map_io,
-        .init_irq       = irqchip_init,
         .init_machine   = vt8500_init,
         .init_time      = clocksource_of_init,
         .restart        = vt8500_restart,
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 5bfe7035b73d..4130e65a0e3f 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -25,7 +25,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/of.h>
-#include <linux/irqchip.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -98,7 +97,6 @@ static void zynq_system_reset(char mode, const char *cmd)
 }
 
 static const char * const zynq_dt_match[] = {
-        "xlnx,zynq-zc702",
         "xlnx,zynq-7000",
         NULL
 };
@@ -106,7 +104,6 @@ static const char * const zynq_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
         .smp            = smp_ops(zynq_smp_ops),
         .map_io         = zynq_map_io,
-        .init_irq       = irqchip_init,
         .init_machine   = zynq_init_machine,
         .init_time      = zynq_timer_init,
         .dt_compat      = zynq_dt_match,
diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c
index 5fc167e07619..023f225493f2 100644
--- a/arch/arm/mach-zynq/platsmp.c
+++ b/arch/arm/mach-zynq/platsmp.c
@@ -53,34 +53,34 @@ int __cpuinit zynq_cpun_start(u32 address, int cpu)
                                                 &zynq_secondary_trampoline;
 
                 zynq_slcr_cpu_stop(cpu);
-
-                if (__pa(PAGE_OFFSET)) {
-                        zero = ioremap(0, trampoline_code_size);
-                        if (!zero) {
-                                pr_warn("BOOTUP jump vectors not accessible\n");
-                                return -1;
+                if (address) {
+                        if (__pa(PAGE_OFFSET)) {
+                                zero = ioremap(0, trampoline_code_size);
+                                if (!zero) {
+                                        pr_warn("BOOTUP jump vectors not accessible\n");
+                                        return -1;
+                                }
+                        } else {
+                                zero = (__force u8 __iomem *)PAGE_OFFSET;
                         }
-                } else {
-                        zero = (__force u8 __iomem *)PAGE_OFFSET;
-                }
-
-                /*
-                 * This is elegant way how to jump to any address
-                 * 0x0: Load address at 0x8 to r0
-                 * 0x4: Jump by mov instruction
-                 * 0x8: Jumping address
-                 */
-                memcpy((__force void *)zero, &zynq_secondary_trampoline,
-                                                trampoline_size);
-                writel(address, zero + trampoline_size);
-
-                flush_cache_all();
-                outer_flush_range(0, trampoline_code_size);
-                smp_wmb();
-
-                if (__pa(PAGE_OFFSET))
-                        iounmap(zero);
 
+                        /*
+                        * This is elegant way how to jump to any address
+                        * 0x0: Load address at 0x8 to r0
+                        * 0x4: Jump by mov instruction
+                        * 0x8: Jumping address
+                        */
+                        memcpy((__force void *)zero, &zynq_secondary_trampoline,
+                                                        trampoline_size);
+                        writel(address, zero + trampoline_size);
+
+                        flush_cache_all();
+                        outer_flush_range(0, trampoline_code_size);
+                        smp_wmb();
+
+                        if (__pa(PAGE_OFFSET))
+                                iounmap(zero);
+                }
                 zynq_slcr_cpu_start(cpu);
 
                 return 0;
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index c70969b9c258..50d008d8f87f 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -117,7 +117,7 @@ int __init zynq_slcr_init(void)
 
         pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
 
-        xilinx_zynq_clocks_init(zynq_slcr_base);
+        zynq_clock_init(zynq_slcr_base);
 
         of_node_put(np);
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 35955b54944c..6cacdc8dd654 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -392,11 +392,21 @@ config CPU_V7
         select CPU_CACHE_V7
         select CPU_CACHE_VIPT
         select CPU_COPY_V6 if MMU
-        select CPU_CP15_MMU
+        select CPU_CP15_MMU if MMU
+        select CPU_CP15_MPU if !MMU
         select CPU_HAS_ASID if MMU
         select CPU_PABRT_V7
         select CPU_TLB_V7 if MMU
 
+# ARMv7M
+config CPU_V7M
+        bool
+        select CPU_32v7M
+        select CPU_ABRT_NOMMU
+        select CPU_CACHE_NOP
+        select CPU_PABRT_LEGACY
+        select CPU_THUMBONLY
+
 config CPU_THUMBONLY
         bool
         # There are no CPUs available with MMU that don't implement an ARM ISA:
@@ -441,6 +451,9 @@ config CPU_32v6K
 config CPU_32v7
         bool
 
+config CPU_32v7M
+        bool
+
 # The abort model
 config CPU_ABRT_NOMMU
         bool
@@ -491,6 +504,9 @@ config CPU_CACHE_V6
 config CPU_CACHE_V7
         bool
 
+config CPU_CACHE_NOP
+        bool
+
 config CPU_CACHE_VIVT
         bool
 
@@ -613,7 +629,11 @@ config ARCH_DMA_ADDR_T_64BIT
 
 config ARM_THUMB
         bool "Support Thumb user binaries" if !CPU_THUMBONLY
-        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON
+        depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
+                CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
+                CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
+                CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
+                CPU_V7 || CPU_FEROCEON || CPU_V7M
         default y
         help
           Say Y if you want to include kernel support for running user space
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 9e51be96f635..ecfe6e53f6e0 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES)		+= proc-syms.o
 
 obj-$(CONFIG_ALIGNMENT_TRAP)    += alignment.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
+obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
 
 obj-$(CONFIG_CPU_ABRT_NOMMU)    += abort-nommu.o
 obj-$(CONFIG_CPU_ABRT_EV4)      += abort-ev4.o
@@ -39,6 +40,7 @@ obj-$(CONFIG_CPU_CACHE_V4WB)	+= cache-v4wb.o
 obj-$(CONFIG_CPU_CACHE_V6)      += cache-v6.o
 obj-$(CONFIG_CPU_CACHE_V7)      += cache-v7.o
 obj-$(CONFIG_CPU_CACHE_FA)      += cache-fa.o
+obj-$(CONFIG_CPU_CACHE_NOP)     += cache-nop.o
 
 AFLAGS_cache-v6.o       :=-Wa,-march=armv6
 AFLAGS_cache-v7.o       :=-Wa,-march=armv7-a
@@ -87,6 +89,7 @@ obj-$(CONFIG_CPU_FEROCEON)	+= proc-feroceon.o
 obj-$(CONFIG_CPU_V6)            += proc-v6.o
 obj-$(CONFIG_CPU_V6K)           += proc-v6.o
 obj-$(CONFIG_CPU_V7)            += proc-v7.o
+obj-$(CONFIG_CPU_V7M)           += proc-v7m.o
 
 AFLAGS_proc-v6.o        :=-Wa,-march=armv6
 AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index c465faca51b0..d70e0aba0c9d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -523,6 +523,147 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
         }
 }
 
+/*
+ * For certain Broadcom SoCs, depending on the address range, different offsets
+ * need to be added to the address before passing it to L2 for
+ * invalidation/clean/flush
+ *
+ * Section Address Range              Offset        EMI
+ *   1     0x00000000 - 0x3FFFFFFF    0x80000000    VC
+ *   2     0x40000000 - 0xBFFFFFFF    0x40000000    SYS
+ *   3     0xC0000000 - 0xFFFFFFFF    0x80000000    VC
+ *
+ * When the start and end addresses have crossed two different sections, we
+ * need to break the L2 operation into two, each within its own section.
+ * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
+ * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
+ * 0xC0000000 - 0xC0001000
+ *
+ * Note 1:
+ * By breaking a single L2 operation into two, we may potentially suffer some
+ * performance hit, but keep in mind the cross section case is very rare
+ *
+ * Note 2:
+ * We do not need to handle the case when the start address is in
+ * Section 1 and the end address is in Section 3, since it is not a valid use
+ * case
+ *
+ * Note 3:
+ * Section 1 in practical terms can no longer be used on rev A2. Because of
+ * that the code does not need to handle section 1 at all.
+ *
+ */
+#define BCM_SYS_EMI_START_ADDR        0x40000000UL
+#define BCM_VC_EMI_SEC3_START_ADDR    0xC0000000UL
+
+#define BCM_SYS_EMI_OFFSET            0x40000000UL
+#define BCM_VC_EMI_OFFSET             0x80000000UL
+
+static inline int bcm_addr_is_sys_emi(unsigned long addr)
+{
+        return (addr >= BCM_SYS_EMI_START_ADDR) &&
+                (addr < BCM_VC_EMI_SEC3_START_ADDR);
+}
+
+static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
+{
+        if (bcm_addr_is_sys_emi(addr))
+                return addr + BCM_SYS_EMI_OFFSET;
+        else
+                return addr + BCM_VC_EMI_OFFSET;
+}
+
+static void bcm_inv_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_inv_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_inv_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
+static void bcm_clean_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        if ((end - start) >= l2x0_size) {
+                l2x0_clean_all();
+                return;
+        }
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_clean_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_clean_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
+static void bcm_flush_range(unsigned long start, unsigned long end)
+{
+        unsigned long new_start, new_end;
+
+        BUG_ON(start < BCM_SYS_EMI_START_ADDR);
+
+        if (unlikely(end <= start))
+                return;
+
+        if ((end - start) >= l2x0_size) {
+                l2x0_flush_all();
+                return;
+        }
+
+        new_start = bcm_l2_phys_addr(start);
+        new_end = bcm_l2_phys_addr(end);
+
+        /* normal case, no cross section between start and end */
+        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
+                l2x0_flush_range(new_start, new_end);
+                return;
+        }
+
+        /* They cross sections, so it can only be a cross from section
+         * 2 to section 3
+         */
+        l2x0_flush_range(new_start,
+                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
+        l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+                new_end);
+}
+
 static void __init l2x0_of_setup(const struct device_node *np,
                                  u32 *aux_val, u32 *aux_mask)
 {
@@ -765,6 +906,21 @@ static const struct l2x0_of_data aurora_no_outer_data = {
         },
 };
 
+static const struct l2x0_of_data bcm_l2x0_data = {
+        .setup = pl310_of_setup,
+        .save  = pl310_save,
+        .outer_cache = {
+                .resume      = pl310_resume,
+                .inv_range   = bcm_inv_range,
+                .clean_range = bcm_clean_range,
+                .flush_range = bcm_flush_range,
+                .sync        = l2x0_cache_sync,
+                .flush_all   = l2x0_flush_all,
+                .inv_all     = l2x0_inv_all,
+                .disable     = l2x0_disable,
+        },
+};
+
 static const struct of_device_id l2x0_ids[] __initconst = {
         { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
         { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
@@ -773,6 +929,8 @@ static const struct of_device_id l2x0_ids[] __initconst = {
           .data = (void *)&aurora_no_outer_data},
         { .compatible = "marvell,aurora-outer-cache",
           .data = (void *)&aurora_with_outer_data},
+        { .compatible = "bcm,bcm11351-a2-pl310-cache",
+          .data = (void *)&bcm_l2x0_data},
         {}
 };
 
diff --git a/arch/arm/mm/cache-nop.S b/arch/arm/mm/cache-nop.S
new file mode 100644
index 000000000000..8e12ddca0031
--- /dev/null
+++ b/arch/arm/mm/cache-nop.S
@@ -0,0 +1,50 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+#include "proc-macros.S"
+
+ENTRY(nop_flush_icache_all)
+        mov     pc, lr
+ENDPROC(nop_flush_icache_all)
+
+        .globl nop_flush_kern_cache_all
+        .equ nop_flush_kern_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_kern_cache_louis
+        .equ nop_flush_kern_cache_louis, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_all
+        .equ nop_flush_user_cache_all, nop_flush_icache_all
+
+        .globl nop_flush_user_cache_range
+        .equ nop_flush_user_cache_range, nop_flush_icache_all
+
+        .globl nop_coherent_kern_range
+        .equ nop_coherent_kern_range, nop_flush_icache_all
+
+ENTRY(nop_coherent_user_range)
+        mov     r0, 0
+        mov     pc, lr
+ENDPROC(nop_coherent_user_range)
+
+        .globl nop_flush_kern_dcache_area
+        .equ nop_flush_kern_dcache_area, nop_flush_icache_all
+
+        .globl nop_dma_flush_range
+        .equ nop_dma_flush_range, nop_flush_icache_all
+
+        .globl nop_dma_map_area
+        .equ nop_dma_map_area, nop_flush_icache_all
+
+        .globl nop_dma_unmap_area
+        .equ nop_dma_unmap_area, nop_flush_icache_all
+
+        __INITDATA
+
+        @ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
+        define_cache_functions nop
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 15451ee4acc8..515b00064da8 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -92,6 +92,14 @@ ENTRY(v7_flush_dcache_louis)
         mrc     p15, 1, r0, c0, c0, 1           @ read clidr, r0 = clidr
         ALT_SMP(ands    r3, r0, #(7 << 21))     @ extract LoUIS from clidr
         ALT_UP(ands     r3, r0, #(7 << 27))     @ extract LoUU from clidr
+#ifdef CONFIG_ARM_ERRATA_643719
+        ALT_SMP(mrceq   p15, 0, r2, c0, c0, 0)  @ read main ID register
+        ALT_UP(moveq    pc, lr)                 @ LoUU is zero, so nothing to do
+        ldreq   r1, =0x410fc090                 @ ID of ARM Cortex A9 r0p?
+        biceq   r2, r2, #0x0000000f             @ clear minor revision number
+        teqeq   r2, r1                          @ test for errata affected core and if so...
+        orreqs  r3, #(1 << 21)                  @   fix LoUIS value (and set flags state to 'ne')
+#endif
         ALT_SMP(mov     r3, r3, lsr #20)        @ r3 = LoUIS * 2
         ALT_UP(mov      r3, r3, lsr #26)        @ r3 = LoUU * 2
         moveq   pc, lr                          @ return if level == 0
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 2ac37372ef52..b55b1015724b 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
+#include <asm/proc-fns.h>
 
 /*
  * On ARMv6, we have the following structure in the Context ID:
@@ -39,33 +40,51 @@
  * non 64-bit operations.
  */
 #define ASID_FIRST_VERSION      (1ULL << ASID_BITS)
-#define NUM_USER_ASIDS          (ASID_FIRST_VERSION - 1)
-
-#define ASID_TO_IDX(asid)       ((asid & ~ASID_MASK) - 1)
-#define IDX_TO_ASID(idx)        ((idx + 1) & ~ASID_MASK)
+#define NUM_USER_ASIDS          ASID_FIRST_VERSION
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
 static atomic64_t asid_generation = ATOMIC64_INIT(ASID_FIRST_VERSION);
 static DECLARE_BITMAP(asid_map, NUM_USER_ASIDS);
 
-DEFINE_PER_CPU(atomic64_t, active_asids);
+static DEFINE_PER_CPU(atomic64_t, active_asids);
 static DEFINE_PER_CPU(u64, reserved_asids);
 static cpumask_t tlb_flush_pending;
 
+#ifdef CONFIG_ARM_ERRATA_798181
+void a15_erratum_get_cpumask(int this_cpu, struct mm_struct *mm,
+                             cpumask_t *mask)
+{
+        int cpu;
+        unsigned long flags;
+        u64 context_id, asid;
+
+        raw_spin_lock_irqsave(&cpu_asid_lock, flags);
+        context_id = mm->context.id.counter;
+        for_each_online_cpu(cpu) {
+                if (cpu == this_cpu)
+                        continue;
+                /*
+                 * We only need to send an IPI if the other CPUs are
+                 * running the same ASID as the one being invalidated.
+                 */
+                asid = per_cpu(active_asids, cpu).counter;
+                if (asid == 0)
+                        asid = per_cpu(reserved_asids, cpu);
+                if (context_id == asid)
+                        cpumask_set_cpu(cpu, mask);
+        }
+        raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
+}
+#endif
+
 #ifdef CONFIG_ARM_LPAE
 static void cpu_set_reserved_ttbr0(void)
 {
-        unsigned long ttbl = __pa(swapper_pg_dir);
-        unsigned long ttbh = 0;
-
         /*
          * Set TTBR0 to swapper_pg_dir which contains only global entries. The
          * ASID is set to 0.
          */
-        asm volatile(
-        "       mcrr    p15, 0, %0, %1, c2              @ set TTBR0\n"
-        :
-        : "r" (ttbl), "r" (ttbh));
+        cpu_set_ttbr(0, __pa(swapper_pg_dir));
         isb();
 }
 #else
@@ -128,7 +147,16 @@ static void flush_context(unsigned int cpu)
                         asid = 0;
                 } else {
                         asid = atomic64_xchg(&per_cpu(active_asids, i), 0);
-                        __set_bit(ASID_TO_IDX(asid), asid_map);
+                        /*
+                         * If this CPU has already been through a
+                         * rollover, but hasn't run another task in
+                         * the meantime, we must preserve its reserved
+                         * ASID, as this is the only trace we have of
+                         * the process it is still running.
+                         */
+                        if (asid == 0)
+                                asid = per_cpu(reserved_asids, i);
+                        __set_bit(asid & ~ASID_MASK, asid_map);
                 }
                 per_cpu(reserved_asids, i) = asid;
         }
@@ -167,17 +195,19 @@ static u64 new_context(struct mm_struct *mm, unsigned int cpu)
                 /*
                  * Allocate a free ASID. If we can't find one, take a
                  * note of the currently active ASIDs and mark the TLBs
-                 * as requiring flushes.
+                 * as requiring flushes. We always count from ASID #1,
+                 * as we reserve ASID #0 to switch via TTBR0 and indicate
+                 * rollover events.
                  */
-                asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                 if (asid == NUM_USER_ASIDS) {
                         generation = atomic64_add_return(ASID_FIRST_VERSION,
                                                          &asid_generation);
                         flush_context(cpu);
-                        asid = find_first_zero_bit(asid_map, NUM_USER_ASIDS);
+                        asid = find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1);
                 }
                 __set_bit(asid, asid_map);
-                asid = generation | IDX_TO_ASID(asid);
+                asid |= generation;
                 cpumask_clear(mm_cpumask(mm));
         }
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index ef3e0f3aac96..7ec02961dfa0 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -250,7 +250,7 @@ static void __dma_free_buffer(struct page *page, size_t size)
 
 #ifdef CONFIG_MMU
 #ifdef CONFIG_HUGETLB_PAGE
-#error ARM Coherent DMA allocator does not (yet) support huge TLB
+#warning ARM Coherent DMA allocator does not (yet) support huge TLB
 #endif
 
 static void *__alloc_from_contiguous(struct device *dev, size_t size,
@@ -880,10 +880,24 @@ static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
         dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
 
         /*
-         * Mark the D-cache clean for this page to avoid extra flushing.
+         * Mark the D-cache clean for these pages to avoid extra flushing.
          */
-        if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
-                set_bit(PG_dcache_clean, &page->flags);
+        if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
+                unsigned long pfn;
+                size_t left = size;
+
+                pfn = page_to_pfn(page) + off / PAGE_SIZE;
+                off %= PAGE_SIZE;
+                if (off) {
+                        pfn++;
+                        left -= PAGE_SIZE - off;
+                }
+                while (left >= PAGE_SIZE) {
+                        page = pfn_to_page(pfn++);
+                        set_bit(PG_dcache_clean, &page->flags);
+                        left -= PAGE_SIZE;
+                }
+        }
 }
 
 /**
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 5dbf13f954f6..c97f7940cb95 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -491,12 +491,14 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
  * Some section permission faults need to be handled gracefully.
  * They can happen due to a __{get,put}_user during an oops.
  */
+#ifndef CONFIG_ARM_LPAE
 static int
 do_sect_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
 {
         do_bad_area(addr, fsr, regs);
         return 0;
 }
+#endif /* CONFIG_ARM_LPAE */
 
 /*
  * This abort handler always returns "fault".
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 0d473cce501c..6d5ba9afb16a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/highmem.h>
 #include <asm/smp_plat.h>
 #include <asm/tlbflush.h>
+#include <linux/hugetlb.h>
 
 #include "mm.h"
 
@@ -168,19 +169,23 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
          * coherent with the kernels mapping.
          */
         if (!PageHighMem(page)) {
-                __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+                size_t page_size = PAGE_SIZE << compound_order(page);
+                __cpuc_flush_dcache_area(page_address(page), page_size);
         } else {
-                void *addr;
-
+                unsigned long i;
                 if (cache_is_vipt_nonaliasing()) {
-                        addr = kmap_atomic(page);
-                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                        kunmap_atomic(addr);
-                } else {
-                        addr = kmap_high_get(page);
-                        if (addr) {
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
+                                void *addr = kmap_atomic(page);
                                 __cpuc_flush_dcache_area(addr, PAGE_SIZE);
-                                kunmap_high(page);
+                                kunmap_atomic(addr);
+                        }
+                } else {
+                        for (i = 0; i < (1 << compound_order(page)); i++) {
+                                void *addr = kmap_high_get(page);
+                                if (addr) {
+                                        __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                                        kunmap_high(page);
+                                }
                         }
                 }
         }
@@ -287,7 +292,7 @@ void flush_dcache_page(struct page *page)
         mapping = page_mapping(page);
 
         if (!cache_ops_need_broadcast() &&
-            mapping && !mapping_mapped(mapping))
+            mapping && !page_mapped(page))
                 clear_bit(PG_dcache_clean, &page->flags);
         else {
                 __flush_dcache_page(mapping, page);
@@ -301,6 +306,39 @@ void flush_dcache_page(struct page *page)
 EXPORT_SYMBOL(flush_dcache_page);
 
 /*
+ * Ensure cache coherency for the kernel mapping of this page. We can
+ * assume that the page is pinned via kmap.
+ *
+ * If the page only exists in the page cache and there are no user
+ * space mappings, this is a no-op since the page was already marked
+ * dirty at creation.  Otherwise, we need to flush the dirty kernel
+ * cache lines directly.
+ */
+void flush_kernel_dcache_page(struct page *page)
+{
+        if (cache_is_vivt() || cache_is_vipt_aliasing()) {
+                struct address_space *mapping;
+
+                mapping = page_mapping(page);
+
+                if (!mapping || mapping_mapped(mapping)) {
+                        void *addr;
+
+                        addr = page_address(page);
+                        /*
+                         * kmap_atomic() doesn't set the page virtual
+                         * address for highmem pages, and
+                         * kunmap_atomic() takes care of cache
+                         * flushing already.
+                         */
+                        if (!IS_ENABLED(CONFIG_HIGHMEM) || addr)
+                                __cpuc_flush_dcache_area(addr, PAGE_SIZE);
+                }
+        }
+}
+EXPORT_SYMBOL(flush_kernel_dcache_page);
+
+/*
  * Flush an anonymous page so that users of get_user_pages()
  * can safely access the data.  The expected sequence is:
  *
diff --git a/arch/arm/mm/fsr-3level.c b/arch/arm/mm/fsr-3level.c
index 05a4e9431836..ab4409a2307e 100644
--- a/arch/arm/mm/fsr-3level.c
+++ b/arch/arm/mm/fsr-3level.c
@@ -9,11 +9,11 @@ static struct fsr_info fsr_info[] = {
         { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "level 3 translation fault"     },
         { do_bad,               SIGBUS,  0,             "reserved access flag fault"    },
         { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 access flag fault"     },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 access flag fault"     },
         { do_bad,               SIGBUS,  0,             "reserved permission fault"     },
         { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 permission fault"      },
-        { do_sect_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 permission fault"      },
         { do_bad,               SIGBUS,  0,             "synchronous external abort"    },
         { do_bad,               SIGBUS,  0,             "asynchronous external abort"   },
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
new file mode 100644
index 000000000000..3d1e4a205b0b
--- /dev/null
+++ b/arch/arm/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
+/*
+ * arch/arm/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h and Bill Carson's patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+/*
+ * On ARM, huge pages are backed by pmd's rather than pte's, so we do a lot
+ * of type casting from pmd_t * to pte_t *.
+ */
+
+pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        if (pgd_present(*pgd)) {
+                pud = pud_offset(pgd, addr);
+                if (pud_present(*pud))
+                        pmd = pmd_offset(pud, addr);
+        }
+
+        return (pte_t *)pmd;
+}
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+                              int write)
+{
+        return ERR_PTR(-EINVAL);
+}
+
+int pud_huge(pud_t pud)
+{
+        return 0;
+}
+
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+        return 0;
+}
+
+pte_t *huge_pte_alloc(struct mm_struct *mm,
+                        unsigned long addr, unsigned long sz)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pte_t *pte = NULL;
+
+        pgd = pgd_offset(mm, addr);
+        pud = pud_alloc(mm, pgd, addr);
+        if (pud)
+                pte = (pte_t *)pmd_alloc(mm, pud, addr);
+
+        return pte;
+}
+
+struct page *
+follow_huge_pmd(struct mm_struct *mm, unsigned long address,
+                pmd_t *pmd, int write)
+{
+        struct page *page;
+
+        page = pte_page(*(pte_t *)pmd);
+        if (page)
+                page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
+        return page;
+}
+
+int pmd_huge(pmd_t pmd)
+{
+        return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 9a5cdc01fcdf..6833cbead6cc 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -36,12 +36,13 @@
 
 #include "mm.h"
 
-static unsigned long phys_initrd_start __initdata = 0;
+static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
 static int __init early_initrd(char *p)
 {
-        unsigned long start, size;
+        phys_addr_t start;
+        unsigned long size;
         char *endp;
 
         start = memparse(p, &endp);
@@ -350,14 +351,14 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #ifdef CONFIG_BLK_DEV_INITRD
         if (phys_initrd_size &&
             !memblock_is_region_memory(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx is not a memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                pr_err("INITRD: 0x%08llx+0x%08lx is not a memory region - disabling initrd\n",
+                       (u64)phys_initrd_start, phys_initrd_size);
                 phys_initrd_start = phys_initrd_size = 0;
         }
         if (phys_initrd_size &&
             memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
-                pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
-                       phys_initrd_start, phys_initrd_size);
+                pr_err("INITRD: 0x%08llx+0x%08lx overlaps in-use memory region - disabling initrd\n",
+                       (u64)phys_initrd_start, phys_initrd_size);
                 phys_initrd_start = phys_initrd_size = 0;
         }
         if (phys_initrd_size) {
@@ -442,7 +443,7 @@ static inline void
 free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
         struct page *start_pg, *end_pg;
-        unsigned long pg, pgend;
+        phys_addr_t pg, pgend;
 
         /*
          * Convert start_pfn/end_pfn to a struct page pointer.
@@ -454,8 +455,8 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
          * Convert to physical addresses, and
          * round start upwards and end downwards.
          */
-        pg = (unsigned long)PAGE_ALIGN(__pa(start_pg));
-        pgend = (unsigned long)__pa(end_pg) & PAGE_MASK;
+        pg = PAGE_ALIGN(__pa(start_pg));
+        pgend = __pa(end_pg) & PAGE_MASK;
 
         /*
          * If there are free pages between these,
@@ -582,9 +583,6 @@ static void __init free_highpages(void)
  */
 void __init mem_init(void)
 {
-        unsigned long reserved_pages, free_pages;
-        struct memblock_region *reg;
-        int i;
 #ifdef CONFIG_HAVE_TCM
         /* These pointers are filled in on TCM detection */
         extern u32 dtcm_end;
@@ -595,57 +593,16 @@ void __init mem_init(void)
 
         /* this will put all unused low memory onto the freelists */
         free_unused_memmap(&meminfo);
-
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
 
 #ifdef CONFIG_SA1111
         /* now that our DMA memory is actually so designated, we can free it */
-        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, 0, NULL);
+        free_reserved_area(__va(PHYS_PFN_OFFSET), swapper_pg_dir, -1, NULL);
 #endif
 
         free_highpages();
 
-        reserved_pages = free_pages = 0;
-
-        for_each_bank(i, &meminfo) {
-                struct membank *bank = &meminfo.bank[i];
-                unsigned int pfn1, pfn2;
-                struct page *page, *end;
-
-                pfn1 = bank_pfn_start(bank);
-                pfn2 = bank_pfn_end(bank);
-
-                page = pfn_to_page(pfn1);
-                end  = pfn_to_page(pfn2 - 1) + 1;
-
-                do {
-                        if (PageReserved(page))
-                                reserved_pages++;
-                        else if (!page_count(page))
-                                free_pages++;
-                        page++;
-                } while (page < end);
-        }
-
-        /*
-         * Since our memory may not be contiguous, calculate the
-         * real number of pages we have in this system
-         */
-        printk(KERN_INFO "Memory:");
-        num_physpages = 0;
-        for_each_memblock(memory, reg) {
-                unsigned long pages = memblock_region_memory_end_pfn(reg) -
-                        memblock_region_memory_base_pfn(reg);
-                num_physpages += pages;
-                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-        }
-        printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                free_pages << (PAGE_SHIFT-10),
-                reserved_pages << (PAGE_SHIFT-10),
-                totalhigh_pages << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -711,7 +668,7 @@ void __init mem_init(void)
         BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE      > PAGE_OFFSET);
 #endif
 
-        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+        if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
                 extern int sysctl_overcommit_memory;
                 /*
                  * On a machine this small we won't get
@@ -728,12 +685,12 @@ void free_initmem(void)
         extern char __tcm_start, __tcm_end;
 
         poison_init_mem(&__tcm_start, &__tcm_end - &__tcm_start);
-        free_reserved_area(&__tcm_start, &__tcm_end, 0, "TCM link");
+        free_reserved_area(&__tcm_start, &__tcm_end, -1, "TCM link");
 #endif
 
         poison_init_mem(__init_begin, __init_end - __init_begin);
         if (!machine_is_integrator() && !machine_is_cintegrator())
-                free_initmem_default(0);
+                free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -744,7 +701,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd) {
                 poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                free_reserved_area(start, end, 0, "initrd");
+                free_reserved_area((void *)start, (void *)end, -1, "initrd");
         }
 }
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 04d9006eab1f..f123d6eb074b 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -331,10 +331,10 @@ void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
         return (void __iomem *) (offset + addr);
 }
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
         unsigned int mtype, void *caller)
 {
-        unsigned long last_addr;
+        phys_addr_t last_addr;
         unsigned long offset = phys_addr & ~PAGE_MASK;
         unsigned long pfn = __phys_to_pfn(phys_addr);
 
@@ -367,12 +367,12 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t,
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
                                       unsigned int, void *) =
         __arm_ioremap_caller;
 
 void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__arm_ioremap(phys_addr_t phys_addr, size_t size, unsigned int mtype)
 {
         return arch_ioremap_caller(phys_addr, size, mtype,
                 __builtin_return_address(0));
@@ -387,7 +387,7 @@ EXPORT_SYMBOL(__arm_ioremap);
  * CONFIG_GENERIC_ALLOCATOR for allocating external memory.
  */
 void __iomem *
-__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached)
+__arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached)
 {
         unsigned int mtype;
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e0d8565671a6..d7229d28c7f8 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -616,10 +616,12 @@ static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
         } while (pte++, addr += PAGE_SIZE, addr != end);
 }
 
-static void __init map_init_section(pmd_t *pmd, unsigned long addr,
+static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
                         unsigned long end, phys_addr_t phys,
                         const struct mem_type *type)
 {
+        pmd_t *p = pmd;
+
 #ifndef CONFIG_ARM_LPAE
         /*
          * In classic MMU format, puds and pmds are folded in to
@@ -638,7 +640,7 @@ static void __init map_init_section(pmd_t *pmd, unsigned long addr,
                 phys += SECTION_SIZE;
         } while (pmd++, addr += SECTION_SIZE, addr != end);
 
-        flush_pmd_entry(pmd);
+        flush_pmd_entry(p);
 }
 
 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
@@ -661,7 +663,7 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
                  */
                 if (type->prot_sect &&
                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
-                        map_init_section(pmd, addr, next, phys, type);
+                        __map_init_section(pmd, addr, next, phys, type);
                 } else {
                         alloc_init_pte(pmd, addr, next,
                                                 __phys_to_pfn(phys), type);
@@ -673,7 +675,8 @@ static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 }
 
 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
-        unsigned long end, unsigned long phys, const struct mem_type *type)
+                                  unsigned long end, phys_addr_t phys,
+                                  const struct mem_type *type)
 {
         pud_t *pud = pud_offset(pgd, addr);
         unsigned long next;
@@ -987,27 +990,28 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
+        phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
 
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
+                phys_addr_t size_limit;
+
                 *bank = meminfo.bank[i];
+                size_limit = bank->size;
 
-                if (bank->start > ULONG_MAX)
-                        highmem = 1;
-
-#ifdef CONFIG_HIGHMEM
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET)
+                if (bank->start >= vmalloc_limit)
                         highmem = 1;
+                else
+                        size_limit = vmalloc_limit - bank->start;
 
                 bank->highmem = highmem;
 
+#ifdef CONFIG_HIGHMEM
                 /*
                  * Split those memory banks which are partially overlapping
                  * the vmalloc area greatly simplifying things later.
                  */
-                if (!highmem && __va(bank->start) < vmalloc_min &&
-                    bank->size > vmalloc_min - __va(bank->start)) {
+                if (!highmem && bank->size > size_limit) {
                         if (meminfo.nr_banks >= NR_BANKS) {
                                 printk(KERN_CRIT "NR_BANKS too low, "
                                                  "ignoring high memory\n");
@@ -1016,16 +1020,14 @@ void __init sanity_check_meminfo(void)
                                         (meminfo.nr_banks - i) * sizeof(*bank));
                                 meminfo.nr_banks++;
                                 i++;
-                                bank[1].size -= vmalloc_min - __va(bank->start);
-                                bank[1].start = __pa(vmalloc_min - 1) + 1;
+                                bank[1].size -= size_limit;
+                                bank[1].start = vmalloc_limit;
                                 bank[1].highmem = highmem = 1;
                                 j++;
                         }
-                        bank->size = vmalloc_min - __va(bank->start);
+                        bank->size = size_limit;
                 }
 #else
-                bank->highmem = highmem;
-
                 /*
                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
                  */
@@ -1038,31 +1040,16 @@ void __init sanity_check_meminfo(void)
                 }
 
                 /*
-                 * Check whether this memory bank would entirely overlap
-                 * the vmalloc area.
-                 */
-                if (__va(bank->start) >= vmalloc_min ||
-                    __va(bank->start) < (void *)PAGE_OFFSET) {
-                        printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-                               "(vmalloc region overlap).\n",
-                               (unsigned long long)bank->start,
-                               (unsigned long long)bank->start + bank->size - 1);
-                        continue;
-                }
-
-                /*
                  * Check whether this memory bank would partially overlap
                  * the vmalloc area.
                  */
-                if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
-                    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
-                        unsigned long newsize = vmalloc_min - __va(bank->start);
+                if (bank->size > size_limit) {
                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
                                "to -%.8llx (vmalloc region overlap).\n",
                                (unsigned long long)bank->start,
                                (unsigned long long)bank->start + bank->size - 1,
-                               (unsigned long long)bank->start + newsize - 1);
-                        bank->size = newsize;
+                               (unsigned long long)bank->start + size_limit - 1);
+                        bank->size = size_limit;
                 }
 #endif
                 if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit)
@@ -1232,6 +1219,8 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
          */
         if (mdesc->map_io)
                 mdesc->map_io();
+        else
+                debug_ll_io_init();
         fill_pmd_gaps();
 
         /* Reserve fixed i/o space in VMALLOC region */
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index d51225f90ae2..1fa50100ab6a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -8,6 +8,7 @@
 #include <linux/pagemap.h>
 #include <linux/io.h>
 #include <linux/memblock.h>
+#include <linux/kernel.h>
 
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
@@ -15,22 +16,282 @@
 #include <asm/setup.h>
 #include <asm/traps.h>
 #include <asm/mach/arch.h>
+#include <asm/cputype.h>
+#include <asm/mpu.h>
 
 #include "mm.h"
 
+#ifdef CONFIG_ARM_MPU
+struct mpu_rgn_info mpu_rgn_info;
+
+/* Region number */
+static void rgnr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c2, 0" : : "r" (v));
+}
+
+/* Data-side / unified region attributes */
+
+/* Region access control register */
+static void dracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 4" : : "r" (v));
+}
+
+/* Region size register */
+static void drsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 2" : : "r" (v));
+}
+
+/* Region base address register */
+static void drbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 0" : : "r" (v));
+}
+
+static u32 drbar_read(void)
+{
+        u32 v;
+        asm("mrc        p15, 0, %0, c6, c1, 0" : "=r" (v));
+        return v;
+}
+/* Optional instruction-side region attributes */
+
+/* I-side Region access control register */
+static void iracr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 5" : : "r" (v));
+}
+
+/* I-side Region size register */
+static void irsr_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 3" : : "r" (v));
+}
+
+/* I-side Region base address register */
+static void irbar_write(u32 v)
+{
+        asm("mcr        p15, 0, %0, c6, c1, 1" : : "r" (v));
+}
+
+static unsigned long irbar_read(void)
+{
+        unsigned long v;
+        asm("mrc        p15, 0, %0, c6, c1, 1" : "=r" (v));
+        return v;
+}
+
+/* MPU initialisation functions */
+void __init sanity_check_meminfo_mpu(void)
+{
+        int i;
+        struct membank *bank = meminfo.bank;
+        phys_addr_t phys_offset = PHYS_OFFSET;
+        phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
+
+        /* Initially only use memory continuous from PHYS_OFFSET */
+        if (bank_phys_start(&bank[0]) != phys_offset)
+                panic("First memory bank must be contiguous from PHYS_OFFSET");
+
+        /* Banks have already been sorted by start address */
+        for (i = 1; i < meminfo.nr_banks; i++) {
+                if (bank[i].start <= bank_phys_end(&bank[0]) &&
+                    bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
+                        bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
+                } else {
+                        pr_notice("Ignoring RAM after 0x%.8lx. "
+                        "First non-contiguous (ignored) bank start: 0x%.8lx\n",
+                                (unsigned long)bank_phys_end(&bank[0]),
+                                (unsigned long)bank_phys_start(&bank[i]));
+                        break;
+                }
+        }
+        /* All contiguous banks are now merged in to the first bank */
+        meminfo.nr_banks = 1;
+        specified_mem_size = bank[0].size;
+
+        /*
+         * MPU has curious alignment requirements: Size must be power of 2, and
+         * region start must be aligned to the region size
+         */
+        if (phys_offset != 0)
+                pr_info("PHYS_OFFSET != 0 => MPU Region size constrained by alignment requirements\n");
+
+        /*
+         * Maximum aligned region might overflow phys_addr_t if phys_offset is
+         * 0. Hence we keep everything below 4G until we take the smaller of
+         * the aligned_region_size and rounded_mem_size, one of which is
+         * guaranteed to be smaller than the maximum physical address.
+         */
+        aligned_region_size = (phys_offset - 1) ^ (phys_offset);
+        /* Find the max power-of-two sized region that fits inside our bank */
+        rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
+
+        /* The actual region size is the smaller of the two */
+        aligned_region_size = aligned_region_size < rounded_mem_size
+                                ? aligned_region_size + 1
+                                : rounded_mem_size + 1;
+
+        if (aligned_region_size != specified_mem_size)
+                pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
+                                (unsigned long)specified_mem_size,
+                                (unsigned long)aligned_region_size);
+
+        meminfo.bank[0].size = aligned_region_size;
+        pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
+                (unsigned long)phys_offset,
+                (unsigned long)aligned_region_size,
+                (unsigned long)bank_phys_end(&bank[0]));
+
+}
+
+static int mpu_present(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7);
+}
+
+static int mpu_max_regions(void)
+{
+        /*
+         * We don't support a different number of I/D side regions so if we
+         * have separate instruction and data memory maps then return
+         * whichever side has a smaller number of supported regions.
+         */
+        u32 dregions, iregions, mpuir;
+        mpuir = read_cpuid(CPUID_MPUIR);
+
+        dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION;
+
+        /* Check for separate d-side and i-side memory maps */
+        if (mpuir & MPUIR_nU)
+                iregions = (mpuir & MPUIR_IREGION_SZMASK) >> MPUIR_IREGION;
+
+        /* Use the smallest of the two maxima */
+        return min(dregions, iregions);
+}
+
+static int mpu_iside_independent(void)
+{
+        /* MPUIR.nU specifies whether there is *not* a unified memory map */
+        return read_cpuid(CPUID_MPUIR) & MPUIR_nU;
+}
+
+static int mpu_min_region_order(void)
+{
+        u32 drbar_result, irbar_result;
+        /* We've kept a region free for this probing */
+        rgnr_write(MPU_PROBE_REGION);
+        isb();
+        /*
+         * As per ARM ARM, write 0xFFFFFFFC to DRBAR to find the minimum
+         * region order
+        */
+        drbar_write(0xFFFFFFFC);
+        drbar_result = irbar_result = drbar_read();
+        drbar_write(0x0);
+        /* If the MPU is non-unified, we use the larger of the two minima*/
+        if (mpu_iside_independent()) {
+                irbar_write(0xFFFFFFFC);
+                irbar_result = irbar_read();
+                irbar_write(0x0);
+        }
+        isb(); /* Ensure that MPU region operations have completed */
+        /* Return whichever result is larger */
+        return __ffs(max(drbar_result, irbar_result));
+}
+
+static int mpu_setup_region(unsigned int number, phys_addr_t start,
+                        unsigned int size_order, unsigned int properties)
+{
+        u32 size_data;
+
+        /* We kept a region free for probing resolution of MPU regions*/
+        if (number > mpu_max_regions() || number == MPU_PROBE_REGION)
+                return -ENOENT;
+
+        if (size_order > 32)
+                return -ENOMEM;
+
+        if (size_order < mpu_min_region_order())
+                return -ENOMEM;
+
+        /* Writing N to bits 5:1 (RSR_SZ)  specifies region size 2^N+1 */
+        size_data = ((size_order - 1) << MPU_RSR_SZ) | 1 << MPU_RSR_EN;
+
+        dsb(); /* Ensure all previous data accesses occur with old mappings */
+        rgnr_write(number);
+        isb();
+        drbar_write(start);
+        dracr_write(properties);
+        isb(); /* Propagate properties before enabling region */
+        drsr_write(size_data);
+
+        /* Check for independent I-side registers */
+        if (mpu_iside_independent()) {
+                irbar_write(start);
+                iracr_write(properties);
+                isb();
+                irsr_write(size_data);
+        }
+        isb();
+
+        /* Store region info (we treat i/d side the same, so only store d) */
+        mpu_rgn_info.rgns[number].dracr = properties;
+        mpu_rgn_info.rgns[number].drbar = start;
+        mpu_rgn_info.rgns[number].drsr = size_data;
+        return 0;
+}
+
+/*
+* Set up default MPU regions, doing nothing if there is no MPU
+*/
+void __init mpu_setup(void)
+{
+        int region_err;
+        if (!mpu_present())
+                return;
+
+        region_err = mpu_setup_region(MPU_RAM_REGION, PHYS_OFFSET,
+                                        ilog2(meminfo.bank[0].size),
+                                        MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL);
+        if (region_err) {
+                panic("MPU region initialization failure! %d", region_err);
+        } else {
+                pr_info("Using ARMv7 PMSA Compliant MPU. "
+                         "Region independence: %s, Max regions: %d\n",
+                        mpu_iside_independent() ? "Yes" : "No",
+                        mpu_max_regions());
+        }
+}
+#else
+static void sanity_check_meminfo_mpu(void) {}
+static void __init mpu_setup(void) {}
+#endif /* CONFIG_ARM_MPU */
+
 void __init arm_mm_memblock_reserve(void)
 {
+#ifndef CONFIG_CPU_V7M
         /*
          * Register the exception vector page.
          * some architectures which the DRAM is the exception vector to trap,
          * alloc_page breaks with error, although it is not NULL, but "0."
          */
         memblock_reserve(CONFIG_VECTORS_BASE, PAGE_SIZE);
+#else /* ifndef CONFIG_CPU_V7M */
+        /*
+         * There is no dedicated vector page on V7-M. So nothing needs to be
+         * reserved here.
+         */
+#endif
 }
 
 void __init sanity_check_meminfo(void)
 {
-        phys_addr_t end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+        phys_addr_t end;
+        sanity_check_meminfo_mpu();
+        end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
         high_memory = __va(end - 1) + 1;
 }
 
@@ -41,6 +302,7 @@ void __init sanity_check_meminfo(void)
 void __init paging_init(struct machine_desc *mdesc)
 {
         early_trap_init((void *)CONFIG_VECTORS_BASE);
+        mpu_setup();
         bootmem_init();
 }
 
@@ -57,6 +319,12 @@ void flush_dcache_page(struct page *page)
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
+void flush_kernel_dcache_page(struct page *page)
+{
+        __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
+}
+EXPORT_SYMBOL(flush_kernel_dcache_page);
+
 void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
                        unsigned long uaddr, void *dst, const void *src,
                        unsigned long len)
@@ -81,16 +349,16 @@ void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
         return __arm_ioremap_pfn(pfn, offset, size, mtype);
 }
 
-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size,
                             unsigned int mtype)
 {
         return (void __iomem *)phys_addr;
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *);
+void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *);
 
-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size,
                                    unsigned int mtype, void *caller)
 {
         return __arm_ioremap(phys_addr, size, mtype);
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index d217e9795d74..aaeb6c127c7a 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -81,7 +81,6 @@ ENDPROC(cpu_fa526_reset)
  */
         .align  4
 ENTRY(cpu_fa526_do_idle)
-        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
         mov     pc, lr
 
 
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index f9a0aa725ea9..e3c48a3fe063 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -333,3 +333,8 @@ ENTRY(\name\()_tlb_fns)
         .endif
         .size   \name\()_tlb_fns, . - \name\()_tlb_fns
 .endm
+
+.macro globl_equ x, y
+        .globl  \x
+        .equ    \x, \y
+.endm
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 919405e20b80..2d1ef87328a1 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -140,8 +140,10 @@ ENTRY(cpu_v6_set_pte_ext)
 ENTRY(cpu_v6_do_suspend)
         stmfd   sp!, {r4 - r9, lr}
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
         mrc     p15, 0, r5, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+#endif
         mrc     p15, 0, r7, c1, c0, 1   @ auxiliary control register
         mrc     p15, 0, r8, c1, c0, 2   @ co-processor access control
         mrc     p15, 0, r9, c1, c0, 0   @ control register
@@ -158,14 +160,16 @@ ENTRY(cpu_v6_do_resume)
         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
         ldmia   r0, {r4 - r9}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
+#ifdef CONFIG_MMU
         mcr     p15, 0, r5, c3, c0, 0   @ Domain ID
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
         mcr     p15, 0, r1, c2, c0, 0   @ Translation table base 0
         mcr     p15, 0, r6, c2, c0, 1   @ Translation table base 1
+        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
+#endif
         mcr     p15, 0, r7, c1, c0, 1   @ auxiliary control register
         mcr     p15, 0, r8, c1, c0, 2   @ co-processor access control
-        mcr     p15, 0, ip, c2, c0, 2   @ TTB control register
         mcr     p15, 0, ip, c7, c5, 4   @ ISB
         mov     r0, r9                  @ control register
         b       cpu_resume_mmu
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 363027e811d6..5ffe1956c6d9 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -39,6 +39,14 @@
 #define TTB_FLAGS_SMP   (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
 #define PMD_FLAGS_SMP   (PMD_SECT_WBWA|PMD_SECT_S)
 
+#ifndef __ARMEB__
+#  define rpgdl r0
+#  define rpgdh r1
+#else
+#  define rpgdl r1
+#  define rpgdh r0
+#endif
+
 /*
  * cpu_v7_switch_mm(pgd_phys, tsk)
  *
@@ -47,10 +55,10 @@
  */
 ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_MMU
-        mmid    r1, r1                          @ get mm->context.id
-        asid    r3, r1
-        mov     r3, r3, lsl #(48 - 32)          @ ASID
-        mcrr    p15, 0, r0, r3, c2              @ set TTB 0
+        mmid    r2, r2
+        asid    r2, r2
+        orr     rpgdh, rpgdh, r2, lsl #(48 - 32)        @ upper 32-bits of pgd
+        mcrr    p15, 0, rpgdl, rpgdh, c2                @ set TTB 0
         isb
 #endif
         mov     pc, lr
@@ -106,7 +114,8 @@ ENDPROC(cpu_v7_set_pte_ext)
          */
         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
         ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
-        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET? (branch below)
+        mov     \tmp, \tmp, lsr #ARCH_PGD_SHIFT
+        cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
         mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
         orr     \tmp, \tmp, #TTB_EAE
         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
@@ -114,27 +123,21 @@ ENDPROC(cpu_v7_set_pte_ext)
         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
         /*
-         * TTBR0/TTBR1 split (PAGE_OFFSET):
-         *   0x40000000: T0SZ = 2, T1SZ = 0 (not used)
-         *   0x80000000: T0SZ = 0, T1SZ = 1
-         *   0xc0000000: T0SZ = 0, T1SZ = 2
-         *
-         * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise
-         * booting secondary CPUs would end up using TTBR1 for the identity
-         * mapping set up in TTBR0.
+         * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
+         * otherwise booting secondary CPUs would end up using TTBR1 for the
+         * identity mapping set up in TTBR0.
          */
-        bhi     9001f                           @ PHYS_OFFSET > PAGE_OFFSET?
-        orr     \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ
-#if defined CONFIG_VMSPLIT_2G
-        /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */
-        add     \ttbr1, \ttbr1, #1 << 4         @ skip two L1 entries
-#elif defined CONFIG_VMSPLIT_3G
-        /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */
-        add     \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd
-#endif
-        /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */
-9001:   mcr     p15, 0, \tmp, c2, c0, 2         @ TTB control register
-        mcrr    p15, 1, \ttbr1, \zero, c2       @ load TTBR1
+        orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
+        mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
+        mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
+        addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
+        mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
+        mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+        mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
         .endm
 
         __CPUINIT
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 2c73a7301ff7..7ef3ad05df39 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -98,9 +98,11 @@ ENTRY(cpu_v7_do_suspend)
         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         stmia   r0!, {r4 - r5}
+#ifdef CONFIG_MMU
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
+#endif
         mrc     p15, 0, r8, c1, c0, 0   @ Control register
         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
@@ -110,13 +112,14 @@ ENDPROC(cpu_v7_do_suspend)
 
 ENTRY(cpu_v7_do_resume)
         mov     ip, #0
-        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
         ldmia   r0!, {r4 - r5}
         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
         ldmia   r0, {r6 - r11}
+#ifdef CONFIG_MMU
+        mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 #ifndef CONFIG_ARM_LPAE
         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
@@ -125,14 +128,15 @@ ENTRY(cpu_v7_do_resume)
         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
-        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
-        teq     r4, r9                  @ Is it already set?
-        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
-        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         ldr     r4, =PRRR               @ PRRR
         ldr     r5, =NMRR               @ NMRR
         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
+#endif  /* CONFIG_MMU */
+        mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
+        teq     r4, r9                  @ Is it already set?
+        mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
+        mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
         isb
         dsb
         mov     r0, r8                  @ control register
@@ -140,6 +144,29 @@ ENTRY(cpu_v7_do_resume)
 ENDPROC(cpu_v7_do_resume)
 #endif
 
+#ifdef CONFIG_CPU_PJ4B
+        globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
+        globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
+        globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
+        globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
+        globl_equ       cpu_pj4b_reset,         cpu_v7_reset
+#ifdef CONFIG_PJ4B_ERRATA_4742
+ENTRY(cpu_pj4b_do_idle)
+        dsb                                     @ WFI may enter a low-power mode
+        wfi
+        dsb                                     @barrier
+        mov     pc, lr
+ENDPROC(cpu_pj4b_do_idle)
+#else
+        globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
+#endif
+        globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
+        globl_equ       cpu_pj4b_do_suspend,    cpu_v7_do_suspend
+        globl_equ       cpu_pj4b_do_resume,     cpu_v7_do_resume
+        globl_equ       cpu_pj4b_suspend_size,  cpu_v7_suspend_size
+
+#endif
+
         __CPUINIT
 
 /*
@@ -155,7 +182,8 @@ ENDPROC(cpu_v7_do_resume)
  */
 __v7_ca5mp_setup:
 __v7_ca9mp_setup:
-        mov     r10, #(1 << 0)                  @ TLB ops broadcasting
+__v7_cr7mp_setup:
+        mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
         b       1f
 __v7_ca7mp_setup:
 __v7_ca15mp_setup:
@@ -350,6 +378,9 @@ __v7_setup_stack:
 
         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+#ifdef CONFIG_CPU_PJ4B
+        define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+#endif
 
         .section ".rodata"
 
@@ -362,7 +393,7 @@ __v7_setup_stack:
         /*
          * Standard v7 proc info content
          */
-.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
+.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -375,7 +406,7 @@ __v7_setup_stack:
         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
         .long   cpu_v7_name
-        .long   v7_processor_functions
+        .long   \proc_fns
         .long   v7wbi_tlb_fns
         .long   v6_user_fns
         .long   v7_cache_fns
@@ -407,12 +438,24 @@ __v7_ca9mp_proc_info:
         /*
          * Marvell PJ4B processor.
          */
+#ifdef CONFIG_CPU_PJ4B
         .type   __v7_pj4b_proc_info, #object
 __v7_pj4b_proc_info:
-        .long   0x562f5840
-        .long   0xfffffff0
-        __v7_proc __v7_pj4b_setup
+        .long   0x560f5800
+        .long   0xff0fff00
+        __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
+#endif
+
+        /*
+         * ARM Ltd. Cortex R7 processor.
+         */
+        .type   __v7_cr7mp_proc_info, #object
+__v7_cr7mp_proc_info:
+        .long   0x410fc170
+        .long   0xff0ffff0
+        __v7_proc __v7_cr7mp_setup
+        .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 
         /*
          * ARM Ltd. Cortex A7 processor.
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
new file mode 100644
index 000000000000..0c93588fcb91
--- /dev/null
+++ b/arch/arm/mm/proc-v7m.S
@@ -0,0 +1,157 @@
+/*
+ *  linux/arch/arm/mm/proc-v7m.S
+ *
+ *  Copyright (C) 2008 ARM Ltd.
+ *  Copyright (C) 2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This is the "shell" of the ARMv7-M processor support.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/v7m.h>
+#include "proc-macros.S"
+
+ENTRY(cpu_v7m_proc_init)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_init)
+
+ENTRY(cpu_v7m_proc_fin)
+        mov     pc, lr
+ENDPROC(cpu_v7m_proc_fin)
+
+/*
+ *      cpu_v7m_reset(loc)
+ *
+ *      Perform a soft reset of the system.  Put the CPU into the
+ *      same state as it would be if it had been reset, and branch
+ *      to what would be the reset vector.
+ *
+ *      - loc   - location to jump to for soft reset
+ */
+        .align  5
+ENTRY(cpu_v7m_reset)
+        mov     pc, r0
+ENDPROC(cpu_v7m_reset)
+
+/*
+ *      cpu_v7m_do_idle()
+ *
+ *      Idle the processor (eg, wait for interrupt).
+ *
+ *      IRQs are already disabled.
+ */
+ENTRY(cpu_v7m_do_idle)
+        wfi
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_idle)
+
+ENTRY(cpu_v7m_dcache_clean_area)
+        mov     pc, lr
+ENDPROC(cpu_v7m_dcache_clean_area)
+
+/*
+ * There is no MMU, so here is nothing to do.
+ */
+ENTRY(cpu_v7m_switch_mm)
+        mov     pc, lr
+ENDPROC(cpu_v7m_switch_mm)
+
+.globl  cpu_v7m_suspend_size
+.equ    cpu_v7m_suspend_size, 0
+
+#ifdef CONFIG_ARM_CPU_SUSPEND
+ENTRY(cpu_v7m_do_suspend)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_suspend)
+
+ENTRY(cpu_v7m_do_resume)
+        mov     pc, lr
+ENDPROC(cpu_v7m_do_resume)
+#endif
+
+        .section ".text.init", #alloc, #execinstr
+
+/*
+ *      __v7m_setup
+ *
+ *      This should be able to cover all ARMv7-M cores.
+ */
+__v7m_setup:
+        @ Configure the vector table base address
+        ldr     r0, =BASEADDR_V7M_SCB
+        ldr     r12, =vector_table
+        str     r12, [r0, V7M_SCB_VTOR]
+
+        @ enable UsageFault, BusFault and MemManage fault.
+        ldr     r5, [r0, #V7M_SCB_SHCSR]
+        orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
+        str     r5, [r0, #V7M_SCB_SHCSR]
+
+        @ Lower the priority of the SVC and PendSV exceptions
+        mov     r5, #0x80000000
+        str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
+        mov     r5, #0x00800000
+        str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
+
+        @ SVC to run the kernel in this mode
+        adr     r1, BSYM(1f)
+        ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
+        str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
+        mov     r6, lr                  @ save LR
+        mov     r7, sp                  @ save SP
+        ldr     sp, =__v7m_setup_stack_top
+        cpsie   i
+        svc     #0
+1:      cpsid   i
+        str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
+        mov     lr, r6                  @ restore LR
+        mov     sp, r7                  @ restore SP
+
+        @ Special-purpose control register
+        mov     r1, #1
+        msr     control, r1             @ Thread mode has unpriviledged access
+
+        @ Configure the System Control Register to ensure 8-byte stack alignment
+        @ Note the STKALIGN bit is either RW or RAO.
+        ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
+        orr     r12, #V7M_SCB_CCR_STKALIGN
+        str     r12, [r0, V7M_SCB_CCR]
+        mov     pc, lr
+ENDPROC(__v7m_setup)
+
+        define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
+
+        .section ".rodata"
+        string cpu_arch_name, "armv7m"
+        string cpu_elf_name "v7m"
+        string cpu_v7m_name "ARMv7-M"
+
+        .section ".proc.info.init", #alloc, #execinstr
+
+        /*
+         * Match any ARMv7-M processor core.
+         */
+        .type   __v7m_proc_info, #object
+__v7m_proc_info:
+        .long   0x000f0000              @ Required ID value
+        .long   0x000f0000              @ Mask for ID
+        .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
+        .long   0                       @ proc_info_list.__cpu_io_mmu_flags
+        b       __v7m_setup             @ proc_info_list.__cpu_flush
+        .long   cpu_arch_name
+        .long   cpu_elf_name
+        .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
+        .long   cpu_v7m_name
+        .long   v7m_processor_functions @ proc_info_list.proc
+        .long   0                       @ proc_info_list.tlb
+        .long   0                       @ proc_info_list.user
+        .long   nop_cache_fns           @ proc_info_list.cache
+        .size   __v7m_proc_info, . - __v7m_proc_info
+
+__v7m_setup_stack:
+        .space  4 * 8                           @ 8 registers
+__v7m_setup_stack_top:
diff --git a/arch/arm/plat-iop/adma.c b/arch/arm/plat-iop/adma.c
index 1ff6a37e893c..a4d1f8de3b5b 100644
--- a/arch/arm/plat-iop/adma.c
+++ b/arch/arm/plat-iop/adma.c
@@ -192,12 +192,10 @@ static int __init iop3xx_adma_cap_init(void)
 
         #ifdef CONFIG_ARCH_IOP32X /* the 32x AAU does not perform zero sum */
         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
         #else
         dma_cap_set(DMA_XOR, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_XOR_VAL, iop3xx_aau_data.cap_mask);
-        dma_cap_set(DMA_MEMSET, iop3xx_aau_data.cap_mask);
         dma_cap_set(DMA_INTERRUPT, iop3xx_aau_data.cap_mask);
         #endif
 
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ce66eb9be481..f82bae2171eb 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -86,22 +86,6 @@ config OMAP_MUX_WARNINGS
           to change the pin multiplexing setup.  When there are no warnings
           printed, it's safe to deselect OMAP_MUX for your product.
 
-config OMAP_MBOX_FWK
-        tristate "Mailbox framework support"
-        depends on ARCH_OMAP && !ARCH_MULTIPLATFORM
-        help
-          Say Y here if you want to use OMAP Mailbox framework support for
-          DSP, IVA1.0 and IVA2 in OMAP1/2/3.
-
-config OMAP_MBOX_KFIFO_SIZE
-        int "Mailbox kfifo default buffer size (bytes)"
-        depends on OMAP_MBOX_FWK
-        default 256
-        help
-          Specify the default size of mailbox's kfifo buffers (bytes).
-          This can also be changed at runtime (via the mbox_kfifo_size
-          module parameter).
-
 config OMAP_IOMMU_IVA2
         bool
 
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 31199417b56a..0b01b68fd033 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -17,6 +17,3 @@ obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
 i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
 obj-y += $(i2c-omap-m) $(i2c-omap-y)
 
-# OMAP mailbox framework
-obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
-
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e06c34bdc34a..4d463ca6821f 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -701,8 +701,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
         for (ch = 0; ch < dma_chan_count; ch++) {
                 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
                         free_ch = ch;
-                        if (dev_id == 0)
-                                break;
+                        /* Exit after first free channel found */
+                        break;
                 }
         }
         if (free_ch == -1) {
@@ -894,11 +894,12 @@ void omap_start_dma(int lch)
                 int next_lch, cur_lch;
                 char dma_chan_link_map[MAX_LOGICAL_DMA_CH_COUNT];
 
-                dma_chan_link_map[lch] = 1;
                 /* Set the link register of the first channel */
                 enable_lnk(lch);
 
                 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
+                dma_chan_link_map[lch] = 1;
+
                 cur_lch = dma_chan[lch].next_lch;
                 do {
                         next_lch = dma_chan[cur_lch].next_lch;
@@ -2110,8 +2111,6 @@ exit_dma_irq_fail:
         }
 
 exit_dma_lch_fail:
-        kfree(p);
-        kfree(d);
         kfree(dma_chan);
         return ret;
 }
@@ -2132,8 +2131,6 @@ static int omap_system_dma_remove(struct platform_device *pdev)
                         free_irq(dma_irq, (void *)(irq_rel + 1));
                 }
         }
-        kfree(p);
-        kfree(d);
         kfree(dma_chan);
         return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
deleted file mode 100644
index cc3921e9059c..000000000000
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* mailbox.h */
-
-#ifndef MAILBOX_H
-#define MAILBOX_H
-
-#include <linux/spinlock.h>
-#include <linux/workqueue.h>
-#include <linux/interrupt.h>
-#include <linux/device.h>
-#include <linux/kfifo.h>
-
-typedef u32 mbox_msg_t;
-struct omap_mbox;
-
-typedef int __bitwise omap_mbox_irq_t;
-#define IRQ_TX ((__force omap_mbox_irq_t) 1)
-#define IRQ_RX ((__force omap_mbox_irq_t) 2)
-
-typedef int __bitwise omap_mbox_type_t;
-#define OMAP_MBOX_TYPE1 ((__force omap_mbox_type_t) 1)
-#define OMAP_MBOX_TYPE2 ((__force omap_mbox_type_t) 2)
-
-struct omap_mbox_ops {
-        omap_mbox_type_t        type;
-        int             (*startup)(struct omap_mbox *mbox);
-        void            (*shutdown)(struct omap_mbox *mbox);
-        /* fifo */
-        mbox_msg_t      (*fifo_read)(struct omap_mbox *mbox);
-        void            (*fifo_write)(struct omap_mbox *mbox, mbox_msg_t msg);
-        int             (*fifo_empty)(struct omap_mbox *mbox);
-        int             (*fifo_full)(struct omap_mbox *mbox);
-        /* irq */
-        void            (*enable_irq)(struct omap_mbox *mbox,
-                                                omap_mbox_irq_t irq);
-        void            (*disable_irq)(struct omap_mbox *mbox,
-                                                omap_mbox_irq_t irq);
-        void            (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        int             (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq);
-        /* ctx */
-        void            (*save_ctx)(struct omap_mbox *mbox);
-        void            (*restore_ctx)(struct omap_mbox *mbox);
-};
-
-struct omap_mbox_queue {
-        spinlock_t              lock;
-        struct kfifo            fifo;
-        struct work_struct      work;
-        struct tasklet_struct   tasklet;
-        struct omap_mbox        *mbox;
-        bool full;
-};
-
-struct omap_mbox {
-        char                    *name;
-        unsigned int            irq;
-        struct omap_mbox_queue  *txq, *rxq;
-        struct omap_mbox_ops    *ops;
-        struct device           *dev;
-        void                    *priv;
-        int                     use_count;
-        struct blocking_notifier_head   notifier;
-};
-
-int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
-void omap_mbox_init_seq(struct omap_mbox *);
-
-struct omap_mbox *omap_mbox_get(const char *, struct notifier_block *nb);
-void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb);
-
-int omap_mbox_register(struct device *parent, struct omap_mbox **);
-int omap_mbox_unregister(void);
-
-static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
-{
-        if (!mbox->ops->save_ctx) {
-                dev_err(mbox->dev, "%s:\tno save\n", __func__);
-                return;
-        }
-
-        mbox->ops->save_ctx(mbox);
-}
-
-static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox)
-{
-        if (!mbox->ops->restore_ctx) {
-                dev_err(mbox->dev, "%s:\tno restore\n", __func__);
-                return;
-        }
-
-        mbox->ops->restore_ctx(mbox);
-}
-
-static inline void omap_mbox_enable_irq(struct omap_mbox *mbox,
-                                        omap_mbox_irq_t irq)
-{
-        mbox->ops->enable_irq(mbox, irq);
-}
-
-static inline void omap_mbox_disable_irq(struct omap_mbox *mbox,
-                                         omap_mbox_irq_t irq)
-{
-        mbox->ops->disable_irq(mbox, irq);
-}
-
-#endif /* MAILBOX_H */
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
deleted file mode 100644
index 42377ef9ea3d..000000000000
--- a/arch/arm/plat-omap/mailbox.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * OMAP mailbox driver
- *
- * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved.
- *
- * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/kfifo.h>
-#include <linux/err.h>
-#include <linux/notifier.h>
-#include <linux/module.h>
-
-#include <plat/mailbox.h>
-
-static struct omap_mbox **mboxes;
-
-static int mbox_configured;
-static DEFINE_MUTEX(mbox_configured_lock);
-
-static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
-module_param(mbox_kfifo_size, uint, S_IRUGO);
-MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
-
-/* Mailbox FIFO handle functions */
-static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_read(mbox);
-}
-static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        mbox->ops->fifo_write(mbox, msg);
-}
-static inline int mbox_fifo_empty(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_empty(mbox);
-}
-static inline int mbox_fifo_full(struct omap_mbox *mbox)
-{
-        return mbox->ops->fifo_full(mbox);
-}
-
-/* Mailbox IRQ handle functions */
-static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        if (mbox->ops->ack_irq)
-                mbox->ops->ack_irq(mbox, irq);
-}
-static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
-{
-        return mbox->ops->is_irq(mbox, irq);
-}
-
-/*
- * message sender
- */
-static int __mbox_poll_for_space(struct omap_mbox *mbox)
-{
-        int ret = 0, i = 1000;
-
-        while (mbox_fifo_full(mbox)) {
-                if (mbox->ops->type == OMAP_MBOX_TYPE2)
-                        return -1;
-                if (--i == 0)
-                        return -1;
-                udelay(1);
-        }
-        return ret;
-}
-
-int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
-{
-        struct omap_mbox_queue *mq = mbox->txq;
-        int ret = 0, len;
-
-        spin_lock_bh(&mq->lock);
-
-        if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
-                ret = -ENOMEM;
-                goto out;
-        }
-
-        if (kfifo_is_empty(&mq->fifo) && !__mbox_poll_for_space(mbox)) {
-                mbox_fifo_write(mbox, msg);
-                goto out;
-        }
-
-        len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-        WARN_ON(len != sizeof(msg));
-
-        tasklet_schedule(&mbox->txq->tasklet);
-
-out:
-        spin_unlock_bh(&mq->lock);
-        return ret;
-}
-EXPORT_SYMBOL(omap_mbox_msg_send);
-
-static void mbox_tx_tasklet(unsigned long tx_data)
-{
-        struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
-        struct omap_mbox_queue *mq = mbox->txq;
-        mbox_msg_t msg;
-        int ret;
-
-        while (kfifo_len(&mq->fifo)) {
-                if (__mbox_poll_for_space(mbox)) {
-                        omap_mbox_enable_irq(mbox, IRQ_TX);
-                        break;
-                }
-
-                ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
-                                                                sizeof(msg));
-                WARN_ON(ret != sizeof(msg));
-
-                mbox_fifo_write(mbox, msg);
-        }
-}
-
-/*
- * Message receiver(workqueue)
- */
-static void mbox_rx_work(struct work_struct *work)
-{
-        struct omap_mbox_queue *mq =
-                        container_of(work, struct omap_mbox_queue, work);
-        mbox_msg_t msg;
-        int len;
-
-        while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
-                len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-                WARN_ON(len != sizeof(msg));
-
-                blocking_notifier_call_chain(&mq->mbox->notifier, len,
-                                                                (void *)msg);
-                spin_lock_irq(&mq->lock);
-                if (mq->full) {
-                        mq->full = false;
-                        omap_mbox_enable_irq(mq->mbox, IRQ_RX);
-                }
-                spin_unlock_irq(&mq->lock);
-        }
-}
-
-/*
- * Mailbox interrupt handler
- */
-static void __mbox_tx_interrupt(struct omap_mbox *mbox)
-{
-        omap_mbox_disable_irq(mbox, IRQ_TX);
-        ack_mbox_irq(mbox, IRQ_TX);
-        tasklet_schedule(&mbox->txq->tasklet);
-}
-
-static void __mbox_rx_interrupt(struct omap_mbox *mbox)
-{
-        struct omap_mbox_queue *mq = mbox->rxq;
-        mbox_msg_t msg;
-        int len;
-
-        while (!mbox_fifo_empty(mbox)) {
-                if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
-                        omap_mbox_disable_irq(mbox, IRQ_RX);
-                        mq->full = true;
-                        goto nomem;
-                }
-
-                msg = mbox_fifo_read(mbox);
-
-                len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
-                WARN_ON(len != sizeof(msg));
-
-                if (mbox->ops->type == OMAP_MBOX_TYPE1)
-                        break;
-        }
-
-        /* no more messages in the fifo. clear IRQ source. */
-        ack_mbox_irq(mbox, IRQ_RX);
-nomem:
-        schedule_work(&mbox->rxq->work);
-}
-
-static irqreturn_t mbox_interrupt(int irq, void *p)
-{
-        struct omap_mbox *mbox = p;
-
-        if (is_mbox_irq(mbox, IRQ_TX))
-                __mbox_tx_interrupt(mbox);
-
-        if (is_mbox_irq(mbox, IRQ_RX))
-                __mbox_rx_interrupt(mbox);
-
-        return IRQ_HANDLED;
-}
-
-static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-                                        void (*work) (struct work_struct *),
-                                        void (*tasklet)(unsigned long))
-{
-        struct omap_mbox_queue *mq;
-
-        mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
-        if (!mq)
-                return NULL;
-
-        spin_lock_init(&mq->lock);
-
-        if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
-                goto error;
-
-        if (work)
-                INIT_WORK(&mq->work, work);
-
-        if (tasklet)
-                tasklet_init(&mq->tasklet, tasklet, (unsigned long)mbox);
-        return mq;
-error:
-        kfree(mq);
-        return NULL;
-}
-
-static void mbox_queue_free(struct omap_mbox_queue *q)
-{
-        kfifo_free(&q->fifo);
-        kfree(q);
-}
-
-static int omap_mbox_startup(struct omap_mbox *mbox)
-{
-        int ret = 0;
-        struct omap_mbox_queue *mq;
-
-        mutex_lock(&mbox_configured_lock);
-        if (!mbox_configured++) {
-                if (likely(mbox->ops->startup)) {
-                        ret = mbox->ops->startup(mbox);
-                        if (unlikely(ret))
-                                goto fail_startup;
-                } else
-                        goto fail_startup;
-        }
-
-        if (!mbox->use_count++) {
-                ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
-                                                        mbox->name, mbox);
-                if (unlikely(ret)) {
-                        pr_err("failed to register mailbox interrupt:%d\n",
-                                                                        ret);
-                        goto fail_request_irq;
-                }
-                mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
-                if (!mq) {
-                        ret = -ENOMEM;
-                        goto fail_alloc_txq;
-                }
-                mbox->txq = mq;
-
-                mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
-                if (!mq) {
-                        ret = -ENOMEM;
-                        goto fail_alloc_rxq;
-                }
-                mbox->rxq = mq;
-                mq->mbox = mbox;
-
-                omap_mbox_enable_irq(mbox, IRQ_RX);
-        }
-        mutex_unlock(&mbox_configured_lock);
-        return 0;
-
-fail_alloc_rxq:
-        mbox_queue_free(mbox->txq);
-fail_alloc_txq:
-        free_irq(mbox->irq, mbox);
-fail_request_irq:
-        if (mbox->ops->shutdown)
-                mbox->ops->shutdown(mbox);
-        mbox->use_count--;
-fail_startup:
-        mbox_configured--;
-        mutex_unlock(&mbox_configured_lock);
-        return ret;
-}
-
-static void omap_mbox_fini(struct omap_mbox *mbox)
-{
-        mutex_lock(&mbox_configured_lock);
-
-        if (!--mbox->use_count) {
-                omap_mbox_disable_irq(mbox, IRQ_RX);
-                free_irq(mbox->irq, mbox);
-                tasklet_kill(&mbox->txq->tasklet);
-                flush_work(&mbox->rxq->work);
-                mbox_queue_free(mbox->txq);
-                mbox_queue_free(mbox->rxq);
-        }
-
-        if (likely(mbox->ops->shutdown)) {
-                if (!--mbox_configured)
-                        mbox->ops->shutdown(mbox);
-        }
-
-        mutex_unlock(&mbox_configured_lock);
-}
-
-struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
-{
-        struct omap_mbox *_mbox, *mbox = NULL;
-        int i, ret;
-
-        if (!mboxes)
-                return ERR_PTR(-EINVAL);
-
-        for (i = 0; (_mbox = mboxes[i]); i++) {
-                if (!strcmp(_mbox->name, name)) {
-                        mbox = _mbox;
-                        break;
-                }
-        }
-
-        if (!mbox)
-                return ERR_PTR(-ENOENT);
-
-        if (nb)
-                blocking_notifier_chain_register(&mbox->notifier, nb);
-
-        ret = omap_mbox_startup(mbox);
-        if (ret) {
-                blocking_notifier_chain_unregister(&mbox->notifier, nb);
-                return ERR_PTR(-ENODEV);
-        }
-
-        return mbox;
-}
-EXPORT_SYMBOL(omap_mbox_get);
-
-void omap_mbox_put(struct omap_mbox *mbox, struct notifier_block *nb)
-{
-        blocking_notifier_chain_unregister(&mbox->notifier, nb);
-        omap_mbox_fini(mbox);
-}
-EXPORT_SYMBOL(omap_mbox_put);
-
-static struct class omap_mbox_class = { .name = "mbox", };
-
-int omap_mbox_register(struct device *parent, struct omap_mbox **list)
-{
-        int ret;
-        int i;
-
-        mboxes = list;
-        if (!mboxes)
-                return -EINVAL;
-
-        for (i = 0; mboxes[i]; i++) {
-                struct omap_mbox *mbox = mboxes[i];
-                mbox->dev = device_create(&omap_mbox_class,
-                                parent, 0, mbox, "%s", mbox->name);
-                if (IS_ERR(mbox->dev)) {
-                        ret = PTR_ERR(mbox->dev);
-                        goto err_out;
-                }
-
-                BLOCKING_INIT_NOTIFIER_HEAD(&mbox->notifier);
-        }
-        return 0;
-
-err_out:
-        while (i--)
-                device_unregister(mboxes[i]->dev);
-        return ret;
-}
-EXPORT_SYMBOL(omap_mbox_register);
-
-int omap_mbox_unregister(void)
-{
-        int i;
-
-        if (!mboxes)
-                return -EINVAL;
-
-        for (i = 0; mboxes[i]; i++)
-                device_unregister(mboxes[i]->dev);
-        mboxes = NULL;
-        return 0;
-}
-EXPORT_SYMBOL(omap_mbox_unregister);
-
-static int __init omap_mbox_init(void)
-{
-        int err;
-
-        err = class_register(&omap_mbox_class);
-        if (err)
-                return err;
-
-        /* kfifo size sanity check: alignment and minimal size */
-        mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
-        mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
-                                                        sizeof(mbox_msg_t));
-
-        return 0;
-}
-subsys_initcall(omap_mbox_init);
-
-static void __exit omap_mbox_exit(void)
-{
-        class_unregister(&omap_mbox_class);
-}
-module_exit(omap_mbox_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
-MODULE_AUTHOR("Toshihiro Kobayashi");
-MODULE_AUTHOR("Hiroshi DOYU");
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c019b7aaf776..c66d163d7a2a 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -666,14 +666,9 @@ void __init orion_xor0_init(unsigned long mapbase_low,
         orion_xor0_shared_resources[3].start = irq_1;
         orion_xor0_shared_resources[3].end = irq_1;
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
         dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[0].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor0_channels_data[0].cap_mask);
 
-        dma_cap_set(DMA_MEMSET, orion_xor0_channels_data[1].cap_mask);
         dma_cap_set(DMA_MEMCPY, orion_xor0_channels_data[1].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor0_channels_data[1].cap_mask);
 
@@ -732,14 +727,9 @@ void __init orion_xor1_init(unsigned long mapbase_low,
         orion_xor1_shared_resources[3].start = irq_1;
         orion_xor1_shared_resources[3].end = irq_1;
 
-        /*
-         * two engines can't do memset simultaneously, this limitation
-         * satisfied by removing memset support from one of the engines.
-         */
         dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[0].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor1_channels_data[0].cap_mask);
 
-        dma_cap_set(DMA_MEMSET, orion_xor1_channels_data[1].cap_mask);
         dma_cap_set(DMA_MEMCPY, orion_xor1_channels_data[1].cap_mask);
         dma_cap_set(DMA_XOR, orion_xor1_channels_data[1].cap_mask);
 
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 249fe6333e18..6816192a7561 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -426,7 +426,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 if (!(cause & (1 << i)))
                         continue;
 
-                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                type = irq_get_trigger_type(irq);
                 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                         /* Swap polarity (race with GPIO line) */
                         u32 polarity;
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index f8ed2de0a678..3dc5cbea86cc 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
 
 config PLAT_SAMSUNG
         bool
-        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
+        depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P || ARCH_EXYNOS
         default y
         select GENERIC_IRQ_CHIP
         select NO_IOPORT
@@ -15,12 +15,10 @@ config PLAT_SAMSUNG
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
         default y
         select ARCH_REQUIRE_GPIOLIB
-        select ARM_GIC if ARCH_EXYNOS
-        select ARM_VIC if !ARCH_EXYNOS
-        select GIC_NON_BANKED if ARCH_EXYNOS4
+        select ARM_VIC
         select NO_IOPORT
         select PLAT_SAMSUNG
         select S3C_GPIO_TRACK
@@ -60,6 +58,20 @@ config S3C_LOWLEVEL_UART_PORT
           this configuration should be between zero and two. The port
           must have been initialised by the boot-loader before use.
 
+config SAMSUNG_ATAGS
+        def_bool n
+        depends on !ARCH_MULTIPLATFORM
+        depends on ATAGS
+        help
+           This option enables ATAGS based boot support code for
+           Samsung platforms, including static platform devices, legacy
+           clock, timer and interrupt initialization, etc.
+
+           Platforms that support only DT based boot need not to select
+           this option.
+
+if SAMSUNG_ATAGS
+
 # timer options
 
 config SAMSUNG_HRT
@@ -367,11 +379,6 @@ config S5P_DEV_JPEG
         help
           Compile in platform device definitions for JPEG codec
 
-config S5P_DEV_MFC
-        bool
-        help
-          Compile in setup memory (init) code for MFC
-
 config S5P_DEV_ONENAND
         bool
         help
@@ -412,6 +419,21 @@ config S3C_DMA
         help
           Internal configuration for S3C DMA core
 
+config S5P_IRQ_PM
+        bool
+        default y if S5P_PM
+        help
+          Legacy IRQ power management for S5P platforms
+
+config SAMSUNG_PM_GPIO
+        bool
+        default y if GPIO_SAMSUNG && PM
+        help
+          Include legacy GPIO power management code for platforms not using
+          pinctrl-samsung driver.
+
+endif
+
 config SAMSUNG_DMADEV
         bool
         select ARM_AMBA
@@ -421,6 +443,11 @@ config SAMSUNG_DMADEV
         help
           Use DMA device engine for PL330 DMAC.
 
+config S5P_DEV_MFC
+        bool
+        help
+          Compile in setup memory (init) code for MFC
+
 comment "Power management"
 
 config SAMSUNG_PM_DEBUG
@@ -475,6 +502,12 @@ config SAMSUNG_WAKEMASK
           and above. This code allows a set of interrupt to wakeup-mask
           mappings. See <plat/wakeup-mask.h>
 
+config SAMSUNG_WDT_RESET
+        bool
+        help
+          Compile support for system restart by triggering watchdog reset.
+          Used on SoCs that do not provide dedicated reset control.
+
 config S5P_PM
         bool
         help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index a23c460299a1..98d07d8fc7a7 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -31,10 +31,10 @@ obj-$(CONFIG_S3C_ADC)	+= adc.o
 
 # devices
 
-obj-y                           += platformdata.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += platformdata.o
 
-obj-y                           += devs.o
-obj-y                           += dev-uart.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += devs.o
+obj-$(CONFIG_SAMSUNG_ATAGS)     += dev-uart.o
 obj-$(CONFIG_S5P_DEV_MFC)       += s5p-dev-mfc.o
 obj-$(CONFIG_S5P_DEV_UART)      += s5p-dev-uart.o
 
@@ -52,10 +52,12 @@ obj-$(CONFIG_SAMSUNG_DMADEV)	+= dma-ops.o
 # PM support
 
 obj-$(CONFIG_PM)                += pm.o
-obj-$(CONFIG_PM)                += pm-gpio.o
+obj-$(CONFIG_SAMSUNG_PM_GPIO)   += pm-gpio.o
 obj-$(CONFIG_SAMSUNG_PM_CHECK)  += pm-check.o
 
 obj-$(CONFIG_SAMSUNG_WAKEMASK)  += wakeup-mask.o
+obj-$(CONFIG_SAMSUNG_WDT_RESET) += watchdog-reset.o
 
-obj-$(CONFIG_S5P_PM)            += s5p-pm.o s5p-irq-pm.o
+obj-$(CONFIG_S5P_PM)            += s5p-pm.o
+obj-$(CONFIG_S5P_IRQ_PM)        += s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 95509d8eb140..7231c8e4975e 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -202,7 +202,7 @@ extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
 extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
 extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
 
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
 #define s3c_cpufreq_debugfs_call(x) x
 #else
 #define s3c_cpufreq_debugfs_call(x) NULL
@@ -259,17 +259,17 @@ extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
 #define s3c2412_iotiming_set NULL
 #endif /* CONFIG_S3C2412_IOTIMING */
 
-#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
 #define s3c_freq_dbg(x...) printk(KERN_INFO x)
 #else
 #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
+#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
 
-#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
+#ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
 #define s3c_freq_iodbg(x...) printk(KERN_INFO x)
 #else
 #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
-#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
+#endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
 
 static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
                                       int index, size_t table_size,
@@ -285,7 +285,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
                 s3c_freq_dbg("%s: { %d = %u kHz }\n",
                              __func__, index, freq);
 
-                table[index].index = index;
+                table[index].driver_data = index;
                 table[index].frequency = freq;
         }
 
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq.h b/arch/arm/plat-samsung/include/plat/cpu-freq.h
index 80c4a809c721..85517ab962ae 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq.h
@@ -126,7 +126,7 @@ struct s3c_cpufreq_board {
 };
 
 /* Things depending on frequency scaling. */
-#ifdef CONFIG_CPU_FREQ_S3C
+#ifdef CONFIG_ARM_S3C_CPUFREQ
 #define __init_or_cpufreq
 #else
 #define __init_or_cpufreq __init
@@ -134,7 +134,7 @@ struct s3c_cpufreq_board {
 
 /* Board functions */
 
-#ifdef CONFIG_CPU_FREQ_S3C
+#ifdef CONFIG_ARM_S3C_CPUFREQ
 extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board);
 #else
 
@@ -142,4 +142,4 @@ static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
 {
         return 0;
 }
-#endif  /* CONFIG_CPU_FREQ_S3C */
+#endif  /* CONFIG_ARM_S3C_CPUFREQ */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 989fefe18be6..4fb1f03a10d1 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
 #define EXYNOS4_CPU_MASK        0xFFFE0000
 
 #define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5420_SOC_ID       0xE5420000
 #define EXYNOS5440_SOC_ID       0xE5440000
 #define EXYNOS5_SOC_MASK        0xFFFFF000
 
@@ -67,6 +68,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
 IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
 IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -142,6 +144,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_exynos5250()    0
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+# define soc_is_exynos5420()    is_samsung_exynos5420()
+#else
+# define soc_is_exynos5420()    0
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 # define soc_is_exynos5440()    is_samsung_exynos5440()
 #else
diff --git a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
index d01576318b2c..bd3a6db14cbb 100644
--- a/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
+++ b/arch/arm/plat-samsung/include/plat/dma-s3c24xx.h
@@ -28,7 +28,6 @@ struct s3c24xx_dma_map {
         const char              *name;
 
         unsigned long            channels[S3C_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C_DMA_CHANNELS];
 };
 
 struct s3c24xx_dma_selection {
@@ -38,10 +37,6 @@ struct s3c24xx_dma_selection {
 
         void    (*select)(struct s3c2410_dma_chan *chan,
                           struct s3c24xx_dma_map *map);
-
-        void    (*direction)(struct s3c2410_dma_chan *chan,
-                             struct s3c24xx_dma_map *map,
-                             enum dma_data_direction dir);
 };
 
 extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index f6fcadeee969..5d47ca35cabd 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -166,6 +166,7 @@ extern void s3c_pm_check_store(void);
  */
 extern void s3c_pm_configure_extint(void);
 
+#ifdef CONFIG_GPIO_SAMSUNG
 /**
  * samsung_pm_restore_gpios() - restore the state of the gpios after sleep.
  *
@@ -181,6 +182,10 @@ extern void samsung_pm_restore_gpios(void);
  * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios().
  */
 extern void samsung_pm_save_gpios(void);
+#else
+static inline void samsung_pm_restore_gpios(void) {}
+static inline void samsung_pm_save_gpios(void) {}
+#endif
 
 extern void s3c_pm_save_core(void);
 extern void s3c_pm_restore_core(void);
diff --git a/arch/arm/plat-samsung/include/plat/regs-watchdog.h b/arch/arm/plat-samsung/include/plat/regs-watchdog.h
deleted file mode 100644
index 4938492470f7..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H
-
-#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-
-#define S3C2410_WTCON      S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN   (0x01)
-#define S3C2410_WTCON_INTEN   (1<<2)
-#define S3C2410_WTCON_ENABLE  (1<<5)
-
-#define S3C2410_WTCON_DIV16   (0<<3)
-#define S3C2410_WTCON_DIV32   (1<<3)
-#define S3C2410_WTCON_DIV64   (2<<3)
-#define S3C2410_WTCON_DIV128  (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 02b66d723d1a..4afc32f90b6d 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -21,6 +21,8 @@ typedef unsigned int upf_t;	/* cannot include linux/serial_core.h */
 unsigned int fifo_mask;
 unsigned int fifo_max;
 
+volatile u8 *uart_base;
+
 /* forward declerations */
 
 static void arch_detect_cpu(void);
@@ -28,19 +30,24 @@ static void arch_detect_cpu(void);
 /* defines for UART registers */
 
 #include <plat/regs-serial.h>
-#include <plat/regs-watchdog.h>
 
 /* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+#define S3C_WDOGREG(x)  ((S3C_PA_WDT + (x)))
+
+#define S3C2410_WTCON   S3C_WDOGREG(0x00)
+#define S3C2410_WTDAT   S3C_WDOGREG(0x04)
+#define S3C2410_WTCNT   S3C_WDOGREG(0x08)
+
+#define S3C2410_WTCON_RSTEN     (1 << 0)
+#define S3C2410_WTCON_ENABLE    (1 << 5)
+
+#define S3C2410_WTCON_DIV128    (3 << 3)
+
+#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
 
 /* how many bytes we allow into the FIFO at a time in FIFO mode */
 #define FIFO_MAX         (14)
 
-#ifdef S3C_PA_UART
-#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT)
-#endif
-
 static __inline__ void
 uart_wr(unsigned int reg, unsigned int val)
 {
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index bc4db9b04e36..0386b8f76623 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,37 +10,11 @@
  * published by the Free Software Foundation.
 */
 
-#include <plat/clock.h>
-#include <plat/regs-watchdog.h>
-#include <mach/map.h>
+#ifndef __PLAT_SAMSUNG_WATCHDOG_RESET_H
+#define __PLAT_SAMSUNG_WATCHDOG_RESET_H
 
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/delay.h>
+extern void samsung_wdt_reset(void);
+extern void samsung_wdt_reset_of_init(void);
+extern void samsung_wdt_reset_init(void __iomem *base);
 
-static inline void arch_wdt_reset(void)
-{
-        printk("arch_reset: attempting watchdog reset\n");
-
-        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
-
-        if (!IS_ERR(s3c2410_wdtclk))
-                clk_enable(s3c2410_wdtclk);
-
-        /* put initial values into count and data */
-        __raw_writel(0x80, S3C2410_WTCNT);
-        __raw_writel(0x80, S3C2410_WTDAT);
-
-        /* set the watchdog to go and reset... */
-        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
-                     S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
-
-        /* wait for reset to assert... */
-        mdelay(500);
-
-        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
-
-        /* delay to allow the serial port to show the message */
-        mdelay(50);
-}
+#endif /* __PLAT_SAMSUNG_WATCHDOG_RESET_H */
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 79d10fca9090..3e5c4619caa5 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -87,7 +87,7 @@ void __init s3c24xx_init_clocks(int xtal)
 }
 
 /* uart management */
-
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
 static int nr_uarts __initdata = 0;
 
 static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS];
@@ -134,11 +134,12 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
         if (cpu == NULL)
                 return;
 
-        if (cpu->init_uarts == NULL) {
+        if (cpu->init_uarts == NULL && IS_ENABLED(CONFIG_SAMSUNG_ATAGS)) {
                 printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
         } else
                 (cpu->init_uarts)(cfg, no);
 }
+#endif
 
 static int __init s3c_arch_init(void)
 {
@@ -152,8 +153,9 @@ static int __init s3c_arch_init(void)
         ret = (cpu->init)();
         if (ret != 0)
                 return ret;
-
+#if IS_ENABLED(CONFIG_SAMSUNG_ATAGS)
         ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
+#endif
         return ret;
 }
 
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index c2ff92c30bdf..a8de3cfe2ee1 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,8 @@ struct samsung_gpio_pm samsung_gpio_pm_2bit = {
         .resume = samsung_gpio_pm_2bit_resume,
 };
 
-#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) \
+        || defined(CONFIG_ARCH_EXYNOS)
 static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip)
 {
         chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +303,7 @@ struct samsung_gpio_pm samsung_gpio_pm_4bit = {
         .save   = samsung_gpio_pm_4bit_save,
         .resume = samsung_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P || CONFIG_ARCH_EXYNOS */
 
 /**
  * samsung_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 53210ec4e8ec..ea3613642451 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -16,18 +16,23 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/of.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
 #include <asm/suspend.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
 
 #include <plat/regs-serial.h>
+
+#ifdef CONFIG_SAMSUNG_ATAGS
+#include <mach/hardware.h>
+#include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
 #include <mach/irqs.h>
+#endif
+
 #include <asm/irq.h>
 
 #include <plat/pm.h>
@@ -261,7 +266,8 @@ static int s3c_pm_enter(suspend_state_t state)
          * require a full power-cycle)
         */
 
-        if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
+        if (!of_have_populated_dt() &&
+            !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
                 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
                 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
@@ -270,8 +276,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         /* save all necessary core registers not covered by the drivers */
 
-        samsung_pm_save_gpios();
-        samsung_pm_saved_gpios();
+        if (!of_have_populated_dt()) {
+                samsung_pm_save_gpios();
+                samsung_pm_saved_gpios();
+        }
+
         s3c_pm_save_uarts();
         s3c_pm_save_core();
 
@@ -310,8 +319,11 @@ static int s3c_pm_enter(suspend_state_t state)
 
         s3c_pm_restore_core();
         s3c_pm_restore_uarts();
-        samsung_pm_restore_gpios();
-        s3c_pm_restored_gpios();
+
+        if (!of_have_populated_dt()) {
+                samsung_pm_restore_gpios();
+                s3c_pm_restored_gpios();
+        }
 
         s3c_pm_debug_init();
 
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index a93fb6fb6606..ad51f85fbd01 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -17,10 +17,12 @@
 #include <linux/of_fdt.h>
 #include <linux/of.h>
 
+#include <plat/mfc.h>
+
+#ifdef CONFIG_SAMSUNG_ATAGS
 #include <mach/map.h>
 #include <mach/irqs.h>
 #include <plat/devs.h>
-#include <plat/mfc.h>
 
 static struct resource s5p_mfc_resource[] = {
         [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
@@ -61,6 +63,10 @@ struct platform_device s5p_device_mfc_r = {
                 .coherent_dma_mask      = DMA_BIT_MASK(32),
         },
 };
+#else
+static struct platform_device s5p_device_mfc_l;
+static struct platform_device s5p_device_mfc_r;
+#endif
 
 struct s5p_mfc_reserved_mem {
         phys_addr_t     base;
@@ -70,6 +76,7 @@ struct s5p_mfc_reserved_mem {
 
 static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
 
+
 void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
                                 phys_addr_t lbase, unsigned int lsize)
 {
@@ -93,6 +100,7 @@ void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
         }
 }
 
+#ifdef CONFIG_SAMSUNG_ATAGS
 static int __init s5p_mfc_memory_init(void)
 {
         int i;
@@ -111,6 +119,7 @@ static int __init s5p_mfc_memory_init(void)
         return 0;
 }
 device_initcall(s5p_mfc_memory_init);
+#endif
 
 #ifdef CONFIG_OF
 int __init s5p_fdt_find_mfc_mem(unsigned long node, const char *uname,
diff --git a/arch/arm/plat-samsung/watchdog-reset.c b/arch/arm/plat-samsung/watchdog-reset.c
new file mode 100644
index 000000000000..2ecb50bea044
--- /dev/null
+++ b/arch/arm/plat-samsung/watchdog-reset.c
@@ -0,0 +1,97 @@
+/* arch/arm/plat-samsung/watchdog-reset.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Coyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+ *
+ * Watchdog reset support for Samsung SoCs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define S3C2410_WTCON                   0x00
+#define S3C2410_WTDAT                   0x04
+#define S3C2410_WTCNT                   0x08
+
+#define S3C2410_WTCON_ENABLE            (1 << 5)
+#define S3C2410_WTCON_DIV16             (0 << 3)
+#define S3C2410_WTCON_RSTEN             (1 << 0)
+#define S3C2410_WTCON_PRESCALE(x)       ((x) << 8)
+
+static void __iomem *wdt_base;
+static struct clk *wdt_clock;
+
+void samsung_wdt_reset(void)
+{
+        if (!wdt_base) {
+                pr_err("%s: wdt reset not initialized\n", __func__);
+                /* delay to allow the serial port to show the message */
+                mdelay(50);
+                return;
+        }
+
+        if (!IS_ERR(wdt_clock))
+                clk_prepare_enable(wdt_clock);
+
+        /* disable watchdog, to be safe  */
+        __raw_writel(0, wdt_base + S3C2410_WTCON);
+
+        /* put initial values into count and data */
+        __raw_writel(0x80, wdt_base + S3C2410_WTCNT);
+        __raw_writel(0x80, wdt_base + S3C2410_WTDAT);
+
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
+                        S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
+                        wdt_base + S3C2410_WTCON);
+
+        /* wait for reset to assert... */
+        mdelay(500);
+
+        pr_err("Watchdog reset failed to assert reset\n");
+
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+}
+
+#ifdef CONFIG_OF
+static const struct of_device_id s3c2410_wdt_match[] = {
+        { .compatible = "samsung,s3c2410-wdt" },
+        {},
+};
+
+void __init samsung_wdt_reset_of_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, s3c2410_wdt_match);
+        if (!np) {
+                pr_err("%s: failed to find watchdog node\n", __func__);
+                return;
+        }
+
+        wdt_base = of_iomap(np, 0);
+        if (!wdt_base) {
+                pr_err("%s: failed to map watchdog registers\n", __func__);
+                return;
+        }
+
+        wdt_clock = of_clk_get(np, 0);
+}
+#endif
+
+void __init samsung_wdt_reset_init(void __iomem *base)
+{
+        wdt_base = base;
+        wdt_clock = clk_get(NULL, "watchdog");
+}
diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S
index b178d44e9eaa..2677bc3762d7 100644
--- a/arch/arm/plat-versatile/headsmp.S
+++ b/arch/arm/plat-versatile/headsmp.S
@@ -11,8 +11,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        __INIT
-
 /*
  * Realview/Versatile Express specific entry point for secondary CPUs.
  * This provides a "holding pen" into which all secondary cores are held
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 56b3f6d447ae..4143d9b0d87a 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -7,6 +7,7 @@ config ARM64
         select ARM_AMBA
         select ARM_ARCH_TIMER
         select ARM_GIC
+        select BUILDTIME_EXTABLE_SORT
         select CLONE_BACKWARDS
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
@@ -111,6 +112,11 @@ config ARCH_VEXPRESS
           This enables support for the ARMv8 software model (Versatile
           Express).
 
+config ARCH_XGENE
+        bool "AppliedMicro X-Gene SOC Family"
+        help
+          This enables support for AppliedMicro X-Gene SOC Family
+
 endmenu
 
 menu "Bus support"
@@ -148,6 +154,8 @@ config NR_CPUS
         int "Maximum number of CPUs (2-32)"
         range 2 32
         depends on SMP
+        # These have to remain sorted largest to smallest
+        default "8" if ARCH_XGENE
         default "4"
 
 source kernel/Kconfig.preempt
@@ -180,8 +188,35 @@ config HW_PERF_EVENTS
           Enable hardware performance counter support for perf events. If
           disabled, perf events will use software events only.
 
+config SYS_SUPPORTS_HUGETLBFS
+        def_bool y
+
+config ARCH_WANT_GENERAL_HUGETLB
+        def_bool y
+
+config ARCH_WANT_HUGE_PMD_SHARE
+        def_bool y if !ARM64_64K_PAGES
+
+config HAVE_ARCH_TRANSPARENT_HUGEPAGE
+        def_bool y
+
 source "mm/Kconfig"
 
+config XEN_DOM0
+        def_bool y
+        depends on XEN
+
+config XEN
+        bool "Xen guest support on ARM64 (EXPERIMENTAL)"
+        depends on ARM64 && OF
+        help
+          Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
+
+config FORCE_MAX_ZONEORDER
+        int
+        default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
+        default "11"
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index c95c5cb212fd..d90cf79f233a 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -37,6 +37,8 @@ TEXT_OFFSET := 0x00080000
 export  TEXT_OFFSET GZFLAGS
 
 core-y          += arch/arm64/kernel/ arch/arm64/mm/
+core-$(CONFIG_KVM) += arch/arm64/kvm/
+core-$(CONFIG_XEN) += arch/arm64/xen/
 libs-y          := arch/arm64/lib/ $(libs-y)
 libs-y          += $(LIBGCC)
 
@@ -60,6 +62,10 @@ zinstall install: vmlinux
 dtbs: scripts
         $(Q)$(MAKE) $(build)=$(boot)/dts dtbs
 
+PHONY += vdso_install
+vdso_install:
+        $(Q)$(MAKE) $(build)=arch/arm64/kernel/vdso $@
+
 # We use MRPROPER_FILES and CLEAN_FILES now
 archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index 68457e9e0975..c52bdb051f66 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -1,4 +1,5 @@
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
+dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
 
 targets += dtbs
 targets += $(dtb-y)
diff --git a/arch/arm64/boot/dts/apm-mustang.dts b/arch/arm64/boot/dts/apm-mustang.dts
new file mode 100644
index 000000000000..1247ca1200b1
--- /dev/null
+++ b/arch/arm64/boot/dts/apm-mustang.dts
@@ -0,0 +1,26 @@
+/*
+ * dts file for AppliedMicro (APM) Mustang Board
+ *
+ * Copyright (C) 2013, Applied Micro Circuits Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "apm-storm.dtsi"
+
+/ {
+        model = "APM X-Gene Mustang board";
+        compatible = "apm,mustang", "apm,xgene-storm";
+
+        chosen { };
+
+        memory {
+                device_type = "memory";
+                reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
+        };
+};
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
new file mode 100644
index 000000000000..bfdc57834929
--- /dev/null
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -0,0 +1,116 @@
+/*
+ * dts file for AppliedMicro (APM) X-Gene Storm SOC
+ *
+ * Copyright (C) 2013, Applied Micro Circuits Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+        compatible = "apm,xgene-storm";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <2>;
+                #size-cells = <0>;
+
+                cpu@000 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x000>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@001 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x001>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@100 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x100>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@101 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x101>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@200 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x200>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@201 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x201>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@300 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x300>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+                cpu@301 {
+                        device_type = "cpu";
+                        compatible = "apm,potenza", "arm,armv8";
+                        reg = <0x0 0x301>;
+                        enable-method = "spin-table";
+                        cpu-release-addr = <0x1 0x0000fff8>;
+                };
+        };
+
+        gic: interrupt-controller@78010000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x0 0x78010000 0x0 0x1000>,      /* GIC Dist */
+                      <0x0 0x78020000 0x0 0x1000>,      /* GIC CPU */
+                      <0x0 0x78040000 0x0 0x2000>,      /* GIC VCPU Control */
+                      <0x0 0x78060000 0x0 0x2000>;      /* GIC VCPU */
+                interrupts = <1 9 0xf04>;       /* GIC Maintenence IRQ */
+        };
+
+        timer {
+                compatible = "arm,armv8-timer";
+                interrupts = <1 0 0xff01>,      /* Secure Phys IRQ */
+                             <1 13 0xff01>,     /* Non-secure Phys IRQ */
+                             <1 14 0xff01>,     /* Virt IRQ */
+                             <1 15 0xff01>;     /* Hyp IRQ */
+                clock-frequency = <50000000>;
+        };
+
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                serial0: serial@1c020000 {
+                        device_type = "serial";
+                        compatible = "ns16550";
+                        reg = <0 0x1c020000 0x0 0x1000>;
+                        reg-shift = <2>;
+                        clock-frequency = <10000000>; /* Updated by bootloader */
+                        interrupt-parent = <&gic>;
+                        interrupts = <0x0 0x4c 0x4>;
+                };
+        };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8d9696adb440..5b3e83217b03 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -24,6 +24,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_XGENE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_CMDLINE="console=ttyAMA0"
@@ -54,6 +55,9 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_SERIO_I8042 is not set
 # CONFIG_SERIO_SERPORT is not set
 CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
index bf6ab242f047..d56ed11ba9a3 100644
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -110,16 +110,6 @@ static inline void __cpuinit arch_counter_set_user_access(void)
         asm volatile("msr       cntkctl_el1, %0" : : "r" (cntkctl));
 }
 
-static inline u64 arch_counter_get_cntpct(void)
-{
-        u64 cval;
-
-        isb();
-        asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
-
-        return cval;
-}
-
 static inline u64 arch_counter_get_cntvct(void)
 {
         u64 cval;
diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 3300cbd18a89..fea9ee327206 100644
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -123,9 +123,6 @@ static inline void __flush_icache_all(void)
 #define flush_dcache_mmap_unlock(mapping) \
         spin_unlock_irq(&(mapping)->tree_lock)
 
-#define flush_icache_user_range(vma,page,addr,len) \
-        flush_dcache_page(page)
-
 /*
  * We don't appear to need to do anything here.  In fact, if we did, we'd
  * duplicate cache flushing elsewhere performed by flush_dcache_page().
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index cf2749488cd4..5fe138e0b828 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -37,11 +37,14 @@
 })
 
 #define ARM_CPU_IMP_ARM         0x41
+#define ARM_CPU_IMP_APM         0x50
 
 #define ARM_CPU_PART_AEM_V8     0xD0F0
 #define ARM_CPU_PART_FOUNDATION 0xD000
 #define ARM_CPU_PART_CORTEX_A57 0xD070
 
+#define APM_CPU_PART_POTENZA    0x0000
+
 #ifndef __ASSEMBLY__
 
 /*
diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h
index 7eaa0b302493..ef8235c68c09 100644
--- a/arch/arm64/include/asm/debug-monitors.h
+++ b/arch/arm64/include/asm/debug-monitors.h
@@ -83,6 +83,15 @@ static inline int reinstall_suspended_bps(struct pt_regs *regs)
 }
 #endif
 
+#ifdef CONFIG_COMPAT
+int aarch32_break_handler(struct pt_regs *regs);
+#else
+static int aarch32_break_handler(struct pt_regs *regs)
+{
+        return -EFAULT;
+}
+#endif
+
 #endif  /* __ASSEMBLY */
 #endif  /* __KERNEL__ */
 #endif  /* __ASM_DEBUG_MONITORS_H */
diff --git a/arch/arm64/include/asm/device.h b/arch/arm64/include/asm/device.h
index 0d8453c755a8..cf98b362094b 100644
--- a/arch/arm64/include/asm/device.h
+++ b/arch/arm64/include/asm/device.h
@@ -18,6 +18,9 @@
 
 struct dev_archdata {
         struct dma_map_ops *dma_ops;
+#ifdef CONFIG_IOMMU_API
+        void *iommu;                    /* private IOMMU data */
+#endif
 };
 
 struct pdev_archdata {
diff --git a/arch/arm64/include/asm/dma-mapping.h b/arch/arm64/include/asm/dma-mapping.h
index 994776894198..8d1810001aef 100644
--- a/arch/arm64/include/asm/dma-mapping.h
+++ b/arch/arm64/include/asm/dma-mapping.h
@@ -81,8 +81,12 @@ static inline void dma_mark_clean(void *addr, size_t size)
 {
 }
 
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                                       dma_addr_t *dma_handle, gfp_t flags)
+#define dma_alloc_coherent(d, s, h, f)  dma_alloc_attrs(d, s, h, f, NULL)
+#define dma_free_coherent(d, s, h, f)   dma_free_attrs(d, s, h, f, NULL)
+
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+                                    dma_addr_t *dma_handle, gfp_t flags,
+                                    struct dma_attrs *attrs)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
         void *vaddr;
@@ -90,13 +94,14 @@ static inline void *dma_alloc_coherent(struct device *dev, size_t size,
         if (dma_alloc_from_coherent(dev, size, dma_handle, &vaddr))
                 return vaddr;
 
-        vaddr = ops->alloc(dev, size, dma_handle, flags, NULL);
+        vaddr = ops->alloc(dev, size, dma_handle, flags, attrs);
         debug_dma_alloc_coherent(dev, size, *dma_handle, vaddr);
         return vaddr;
 }
 
-static inline void dma_free_coherent(struct device *dev, size_t size,
-                                     void *vaddr, dma_addr_t dev_addr)
+static inline void dma_free_attrs(struct device *dev, size_t size,
+                                  void *vaddr, dma_addr_t dev_addr,
+                                  struct dma_attrs *attrs)
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
 
@@ -104,7 +109,7 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
                 return;
 
         debug_dma_free_coherent(dev, size, vaddr, dev_addr);
-        ops->free(dev, size, vaddr, dev_addr, NULL);
+        ops->free(dev, size, vaddr, dev_addr, attrs);
 }
 
 /*
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
new file mode 100644
index 000000000000..5b7ca8ace95f
--- /dev/null
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm64/include/asm/hugetlb.h
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/include/asm/hugetlb.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __ASM_HUGETLB_H
+#define __ASM_HUGETLB_H
+
+#include <asm-generic/hugetlb.h>
+#include <asm/page.h>
+
+static inline pte_t huge_ptep_get(pte_t *ptep)
+{
+        return *ptep;
+}
+
+static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+                                   pte_t *ptep, pte_t pte)
+{
+        set_pte_at(mm, addr, ptep, pte);
+}
+
+static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
+                                         unsigned long addr, pte_t *ptep)
+{
+        ptep_clear_flush(vma, addr, ptep);
+}
+
+static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
+                                           unsigned long addr, pte_t *ptep)
+{
+        ptep_set_wrprotect(mm, addr, ptep);
+}
+
+static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return ptep_get_and_clear(mm, addr, ptep);
+}
+
+static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+                                             unsigned long addr, pte_t *ptep,
+                                             pte_t pte, int dirty)
+{
+        return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+}
+
+static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
+                                          unsigned long addr, unsigned long end,
+                                          unsigned long floor,
+                                          unsigned long ceiling)
+{
+        free_pgd_range(tlb, addr, end, floor, ceiling);
+}
+
+static inline int is_hugepage_only_range(struct mm_struct *mm,
+                                         unsigned long addr, unsigned long len)
+{
+        return 0;
+}
+
+static inline int prepare_hugepage_range(struct file *file,
+                                         unsigned long addr, unsigned long len)
+{
+        struct hstate *h = hstate_file(file);
+        if (len & ~huge_page_mask(h))
+                return -EINVAL;
+        if (addr & ~huge_page_mask(h))
+                return -EINVAL;
+        return 0;
+}
+
+static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
+{
+}
+
+static inline int huge_pte_none(pte_t pte)
+{
+        return pte_none(pte);
+}
+
+static inline pte_t huge_pte_wrprotect(pte_t pte)
+{
+        return pte_wrprotect(pte);
+}
+
+static inline int arch_prepare_hugepage(struct page *page)
+{
+        return 0;
+}
+
+static inline void arch_release_hugepage(struct page *page)
+{
+}
+
+static inline void arch_clear_hugepage_flags(struct page *page)
+{
+        clear_bit(PG_dcache_clean, &page->flags);
+}
+
+#endif /* __ASM_HUGETLB_H */
diff --git a/arch/arm64/include/asm/hypervisor.h b/arch/arm64/include/asm/hypervisor.h
new file mode 100644
index 000000000000..d2c79049ff11
--- /dev/null
+++ b/arch/arm64/include/asm/hypervisor.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM64_HYPERVISOR_H
+#define _ASM_ARM64_HYPERVISOR_H
+
+#include <asm/xen/hypervisor.h>
+
+#endif
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 2e12258aa7e4..1d12f89140ba 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -228,10 +228,12 @@ extern void __iounmap(volatile void __iomem *addr);
 #define PROT_DEFAULT            (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY)
 #define PROT_DEVICE_nGnRE       (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
 #define PROT_NORMAL_NC          (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC))
+#define PROT_NORMAL             (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
 
 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
+#define ioremap_cached(addr, size)      __ioremap((addr), (size), __pgprot(PROT_NORMAL))
 #define iounmap                         __iounmap
 
 #define PROT_SECT_DEFAULT       (PMD_TYPE_SECT | PMD_SECT_AF)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
new file mode 100644
index 000000000000..a5f28e2720c7
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_ARM_H__
+#define __ARM64_KVM_ARM_H__
+
+#include <asm/types.h>
+
+/* Hyp Configuration Register (HCR) bits */
+#define HCR_ID          (UL(1) << 33)
+#define HCR_CD          (UL(1) << 32)
+#define HCR_RW_SHIFT    31
+#define HCR_RW          (UL(1) << HCR_RW_SHIFT)
+#define HCR_TRVM        (UL(1) << 30)
+#define HCR_HCD         (UL(1) << 29)
+#define HCR_TDZ         (UL(1) << 28)
+#define HCR_TGE         (UL(1) << 27)
+#define HCR_TVM         (UL(1) << 26)
+#define HCR_TTLB        (UL(1) << 25)
+#define HCR_TPU         (UL(1) << 24)
+#define HCR_TPC         (UL(1) << 23)
+#define HCR_TSW         (UL(1) << 22)
+#define HCR_TAC         (UL(1) << 21)
+#define HCR_TIDCP       (UL(1) << 20)
+#define HCR_TSC         (UL(1) << 19)
+#define HCR_TID3        (UL(1) << 18)
+#define HCR_TID2        (UL(1) << 17)
+#define HCR_TID1        (UL(1) << 16)
+#define HCR_TID0        (UL(1) << 15)
+#define HCR_TWE         (UL(1) << 14)
+#define HCR_TWI         (UL(1) << 13)
+#define HCR_DC          (UL(1) << 12)
+#define HCR_BSU         (3 << 10)
+#define HCR_BSU_IS      (UL(1) << 10)
+#define HCR_FB          (UL(1) << 9)
+#define HCR_VA          (UL(1) << 8)
+#define HCR_VI          (UL(1) << 7)
+#define HCR_VF          (UL(1) << 6)
+#define HCR_AMO         (UL(1) << 5)
+#define HCR_IMO         (UL(1) << 4)
+#define HCR_FMO         (UL(1) << 3)
+#define HCR_PTW         (UL(1) << 2)
+#define HCR_SWIO        (UL(1) << 1)
+#define HCR_VM          (UL(1) << 0)
+
+/*
+ * The bits we set in HCR:
+ * RW:          64bit by default, can be overriden for 32bit VMs
+ * TAC:         Trap ACTLR
+ * TSC:         Trap SMC
+ * TSW:         Trap cache operations by set/way
+ * TWI:         Trap WFI
+ * TIDCP:       Trap L2CTLR/L2ECTLR
+ * BSU_IS:      Upgrade barriers to the inner shareable domain
+ * FB:          Force broadcast of all maintainance operations
+ * AMO:         Override CPSR.A and enable signaling with VA
+ * IMO:         Override CPSR.I and enable signaling with VI
+ * FMO:         Override CPSR.F and enable signaling with VF
+ * SWIO:        Turn set/way invalidates into set/way clean+invalidate
+ */
+#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \
+                         HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \
+                         HCR_SWIO | HCR_TIDCP | HCR_RW)
+#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)
+
+/* Hyp System Control Register (SCTLR_EL2) bits */
+#define SCTLR_EL2_EE    (1 << 25)
+#define SCTLR_EL2_WXN   (1 << 19)
+#define SCTLR_EL2_I     (1 << 12)
+#define SCTLR_EL2_SA    (1 << 3)
+#define SCTLR_EL2_C     (1 << 2)
+#define SCTLR_EL2_A     (1 << 1)
+#define SCTLR_EL2_M     1
+#define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C |      \
+                         SCTLR_EL2_SA | SCTLR_EL2_I)
+
+/* TCR_EL2 Registers bits */
+#define TCR_EL2_TBI     (1 << 20)
+#define TCR_EL2_PS      (7 << 16)
+#define TCR_EL2_PS_40B  (2 << 16)
+#define TCR_EL2_TG0     (1 << 14)
+#define TCR_EL2_SH0     (3 << 12)
+#define TCR_EL2_ORGN0   (3 << 10)
+#define TCR_EL2_IRGN0   (3 << 8)
+#define TCR_EL2_T0SZ    0x3f
+#define TCR_EL2_MASK    (TCR_EL2_TG0 | TCR_EL2_SH0 | \
+                         TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ)
+
+#define TCR_EL2_FLAGS   (TCR_EL2_PS_40B)
+
+/* VTCR_EL2 Registers bits */
+#define VTCR_EL2_PS_MASK        (7 << 16)
+#define VTCR_EL2_PS_40B         (2 << 16)
+#define VTCR_EL2_TG0_MASK       (1 << 14)
+#define VTCR_EL2_TG0_4K         (0 << 14)
+#define VTCR_EL2_TG0_64K        (1 << 14)
+#define VTCR_EL2_SH0_MASK       (3 << 12)
+#define VTCR_EL2_SH0_INNER      (3 << 12)
+#define VTCR_EL2_ORGN0_MASK     (3 << 10)
+#define VTCR_EL2_ORGN0_WBWA     (1 << 10)
+#define VTCR_EL2_IRGN0_MASK     (3 << 8)
+#define VTCR_EL2_IRGN0_WBWA     (1 << 8)
+#define VTCR_EL2_SL0_MASK       (3 << 6)
+#define VTCR_EL2_SL0_LVL1       (1 << 6)
+#define VTCR_EL2_T0SZ_MASK      0x3f
+#define VTCR_EL2_T0SZ_40B       24
+
+#ifdef CONFIG_ARM64_64K_PAGES
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 64kB pages (TG0 = 1)
+ * 2 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS          (VTCR_EL2_PS_40B | VTCR_EL2_TG0_64K | \
+                                 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+                                 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+                                 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X         (38 - VTCR_EL2_T0SZ_40B)
+#else
+/*
+ * Stage2 translation configuration:
+ * 40bits output (PS = 2)
+ * 40bits input  (T0SZ = 24)
+ * 4kB pages (TG0 = 0)
+ * 3 level page tables (SL = 1)
+ */
+#define VTCR_EL2_FLAGS          (VTCR_EL2_PS_40B | VTCR_EL2_TG0_4K | \
+                                 VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
+                                 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_SL0_LVL1 | \
+                                 VTCR_EL2_T0SZ_40B)
+#define VTTBR_X         (37 - VTCR_EL2_T0SZ_40B)
+#endif
+
+#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
+#define VTTBR_BADDR_MASK  (((1LLU << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_VMID_SHIFT  (48LLU)
+#define VTTBR_VMID_MASK   (0xffLLU << VTTBR_VMID_SHIFT)
+
+/* Hyp System Trap Register */
+#define HSTR_EL2_TTEE   (1 << 16)
+#define HSTR_EL2_T(x)   (1 << x)
+
+/* Hyp Coprocessor Trap Register */
+#define CPTR_EL2_TCPAC  (1 << 31)
+#define CPTR_EL2_TTA    (1 << 20)
+#define CPTR_EL2_TFP    (1 << 10)
+
+/* Hyp Debug Configuration Register bits */
+#define MDCR_EL2_TDRA           (1 << 11)
+#define MDCR_EL2_TDOSA          (1 << 10)
+#define MDCR_EL2_TDA            (1 << 9)
+#define MDCR_EL2_TDE            (1 << 8)
+#define MDCR_EL2_HPME           (1 << 7)
+#define MDCR_EL2_TPM            (1 << 6)
+#define MDCR_EL2_TPMCR          (1 << 5)
+#define MDCR_EL2_HPMN_MASK      (0x1F)
+
+/* Exception Syndrome Register (ESR) bits */
+#define ESR_EL2_EC_SHIFT        (26)
+#define ESR_EL2_EC              (0x3fU << ESR_EL2_EC_SHIFT)
+#define ESR_EL2_IL              (1U << 25)
+#define ESR_EL2_ISS             (ESR_EL2_IL - 1)
+#define ESR_EL2_ISV_SHIFT       (24)
+#define ESR_EL2_ISV             (1U << ESR_EL2_ISV_SHIFT)
+#define ESR_EL2_SAS_SHIFT       (22)
+#define ESR_EL2_SAS             (3U << ESR_EL2_SAS_SHIFT)
+#define ESR_EL2_SSE             (1 << 21)
+#define ESR_EL2_SRT_SHIFT       (16)
+#define ESR_EL2_SRT_MASK        (0x1f << ESR_EL2_SRT_SHIFT)
+#define ESR_EL2_SF              (1 << 15)
+#define ESR_EL2_AR              (1 << 14)
+#define ESR_EL2_EA              (1 << 9)
+#define ESR_EL2_CM              (1 << 8)
+#define ESR_EL2_S1PTW           (1 << 7)
+#define ESR_EL2_WNR             (1 << 6)
+#define ESR_EL2_FSC             (0x3f)
+#define ESR_EL2_FSC_TYPE        (0x3c)
+
+#define ESR_EL2_CV_SHIFT        (24)
+#define ESR_EL2_CV              (1U << ESR_EL2_CV_SHIFT)
+#define ESR_EL2_COND_SHIFT      (20)
+#define ESR_EL2_COND            (0xfU << ESR_EL2_COND_SHIFT)
+
+
+#define FSC_FAULT       (0x04)
+#define FSC_PERM        (0x0c)
+
+/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
+#define HPFAR_MASK      (~0xFUL)
+
+#define ESR_EL2_EC_UNKNOWN      (0x00)
+#define ESR_EL2_EC_WFI          (0x01)
+#define ESR_EL2_EC_CP15_32      (0x03)
+#define ESR_EL2_EC_CP15_64      (0x04)
+#define ESR_EL2_EC_CP14_MR      (0x05)
+#define ESR_EL2_EC_CP14_LS      (0x06)
+#define ESR_EL2_EC_FP_ASIMD     (0x07)
+#define ESR_EL2_EC_CP10_ID      (0x08)
+#define ESR_EL2_EC_CP14_64      (0x0C)
+#define ESR_EL2_EC_ILL_ISS      (0x0E)
+#define ESR_EL2_EC_SVC32        (0x11)
+#define ESR_EL2_EC_HVC32        (0x12)
+#define ESR_EL2_EC_SMC32        (0x13)
+#define ESR_EL2_EC_SVC64        (0x15)
+#define ESR_EL2_EC_HVC64        (0x16)
+#define ESR_EL2_EC_SMC64        (0x17)
+#define ESR_EL2_EC_SYS64        (0x18)
+#define ESR_EL2_EC_IABT         (0x20)
+#define ESR_EL2_EC_IABT_HYP     (0x21)
+#define ESR_EL2_EC_PC_ALIGN     (0x22)
+#define ESR_EL2_EC_DABT         (0x24)
+#define ESR_EL2_EC_DABT_HYP     (0x25)
+#define ESR_EL2_EC_SP_ALIGN     (0x26)
+#define ESR_EL2_EC_FP_EXC32     (0x28)
+#define ESR_EL2_EC_FP_EXC64     (0x2C)
+#define ESR_EL2_EC_SERRROR      (0x2F)
+#define ESR_EL2_EC_BREAKPT      (0x30)
+#define ESR_EL2_EC_BREAKPT_HYP  (0x31)
+#define ESR_EL2_EC_SOFTSTP      (0x32)
+#define ESR_EL2_EC_SOFTSTP_HYP  (0x33)
+#define ESR_EL2_EC_WATCHPT      (0x34)
+#define ESR_EL2_EC_WATCHPT_HYP  (0x35)
+#define ESR_EL2_EC_BKPT32       (0x38)
+#define ESR_EL2_EC_VECTOR32     (0x3A)
+#define ESR_EL2_EC_BRK64        (0x3C)
+
+#define ESR_EL2_EC_xABT_xFSR_EXTABT     0x10
+
+#endif /* __ARM64_KVM_ARM_H__ */
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
new file mode 100644
index 000000000000..c92de4163eba
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_ASM_H__
+#define __ARM_KVM_ASM_H__
+
+/*
+ * 0 is reserved as an invalid value.
+ * Order *must* be kept in sync with the hyp switch code.
+ */
+#define MPIDR_EL1       1       /* MultiProcessor Affinity Register */
+#define CSSELR_EL1      2       /* Cache Size Selection Register */
+#define SCTLR_EL1       3       /* System Control Register */
+#define ACTLR_EL1       4       /* Auxilliary Control Register */
+#define CPACR_EL1       5       /* Coprocessor Access Control */
+#define TTBR0_EL1       6       /* Translation Table Base Register 0 */
+#define TTBR1_EL1       7       /* Translation Table Base Register 1 */
+#define TCR_EL1         8       /* Translation Control Register */
+#define ESR_EL1         9       /* Exception Syndrome Register */
+#define AFSR0_EL1       10      /* Auxilary Fault Status Register 0 */
+#define AFSR1_EL1       11      /* Auxilary Fault Status Register 1 */
+#define FAR_EL1         12      /* Fault Address Register */
+#define MAIR_EL1        13      /* Memory Attribute Indirection Register */
+#define VBAR_EL1        14      /* Vector Base Address Register */
+#define CONTEXTIDR_EL1  15      /* Context ID Register */
+#define TPIDR_EL0       16      /* Thread ID, User R/W */
+#define TPIDRRO_EL0     17      /* Thread ID, User R/O */
+#define TPIDR_EL1       18      /* Thread ID, Privileged */
+#define AMAIR_EL1       19      /* Aux Memory Attribute Indirection Register */
+#define CNTKCTL_EL1     20      /* Timer Control Register (EL1) */
+/* 32bit specific registers. Keep them at the end of the range */
+#define DACR32_EL2      21      /* Domain Access Control Register */
+#define IFSR32_EL2      22      /* Instruction Fault Status Register */
+#define FPEXC32_EL2     23      /* Floating-Point Exception Control Register */
+#define DBGVCR32_EL2    24      /* Debug Vector Catch Register */
+#define TEECR32_EL1     25      /* ThumbEE Configuration Register */
+#define TEEHBR32_EL1    26      /* ThumbEE Handler Base Register */
+#define NR_SYS_REGS     27
+
+/* 32bit mapping */
+#define c0_MPIDR        (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
+#define c0_CSSELR       (CSSELR_EL1 * 2)/* Cache Size Selection Register */
+#define c1_SCTLR        (SCTLR_EL1 * 2) /* System Control Register */
+#define c1_ACTLR        (ACTLR_EL1 * 2) /* Auxiliary Control Register */
+#define c1_CPACR        (CPACR_EL1 * 2) /* Coprocessor Access Control */
+#define c2_TTBR0        (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
+#define c2_TTBR0_high   (c2_TTBR0 + 1)  /* TTBR0 top 32 bits */
+#define c2_TTBR1        (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
+#define c2_TTBR1_high   (c2_TTBR1 + 1)  /* TTBR1 top 32 bits */
+#define c2_TTBCR        (TCR_EL1 * 2)   /* Translation Table Base Control R. */
+#define c3_DACR         (DACR32_EL2 * 2)/* Domain Access Control Register */
+#define c5_DFSR         (ESR_EL1 * 2)   /* Data Fault Status Register */
+#define c5_IFSR         (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
+#define c5_ADFSR        (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
+#define c5_AIFSR        (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
+#define c6_DFAR         (FAR_EL1 * 2)   /* Data Fault Address Register */
+#define c6_IFAR         (c6_DFAR + 1)   /* Instruction Fault Address Register */
+#define c10_PRRR        (MAIR_EL1 * 2)  /* Primary Region Remap Register */
+#define c10_NMRR        (c10_PRRR + 1)  /* Normal Memory Remap Register */
+#define c12_VBAR        (VBAR_EL1 * 2)  /* Vector Base Address Register */
+#define c13_CID         (CONTEXTIDR_EL1 * 2)    /* Context ID Register */
+#define c13_TID_URW     (TPIDR_EL0 * 2) /* Thread ID, User R/W */
+#define c13_TID_URO     (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
+#define c13_TID_PRIV    (TPIDR_EL1 * 2) /* Thread ID, Privileged */
+#define c10_AMAIR       (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
+#define c14_CNTKCTL     (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
+#define NR_CP15_REGS    (NR_SYS_REGS * 2)
+
+#define ARM_EXCEPTION_IRQ         0
+#define ARM_EXCEPTION_TRAP        1
+
+#ifndef __ASSEMBLY__
+struct kvm;
+struct kvm_vcpu;
+
+extern char __kvm_hyp_init[];
+extern char __kvm_hyp_init_end[];
+
+extern char __kvm_hyp_vector[];
+
+extern char __kvm_hyp_code_start[];
+extern char __kvm_hyp_code_end[];
+
+extern void __kvm_flush_vm_context(void);
+extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+
+extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+#endif
+
+#endif /* __ARM_KVM_ASM_H__ */
diff --git a/arch/arm64/include/asm/kvm_coproc.h b/arch/arm64/include/asm/kvm_coproc.h
new file mode 100644
index 000000000000..9a59301cd014
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_coproc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_coproc.h
+ * Copyright (C) 2012 Rusty Russell IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_COPROC_H__
+#define __ARM64_KVM_COPROC_H__
+
+#include <linux/kvm_host.h>
+
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu);
+
+struct kvm_sys_reg_table {
+        const struct sys_reg_desc *table;
+        size_t num;
+};
+
+struct kvm_sys_reg_target_table {
+        struct kvm_sys_reg_table table64;
+        struct kvm_sys_reg_table table32;
+};
+
+void kvm_register_target_sys_reg_table(unsigned int target,
+                                       struct kvm_sys_reg_target_table *table);
+
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+#define kvm_coproc_table_init kvm_sys_reg_table_init
+void kvm_sys_reg_table_init(void);
+
+struct kvm_one_reg;
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices);
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_COPROC_H__ */
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
new file mode 100644
index 000000000000..eec073875218
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/kvm_emulate.h
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_EMULATE_H__
+#define __ARM64_KVM_EMULATE_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmio.h>
+#include <asm/ptrace.h>
+
+unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num);
+unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu);
+
+bool kvm_condition_valid32(const struct kvm_vcpu *vcpu);
+void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr);
+
+void kvm_inject_undefined(struct kvm_vcpu *vcpu);
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr);
+
+static inline unsigned long *vcpu_pc(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pc;
+}
+
+static inline unsigned long *vcpu_elr_el1(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->elr_el1;
+}
+
+static inline unsigned long *vcpu_cpsr(const struct kvm_vcpu *vcpu)
+{
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
+}
+
+static inline bool vcpu_mode_is_32bit(const struct kvm_vcpu *vcpu)
+{
+        return !!(*vcpu_cpsr(vcpu) & PSR_MODE32_BIT);
+}
+
+static inline bool kvm_condition_valid(const struct kvm_vcpu *vcpu)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return kvm_condition_valid32(vcpu);
+
+        return true;
+}
+
+static inline void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                kvm_skip_instr32(vcpu, is_wide_instr);
+        else
+                *vcpu_pc(vcpu) += 4;
+}
+
+static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
+{
+        *vcpu_cpsr(vcpu) |= COMPAT_PSR_T_BIT;
+}
+
+static inline unsigned long *vcpu_reg(const struct kvm_vcpu *vcpu, u8 reg_num)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return vcpu_reg32(vcpu, reg_num);
+
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.regs[reg_num];
+}
+
+/* Get vcpu SPSR for current mode */
+static inline unsigned long *vcpu_spsr(const struct kvm_vcpu *vcpu)
+{
+        if (vcpu_mode_is_32bit(vcpu))
+                return vcpu_spsr32(vcpu);
+
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[KVM_SPSR_EL1];
+}
+
+static inline bool vcpu_mode_priv(const struct kvm_vcpu *vcpu)
+{
+        u32 mode = *vcpu_cpsr(vcpu) & PSR_MODE_MASK;
+
+        if (vcpu_mode_is_32bit(vcpu))
+                return mode > COMPAT_PSR_MODE_USR;
+
+        return mode != PSR_MODE_EL0t;
+}
+
+static inline u32 kvm_vcpu_get_hsr(const struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.esr_el2;
+}
+
+static inline unsigned long kvm_vcpu_get_hfar(const struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.fault.far_el2;
+}
+
+static inline phys_addr_t kvm_vcpu_get_fault_ipa(const struct kvm_vcpu *vcpu)
+{
+        return ((phys_addr_t)vcpu->arch.fault.hpfar_el2 & HPFAR_MASK) << 8;
+}
+
+static inline bool kvm_vcpu_dabt_isvalid(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_ISV);
+}
+
+static inline bool kvm_vcpu_dabt_iswrite(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_WNR);
+}
+
+static inline bool kvm_vcpu_dabt_issext(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SSE);
+}
+
+static inline int kvm_vcpu_dabt_get_rd(const struct kvm_vcpu *vcpu)
+{
+        return (kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SRT_MASK) >> ESR_EL2_SRT_SHIFT;
+}
+
+static inline bool kvm_vcpu_dabt_isextabt(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_EA);
+}
+
+static inline bool kvm_vcpu_dabt_iss1tw(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_S1PTW);
+}
+
+static inline int kvm_vcpu_dabt_get_as(const struct kvm_vcpu *vcpu)
+{
+        return 1 << ((kvm_vcpu_get_hsr(vcpu) & ESR_EL2_SAS) >> ESR_EL2_SAS_SHIFT);
+}
+
+/* This one is not specific to Data Abort */
+static inline bool kvm_vcpu_trap_il_is32bit(const struct kvm_vcpu *vcpu)
+{
+        return !!(kvm_vcpu_get_hsr(vcpu) & ESR_EL2_IL);
+}
+
+static inline u8 kvm_vcpu_trap_get_class(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) >> ESR_EL2_EC_SHIFT;
+}
+
+static inline bool kvm_vcpu_trap_is_iabt(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_trap_get_class(vcpu) == ESR_EL2_EC_IABT;
+}
+
+static inline u8 kvm_vcpu_trap_get_fault(const struct kvm_vcpu *vcpu)
+{
+        return kvm_vcpu_get_hsr(vcpu) & ESR_EL2_FSC_TYPE;
+}
+
+#endif /* __ARM64_KVM_EMULATE_H__ */
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
new file mode 100644
index 000000000000..644d73956864
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/asm/kvm_host.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_HOST_H__
+#define __ARM64_KVM_HOST_H__
+
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_mmio.h>
+
+#define KVM_MAX_VCPUS 4
+#define KVM_USER_MEM_SLOTS 32
+#define KVM_PRIVATE_MEM_SLOTS 4
+#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
+
+#include <kvm/arm_vgic.h>
+#include <kvm/arm_arch_timer.h>
+
+#define KVM_VCPU_MAX_FEATURES 2
+
+/* We don't currently support large pages. */
+#define KVM_HPAGE_GFN_SHIFT(x)  0
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
+
+struct kvm_vcpu;
+int kvm_target_cpu(void);
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
+int kvm_arch_dev_ioctl_check_extension(long ext);
+
+struct kvm_arch {
+        /* The VMID generation used for the virt. memory system */
+        u64    vmid_gen;
+        u32    vmid;
+
+        /* 1-level 2nd stage table and lock */
+        spinlock_t pgd_lock;
+        pgd_t *pgd;
+
+        /* VTTBR value associated with above pgd and vmid */
+        u64    vttbr;
+
+        /* Interrupt controller */
+        struct vgic_dist        vgic;
+
+        /* Timer */
+        struct arch_timer_kvm   timer;
+};
+
+#define KVM_NR_MEM_OBJS     40
+
+/*
+ * We don't want allocation failures within the mmu code, so we preallocate
+ * enough memory for a single page fault in a cache.
+ */
+struct kvm_mmu_memory_cache {
+        int nobjs;
+        void *objects[KVM_NR_MEM_OBJS];
+};
+
+struct kvm_vcpu_fault_info {
+        u32 esr_el2;            /* Hyp Syndrom Register */
+        u64 far_el2;            /* Hyp Fault Address Register */
+        u64 hpfar_el2;          /* Hyp IPA Fault Address Register */
+};
+
+struct kvm_cpu_context {
+        struct kvm_regs gp_regs;
+        union {
+                u64 sys_regs[NR_SYS_REGS];
+                u32 cp15[NR_CP15_REGS];
+        };
+};
+
+typedef struct kvm_cpu_context kvm_cpu_context_t;
+
+struct kvm_vcpu_arch {
+        struct kvm_cpu_context ctxt;
+
+        /* HYP configuration */
+        u64 hcr_el2;
+
+        /* Exception Information */
+        struct kvm_vcpu_fault_info fault;
+
+        /* Pointer to host CPU context */
+        kvm_cpu_context_t *host_cpu_context;
+
+        /* VGIC state */
+        struct vgic_cpu vgic_cpu;
+        struct arch_timer_cpu timer_cpu;
+
+        /*
+         * Anything that is not used directly from assembly code goes
+         * here.
+         */
+        /* dcache set/way operation pending */
+        int last_pcpu;
+        cpumask_t require_dcache_flush;
+
+        /* Don't run the guest */
+        bool pause;
+
+        /* IO related fields */
+        struct kvm_decode mmio_decode;
+
+        /* Interrupt related fields */
+        u64 irq_lines;          /* IRQ and FIQ levels */
+
+        /* Cache some mmu pages needed inside spinlock regions */
+        struct kvm_mmu_memory_cache mmu_page_cache;
+
+        /* Target CPU and feature flags */
+        u32 target;
+        DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
+
+        /* Detect first run of a vcpu */
+        bool has_run_once;
+};
+
+#define vcpu_gp_regs(v)         (&(v)->arch.ctxt.gp_regs)
+#define vcpu_sys_reg(v,r)       ((v)->arch.ctxt.sys_regs[(r)])
+#define vcpu_cp15(v,r)          ((v)->arch.ctxt.cp15[(r)])
+
+struct kvm_vm_stat {
+        u32 remote_tlb_flush;
+};
+
+struct kvm_vcpu_stat {
+        u32 halt_wakeup;
+};
+
+struct kvm_vcpu_init;
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init);
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
+struct kvm_one_reg;
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
+
+#define KVM_ARCH_WANT_MMU_NOTIFIER
+struct kvm;
+int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
+int kvm_unmap_hva_range(struct kvm *kvm,
+                        unsigned long start, unsigned long end);
+void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
+
+/* We do not have shadow page tables, hence the empty hooks */
+static inline int kvm_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+
+static inline int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
+{
+        return 0;
+}
+
+struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
+struct kvm_vcpu __percpu **kvm_get_running_vcpus(void);
+
+u64 kvm_call_hyp(void *hypfn, ...);
+
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                int exception_index);
+
+int kvm_perf_init(void);
+int kvm_perf_teardown(void);
+
+static inline void __cpu_init_hyp_mode(phys_addr_t boot_pgd_ptr,
+                                       phys_addr_t pgd_ptr,
+                                       unsigned long hyp_stack_ptr,
+                                       unsigned long vector_ptr)
+{
+        /*
+         * Call initialization code, and switch to the full blown
+         * HYP code.
+         */
+        kvm_call_hyp((void *)boot_pgd_ptr, pgd_ptr,
+                     hyp_stack_ptr, vector_ptr);
+}
+
+#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmio.h b/arch/arm64/include/asm/kvm_mmio.h
new file mode 100644
index 000000000000..fc2f689c0694
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmio.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMIO_H__
+#define __ARM64_KVM_MMIO_H__
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+
+/*
+ * This is annoying. The mmio code requires this, even if we don't
+ * need any decoding. To be fixed.
+ */
+struct kvm_decode {
+        unsigned long rt;
+        bool sign_extend;
+};
+
+/*
+ * The in-kernel MMIO emulation code wants to use a copy of run->mmio,
+ * which is an anonymous type. Use our own type instead.
+ */
+struct kvm_exit_mmio {
+        phys_addr_t     phys_addr;
+        u8              data[8];
+        u32             len;
+        bool            is_write;
+};
+
+static inline void kvm_prepare_mmio(struct kvm_run *run,
+                                    struct kvm_exit_mmio *mmio)
+{
+        run->mmio.phys_addr     = mmio->phys_addr;
+        run->mmio.len           = mmio->len;
+        run->mmio.is_write      = mmio->is_write;
+        memcpy(run->mmio.data, mmio->data, mmio->len);
+        run->exit_reason        = KVM_EXIT_MMIO;
+}
+
+int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                 phys_addr_t fault_ipa);
+
+#endif  /* __ARM64_KVM_MMIO_H__ */
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
new file mode 100644
index 000000000000..efe609c6a3c9
--- /dev/null
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_MMU_H__
+#define __ARM64_KVM_MMU_H__
+
+#include <asm/page.h>
+#include <asm/memory.h>
+
+/*
+ * As we only have the TTBR0_EL2 register, we cannot express
+ * "negative" addresses. This makes it impossible to directly share
+ * mappings with the kernel.
+ *
+ * Instead, give the HYP mode its own VA region at a fixed offset from
+ * the kernel by just masking the top bits (which are all ones for a
+ * kernel address).
+ */
+#define HYP_PAGE_OFFSET_SHIFT   VA_BITS
+#define HYP_PAGE_OFFSET_MASK    ((UL(1) << HYP_PAGE_OFFSET_SHIFT) - 1)
+#define HYP_PAGE_OFFSET         (PAGE_OFFSET & HYP_PAGE_OFFSET_MASK)
+
+/*
+ * Our virtual mapping for the idmap-ed MMU-enable code. Must be
+ * shared across all the page-tables. Conveniently, we use the last
+ * possible page, where no kernel mapping will ever exist.
+ */
+#define TRAMPOLINE_VA           (HYP_PAGE_OFFSET_MASK & PAGE_MASK)
+
+#ifdef __ASSEMBLY__
+
+/*
+ * Convert a kernel VA into a HYP VA.
+ * reg: VA to be converted.
+ */
+.macro kern_hyp_va      reg
+        and     \reg, \reg, #HYP_PAGE_OFFSET_MASK
+.endm
+
+#else
+
+#include <asm/cachetype.h>
+#include <asm/cacheflush.h>
+
+#define KERN_TO_HYP(kva)        ((unsigned long)kva - PAGE_OFFSET + HYP_PAGE_OFFSET)
+
+/*
+ * Align KVM with the kernel's view of physical memory. Should be
+ * 40bit IPA, with PGD being 8kB aligned in the 4KB page configuration.
+ */
+#define KVM_PHYS_SHIFT  PHYS_MASK_SHIFT
+#define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
+#define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
+
+/* Make sure we get the right size, and thus the right alignment */
+#define PTRS_PER_S2_PGD (1 << (KVM_PHYS_SHIFT - PGDIR_SHIFT))
+#define S2_PGD_ORDER    get_order(PTRS_PER_S2_PGD * sizeof(pgd_t))
+
+int create_hyp_mappings(void *from, void *to);
+int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
+void free_boot_hyp_pgd(void);
+void free_hyp_pgds(void);
+
+int kvm_alloc_stage2_pgd(struct kvm *kvm);
+void kvm_free_stage2_pgd(struct kvm *kvm);
+int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
+                          phys_addr_t pa, unsigned long size);
+
+int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
+
+void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
+
+phys_addr_t kvm_mmu_get_httbr(void);
+phys_addr_t kvm_mmu_get_boot_httbr(void);
+phys_addr_t kvm_get_idmap_vector(void);
+int kvm_mmu_init(void);
+void kvm_clear_hyp_idmap(void);
+
+#define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
+
+static inline bool kvm_is_write_fault(unsigned long esr)
+{
+        unsigned long esr_ec = esr >> ESR_EL2_EC_SHIFT;
+
+        if (esr_ec == ESR_EL2_EC_IABT)
+                return false;
+
+        if ((esr & ESR_EL2_ISV) && !(esr & ESR_EL2_WNR))
+                return false;
+
+        return true;
+}
+
+static inline void kvm_clean_dcache_area(void *addr, size_t size) {}
+static inline void kvm_clean_pgd(pgd_t *pgd) {}
+static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
+static inline void kvm_clean_pte(pte_t *pte) {}
+static inline void kvm_clean_pte_entry(pte_t *pte) {}
+
+static inline void kvm_set_s2pte_writable(pte_t *pte)
+{
+        pte_val(*pte) |= PTE_S2_RDWR;
+}
+
+struct kvm;
+
+static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+        if (!icache_is_aliasing()) {            /* PIPT */
+                unsigned long hva = gfn_to_hva(kvm, gfn);
+                flush_icache_range(hva, hva + PAGE_SIZE);
+        } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
+                /* any kind of VIPT cache */
+                __flush_icache_all();
+        }
+}
+
+#define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARM64_KVM_MMU_H__ */
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm64/include/asm/kvm_psci.h
index 7b380b31bd0e..e301a4816355 100644
--- a/arch/arm/mach-msm/gpiomux-8x60.c
+++ b/arch/arm64/include/asm/kvm_psci.h
@@ -1,8 +1,10 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -10,10 +12,12 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
-#include "gpiomux.h"
 
-struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
+#ifndef __ARM64_KVM_PSCI_H__
+#define __ARM64_KVM_PSCI_H__
+
+bool kvm_psci_call(struct kvm_vcpu *vcpu);
+
+#endif /* __ARM64_KVM_PSCI_H__ */
diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
index 381f556b664e..20925bcf4e2a 100644
--- a/arch/arm64/include/asm/memory.h
+++ b/arch/arm64/include/asm/memory.h
@@ -90,6 +90,12 @@
 #define MT_NORMAL_NC            3
 #define MT_NORMAL               4
 
+/*
+ * Memory types for Stage-2 translation
+ */
+#define MT_S2_NORMAL            0xf
+#define MT_S2_DEVICE_nGnRE      0x1
+
 #ifndef __ASSEMBLY__
 
 extern phys_addr_t              memstart_addr;
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index e2bc385adb6b..a9eee33dfa62 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -151,12 +151,6 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
 {
         unsigned int cpu = smp_processor_id();
 
-#ifdef CONFIG_SMP
-        /* check for possible thread migration */
-        if (!cpumask_empty(mm_cpumask(next)) &&
-            !cpumask_test_cpu(cpu, mm_cpumask(next)))
-                __flush_icache_all();
-#endif
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next)
                 check_and_switch_context(next, tsk);
 }
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 75fd13d289b9..e182a356c979 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -25,16 +25,27 @@
 /*
  * Hardware page table definitions.
  *
+ * Level 1 descriptor (PUD).
+ */
+
+#define PUD_TABLE_BIT           (_AT(pgdval_t, 1) << 1)
+
+/*
  * Level 2 descriptor (PMD).
  */
 #define PMD_TYPE_MASK           (_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
 #define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
 #define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
+#define PMD_TABLE_BIT           (_AT(pmdval_t, 1) << 1)
 
 /*
  * Section
  */
+#define PMD_SECT_VALID          (_AT(pmdval_t, 1) << 0)
+#define PMD_SECT_PROT_NONE      (_AT(pmdval_t, 1) << 2)
+#define PMD_SECT_USER           (_AT(pmdval_t, 1) << 6)         /* AP[1] */
+#define PMD_SECT_RDONLY         (_AT(pmdval_t, 1) << 7)         /* AP[2] */
 #define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
 #define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
 #define PMD_SECT_NG             (_AT(pmdval_t, 1) << 11)
@@ -53,6 +64,7 @@
 #define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
 #define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
 #define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
+#define PTE_TABLE_BIT           (_AT(pteval_t, 1) << 1)
 #define PTE_USER                (_AT(pteval_t, 1) << 6)         /* AP[1] */
 #define PTE_RDONLY              (_AT(pteval_t, 1) << 7)         /* AP[2] */
 #define PTE_SHARED              (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
@@ -68,6 +80,24 @@
 #define PTE_ATTRINDX_MASK       (_AT(pteval_t, 7) << 2)
 
 /*
+ * 2nd stage PTE definitions
+ */
+#define PTE_S2_RDONLY           (_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
+#define PTE_S2_RDWR             (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
+
+/*
+ * Memory Attribute override for Stage-2 (MemAttr[3:0])
+ */
+#define PTE_S2_MEMATTR(t)       (_AT(pteval_t, (t)) << 2)
+#define PTE_S2_MEMATTR_MASK     (_AT(pteval_t, 0xf) << 2)
+
+/*
+ * EL2/HYP PTE/PMD definitions
+ */
+#define PMD_HYP                 PMD_SECT_USER
+#define PTE_HYP                 PTE_USER
+
+/*
  * 40-bit physical address supported.
  */
 #define PHYS_MASK_SHIFT         (40)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index e333a243bfcc..f0bebc5e22cd 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -25,8 +25,8 @@
  * Software defined PTE bits definition.
  */
 #define PTE_VALID               (_AT(pteval_t, 1) << 0)
-#define PTE_PROT_NONE           (_AT(pteval_t, 1) << 1) /* only when !PTE_VALID */
-#define PTE_FILE                (_AT(pteval_t, 1) << 2) /* only when !pte_present() */
+#define PTE_PROT_NONE           (_AT(pteval_t, 1) << 2) /* only when !PTE_VALID */
+#define PTE_FILE                (_AT(pteval_t, 1) << 3) /* only when !pte_present() */
 #define PTE_DIRTY               (_AT(pteval_t, 1) << 55)
 #define PTE_SPECIAL             (_AT(pteval_t, 1) << 56)
 
@@ -66,7 +66,7 @@ extern pgprot_t pgprot_default;
 
 #define _MOD_PROT(p, b)         __pgprot_modify(p, 0, b)
 
-#define PAGE_NONE               __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE)
+#define PAGE_NONE               __pgprot_modify(pgprot_default, PTE_TYPE_MASK, PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
 #define PAGE_SHARED             _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define PAGE_SHARED_EXEC        _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN)
 #define PAGE_COPY               _MOD_PROT(pgprot_default, PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
@@ -76,7 +76,13 @@ extern pgprot_t pgprot_default;
 #define PAGE_KERNEL             _MOD_PROT(pgprot_default, PTE_PXN | PTE_UXN | PTE_DIRTY)
 #define PAGE_KERNEL_EXEC        _MOD_PROT(pgprot_default, PTE_UXN | PTE_DIRTY)
 
-#define __PAGE_NONE             __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE)
+#define PAGE_HYP                _MOD_PROT(pgprot_default, PTE_HYP)
+#define PAGE_HYP_DEVICE         __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
+
+#define PAGE_S2                 __pgprot_modify(pgprot_default, PTE_S2_MEMATTR_MASK, PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
+#define PAGE_S2_DEVICE          __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDWR | PTE_UXN)
+
+#define __PAGE_NONE             __pgprot(((_PAGE_DEFAULT) & ~PTE_TYPE_MASK) | PTE_PROT_NONE | PTE_RDONLY | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED           __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
 #define __PAGE_SHARED_EXEC      __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
 #define __PAGE_COPY             __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_RDONLY)
@@ -119,7 +125,7 @@ extern struct page *empty_zero_page;
 #define pte_none(pte)           (!pte_val(pte))
 #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
-#define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + __pte_index(addr))
+#define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + pte_index(addr))
 
 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
@@ -173,12 +179,76 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 /*
  * Huge pte definitions.
  */
-#define pte_huge(pte)           ((pte_val(pte) & PTE_TYPE_MASK) == PTE_TYPE_HUGEPAGE)
-#define pte_mkhuge(pte)         (__pte((pte_val(pte) & ~PTE_TYPE_MASK) | PTE_TYPE_HUGEPAGE))
+#define pte_huge(pte)           (!(pte_val(pte) & PTE_TABLE_BIT))
+#define pte_mkhuge(pte)         (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
+
+/*
+ * Hugetlb definitions.
+ */
+#define HUGE_MAX_HSTATE         2
+#define HPAGE_SHIFT             PMD_SHIFT
+#define HPAGE_SIZE              (_AC(1, UL) << HPAGE_SHIFT)
+#define HPAGE_MASK              (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER      (HPAGE_SHIFT - PAGE_SHIFT)
 
 #define __HAVE_ARCH_PTE_SPECIAL
 
 /*
+ * Software PMD bits for THP
+ */
+
+#define PMD_SECT_DIRTY          (_AT(pmdval_t, 1) << 55)
+#define PMD_SECT_SPLITTING      (_AT(pmdval_t, 1) << 57)
+
+/*
+ * THP definitions.
+ */
+#define pmd_young(pmd)          (pmd_val(pmd) & PMD_SECT_AF)
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)          (!(pmd_val(pmd) & PMD_SECT_RDONLY))
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_trans_huge(pmd)     (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
+#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
+#endif
+
+#define PMD_BIT_FUNC(fn,op) \
+static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
+
+PMD_BIT_FUNC(wrprotect, |= PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkold,     &= ~PMD_SECT_AF);
+PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
+PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
+PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
+PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);
+PMD_BIT_FUNC(mknotpresent, &= ~PMD_TYPE_MASK);
+
+#define pmd_mkhuge(pmd)         (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
+
+#define pmd_pfn(pmd)            (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
+#define pfn_pmd(pfn,prot)       (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+#define mk_pmd(page,prot)       pfn_pmd(page_to_pfn(page),prot)
+
+#define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
+
+static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+        const pmdval_t mask = PMD_SECT_USER | PMD_SECT_PXN | PMD_SECT_UXN |
+                              PMD_SECT_RDONLY | PMD_SECT_PROT_NONE |
+                              PMD_SECT_VALID;
+        pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
+        return pmd;
+}
+
+#define set_pmd_at(mm, addr, pmdp, pmd) set_pmd(pmdp, pmd)
+
+static inline int has_transparent_hugepage(void)
+{
+        return 1;
+}
+
+/*
  * Mark the prot value as uncacheable and unbufferable.
  */
 #define pgprot_noncached(prot) \
@@ -197,6 +267,12 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 
 #define pmd_bad(pmd)            (!(pmd_val(pmd) & 2))
 
+#define pmd_table(pmd)          ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                 PMD_TYPE_TABLE)
+#define pmd_sect(pmd)           ((pmd_val(pmd) & PMD_TYPE_MASK) == \
+                                 PMD_TYPE_SECT)
+
+
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
         *pmdp = pmd;
@@ -263,7 +339,7 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 #endif
 
 /* Find an entry in the third-level page table.. */
-#define __pte_index(addr)       (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_index(addr)         (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 {
@@ -281,12 +357,12 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 
 /*
  * Encode and decode a swap entry:
- *      bits 0-1:       present (must be zero)
- *      bit  2:         PTE_FILE
- *      bits 3-8:       swap type
+ *      bits 0, 2:      present (must both be zero)
+ *      bit  3:         PTE_FILE
+ *      bits 4-8:       swap type
  *      bits 9-63:      swap offset
  */
-#define __SWP_TYPE_SHIFT        3
+#define __SWP_TYPE_SHIFT        4
 #define __SWP_TYPE_BITS         6
 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
@@ -306,27 +382,20 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
 
 /*
  * Encode and decode a file entry:
- *      bits 0-1:       present (must be zero)
- *      bit  2:         PTE_FILE
- *      bits 3-63:      file offset / PAGE_SIZE
+ *      bits 0, 2:      present (must both be zero)
+ *      bit  3:         PTE_FILE
+ *      bits 4-63:      file offset / PAGE_SIZE
  */
 #define pte_file(pte)           (pte_val(pte) & PTE_FILE)
-#define pte_to_pgoff(x)         (pte_val(x) >> 3)
-#define pgoff_to_pte(x)         __pte(((x) << 3) | PTE_FILE)
+#define pte_to_pgoff(x)         (pte_val(x) >> 4)
+#define pgoff_to_pte(x)         __pte(((x) << 4) | PTE_FILE)
 
-#define PTE_FILE_MAX_BITS       61
+#define PTE_FILE_MAX_BITS       60
 
 extern int kern_addr_valid(unsigned long addr);
 
 #include <asm-generic/pgtable.h>
 
-/*
- * remap a physical page `pfn' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_pfn_range(vma,from,pfn,size,prot) \
-                remap_pfn_range(vma, from, pfn, size, prot)
-
 #define pgtable_cache_init() do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index 41a71ee4c3df..0dacbbf9458b 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -171,7 +171,5 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define profile_pc(regs) instruction_pointer(regs)
 #endif
 
-extern int aarch32_break_trap(struct pt_regs *regs);
-
 #endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h
index 7065e920149d..0defa0728a9b 100644
--- a/arch/arm64/include/asm/spinlock.h
+++ b/arch/arm64/include/asm/spinlock.h
@@ -59,9 +59,10 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
         unsigned int tmp;
 
         asm volatile(
-        "       ldaxr   %w0, %1\n"
+        "2:     ldaxr   %w0, %1\n"
         "       cbnz    %w0, 1f\n"
         "       stxr    %w0, %w2, %1\n"
+        "       cbnz    %w0, 2b\n"
         "1:\n"
         : "=&r" (tmp), "+Q" (lock->lock)
         : "r" (1)
diff --git a/arch/arm64/include/asm/sync_bitops.h b/arch/arm64/include/asm/sync_bitops.h
new file mode 100644
index 000000000000..8da0bf4f7659
--- /dev/null
+++ b/arch/arm64/include/asm/sync_bitops.h
@@ -0,0 +1,26 @@
+#ifndef __ASM_SYNC_BITOPS_H__
+#define __ASM_SYNC_BITOPS_H__
+
+#include <asm/bitops.h>
+#include <asm/cmpxchg.h>
+
+/* sync_bitops functions are equivalent to the SMP implementation of the
+ * original functions, independently from CONFIG_SMP being defined.
+ *
+ * We need them because _set_bit etc are not SMP safe if !CONFIG_SMP. But
+ * under Xen you might be communicating with a completely external entity
+ * who might be on another CPU (e.g. two uniprocessor guests communicating
+ * via event channels and grant tables). So we need a variant of the bit
+ * ops which are SMP safe even on a UP kernel.
+ */
+
+#define sync_set_bit(nr, p)            set_bit(nr, p)
+#define sync_clear_bit(nr, p)          clear_bit(nr, p)
+#define sync_change_bit(nr, p)         change_bit(nr, p)
+#define sync_test_and_set_bit(nr, p)   test_and_set_bit(nr, p)
+#define sync_test_and_clear_bit(nr, p) test_and_clear_bit(nr, p)
+#define sync_test_and_change_bit(nr, p)        test_and_change_bit(nr, p)
+#define sync_test_bit(nr, addr)                test_bit(nr, addr)
+#define sync_cmpxchg                   cmpxchg
+
+#endif
diff --git a/arch/arm64/include/asm/timex.h b/arch/arm64/include/asm/timex.h
index b24a31a7e2c9..81a076eb37fa 100644
--- a/arch/arm64/include/asm/timex.h
+++ b/arch/arm64/include/asm/timex.h
@@ -16,14 +16,14 @@
 #ifndef __ASM_TIMEX_H
 #define __ASM_TIMEX_H
 
+#include <asm/arch_timer.h>
+
 /*
  * Use the current timer as a cycle counter since this is what we use for
  * the delay loop.
  */
-#define get_cycles()    ({ cycles_t c; read_current_timer(&c); c; })
+#define get_cycles()    arch_counter_get_cntvct()
 
 #include <asm-generic/timex.h>
 
-#define ARCH_HAS_READ_CURRENT_TIMER
-
 #endif
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 654f0968030b..46b3beb4b773 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -187,4 +187,10 @@ static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 
 #define tlb_migrate_finish(mm)          do { } while (0)
 
+static inline void
+tlb_remove_pmd_tlb_entry(struct mmu_gather *tlb, pmd_t *pmdp, unsigned long addr)
+{
+        tlb_add_flush(tlb, addr);
+}
+
 #endif
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 122d6320f745..8b482035cfc2 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -117,6 +117,8 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         dsb();
 }
 
+#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
+
 #endif
 
 #endif
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 008f8481da65..edb3d5c73a32 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -166,7 +166,7 @@ do {									\
 
 #define get_user(x, ptr)                                                \
 ({                                                                      \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         access_ok(VERIFY_READ, (ptr), sizeof(*(ptr))) ?                 \
                 __get_user((x), (ptr)) :                                \
                 ((x) = 0, -EFAULT);                                     \
@@ -227,7 +227,7 @@ do {									\
 
 #define put_user(x, ptr)                                                \
 ({                                                                      \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         access_ok(VERIFY_WRITE, (ptr), sizeof(*(ptr))) ?                \
                 __put_user((x), (ptr)) :                                \
                 -EFAULT;                                                \
diff --git a/arch/arm64/include/asm/xen/events.h b/arch/arm64/include/asm/xen/events.h
new file mode 100644
index 000000000000..86553213c132
--- /dev/null
+++ b/arch/arm64/include/asm/xen/events.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_ARM64_XEN_EVENTS_H
+#define _ASM_ARM64_XEN_EVENTS_H
+
+#include <asm/ptrace.h>
+#include <asm/atomic.h>
+
+enum ipi_vector {
+        XEN_PLACEHOLDER_VECTOR,
+
+        /* Xen IPIs go here */
+        XEN_NR_IPIS,
+};
+
+static inline int xen_irqs_disabled(struct pt_regs *regs)
+{
+        return raw_irqs_disabled_flags((unsigned long) regs->pstate);
+}
+
+#define xchg_xen_ulong(ptr, val) xchg((ptr), (val))
+
+#endif /* _ASM_ARM64_XEN_EVENTS_H */
diff --git a/arch/arm64/include/asm/xen/hypercall.h b/arch/arm64/include/asm/xen/hypercall.h
new file mode 100644
index 000000000000..74b0c423ff5b
--- /dev/null
+++ b/arch/arm64/include/asm/xen/hypercall.h
@@ -0,0 +1 @@
+#include <../../arm/include/asm/xen/hypercall.h>
diff --git a/arch/arm64/include/asm/xen/hypervisor.h b/arch/arm64/include/asm/xen/hypervisor.h
new file mode 100644
index 000000000000..f263da8e8769
--- /dev/null
+++ b/arch/arm64/include/asm/xen/hypervisor.h
@@ -0,0 +1 @@
+#include <../../arm/include/asm/xen/hypervisor.h>
diff --git a/arch/arm64/include/asm/xen/interface.h b/arch/arm64/include/asm/xen/interface.h
new file mode 100644
index 000000000000..44457aebeed4
--- /dev/null
+++ b/arch/arm64/include/asm/xen/interface.h
@@ -0,0 +1 @@
+#include <../../arm/include/asm/xen/interface.h>
diff --git a/arch/arm64/include/asm/xen/page.h b/arch/arm64/include/asm/xen/page.h
new file mode 100644
index 000000000000..bed87ec36780
--- /dev/null
+++ b/arch/arm64/include/asm/xen/page.h
@@ -0,0 +1 @@
+#include <../../arm/include/asm/xen/page.h>
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
new file mode 100644
index 000000000000..5031f4263937
--- /dev/null
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/include/uapi/asm/kvm.h:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM_KVM_H__
+#define __ARM_KVM_H__
+
+#define KVM_SPSR_EL1    0
+#define KVM_SPSR_SVC    KVM_SPSR_EL1
+#define KVM_SPSR_ABT    1
+#define KVM_SPSR_UND    2
+#define KVM_SPSR_IRQ    3
+#define KVM_SPSR_FIQ    4
+#define KVM_NR_SPSR     5
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/ptrace.h>
+
+#define __KVM_HAVE_GUEST_DEBUG
+#define __KVM_HAVE_IRQ_LINE
+
+#define KVM_REG_SIZE(id)                                                \
+        (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
+
+struct kvm_regs {
+        struct user_pt_regs regs;       /* sp = sp_el0 */
+
+        __u64   sp_el1;
+        __u64   elr_el1;
+
+        __u64   spsr[KVM_NR_SPSR];
+
+        struct user_fpsimd_state fp_regs;
+};
+
+/* Supported Processor Types */
+#define KVM_ARM_TARGET_AEM_V8           0
+#define KVM_ARM_TARGET_FOUNDATION_V8    1
+#define KVM_ARM_TARGET_CORTEX_A57       2
+
+#define KVM_ARM_NUM_TARGETS             3
+
+/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
+#define KVM_ARM_DEVICE_TYPE_SHIFT       0
+#define KVM_ARM_DEVICE_TYPE_MASK        (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
+#define KVM_ARM_DEVICE_ID_SHIFT         16
+#define KVM_ARM_DEVICE_ID_MASK          (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
+
+/* Supported device IDs */
+#define KVM_ARM_DEVICE_VGIC_V2          0
+
+/* Supported VGIC address types  */
+#define KVM_VGIC_V2_ADDR_TYPE_DIST      0
+#define KVM_VGIC_V2_ADDR_TYPE_CPU       1
+
+#define KVM_VGIC_V2_DIST_SIZE           0x1000
+#define KVM_VGIC_V2_CPU_SIZE            0x2000
+
+#define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
+#define KVM_ARM_VCPU_EL1_32BIT          1 /* CPU running a 32bit VM */
+
+struct kvm_vcpu_init {
+        __u32 target;
+        __u32 features[7];
+};
+
+struct kvm_sregs {
+};
+
+struct kvm_fpu {
+};
+
+struct kvm_guest_debug_arch {
+};
+
+struct kvm_debug_exit_arch {
+};
+
+struct kvm_sync_regs {
+};
+
+struct kvm_arch_memory_slot {
+};
+
+/* If you need to interpret the index values, here is the key: */
+#define KVM_REG_ARM_COPROC_MASK         0x000000000FFF0000
+#define KVM_REG_ARM_COPROC_SHIFT        16
+
+/* Normal registers are mapped as coprocessor 16. */
+#define KVM_REG_ARM_CORE                (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_CORE_REG(name)      (offsetof(struct kvm_regs, name) / sizeof(__u32))
+
+/* Some registers need more space to represent values. */
+#define KVM_REG_ARM_DEMUX               (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM_DEMUX_ID_MASK       0x000000000000FF00
+#define KVM_REG_ARM_DEMUX_ID_SHIFT      8
+#define KVM_REG_ARM_DEMUX_ID_CCSIDR     (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
+#define KVM_REG_ARM_DEMUX_VAL_MASK      0x00000000000000FF
+#define KVM_REG_ARM_DEMUX_VAL_SHIFT     0
+
+/* AArch64 system registers */
+#define KVM_REG_ARM64_SYSREG            (0x0013 << KVM_REG_ARM_COPROC_SHIFT)
+#define KVM_REG_ARM64_SYSREG_OP0_MASK   0x000000000000c000
+#define KVM_REG_ARM64_SYSREG_OP0_SHIFT  14
+#define KVM_REG_ARM64_SYSREG_OP1_MASK   0x0000000000003800
+#define KVM_REG_ARM64_SYSREG_OP1_SHIFT  11
+#define KVM_REG_ARM64_SYSREG_CRN_MASK   0x0000000000000780
+#define KVM_REG_ARM64_SYSREG_CRN_SHIFT  7
+#define KVM_REG_ARM64_SYSREG_CRM_MASK   0x0000000000000078
+#define KVM_REG_ARM64_SYSREG_CRM_SHIFT  3
+#define KVM_REG_ARM64_SYSREG_OP2_MASK   0x0000000000000007
+#define KVM_REG_ARM64_SYSREG_OP2_SHIFT  0
+
+/* KVM_IRQ_LINE irq field index values */
+#define KVM_ARM_IRQ_TYPE_SHIFT          24
+#define KVM_ARM_IRQ_TYPE_MASK           0xff
+#define KVM_ARM_IRQ_VCPU_SHIFT          16
+#define KVM_ARM_IRQ_VCPU_MASK           0xff
+#define KVM_ARM_IRQ_NUM_SHIFT           0
+#define KVM_ARM_IRQ_NUM_MASK            0xffff
+
+/* irq_type field */
+#define KVM_ARM_IRQ_TYPE_CPU            0
+#define KVM_ARM_IRQ_TYPE_SPI            1
+#define KVM_ARM_IRQ_TYPE_PPI            2
+
+/* out-of-kernel GIC cpu interrupt injection irq_number field */
+#define KVM_ARM_IRQ_CPU_IRQ             0
+#define KVM_ARM_IRQ_CPU_FIQ             1
+
+/* Highest supported SPI, from VGIC_NR_IRQS */
+#define KVM_ARM_IRQ_GIC_MAX             127
+
+/* PSCI interface */
+#define KVM_PSCI_FN_BASE                0x95c1ba5e
+#define KVM_PSCI_FN(n)                  (KVM_PSCI_FN_BASE + (n))
+
+#define KVM_PSCI_FN_CPU_SUSPEND         KVM_PSCI_FN(0)
+#define KVM_PSCI_FN_CPU_OFF             KVM_PSCI_FN(1)
+#define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
+#define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
+
+#define KVM_PSCI_RET_SUCCESS            0
+#define KVM_PSCI_RET_NI                 ((unsigned long)-1)
+#define KVM_PSCI_RET_INVAL              ((unsigned long)-2)
+#define KVM_PSCI_RET_DENIED             ((unsigned long)-3)
+
+#endif
+
+#endif /* __ARM_KVM_H__ */
diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c
index a2a4d810bea3..49c162c03b69 100644
--- a/arch/arm64/kernel/asm-offsets.c
+++ b/arch/arm64/kernel/asm-offsets.c
@@ -104,5 +104,38 @@ int main(void)
   BLANK();
   DEFINE(TZ_MINWEST,            offsetof(struct timezone, tz_minuteswest));
   DEFINE(TZ_DSTTIME,            offsetof(struct timezone, tz_dsttime));
+  BLANK();
+#ifdef CONFIG_KVM_ARM_HOST
+  DEFINE(VCPU_CONTEXT,          offsetof(struct kvm_vcpu, arch.ctxt));
+  DEFINE(CPU_GP_REGS,           offsetof(struct kvm_cpu_context, gp_regs));
+  DEFINE(CPU_USER_PT_REGS,      offsetof(struct kvm_regs, regs));
+  DEFINE(CPU_FP_REGS,           offsetof(struct kvm_regs, fp_regs));
+  DEFINE(CPU_SP_EL1,            offsetof(struct kvm_regs, sp_el1));
+  DEFINE(CPU_ELR_EL1,           offsetof(struct kvm_regs, elr_el1));
+  DEFINE(CPU_SPSR,              offsetof(struct kvm_regs, spsr));
+  DEFINE(CPU_SYSREGS,           offsetof(struct kvm_cpu_context, sys_regs));
+  DEFINE(VCPU_ESR_EL2,          offsetof(struct kvm_vcpu, arch.fault.esr_el2));
+  DEFINE(VCPU_FAR_EL2,          offsetof(struct kvm_vcpu, arch.fault.far_el2));
+  DEFINE(VCPU_HPFAR_EL2,        offsetof(struct kvm_vcpu, arch.fault.hpfar_el2));
+  DEFINE(VCPU_HCR_EL2,          offsetof(struct kvm_vcpu, arch.hcr_el2));
+  DEFINE(VCPU_IRQ_LINES,        offsetof(struct kvm_vcpu, arch.irq_lines));
+  DEFINE(VCPU_HOST_CONTEXT,     offsetof(struct kvm_vcpu, arch.host_cpu_context));
+  DEFINE(VCPU_TIMER_CNTV_CTL,   offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_ctl));
+  DEFINE(VCPU_TIMER_CNTV_CVAL,  offsetof(struct kvm_vcpu, arch.timer_cpu.cntv_cval));
+  DEFINE(KVM_TIMER_CNTVOFF,     offsetof(struct kvm, arch.timer.cntvoff));
+  DEFINE(KVM_TIMER_ENABLED,     offsetof(struct kvm, arch.timer.enabled));
+  DEFINE(VCPU_KVM,              offsetof(struct kvm_vcpu, kvm));
+  DEFINE(VCPU_VGIC_CPU,         offsetof(struct kvm_vcpu, arch.vgic_cpu));
+  DEFINE(VGIC_CPU_HCR,          offsetof(struct vgic_cpu, vgic_hcr));
+  DEFINE(VGIC_CPU_VMCR,         offsetof(struct vgic_cpu, vgic_vmcr));
+  DEFINE(VGIC_CPU_MISR,         offsetof(struct vgic_cpu, vgic_misr));
+  DEFINE(VGIC_CPU_EISR,         offsetof(struct vgic_cpu, vgic_eisr));
+  DEFINE(VGIC_CPU_ELRSR,        offsetof(struct vgic_cpu, vgic_elrsr));
+  DEFINE(VGIC_CPU_APR,          offsetof(struct vgic_cpu, vgic_apr));
+  DEFINE(VGIC_CPU_LR,           offsetof(struct vgic_cpu, vgic_lr));
+  DEFINE(VGIC_CPU_NR_LR,        offsetof(struct vgic_cpu, nr_lr));
+  DEFINE(KVM_VTTBR,             offsetof(struct kvm, arch.vttbr));
+  DEFINE(KVM_VGIC_VCTRL,        offsetof(struct kvm, arch.vgic.vctrl_base));
+#endif
   return 0;
 }
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c
index f4726dc054b3..08018e3df580 100644
--- a/arch/arm64/kernel/debug-monitors.c
+++ b/arch/arm64/kernel/debug-monitors.c
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/ptrace.h>
 #include <linux/stat.h>
+#include <linux/uaccess.h>
 
 #include <asm/debug-monitors.h>
 #include <asm/local.h>
@@ -226,13 +227,74 @@ static int single_step_handler(unsigned long addr, unsigned int esr,
         return 0;
 }
 
-static int __init single_step_init(void)
+static int brk_handler(unsigned long addr, unsigned int esr,
+                       struct pt_regs *regs)
+{
+        siginfo_t info;
+
+        if (!user_mode(regs))
+                return -EFAULT;
+
+        info = (siginfo_t) {
+                .si_signo = SIGTRAP,
+                .si_errno = 0,
+                .si_code  = TRAP_BRKPT,
+                .si_addr  = (void __user *)instruction_pointer(regs),
+        };
+
+        force_sig_info(SIGTRAP, &info, current);
+        return 0;
+}
+
+int aarch32_break_handler(struct pt_regs *regs)
+{
+        siginfo_t info;
+        unsigned int instr;
+        bool bp = false;
+        void __user *pc = (void __user *)instruction_pointer(regs);
+
+        if (!compat_user_mode(regs))
+                return -EFAULT;
+
+        if (compat_thumb_mode(regs)) {
+                /* get 16-bit Thumb instruction */
+                get_user(instr, (u16 __user *)pc);
+                if (instr == AARCH32_BREAK_THUMB2_LO) {
+                        /* get second half of 32-bit Thumb-2 instruction */
+                        get_user(instr, (u16 __user *)(pc + 2));
+                        bp = instr == AARCH32_BREAK_THUMB2_HI;
+                } else {
+                        bp = instr == AARCH32_BREAK_THUMB;
+                }
+        } else {
+                /* 32-bit ARM instruction */
+                get_user(instr, (u32 __user *)pc);
+                bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM;
+        }
+
+        if (!bp)
+                return -EFAULT;
+
+        info = (siginfo_t) {
+                .si_signo = SIGTRAP,
+                .si_errno = 0,
+                .si_code  = TRAP_BRKPT,
+                .si_addr  = pc,
+        };
+
+        force_sig_info(SIGTRAP, &info, current);
+        return 0;
+}
+
+static int __init debug_traps_init(void)
 {
         hook_debug_fault_code(DBG_ESR_EVT_HWSS, single_step_handler, SIGTRAP,
                               TRAP_HWBKPT, "single-step handler");
+        hook_debug_fault_code(DBG_ESR_EVT_BRK, brk_handler, SIGTRAP,
+                              TRAP_BRKPT, "ptrace BRK handler");
         return 0;
 }
-arch_initcall(single_step_init);
+arch_initcall(debug_traps_init);
 
 /* Re-enable single step for syscall restarting. */
 void user_rewind_single_step(struct task_struct *task)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 1e49e5eb81e9..9ba33c40cdf8 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1336,6 +1336,7 @@ void perf_callchain_user(struct perf_callchain_entry *entry,
                 return;
         }
 
+        perf_callchain_store(entry, regs->pc);
         tail = (struct frame_tail __user *)regs->regs[29];
 
         while (entry->nr < PERF_MAX_STACK_DEPTH &&
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 6e1e77f1831c..fecdbf7de82e 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -53,28 +53,6 @@ void ptrace_disable(struct task_struct *child)
 {
 }
 
-/*
- * Handle hitting a breakpoint.
- */
-static int ptrace_break(struct pt_regs *regs)
-{
-        siginfo_t info = {
-                .si_signo = SIGTRAP,
-                .si_errno = 0,
-                .si_code  = TRAP_BRKPT,
-                .si_addr  = (void __user *)instruction_pointer(regs),
-        };
-
-        force_sig_info(SIGTRAP, &info, current);
-        return 0;
-}
-
-static int arm64_break_trap(unsigned long addr, unsigned int esr,
-                            struct pt_regs *regs)
-{
-        return ptrace_break(regs);
-}
-
 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 /*
  * Handle hitting a HW-breakpoint.
@@ -817,33 +795,6 @@ static const struct user_regset_view user_aarch32_view = {
         .regsets = aarch32_regsets, .n = ARRAY_SIZE(aarch32_regsets)
 };
 
-int aarch32_break_trap(struct pt_regs *regs)
-{
-        unsigned int instr;
-        bool bp = false;
-        void __user *pc = (void __user *)instruction_pointer(regs);
-
-        if (compat_thumb_mode(regs)) {
-                /* get 16-bit Thumb instruction */
-                get_user(instr, (u16 __user *)pc);
-                if (instr == AARCH32_BREAK_THUMB2_LO) {
-                        /* get second half of 32-bit Thumb-2 instruction */
-                        get_user(instr, (u16 __user *)(pc + 2));
-                        bp = instr == AARCH32_BREAK_THUMB2_HI;
-                } else {
-                        bp = instr == AARCH32_BREAK_THUMB;
-                }
-        } else {
-                /* 32-bit ARM instruction */
-                get_user(instr, (u32 __user *)pc);
-                bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM;
-        }
-
-        if (bp)
-                return ptrace_break(regs);
-        return 1;
-}
-
 static int compat_ptrace_read_user(struct task_struct *tsk, compat_ulong_t off,
                                    compat_ulong_t __user *ret)
 {
@@ -1111,16 +1062,6 @@ long arch_ptrace(struct task_struct *child, long request,
         return ptrace_request(child, request, addr, data);
 }
 
-
-static int __init ptrace_break_init(void)
-{
-        hook_debug_fault_code(DBG_ESR_EVT_BRK, arm64_break_trap, SIGTRAP,
-                              TRAP_BRKPT, "ptrace BRK handler");
-        return 0;
-}
-core_initcall(ptrace_break_init);
-
-
 asmlinkage int syscall_trace(int dir, struct pt_regs *regs)
 {
         unsigned long saved_reg;
diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
index a551f88ae2c1..03dc3718eb13 100644
--- a/arch/arm64/kernel/time.c
+++ b/arch/arm64/kernel/time.c
@@ -68,12 +68,6 @@ unsigned long long notrace sched_clock(void)
         return arch_timer_read_counter() * sched_clock_mult;
 }
 
-int read_current_timer(unsigned long *timer_value)
-{
-        *timer_value = arch_timer_read_counter();
-        return 0;
-}
-
 void __init time_init(void)
 {
         u32 arch_timer_rate;
diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c
index f30852d28590..7ffadddb645d 100644
--- a/arch/arm64/kernel/traps.c
+++ b/arch/arm64/kernel/traps.c
@@ -32,6 +32,7 @@
 #include <linux/syscalls.h>
 
 #include <asm/atomic.h>
+#include <asm/debug-monitors.h>
 #include <asm/traps.h>
 #include <asm/stacktrace.h>
 #include <asm/exception.h>
@@ -261,11 +262,9 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
         siginfo_t info;
         void __user *pc = (void __user *)instruction_pointer(regs);
 
-#ifdef CONFIG_COMPAT
         /* check for AArch32 breakpoint instructions */
-        if (compat_user_mode(regs) && aarch32_break_trap(regs) == 0)
+        if (!aarch32_break_handler(regs))
                 return;
-#endif
 
         if (show_unhandled_signals && unhandled_signal(current, SIGILL) &&
             printk_ratelimit()) {
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 3fae2be8b016..f5e55747242f 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -17,6 +17,19 @@ ENTRY(stext)
 
 jiffies = jiffies_64;
 
+#define HYPERVISOR_TEXT                                 \
+        /*                                              \
+         * Force the alignment to be compatible with    \
+         * the vectors requirements                     \
+         */                                             \
+        . = ALIGN(2048);                                \
+        VMLINUX_SYMBOL(__hyp_idmap_text_start) = .;     \
+        *(.hyp.idmap.text)                              \
+        VMLINUX_SYMBOL(__hyp_idmap_text_end) = .;       \
+        VMLINUX_SYMBOL(__hyp_text_start) = .;           \
+        *(.hyp.text)                                    \
+        VMLINUX_SYMBOL(__hyp_text_end) = .;
+
 SECTIONS
 {
         /*
@@ -49,6 +62,7 @@ SECTIONS
                         TEXT_TEXT
                         SCHED_TEXT
                         LOCK_TEXT
+                        HYPERVISOR_TEXT
                         *(.fixup)
                         *(.gnu.warning)
                 . = ALIGN(16);
@@ -56,7 +70,7 @@ SECTIONS
         }
 
         RO_DATA(PAGE_SIZE)
-
+        EXCEPTION_TABLE(8)
         _etext = .;                     /* End of text and rodata section */
 
         . = ALIGN(PAGE_SIZE);
@@ -99,14 +113,6 @@ SECTIONS
                 READ_MOSTLY_DATA(64)
 
                 /*
-                 * The exception fixup table (might need resorting at runtime)
-                 */
-                . = ALIGN(32);
-                __start___ex_table = .;
-                *(__ex_table)
-                __stop___ex_table = .;
-
-                /*
                  * and the usual data section
                  */
                 DATA_DATA
@@ -124,3 +130,9 @@ SECTIONS
         STABS_DEBUG
         .comment 0 : { *(.comment) }
 }
+
+/*
+ * The HYP init code can't be more than a page long.
+ */
+ASSERT(((__hyp_idmap_text_start + PAGE_SIZE) > __hyp_idmap_text_end),
+       "HYP init code too big")
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
new file mode 100644
index 000000000000..72a9fd583ad3
--- /dev/null
+++ b/arch/arm64/kvm/Makefile
@@ -0,0 +1,23 @@
+#
+# Makefile for Kernel-based Virtual Machine module
+#
+
+ccflags-y += -Ivirt/kvm -Iarch/arm64/kvm
+CFLAGS_arm.o := -I.
+CFLAGS_mmu.o := -I.
+
+KVM=../../../virt/kvm
+ARM=../../../arch/arm/kvm
+
+obj-$(CONFIG_KVM_ARM_HOST) += kvm.o
+
+kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
+kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o
+kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/psci.o $(ARM)/perf.o
+
+kvm-$(CONFIG_KVM_ARM_HOST) += emulate.o inject_fault.o regmap.o
+kvm-$(CONFIG_KVM_ARM_HOST) += hyp.o hyp-init.o handle_exit.o
+kvm-$(CONFIG_KVM_ARM_HOST) += guest.o reset.o sys_regs.o sys_regs_generic_v8.o
+
+kvm-$(CONFIG_KVM_ARM_VGIC) += $(KVM)/arm/vgic.o
+kvm-$(CONFIG_KVM_ARM_TIMER) += $(KVM)/arm/arch_timer.o
diff --git a/arch/arm64/kvm/emulate.c b/arch/arm64/kvm/emulate.c
new file mode 100644
index 000000000000..124418d17049
--- /dev/null
+++ b/arch/arm64/kvm/emulate.c
@@ -0,0 +1,158 @@
+/*
+ * (not much of an) Emulation layer for 32bit guests.
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * based on arch/arm/kvm/emulate.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+
+/*
+ * stolen from arch/arm/kernel/opcodes.c
+ *
+ * condition code lookup table
+ * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
+ *
+ * bit position in short is condition code: NZCV
+ */
+static const unsigned short cc_map[16] = {
+        0xF0F0,                 /* EQ == Z set            */
+        0x0F0F,                 /* NE                     */
+        0xCCCC,                 /* CS == C set            */
+        0x3333,                 /* CC                     */
+        0xFF00,                 /* MI == N set            */
+        0x00FF,                 /* PL                     */
+        0xAAAA,                 /* VS == V set            */
+        0x5555,                 /* VC                     */
+        0x0C0C,                 /* HI == C set && Z clear */
+        0xF3F3,                 /* LS == C clear || Z set */
+        0xAA55,                 /* GE == (N==V)           */
+        0x55AA,                 /* LT == (N!=V)           */
+        0x0A05,                 /* GT == (!Z && (N==V))   */
+        0xF5FA,                 /* LE == (Z || (N!=V))    */
+        0xFFFF,                 /* AL always              */
+        0                       /* NV                     */
+};
+
+static int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
+{
+        u32 esr = kvm_vcpu_get_hsr(vcpu);
+
+        if (esr & ESR_EL2_CV)
+                return (esr & ESR_EL2_COND) >> ESR_EL2_COND_SHIFT;
+
+        return -1;
+}
+
+/*
+ * Check if a trapped instruction should have been executed or not.
+ */
+bool kvm_condition_valid32(const struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr;
+        u32 cpsr_cond;
+        int cond;
+
+        /* Top two bits non-zero?  Unconditional. */
+        if (kvm_vcpu_get_hsr(vcpu) >> 30)
+                return true;
+
+        /* Is condition field valid? */
+        cond = kvm_vcpu_get_condition(vcpu);
+        if (cond == 0xE)
+                return true;
+
+        cpsr = *vcpu_cpsr(vcpu);
+
+        if (cond < 0) {
+                /* This can happen in Thumb mode: examine IT state. */
+                unsigned long it;
+
+                it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+
+                /* it == 0 => unconditional. */
+                if (it == 0)
+                        return true;
+
+                /* The cond for this insn works out as the top 4 bits. */
+                cond = (it >> 4);
+        }
+
+        cpsr_cond = cpsr >> 28;
+
+        if (!((cc_map[cond] >> cpsr_cond) & 1))
+                return false;
+
+        return true;
+}
+
+/**
+ * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
+ * @vcpu:       The VCPU pointer
+ *
+ * When exceptions occur while instructions are executed in Thumb IF-THEN
+ * blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
+ * to do this little bit of work manually. The fields map like this:
+ *
+ * IT[7:0] -> CPSR[26:25],CPSR[15:10]
+ */
+static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
+{
+        unsigned long itbits, cond;
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
+        bool is_arm = !(cpsr & COMPAT_PSR_T_BIT);
+
+        BUG_ON(is_arm && (cpsr & COMPAT_PSR_IT_MASK));
+
+        if (!(cpsr & COMPAT_PSR_IT_MASK))
+                return;
+
+        cond = (cpsr & 0xe000) >> 13;
+        itbits = (cpsr & 0x1c00) >> (10 - 2);
+        itbits |= (cpsr & (0x3 << 25)) >> 25;
+
+        /* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
+        if ((itbits & 0x7) == 0)
+                itbits = cond = 0;
+        else
+                itbits = (itbits << 1) & 0x1f;
+
+        cpsr &= ~COMPAT_PSR_IT_MASK;
+        cpsr |= cond << 13;
+        cpsr |= (itbits & 0x1c) << (10 - 2);
+        cpsr |= (itbits & 0x3) << 25;
+        *vcpu_cpsr(vcpu) = cpsr;
+}
+
+/**
+ * kvm_skip_instr - skip a trapped instruction and proceed to the next
+ * @vcpu: The vcpu pointer
+ */
+void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
+{
+        bool is_thumb;
+
+        is_thumb = !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_T_BIT);
+        if (is_thumb && !is_wide_instr)
+                *vcpu_pc(vcpu) += 2;
+        else
+                *vcpu_pc(vcpu) += 4;
+        kvm_adjust_itstate(vcpu);
+}
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
new file mode 100644
index 000000000000..2c3ff67a8ecb
--- /dev/null
+++ b/arch/arm64/kvm/guest.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/guest.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/kvm_host.h>
+#include <linux/module.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <asm/cputype.h>
+#include <asm/uaccess.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+
+struct kvm_stats_debugfs_item debugfs_entries[] = {
+        { NULL }
+};
+
+int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
+{
+        vcpu->arch.hcr_el2 = HCR_GUEST_FLAGS;
+        return 0;
+}
+
+static u64 core_reg_offset_from_id(u64 id)
+{
+        return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE);
+}
+
+static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /*
+         * Because the kvm_regs structure is a mix of 32, 64 and
+         * 128bit fields, we index it as if it was a 32bit
+         * array. Hence below, nr_regs is the number of entries, and
+         * off the index in the "array".
+         */
+        __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
+        struct kvm_regs *regs = vcpu_gp_regs(vcpu);
+        int nr_regs = sizeof(*regs) / sizeof(__u32);
+        u32 off;
+
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= nr_regs ||
+            (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
+                return -ENOENT;
+
+        if (copy_to_user(uaddr, ((u32 *)regs) + off, KVM_REG_SIZE(reg->id)))
+                return -EFAULT;
+
+        return 0;
+}
+
+static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        __u32 __user *uaddr = (__u32 __user *)(unsigned long)reg->addr;
+        struct kvm_regs *regs = vcpu_gp_regs(vcpu);
+        int nr_regs = sizeof(*regs) / sizeof(__u32);
+        __uint128_t tmp;
+        void *valp = &tmp;
+        u64 off;
+        int err = 0;
+
+        /* Our ID is an index into the kvm_regs struct. */
+        off = core_reg_offset_from_id(reg->id);
+        if (off >= nr_regs ||
+            (off + (KVM_REG_SIZE(reg->id) / sizeof(__u32))) >= nr_regs)
+                return -ENOENT;
+
+        if (KVM_REG_SIZE(reg->id) > sizeof(tmp))
+                return -EINVAL;
+
+        if (copy_from_user(valp, uaddr, KVM_REG_SIZE(reg->id))) {
+                err = -EFAULT;
+                goto out;
+        }
+
+        if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
+                u32 mode = (*(u32 *)valp) & COMPAT_PSR_MODE_MASK;
+                switch (mode) {
+                case COMPAT_PSR_MODE_USR:
+                case COMPAT_PSR_MODE_FIQ:
+                case COMPAT_PSR_MODE_IRQ:
+                case COMPAT_PSR_MODE_SVC:
+                case COMPAT_PSR_MODE_ABT:
+                case COMPAT_PSR_MODE_UND:
+                case PSR_MODE_EL0t:
+                case PSR_MODE_EL1t:
+                case PSR_MODE_EL1h:
+                        break;
+                default:
+                        err = -EINVAL;
+                        goto out;
+                }
+        }
+
+        memcpy((u32 *)regs + off, valp, KVM_REG_SIZE(reg->id));
+out:
+        return err;
+}
+
+int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
+{
+        return -EINVAL;
+}
+
+static unsigned long num_core_regs(void)
+{
+        return sizeof(struct kvm_regs) / sizeof(__u32);
+}
+
+/**
+ * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG
+ *
+ * This is for all registers.
+ */
+unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu)
+{
+        return num_core_regs() + kvm_arm_num_sys_reg_descs(vcpu);
+}
+
+/**
+ * kvm_arm_copy_reg_indices - get indices of all registers.
+ *
+ * We do core registers right here, then we apppend system regs.
+ */
+int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE;
+
+        for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) {
+                if (put_user(core_reg | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+
+        return kvm_arm_copy_sys_reg_indices(vcpu, uindices);
+}
+
+int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
+                return -EINVAL;
+
+        /* Register group 16 means we want a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return get_core_reg(vcpu, reg);
+
+        return kvm_arm_sys_reg_get_reg(vcpu, reg);
+}
+
+int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        /* We currently use nothing arch-specific in upper 32 bits */
+        if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 != KVM_REG_ARM64 >> 32)
+                return -EINVAL;
+
+        /* Register group 16 means we set a core register. */
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_CORE)
+                return set_core_reg(vcpu, reg);
+
+        return kvm_arm_sys_reg_set_reg(vcpu, reg);
+}
+
+int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
+                                  struct kvm_sregs *sregs)
+{
+        return -EINVAL;
+}
+
+int __attribute_const__ kvm_target_cpu(void)
+{
+        unsigned long implementor = read_cpuid_implementor();
+        unsigned long part_number = read_cpuid_part_number();
+
+        if (implementor != ARM_CPU_IMP_ARM)
+                return -EINVAL;
+
+        switch (part_number) {
+        case ARM_CPU_PART_AEM_V8:
+                return KVM_ARM_TARGET_AEM_V8;
+        case ARM_CPU_PART_FOUNDATION:
+                return KVM_ARM_TARGET_FOUNDATION_V8;
+        case ARM_CPU_PART_CORTEX_A57:
+                /* Currently handled by the generic backend */
+                return KVM_ARM_TARGET_CORTEX_A57;
+        default:
+                return -EINVAL;
+        }
+}
+
+int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
+                        const struct kvm_vcpu_init *init)
+{
+        unsigned int i;
+        int phys_target = kvm_target_cpu();
+
+        if (init->target != phys_target)
+                return -EINVAL;
+
+        vcpu->arch.target = phys_target;
+        bitmap_zero(vcpu->arch.features, KVM_VCPU_MAX_FEATURES);
+
+        /* -ENOENT for unknown features, -EINVAL for invalid combinations. */
+        for (i = 0; i < sizeof(init->features) * 8; i++) {
+                if (init->features[i / 32] & (1 << (i % 32))) {
+                        if (i >= KVM_VCPU_MAX_FEATURES)
+                                return -ENOENT;
+                        set_bit(i, vcpu->arch.features);
+                }
+        }
+
+        /* Now we know what it is, we can reset it. */
+        return kvm_reset_vcpu(vcpu);
+}
+
+int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
+{
+        return -EINVAL;
+}
+
+int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
+                                  struct kvm_translation *tr)
+{
+        return -EINVAL;
+}
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
new file mode 100644
index 000000000000..9beaca033437
--- /dev/null
+++ b/arch/arm64/kvm/handle_exit.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/handle_exit.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/kvm_mmu.h>
+#include <asm/kvm_psci.h>
+
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        if (kvm_psci_call(vcpu))
+                return 1;
+
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        if (kvm_psci_call(vcpu))
+                return 1;
+
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu:       the vcpu pointer
+ *
+ * Simply call kvm_vcpu_block(), which will halt execution of
+ * world-switches and schedule other host processes until there is an
+ * incoming IRQ or FIQ to the VM.
+ */
+static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_vcpu_block(vcpu);
+        return 1;
+}
+
+static exit_handle_fn arm_exit_handlers[] = {
+        [ESR_EL2_EC_WFI]        = kvm_handle_wfi,
+        [ESR_EL2_EC_CP15_32]    = kvm_handle_cp15_32,
+        [ESR_EL2_EC_CP15_64]    = kvm_handle_cp15_64,
+        [ESR_EL2_EC_CP14_MR]    = kvm_handle_cp14_access,
+        [ESR_EL2_EC_CP14_LS]    = kvm_handle_cp14_load_store,
+        [ESR_EL2_EC_CP14_64]    = kvm_handle_cp14_access,
+        [ESR_EL2_EC_HVC32]      = handle_hvc,
+        [ESR_EL2_EC_SMC32]      = handle_smc,
+        [ESR_EL2_EC_HVC64]      = handle_hvc,
+        [ESR_EL2_EC_SMC64]      = handle_smc,
+        [ESR_EL2_EC_SYS64]      = kvm_handle_sys_reg,
+        [ESR_EL2_EC_IABT]       = kvm_handle_guest_abort,
+        [ESR_EL2_EC_DABT]       = kvm_handle_guest_abort,
+};
+
+static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
+{
+        u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
+
+        if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
+            !arm_exit_handlers[hsr_ec]) {
+                kvm_err("Unkown exception class: hsr: %#08x\n",
+                        (unsigned int)kvm_vcpu_get_hsr(vcpu));
+                BUG();
+        }
+
+        return arm_exit_handlers[hsr_ec];
+}
+
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to userspace.
+ */
+int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+                       int exception_index)
+{
+        exit_handle_fn exit_handler;
+
+        switch (exception_index) {
+        case ARM_EXCEPTION_IRQ:
+                return 1;
+        case ARM_EXCEPTION_TRAP:
+                /*
+                 * See ARM ARM B1.14.1: "Hyp traps on instructions
+                 * that fail their condition code check"
+                 */
+                if (!kvm_condition_valid(vcpu)) {
+                        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+                        return 1;
+                }
+
+                exit_handler = kvm_get_exit_handler(vcpu);
+
+                return exit_handler(vcpu, run);
+        default:
+                kvm_pr_unimpl("Unsupported exception type: %d",
+                              exception_index);
+                run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+                return 0;
+        }
+}
diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
new file mode 100644
index 000000000000..ba84e6705e20
--- /dev/null
+++ b/arch/arm64/kvm/hyp-init.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+
+        .text
+        .pushsection    .hyp.idmap.text, "ax"
+
+        .align  11
+
+ENTRY(__kvm_hyp_init)
+        ventry  __invalid               // Synchronous EL2t
+        ventry  __invalid               // IRQ EL2t
+        ventry  __invalid               // FIQ EL2t
+        ventry  __invalid               // Error EL2t
+
+        ventry  __invalid               // Synchronous EL2h
+        ventry  __invalid               // IRQ EL2h
+        ventry  __invalid               // FIQ EL2h
+        ventry  __invalid               // Error EL2h
+
+        ventry  __do_hyp_init           // Synchronous 64-bit EL1
+        ventry  __invalid               // IRQ 64-bit EL1
+        ventry  __invalid               // FIQ 64-bit EL1
+        ventry  __invalid               // Error 64-bit EL1
+
+        ventry  __invalid               // Synchronous 32-bit EL1
+        ventry  __invalid               // IRQ 32-bit EL1
+        ventry  __invalid               // FIQ 32-bit EL1
+        ventry  __invalid               // Error 32-bit EL1
+
+__invalid:
+        b       .
+
+        /*
+         * x0: HYP boot pgd
+         * x1: HYP pgd
+         * x2: HYP stack
+         * x3: HYP vectors
+         */
+__do_hyp_init:
+
+        msr     ttbr0_el2, x0
+
+        mrs     x4, tcr_el1
+        ldr     x5, =TCR_EL2_MASK
+        and     x4, x4, x5
+        ldr     x5, =TCR_EL2_FLAGS
+        orr     x4, x4, x5
+        msr     tcr_el2, x4
+
+        ldr     x4, =VTCR_EL2_FLAGS
+        msr     vtcr_el2, x4
+
+        mrs     x4, mair_el1
+        msr     mair_el2, x4
+        isb
+
+        mov     x4, #SCTLR_EL2_FLAGS
+        msr     sctlr_el2, x4
+        isb
+
+        /* MMU is now enabled. Get ready for the trampoline dance */
+        ldr     x4, =TRAMPOLINE_VA
+        adr     x5, target
+        bfi     x4, x5, #0, #PAGE_SHIFT
+        br      x4
+
+target: /* We're now in the trampoline code, switch page tables */
+        msr     ttbr0_el2, x1
+        isb
+
+        /* Invalidate the old TLBs */
+        tlbi    alle2
+        dsb     sy
+
+        /* Set the stack and new vectors */
+        kern_hyp_va     x2
+        mov     sp, x2
+        kern_hyp_va     x3
+        msr     vbar_el2, x3
+
+        /* Hello, World! */
+        eret
+ENDPROC(__kvm_hyp_init)
+
+        .ltorg
+
+        .popsection
diff --git a/arch/arm64/kvm/hyp.S b/arch/arm64/kvm/hyp.S
new file mode 100644
index 000000000000..ff985e3d8b72
--- /dev/null
+++ b/arch/arm64/kvm/hyp.S
@@ -0,0 +1,831 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+#include <linux/irqchip/arm-gic.h>
+
+#include <asm/assembler.h>
+#include <asm/memory.h>
+#include <asm/asm-offsets.h>
+#include <asm/fpsimdmacros.h>
+#include <asm/kvm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_mmu.h>
+
+#define CPU_GP_REG_OFFSET(x)    (CPU_GP_REGS + x)
+#define CPU_XREG_OFFSET(x)      CPU_GP_REG_OFFSET(CPU_USER_PT_REGS + 8*x)
+#define CPU_SPSR_OFFSET(x)      CPU_GP_REG_OFFSET(CPU_SPSR + 8*x)
+#define CPU_SYSREG_OFFSET(x)    (CPU_SYSREGS + 8*x)
+
+        .text
+        .pushsection    .hyp.text, "ax"
+        .align  PAGE_SHIFT
+
+__kvm_hyp_code_start:
+        .globl __kvm_hyp_code_start
+
+.macro save_common_regs
+        // x2: base address for cpu context
+        // x3: tmp register
+
+        add     x3, x2, #CPU_XREG_OFFSET(19)
+        stp     x19, x20, [x3]
+        stp     x21, x22, [x3, #16]
+        stp     x23, x24, [x3, #32]
+        stp     x25, x26, [x3, #48]
+        stp     x27, x28, [x3, #64]
+        stp     x29, lr, [x3, #80]
+
+        mrs     x19, sp_el0
+        mrs     x20, elr_el2            // EL1 PC
+        mrs     x21, spsr_el2           // EL1 pstate
+
+        stp     x19, x20, [x3, #96]
+        str     x21, [x3, #112]
+
+        mrs     x22, sp_el1
+        mrs     x23, elr_el1
+        mrs     x24, spsr_el1
+
+        str     x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
+        str     x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
+        str     x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
+.endm
+
+.macro restore_common_regs
+        // x2: base address for cpu context
+        // x3: tmp register
+
+        ldr     x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
+        ldr     x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
+        ldr     x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
+
+        msr     sp_el1, x22
+        msr     elr_el1, x23
+        msr     spsr_el1, x24
+
+        add     x3, x2, #CPU_XREG_OFFSET(31)    // SP_EL0
+        ldp     x19, x20, [x3]
+        ldr     x21, [x3, #16]
+
+        msr     sp_el0, x19
+        msr     elr_el2, x20                            // EL1 PC
+        msr     spsr_el2, x21                           // EL1 pstate
+
+        add     x3, x2, #CPU_XREG_OFFSET(19)
+        ldp     x19, x20, [x3]
+        ldp     x21, x22, [x3, #16]
+        ldp     x23, x24, [x3, #32]
+        ldp     x25, x26, [x3, #48]
+        ldp     x27, x28, [x3, #64]
+        ldp     x29, lr, [x3, #80]
+.endm
+
+.macro save_host_regs
+        save_common_regs
+.endm
+
+.macro restore_host_regs
+        restore_common_regs
+.endm
+
+.macro save_fpsimd
+        // x2: cpu context address
+        // x3, x4: tmp regs
+        add     x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
+        fpsimd_save x3, 4
+.endm
+
+.macro restore_fpsimd
+        // x2: cpu context address
+        // x3, x4: tmp regs
+        add     x3, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
+        fpsimd_restore x3, 4
+.endm
+
+.macro save_guest_regs
+        // x0 is the vcpu address
+        // x1 is the return code, do not corrupt!
+        // x2 is the cpu context
+        // x3 is a tmp register
+        // Guest's x0-x3 are on the stack
+
+        // Compute base to save registers
+        add     x3, x2, #CPU_XREG_OFFSET(4)
+        stp     x4, x5, [x3]
+        stp     x6, x7, [x3, #16]
+        stp     x8, x9, [x3, #32]
+        stp     x10, x11, [x3, #48]
+        stp     x12, x13, [x3, #64]
+        stp     x14, x15, [x3, #80]
+        stp     x16, x17, [x3, #96]
+        str     x18, [x3, #112]
+
+        pop     x6, x7                  // x2, x3
+        pop     x4, x5                  // x0, x1
+
+        add     x3, x2, #CPU_XREG_OFFSET(0)
+        stp     x4, x5, [x3]
+        stp     x6, x7, [x3, #16]
+
+        save_common_regs
+.endm
+
+.macro restore_guest_regs
+        // x0 is the vcpu address.
+        // x2 is the cpu context
+        // x3 is a tmp register
+
+        // Prepare x0-x3 for later restore
+        add     x3, x2, #CPU_XREG_OFFSET(0)
+        ldp     x4, x5, [x3]
+        ldp     x6, x7, [x3, #16]
+        push    x4, x5          // Push x0-x3 on the stack
+        push    x6, x7
+
+        // x4-x18
+        ldp     x4, x5, [x3, #32]
+        ldp     x6, x7, [x3, #48]
+        ldp     x8, x9, [x3, #64]
+        ldp     x10, x11, [x3, #80]
+        ldp     x12, x13, [x3, #96]
+        ldp     x14, x15, [x3, #112]
+        ldp     x16, x17, [x3, #128]
+        ldr     x18, [x3, #144]
+
+        // x19-x29, lr, sp*, elr*, spsr*
+        restore_common_regs
+
+        // Last bits of the 64bit state
+        pop     x2, x3
+        pop     x0, x1
+
+        // Do not touch any register after this!
+.endm
+
+/*
+ * Macros to perform system register save/restore.
+ *
+ * Ordering here is absolutely critical, and must be kept consistent
+ * in {save,restore}_sysregs, {save,restore}_guest_32bit_state,
+ * and in kvm_asm.h.
+ *
+ * In other words, don't touch any of these unless you know what
+ * you are doing.
+ */
+.macro save_sysregs
+        // x2: base address for cpu context
+        // x3: tmp register
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
+
+        mrs     x4,     vmpidr_el2
+        mrs     x5,     csselr_el1
+        mrs     x6,     sctlr_el1
+        mrs     x7,     actlr_el1
+        mrs     x8,     cpacr_el1
+        mrs     x9,     ttbr0_el1
+        mrs     x10,    ttbr1_el1
+        mrs     x11,    tcr_el1
+        mrs     x12,    esr_el1
+        mrs     x13,    afsr0_el1
+        mrs     x14,    afsr1_el1
+        mrs     x15,    far_el1
+        mrs     x16,    mair_el1
+        mrs     x17,    vbar_el1
+        mrs     x18,    contextidr_el1
+        mrs     x19,    tpidr_el0
+        mrs     x20,    tpidrro_el0
+        mrs     x21,    tpidr_el1
+        mrs     x22,    amair_el1
+        mrs     x23,    cntkctl_el1
+
+        stp     x4, x5, [x3]
+        stp     x6, x7, [x3, #16]
+        stp     x8, x9, [x3, #32]
+        stp     x10, x11, [x3, #48]
+        stp     x12, x13, [x3, #64]
+        stp     x14, x15, [x3, #80]
+        stp     x16, x17, [x3, #96]
+        stp     x18, x19, [x3, #112]
+        stp     x20, x21, [x3, #128]
+        stp     x22, x23, [x3, #144]
+.endm
+
+.macro restore_sysregs
+        // x2: base address for cpu context
+        // x3: tmp register
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(MPIDR_EL1)
+
+        ldp     x4, x5, [x3]
+        ldp     x6, x7, [x3, #16]
+        ldp     x8, x9, [x3, #32]
+        ldp     x10, x11, [x3, #48]
+        ldp     x12, x13, [x3, #64]
+        ldp     x14, x15, [x3, #80]
+        ldp     x16, x17, [x3, #96]
+        ldp     x18, x19, [x3, #112]
+        ldp     x20, x21, [x3, #128]
+        ldp     x22, x23, [x3, #144]
+
+        msr     vmpidr_el2,     x4
+        msr     csselr_el1,     x5
+        msr     sctlr_el1,      x6
+        msr     actlr_el1,      x7
+        msr     cpacr_el1,      x8
+        msr     ttbr0_el1,      x9
+        msr     ttbr1_el1,      x10
+        msr     tcr_el1,        x11
+        msr     esr_el1,        x12
+        msr     afsr0_el1,      x13
+        msr     afsr1_el1,      x14
+        msr     far_el1,        x15
+        msr     mair_el1,       x16
+        msr     vbar_el1,       x17
+        msr     contextidr_el1, x18
+        msr     tpidr_el0,      x19
+        msr     tpidrro_el0,    x20
+        msr     tpidr_el1,      x21
+        msr     amair_el1,      x22
+        msr     cntkctl_el1,    x23
+.endm
+
+.macro skip_32bit_state tmp, target
+        // Skip 32bit state if not needed
+        mrs     \tmp, hcr_el2
+        tbnz    \tmp, #HCR_RW_SHIFT, \target
+.endm
+
+.macro skip_tee_state tmp, target
+        // Skip ThumbEE state if not needed
+        mrs     \tmp, id_pfr0_el1
+        tbz     \tmp, #12, \target
+.endm
+
+.macro save_guest_32bit_state
+        skip_32bit_state x3, 1f
+
+        add     x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
+        mrs     x4, spsr_abt
+        mrs     x5, spsr_und
+        mrs     x6, spsr_irq
+        mrs     x7, spsr_fiq
+        stp     x4, x5, [x3]
+        stp     x6, x7, [x3, #16]
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
+        mrs     x4, dacr32_el2
+        mrs     x5, ifsr32_el2
+        mrs     x6, fpexc32_el2
+        mrs     x7, dbgvcr32_el2
+        stp     x4, x5, [x3]
+        stp     x6, x7, [x3, #16]
+
+        skip_tee_state x8, 1f
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
+        mrs     x4, teecr32_el1
+        mrs     x5, teehbr32_el1
+        stp     x4, x5, [x3]
+1:
+.endm
+
+.macro restore_guest_32bit_state
+        skip_32bit_state x3, 1f
+
+        add     x3, x2, #CPU_SPSR_OFFSET(KVM_SPSR_ABT)
+        ldp     x4, x5, [x3]
+        ldp     x6, x7, [x3, #16]
+        msr     spsr_abt, x4
+        msr     spsr_und, x5
+        msr     spsr_irq, x6
+        msr     spsr_fiq, x7
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(DACR32_EL2)
+        ldp     x4, x5, [x3]
+        ldp     x6, x7, [x3, #16]
+        msr     dacr32_el2, x4
+        msr     ifsr32_el2, x5
+        msr     fpexc32_el2, x6
+        msr     dbgvcr32_el2, x7
+
+        skip_tee_state x8, 1f
+
+        add     x3, x2, #CPU_SYSREG_OFFSET(TEECR32_EL1)
+        ldp     x4, x5, [x3]
+        msr     teecr32_el1, x4
+        msr     teehbr32_el1, x5
+1:
+.endm
+
+.macro activate_traps
+        ldr     x2, [x0, #VCPU_IRQ_LINES]
+        ldr     x1, [x0, #VCPU_HCR_EL2]
+        orr     x2, x2, x1
+        msr     hcr_el2, x2
+
+        ldr     x2, =(CPTR_EL2_TTA)
+        msr     cptr_el2, x2
+
+        ldr     x2, =(1 << 15)  // Trap CP15 Cr=15
+        msr     hstr_el2, x2
+
+        mrs     x2, mdcr_el2
+        and     x2, x2, #MDCR_EL2_HPMN_MASK
+        orr     x2, x2, #(MDCR_EL2_TPM | MDCR_EL2_TPMCR)
+        msr     mdcr_el2, x2
+.endm
+
+.macro deactivate_traps
+        mov     x2, #HCR_RW
+        msr     hcr_el2, x2
+        msr     cptr_el2, xzr
+        msr     hstr_el2, xzr
+
+        mrs     x2, mdcr_el2
+        and     x2, x2, #MDCR_EL2_HPMN_MASK
+        msr     mdcr_el2, x2
+.endm
+
+.macro activate_vm
+        ldr     x1, [x0, #VCPU_KVM]
+        kern_hyp_va     x1
+        ldr     x2, [x1, #KVM_VTTBR]
+        msr     vttbr_el2, x2
+.endm
+
+.macro deactivate_vm
+        msr     vttbr_el2, xzr
+.endm
+
+/*
+ * Save the VGIC CPU state into memory
+ * x0: Register pointing to VCPU struct
+ * Do not corrupt x1!!!
+ */
+.macro save_vgic_state
+        /* Get VGIC VCTRL base into x2 */
+        ldr     x2, [x0, #VCPU_KVM]
+        kern_hyp_va     x2
+        ldr     x2, [x2, #KVM_VGIC_VCTRL]
+        kern_hyp_va     x2
+        cbz     x2, 2f          // disabled
+
+        /* Compute the address of struct vgic_cpu */
+        add     x3, x0, #VCPU_VGIC_CPU
+
+        /* Save all interesting registers */
+        ldr     w4, [x2, #GICH_HCR]
+        ldr     w5, [x2, #GICH_VMCR]
+        ldr     w6, [x2, #GICH_MISR]
+        ldr     w7, [x2, #GICH_EISR0]
+        ldr     w8, [x2, #GICH_EISR1]
+        ldr     w9, [x2, #GICH_ELRSR0]
+        ldr     w10, [x2, #GICH_ELRSR1]
+        ldr     w11, [x2, #GICH_APR]
+
+        str     w4, [x3, #VGIC_CPU_HCR]
+        str     w5, [x3, #VGIC_CPU_VMCR]
+        str     w6, [x3, #VGIC_CPU_MISR]
+        str     w7, [x3, #VGIC_CPU_EISR]
+        str     w8, [x3, #(VGIC_CPU_EISR + 4)]
+        str     w9, [x3, #VGIC_CPU_ELRSR]
+        str     w10, [x3, #(VGIC_CPU_ELRSR + 4)]
+        str     w11, [x3, #VGIC_CPU_APR]
+
+        /* Clear GICH_HCR */
+        str     wzr, [x2, #GICH_HCR]
+
+        /* Save list registers */
+        add     x2, x2, #GICH_LR0
+        ldr     w4, [x3, #VGIC_CPU_NR_LR]
+        add     x3, x3, #VGIC_CPU_LR
+1:      ldr     w5, [x2], #4
+        str     w5, [x3], #4
+        sub     w4, w4, #1
+        cbnz    w4, 1b
+2:
+.endm
+
+/*
+ * Restore the VGIC CPU state from memory
+ * x0: Register pointing to VCPU struct
+ */
+.macro restore_vgic_state
+        /* Get VGIC VCTRL base into x2 */
+        ldr     x2, [x0, #VCPU_KVM]
+        kern_hyp_va     x2
+        ldr     x2, [x2, #KVM_VGIC_VCTRL]
+        kern_hyp_va     x2
+        cbz     x2, 2f          // disabled
+
+        /* Compute the address of struct vgic_cpu */
+        add     x3, x0, #VCPU_VGIC_CPU
+
+        /* We only restore a minimal set of registers */
+        ldr     w4, [x3, #VGIC_CPU_HCR]
+        ldr     w5, [x3, #VGIC_CPU_VMCR]
+        ldr     w6, [x3, #VGIC_CPU_APR]
+
+        str     w4, [x2, #GICH_HCR]
+        str     w5, [x2, #GICH_VMCR]
+        str     w6, [x2, #GICH_APR]
+
+        /* Restore list registers */
+        add     x2, x2, #GICH_LR0
+        ldr     w4, [x3, #VGIC_CPU_NR_LR]
+        add     x3, x3, #VGIC_CPU_LR
+1:      ldr     w5, [x3], #4
+        str     w5, [x2], #4
+        sub     w4, w4, #1
+        cbnz    w4, 1b
+2:
+.endm
+
+.macro save_timer_state
+        // x0: vcpu pointer
+        ldr     x2, [x0, #VCPU_KVM]
+        kern_hyp_va x2
+        ldr     w3, [x2, #KVM_TIMER_ENABLED]
+        cbz     w3, 1f
+
+        mrs     x3, cntv_ctl_el0
+        and     x3, x3, #3
+        str     w3, [x0, #VCPU_TIMER_CNTV_CTL]
+        bic     x3, x3, #1              // Clear Enable
+        msr     cntv_ctl_el0, x3
+
+        isb
+
+        mrs     x3, cntv_cval_el0
+        str     x3, [x0, #VCPU_TIMER_CNTV_CVAL]
+
+1:
+        // Allow physical timer/counter access for the host
+        mrs     x2, cnthctl_el2
+        orr     x2, x2, #3
+        msr     cnthctl_el2, x2
+
+        // Clear cntvoff for the host
+        msr     cntvoff_el2, xzr
+.endm
+
+.macro restore_timer_state
+        // x0: vcpu pointer
+        // Disallow physical timer access for the guest
+        // Physical counter access is allowed
+        mrs     x2, cnthctl_el2
+        orr     x2, x2, #1
+        bic     x2, x2, #2
+        msr     cnthctl_el2, x2
+
+        ldr     x2, [x0, #VCPU_KVM]
+        kern_hyp_va x2
+        ldr     w3, [x2, #KVM_TIMER_ENABLED]
+        cbz     w3, 1f
+
+        ldr     x3, [x2, #KVM_TIMER_CNTVOFF]
+        msr     cntvoff_el2, x3
+        ldr     x2, [x0, #VCPU_TIMER_CNTV_CVAL]
+        msr     cntv_cval_el0, x2
+        isb
+
+        ldr     w2, [x0, #VCPU_TIMER_CNTV_CTL]
+        and     x2, x2, #3
+        msr     cntv_ctl_el0, x2
+1:
+.endm
+
+__save_sysregs:
+        save_sysregs
+        ret
+
+__restore_sysregs:
+        restore_sysregs
+        ret
+
+__save_fpsimd:
+        save_fpsimd
+        ret
+
+__restore_fpsimd:
+        restore_fpsimd
+        ret
+
+/*
+ * u64 __kvm_vcpu_run(struct kvm_vcpu *vcpu);
+ *
+ * This is the world switch. The first half of the function
+ * deals with entering the guest, and anything from __kvm_vcpu_return
+ * to the end of the function deals with reentering the host.
+ * On the enter path, only x0 (vcpu pointer) must be preserved until
+ * the last moment. On the exit path, x0 (vcpu pointer) and x1 (exception
+ * code) must both be preserved until the epilogue.
+ * In both cases, x2 points to the CPU context we're saving/restoring from/to.
+ */
+ENTRY(__kvm_vcpu_run)
+        kern_hyp_va     x0
+        msr     tpidr_el2, x0   // Save the vcpu register
+
+        // Host context
+        ldr     x2, [x0, #VCPU_HOST_CONTEXT]
+        kern_hyp_va x2
+
+        save_host_regs
+        bl __save_fpsimd
+        bl __save_sysregs
+
+        activate_traps
+        activate_vm
+
+        restore_vgic_state
+        restore_timer_state
+
+        // Guest context
+        add     x2, x0, #VCPU_CONTEXT
+
+        bl __restore_sysregs
+        bl __restore_fpsimd
+        restore_guest_32bit_state
+        restore_guest_regs
+
+        // That's it, no more messing around.
+        eret
+
+__kvm_vcpu_return:
+        // Assume x0 is the vcpu pointer, x1 the return code
+        // Guest's x0-x3 are on the stack
+
+        // Guest context
+        add     x2, x0, #VCPU_CONTEXT
+
+        save_guest_regs
+        bl __save_fpsimd
+        bl __save_sysregs
+        save_guest_32bit_state
+
+        save_timer_state
+        save_vgic_state
+
+        deactivate_traps
+        deactivate_vm
+
+        // Host context
+        ldr     x2, [x0, #VCPU_HOST_CONTEXT]
+        kern_hyp_va x2
+
+        bl __restore_sysregs
+        bl __restore_fpsimd
+        restore_host_regs
+
+        mov     x0, x1
+        ret
+END(__kvm_vcpu_run)
+
+// void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+ENTRY(__kvm_tlb_flush_vmid_ipa)
+        kern_hyp_va     x0
+        ldr     x2, [x0, #KVM_VTTBR]
+        msr     vttbr_el2, x2
+        isb
+
+        /*
+         * We could do so much better if we had the VA as well.
+         * Instead, we invalidate Stage-2 for this IPA, and the
+         * whole of Stage-1. Weep...
+         */
+        tlbi    ipas2e1is, x1
+        dsb     sy
+        tlbi    vmalle1is
+        dsb     sy
+        isb
+
+        msr     vttbr_el2, xzr
+        ret
+ENDPROC(__kvm_tlb_flush_vmid_ipa)
+
+ENTRY(__kvm_flush_vm_context)
+        tlbi    alle1is
+        ic      ialluis
+        dsb     sy
+        ret
+ENDPROC(__kvm_flush_vm_context)
+
+__kvm_hyp_panic:
+        // Guess the context by looking at VTTBR:
+        // If zero, then we're already a host.
+        // Otherwise restore a minimal host context before panicing.
+        mrs     x0, vttbr_el2
+        cbz     x0, 1f
+
+        mrs     x0, tpidr_el2
+
+        deactivate_traps
+        deactivate_vm
+
+        ldr     x2, [x0, #VCPU_HOST_CONTEXT]
+        kern_hyp_va x2
+
+        bl __restore_sysregs
+
+1:      adr     x0, __hyp_panic_str
+        adr     x1, 2f
+        ldp     x2, x3, [x1]
+        sub     x0, x0, x2
+        add     x0, x0, x3
+        mrs     x1, spsr_el2
+        mrs     x2, elr_el2
+        mrs     x3, esr_el2
+        mrs     x4, far_el2
+        mrs     x5, hpfar_el2
+        mrs     x6, par_el1
+        mrs     x7, tpidr_el2
+
+        mov     lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
+                      PSR_MODE_EL1h)
+        msr     spsr_el2, lr
+        ldr     lr, =panic
+        msr     elr_el2, lr
+        eret
+
+        .align  3
+2:      .quad   HYP_PAGE_OFFSET
+        .quad   PAGE_OFFSET
+ENDPROC(__kvm_hyp_panic)
+
+__hyp_panic_str:
+        .ascii  "HYP panic:\nPS:%08x PC:%p ESR:%p\nFAR:%p HPFAR:%p PAR:%p\nVCPU:%p\n\0"
+
+        .align  2
+
+ENTRY(kvm_call_hyp)
+        hvc     #0
+        ret
+ENDPROC(kvm_call_hyp)
+
+.macro invalid_vector   label, target
+        .align  2
+\label:
+        b \target
+ENDPROC(\label)
+.endm
+
+        /* None of these should ever happen */
+        invalid_vector  el2t_sync_invalid, __kvm_hyp_panic
+        invalid_vector  el2t_irq_invalid, __kvm_hyp_panic
+        invalid_vector  el2t_fiq_invalid, __kvm_hyp_panic
+        invalid_vector  el2t_error_invalid, __kvm_hyp_panic
+        invalid_vector  el2h_sync_invalid, __kvm_hyp_panic
+        invalid_vector  el2h_irq_invalid, __kvm_hyp_panic
+        invalid_vector  el2h_fiq_invalid, __kvm_hyp_panic
+        invalid_vector  el2h_error_invalid, __kvm_hyp_panic
+        invalid_vector  el1_sync_invalid, __kvm_hyp_panic
+        invalid_vector  el1_irq_invalid, __kvm_hyp_panic
+        invalid_vector  el1_fiq_invalid, __kvm_hyp_panic
+        invalid_vector  el1_error_invalid, __kvm_hyp_panic
+
+el1_sync:                                       // Guest trapped into EL2
+        push    x0, x1
+        push    x2, x3
+
+        mrs     x1, esr_el2
+        lsr     x2, x1, #ESR_EL2_EC_SHIFT
+
+        cmp     x2, #ESR_EL2_EC_HVC64
+        b.ne    el1_trap
+
+        mrs     x3, vttbr_el2                   // If vttbr is valid, the 64bit guest
+        cbnz    x3, el1_trap                    // called HVC
+
+        /* Here, we're pretty sure the host called HVC. */
+        pop     x2, x3
+        pop     x0, x1
+
+        push    lr, xzr
+
+        /*
+         * Compute the function address in EL2, and shuffle the parameters.
+         */
+        kern_hyp_va     x0
+        mov     lr, x0
+        mov     x0, x1
+        mov     x1, x2
+        mov     x2, x3
+        blr     lr
+
+        pop     lr, xzr
+        eret
+
+el1_trap:
+        /*
+         * x1: ESR
+         * x2: ESR_EC
+         */
+        cmp     x2, #ESR_EL2_EC_DABT
+        mov     x0, #ESR_EL2_EC_IABT
+        ccmp    x2, x0, #4, ne
+        b.ne    1f              // Not an abort we care about
+
+        /* This is an abort. Check for permission fault */
+        and     x2, x1, #ESR_EL2_FSC_TYPE
+        cmp     x2, #FSC_PERM
+        b.ne    1f              // Not a permission fault
+
+        /*
+         * Check for Stage-1 page table walk, which is guaranteed
+         * to give a valid HPFAR_EL2.
+         */
+        tbnz    x1, #7, 1f      // S1PTW is set
+
+        /*
+         * Permission fault, HPFAR_EL2 is invalid.
+         * Resolve the IPA the hard way using the guest VA.
+         * Stage-1 translation already validated the memory access rights.
+         * As such, we can use the EL1 translation regime, and don't have
+         * to distinguish between EL0 and EL1 access.
+         */
+        mrs     x2, far_el2
+        at      s1e1r, x2
+        isb
+
+        /* Read result */
+        mrs     x3, par_el1
+        tbnz    x3, #0, 3f              // Bail out if we failed the translation
+        ubfx    x3, x3, #12, #36        // Extract IPA
+        lsl     x3, x3, #4              // and present it like HPFAR
+        b       2f
+
+1:      mrs     x3, hpfar_el2
+        mrs     x2, far_el2
+
+2:      mrs     x0, tpidr_el2
+        str     x1, [x0, #VCPU_ESR_EL2]
+        str     x2, [x0, #VCPU_FAR_EL2]
+        str     x3, [x0, #VCPU_HPFAR_EL2]
+
+        mov     x1, #ARM_EXCEPTION_TRAP
+        b       __kvm_vcpu_return
+
+        /*
+         * Translation failed. Just return to the guest and
+         * let it fault again. Another CPU is probably playing
+         * behind our back.
+         */
+3:      pop     x2, x3
+        pop     x0, x1
+
+        eret
+
+el1_irq:
+        push    x0, x1
+        push    x2, x3
+        mrs     x0, tpidr_el2
+        mov     x1, #ARM_EXCEPTION_IRQ
+        b       __kvm_vcpu_return
+
+        .ltorg
+
+        .align 11
+
+ENTRY(__kvm_hyp_vector)
+        ventry  el2t_sync_invalid               // Synchronous EL2t
+        ventry  el2t_irq_invalid                // IRQ EL2t
+        ventry  el2t_fiq_invalid                // FIQ EL2t
+        ventry  el2t_error_invalid              // Error EL2t
+
+        ventry  el2h_sync_invalid               // Synchronous EL2h
+        ventry  el2h_irq_invalid                // IRQ EL2h
+        ventry  el2h_fiq_invalid                // FIQ EL2h
+        ventry  el2h_error_invalid              // Error EL2h
+
+        ventry  el1_sync                        // Synchronous 64-bit EL1
+        ventry  el1_irq                         // IRQ 64-bit EL1
+        ventry  el1_fiq_invalid                 // FIQ 64-bit EL1
+        ventry  el1_error_invalid               // Error 64-bit EL1
+
+        ventry  el1_sync                        // Synchronous 32-bit EL1
+        ventry  el1_irq                         // IRQ 32-bit EL1
+        ventry  el1_fiq_invalid                 // FIQ 32-bit EL1
+        ventry  el1_error_invalid               // Error 32-bit EL1
+ENDPROC(__kvm_hyp_vector)
+
+__kvm_hyp_code_end:
+        .globl  __kvm_hyp_code_end
+
+        .popsection
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
new file mode 100644
index 000000000000..81a02a8762b0
--- /dev/null
+++ b/arch/arm64/kvm/inject_fault.c
@@ -0,0 +1,203 @@
+/*
+ * Fault injection for both 32 and 64bit guests.
+ *
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on arch/arm/kvm/emulate.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/esr.h>
+
+#define PSTATE_FAULT_BITS_64    (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
+                                 PSR_I_BIT | PSR_D_BIT)
+#define EL1_EXCEPT_SYNC_OFFSET  0x200
+
+static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
+{
+        unsigned long cpsr;
+        unsigned long new_spsr_value = *vcpu_cpsr(vcpu);
+        bool is_thumb = (new_spsr_value & COMPAT_PSR_T_BIT);
+        u32 return_offset = (is_thumb) ? 4 : 0;
+        u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
+
+        cpsr = mode | COMPAT_PSR_I_BIT;
+
+        if (sctlr & (1 << 30))
+                cpsr |= COMPAT_PSR_T_BIT;
+        if (sctlr & (1 << 25))
+                cpsr |= COMPAT_PSR_E_BIT;
+
+        *vcpu_cpsr(vcpu) = cpsr;
+
+        /* Note: These now point to the banked copies */
+        *vcpu_spsr(vcpu) = new_spsr_value;
+        *vcpu_reg(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
+
+        /* Branch to exception vector */
+        if (sctlr & (1 << 13))
+                vect_offset += 0xffff0000;
+        else /* always have security exceptions */
+                vect_offset += vcpu_cp15(vcpu, c12_VBAR);
+
+        *vcpu_pc(vcpu) = vect_offset;
+}
+
+static void inject_undef32(struct kvm_vcpu *vcpu)
+{
+        prepare_fault32(vcpu, COMPAT_PSR_MODE_UND, 4);
+}
+
+/*
+ * Modelled after TakeDataAbortException() and TakePrefetchAbortException
+ * pseudocode.
+ */
+static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
+                         unsigned long addr)
+{
+        u32 vect_offset;
+        u32 *far, *fsr;
+        bool is_lpae;
+
+        if (is_pabt) {
+                vect_offset = 12;
+                far = &vcpu_cp15(vcpu, c6_IFAR);
+                fsr = &vcpu_cp15(vcpu, c5_IFSR);
+        } else { /* !iabt */
+                vect_offset = 16;
+                far = &vcpu_cp15(vcpu, c6_DFAR);
+                fsr = &vcpu_cp15(vcpu, c5_DFSR);
+        }
+
+        prepare_fault32(vcpu, COMPAT_PSR_MODE_ABT | COMPAT_PSR_A_BIT, vect_offset);
+
+        *far = addr;
+
+        /* Give the guest an IMPLEMENTATION DEFINED exception */
+        is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
+        if (is_lpae)
+                *fsr = 1 << 9 | 0x34;
+        else
+                *fsr = 0x14;
+}
+
+static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
+{
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
+        bool is_aarch32;
+        u32 esr = 0;
+
+        is_aarch32 = vcpu_mode_is_32bit(vcpu);
+
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+
+        *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
+        *vcpu_pc(vcpu) = vcpu_sys_reg(vcpu, VBAR_EL1) + EL1_EXCEPT_SYNC_OFFSET;
+
+        vcpu_sys_reg(vcpu, FAR_EL1) = addr;
+
+        /*
+         * Build an {i,d}abort, depending on the level and the
+         * instruction set. Report an external synchronous abort.
+         */
+        if (kvm_vcpu_trap_il_is32bit(vcpu))
+                esr |= ESR_EL1_IL;
+
+        /*
+         * Here, the guest runs in AArch64 mode when in EL1. If we get
+         * an AArch32 fault, it means we managed to trap an EL0 fault.
+         */
+        if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
+                esr |= (ESR_EL1_EC_IABT_EL0 << ESR_EL1_EC_SHIFT);
+        else
+                esr |= (ESR_EL1_EC_IABT_EL1 << ESR_EL1_EC_SHIFT);
+
+        if (!is_iabt)
+                esr |= ESR_EL1_EC_DABT_EL0;
+
+        vcpu_sys_reg(vcpu, ESR_EL1) = esr | ESR_EL2_EC_xABT_xFSR_EXTABT;
+}
+
+static void inject_undef64(struct kvm_vcpu *vcpu)
+{
+        unsigned long cpsr = *vcpu_cpsr(vcpu);
+        u32 esr = (ESR_EL1_EC_UNKNOWN << ESR_EL1_EC_SHIFT);
+
+        *vcpu_spsr(vcpu) = cpsr;
+        *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
+
+        *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
+        *vcpu_pc(vcpu) = vcpu_sys_reg(vcpu, VBAR_EL1) + EL1_EXCEPT_SYNC_OFFSET;
+
+        /*
+         * Build an unknown exception, depending on the instruction
+         * set.
+         */
+        if (kvm_vcpu_trap_il_is32bit(vcpu))
+                esr |= ESR_EL1_IL;
+
+        vcpu_sys_reg(vcpu, ESR_EL1) = esr;
+}
+
+/**
+ * kvm_inject_dabt - inject a data abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        if (!(vcpu->arch.hcr_el2 & HCR_RW))
+                inject_abt32(vcpu, false, addr);
+
+        inject_abt64(vcpu, false, addr);
+}
+
+/**
+ * kvm_inject_pabt - inject a prefetch abort into the guest
+ * @vcpu: The VCPU to receive the undefined exception
+ * @addr: The address to report in the DFAR
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
+{
+        if (!(vcpu->arch.hcr_el2 & HCR_RW))
+                inject_abt32(vcpu, true, addr);
+
+        inject_abt64(vcpu, true, addr);
+}
+
+/**
+ * kvm_inject_undefined - inject an undefined instruction into the guest
+ *
+ * It is assumed that this code is called from the VCPU thread and that the
+ * VCPU therefore is not currently executing guest code.
+ */
+void kvm_inject_undefined(struct kvm_vcpu *vcpu)
+{
+        if (!(vcpu->arch.hcr_el2 & HCR_RW))
+                inject_undef32(vcpu);
+
+        inject_undef64(vcpu);
+}
diff --git a/arch/arm64/kvm/regmap.c b/arch/arm64/kvm/regmap.c
new file mode 100644
index 000000000000..bbc6ae32e4af
--- /dev/null
+++ b/arch/arm64/kvm/regmap.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/emulate.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/ptrace.h>
+
+#define VCPU_NR_MODES 6
+#define REG_OFFSET(_reg) \
+        (offsetof(struct user_pt_regs, _reg) / sizeof(unsigned long))
+
+#define USR_REG_OFFSET(R) REG_OFFSET(compat_usr(R))
+
+static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][16] = {
+        /* USR Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12), USR_REG_OFFSET(13), USR_REG_OFFSET(14),
+                REG_OFFSET(pc)
+        },
+
+        /* FIQ Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7),
+                REG_OFFSET(compat_r8_fiq),  /* r8 */
+                REG_OFFSET(compat_r9_fiq),  /* r9 */
+                REG_OFFSET(compat_r10_fiq), /* r10 */
+                REG_OFFSET(compat_r11_fiq), /* r11 */
+                REG_OFFSET(compat_r12_fiq), /* r12 */
+                REG_OFFSET(compat_sp_fiq),  /* r13 */
+                REG_OFFSET(compat_lr_fiq),  /* r14 */
+                REG_OFFSET(pc)
+        },
+
+        /* IRQ Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(compat_sp_irq), /* r13 */
+                REG_OFFSET(compat_lr_irq), /* r14 */
+                REG_OFFSET(pc)
+        },
+
+        /* SVC Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(compat_sp_svc), /* r13 */
+                REG_OFFSET(compat_lr_svc), /* r14 */
+                REG_OFFSET(pc)
+        },
+
+        /* ABT Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(compat_sp_abt), /* r13 */
+                REG_OFFSET(compat_lr_abt), /* r14 */
+                REG_OFFSET(pc)
+        },
+
+        /* UND Registers */
+        {
+                USR_REG_OFFSET(0), USR_REG_OFFSET(1), USR_REG_OFFSET(2),
+                USR_REG_OFFSET(3), USR_REG_OFFSET(4), USR_REG_OFFSET(5),
+                USR_REG_OFFSET(6), USR_REG_OFFSET(7), USR_REG_OFFSET(8),
+                USR_REG_OFFSET(9), USR_REG_OFFSET(10), USR_REG_OFFSET(11),
+                USR_REG_OFFSET(12),
+                REG_OFFSET(compat_sp_und), /* r13 */
+                REG_OFFSET(compat_lr_und), /* r14 */
+                REG_OFFSET(pc)
+        },
+};
+
+/*
+ * Return a pointer to the register number valid in the current mode of
+ * the virtual CPU.
+ */
+unsigned long *vcpu_reg32(const struct kvm_vcpu *vcpu, u8 reg_num)
+{
+        unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs.regs;
+        unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
+
+        switch (mode) {
+        case COMPAT_PSR_MODE_USR ... COMPAT_PSR_MODE_SVC:
+                mode &= ~PSR_MODE32_BIT; /* 0 ... 3 */
+                break;
+
+        case COMPAT_PSR_MODE_ABT:
+                mode = 4;
+                break;
+
+        case COMPAT_PSR_MODE_UND:
+                mode = 5;
+                break;
+
+        case COMPAT_PSR_MODE_SYS:
+                mode = 0;       /* SYS maps to USR */
+                break;
+
+        default:
+                BUG();
+        }
+
+        return reg_array + vcpu_reg_offsets[mode][reg_num];
+}
+
+/*
+ * Return the SPSR for the current mode of the virtual CPU.
+ */
+unsigned long *vcpu_spsr32(const struct kvm_vcpu *vcpu)
+{
+        unsigned long mode = *vcpu_cpsr(vcpu) & COMPAT_PSR_MODE_MASK;
+        switch (mode) {
+        case COMPAT_PSR_MODE_SVC:
+                mode = KVM_SPSR_SVC;
+                break;
+        case COMPAT_PSR_MODE_ABT:
+                mode = KVM_SPSR_ABT;
+                break;
+        case COMPAT_PSR_MODE_UND:
+                mode = KVM_SPSR_UND;
+                break;
+        case COMPAT_PSR_MODE_IRQ:
+                mode = KVM_SPSR_IRQ;
+                break;
+        case COMPAT_PSR_MODE_FIQ:
+                mode = KVM_SPSR_FIQ;
+                break;
+        default:
+                BUG();
+        }
+
+        return (unsigned long *)&vcpu_gp_regs(vcpu)->spsr[mode];
+}
diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
new file mode 100644
index 000000000000..70a7816535cd
--- /dev/null
+++ b/arch/arm64/kvm/reset.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/reset.c
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Author: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/errno.h>
+#include <linux/kvm_host.h>
+#include <linux/kvm.h>
+
+#include <kvm/arm_arch_timer.h>
+
+#include <asm/cputype.h>
+#include <asm/ptrace.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_coproc.h>
+
+/*
+ * ARMv8 Reset Values
+ */
+static const struct kvm_regs default_regs_reset = {
+        .regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
+                        PSR_F_BIT | PSR_D_BIT),
+};
+
+static const struct kvm_regs default_regs_reset32 = {
+        .regs.pstate = (COMPAT_PSR_MODE_SVC | COMPAT_PSR_A_BIT |
+                        COMPAT_PSR_I_BIT | COMPAT_PSR_F_BIT),
+};
+
+static const struct kvm_irq_level default_vtimer_irq = {
+        .irq    = 27,
+        .level  = 1,
+};
+
+static bool cpu_has_32bit_el1(void)
+{
+        u64 pfr0;
+
+        pfr0 = read_cpuid(ID_AA64PFR0_EL1);
+        return !!(pfr0 & 0x20);
+}
+
+int kvm_arch_dev_ioctl_check_extension(long ext)
+{
+        int r;
+
+        switch (ext) {
+        case KVM_CAP_ARM_EL1_32BIT:
+                r = cpu_has_32bit_el1();
+                break;
+        default:
+                r = 0;
+        }
+
+        return r;
+}
+
+/**
+ * kvm_reset_vcpu - sets core registers and sys_regs to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on
+ * the virtual CPU struct to their architectually defined reset
+ * values.
+ */
+int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
+{
+        const struct kvm_irq_level *cpu_vtimer_irq;
+        const struct kvm_regs *cpu_reset;
+
+        switch (vcpu->arch.target) {
+        default:
+                if (test_bit(KVM_ARM_VCPU_EL1_32BIT, vcpu->arch.features)) {
+                        if (!cpu_has_32bit_el1())
+                                return -EINVAL;
+                        cpu_reset = &default_regs_reset32;
+                        vcpu->arch.hcr_el2 &= ~HCR_RW;
+                } else {
+                        cpu_reset = &default_regs_reset;
+                }
+
+                cpu_vtimer_irq = &default_vtimer_irq;
+                break;
+        }
+
+        /* Reset core registers */
+        memcpy(vcpu_gp_regs(vcpu), cpu_reset, sizeof(*cpu_reset));
+
+        /* Reset system registers */
+        kvm_reset_sys_regs(vcpu);
+
+        /* Reset timer */
+        kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
+
+        return 0;
+}
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
new file mode 100644
index 000000000000..94923609753b
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs.c
@@ -0,0 +1,1050 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/coproc.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.com.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/mm.h>
+#include <linux/kvm_host.h>
+#include <linux/uaccess.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <trace/events/kvm.h>
+
+#include "sys_regs.h"
+
+/*
+ * All of this file is extremly similar to the ARM coproc.c, but the
+ * types are different. My gut feeling is that it should be pretty
+ * easy to merge, but that would be an ABI breakage -- again. VFP
+ * would also need to be abstracted.
+ *
+ * For AArch32, we only take care of what is being trapped. Anything
+ * that has to do with init and userspace access has to go via the
+ * 64bit interface.
+ */
+
+/* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
+static u32 cache_levels;
+
+/* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
+#define CSSELR_MAX 12
+
+/* Which cache CCSIDR represents depends on CSSELR value. */
+static u32 get_ccsidr(u32 csselr)
+{
+        u32 ccsidr;
+
+        /* Make sure noone else changes CSSELR during this! */
+        local_irq_disable();
+        /* Put value into CSSELR */
+        asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
+        isb();
+        /* Read result out of CCSIDR */
+        asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
+        local_irq_enable();
+
+        return ccsidr;
+}
+
+static void do_dc_cisw(u32 val)
+{
+        asm volatile("dc cisw, %x0" : : "r" (val));
+        dsb();
+}
+
+static void do_dc_csw(u32 val)
+{
+        asm volatile("dc csw, %x0" : : "r" (val));
+        dsb();
+}
+
+/* See note at ARM ARM B1.14.4 */
+static bool access_dcsw(struct kvm_vcpu *vcpu,
+                        const struct sys_reg_params *p,
+                        const struct sys_reg_desc *r)
+{
+        unsigned long val;
+        int cpu;
+
+        if (!p->is_write)
+                return read_from_write_only(vcpu, p);
+
+        cpu = get_cpu();
+
+        cpumask_setall(&vcpu->arch.require_dcache_flush);
+        cpumask_clear_cpu(cpu, &vcpu->arch.require_dcache_flush);
+
+        /* If we were already preempted, take the long way around */
+        if (cpu != vcpu->arch.last_pcpu) {
+                flush_cache_all();
+                goto done;
+        }
+
+        val = *vcpu_reg(vcpu, p->Rt);
+
+        switch (p->CRm) {
+        case 6:                 /* Upgrade DCISW to DCCISW, as per HCR.SWIO */
+        case 14:                /* DCCISW */
+                do_dc_cisw(val);
+                break;
+
+        case 10:                /* DCCSW */
+                do_dc_csw(val);
+                break;
+        }
+
+done:
+        put_cpu();
+
+        return true;
+}
+
+/*
+ * We could trap ID_DFR0 and tell the guest we don't support performance
+ * monitoring.  Unfortunately the patch to make the kernel check ID_DFR0 was
+ * NAKed, so it will read the PMCR anyway.
+ *
+ * Therefore we tell the guest we have 0 counters.  Unfortunately, we
+ * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
+ * all PM registers, which doesn't crash the guest kernel at least.
+ */
+static bool pm_fake(struct kvm_vcpu *vcpu,
+                    const struct sys_reg_params *p,
+                    const struct sys_reg_desc *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+        else
+                return read_zero(vcpu, p);
+}
+
+static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+        u64 amair;
+
+        asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
+        vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
+}
+
+static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+        /*
+         * Simply map the vcpu_id into the Aff0 field of the MPIDR.
+         */
+        vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
+}
+
+/*
+ * Architected system registers.
+ * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
+ */
+static const struct sys_reg_desc sys_reg_descs[] = {
+        /* DC ISW */
+        { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
+          access_dcsw },
+        /* DC CSW */
+        { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
+          access_dcsw },
+        /* DC CISW */
+        { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
+          access_dcsw },
+
+        /* TEECR32_EL1 */
+        { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
+          NULL, reset_val, TEECR32_EL1, 0 },
+        /* TEEHBR32_EL1 */
+        { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
+          NULL, reset_val, TEEHBR32_EL1, 0 },
+        /* DBGVCR32_EL2 */
+        { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
+          NULL, reset_val, DBGVCR32_EL2, 0 },
+
+        /* MPIDR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
+          NULL, reset_mpidr, MPIDR_EL1 },
+        /* SCTLR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
+          NULL, reset_val, SCTLR_EL1, 0x00C50078 },
+        /* CPACR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
+          NULL, reset_val, CPACR_EL1, 0 },
+        /* TTBR0_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
+          NULL, reset_unknown, TTBR0_EL1 },
+        /* TTBR1_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
+          NULL, reset_unknown, TTBR1_EL1 },
+        /* TCR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
+          NULL, reset_val, TCR_EL1, 0 },
+
+        /* AFSR0_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
+          NULL, reset_unknown, AFSR0_EL1 },
+        /* AFSR1_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
+          NULL, reset_unknown, AFSR1_EL1 },
+        /* ESR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
+          NULL, reset_unknown, ESR_EL1 },
+        /* FAR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
+          NULL, reset_unknown, FAR_EL1 },
+
+        /* PMINTENSET_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
+          pm_fake },
+        /* PMINTENCLR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
+          pm_fake },
+
+        /* MAIR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
+          NULL, reset_unknown, MAIR_EL1 },
+        /* AMAIR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
+          NULL, reset_amair_el1, AMAIR_EL1 },
+
+        /* VBAR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
+          NULL, reset_val, VBAR_EL1, 0 },
+        /* CONTEXTIDR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
+          NULL, reset_val, CONTEXTIDR_EL1, 0 },
+        /* TPIDR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
+          NULL, reset_unknown, TPIDR_EL1 },
+
+        /* CNTKCTL_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
+          NULL, reset_val, CNTKCTL_EL1, 0},
+
+        /* CSSELR_EL1 */
+        { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
+          NULL, reset_unknown, CSSELR_EL1 },
+
+        /* PMCR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
+          pm_fake },
+        /* PMCNTENSET_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
+          pm_fake },
+        /* PMCNTENCLR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
+          pm_fake },
+        /* PMOVSCLR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
+          pm_fake },
+        /* PMSWINC_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
+          pm_fake },
+        /* PMSELR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
+          pm_fake },
+        /* PMCEID0_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
+          pm_fake },
+        /* PMCEID1_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
+          pm_fake },
+        /* PMCCNTR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
+          pm_fake },
+        /* PMXEVTYPER_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
+          pm_fake },
+        /* PMXEVCNTR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
+          pm_fake },
+        /* PMUSERENR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
+          pm_fake },
+        /* PMOVSSET_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
+          pm_fake },
+
+        /* TPIDR_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
+          NULL, reset_unknown, TPIDR_EL0 },
+        /* TPIDRRO_EL0 */
+        { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
+          NULL, reset_unknown, TPIDRRO_EL0 },
+
+        /* DACR32_EL2 */
+        { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
+          NULL, reset_unknown, DACR32_EL2 },
+        /* IFSR32_EL2 */
+        { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
+          NULL, reset_unknown, IFSR32_EL2 },
+        /* FPEXC32_EL2 */
+        { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
+          NULL, reset_val, FPEXC32_EL2, 0x70 },
+};
+
+/* Trapped cp15 registers */
+static const struct sys_reg_desc cp15_regs[] = {
+        /*
+         * DC{C,I,CI}SW operations:
+         */
+        { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
+        { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
+        { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 0), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 1), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 2), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 3), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 5), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 6), pm_fake },
+        { Op1( 0), CRn( 9), CRm(12), Op2( 7), pm_fake },
+        { Op1( 0), CRn( 9), CRm(13), Op2( 0), pm_fake },
+        { Op1( 0), CRn( 9), CRm(13), Op2( 1), pm_fake },
+        { Op1( 0), CRn( 9), CRm(13), Op2( 2), pm_fake },
+        { Op1( 0), CRn( 9), CRm(14), Op2( 0), pm_fake },
+        { Op1( 0), CRn( 9), CRm(14), Op2( 1), pm_fake },
+        { Op1( 0), CRn( 9), CRm(14), Op2( 2), pm_fake },
+};
+
+/* Target specific emulation tables */
+static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
+
+void kvm_register_target_sys_reg_table(unsigned int target,
+                                       struct kvm_sys_reg_target_table *table)
+{
+        target_tables[target] = table;
+}
+
+/* Get specific register table for this target. */
+static const struct sys_reg_desc *get_target_table(unsigned target,
+                                                   bool mode_is_64,
+                                                   size_t *num)
+{
+        struct kvm_sys_reg_target_table *table;
+
+        table = target_tables[target];
+        if (mode_is_64) {
+                *num = table->table64.num;
+                return table->table64.table;
+        } else {
+                *num = table->table32.num;
+                return table->table32.table;
+        }
+}
+
+static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
+                                         const struct sys_reg_desc table[],
+                                         unsigned int num)
+{
+        unsigned int i;
+
+        for (i = 0; i < num; i++) {
+                const struct sys_reg_desc *r = &table[i];
+
+                if (params->Op0 != r->Op0)
+                        continue;
+                if (params->Op1 != r->Op1)
+                        continue;
+                if (params->CRn != r->CRn)
+                        continue;
+                if (params->CRm != r->CRm)
+                        continue;
+                if (params->Op2 != r->Op2)
+                        continue;
+
+                return r;
+        }
+        return NULL;
+}
+
+int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+static void emulate_cp15(struct kvm_vcpu *vcpu,
+                         const struct sys_reg_params *params)
+{
+        size_t num;
+        const struct sys_reg_desc *table, *r;
+
+        table = get_target_table(vcpu->arch.target, false, &num);
+
+        /* Search target-specific then generic table. */
+        r = find_reg(params, table, num);
+        if (!r)
+                r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
+
+        if (likely(r)) {
+                /*
+                 * Not having an accessor means that we have
+                 * configured a trap that we don't know how to
+                 * handle. This certainly qualifies as a gross bug
+                 * that should be fixed right away.
+                 */
+                BUG_ON(!r->access);
+
+                if (likely(r->access(vcpu, params, r))) {
+                        /* Skip instruction, since it was emulated */
+                        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+                        return;
+                }
+                /* If access function fails, it should complain. */
+        }
+
+        kvm_err("Unsupported guest CP15 access at: %08lx\n", *vcpu_pc(vcpu));
+        print_sys_reg_instr(params);
+        kvm_inject_undefined(vcpu);
+}
+
+/**
+ * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct sys_reg_params params;
+        u32 hsr = kvm_vcpu_get_hsr(vcpu);
+        int Rt2 = (hsr >> 10) & 0xf;
+
+        params.CRm = (hsr >> 1) & 0xf;
+        params.Rt = (hsr >> 5) & 0xf;
+        params.is_write = ((hsr & 1) == 0);
+
+        params.Op0 = 0;
+        params.Op1 = (hsr >> 16) & 0xf;
+        params.Op2 = 0;
+        params.CRn = 0;
+
+        /*
+         * Massive hack here. Store Rt2 in the top 32bits so we only
+         * have one register to deal with. As we use the same trap
+         * backends between AArch32 and AArch64, we get away with it.
+         */
+        if (params.is_write) {
+                u64 val = *vcpu_reg(vcpu, params.Rt);
+                val &= 0xffffffff;
+                val |= *vcpu_reg(vcpu, Rt2) << 32;
+                *vcpu_reg(vcpu, params.Rt) = val;
+        }
+
+        emulate_cp15(vcpu, &params);
+
+        /* Do the opposite hack for the read side */
+        if (!params.is_write) {
+                u64 val = *vcpu_reg(vcpu, params.Rt);
+                val >>= 32;
+                *vcpu_reg(vcpu, Rt2) = val;
+        }
+
+        return 1;
+}
+
+/**
+ * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct sys_reg_params params;
+        u32 hsr = kvm_vcpu_get_hsr(vcpu);
+
+        params.CRm = (hsr >> 1) & 0xf;
+        params.Rt  = (hsr >> 5) & 0xf;
+        params.is_write = ((hsr & 1) == 0);
+        params.CRn = (hsr >> 10) & 0xf;
+        params.Op0 = 0;
+        params.Op1 = (hsr >> 14) & 0x7;
+        params.Op2 = (hsr >> 17) & 0x7;
+
+        emulate_cp15(vcpu, &params);
+        return 1;
+}
+
+static int emulate_sys_reg(struct kvm_vcpu *vcpu,
+                           const struct sys_reg_params *params)
+{
+        size_t num;
+        const struct sys_reg_desc *table, *r;
+
+        table = get_target_table(vcpu->arch.target, true, &num);
+
+        /* Search target-specific then generic table. */
+        r = find_reg(params, table, num);
+        if (!r)
+                r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+        if (likely(r)) {
+                /*
+                 * Not having an accessor means that we have
+                 * configured a trap that we don't know how to
+                 * handle. This certainly qualifies as a gross bug
+                 * that should be fixed right away.
+                 */
+                BUG_ON(!r->access);
+
+                if (likely(r->access(vcpu, params, r))) {
+                        /* Skip instruction, since it was emulated */
+                        kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+                        return 1;
+                }
+                /* If access function fails, it should complain. */
+        } else {
+                kvm_err("Unsupported guest sys_reg access at: %lx\n",
+                        *vcpu_pc(vcpu));
+                print_sys_reg_instr(params);
+        }
+        kvm_inject_undefined(vcpu);
+        return 1;
+}
+
+static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
+                              const struct sys_reg_desc *table, size_t num)
+{
+        unsigned long i;
+
+        for (i = 0; i < num; i++)
+                if (table[i].reset)
+                        table[i].reset(vcpu, &table[i]);
+}
+
+/**
+ * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
+ * @vcpu: The VCPU pointer
+ * @run:  The kvm_run struct
+ */
+int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+        struct sys_reg_params params;
+        unsigned long esr = kvm_vcpu_get_hsr(vcpu);
+
+        params.Op0 = (esr >> 20) & 3;
+        params.Op1 = (esr >> 14) & 0x7;
+        params.CRn = (esr >> 10) & 0xf;
+        params.CRm = (esr >> 1) & 0xf;
+        params.Op2 = (esr >> 17) & 0x7;
+        params.Rt = (esr >> 5) & 0x1f;
+        params.is_write = !(esr & 1);
+
+        return emulate_sys_reg(vcpu, &params);
+}
+
+/******************************************************************************
+ * Userspace API
+ *****************************************************************************/
+
+static bool index_to_params(u64 id, struct sys_reg_params *params)
+{
+        switch (id & KVM_REG_SIZE_MASK) {
+        case KVM_REG_SIZE_U64:
+                /* Any unused index bits means it's not valid. */
+                if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
+                              | KVM_REG_ARM_COPROC_MASK
+                              | KVM_REG_ARM64_SYSREG_OP0_MASK
+                              | KVM_REG_ARM64_SYSREG_OP1_MASK
+                              | KVM_REG_ARM64_SYSREG_CRN_MASK
+                              | KVM_REG_ARM64_SYSREG_CRM_MASK
+                              | KVM_REG_ARM64_SYSREG_OP2_MASK))
+                        return false;
+                params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
+                               >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
+                params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
+                               >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
+                params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
+                               >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
+                params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
+                               >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
+                params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
+                               >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
+                return true;
+        default:
+                return false;
+        }
+}
+
+/* Decode an index value, and find the sys_reg_desc entry. */
+static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
+                                                    u64 id)
+{
+        size_t num;
+        const struct sys_reg_desc *table, *r;
+        struct sys_reg_params params;
+
+        /* We only do sys_reg for now. */
+        if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
+                return NULL;
+
+        if (!index_to_params(id, &params))
+                return NULL;
+
+        table = get_target_table(vcpu->arch.target, true, &num);
+        r = find_reg(&params, table, num);
+        if (!r)
+                r = find_reg(&params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+        /* Not saved in the sys_reg array? */
+        if (r && !r->reg)
+                r = NULL;
+
+        return r;
+}
+
+/*
+ * These are the invariant sys_reg registers: we let the guest see the
+ * host versions of these, so they're part of the guest state.
+ *
+ * A future CPU may provide a mechanism to present different values to
+ * the guest, or a future kvm may trap them.
+ */
+
+#define FUNCTION_INVARIANT(reg)                                         \
+        static void get_##reg(struct kvm_vcpu *v,                       \
+                              const struct sys_reg_desc *r)             \
+        {                                                               \
+                u64 val;                                                \
+                                                                        \
+                asm volatile("mrs %0, " __stringify(reg) "\n"           \
+                             : "=r" (val));                             \
+                ((struct sys_reg_desc *)r)->val = val;                  \
+        }
+
+FUNCTION_INVARIANT(midr_el1)
+FUNCTION_INVARIANT(ctr_el0)
+FUNCTION_INVARIANT(revidr_el1)
+FUNCTION_INVARIANT(id_pfr0_el1)
+FUNCTION_INVARIANT(id_pfr1_el1)
+FUNCTION_INVARIANT(id_dfr0_el1)
+FUNCTION_INVARIANT(id_afr0_el1)
+FUNCTION_INVARIANT(id_mmfr0_el1)
+FUNCTION_INVARIANT(id_mmfr1_el1)
+FUNCTION_INVARIANT(id_mmfr2_el1)
+FUNCTION_INVARIANT(id_mmfr3_el1)
+FUNCTION_INVARIANT(id_isar0_el1)
+FUNCTION_INVARIANT(id_isar1_el1)
+FUNCTION_INVARIANT(id_isar2_el1)
+FUNCTION_INVARIANT(id_isar3_el1)
+FUNCTION_INVARIANT(id_isar4_el1)
+FUNCTION_INVARIANT(id_isar5_el1)
+FUNCTION_INVARIANT(clidr_el1)
+FUNCTION_INVARIANT(aidr_el1)
+
+/* ->val is filled in by kvm_sys_reg_table_init() */
+static struct sys_reg_desc invariant_sys_regs[] = {
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
+          NULL, get_midr_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
+          NULL, get_revidr_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
+          NULL, get_id_pfr0_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
+          NULL, get_id_pfr1_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
+          NULL, get_id_dfr0_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
+          NULL, get_id_afr0_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
+          NULL, get_id_mmfr0_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
+          NULL, get_id_mmfr1_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
+          NULL, get_id_mmfr2_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
+          NULL, get_id_mmfr3_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
+          NULL, get_id_isar0_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
+          NULL, get_id_isar1_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
+          NULL, get_id_isar2_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
+          NULL, get_id_isar3_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
+          NULL, get_id_isar4_el1 },
+        { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
+          NULL, get_id_isar5_el1 },
+        { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
+          NULL, get_clidr_el1 },
+        { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
+          NULL, get_aidr_el1 },
+        { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
+          NULL, get_ctr_el0 },
+};
+
+static int reg_from_user(void *val, const void __user *uaddr, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+
+static int reg_to_user(void __user *uaddr, const void *val, u64 id)
+{
+        /* This Just Works because we are little endian. */
+        if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
+                return -EFAULT;
+        return 0;
+}
+
+static int get_invariant_sys_reg(u64 id, void __user *uaddr)
+{
+        struct sys_reg_params params;
+        const struct sys_reg_desc *r;
+
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+
+        r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
+        if (!r)
+                return -ENOENT;
+
+        return reg_to_user(uaddr, &r->val, id);
+}
+
+static int set_invariant_sys_reg(u64 id, void __user *uaddr)
+{
+        struct sys_reg_params params;
+        const struct sys_reg_desc *r;
+        int err;
+        u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
+
+        if (!index_to_params(id, &params))
+                return -ENOENT;
+        r = find_reg(&params, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
+        if (!r)
+                return -ENOENT;
+
+        err = reg_from_user(&val, uaddr, id);
+        if (err)
+                return err;
+
+        /* This is what we mean by invariant: you can't change it. */
+        if (r->val != val)
+                return -EINVAL;
+
+        return 0;
+}
+
+static bool is_valid_cache(u32 val)
+{
+        u32 level, ctype;
+
+        if (val >= CSSELR_MAX)
+                return -ENOENT;
+
+        /* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */
+        level = (val >> 1);
+        ctype = (cache_levels >> (level * 3)) & 7;
+
+        switch (ctype) {
+        case 0: /* No cache */
+                return false;
+        case 1: /* Instruction cache only */
+                return (val & 1);
+        case 2: /* Data cache only */
+        case 4: /* Unified cache */
+                return !(val & 1);
+        case 3: /* Separate instruction and data caches */
+                return true;
+        default: /* Reserved: we can't know instruction or data. */
+                return false;
+        }
+}
+
+static int demux_c15_get(u64 id, void __user *uaddr)
+{
+        u32 val;
+        u32 __user *uval = uaddr;
+
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+
+                return put_user(get_ccsidr(val), uval);
+        default:
+                return -ENOENT;
+        }
+}
+
+static int demux_c15_set(u64 id, void __user *uaddr)
+{
+        u32 val, newval;
+        u32 __user *uval = uaddr;
+
+        /* Fail if we have unknown bits set. */
+        if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
+                   | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
+                return -ENOENT;
+
+        switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
+        case KVM_REG_ARM_DEMUX_ID_CCSIDR:
+                if (KVM_REG_SIZE(id) != 4)
+                        return -ENOENT;
+                val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
+                        >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
+                if (!is_valid_cache(val))
+                        return -ENOENT;
+
+                if (get_user(newval, uval))
+                        return -EFAULT;
+
+                /* This is also invariant: you can't change it. */
+                if (newval != get_ccsidr(val))
+                        return -EINVAL;
+                return 0;
+        default:
+                return -ENOENT;
+        }
+}
+
+int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct sys_reg_desc *r;
+        void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_get(reg->id, uaddr);
+
+        if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
+                return -ENOENT;
+
+        r = index_to_sys_reg_desc(vcpu, reg->id);
+        if (!r)
+                return get_invariant_sys_reg(reg->id, uaddr);
+
+        return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
+}
+
+int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+        const struct sys_reg_desc *r;
+        void __user *uaddr = (void __user *)(unsigned long)reg->addr;
+
+        if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
+                return demux_c15_set(reg->id, uaddr);
+
+        if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
+                return -ENOENT;
+
+        r = index_to_sys_reg_desc(vcpu, reg->id);
+        if (!r)
+                return set_invariant_sys_reg(reg->id, uaddr);
+
+        return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
+}
+
+static unsigned int num_demux_regs(void)
+{
+        unsigned int i, count = 0;
+
+        for (i = 0; i < CSSELR_MAX; i++)
+                if (is_valid_cache(i))
+                        count++;
+
+        return count;
+}
+
+static int write_demux_regids(u64 __user *uindices)
+{
+        u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
+        unsigned int i;
+
+        val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
+        for (i = 0; i < CSSELR_MAX; i++) {
+                if (!is_valid_cache(i))
+                        continue;
+                if (put_user(val | i, uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+        return 0;
+}
+
+static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
+{
+        return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
+                KVM_REG_ARM64_SYSREG |
+                (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
+                (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
+                (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
+                (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
+                (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
+}
+
+static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
+{
+        if (!*uind)
+                return true;
+
+        if (put_user(sys_reg_to_index(reg), *uind))
+                return false;
+
+        (*uind)++;
+        return true;
+}
+
+/* Assumed ordered tables, see kvm_sys_reg_table_init. */
+static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
+{
+        const struct sys_reg_desc *i1, *i2, *end1, *end2;
+        unsigned int total = 0;
+        size_t num;
+
+        /* We check for duplicates here, to allow arch-specific overrides. */
+        i1 = get_target_table(vcpu->arch.target, true, &num);
+        end1 = i1 + num;
+        i2 = sys_reg_descs;
+        end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
+
+        BUG_ON(i1 == end1 || i2 == end2);
+
+        /* Walk carefully, as both tables may refer to the same register. */
+        while (i1 || i2) {
+                int cmp = cmp_sys_reg(i1, i2);
+                /* target-specific overrides generic entry. */
+                if (cmp <= 0) {
+                        /* Ignore registers we trap but don't save. */
+                        if (i1->reg) {
+                                if (!copy_reg_to_user(i1, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                } else {
+                        /* Ignore registers we trap but don't save. */
+                        if (i2->reg) {
+                                if (!copy_reg_to_user(i2, &uind))
+                                        return -EFAULT;
+                                total++;
+                        }
+                }
+
+                if (cmp <= 0 && ++i1 == end1)
+                        i1 = NULL;
+                if (cmp >= 0 && ++i2 == end2)
+                        i2 = NULL;
+        }
+        return total;
+}
+
+unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
+{
+        return ARRAY_SIZE(invariant_sys_regs)
+                + num_demux_regs()
+                + walk_sys_regs(vcpu, (u64 __user *)NULL);
+}
+
+int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
+{
+        unsigned int i;
+        int err;
+
+        /* Then give them all the invariant registers' indices. */
+        for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
+                if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
+                        return -EFAULT;
+                uindices++;
+        }
+
+        err = walk_sys_regs(vcpu, uindices);
+        if (err < 0)
+                return err;
+        uindices += err;
+
+        return write_demux_regids(uindices);
+}
+
+void kvm_sys_reg_table_init(void)
+{
+        unsigned int i;
+        struct sys_reg_desc clidr;
+
+        /* Make sure tables are unique and in order. */
+        for (i = 1; i < ARRAY_SIZE(sys_reg_descs); i++)
+                BUG_ON(cmp_sys_reg(&sys_reg_descs[i-1], &sys_reg_descs[i]) >= 0);
+
+        /* We abuse the reset function to overwrite the table itself. */
+        for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
+                invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
+
+        /*
+         * CLIDR format is awkward, so clean it up.  See ARM B4.1.20:
+         *
+         *   If software reads the Cache Type fields from Ctype1
+         *   upwards, once it has seen a value of 0b000, no caches
+         *   exist at further-out levels of the hierarchy. So, for
+         *   example, if Ctype3 is the first Cache Type field with a
+         *   value of 0b000, the values of Ctype4 to Ctype7 must be
+         *   ignored.
+         */
+        get_clidr_el1(NULL, &clidr); /* Ugly... */
+        cache_levels = clidr.val;
+        for (i = 0; i < 7; i++)
+                if (((cache_levels >> (i*3)) & 7) == 0)
+                        break;
+        /* Clear all higher bits. */
+        cache_levels &= (1 << (i*3))-1;
+}
+
+/**
+ * kvm_reset_sys_regs - sets system registers to reset value
+ * @vcpu: The VCPU pointer
+ *
+ * This function finds the right table above and sets the registers on the
+ * virtual CPU struct to their architecturally defined reset values.
+ */
+void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
+{
+        size_t num;
+        const struct sys_reg_desc *table;
+
+        /* Catch someone adding a register without putting in reset entry. */
+        memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
+
+        /* Generic chip reset first (so target could override). */
+        reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
+
+        table = get_target_table(vcpu->arch.target, true, &num);
+        reset_sys_reg_descs(vcpu, table, num);
+
+        for (num = 1; num < NR_SYS_REGS; num++)
+                if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
+                        panic("Didn't reset vcpu_sys_reg(%zi)", num);
+}
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
new file mode 100644
index 000000000000..d50d3722998e
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Derived from arch/arm/kvm/coproc.h
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __ARM64_KVM_SYS_REGS_LOCAL_H__
+#define __ARM64_KVM_SYS_REGS_LOCAL_H__
+
+struct sys_reg_params {
+        u8      Op0;
+        u8      Op1;
+        u8      CRn;
+        u8      CRm;
+        u8      Op2;
+        u8      Rt;
+        bool    is_write;
+};
+
+struct sys_reg_desc {
+        /* MRS/MSR instruction which accesses it. */
+        u8      Op0;
+        u8      Op1;
+        u8      CRn;
+        u8      CRm;
+        u8      Op2;
+
+        /* Trapped access from guest, if non-NULL. */
+        bool (*access)(struct kvm_vcpu *,
+                       const struct sys_reg_params *,
+                       const struct sys_reg_desc *);
+
+        /* Initialization for vcpu. */
+        void (*reset)(struct kvm_vcpu *, const struct sys_reg_desc *);
+
+        /* Index into sys_reg[], or 0 if we don't need to save it. */
+        int reg;
+
+        /* Value (usually reset value) */
+        u64 val;
+};
+
+static inline void print_sys_reg_instr(const struct sys_reg_params *p)
+{
+        /* Look, we even formatted it for you to paste into the table! */
+        kvm_pr_unimpl(" { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
+                      p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
+}
+
+static inline bool ignore_write(struct kvm_vcpu *vcpu,
+                                const struct sys_reg_params *p)
+{
+        return true;
+}
+
+static inline bool read_zero(struct kvm_vcpu *vcpu,
+                             const struct sys_reg_params *p)
+{
+        *vcpu_reg(vcpu, p->Rt) = 0;
+        return true;
+}
+
+static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
+                                      const struct sys_reg_params *params)
+{
+        kvm_debug("sys_reg write to read-only register at: %lx\n",
+                  *vcpu_pc(vcpu));
+        print_sys_reg_instr(params);
+        return false;
+}
+
+static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
+                                        const struct sys_reg_params *params)
+{
+        kvm_debug("sys_reg read to write-only register at: %lx\n",
+                  *vcpu_pc(vcpu));
+        print_sys_reg_instr(params);
+        return false;
+}
+
+/* Reset functions */
+static inline void reset_unknown(struct kvm_vcpu *vcpu,
+                                 const struct sys_reg_desc *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= NR_SYS_REGS);
+        vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
+}
+
+static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+        BUG_ON(!r->reg);
+        BUG_ON(r->reg >= NR_SYS_REGS);
+        vcpu_sys_reg(vcpu, r->reg) = r->val;
+}
+
+static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
+                              const struct sys_reg_desc *i2)
+{
+        BUG_ON(i1 == i2);
+        if (!i1)
+                return 1;
+        else if (!i2)
+                return -1;
+        if (i1->Op0 != i2->Op0)
+                return i1->Op0 - i2->Op0;
+        if (i1->Op1 != i2->Op1)
+                return i1->Op1 - i2->Op1;
+        if (i1->CRn != i2->CRn)
+                return i1->CRn - i2->CRn;
+        if (i1->CRm != i2->CRm)
+                return i1->CRm - i2->CRm;
+        return i1->Op2 - i2->Op2;
+}
+
+
+#define Op0(_x)         .Op0 = _x
+#define Op1(_x)         .Op1 = _x
+#define CRn(_x)         .CRn = _x
+#define CRm(_x)         .CRm = _x
+#define Op2(_x)         .Op2 = _x
+
+#endif /* __ARM64_KVM_SYS_REGS_LOCAL_H__ */
diff --git a/arch/arm64/kvm/sys_regs_generic_v8.c b/arch/arm64/kvm/sys_regs_generic_v8.c
new file mode 100644
index 000000000000..4268ab9356b1
--- /dev/null
+++ b/arch/arm64/kvm/sys_regs_generic_v8.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (C) 2012,2013 - ARM Ltd
+ * Author: Marc Zyngier <marc.zyngier@arm.com>
+ *
+ * Based on arch/arm/kvm/coproc_a15.c:
+ * Copyright (C) 2012 - Virtual Open Systems and Columbia University
+ * Authors: Rusty Russell <rusty@rustcorp.au>
+ *          Christoffer Dall <c.dall@virtualopensystems.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kvm_host.h>
+#include <asm/cputype.h>
+#include <asm/kvm_arm.h>
+#include <asm/kvm_asm.h>
+#include <asm/kvm_host.h>
+#include <asm/kvm_emulate.h>
+#include <asm/kvm_coproc.h>
+#include <linux/init.h>
+
+#include "sys_regs.h"
+
+static bool access_actlr(struct kvm_vcpu *vcpu,
+                         const struct sys_reg_params *p,
+                         const struct sys_reg_desc *r)
+{
+        if (p->is_write)
+                return ignore_write(vcpu, p);
+
+        *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, ACTLR_EL1);
+        return true;
+}
+
+static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+        u64 actlr;
+
+        asm volatile("mrs %0, actlr_el1\n" : "=r" (actlr));
+        vcpu_sys_reg(vcpu, ACTLR_EL1) = actlr;
+}
+
+/*
+ * Implementation specific sys-reg registers.
+ * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
+ */
+static const struct sys_reg_desc genericv8_sys_regs[] = {
+        /* ACTLR_EL1 */
+        { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
+          access_actlr, reset_actlr, ACTLR_EL1 },
+};
+
+static const struct sys_reg_desc genericv8_cp15_regs[] = {
+        /* ACTLR */
+        { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
+          access_actlr },
+};
+
+static struct kvm_sys_reg_target_table genericv8_target_table = {
+        .table64 = {
+                .table = genericv8_sys_regs,
+                .num = ARRAY_SIZE(genericv8_sys_regs),
+        },
+        .table32 = {
+                .table = genericv8_cp15_regs,
+                .num = ARRAY_SIZE(genericv8_cp15_regs),
+        },
+};
+
+static int __init sys_reg_genericv8_init(void)
+{
+        unsigned int i;
+
+        for (i = 1; i < ARRAY_SIZE(genericv8_sys_regs); i++)
+                BUG_ON(cmp_sys_reg(&genericv8_sys_regs[i-1],
+                               &genericv8_sys_regs[i]) >= 0);
+
+        kvm_register_target_sys_reg_table(KVM_ARM_TARGET_AEM_V8,
+                                          &genericv8_target_table);
+        kvm_register_target_sys_reg_table(KVM_ARM_TARGET_FOUNDATION_V8,
+                                          &genericv8_target_table);
+        kvm_register_target_sys_reg_table(KVM_ARM_TARGET_CORTEX_A57,
+                                          &genericv8_target_table);
+        return 0;
+}
+late_initcall(sys_reg_genericv8_init);
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index 3140a2abcdc2..b51d36401d83 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -2,3 +2,4 @@ obj-y				:= dma-mapping.o extable.o fault.o init.o \
                                    cache.o copypage.o flush.o \
                                    ioremap.o mmap.o pgd.o mmu.o \
                                    context.o tlb.o proc.o
+obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 1426468b77f3..0ecac8980aae 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -365,17 +365,6 @@ static int __kprobes do_translation_fault(unsigned long addr,
 }
 
 /*
- * Some section permission faults need to be handled gracefully.  They can
- * happen due to a __{get,put}_user during an oops.
- */
-static int do_sect_fault(unsigned long addr, unsigned int esr,
-                         struct pt_regs *regs)
-{
-        do_bad_area(addr, esr, regs);
-        return 0;
-}
-
-/*
  * This abort handler always returns "fault".
  */
 static int do_bad(unsigned long addr, unsigned int esr, struct pt_regs *regs)
@@ -398,12 +387,12 @@ static struct fault_info {
         { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "level 2 translation fault"     },
         { do_page_fault,        SIGSEGV, SEGV_MAPERR,   "level 3 translation fault"     },
         { do_bad,               SIGBUS,  0,             "reserved access flag fault"    },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 access flag fault"     },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 1 access flag fault"     },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 access flag fault"     },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 access flag fault"     },
         { do_bad,               SIGBUS,  0,             "reserved permission fault"     },
-        { do_bad,               SIGSEGV, SEGV_ACCERR,   "level 1 permission fault"      },
-        { do_sect_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 1 permission fault"      },
+        { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 2 permission fault"      },
         { do_page_fault,        SIGSEGV, SEGV_ACCERR,   "level 3 permission fault"      },
         { do_bad,               SIGBUS,  0,             "synchronous external abort"    },
         { do_bad,               SIGBUS,  0,             "asynchronous external abort"   },
diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
index 88611c3a421a..e4193e3adc7f 100644
--- a/arch/arm64/mm/flush.c
+++ b/arch/arm64/mm/flush.c
@@ -70,23 +70,16 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
 #endif
 }
 
-void __flush_dcache_page(struct page *page)
-{
-        __flush_dcache_area(page_address(page), PAGE_SIZE);
-}
-
 void __sync_icache_dcache(pte_t pte, unsigned long addr)
 {
-        unsigned long pfn;
-        struct page *page;
+        struct page *page = pte_page(pte);
 
-        pfn = pte_pfn(pte);
-        if (!pfn_valid(pfn))
+        /* no flushing needed for anonymous pages */
+        if (!page_mapping(page))
                 return;
 
-        page = pfn_to_page(pfn);
         if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
-                __flush_dcache_page(page);
+                __flush_dcache_area(page_address(page), PAGE_SIZE);
                 __flush_icache_all();
         } else if (icache_is_aivivt()) {
                 __flush_icache_all();
@@ -94,28 +87,14 @@ void __sync_icache_dcache(pte_t pte, unsigned long addr)
 }
 
 /*
- * Ensure cache coherency between kernel mapping and userspace mapping of this
- * page.
+ * This function is called when a page has been modified by the kernel. Mark
+ * it as dirty for later flushing when mapped in user space (if executable,
+ * see __sync_icache_dcache).
  */
 void flush_dcache_page(struct page *page)
 {
-        struct address_space *mapping;
-
-        /*
-         * The zero page is never written to, so never has any dirty cache
-         * lines, and therefore never needs to be flushed.
-         */
-        if (page == ZERO_PAGE(0))
-                return;
-
-        mapping = page_mapping(page);
-        if (mapping && mapping_mapped(mapping)) {
-                __flush_dcache_page(page);
-                __flush_icache_all();
-                set_bit(PG_dcache_clean, &page->flags);
-        } else {
+        if (test_bit(PG_dcache_clean, &page->flags))
                 clear_bit(PG_dcache_clean, &page->flags);
-        }
 }
 EXPORT_SYMBOL(flush_dcache_page);
 
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
new file mode 100644
index 000000000000..2fc8258bab2d
--- /dev/null
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -0,0 +1,70 @@
+/*
+ * arch/arm64/mm/hugetlbpage.c
+ *
+ * Copyright (C) 2013 Linaro Ltd.
+ *
+ * Based on arch/x86/mm/hugetlbpage.c.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/hugetlb.h>
+#include <linux/pagemap.h>
+#include <linux/err.h>
+#include <linux/sysctl.h>
+#include <asm/mman.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+#ifndef CONFIG_ARCH_WANT_HUGE_PMD_SHARE
+int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
+{
+        return 0;
+}
+#endif
+
+struct page *follow_huge_addr(struct mm_struct *mm, unsigned long address,
+                              int write)
+{
+        return ERR_PTR(-EINVAL);
+}
+
+int pmd_huge(pmd_t pmd)
+{
+        return !(pmd_val(pmd) & PMD_TABLE_BIT);
+}
+
+int pud_huge(pud_t pud)
+{
+        return !(pud_val(pud) & PUD_TABLE_BIT);
+}
+
+static __init int setup_hugepagesz(char *opt)
+{
+        unsigned long ps = memparse(opt, &opt);
+        if (ps == PMD_SIZE) {
+                hugetlb_add_hstate(PMD_SHIFT - PAGE_SHIFT);
+        } else if (ps == PUD_SIZE) {
+                hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT);
+        } else {
+                pr_err("hugepagesz: Unsupported page size %lu M\n", ps >> 20);
+                return 0;
+        }
+        return 1;
+}
+__setup("hugepagesz=", setup_hugepagesz);
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index f497ca77925a..67e8d7ce3fe7 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -197,14 +197,6 @@ void __init bootmem_init(void)
         max_pfn = max_low_pfn = max;
 }
 
-/*
- * Poison init memory with an undefined instruction (0x0).
- */
-static inline void poison_init_mem(void *s, size_t count)
-{
-        memset(s, 0, count);
-}
-
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
 static inline void free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 {
@@ -280,59 +272,17 @@ static void __init free_unused_memmap(void)
  */
 void __init mem_init(void)
 {
-        unsigned long reserved_pages, free_pages;
-        struct memblock_region *reg;
-
         arm64_swiotlb_init();
 
         max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 
 #ifndef CONFIG_SPARSEMEM_VMEMMAP
-        /* this will put all unused low memory onto the freelists */
         free_unused_memmap();
 #endif
+        /* this will put all unused low memory onto the freelists */
+        free_all_bootmem();
 
-        totalram_pages += free_all_bootmem();
-
-        reserved_pages = free_pages = 0;
-
-        for_each_memblock(memory, reg) {
-                unsigned int pfn1, pfn2;
-                struct page *page, *end;
-
-                pfn1 = __phys_to_pfn(reg->base);
-                pfn2 = pfn1 + __phys_to_pfn(reg->size);
-
-                page = pfn_to_page(pfn1);
-                end  = pfn_to_page(pfn2 - 1) + 1;
-
-                do {
-                        if (PageReserved(page))
-                                reserved_pages++;
-                        else if (!page_count(page))
-                                free_pages++;
-                        page++;
-                } while (page < end);
-        }
-
-        /*
-         * Since our memory may not be contiguous, calculate the real number
-         * of pages we have in this system.
-         */
-        pr_info("Memory:");
-        num_physpages = 0;
-        for_each_memblock(memory, reg) {
-                unsigned long pages = memblock_region_memory_end_pfn(reg) -
-                        memblock_region_memory_base_pfn(reg);
-                num_physpages += pages;
-                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-        }
-        printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-        pr_notice("Memory: %luk/%luk available, %luk reserved\n",
-                  nr_free_pages() << (PAGE_SHIFT-10),
-                  free_pages << (PAGE_SHIFT-10),
-                  reserved_pages << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
 
 #define MLK(b, t) b, t, ((t) - (b)) >> 10
 #define MLM(b, t) b, t, ((t) - (b)) >> 20
@@ -374,7 +324,7 @@ void __init mem_init(void)
         BUILD_BUG_ON(TASK_SIZE_64                       > MODULES_VADDR);
         BUG_ON(TASK_SIZE_64                             > MODULES_VADDR);
 
-        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+        if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
                 extern int sysctl_overcommit_memory;
                 /*
                  * On a machine this small we won't get anywhere without
@@ -386,7 +336,6 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        poison_init_mem(__init_begin, __init_end - __init_begin);
         free_initmem_default(0);
 }
 
@@ -396,10 +345,8 @@ static int keep_initrd;
 
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (!keep_initrd) {
-                poison_init_mem((void *)start, PAGE_ALIGN(end) - start);
-                free_reserved_area(start, end, 0, "initrd");
-        }
+        if (!keep_initrd)
+                free_reserved_area((void *)start, (void *)end, 0, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/arm64/mm/mm.h b/arch/arm64/mm/mm.h
index 916701e6d040..d519f4f50c8c 100644
--- a/arch/arm64/mm/mm.h
+++ b/arch/arm64/mm/mm.h
@@ -1,3 +1,2 @@
-extern void __flush_dcache_page(struct page *page);
 extern void __init bootmem_init(void);
 extern void __init arm64_swiotlb_init(void);
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index eeecc9c8ed68..a8d1059b91b2 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -297,6 +297,16 @@ static void __init map_mem(void)
 {
         struct memblock_region *reg;
 
+        /*
+         * Temporarily limit the memblock range. We need to do this as
+         * create_mapping requires puds, pmds and ptes to be allocated from
+         * memory addressable from the initial direct kernel mapping.
+         *
+         * The initial direct kernel mapping, located at swapper_pg_dir,
+         * gives us PGDIR_SIZE memory starting from PHYS_OFFSET (aligned).
+         */
+        memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
+
         /* map all the memory banks */
         for_each_memblock(memory, reg) {
                 phys_addr_t start = reg->base;
@@ -307,6 +317,9 @@ static void __init map_mem(void)
 
                 create_mapping(start, __phys_to_virt(start), end - start);
         }
+
+        /* Limit no longer required. */
+        memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 }
 
 /*
@@ -317,12 +330,6 @@ void __init paging_init(void)
 {
         void *zero_page;
 
-        /*
-         * Maximum PGDIR_SIZE addressable via the initial direct kernel
-         * mapping in swapper_pg_dir.
-         */
-        memblock_set_current_limit((PHYS_OFFSET & PGDIR_MASK) + PGDIR_SIZE);
-
         init_mem_pgprot();
         map_mem();
 
@@ -339,7 +346,6 @@ void __init paging_init(void)
         bootmem_init();
 
         empty_zero_page = virt_to_page(zero_page);
-        __flush_dcache_page(empty_zero_page);
 
         /*
          * TTBR0 is only used for the identity mapping at this stage. Make it
diff --git a/arch/arm64/xen/Makefile b/arch/arm64/xen/Makefile
new file mode 100644
index 000000000000..be240404ba96
--- /dev/null
+++ b/arch/arm64/xen/Makefile
@@ -0,0 +1,2 @@
+xen-arm-y       += $(addprefix ../../arm/xen/, enlighten.o grant-table.o)
+obj-y           := xen-arm.o hypercall.o
diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S
new file mode 100644
index 000000000000..2816c479cd49
--- /dev/null
+++ b/arch/arm64/xen/hypercall.S
@@ -0,0 +1,92 @@
+/******************************************************************************
+ * hypercall.S
+ *
+ * Xen hypercall wrappers
+ *
+ * Stefano Stabellini <stefano.stabellini@eu.citrix.com>, Citrix, 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+/*
+ * The Xen hypercall calling convention is very similar to the procedure
+ * call standard for the ARM 64-bit architecture: the first parameter is
+ * passed in x0, the second in x1, the third in x2, the fourth in x3 and
+ * the fifth in x4.
+ *
+ * The hypercall number is passed in x16.
+ *
+ * The return value is in x0.
+ *
+ * The hvc ISS is required to be 0xEA1, that is the Xen specific ARM
+ * hypercall tag.
+ *
+ * Parameter structs passed to hypercalls are laid out according to
+ * the ARM 64-bit EABI standard.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <xen/interface/xen.h>
+
+
+#define XEN_IMM 0xEA1
+
+#define HYPERCALL_SIMPLE(hypercall)             \
+ENTRY(HYPERVISOR_##hypercall)                   \
+        mov x16, #__HYPERVISOR_##hypercall;     \
+        hvc XEN_IMM;                            \
+        ret;                                    \
+ENDPROC(HYPERVISOR_##hypercall)
+
+#define HYPERCALL0 HYPERCALL_SIMPLE
+#define HYPERCALL1 HYPERCALL_SIMPLE
+#define HYPERCALL2 HYPERCALL_SIMPLE
+#define HYPERCALL3 HYPERCALL_SIMPLE
+#define HYPERCALL4 HYPERCALL_SIMPLE
+#define HYPERCALL5 HYPERCALL_SIMPLE
+
+                .text
+
+HYPERCALL2(xen_version);
+HYPERCALL3(console_io);
+HYPERCALL3(grant_table_op);
+HYPERCALL2(sched_op);
+HYPERCALL2(event_channel_op);
+HYPERCALL2(hvm_op);
+HYPERCALL2(memory_op);
+HYPERCALL2(physdev_op);
+HYPERCALL3(vcpu_op);
+
+ENTRY(privcmd_call)
+        mov x16, x0
+        mov x0, x1
+        mov x1, x2
+        mov x2, x3
+        mov x3, x4
+        mov x4, x5
+        hvc XEN_IMM
+        ret
+ENDPROC(privcmd_call);
diff --git a/arch/avr32/include/asm/pgtable.h b/arch/avr32/include/asm/pgtable.h
index 6fbfea61f7bb..4beff97e2033 100644
--- a/arch/avr32/include/asm/pgtable.h
+++ b/arch/avr32/include/asm/pgtable.h
@@ -362,9 +362,6 @@ typedef pte_t *pte_addr_t;
 
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /* No page table caches to initialize (?) */
 #define pgtable_cache_init()    do { } while(0)
 
diff --git a/arch/avr32/kernel/process.c b/arch/avr32/kernel/process.c
index e7b61494c312..c2731003edef 100644
--- a/arch/avr32/kernel/process.c
+++ b/arch/avr32/kernel/process.c
@@ -341,7 +341,7 @@ unsigned long get_wchan(struct task_struct *p)
                  * is actually quite ugly. It might be possible to
                  * determine the frame size automatically at build
                  * time by doing this:
-                 *   - compile sched.c
+                 *   - compile sched/core.c
                  *   - disassemble the resulting sched.o
                  *   - look for 'sub sp,??' shortly after '<schedule>:'
                  */
diff --git a/arch/avr32/kernel/setup.c b/arch/avr32/kernel/setup.c
index b4247f478065..209ae5ad3495 100644
--- a/arch/avr32/kernel/setup.c
+++ b/arch/avr32/kernel/setup.c
@@ -555,7 +555,7 @@ void __init setup_arch (char **cmdline_p)
 {
         struct clk *cpu_clk;
 
-        init_mm.start_code = (unsigned long)_text;
+        init_mm.start_code = (unsigned long)_stext;
         init_mm.end_code = (unsigned long)_etext;
         init_mm.end_data = (unsigned long)_edata;
         init_mm.brk = (unsigned long)_end;
diff --git a/arch/avr32/kernel/vmlinux.lds.S b/arch/avr32/kernel/vmlinux.lds.S
index 9cd2bd91d64a..a4589176bed5 100644
--- a/arch/avr32/kernel/vmlinux.lds.S
+++ b/arch/avr32/kernel/vmlinux.lds.S
@@ -23,7 +23,7 @@ SECTIONS
 {
         . = CONFIG_ENTRY_ADDRESS;
         .init           : AT(ADDR(.init) - LOAD_OFFSET) {
-                _stext = .;
+                _text = .;
                 __init_begin = .;
                         _sinittext = .;
                         *(.text.reset)
@@ -46,7 +46,7 @@ SECTIONS
 
         .text           : AT(ADDR(.text) - LOAD_OFFSET) {
                 _evba = .;
-                _text = .;
+                _stext = .;
                 *(.ex.text)
                 *(.irq.text)
                 KPROBES_TEXT
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 7c2f6685bf43..7f8759a8a92a 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1060,7 +1060,9 @@ struct platform_device *__init at32_add_device_usart(unsigned int id)
 
 void __init at32_setup_serial_console(unsigned int usart_id)
 {
+#ifdef CONFIG_SERIAL_ATMEL
         atmel_default_console_device = at32_usarts[usart_id];
+#endif
 }
 
 /* --------------------------------------------------------------------
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index e66e8406f992..def5391d927a 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -100,60 +100,26 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-        int nid, i;
+        pg_data_t *pgdat;
 
-        reservedpages = 0;
         high_memory = NULL;
+        for_each_online_pgdat(pgdat)
+                high_memory = max_t(void *, high_memory,
+                                    __va(pgdat_end_pfn(pgdat) << PAGE_SHIFT));
 
-        /* this will put all low memory onto the freelists */
-        for_each_online_node(nid) {
-                pg_data_t *pgdat = NODE_DATA(nid);
-                unsigned long node_pages = 0;
-                void *node_high_memory;
-
-                num_physpages += pgdat->node_present_pages;
-
-                if (pgdat->node_spanned_pages != 0)
-                        node_pages = free_all_bootmem_node(pgdat);
-
-                totalram_pages += node_pages;
-
-                for (i = 0; i < node_pages; i++)
-                        if (PageReserved(pgdat->node_mem_map + i))
-                                reservedpages++;
-
-                node_high_memory = (void *)((pgdat->node_start_pfn
-                                             + pgdat->node_spanned_pages)
-                                            << PAGE_SHIFT);
-                if (node_high_memory > high_memory)
-                        high_memory = node_high_memory;
-        }
-
-        max_mapnr = MAP_NR(high_memory);
-
-        codesize = (unsigned long)_etext - (unsigned long)_text;
-        datasize = (unsigned long)_edata - (unsigned long)_data;
-        initsize = (unsigned long)__init_end - (unsigned long)__init_begin;
-
-        printk ("Memory: %luk/%luk available (%dk kernel code, "
-                "%dk reserved, %dk data, %dk init)\n",
-                nr_free_pages() << (PAGE_SHIFT - 10),
-                totalram_pages << (PAGE_SHIFT - 10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT - 10),
-                datasize >> 10,
-                initsize >> 10);
+        set_max_mapnr(MAP_NR(high_memory));
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 }
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index a117652b5fea..08c7ac650405 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -41,6 +41,7 @@ config BLACKFIN
         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
         select HAVE_MOD_ARCH_SPECIFIC
         select MODULES_USE_ELF_RELA
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config GENERIC_CSUM
         def_bool y
@@ -253,7 +254,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
-        depends on SMP && HOTPLUG
+        depends on SMP
         default y
 
 config BF_REV_MIN
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 79594694ee90..f3337ee03621 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -2,13 +2,6 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config DEBUG_VERBOSE
         bool "Verbose fault messages"
         default y
diff --git a/arch/blackfin/include/asm/pgtable.h b/arch/blackfin/include/asm/pgtable.h
index b8663921d3c1..0b049019eba7 100644
--- a/arch/blackfin/include/asm/pgtable.h
+++ b/arch/blackfin/include/asm/pgtable.h
@@ -88,7 +88,6 @@ extern char empty_zero_page[];
  * No page table caches to initialise.
  */
 #define pgtable_cache_init()    do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
 
 /*
  * All 32bit addresses are effectively valid for vmalloc...
diff --git a/arch/blackfin/mach-bf527/boards/ad7160eval.c b/arch/blackfin/mach-bf527/boards/ad7160eval.c
index d58f50e5aa4b..1e7be62fccb6 100644
--- a/arch/blackfin/mach-bf527/boards/ad7160eval.c
+++ b/arch/blackfin/mach-bf527/boards/ad7160eval.c
@@ -283,14 +283,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
-};
-#endif
-
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -800,10 +792,6 @@ static struct platform_device *stamp_devices[] __initdata = {
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s,
 #endif
-
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
-#endif
 };
 
 static int __init ad7160eval_init(void)
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 29f16e5c37b9..d0a0c5e527cd 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -493,8 +493,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 
 static const u16 bfin_snd_pin[][7] = {
         {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
@@ -549,13 +548,6 @@ static struct platform_device bfin_i2s_pcm = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm_pcm = {
-        .name = "bfin-tdm-pcm-audio",
-        .id = -1,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97_pcm = {
         .name = "bfin-ac97-pcm-audio",
@@ -575,22 +567,10 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
-        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
-        .dev = {
-                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
-        },
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
-        "bfin-tdm.0",
+        "bfin-i2s.0",
         "spi0.4",
 };
 static struct platform_device bfin_ad1836_machine = {
@@ -1269,10 +1249,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s_pcm,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm_pcm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97_pcm,
 #endif
@@ -1281,10 +1257,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) || \
         defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
         &bfin_ad1836_machine,
diff --git a/arch/blackfin/mach-bf533/boards/ezkit.c b/arch/blackfin/mach-bf533/boards/ezkit.c
index 07811c209b9d..90fb0d14b147 100644
--- a/arch/blackfin/mach-bf533/boards/ezkit.c
+++ b/arch/blackfin/mach-bf533/boards/ezkit.c
@@ -450,14 +450,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
@@ -516,10 +508,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97,
 #endif
diff --git a/arch/blackfin/mach-bf533/boards/stamp.c b/arch/blackfin/mach-bf533/boards/stamp.c
index 6fca8698bf3b..4a8c2e3fd7e5 100644
--- a/arch/blackfin/mach-bf533/boards/stamp.c
+++ b/arch/blackfin/mach-bf533/boards/stamp.c
@@ -542,8 +542,7 @@ static struct platform_device bfin_dpmc = {
 };
 
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) \
-        || defined(CONFIG_SND_BF5XX_AC97) || \
+        defined(CONFIG_SND_BF5XX_AC97) || \
         defined(CONFIG_SND_BF5XX_AC97_MODULE)
 
 #include <asm/bfin_sport.h>
@@ -603,13 +602,6 @@ static struct platform_device bfin_i2s_pcm = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm_pcm = {
-        .name = "bfin-tdm-pcm-audio",
-        .id = -1,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97_pcm = {
         .name = "bfin-ac97-pcm-audio",
@@ -620,7 +612,7 @@ static struct platform_device bfin_ac97_pcm = {
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
-        "bfin-tdm.0",
+        "bfin-i2s.0",
         "spi0.4",
 };
 static struct platform_device bfin_ad1836_machine = {
@@ -675,20 +667,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \
-        defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        .num_resources =
-                ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
-        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
-        .dev = {
-                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
-        },
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
         defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
@@ -761,10 +739,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s_pcm,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm_pcm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97_pcm,
 #endif
@@ -792,11 +766,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_TDM) || \
-        defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AC97) || \
         defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
         &bfin_ac97,
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 6a3a14bcd3a1..44fd1d4682ac 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -2570,7 +2570,6 @@ static struct platform_device bfin_dpmc = {
 };
 
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
         defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 
 #define SPORT_REQ(x) \
@@ -2628,13 +2627,6 @@ static struct platform_device bfin_i2s_pcm = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm_pcm = {
-        .name = "bfin-tdm-pcm-audio",
-        .id = -1,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97_pcm = {
         .name = "bfin-ac97-pcm-audio",
@@ -2645,7 +2637,7 @@ static struct platform_device bfin_ac97_pcm = {
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
-        "bfin-tdm.0",
+        "bfin-i2s.0",
         "spi0.4",
 };
 static struct platform_device bfin_ad1836_machine = {
@@ -2699,18 +2691,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
-        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
-        .dev = {
-                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
-        },
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
@@ -2935,10 +2915,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s_pcm,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm_pcm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97_pcm,
 #endif
@@ -2961,10 +2937,6 @@ static struct platform_device *stamp_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
         &bfin_ac97,
 #endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index c4d07f040947..372eb54944ef 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -1393,7 +1393,6 @@ static struct platform_device bfin_dpmc = {
 };
 
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
-        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
         defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 
 #define SPORT_REQ(x) \
@@ -1461,13 +1460,6 @@ static struct platform_device bfin_i2s_pcm = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm_pcm = {
-        .name = "bfin-tdm-pcm-audio",
-        .id = -1,
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97_pcm = {
         .name = "bfin-ac97-pcm-audio",
@@ -1501,18 +1493,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
-        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
-        .dev = {
-                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
-        },
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
@@ -1646,9 +1626,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s_pcm,
 #endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm_pcm,
-#endif
+
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97_pcm,
 #endif
@@ -1661,10 +1639,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97,
 #endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 551f866172cf..92938e79b9e3 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -523,14 +523,6 @@ static struct platform_device bfin_i2s = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-static struct platform_device bfin_tdm = {
-        .name = "bfin-tdm",
-        .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
-};
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
@@ -542,7 +534,7 @@ static struct platform_device bfin_ac97 = {
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
-        "bfin-tdm.0",
+        "bfin-i2s.0",
         "spi0.4",
 };
 static struct platform_device bfin_ad1836_machine = {
@@ -611,10 +603,6 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
-        &bfin_tdm,
-#endif
-
 #if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
         &bfin_ac97,
 #endif
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index 97d701639585..bba40aed4273 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -821,7 +821,7 @@ static struct platform_device bfin_i2s = {
 #if defined(CONFIG_SND_BF5XX_SOC_AD1836) \
                 || defined(CONFIG_SND_BF5XX_SOC_AD1836_MODULE)
 static const char * const ad1836_link[] = {
-        "bfin-tdm.0",
+        "bfin-i2s.0",
         "spi0.76",
 };
 static struct platform_device bfin_ad1836_machine = {
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index 82d01a71207f..166842de3dc7 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -90,50 +90,24 @@ asmlinkage void __init init_pda(void)
 
 void __init mem_init(void)
 {
-        unsigned int codek = 0, datak = 0, initk = 0;
-        unsigned int reservedpages = 0, freepages = 0;
-        unsigned long tmp;
-        unsigned long start_mem = memory_start;
-        unsigned long end_mem = memory_end;
+        char buf[64];
 
-        end_mem &= PAGE_MASK;
-        high_memory = (void *)end_mem;
-
-        start_mem = PAGE_ALIGN(start_mem);
-        max_mapnr = num_physpages = MAP_NR(high_memory);
-        printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages);
+        high_memory = (void *)(memory_end & PAGE_MASK);
+        max_mapnr = MAP_NR(high_memory);
+        printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", max_mapnr);
 
         /* This will put all low memory onto the freelists. */
-        totalram_pages = free_all_bootmem();
-
-        reservedpages = 0;
-        for (tmp = ARCH_PFN_OFFSET; tmp < max_mapnr; tmp++)
-                if (PageReserved(pfn_to_page(tmp)))
-                        reservedpages++;
-        freepages =  max_mapnr - ARCH_PFN_OFFSET - reservedpages;
-
-        /* do not count in kernel image between _rambase and _ramstart */
-        reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
-#if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
-        reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
-#endif
-
-        codek = (_etext - _stext) >> 10;
-        initk = (__init_end - __init_begin) >> 10;
-        datak = ((_ramstart - _rambase) >> 10) - codek - initk;
+        free_all_bootmem();
 
-        printk(KERN_INFO
-             "Memory available: %luk/%luk RAM, "
-                "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
-                (unsigned long) freepages << (PAGE_SHIFT-10), (_ramend - CONFIG_PHY_RAM_BASE_ADDRESS) >> 10,
-                initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
+        snprintf(buf, sizeof(buf) - 1, "%uK DMA", DMA_UNCACHED_REGION >> 10);
+        mem_init_print_info(buf);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
 #ifndef CONFIG_MPU
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 #endif
 }
 #endif
@@ -141,7 +115,7 @@ void __init free_initrd_mem(unsigned long start, unsigned long end)
 void __init_refok free_initmem(void)
 {
 #if defined CONFIG_RAMKERNEL && !defined CONFIG_MPU
-        free_initmem_default(0);
+        free_initmem_default(-1);
         if (memory_start == (unsigned long)(&__init_end))
                 memory_start = (unsigned long)(&__init_begin);
 #endif
diff --git a/arch/c6x/include/asm/Kbuild b/arch/c6x/include/asm/Kbuild
index 4258b088aa93..e49f918531ad 100644
--- a/arch/c6x/include/asm/Kbuild
+++ b/arch/c6x/include/asm/Kbuild
@@ -55,3 +55,4 @@ generic-y += types.h
 generic-y += ucontext.h
 generic-y += user.h
 generic-y += vga.h
+generic-y += xor.h
diff --git a/arch/c6x/include/asm/pgtable.h b/arch/c6x/include/asm/pgtable.h
index 38a4312eb2cb..c0eed5b18860 100644
--- a/arch/c6x/include/asm/pgtable.h
+++ b/arch/c6x/include/asm/pgtable.h
@@ -71,7 +71,6 @@ extern unsigned long empty_zero_page;
  * No page table caches to initialise
  */
 #define pgtable_cache_init()   do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
 
 #include <asm-generic/pgtable.h>
 
diff --git a/arch/c6x/kernel/vmlinux.lds.S b/arch/c6x/kernel/vmlinux.lds.S
index 1d81c4c129ec..279d80725128 100644
--- a/arch/c6x/kernel/vmlinux.lds.S
+++ b/arch/c6x/kernel/vmlinux.lds.S
@@ -54,16 +54,15 @@ SECTIONS
         }
 
         . = ALIGN(PAGE_SIZE);
+        __init_begin = .;
         .init :
         {
-                _stext = .;
                 _sinittext = .;
                 HEAD_TEXT
                 INIT_TEXT
                 _einittext = .;
         }
 
-        __init_begin = _stext;
         INIT_DATA_SECTION(16)
 
         PERCPU_SECTION(128)
@@ -74,6 +73,7 @@ SECTIONS
         .text :
         {
                 _text = .;
+                _stext = .;
                 TEXT_TEXT
                 SCHED_TEXT
                 LOCK_TEXT
diff --git a/arch/c6x/mm/init.c b/arch/c6x/mm/init.c
index a9fcd89b251b..63f5560d6eb2 100644
--- a/arch/c6x/mm/init.c
+++ b/arch/c6x/mm/init.c
@@ -18,6 +18,7 @@
 #include <linux/initrd.h>
 
 #include <asm/sections.h>
+#include <asm/uaccess.h>
 
 /*
  * ZERO_PAGE is a special page that is used for zero-initialized
@@ -57,31 +58,22 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        int codek, datak;
-        unsigned long tmp;
-        unsigned long len = memory_end - memory_start;
-
         high_memory = (void *)(memory_end & PAGE_MASK);
 
         /* this will put all memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-        codek = (_etext - _stext) >> 10;
-        datak = (_end - _sdata) >> 10;
+        free_all_bootmem();
 
-        tmp = nr_free_pages() << PAGE_SHIFT;
-        printk(KERN_INFO "Memory: %luk/%luk RAM (%dk kernel code, %dk data)\n",
-               tmp >> 10, len >> 10, codek, datak);
+        mem_init_print_info(NULL);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
 void __init free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 8769a9045a54..3201ddb8da6a 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -134,11 +134,13 @@ config SVINTO_SIM
 
 config ETRAXFS
         bool "ETRAX-FS-V32"
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support CRIS V32.
 
 config CRIS_MACH_ARTPEC3
         bool "ARTPEC-3"
+        select CPU_FREQ_TABLE if CPU_FREQ
         help
           Support Axis ARTPEC-3.
 
@@ -637,40 +639,10 @@ endchoice
 
 endmenu
 
-source "drivers/base/Kconfig"
-
-# standard linux drivers
-source "drivers/mtd/Kconfig"
-
-source "drivers/parport/Kconfig"
-
-source "drivers/pnp/Kconfig"
-
-source "drivers/block/Kconfig"
-
-source "drivers/ide/Kconfig"
-
-source "drivers/net/Kconfig"
-
-source "drivers/i2c/Kconfig"
-
-source "drivers/rtc/Kconfig"
-
-#
-# input before char - char/joystick depends on it. As does USB.
-#
-source "drivers/input/Kconfig"
-
-source "drivers/char/Kconfig"
+source "drivers/Kconfig"
 
 source "fs/Kconfig"
 
-source "drivers/usb/Kconfig"
-
-source "drivers/uwb/Kconfig"
-
-source "drivers/staging/Kconfig"
-
 source "arch/cris/Kconfig.debug"
 
 source "security/Kconfig"
diff --git a/arch/cris/arch-v10/kernel/kgdb.c b/arch/cris/arch-v10/kernel/kgdb.c
index 37e6d2c50b76..22d846bfc570 100644
--- a/arch/cris/arch-v10/kernel/kgdb.c
+++ b/arch/cris/arch-v10/kernel/kgdb.c
@@ -230,46 +230,6 @@ struct register_image
         unsigned int    usp;   /* 0x66 User mode stack pointer */
 } registers;
 
-/************** Prototypes for local library functions ***********************/
-
-/* Copy of strcpy from libc. */
-static char *gdb_cris_strcpy (char *s1, const char *s2);
-
-/* Copy of strlen from libc. */
-static int gdb_cris_strlen (const char *s);
-
-/* Copy of memchr from libc. */
-static void *gdb_cris_memchr (const void *s, int c, int n);
-
-/* Copy of strtol from libc. Does only support base 16. */
-static int gdb_cris_strtol (const char *s, char **endptr, int base);
-
-/********************** Prototypes for local functions. **********************/
-/* Copy the content of a register image into another. The size n is
-   the size of the register image. Due to struct assignment generation of
-   memcpy in libc. */
-static void copy_registers (registers *dptr, registers *sptr, int n);
-
-/* Copy the stored registers from the stack. Put the register contents
-   of thread thread_id in the struct reg. */
-static void copy_registers_from_stack (int thread_id, registers *reg);
-
-/* Copy the registers to the stack. Put the register contents of thread
-   thread_id from struct reg to the stack. */
-static void copy_registers_to_stack (int thread_id, registers *reg);
-
-/* Write a value to a specified register regno in the register image
-   of the current thread. */
-static int write_register (int regno, char *val);
-
-/* Write a value to a specified register in the stack of a thread other
-   than the current thread. */
-static int write_stack_register(int thread_id, int regno, char *valptr);
-
-/* Read a value from a specified register in the register image. Returns the
-   status of the read operation. The register value is returned in valptr. */
-static int read_register (char regno, unsigned int *valptr);
-
 /* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
 int getDebugChar (void);
 
@@ -278,42 +238,6 @@ void putDebugChar (int val);
 
 void enableDebugIRQ (void);
 
-/* Returns the integer equivalent of a hexadecimal character. */
-static int hex (char ch);
-
-/* Convert the memory, pointed to by mem into hexadecimal representation.
-   Put the result in buf, and return a pointer to the last character
-   in buf (null). */
-static char *mem2hex (char *buf, unsigned char *mem, int count);
-
-/* Convert the array, in hexadecimal representation, pointed to by buf into
-   binary representation. Put the result in mem, and return a pointer to
-   the character after the last byte written. */
-static unsigned char *hex2mem (unsigned char *mem, char *buf, int count);
-
-/* Put the content of the array, in binary representation, pointed to by buf
-   into memory pointed to by mem, and return a pointer to
-   the character after the last byte written. */
-static unsigned char *bin2mem (unsigned char *mem, unsigned char *buf, int count);
-
-/* Await the sequence $<data>#<checksum> and store <data> in the array buffer
-   returned. */
-static void getpacket (char *buffer);
-
-/* Send $<data>#<checksum> from the <data> in the array buffer. */
-static void putpacket (char *buffer);
-
-/* Build and send a response packet in order to inform the host the
-   stub is stopped. */
-static void stub_is_stopped (int sigval);
-
-/* All expected commands are sent from remote.c. Send a response according
-   to the description in remote.c. */
-static void handle_exception (int sigval);
-
-/* Performs a complete re-start from scratch. ETRAX specific. */
-static void kill_restart (void);
-
 /******************** Prototypes for global functions. ***********************/
 
 /* The string str is prepended with the GDB printout token and sent. */
@@ -336,10 +260,6 @@ extern unsigned char executing_task;
 /* The number of characters used for a 64 bit thread identifier. */
 #define HEXCHARS_IN_THREAD_ID 16
 
-/* Avoid warning as the internal_stack is not used in the C-code. */
-#define USEDVAR(name)    { if (name) { ; } }
-#define USEDFUN(name) { void (*pf)(void) = (void *)name; USEDVAR(pf) }
-
 /********************************** Packet I/O ******************************/
 /* BUFMAX defines the maximum number of characters in
    inbound/outbound buffers */
@@ -405,7 +325,7 @@ static int register_size[] =
 
 /* Contains the register image of the executing thread in the assembler
    part of the code in order to avoid horrible addressing modes. */
-static registers reg;
+registers cris_reg;
 
 /* FIXME: Should this be used? Delete otherwise. */
 /* Contains the assumed consistency state of the register image. Uses the
@@ -413,7 +333,7 @@ static registers reg;
 static int consistency_status = SUCCESS;
 
 /********************************** Handle exceptions ************************/
-/* The variable reg contains the register image associated with the
+/* The variable cris_reg contains the register image associated with the
    current_thread_c variable. It is a complete register image created at
    entry. The reg_g contains a register image of a task where the general
    registers are taken from the stack and all special registers are taken
@@ -421,18 +341,10 @@ static int consistency_status = SUCCESS;
    in order to provide access mainly for 'g', 'G' and 'P'.
 */
 
-/* Need two task id pointers in order to handle Hct and Hgt commands. */
-static int current_thread_c = 0;
-static int current_thread_g = 0;
-
-/* Need two register images in order to handle Hct and Hgt commands. The
-   variable reg_g is in addition to reg above. */
-static registers reg_g;
-
 /********************************** Breakpoint *******************************/
 /* Use an internal stack in the breakpoint and interrupt response routines */
 #define INTERNAL_STACK_SIZE 1024
-static char internal_stack[INTERNAL_STACK_SIZE];
+char internal_stack[INTERNAL_STACK_SIZE];
 
 /* Due to the breakpoint return pointer, a state variable is needed to keep
    track of whether it is a static (compiled) or dynamic (gdb-invoked)
@@ -500,164 +412,6 @@ gdb_cris_strtol (const char *s, char **endptr, int base)
         return x;
 }
 
-/********************************* Register image ****************************/
-/* Copy the content of a register image into another. The size n is
-   the size of the register image. Due to struct assignment generation of
-   memcpy in libc. */
-static void
-copy_registers (registers *dptr, registers *sptr, int n)
-{
-        unsigned char *dreg;
-        unsigned char *sreg;
-        
-        for (dreg = (unsigned char*)dptr, sreg = (unsigned char*)sptr; n > 0; n--)
-                *dreg++ = *sreg++;
-}
-
-#ifdef PROCESS_SUPPORT
-/* Copy the stored registers from the stack. Put the register contents
-   of thread thread_id in the struct reg. */
-static void
-copy_registers_from_stack (int thread_id, registers *regptr)
-{
-        int j;
-        stack_registers *s = (stack_registers *)stack_list[thread_id];
-        unsigned int *d = (unsigned int *)regptr;
-        
-        for (j = 13; j >= 0; j--)
-                *d++ = s->r[j];
-        regptr->sp = (unsigned int)stack_list[thread_id];
-        regptr->pc = s->pc;
-        regptr->dccr = s->dccr;
-        regptr->srp = s->srp;
-}
-
-/* Copy the registers to the stack. Put the register contents of thread
-   thread_id from struct reg to the stack. */
-static void
-copy_registers_to_stack (int thread_id, registers *regptr)
-{
-        int i;
-        stack_registers *d = (stack_registers *)stack_list[thread_id];
-        unsigned int *s = (unsigned int *)regptr;
-        
-        for (i = 0; i < 14; i++) {
-                d->r[i] = *s++;
-        }
-        d->pc = regptr->pc;
-        d->dccr = regptr->dccr;
-        d->srp = regptr->srp;
-}
-#endif
-
-/* Write a value to a specified register in the register image of the current
-   thread. Returns status code SUCCESS, E02 or E05. */
-static int
-write_register (int regno, char *val)
-{
-        int status = SUCCESS;
-        registers *current_reg = &reg;
-
-        if (regno >= R0 && regno <= PC) {
-                /* 32-bit register with simple offset. */
-                hex2mem ((unsigned char *)current_reg + regno * sizeof(unsigned int),
-                         val, sizeof(unsigned int));
-        }
-        else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
-                /* Do not support read-only registers. */
-                status = E02;
-        }
-        else if (regno == CCR) {
-                /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented, 
-                   and P7 (MOF) is 32 bits in ETRAX 100LX. */
-                hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
-                         val, sizeof(unsigned short));
-        }
-        else if (regno >= MOF && regno <= USP) {
-                /* 32 bit register with complex offset.  (P8 has been taken care of.) */
-                hex2mem ((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
-                         val, sizeof(unsigned int));
-        } 
-        else {
-                /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
-                status = E05;
-        }
-        return status;
-}
-
-#ifdef PROCESS_SUPPORT
-/* Write a value to a specified register in the stack of a thread other
-   than the current thread. Returns status code SUCCESS or E07. */
-static int
-write_stack_register (int thread_id, int regno, char *valptr)
-{
-        int status = SUCCESS;
-        stack_registers *d = (stack_registers *)stack_list[thread_id];
-        unsigned int val;
-        
-        hex2mem ((unsigned char *)&val, valptr, sizeof(unsigned int));
-        if (regno >= R0 && regno < SP) {
-                d->r[regno] = val;
-        }
-        else if (regno == SP) {
-                stack_list[thread_id] = val;
-        }
-        else if (regno == PC) {
-                d->pc = val;
-        }
-        else if (regno == SRP) {
-                d->srp = val;
-        }
-        else if (regno == DCCR) {
-                d->dccr = val;
-        }
-        else {
-                /* Do not support registers in the current thread. */
-                status = E07;
-        }
-        return status;
-}
-#endif
-
-/* Read a value from a specified register in the register image. Returns the
-   value in the register or -1 for non-implemented registers.
-   Should check consistency_status after a call which may be E05 after changes
-   in the implementation. */
-static int
-read_register (char regno, unsigned int *valptr)
-{
-        registers *current_reg = &reg;
-
-        if (regno >= R0 && regno <= PC) {
-                /* 32-bit register with simple offset. */
-                *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int));
-                return SUCCESS;
-        }
-        else if (regno == P0 || regno == VR) {
-                /* 8 bit register with complex offset. */
-                *valptr = (unsigned int)(*(unsigned char *)
-                                         ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char)));
-                return SUCCESS;
-        }
-        else if (regno == P4 || regno == CCR) {
-                /* 16 bit register with complex offset. */
-                *valptr = (unsigned int)(*(unsigned short *)
-                                         ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
-                return SUCCESS;
-        }
-        else if (regno >= MOF && regno <= USP) {
-                /* 32 bit register with complex offset. */
-                *valptr = *(unsigned int *)((char *)&(current_reg->p8)
-                                            + (regno-P8) * sizeof(unsigned int));
-                return SUCCESS;
-        }
-        else {
-                /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
-                consistency_status = E05;
-                return E05;
-        }
-}
-
 /********************************** Packet I/O ******************************/
 /* Returns the integer equivalent of a hexadecimal character. */
 static int
@@ -676,8 +430,6 @@ hex (char ch)
    Put the result in buf, and return a pointer to the last character
    in buf (null). */
 
-static int do_printk = 0;
-
 static char *
 mem2hex(char *buf, unsigned char *mem, int count)
 {
@@ -761,7 +513,7 @@ getpacket (char *buffer)
                 xmitcsum = -1;
                 count = 0;
                 /* Read until a # or the end of the buffer is reached */
-                while (count < BUFMAX) {
+                while (count < BUFMAX - 1) {
                         ch = getDebugChar ();
                         if (ch == '#')
                                 break;
@@ -845,6 +597,81 @@ putDebugString (const unsigned char *str, int length)
         putpacket(remcomOutBuffer);
 }
 
+/********************************* Register image ****************************/
+/* Write a value to a specified register in the register image of the current
+   thread. Returns status code SUCCESS, E02 or E05. */
+static int
+write_register (int regno, char *val)
+{
+        int status = SUCCESS;
+        registers *current_reg = &cris_reg;
+
+        if (regno >= R0 && regno <= PC) {
+                /* 32-bit register with simple offset. */
+                hex2mem ((unsigned char *)current_reg + regno * sizeof(unsigned int),
+                         val, sizeof(unsigned int));
+        }
+        else if (regno == P0 || regno == VR || regno == P4 || regno == P8) {
+                /* Do not support read-only registers. */
+                status = E02;
+        }
+        else if (regno == CCR) {
+                /* 16 bit register with complex offset. (P4 is read-only, P6 is not implemented, 
+                   and P7 (MOF) is 32 bits in ETRAX 100LX. */
+                hex2mem ((unsigned char *)&(current_reg->ccr) + (regno-CCR) * sizeof(unsigned short),
+                         val, sizeof(unsigned short));
+        }
+        else if (regno >= MOF && regno <= USP) {
+                /* 32 bit register with complex offset.  (P8 has been taken care of.) */
+                hex2mem ((unsigned char *)&(current_reg->ibr) + (regno-IBR) * sizeof(unsigned int),
+                         val, sizeof(unsigned int));
+        } 
+        else {
+                /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
+                status = E05;
+        }
+        return status;
+}
+
+/* Read a value from a specified register in the register image. Returns the
+   value in the register or -1 for non-implemented registers.
+   Should check consistency_status after a call which may be E05 after changes
+   in the implementation. */
+static int
+read_register (char regno, unsigned int *valptr)
+{
+        registers *current_reg = &cris_reg;
+
+        if (regno >= R0 && regno <= PC) {
+                /* 32-bit register with simple offset. */
+                *valptr = *(unsigned int *)((char *)current_reg + regno * sizeof(unsigned int));
+                return SUCCESS;
+        }
+        else if (regno == P0 || regno == VR) {
+                /* 8 bit register with complex offset. */
+                *valptr = (unsigned int)(*(unsigned char *)
+                                         ((char *)&(current_reg->p0) + (regno-P0) * sizeof(char)));
+                return SUCCESS;
+        }
+        else if (regno == P4 || regno == CCR) {
+                /* 16 bit register with complex offset. */
+                *valptr = (unsigned int)(*(unsigned short *)
+                                         ((char *)&(current_reg->p4) + (regno-P4) * sizeof(unsigned short)));
+                return SUCCESS;
+        }
+        else if (regno >= MOF && regno <= USP) {
+                /* 32 bit register with complex offset. */
+                *valptr = *(unsigned int *)((char *)&(current_reg->p8)
+                                            + (regno-P8) * sizeof(unsigned int));
+                return SUCCESS;
+        }
+        else {
+                /* Do not support nonexisting or unimplemented registers (P2, P3, and P6). */
+                consistency_status = E05;
+                return E05;
+        }
+}
+
 /********************************** Handle exceptions ************************/
 /* Build and send a response packet in order to inform the host the
    stub is stopped. TAAn...:r...;n...:r...;n...:r...;
@@ -891,26 +718,6 @@ stub_is_stopped(int sigval)
                 
         }
 
-#ifdef PROCESS_SUPPORT
-        /* Store the registers of the executing thread. Assume that both step,
-           continue, and register content requests are with respect to this
-           thread. The executing task is from the operating system scheduler. */
-
-        current_thread_c = executing_task;
-        current_thread_g = executing_task;
-
-        /* A struct assignment translates into a libc memcpy call. Avoid
-           all libc functions in order to prevent recursive break points. */
-        copy_registers (&reg_g, &reg, sizeof(registers));
-
-        /* Store thread:r...; with the executing task TID. */
-        gdb_cris_strcpy (&remcomOutBuffer[pos], "thread:");
-        pos += gdb_cris_strlen ("thread:");
-        remcomOutBuffer[pos++] = hex_asc_hi(executing_task);
-        remcomOutBuffer[pos++] = hex_asc_lo(executing_task);
-        gdb_cris_strcpy (&remcomOutBuffer[pos], ";");
-#endif
-
         /* null-terminate and send it off */
 
         *ptr = 0;
@@ -918,16 +725,18 @@ stub_is_stopped(int sigval)
         putpacket (remcomOutBuffer);
 }
 
+/* Performs a complete re-start from scratch. */
+static void
+kill_restart (void)
+{
+        machine_restart("");
+}
+
 /* All expected commands are sent from remote.c. Send a response according
    to the description in remote.c. */
-static void
+void
 handle_exception (int sigval)
 {
-        /* Avoid warning of not used. */
-
-        USEDFUN(handle_exception);
-        USEDVAR(internal_stack[0]);
-
         /* Send response. */
 
         stub_is_stopped (sigval);
@@ -943,19 +752,7 @@ handle_exception (int sigval)
                                    in a register  are in the same order the machine uses.
                                    Failure: void. */
                                 
-                                {
-#ifdef PROCESS_SUPPORT
-                                        /* Use the special register content in the executing thread. */
-                                        copy_registers (&reg_g, &reg, sizeof(registers));
-                                        /* Replace the content available on the stack. */
-                                        if (current_thread_g != executing_task) {
-                                                copy_registers_from_stack (current_thread_g, &reg_g);
-                                        }
-                                        mem2hex ((unsigned char *)remcomOutBuffer, (unsigned char *)&reg_g, sizeof(registers));
-#else
-                                        mem2hex(remcomOutBuffer, (char *)&reg, sizeof(registers));
-#endif
-                                }
+                                mem2hex(remcomOutBuffer, (char *)&cris_reg, sizeof(registers));
                                 break;
                                 
                         case 'G':
@@ -963,17 +760,7 @@ handle_exception (int sigval)
                                    Each byte of register data  is described by two hex digits.
                                    Success: OK
                                    Failure: void. */
-#ifdef PROCESS_SUPPORT
-                                hex2mem ((unsigned char *)&reg_g, &remcomInBuffer[1], sizeof(registers));
-                                if (current_thread_g == executing_task) {
-                                        copy_registers (&reg, &reg_g, sizeof(registers));
-                                }
-                                else {
-                                        copy_registers_to_stack(current_thread_g, &reg_g);
-                                }
-#else
-                                hex2mem((char *)&reg, &remcomInBuffer[1], sizeof(registers));
-#endif
+                                hex2mem((char *)&cris_reg, &remcomInBuffer[1], sizeof(registers));
                                 gdb_cris_strcpy (remcomOutBuffer, "OK");
                                 break;
                                 
@@ -989,12 +776,7 @@ handle_exception (int sigval)
                                         char *suffix;
                                         int regno = gdb_cris_strtol (&remcomInBuffer[1], &suffix, 16);
                                         int status;
-#ifdef PROCESS_SUPPORT
-                                        if (current_thread_g != executing_task)
-                                                status = write_stack_register (current_thread_g, regno, suffix+1);
-                                        else
-#endif
-                                                status = write_register (regno, suffix+1);
+                                        status = write_register (regno, suffix+1);
 
                                         switch (status) {
                                                 case E02:
@@ -1073,7 +855,7 @@ handle_exception (int sigval)
                                    Success: return to the executing thread.
                                    Failure: will never know. */
                                 if (remcomInBuffer[1] != '\0') {
-                                        reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16);
+                                        cris_reg.pc = gdb_cris_strtol (&remcomInBuffer[1], 0, 16);
                                 }
                                 enableDebugIRQ();
                                 return;
@@ -1129,119 +911,6 @@ handle_exception (int sigval)
                                    Not supported: E04 */
                                 gdb_cris_strcpy (remcomOutBuffer, error_message[E04]);
                                 break;
-#ifdef PROCESS_SUPPORT
-
-                        case 'T':
-                                /* Thread alive. TXX
-                                   Is thread XX alive?
-                                   Success: OK, thread XX is alive.
-                                   Failure: E03, thread XX is dead. */
-                                {
-                                        int thread_id = (int)gdb_cris_strtol (&remcomInBuffer[1], 0, 16);
-                                        /* Cannot tell whether it is alive or not. */
-                                        if (thread_id >= 0 && thread_id < number_of_tasks)
-                                                gdb_cris_strcpy (remcomOutBuffer, "OK");
-                                }
-                                break;
-                                                                
-                        case 'H':
-                                /* Set thread for subsequent operations: Hct
-                                   c = 'c' for thread used in step and continue;
-                                   t can be -1 for all threads.
-                                   c = 'g' for thread used in other  operations.
-                                   t = 0 means pick any thread.
-                                   Success: OK
-                                   Failure: E01 */
-                                {
-                                        int thread_id = gdb_cris_strtol (&remcomInBuffer[2], 0, 16);
-                                        if (remcomInBuffer[1] == 'c') {
-                                                /* c = 'c' for thread used in step and continue */
-                                                /* Do not change current_thread_c here. It would create a mess in
-                                                   the scheduler. */
-                                                gdb_cris_strcpy (remcomOutBuffer, "OK");
-                                        }
-                                        else if (remcomInBuffer[1] == 'g') {
-                                                /* c = 'g' for thread used in other  operations.
-                                                   t = 0 means pick any thread. Impossible since the scheduler does
-                                                   not allow that. */
-                                                if (thread_id >= 0 && thread_id < number_of_tasks) {
-                                                        current_thread_g = thread_id;
-                                                        gdb_cris_strcpy (remcomOutBuffer, "OK");
-                                                }
-                                                else {
-                                                        /* Not expected - send an error message. */
-                                                        gdb_cris_strcpy (remcomOutBuffer, error_message[E01]);
-                                                }
-                                        }
-                                        else {
-                                                /* Not expected - send an error message. */
-                                                gdb_cris_strcpy (remcomOutBuffer, error_message[E01]);
-                                        }
-                                }
-                                break;
-                                
-                        case 'q':
-                        case 'Q':
-                                /* Query of general interest. qXXXX
-                                   Set general value XXXX. QXXXX=yyyy */
-                                {
-                                        int pos;
-                                        int nextpos;
-                                        int thread_id;
-                                        
-                                        switch (remcomInBuffer[1]) {
-                                                case 'C':
-                                                        /* Identify the remote current thread. */
-                                                        gdb_cris_strcpy (&remcomOutBuffer[0], "QC");
-                                                        remcomOutBuffer[2] = hex_asc_hi(current_thread_c);
-                                                        remcomOutBuffer[3] = hex_asc_lo(current_thread_c);
-                                                        remcomOutBuffer[4] = '\0';
-                                                        break;
-                                                case 'L':
-                                                        gdb_cris_strcpy (&remcomOutBuffer[0], "QM");
-                                                        /* Reply with number of threads. */
-                                                        if (os_is_started()) {
-                                                                remcomOutBuffer[2] = hex_asc_hi(number_of_tasks);
-                                                                remcomOutBuffer[3] = hex_asc_lo(number_of_tasks);
-                                                        }
-                                                        else {
-                                                                remcomOutBuffer[2] = hex_asc_hi(0);
-                                                                remcomOutBuffer[3] = hex_asc_lo(1);
-                                                        }
-                                                        /* Done with the reply. */
-                                                        remcomOutBuffer[4] = hex_asc_lo(1);
-                                                        pos = 5;
-                                                        /* Expects the argument thread id. */
-                                                        for (; pos < (5 + HEXCHARS_IN_THREAD_ID); pos++)
-                                                                remcomOutBuffer[pos] = remcomInBuffer[pos];
-                                                        /* Reply with the thread identifiers. */
-                                                        if (os_is_started()) {
-                                                                /* Store the thread identifiers of all tasks. */
-                                                                for (thread_id = 0; thread_id < number_of_tasks; thread_id++) {
-                                                                        nextpos = pos + HEXCHARS_IN_THREAD_ID - 1;
-                                                                        for (; pos < nextpos; pos ++)
-                                                                                remcomOutBuffer[pos] = hex_asc_lo(0);
-                                                                        remcomOutBuffer[pos++] = hex_asc_lo(thread_id);
-                                                                }
-                                                        }
-                                                        else {
-                                                                /* Store the thread identifier of the boot task. */
-                                                                nextpos = pos + HEXCHARS_IN_THREAD_ID - 1;
-                                                                for (; pos < nextpos; pos ++)
-                                                                        remcomOutBuffer[pos] = hex_asc_lo(0);
-                                                                remcomOutBuffer[pos++] = hex_asc_lo(current_thread_c);
-                                                        }
-                                                        remcomOutBuffer[pos] = '\0';
-                                                        break;
-                                                default:
-                                                        /* Not supported: "" */
-                                                        /* Request information about section offsets: qOffsets. */
-                                                        remcomOutBuffer[0] = 0;
-                                                        break;
-                                        }
-                                }
-                                break;
-#endif /* PROCESS_SUPPORT */
                                 
                         default:
                                 /* The stub should ignore other request and send an empty
@@ -1254,13 +923,6 @@ handle_exception (int sigval)
         }
 }
 
-/* Performs a complete re-start from scratch. */
-static void
-kill_restart ()
-{
-        machine_restart("");
-}
-
 /********************************** Breakpoint *******************************/
 /* The hook for both a static (compiled) and a dynamic breakpoint set by GDB.
    An internal stack is used by the stub. The register image of the caller is
@@ -1270,93 +932,93 @@ kill_restart ()
 
 void kgdb_handle_breakpoint(void);
 
-asm ("
-  .global kgdb_handle_breakpoint
-kgdb_handle_breakpoint:
-;;
-;; Response to the break-instruction
-;;
-;; Create a register image of the caller
-;;
-  move     $dccr,[reg+0x5E] ; Save the flags in DCCR before disable interrupts
-  di                        ; Disable interrupts
-  move.d   $r0,[reg]        ; Save R0
-  move.d   $r1,[reg+0x04]   ; Save R1
-  move.d   $r2,[reg+0x08]   ; Save R2
-  move.d   $r3,[reg+0x0C]   ; Save R3
-  move.d   $r4,[reg+0x10]   ; Save R4
-  move.d   $r5,[reg+0x14]   ; Save R5
-  move.d   $r6,[reg+0x18]   ; Save R6
-  move.d   $r7,[reg+0x1C]   ; Save R7
-  move.d   $r8,[reg+0x20]   ; Save R8
-  move.d   $r9,[reg+0x24]   ; Save R9
-  move.d   $r10,[reg+0x28]  ; Save R10
-  move.d   $r11,[reg+0x2C]  ; Save R11
-  move.d   $r12,[reg+0x30]  ; Save R12
-  move.d   $r13,[reg+0x34]  ; Save R13
-  move.d   $sp,[reg+0x38]   ; Save SP (R14)
-;; Due to the old assembler-versions BRP might not be recognized
-  .word 0xE670              ; move brp,$r0
-  subq     2,$r0             ; Set to address of previous instruction.
-  move.d   $r0,[reg+0x3c]   ; Save the address in PC (R15)
-  clear.b  [reg+0x40]      ; Clear P0
-  move     $vr,[reg+0x41]   ; Save special register P1
-  clear.w  [reg+0x42]      ; Clear P4
-  move     $ccr,[reg+0x44]  ; Save special register CCR
-  move     $mof,[reg+0x46]  ; P7
-  clear.d  [reg+0x4A]      ; Clear P8
-  move     $ibr,[reg+0x4E]  ; P9,
-  move     $irp,[reg+0x52]  ; P10,
-  move     $srp,[reg+0x56]  ; P11,
-  move     $dtp0,[reg+0x5A] ; P12, register BAR, assembler might not know BAR
-                            ; P13, register DCCR already saved
-;; Due to the old assembler-versions BRP might not be recognized
-  .word 0xE670              ; move brp,r0
-;; Static (compiled) breakpoints must return to the next instruction in order
-;; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction
-;; in order to execute it when execution is continued.
-  test.b   [is_dyn_brkp]    ; Is this a dynamic breakpoint?
-  beq      is_static         ; No, a static breakpoint
-  nop
-  subq     2,$r0              ; rerun the instruction the break replaced
-is_static:
-  moveq    1,$r1
-  move.b   $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint
-  move.d   $r0,[reg+0x62]    ; Save the return address in BRP
-  move     $usp,[reg+0x66]   ; USP
-;;
-;; Handle the communication
-;;
-  move.d   internal_stack+1020,$sp ; Use the internal stack which grows upward
-  moveq    5,$r10                   ; SIGTRAP
-  jsr      handle_exception       ; Interactive routine
-;;
-;; Return to the caller
-;;
-   move.d  [reg],$r0         ; Restore R0
-   move.d  [reg+0x04],$r1    ; Restore R1
-   move.d  [reg+0x08],$r2    ; Restore R2
-   move.d  [reg+0x0C],$r3    ; Restore R3
-   move.d  [reg+0x10],$r4    ; Restore R4
-   move.d  [reg+0x14],$r5    ; Restore R5
-   move.d  [reg+0x18],$r6    ; Restore R6
-   move.d  [reg+0x1C],$r7    ; Restore R7
-   move.d  [reg+0x20],$r8    ; Restore R8
-   move.d  [reg+0x24],$r9    ; Restore R9
-   move.d  [reg+0x28],$r10   ; Restore R10
-   move.d  [reg+0x2C],$r11   ; Restore R11
-   move.d  [reg+0x30],$r12   ; Restore R12
-   move.d  [reg+0x34],$r13   ; Restore R13
-;;
-;; FIXME: Which registers should be restored?
-;;
-   move.d  [reg+0x38],$sp    ; Restore SP (R14)
-   move    [reg+0x56],$srp   ; Restore the subroutine return pointer.
-   move    [reg+0x5E],$dccr  ; Restore DCCR
-   move    [reg+0x66],$usp   ; Restore USP
-   jump    [reg+0x62]       ; A jump to the content in register BRP works.
-   nop                       ;
-");
+asm ("\n"
+"  .global kgdb_handle_breakpoint\n"
+"kgdb_handle_breakpoint:\n"
+";;\n"
+";; Response to the break-instruction\n"
+";;\n"
+";; Create a register image of the caller\n"
+";;\n"
+"  move     $dccr,[cris_reg+0x5E] ; Save the flags in DCCR before disable interrupts\n"
+"  di                        ; Disable interrupts\n"
+"  move.d   $r0,[cris_reg]        ; Save R0\n"
+"  move.d   $r1,[cris_reg+0x04]   ; Save R1\n"
+"  move.d   $r2,[cris_reg+0x08]   ; Save R2\n"
+"  move.d   $r3,[cris_reg+0x0C]   ; Save R3\n"
+"  move.d   $r4,[cris_reg+0x10]   ; Save R4\n"
+"  move.d   $r5,[cris_reg+0x14]   ; Save R5\n"
+"  move.d   $r6,[cris_reg+0x18]   ; Save R6\n"
+"  move.d   $r7,[cris_reg+0x1C]   ; Save R7\n"
+"  move.d   $r8,[cris_reg+0x20]   ; Save R8\n"
+"  move.d   $r9,[cris_reg+0x24]   ; Save R9\n"
+"  move.d   $r10,[cris_reg+0x28]  ; Save R10\n"
+"  move.d   $r11,[cris_reg+0x2C]  ; Save R11\n"
+"  move.d   $r12,[cris_reg+0x30]  ; Save R12\n"
+"  move.d   $r13,[cris_reg+0x34]  ; Save R13\n"
+"  move.d   $sp,[cris_reg+0x38]   ; Save SP (R14)\n"
+";; Due to the old assembler-versions BRP might not be recognized\n"
+"  .word 0xE670              ; move brp,$r0\n"
+"  subq     2,$r0             ; Set to address of previous instruction.\n"
+"  move.d   $r0,[cris_reg+0x3c]   ; Save the address in PC (R15)\n"
+"  clear.b  [cris_reg+0x40]      ; Clear P0\n"
+"  move     $vr,[cris_reg+0x41]   ; Save special register P1\n"
+"  clear.w  [cris_reg+0x42]      ; Clear P4\n"
+"  move     $ccr,[cris_reg+0x44]  ; Save special register CCR\n"
+"  move     $mof,[cris_reg+0x46]  ; P7\n"
+"  clear.d  [cris_reg+0x4A]      ; Clear P8\n"
+"  move     $ibr,[cris_reg+0x4E]  ; P9,\n"
+"  move     $irp,[cris_reg+0x52]  ; P10,\n"
+"  move     $srp,[cris_reg+0x56]  ; P11,\n"
+"  move     $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
+"                            ; P13, register DCCR already saved\n"
+";; Due to the old assembler-versions BRP might not be recognized\n"
+"  .word 0xE670              ; move brp,r0\n"
+";; Static (compiled) breakpoints must return to the next instruction in order\n"
+";; to avoid infinite loops. Dynamic (gdb-invoked) must restore the instruction\n"
+";; in order to execute it when execution is continued.\n"
+"  test.b   [is_dyn_brkp]    ; Is this a dynamic breakpoint?\n"
+"  beq      is_static         ; No, a static breakpoint\n"
+"  nop\n"
+"  subq     2,$r0              ; rerun the instruction the break replaced\n"
+"is_static:\n"
+"  moveq    1,$r1\n"
+"  move.b   $r1,[is_dyn_brkp] ; Set the state variable to dynamic breakpoint\n"
+"  move.d   $r0,[cris_reg+0x62]    ; Save the return address in BRP\n"
+"  move     $usp,[cris_reg+0x66]   ; USP\n"
+";;\n"
+";; Handle the communication\n"
+";;\n"
+"  move.d   internal_stack+1020,$sp ; Use the internal stack which grows upward\n"
+"  moveq    5,$r10                   ; SIGTRAP\n"
+"  jsr      handle_exception       ; Interactive routine\n"
+";;\n"
+";; Return to the caller\n"
+";;\n"
+"   move.d  [cris_reg],$r0         ; Restore R0\n"
+"   move.d  [cris_reg+0x04],$r1    ; Restore R1\n"
+"   move.d  [cris_reg+0x08],$r2    ; Restore R2\n"
+"   move.d  [cris_reg+0x0C],$r3    ; Restore R3\n"
+"   move.d  [cris_reg+0x10],$r4    ; Restore R4\n"
+"   move.d  [cris_reg+0x14],$r5    ; Restore R5\n"
+"   move.d  [cris_reg+0x18],$r6    ; Restore R6\n"
+"   move.d  [cris_reg+0x1C],$r7    ; Restore R7\n"
+"   move.d  [cris_reg+0x20],$r8    ; Restore R8\n"
+"   move.d  [cris_reg+0x24],$r9    ; Restore R9\n"
+"   move.d  [cris_reg+0x28],$r10   ; Restore R10\n"
+"   move.d  [cris_reg+0x2C],$r11   ; Restore R11\n"
+"   move.d  [cris_reg+0x30],$r12   ; Restore R12\n"
+"   move.d  [cris_reg+0x34],$r13   ; Restore R13\n"
+";;\n"
+";; FIXME: Which registers should be restored?\n"
+";;\n"
+"   move.d  [cris_reg+0x38],$sp    ; Restore SP (R14)\n"
+"   move    [cris_reg+0x56],$srp   ; Restore the subroutine return pointer.\n"
+"   move    [cris_reg+0x5E],$dccr  ; Restore DCCR\n"
+"   move    [cris_reg+0x66],$usp   ; Restore USP\n"
+"   jump    [cris_reg+0x62]       ; A jump to the content in register BRP works.\n"
+"   nop                       ;\n"
+"\n");
 
 /* The hook for an interrupt generated by GDB. An internal stack is used
    by the stub. The register image of the caller is stored in the structure
@@ -1367,94 +1029,94 @@ is_static:
 
 void kgdb_handle_serial(void);
 
-asm ("
-  .global kgdb_handle_serial
-kgdb_handle_serial:
-;;
-;; Response to a serial interrupt
-;;
-
-  move     $dccr,[reg+0x5E] ; Save the flags in DCCR
-  di                        ; Disable interrupts
-  move.d   $r0,[reg]        ; Save R0
-  move.d   $r1,[reg+0x04]   ; Save R1
-  move.d   $r2,[reg+0x08]   ; Save R2
-  move.d   $r3,[reg+0x0C]   ; Save R3
-  move.d   $r4,[reg+0x10]   ; Save R4
-  move.d   $r5,[reg+0x14]   ; Save R5
-  move.d   $r6,[reg+0x18]   ; Save R6
-  move.d   $r7,[reg+0x1C]   ; Save R7
-  move.d   $r8,[reg+0x20]   ; Save R8
-  move.d   $r9,[reg+0x24]   ; Save R9
-  move.d   $r10,[reg+0x28]  ; Save R10
-  move.d   $r11,[reg+0x2C]  ; Save R11
-  move.d   $r12,[reg+0x30]  ; Save R12
-  move.d   $r13,[reg+0x34]  ; Save R13
-  move.d   $sp,[reg+0x38]   ; Save SP (R14)
-  move     $irp,[reg+0x3c]  ; Save the address in PC (R15)
-  clear.b  [reg+0x40]      ; Clear P0
-  move     $vr,[reg+0x41]   ; Save special register P1,
-  clear.w  [reg+0x42]      ; Clear P4
-  move     $ccr,[reg+0x44]  ; Save special register CCR
-  move     $mof,[reg+0x46]  ; P7
-  clear.d  [reg+0x4A]      ; Clear P8
-  move     $ibr,[reg+0x4E]  ; P9,
-  move     $irp,[reg+0x52]  ; P10,
-  move     $srp,[reg+0x56]  ; P11,
-  move     $dtp0,[reg+0x5A] ; P12, register BAR, assembler might not know BAR
-                            ; P13, register DCCR already saved
-;; Due to the old assembler-versions BRP might not be recognized
-  .word 0xE670              ; move brp,r0
-  move.d   $r0,[reg+0x62]   ; Save the return address in BRP
-  move     $usp,[reg+0x66]  ; USP
-
-;; get the serial character (from debugport.c) and check if it is a ctrl-c
-
-  jsr getDebugChar
-  cmp.b 3, $r10
-  bne goback
-  nop
-
-  move.d  [reg+0x5E], $r10              ; Get DCCR
-  btstq    8, $r10                      ; Test the U-flag.
-  bmi      goback
-  nop
-
-;;
-;; Handle the communication
-;;
-  move.d   internal_stack+1020,$sp ; Use the internal stack
-  moveq    2,$r10                   ; SIGINT
-  jsr      handle_exception       ; Interactive routine
-
-goback:
-;;
-;; Return to the caller
-;;
-   move.d  [reg],$r0         ; Restore R0
-   move.d  [reg+0x04],$r1    ; Restore R1
-   move.d  [reg+0x08],$r2    ; Restore R2
-   move.d  [reg+0x0C],$r3    ; Restore R3
-   move.d  [reg+0x10],$r4    ; Restore R4
-   move.d  [reg+0x14],$r5    ; Restore R5
-   move.d  [reg+0x18],$r6    ; Restore R6
-   move.d  [reg+0x1C],$r7    ; Restore R7
-   move.d  [reg+0x20],$r8    ; Restore R8
-   move.d  [reg+0x24],$r9    ; Restore R9
-   move.d  [reg+0x28],$r10   ; Restore R10
-   move.d  [reg+0x2C],$r11   ; Restore R11
-   move.d  [reg+0x30],$r12   ; Restore R12
-   move.d  [reg+0x34],$r13   ; Restore R13
-;;
-;; FIXME: Which registers should be restored?
-;;
-   move.d  [reg+0x38],$sp    ; Restore SP (R14)
-   move    [reg+0x56],$srp   ; Restore the subroutine return pointer.
-   move    [reg+0x5E],$dccr  ; Restore DCCR
-   move    [reg+0x66],$usp   ; Restore USP
-   reti                      ; Return from the interrupt routine
-   nop
-");
+asm ("\n"
+"  .global kgdb_handle_serial\n"
+"kgdb_handle_serial:\n"
+";;\n"
+";; Response to a serial interrupt\n"
+";;\n"
+"\n"
+"  move     $dccr,[cris_reg+0x5E] ; Save the flags in DCCR\n"
+"  di                        ; Disable interrupts\n"
+"  move.d   $r0,[cris_reg]        ; Save R0\n"
+"  move.d   $r1,[cris_reg+0x04]   ; Save R1\n"
+"  move.d   $r2,[cris_reg+0x08]   ; Save R2\n"
+"  move.d   $r3,[cris_reg+0x0C]   ; Save R3\n"
+"  move.d   $r4,[cris_reg+0x10]   ; Save R4\n"
+"  move.d   $r5,[cris_reg+0x14]   ; Save R5\n"
+"  move.d   $r6,[cris_reg+0x18]   ; Save R6\n"
+"  move.d   $r7,[cris_reg+0x1C]   ; Save R7\n"
+"  move.d   $r8,[cris_reg+0x20]   ; Save R8\n"
+"  move.d   $r9,[cris_reg+0x24]   ; Save R9\n"
+"  move.d   $r10,[cris_reg+0x28]  ; Save R10\n"
+"  move.d   $r11,[cris_reg+0x2C]  ; Save R11\n"
+"  move.d   $r12,[cris_reg+0x30]  ; Save R12\n"
+"  move.d   $r13,[cris_reg+0x34]  ; Save R13\n"
+"  move.d   $sp,[cris_reg+0x38]   ; Save SP (R14)\n"
+"  move     $irp,[cris_reg+0x3c]  ; Save the address in PC (R15)\n"
+"  clear.b  [cris_reg+0x40]      ; Clear P0\n"
+"  move     $vr,[cris_reg+0x41]   ; Save special register P1,\n"
+"  clear.w  [cris_reg+0x42]      ; Clear P4\n"
+"  move     $ccr,[cris_reg+0x44]  ; Save special register CCR\n"
+"  move     $mof,[cris_reg+0x46]  ; P7\n"
+"  clear.d  [cris_reg+0x4A]      ; Clear P8\n"
+"  move     $ibr,[cris_reg+0x4E]  ; P9,\n"
+"  move     $irp,[cris_reg+0x52]  ; P10,\n"
+"  move     $srp,[cris_reg+0x56]  ; P11,\n"
+"  move     $dtp0,[cris_reg+0x5A] ; P12, register BAR, assembler might not know BAR\n"
+"                            ; P13, register DCCR already saved\n"
+";; Due to the old assembler-versions BRP might not be recognized\n"
+"  .word 0xE670              ; move brp,r0\n"
+"  move.d   $r0,[cris_reg+0x62]   ; Save the return address in BRP\n"
+"  move     $usp,[cris_reg+0x66]  ; USP\n"
+"\n"
+";; get the serial character (from debugport.c) and check if it is a ctrl-c\n"
+"\n"
+"  jsr getDebugChar\n"
+"  cmp.b 3, $r10\n"
+"  bne goback\n"
+"  nop\n"
+"\n"
+"  move.d  [cris_reg+0x5E], $r10                ; Get DCCR\n"
+"  btstq           8, $r10                      ; Test the U-flag.\n"
+"  bmi     goback\n"
+"  nop\n"
+"\n"
+";;\n"
+";; Handle the communication\n"
+";;\n"
+"  move.d   internal_stack+1020,$sp ; Use the internal stack\n"
+"  moveq    2,$r10                   ; SIGINT\n"
+"  jsr      handle_exception       ; Interactive routine\n"
+"\n"
+"goback:\n"
+";;\n"
+";; Return to the caller\n"
+";;\n"
+"   move.d  [cris_reg],$r0         ; Restore R0\n"
+"   move.d  [cris_reg+0x04],$r1    ; Restore R1\n"
+"   move.d  [cris_reg+0x08],$r2    ; Restore R2\n"
+"   move.d  [cris_reg+0x0C],$r3    ; Restore R3\n"
+"   move.d  [cris_reg+0x10],$r4    ; Restore R4\n"
+"   move.d  [cris_reg+0x14],$r5    ; Restore R5\n"
+"   move.d  [cris_reg+0x18],$r6    ; Restore R6\n"
+"   move.d  [cris_reg+0x1C],$r7    ; Restore R7\n"
+"   move.d  [cris_reg+0x20],$r8    ; Restore R8\n"
+"   move.d  [cris_reg+0x24],$r9    ; Restore R9\n"
+"   move.d  [cris_reg+0x28],$r10   ; Restore R10\n"
+"   move.d  [cris_reg+0x2C],$r11   ; Restore R11\n"
+"   move.d  [cris_reg+0x30],$r12   ; Restore R12\n"
+"   move.d  [cris_reg+0x34],$r13   ; Restore R13\n"
+";;\n"
+";; FIXME: Which registers should be restored?\n"
+";;\n"
+"   move.d  [cris_reg+0x38],$sp    ; Restore SP (R14)\n"
+"   move    [cris_reg+0x56],$srp   ; Restore the subroutine return pointer.\n"
+"   move    [cris_reg+0x5E],$dccr  ; Restore DCCR\n"
+"   move    [cris_reg+0x66],$usp   ; Restore USP\n"
+"   reti                      ; Return from the interrupt routine\n"
+"   nop\n"
+"\n");
 
 /* Use this static breakpoint in the start-up only. */
 
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index c55971a40c34..acff3df8c43f 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -617,7 +617,6 @@ config ETRAX_PV_CHANGEABLE_BITS
 config ETRAX_CARDBUS
         bool "Cardbus support"
         depends on ETRAX_ARCH_V32
-        select HOTPLUG
         help
          Enabled the ETRAX Cardbus driver.
 
@@ -641,8 +640,6 @@ config ETRAX_STREAMCOPROC
           This option enables a driver for the stream co-processor
           for cryptographic operations.
 
-source drivers/mmc/Kconfig
-
 config ETRAX_MMC_IOP
         tristate "MMC/SD host driver using IO-processor"
         depends on ETRAX_ARCH_V32 && MMC
@@ -834,9 +831,4 @@ config ETRAX_SPI_MMC_WP_GPIO_PIN
           The pin to use for the SD/MMC write-protect signal for a memory
           card.  If defined as " " (space), the card is considered writable.
 
-# Avoid choices causing non-working configs by conditionalizing the inclusion.
-if ETRAX_SPI_MMC
-source drivers/spi/Kconfig
-endif
-
 endif
diff --git a/arch/cris/include/arch-v10/arch/bitops.h b/arch/cris/include/arch-v10/arch/bitops.h
index be85f6de25d3..03d9cfd92c8a 100644
--- a/arch/cris/include/arch-v10/arch/bitops.h
+++ b/arch/cris/include/arch-v10/arch/bitops.h
@@ -17,7 +17,7 @@ static inline unsigned long cris_swapnwbrlz(unsigned long w)
            in another register:
            !  __asm__ ("swapnwbr %2\n\tlz %2,%0"
            !          : "=r,r" (res), "=r,X" (dummy) : "1,0" (w));
-           confuses gcc (sched.c, gcc from cris-dist-1.14).  */
+           confuses gcc (core.c, gcc from cris-dist-1.14).  */
 
         unsigned long res;
         __asm__ ("swapnwbr %0 \n\t"
diff --git a/arch/cris/include/asm/Kbuild b/arch/cris/include/asm/Kbuild
index f1e79edc9dd2..c8325455520e 100644
--- a/arch/cris/include/asm/Kbuild
+++ b/arch/cris/include/asm/Kbuild
@@ -5,5 +5,9 @@ header-y += arch-v32/
 
 generic-y += clkdev.h
 generic-y += exec.h
+generic-y += kvm_para.h
+generic-y += linkage.h
 generic-y += module.h
 generic-y += trace_clock.h
+generic-y += vga.h
+generic-y += xor.h
diff --git a/arch/cris/include/asm/io.h b/arch/cris/include/asm/io.h
index ac12ae2b9286..5d3047e5563b 100644
--- a/arch/cris/include/asm/io.h
+++ b/arch/cris/include/asm/io.h
@@ -167,6 +167,9 @@ static inline void outsl(unsigned int port, const void *addr,
                 cris_iops->write_io(port, (void *)addr, 4, count);
 }
 
+#define inb_p(port)             inb(port)
+#define outb_p(val, port)       outb((val), (port))
+
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  * access
diff --git a/arch/cris/include/asm/linkage.h b/arch/cris/include/asm/linkage.h
deleted file mode 100644
index 291c2d01c44f..000000000000
--- a/arch/cris/include/asm/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
diff --git a/arch/cris/include/asm/page.h b/arch/cris/include/asm/page.h
index be45ee366be9..dfc53f9b88ec 100644
--- a/arch/cris/include/asm/page.h
+++ b/arch/cris/include/asm/page.h
@@ -51,7 +51,6 @@ typedef struct page *pgtable_t;
  */ 
 
 #define virt_to_page(kaddr)    (mem_map + (((unsigned long)(kaddr) - PAGE_OFFSET) >> PAGE_SHIFT))
-#define VALID_PAGE(page)       (((page) - mem_map) < max_mapnr)
 #define virt_addr_valid(kaddr)  pfn_valid((unsigned)(kaddr) >> PAGE_SHIFT)
 
 /* convert a page (based on mem_map and forward) to a physical address
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
index 7df430138355..8b8c86793225 100644
--- a/arch/cris/include/asm/pgtable.h
+++ b/arch/cris/include/asm/pgtable.h
@@ -258,9 +258,6 @@ static inline pgd_t * pgd_offset(const struct mm_struct *mm, unsigned long addre
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %p(%08lx).\n", __FILE__, __LINE__, &(e), pgd_val(e))
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
 
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
index 9ac80946dada..c81af5bd9167 100644
--- a/arch/cris/mm/init.c
+++ b/arch/cris/mm/init.c
@@ -19,9 +19,6 @@ unsigned long empty_zero_page;
 void __init
 mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-        unsigned long tmp;
-
         BUG_ON(!mem_map);
 
         /* max/min_low_pfn was set by setup.c
@@ -29,35 +26,9 @@ mem_init(void)
          *
          * high_memory was also set in setup.c
          */
-
-        max_mapnr = num_physpages = max_low_pfn - min_low_pfn;
- 
-        /* this will put all memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-        reservedpages = 0;
-        for (tmp = 0; tmp < max_mapnr; tmp++) {
-                /*
-                 * Only count reserved RAM pages
-                 */
-                if (PageReserved(mem_map + tmp))
-                        reservedpages++;
-        }
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_stext;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-        
-        printk(KERN_INFO
-               "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, "
-               "%dk init)\n" ,
-               nr_free_pages() << (PAGE_SHIFT-10),
-               max_mapnr << (PAGE_SHIFT-10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10
-               );
+        max_mapnr = max_low_pfn - min_low_pfn;
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 }
 
 /* free the pages occupied by initialization code */
@@ -65,5 +36,5 @@ mem_init(void)
 void 
 free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index 2ce731f9aa4d..4b6628ea381e 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -14,6 +14,7 @@ config FRV
         select ARCH_WANT_IPC_PARSE_VERSION
         select OLD_SIGSUSPEND3
         select OLD_SIGACTION
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config ZONE_DMA
         bool
diff --git a/arch/frv/Kconfig.debug b/arch/frv/Kconfig.debug
index 211f01bc4caa..98c99a3ed2be 100644
--- a/arch/frv/Kconfig.debug
+++ b/arch/frv/Kconfig.debug
@@ -2,10 +2,6 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-
 config GDBSTUB
         bool "Remote GDB kernel debugging"
         depends on DEBUG_KERNEL
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
index 6bc241e4b4f8..eb0110acd19b 100644
--- a/arch/frv/include/asm/pgtable.h
+++ b/arch/frv/include/asm/pgtable.h
@@ -488,9 +488,6 @@ static inline int pte_file(pte_t pte)
 #define PageSkip(page)          (0)
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
diff --git a/arch/frv/include/asm/uaccess.h b/arch/frv/include/asm/uaccess.h
index 0b67ec5b4414..3ac9a59d65d4 100644
--- a/arch/frv/include/asm/uaccess.h
+++ b/arch/frv/include/asm/uaccess.h
@@ -280,14 +280,14 @@ extern long __memcpy_user(void *dst, const void *src, unsigned long count);
 static inline unsigned long __must_check
 __copy_to_user(void __user *to, const void *from, unsigned long n)
 {
-       might_sleep();
+       might_fault();
        return __copy_to_user_inatomic(to, from, n);
 }
 
 static inline unsigned long
 __copy_from_user(void *to, const void __user *from, unsigned long n)
 {
-       might_sleep();
+       might_fault();
        return __copy_from_user_inatomic(to, from, n);
 }
 
diff --git a/arch/frv/kernel/head.S b/arch/frv/kernel/head.S
index e9a8cc63ac94..a7d0bea9c036 100644
--- a/arch/frv/kernel/head.S
+++ b/arch/frv/kernel/head.S
@@ -479,11 +479,6 @@ __head_mmu_enabled:
 
         LEDS            0x000c
 
-        # initialise the processor and the peripherals
-        #call           SYMBOL_NAME(processor_init)
-        #call           SYMBOL_NAME(unit_init)
-        #LEDS           0x0aff
-
         sethi.p         #0xe5e5,gr3
         setlo           #0xe5e5,gr3
         or.p            gr3,gr0,gr4
diff --git a/arch/frv/kernel/pm.c b/arch/frv/kernel/pm.c
index 0b579927439d..ac767d94a880 100644
--- a/arch/frv/kernel/pm.c
+++ b/arch/frv/kernel/pm.c
@@ -150,7 +150,7 @@ static int user_atoi(char __user *ubuf, size_t len)
 /*
  * Send us to sleep.
  */
-static int sysctl_pm_do_suspend(ctl_table *ctl, int write,
+static int sysctl_pm_do_suspend(struct ctl_table *ctl, int write,
                                 void __user *buffer, size_t *lenp, loff_t *fpos)
 {
         int mode;
@@ -197,7 +197,7 @@ static int try_set_cmode(int new_cmode)
 }
 
 
-static int cmode_procctl(ctl_table *ctl, int write,
+static int cmode_procctl(struct ctl_table *ctl, int write,
                          void __user *buffer, size_t *lenp, loff_t *fpos)
 {
         int new_cmode;
@@ -269,7 +269,7 @@ static int try_set_cm(int new_cm)
         return 0;
 }
 
-static int p0_procctl(ctl_table *ctl, int write,
+static int p0_procctl(struct ctl_table *ctl, int write,
                       void __user *buffer, size_t *lenp, loff_t *fpos)
 {
         int new_p0;
@@ -282,7 +282,7 @@ static int p0_procctl(ctl_table *ctl, int write,
         return try_set_p0(new_p0)?:*lenp;
 }
 
-static int cm_procctl(ctl_table *ctl, int write,
+static int cm_procctl(struct ctl_table *ctl, int write,
                       void __user *buffer, size_t *lenp, loff_t *fpos)
 {
         int new_cm;
diff --git a/arch/frv/kernel/setup.c b/arch/frv/kernel/setup.c
index a5136474c6fd..ae3a6706419b 100644
--- a/arch/frv/kernel/setup.c
+++ b/arch/frv/kernel/setup.c
@@ -735,7 +735,7 @@ static void __init parse_cmdline_early(char *cmdline)
                 /* "mem=XXX[kKmM]" sets SDRAM size to <mem>, overriding the value we worked
                  * out from the SDRAM controller mask register
                  */
-                if (!memcmp(cmdline, "mem=", 4)) {
+                if (!strncmp(cmdline, "mem=", 4)) {
                         unsigned long long mem_size;
 
                         mem_size = memparse(cmdline + 4, &cmdline);
@@ -876,6 +876,7 @@ late_initcall(setup_arch_serial);
 static void __init setup_linux_memory(void)
 {
         unsigned long bootmap_size, low_top_pfn, kstart, kend, high_mem;
+        unsigned long physpages;
 
         kstart  = (unsigned long) &__kernel_image_start - PAGE_OFFSET;
         kend    = (unsigned long) &__kernel_image_end - PAGE_OFFSET;
@@ -893,19 +894,19 @@ static void __init setup_linux_memory(void)
                                          );
 
         /* pass the memory that the kernel can immediately use over to the bootmem allocator */
-        max_mapnr = num_physpages = (memory_end - memory_start) >> PAGE_SHIFT;
+        max_mapnr = physpages = (memory_end - memory_start) >> PAGE_SHIFT;
         low_top_pfn = (KERNEL_LOWMEM_END - KERNEL_LOWMEM_START) >> PAGE_SHIFT;
         high_mem = 0;
 
-        if (num_physpages > low_top_pfn) {
+        if (physpages > low_top_pfn) {
 #ifdef CONFIG_HIGHMEM
-                high_mem = num_physpages - low_top_pfn;
+                high_mem = physpages - low_top_pfn;
 #else
-                max_mapnr = num_physpages = low_top_pfn;
+                max_mapnr = physpages = low_top_pfn;
 #endif
         }
         else {
-                low_top_pfn = num_physpages;
+                low_top_pfn = physpages;
         }
 
         min_low_pfn = memory_start >> PAGE_SHIFT;
@@ -979,7 +980,7 @@ static void __init setup_uclinux_memory(void)
         free_bootmem(memory_start, memory_end - memory_start);
 
         high_memory = (void *) (memory_end & PAGE_MASK);
-        max_mapnr = num_physpages = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
+        max_mapnr = ((unsigned long) high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
 
         min_low_pfn = memory_start >> PAGE_SHIFT;
         max_low_pfn = memory_end >> PAGE_SHIFT;
diff --git a/arch/frv/kernel/sysctl.c b/arch/frv/kernel/sysctl.c
index 6c155d69da29..f4dfae2c75ad 100644
--- a/arch/frv/kernel/sysctl.c
+++ b/arch/frv/kernel/sysctl.c
@@ -46,7 +46,7 @@ static void frv_change_dcache_mode(unsigned long newmode)
 /*
  * handle requests to dynamically switch the write caching mode delivered by /proc
  */
-static int procctl_frv_cachemode(ctl_table *table, int write,
+static int procctl_frv_cachemode(struct ctl_table *table, int write,
                                  void __user *buffer, size_t *lenp,
                                  loff_t *ppos)
 {
@@ -121,7 +121,7 @@ static int procctl_frv_cachemode(ctl_table *table, int write,
  * permit the mm_struct the nominated process is using have its MMU context ID pinned
  */
 #ifdef CONFIG_MMU
-static int procctl_frv_pin_cxnr(ctl_table *table, int write,
+static int procctl_frv_pin_cxnr(struct ctl_table *table, int write,
                                 void __user *buffer, size_t *lenp,
                                 loff_t *ppos)
 {
diff --git a/arch/frv/kernel/traps.c b/arch/frv/kernel/traps.c
index 4bff48c19d29..a6d105d61b26 100644
--- a/arch/frv/kernel/traps.c
+++ b/arch/frv/kernel/traps.c
@@ -523,7 +523,7 @@ void die_if_kernel(const char *str, ...)
                 return;
 
         va_start(va, str);
-        vsprintf(buffer, str, va);
+        vsnprintf(buffer, sizeof(buffer), str, va);
         va_end(va);
 
         console_verbose();
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index dee354fa6b64..88a159743528 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -78,7 +78,7 @@ void __init paging_init(void)
         memset((void *) empty_zero_page, 0, PAGE_SIZE);
 
 #ifdef CONFIG_HIGHMEM
-        if (num_physpages - num_mappedpages) {
+        if (get_num_physpages() - num_mappedpages) {
                 pgd_t *pge;
                 pud_t *pue;
                 pmd_t *pme;
@@ -96,7 +96,7 @@ void __init paging_init(void)
          */
         zones_size[ZONE_NORMAL]  = max_low_pfn - min_low_pfn;
 #ifdef CONFIG_HIGHMEM
-        zones_size[ZONE_HIGHMEM] = num_physpages - num_mappedpages;
+        zones_size[ZONE_HIGHMEM] = get_num_physpages() - num_mappedpages;
 #endif
 
         free_area_init(zones_size);
@@ -114,45 +114,24 @@ void __init paging_init(void)
  */
 void __init mem_init(void)
 {
-        unsigned long npages = (memory_end - memory_start) >> PAGE_SHIFT;
-        unsigned long tmp;
-#ifdef CONFIG_MMU
-        unsigned long loop, pfn;
-        int datapages = 0;
-#endif
-        int codek = 0, datak = 0;
+        unsigned long code_size = _etext - _stext;
 
         /* this will put all low memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-#ifdef CONFIG_MMU
-        for (loop = 0 ; loop < npages ; loop++)
-                if (PageReserved(&mem_map[loop]))
-                        datapages++;
-
-#ifdef CONFIG_HIGHMEM
-        for (pfn = num_physpages - 1; pfn >= num_mappedpages; pfn--)
-                free_highmem_page(&mem_map[pfn]);
-#endif
-
-        codek = ((unsigned long) &_etext - (unsigned long) &_stext) >> 10;
-        datak = datapages << (PAGE_SHIFT - 10);
-
-#else
-        codek = (_etext - _stext) >> 10;
-        datak = 0; //(__bss_stop - _sdata) >> 10;
+        free_all_bootmem();
+#if defined(CONFIG_MMU) && defined(CONFIG_HIGHMEM)
+        {
+                unsigned long pfn;
+
+                for (pfn = get_num_physpages() - 1;
+                     pfn >= num_mappedpages; pfn--)
+                        free_highmem_page(&mem_map[pfn]);
+        }
 #endif
 
-        tmp = nr_free_pages() << PAGE_SHIFT;
-        printk("Memory available: %luKiB/%luKiB RAM, %luKiB/%luKiB ROM (%dKiB kernel code, %dKiB data)\n",
-               tmp >> 10,
-               npages << (PAGE_SHIFT - 10),
-               (rom_length > 0) ? ((rom_length >> 10) - codek) : 0,
-               rom_length >> 10,
-               codek,
-               datak
-               );
-
+        mem_init_print_info(NULL);
+        if (rom_length > 0 && rom_length >= code_size)
+                printk("Memory available:  %luKiB/%luKiB ROM\n",
+                        (rom_length - code_size) >> 10, rom_length >> 10);
 } /* end mem_init() */
 
 /*****************************************************************************/
@@ -162,7 +141,7 @@ void __init mem_init(void)
 void free_initmem(void)
 {
 #if defined(CONFIG_RAMKERNEL) && !defined(CONFIG_PROTECT_KERNEL)
-        free_initmem_default(0);
+        free_initmem_default(-1);
 #endif
 } /* end free_initmem() */
 
@@ -173,6 +152,6 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 } /* end free_initrd_mem() */
 #endif
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 303e4f9a79d1..3d6759ee382f 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -94,126 +94,10 @@ endmenu
 
 source "net/Kconfig"
 
-source "drivers/base/Kconfig"
-
-source "drivers/mtd/Kconfig"
-
-source "drivers/block/Kconfig"
-
-source "drivers/ide/Kconfig"
+source "drivers/Kconfig"
 
 source "arch/h8300/Kconfig.ide"
 
-source "drivers/net/Kconfig"
-
-#
-# input - input/joystick depends on it. As does USB.
-#
-source "drivers/input/Kconfig"
-
-menu "Character devices"
-
-config VT
-        bool "Virtual terminal"
-        ---help---
-          If you say Y here, you will get support for terminal devices with
-          display and keyboard devices. These are called "virtual" because you
-          can run several virtual terminals (also called virtual consoles) on
-          one physical terminal. This is rather useful, for example one
-          virtual terminal can collect system messages and warnings, another
-          one can be used for a text-mode user session, and a third could run
-          an X session, all in parallel. Switching between virtual terminals
-          is done with certain key combinations, usually Alt-<function key>.
-
-          The setterm command ("man setterm") can be used to change the
-          properties (such as colors or beeping) of a virtual terminal. The
-          man page console_codes(4) ("man console_codes") contains the special
-          character sequences that can be used to change those properties
-          directly. The fonts used on virtual terminals can be changed with
-          the setfont ("man setfont") command and the key bindings are defined
-          with the loadkeys ("man loadkeys") command.
-
-          You need at least one virtual terminal device in order to make use
-          of your keyboard and monitor. Therefore, only people configuring an
-          embedded system would want to say N here in order to save some
-          memory; the only way to log into such a system is then via a serial
-          or network connection.
-
-          If unsure, say Y, or else you won't be able to do much with your new
-          shiny Linux system :-)
-
-config VT_CONSOLE
-        bool "Support for console on virtual terminal"
-        depends on VT
-        ---help---
-          The system console is the device which receives all kernel messages
-          and warnings and which allows logins in single user mode. If you
-          answer Y here, a virtual terminal (the device used to interact with
-          a physical terminal) can be used as system console. This is the most
-          common mode of operations, so you should say Y here unless you want
-          the kernel messages be output only to a serial port (in which case
-          you should say Y to "Console on serial port", below).
-
-          If you do say Y here, by default the currently visible virtual
-          terminal (/dev/tty0) will be used as system console. You can change
-          that with a kernel command line option such as "console=tty3" which
-          would use the third virtual terminal as system console. (Try "man
-          bootparam" or see the documentation of your boot loader (lilo or
-          loadlin) about how to pass options to the kernel at boot time.)
-
-          If unsure, say Y.
-
-config HW_CONSOLE
-        bool
-        depends on VT
-        default y
-
-comment "Unix98 PTY support"
-
-config UNIX98_PTYS
-        bool "Unix98 PTY support"
-        ---help---
-          A pseudo terminal (PTY) is a software device consisting of two
-          halves: a master and a slave. The slave device behaves identical to
-          a physical terminal; the master device is used by a process to
-          read data from and write data to the slave, thereby emulating a
-          terminal. Typical programs for the master side are telnet servers
-          and xterms.
-
-          Linux has traditionally used the BSD-like names /dev/ptyxx for
-          masters and /dev/ttyxx for slaves of pseudo terminals. This scheme
-          has a number of problems. The GNU C library glibc 2.1 and later,
-          however, supports the Unix98 naming standard: in order to acquire a
-          pseudo terminal, a process opens /dev/ptmx; the number of the pseudo
-          terminal is then made available to the process and the pseudo
-          terminal slave can be accessed as /dev/pts/<number>. What was
-          traditionally /dev/ttyp2 will then be /dev/pts/2, for example.
-
-          The entries in /dev/pts/ are created on the fly by a virtual
-          file system; therefore, if you say Y here you should say Y to
-          "/dev/pts file system for Unix98 PTYs" as well.
-
-          If you want to say Y here, you need to have the C library glibc 2.1
-          or later (equal to libc-6.1, check with "ls -l /lib/libc.so.*").
-          Read the instructions in <file:Documentation/Changes> pertaining to
-          pseudo terminals. It's safe to say N.
-
-source "drivers/char/pcmcia/Kconfig"
-
-source "drivers/tty/serial/Kconfig"
-
-source "drivers/i2c/Kconfig"
-
-source "drivers/hwmon/Kconfig"
-
-source "drivers/usb/Kconfig"
-
-source "drivers/uwb/Kconfig"
-
-endmenu
-
-source "drivers/staging/Kconfig"
-
 source "fs/Kconfig"
 
 source "arch/h8300/Kconfig.debug"
diff --git a/arch/h8300/Kconfig.cpu b/arch/h8300/Kconfig.cpu
index 321f3922728b..cdee771460ed 100644
--- a/arch/h8300/Kconfig.cpu
+++ b/arch/h8300/Kconfig.cpu
@@ -64,6 +64,7 @@ choice
 
 config H83002
         bool "H8/3001,3002,3003"
+        depends on BROKEN
         select CPU_H8300H
 
 config H83007
@@ -72,6 +73,7 @@ config H83007
 
 config H83048
         bool "H8/3044,3045,3046,3047,3048,3052"
+        depends on BROKEN
         select CPU_H8300H
 
 config H83068
@@ -155,10 +157,12 @@ config H8300_TIMER16_CH
 config H8300_ITU_CH
         int "ITU channel"
         depends on H8300_ITU
+        range 0 4
 
 config H8300_TPU_CH
         int "TPU channel"
         depends on H8300_TPU
+        range 0 4
 
 source "kernel/Kconfig.preempt"
 
diff --git a/arch/h8300/boot/compressed/Makefile b/arch/h8300/boot/compressed/Makefile
index 6745cb1ffb4f..a6c98fe3bbc3 100644
--- a/arch/h8300/boot/compressed/Makefile
+++ b/arch/h8300/boot/compressed/Makefile
@@ -16,7 +16,7 @@ OBJECTS = $(obj)/head.o $(obj)/misc.o
 #
 CONFIG_MEMORY_START     ?= 0x00400000
 CONFIG_BOOT_LINK_OFFSET ?= 0x00140000
-IMAGE_OFFSET := $(shell printf "0x%08x" $$[$(CONFIG_MEMORY_START)+$(CONFIG_BOOT_LINK_OFFSET)])
+IMAGE_OFFSET := $(shell printf "0x%08x" $$(($(CONFIG_MEMORY_START)+$(CONFIG_BOOT_LINK_OFFSET))))
 
 LDFLAGS_vmlinux := -Ttext $(IMAGE_OFFSET) -estartup $(obj)/vmlinux.lds
 
diff --git a/arch/h8300/boot/compressed/misc.c b/arch/h8300/boot/compressed/misc.c
index 51ab6cbd030f..4a1e3dd43948 100644
--- a/arch/h8300/boot/compressed/misc.c
+++ b/arch/h8300/boot/compressed/misc.c
@@ -79,7 +79,6 @@ static void error(char *m);
 
 int puts(const char *);
 
-extern int _text;               /* Defined in vmlinux.lds.S */
 extern int _end;
 static unsigned long free_mem_ptr;
 static unsigned long free_mem_end_ptr;
diff --git a/arch/h8300/include/asm/Kbuild b/arch/h8300/include/asm/Kbuild
index 995eb47e01bb..8ada3cf0c98d 100644
--- a/arch/h8300/include/asm/Kbuild
+++ b/arch/h8300/include/asm/Kbuild
@@ -1,6 +1,8 @@
 
 generic-y += clkdev.h
 generic-y += exec.h
+generic-y += linkage.h
 generic-y += mmu.h
 generic-y += module.h
 generic-y += trace_clock.h
+generic-y += xor.h
diff --git a/arch/h8300/include/asm/barrier.h b/arch/h8300/include/asm/barrier.h
index c7283c343c55..9e0aa9fc195d 100644
--- a/arch/h8300/include/asm/barrier.h
+++ b/arch/h8300/include/asm/barrier.h
@@ -12,6 +12,8 @@
 #define wmb()  asm volatile (""   : : :"memory")
 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 
+#define read_barrier_depends()  do { } while (0)
+
 #ifdef CONFIG_SMP
 #define smp_mb()        mb()
 #define smp_rmb()       rmb()
diff --git a/arch/h8300/include/asm/linkage.h b/arch/h8300/include/asm/linkage.h
deleted file mode 100644
index 1d81604fb0ad..000000000000
--- a/arch/h8300/include/asm/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_LINKAGE_H
-#define _H8300_LINKAGE_H
-
-#undef SYMBOL_NAME_LABEL
-#define SYMBOL_NAME_LABEL(_name_) _##_name_##:
-#endif
diff --git a/arch/h8300/include/asm/pgtable.h b/arch/h8300/include/asm/pgtable.h
index 62ef17676b40..7ca20f894dd7 100644
--- a/arch/h8300/include/asm/pgtable.h
+++ b/arch/h8300/include/asm/pgtable.h
@@ -52,9 +52,6 @@ extern int is_in_rom(unsigned long);
  */
 #define pgtable_cache_init()   do { } while (0)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
diff --git a/arch/h8300/include/asm/tlb.h b/arch/h8300/include/asm/tlb.h
index 3dea80ad9e6f..7f0743051ad5 100644
--- a/arch/h8300/include/asm/tlb.h
+++ b/arch/h8300/include/asm/tlb.h
@@ -1,16 +1,3 @@
-/* 
-  include/asm-h8300/tlb.h 
-*/
-
-#ifndef __H8300_TLB_H__
-#define __H8300_TLB_H__
-
-#define tlb_flush(tlb)  do { } while(0)
-
-/* 
-  include/asm-h8300/tlb.h 
-*/
-
 #ifndef __H8300_TLB_H__
 #define __H8300_TLB_H__
 
@@ -19,5 +6,3 @@
 #include <asm-generic/tlb.h>
 
 #endif
-
-#endif
diff --git a/arch/h8300/kernel/entry.S b/arch/h8300/kernel/entry.S
index 617a6878787f..94bd30f11df6 100644
--- a/arch/h8300/kernel/entry.S
+++ b/arch/h8300/kernel/entry.S
@@ -87,13 +87,13 @@ INTERRUPTS = 128
         bne     5f
 
         /* user mode */
-        mov.l   sp,@SYMBOL_NAME(sw_usp)
+        mov.l   sp,@_sw_usp
         mov.l   @sp,er0                         /* restore saved er0 */
         orc     #0x10,ccr                       /* switch kernel stack */
-        mov.l   @SYMBOL_NAME(sw_ksp),sp
+        mov.l   @_sw_ksp,sp
         sub.l   #(LRET-LORIG),sp                /* allocate LORIG - LRET */
         SAVEREGS
-        mov.l   @SYMBOL_NAME(sw_usp),er0
+        mov.l   @_sw_usp,er0
         mov.l   @(USERRET:16,er0),er1           /* copy the RET addr */
         mov.l   er1,@(LRET-LER3:16,sp)
         SAVEEXR
@@ -128,7 +128,7 @@ INTERRUPTS = 128
         bne     7f
 
         orc     #0x80,ccr
-        mov.l   @SYMBOL_NAME(sw_usp),er0
+        mov.l   @_sw_usp,er0
         mov.l   @(LER0-LER1:16,sp),er1          /* restore ER0 */
         mov.l   er1,@er0
         RESTOREEXR
@@ -141,7 +141,7 @@ INTERRUPTS = 128
 
         mov.l   @sp+,er1
         add.l   #(LRET-LER1),sp                 /* remove LORIG - LRET */
-        mov.l   sp,@SYMBOL_NAME(sw_ksp)
+        mov.l   sp,@_sw_ksp
         andc    #0xef,ccr                       /* switch to user mode */
         mov.l   er0,sp
         bra     8f
@@ -155,20 +155,20 @@ INTERRUPTS = 128
         rte
         .endm
 
-.globl SYMBOL_NAME(system_call)
-.globl SYMBOL_NAME(ret_from_exception)
-.globl SYMBOL_NAME(ret_from_fork)
-.globl SYMBOL_NAME(ret_from_kernel_thread)
-.globl SYMBOL_NAME(ret_from_interrupt)
-.globl SYMBOL_NAME(interrupt_redirect_table)
-.globl SYMBOL_NAME(sw_ksp),SYMBOL_NAME(sw_usp)
-.globl SYMBOL_NAME(resume)
-.globl SYMBOL_NAME(interrupt_entry)
-.globl SYMBOL_NAME(trace_break)
+.globl _system_call
+.globl _ret_from_exception
+.globl _ret_from_fork
+.globl _ret_from_kernel_thread
+.globl _ret_from_interrupt
+.globl _interrupt_redirect_table
+.globl _sw_ksp,_sw_usp
+.globl _resume
+.globl _interrupt_entry
+.globl _trace_break
 
 #if defined(CONFIG_ROMKERNEL)
         .section .int_redirect,"ax"
-SYMBOL_NAME_LABEL(interrupt_redirect_table)
+_interrupt_redirect_table:
 #if defined(CONFIG_CPU_H8300H)
         .rept   7
         .long   0
@@ -178,54 +178,54 @@ SYMBOL_NAME_LABEL(interrupt_redirect_table)
         .rept   5
         .long   0
         .endr
-        jmp     @SYMBOL_NAME(trace_break)
+        jmp     @_trace_break
         .long   0
 #endif
 
-        jsr     @SYMBOL_NAME(interrupt_entry)   /* NMI */
-        jmp     @SYMBOL_NAME(system_call)       /* TRAPA #0 (System call) */
+        jsr     @_interrupt_entry               /* NMI */
+        jmp     @_system_call                   /* TRAPA #0 (System call) */
         .long   0
         .long   0
-        jmp     @SYMBOL_NAME(trace_break)       /* TRAPA #3 (breakpoint) */
+        jmp     @_trace_break                   /* TRAPA #3 (breakpoint) */
         .rept   INTERRUPTS-12
-        jsr     @SYMBOL_NAME(interrupt_entry)
+        jsr     @_interrupt_entry
         .endr
 #endif
 #if defined(CONFIG_RAMKERNEL)
-.globl SYMBOL_NAME(interrupt_redirect_table)
+.globl _interrupt_redirect_table
         .section .bss
-SYMBOL_NAME_LABEL(interrupt_redirect_table)
+_interrupt_redirect_table:
         .space  4
 #endif
 
         .section .text
         .align  2
-SYMBOL_NAME_LABEL(interrupt_entry)
+_interrupt_entry:
         SAVE_ALL
         mov.l   sp,er0
         add.l   #LVEC,er0
         btst    #4,r1l
         bne     1f
         /* user LVEC */
-        mov.l   @SYMBOL_NAME(sw_usp),er0
+        mov.l   @_sw_usp,er0
         adds    #4,er0
 1:
         mov.l   @er0,er0                        /* LVEC address */
 #if defined(CONFIG_ROMKERNEL)
-        sub.l   #SYMBOL_NAME(interrupt_redirect_table),er0
+        sub.l   #_interrupt_redirect_table,er0
 #endif
 #if defined(CONFIG_RAMKERNEL)
-        mov.l   @SYMBOL_NAME(interrupt_redirect_table),er1
+        mov.l   @_interrupt_redirect_table,er1
         sub.l   er1,er0
 #endif
         SHLR2   er0
         dec.l   #1,er0
         mov.l   sp,er1
         subs    #4,er1                          /* adjust ret_pc */
-        jsr     @SYMBOL_NAME(do_IRQ)
-        jmp     @SYMBOL_NAME(ret_from_interrupt)
+        jsr     @_do_IRQ
+        jmp     @_ret_from_interrupt
 
-SYMBOL_NAME_LABEL(system_call)
+_system_call:
         subs    #4,sp                           /* dummy LVEC */
         SAVE_ALL
         andc    #0x7f,ccr
@@ -233,21 +233,21 @@ SYMBOL_NAME_LABEL(system_call)
 
         /* save top of frame */
         mov.l   sp,er0
-        jsr     @SYMBOL_NAME(set_esp0)
+        jsr     @_set_esp0
         mov.l   sp,er2
         and.w   #0xe000,r2
         mov.b   @((TI_FLAGS+3-(TIF_SYSCALL_TRACE >> 3)):16,er2),r2l
         btst    #(TIF_SYSCALL_TRACE & 7),r2l
         beq     1f
-        jsr     @SYMBOL_NAME(do_syscall_trace)
+        jsr     @_do_syscall_trace
 1:
         cmp.l   #NR_syscalls,er4
         bcc     badsys
         SHLL2   er4
-        mov.l   #SYMBOL_NAME(sys_call_table),er0
+        mov.l   #_sys_call_table,er0
         add.l   er4,er0
         mov.l   @er0,er4
-        beq     SYMBOL_NAME(ret_from_exception):16
+        beq     _ret_from_exception:16
         mov.l   @(LER1:16,sp),er0
         mov.l   @(LER2:16,sp),er1
         mov.l   @(LER3:16,sp),er2
@@ -258,10 +258,10 @@ SYMBOL_NAME_LABEL(system_call)
         mov.b   @((TI_FLAGS+3-(TIF_SYSCALL_TRACE >> 3)):16,er2),r2l
         btst    #(TIF_SYSCALL_TRACE & 7),r2l
         beq     2f
-        jsr     @SYMBOL_NAME(do_syscall_trace)
+        jsr     @_do_syscall_trace
 2:
 #if defined(CONFIG_SYSCALL_PRINT)
-        jsr     @SYMBOL_NAME(syscall_print)
+        jsr     @_syscall_print
 #endif
         orc     #0x80,ccr
         bra     resume_userspace
@@ -275,11 +275,11 @@ badsys:
 #define resume_kernel restore_all
 #endif
 
-SYMBOL_NAME_LABEL(ret_from_exception)
+_ret_from_exception:
 #if defined(CONFIG_PREEMPT)
         orc     #0x80,ccr
 #endif
-SYMBOL_NAME_LABEL(ret_from_interrupt)
+_ret_from_interrupt:
         mov.b   @(LCCR+1:16,sp),r0l
         btst    #4,r0l
         bne     resume_kernel:8         /* return from kernel */
@@ -296,12 +296,12 @@ work_pending:
         /* work notifysig */
         mov.l   sp,er0
         subs    #4,er0                  /* er0: pt_regs */
-        jsr     @SYMBOL_NAME(do_notify_resume)
+        jsr     @_do_notify_resume
         bra     restore_all:8
 work_resched:
         mov.l   sp,er0
-        jsr     @SYMBOL_NAME(set_esp0)
-        jsr     @SYMBOL_NAME(schedule)
+        jsr     @_set_esp0
+        jsr     @_schedule
         bra     resume_userspace:8
 restore_all:
         RESTORE_ALL                     /* Does RTE */
@@ -320,26 +320,26 @@ need_resched:
         mov.l   er0,@(TI_PRE_COUNT:16,er4)
         andc    #0x7f,ccr
         mov.l   sp,er0
-        jsr     @SYMBOL_NAME(set_esp0)
-        jsr     @SYMBOL_NAME(schedule)
+        jsr     @_set_esp0
+        jsr     @_schedule
         orc     #0x80,ccr
         bra     need_resched:8
 #endif
 
-SYMBOL_NAME_LABEL(ret_from_fork)
+_ret_from_fork:
         mov.l   er2,er0
-        jsr     @SYMBOL_NAME(schedule_tail)
-        jmp     @SYMBOL_NAME(ret_from_exception)
+        jsr     @_schedule_tail
+        jmp     @_ret_from_exception
 
-SYMBOL_NAME_LABEL(ret_from_kernel_thread)
+_ret_from_kernel_thread:
         mov.l   er2,er0
-        jsr     @SYMBOL_NAME(schedule_tail)
+        jsr     @_schedule_tail
         mov.l   @(LER4:16,sp),er0
         mov.l   @(LER5:16,sp),er1
         jsr     @er1
-        jmp     @SYMBOL_NAME(ret_from_exception)
+        jmp     @_ret_from_exception
 
-SYMBOL_NAME_LABEL(resume)
+_resume:
         /*
          * Beware - when entering resume, offset of tss is in d1,
          * prev (the current task) is in a0, next (the new task)
@@ -355,7 +355,7 @@ SYMBOL_NAME_LABEL(resume)
 
         /* disable interrupts */
         orc     #0x80,ccr
-        mov.l   @SYMBOL_NAME(sw_usp),er3
+        mov.l   @_sw_usp,er3
         mov.l   er3,@(THREAD_USP:16,er0)
         mov.l   sp,@(THREAD_KSP:16,er0)
 
@@ -363,7 +363,7 @@ SYMBOL_NAME_LABEL(resume)
         /* FIXME: what did we hack out of here, this does nothing! */
 
         mov.l   @(THREAD_USP:16,er1),er0
-        mov.l   er0,@SYMBOL_NAME(sw_usp)
+        mov.l   er0,@_sw_usp
         mov.l   @(THREAD_KSP:16,er1),sp
 
         /* restore status register */
@@ -372,15 +372,15 @@ SYMBOL_NAME_LABEL(resume)
         ldc     r3l,ccr
         rts
 
-SYMBOL_NAME_LABEL(trace_break)
+_trace_break:
         subs    #4,sp
         SAVE_ALL
         sub.l   er1,er1
         dec.l   #1,er1
         mov.l   er1,@(LORIG,sp)
         mov.l   sp,er0
-        jsr     @SYMBOL_NAME(set_esp0)
-        mov.l   @SYMBOL_NAME(sw_usp),er0
+        jsr     @_set_esp0
+        mov.l   @_sw_usp,er0
         mov.l   @er0,er1
         mov.w   @(-2:16,er1),r2
         cmp.w   #0x5730,r2
@@ -390,13 +390,13 @@ SYMBOL_NAME_LABEL(trace_break)
 1:
         and.w   #0xff,e1
         mov.l   er1,er0
-        jsr     @SYMBOL_NAME(trace_trap)
-        jmp     @SYMBOL_NAME(ret_from_exception)
+        jsr     @_trace_trap
+        jmp     @_ret_from_exception
 
         .section        .bss
-SYMBOL_NAME_LABEL(sw_ksp)
+_sw_ksp:
         .space  4
-SYMBOL_NAME_LABEL(sw_usp)
+_sw_usp:
         .space  4
 
         .end
diff --git a/arch/h8300/kernel/syscalls.S b/arch/h8300/kernel/syscalls.S
index 5c2168fb9b9e..c55e0ed270d5 100644
--- a/arch/h8300/kernel/syscalls.S
+++ b/arch/h8300/kernel/syscalls.S
@@ -2,8 +2,10 @@
 #include <linux/sys.h>
 #include <asm/linkage.h>
 #include <asm/unistd.h>
-        
-.globl SYMBOL_NAME(sys_call_table)
+
+#define CALL(x) .long _ ## x
+
+.globl _sys_call_table
 
 #if defined(CONFIG_CPU_H8300H)
         .h8300h
@@ -13,324 +15,324 @@
 #endif
         .section .text
         .align  2
-SYMBOL_NAME_LABEL(sys_call_table)       
-        .long SYMBOL_NAME(sys_ni_syscall)       /* 0  -  old "setup()" system call*/
-        .long SYMBOL_NAME(sys_exit)
-        .long SYMBOL_NAME(sys_fork)
-        .long SYMBOL_NAME(sys_read)
-        .long SYMBOL_NAME(sys_write)
-        .long SYMBOL_NAME(sys_open)             /* 5 */
-        .long SYMBOL_NAME(sys_close)
-        .long SYMBOL_NAME(sys_waitpid)
-        .long SYMBOL_NAME(sys_creat)
-        .long SYMBOL_NAME(sys_link)
-        .long SYMBOL_NAME(sys_unlink)           /* 10 */
-        .long SYMBOL_NAME(sys_execve)
-        .long SYMBOL_NAME(sys_chdir)
-        .long SYMBOL_NAME(sys_time)
-        .long SYMBOL_NAME(sys_mknod)
-        .long SYMBOL_NAME(sys_chmod)            /* 15 */
-        .long SYMBOL_NAME(sys_chown16)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old break syscall holder */
-        .long SYMBOL_NAME(sys_stat)
-        .long SYMBOL_NAME(sys_lseek)
-        .long SYMBOL_NAME(sys_getpid)           /* 20 */
-        .long SYMBOL_NAME(sys_mount)
-        .long SYMBOL_NAME(sys_oldumount)
-        .long SYMBOL_NAME(sys_setuid16)
-        .long SYMBOL_NAME(sys_getuid16)
-        .long SYMBOL_NAME(sys_stime)            /* 25 */
-        .long SYMBOL_NAME(sys_ptrace)
-        .long SYMBOL_NAME(sys_alarm)
-        .long SYMBOL_NAME(sys_fstat)
-        .long SYMBOL_NAME(sys_pause)
-        .long SYMBOL_NAME(sys_utime)            /* 30 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old stty syscall holder */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old gtty syscall holder */
-        .long SYMBOL_NAME(sys_access)
-        .long SYMBOL_NAME(sys_nice)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* 35 old ftime syscall holder */
-        .long SYMBOL_NAME(sys_sync)
-        .long SYMBOL_NAME(sys_kill)
-        .long SYMBOL_NAME(sys_rename)
-        .long SYMBOL_NAME(sys_mkdir)
-        .long SYMBOL_NAME(sys_rmdir)            /* 40 */
-        .long SYMBOL_NAME(sys_dup)
-        .long SYMBOL_NAME(sys_pipe)
-        .long SYMBOL_NAME(sys_times)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old prof syscall holder */
-        .long SYMBOL_NAME(sys_brk)              /* 45 */
-        .long SYMBOL_NAME(sys_setgid16)
-        .long SYMBOL_NAME(sys_getgid16)
-        .long SYMBOL_NAME(sys_signal)
-        .long SYMBOL_NAME(sys_geteuid16)
-        .long SYMBOL_NAME(sys_getegid16)        /* 50 */
-        .long SYMBOL_NAME(sys_acct)
-        .long SYMBOL_NAME(sys_umount)           /* recycled never used phys() */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old lock syscall holder */
-        .long SYMBOL_NAME(sys_ioctl)
-        .long SYMBOL_NAME(sys_fcntl)            /* 55 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old mpx syscall holder */
-        .long SYMBOL_NAME(sys_setpgid)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old ulimit syscall holder */
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_umask)            /* 60 */
-        .long SYMBOL_NAME(sys_chroot)
-        .long SYMBOL_NAME(sys_ustat)
-        .long SYMBOL_NAME(sys_dup2)
-        .long SYMBOL_NAME(sys_getppid)
-        .long SYMBOL_NAME(sys_getpgrp)          /* 65 */
-        .long SYMBOL_NAME(sys_setsid)
-        .long SYMBOL_NAME(sys_sigaction)
-        .long SYMBOL_NAME(sys_sgetmask)
-        .long SYMBOL_NAME(sys_ssetmask)
-        .long SYMBOL_NAME(sys_setreuid16)       /* 70 */
-        .long SYMBOL_NAME(sys_setregid16)
-        .long SYMBOL_NAME(sys_sigsuspend)
-        .long SYMBOL_NAME(sys_sigpending)
-        .long SYMBOL_NAME(sys_sethostname)
-        .long SYMBOL_NAME(sys_setrlimit)        /* 75 */
-        .long SYMBOL_NAME(sys_old_getrlimit)
-        .long SYMBOL_NAME(sys_getrusage)
-        .long SYMBOL_NAME(sys_gettimeofday)
-        .long SYMBOL_NAME(sys_settimeofday)
-        .long SYMBOL_NAME(sys_getgroups16)      /* 80 */
-        .long SYMBOL_NAME(sys_setgroups16)
-        .long SYMBOL_NAME(sys_old_select)
-        .long SYMBOL_NAME(sys_symlink)
-        .long SYMBOL_NAME(sys_lstat)
-        .long SYMBOL_NAME(sys_readlink)         /* 85 */
-        .long SYMBOL_NAME(sys_uselib)
-        .long SYMBOL_NAME(sys_swapon)
-        .long SYMBOL_NAME(sys_reboot)
-        .long SYMBOL_NAME(sys_old_readdir)
-        .long SYMBOL_NAME(sys_old_mmap)         /* 90 */
-        .long SYMBOL_NAME(sys_munmap)
-        .long SYMBOL_NAME(sys_truncate)
-        .long SYMBOL_NAME(sys_ftruncate)
-        .long SYMBOL_NAME(sys_fchmod)
-        .long SYMBOL_NAME(sys_fchown16)         /* 95 */
-        .long SYMBOL_NAME(sys_getpriority)
-        .long SYMBOL_NAME(sys_setpriority)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old profil syscall holder */
-        .long SYMBOL_NAME(sys_statfs)
-        .long SYMBOL_NAME(sys_fstatfs)          /* 100 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* ioperm for i386 */
-        .long SYMBOL_NAME(sys_socketcall)
-        .long SYMBOL_NAME(sys_syslog)
-        .long SYMBOL_NAME(sys_setitimer)
-        .long SYMBOL_NAME(sys_getitimer)        /* 105 */
-        .long SYMBOL_NAME(sys_newstat)
-        .long SYMBOL_NAME(sys_newlstat)
-        .long SYMBOL_NAME(sys_newfstat)
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* iopl for i386 */ /* 110 */
-        .long SYMBOL_NAME(sys_vhangup)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* obsolete idle() syscall */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* vm86old for i386 */
-        .long SYMBOL_NAME(sys_wait4)
-        .long SYMBOL_NAME(sys_swapoff)          /* 115 */
-        .long SYMBOL_NAME(sys_sysinfo)
-        .long SYMBOL_NAME(sys_ipc)
-        .long SYMBOL_NAME(sys_fsync)
-        .long SYMBOL_NAME(sys_sigreturn)
-        .long SYMBOL_NAME(sys_clone)            /* 120 */
-        .long SYMBOL_NAME(sys_setdomainname)
-        .long SYMBOL_NAME(sys_newuname)
-        .long SYMBOL_NAME(sys_cacheflush)       /* modify_ldt for i386 */
-        .long SYMBOL_NAME(sys_adjtimex)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* 125 sys_mprotect */
-        .long SYMBOL_NAME(sys_sigprocmask)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_create_module */
-        .long SYMBOL_NAME(sys_init_module)
-        .long SYMBOL_NAME(sys_delete_module)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* 130 sys_get_kernel_syms */
-        .long SYMBOL_NAME(sys_quotactl)
-        .long SYMBOL_NAME(sys_getpgid)
-        .long SYMBOL_NAME(sys_fchdir)
-        .long SYMBOL_NAME(sys_bdflush)
-        .long SYMBOL_NAME(sys_sysfs)            /* 135 */
-        .long SYMBOL_NAME(sys_personality)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* for afs_syscall */
-        .long SYMBOL_NAME(sys_setfsuid16)
-        .long SYMBOL_NAME(sys_setfsgid16)
-        .long SYMBOL_NAME(sys_llseek)           /* 140 */
-        .long SYMBOL_NAME(sys_getdents)
-        .long SYMBOL_NAME(sys_select)
-        .long SYMBOL_NAME(sys_flock)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_msync */
-        .long SYMBOL_NAME(sys_readv)            /* 145 */
-        .long SYMBOL_NAME(sys_writev)
-        .long SYMBOL_NAME(sys_getsid)
-        .long SYMBOL_NAME(sys_fdatasync)
-        .long SYMBOL_NAME(sys_sysctl)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* 150 sys_mlock */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_munlock */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_mlockall */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_munlockall */
-        .long SYMBOL_NAME(sys_sched_setparam)
-        .long SYMBOL_NAME(sys_sched_getparam)   /* 155 */
-        .long SYMBOL_NAME(sys_sched_setscheduler)
-        .long SYMBOL_NAME(sys_sched_getscheduler)
-        .long SYMBOL_NAME(sys_sched_yield)
-        .long SYMBOL_NAME(sys_sched_get_priority_max)
-        .long SYMBOL_NAME(sys_sched_get_priority_min)  /* 160 */
-        .long SYMBOL_NAME(sys_sched_rr_get_interval)
-        .long SYMBOL_NAME(sys_nanosleep)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_mremap */
-        .long SYMBOL_NAME(sys_setresuid16)
-        .long SYMBOL_NAME(sys_getresuid16)      /* 165 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* for vm86 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_query_module */
-        .long SYMBOL_NAME(sys_poll)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* old nfsservctl */
-        .long SYMBOL_NAME(sys_setresgid16)      /* 170 */
-        .long SYMBOL_NAME(sys_getresgid16)
-        .long SYMBOL_NAME(sys_prctl)
-        .long SYMBOL_NAME(sys_rt_sigreturn)
-        .long SYMBOL_NAME(sys_rt_sigaction)
-        .long SYMBOL_NAME(sys_rt_sigprocmask)   /* 175 */
-        .long SYMBOL_NAME(sys_rt_sigpending)
-        .long SYMBOL_NAME(sys_rt_sigtimedwait)
-        .long SYMBOL_NAME(sys_rt_sigqueueinfo)
-        .long SYMBOL_NAME(sys_rt_sigsuspend)
-        .long SYMBOL_NAME(sys_pread64)          /* 180 */
-        .long SYMBOL_NAME(sys_pwrite64)
-        .long SYMBOL_NAME(sys_lchown16);
-        .long SYMBOL_NAME(sys_getcwd)
-        .long SYMBOL_NAME(sys_capget)
-        .long SYMBOL_NAME(sys_capset)           /* 185 */
-        .long SYMBOL_NAME(sys_sigaltstack)
-        .long SYMBOL_NAME(sys_sendfile)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* streams1 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* streams2 */
-        .long SYMBOL_NAME(sys_vfork)            /* 190 */
-        .long SYMBOL_NAME(sys_getrlimit)
-        .long SYMBOL_NAME(sys_mmap_pgoff)
-        .long SYMBOL_NAME(sys_truncate64)
-        .long SYMBOL_NAME(sys_ftruncate64)
-        .long SYMBOL_NAME(sys_stat64)           /* 195 */
-        .long SYMBOL_NAME(sys_lstat64)
-        .long SYMBOL_NAME(sys_fstat64)
-        .long SYMBOL_NAME(sys_chown)
-        .long SYMBOL_NAME(sys_getuid)
-        .long SYMBOL_NAME(sys_getgid)           /* 200 */
-        .long SYMBOL_NAME(sys_geteuid)
-        .long SYMBOL_NAME(sys_getegid)
-        .long SYMBOL_NAME(sys_setreuid)
-        .long SYMBOL_NAME(sys_setregid)
-        .long SYMBOL_NAME(sys_getgroups)        /* 205 */
-        .long SYMBOL_NAME(sys_setgroups)
-        .long SYMBOL_NAME(sys_fchown)
-        .long SYMBOL_NAME(sys_setresuid)
-        .long SYMBOL_NAME(sys_getresuid)
-        .long SYMBOL_NAME(sys_setresgid)        /* 210 */
-        .long SYMBOL_NAME(sys_getresgid)
-        .long SYMBOL_NAME(sys_lchown)
-        .long SYMBOL_NAME(sys_setuid)
-        .long SYMBOL_NAME(sys_setgid)
-        .long SYMBOL_NAME(sys_setfsuid)         /* 215 */
-        .long SYMBOL_NAME(sys_setfsgid)
-        .long SYMBOL_NAME(sys_pivot_root)
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_getdents64)       /* 220 */
-        .long SYMBOL_NAME(sys_fcntl64)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* reserved TUX */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* reserved Security */
-        .long SYMBOL_NAME(sys_gettid)
-        .long SYMBOL_NAME(sys_readahead)        /* 225 */
-        .long SYMBOL_NAME(sys_setxattr)
-        .long SYMBOL_NAME(sys_lsetxattr)
-        .long SYMBOL_NAME(sys_fsetxattr)
-        .long SYMBOL_NAME(sys_getxattr)
-        .long SYMBOL_NAME(sys_lgetxattr)        /* 230 */
-        .long SYMBOL_NAME(sys_fgetxattr)
-        .long SYMBOL_NAME(sys_listxattr)
-        .long SYMBOL_NAME(sys_llistxattr)
-        .long SYMBOL_NAME(sys_flistxattr)
-        .long SYMBOL_NAME(sys_removexattr)      /* 235 */
-        .long SYMBOL_NAME(sys_lremovexattr)
-        .long SYMBOL_NAME(sys_fremovexattr)
-        .long SYMBOL_NAME(sys_tkill)
-        .long SYMBOL_NAME(sys_sendfile64)
-        .long SYMBOL_NAME(sys_futex)            /* 240 */
-        .long SYMBOL_NAME(sys_sched_setaffinity)
-        .long SYMBOL_NAME(sys_sched_getaffinity)
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_io_setup)         /* 245 */
-        .long SYMBOL_NAME(sys_io_destroy)
-        .long SYMBOL_NAME(sys_io_getevents)
-        .long SYMBOL_NAME(sys_io_submit)
-        .long SYMBOL_NAME(sys_io_cancel)
-        .long SYMBOL_NAME(sys_fadvise64)        /* 250 */
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_exit_group)
-        .long SYMBOL_NAME(sys_lookup_dcookie)
-        .long SYMBOL_NAME(sys_epoll_create)
-        .long SYMBOL_NAME(sys_epoll_ctl)        /* 255 */
-        .long SYMBOL_NAME(sys_epoll_wait)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_remap_file_pages */
-        .long SYMBOL_NAME(sys_set_tid_address)
-        .long SYMBOL_NAME(sys_timer_create)
-        .long SYMBOL_NAME(sys_timer_settime)    /* 260 */
-        .long SYMBOL_NAME(sys_timer_gettime)
-        .long SYMBOL_NAME(sys_timer_getoverrun)
-        .long SYMBOL_NAME(sys_timer_delete)
-        .long SYMBOL_NAME(sys_clock_settime)
-        .long SYMBOL_NAME(sys_clock_gettime)    /* 265 */
-        .long SYMBOL_NAME(sys_clock_getres)
-        .long SYMBOL_NAME(sys_clock_nanosleep)
-        .long SYMBOL_NAME(sys_statfs64)
-        .long SYMBOL_NAME(sys_fstatfs64)        
-        .long SYMBOL_NAME(sys_tgkill)           /* 270 */
-        .long SYMBOL_NAME(sys_utimes)
-        .long SYMBOL_NAME(sys_fadvise64_64)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_vserver */
-        .long SYMBOL_NAME(sys_ni_syscall)
-        .long SYMBOL_NAME(sys_get_mempolicy)    /* 275 */
-        .long SYMBOL_NAME(sys_set_mempolicy)
-        .long SYMBOL_NAME(sys_mq_open)
-        .long SYMBOL_NAME(sys_mq_unlink)
-        .long SYMBOL_NAME(sys_mq_timedsend)
-        .long SYMBOL_NAME(sys_mq_timedreceive)  /* 280 */
-        .long SYMBOL_NAME(sys_mq_notify)
-        .long SYMBOL_NAME(sys_mq_getsetattr)
-        .long SYMBOL_NAME(sys_waitid)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_kexec_load */
-        .long SYMBOL_NAME(sys_add_key)          /* 285 */
-        .long SYMBOL_NAME(sys_request_key)
-        .long SYMBOL_NAME(sys_keyctl)
-        .long SYMBOL_NAME(sys_ioprio_set)
-        .long SYMBOL_NAME(sys_ioprio_get)       /* 290 */
-        .long SYMBOL_NAME(sys_inotify_init)
-        .long SYMBOL_NAME(sys_inotify_add_watch)
-        .long SYMBOL_NAME(sys_inotify_rm_watch)
-        .long SYMBOL_NAME(sys_migrate_pages)
-        .long SYMBOL_NAME(sys_openat)           /* 295 */
-        .long SYMBOL_NAME(sys_mkdirat)
-        .long SYMBOL_NAME(sys_mknodat)
-        .long SYMBOL_NAME(sys_fchownat)
-        .long SYMBOL_NAME(sys_futimesat)
-        .long SYMBOL_NAME(sys_fstatat64)        /* 300 */
-        .long SYMBOL_NAME(sys_unlinkat)
-        .long SYMBOL_NAME(sys_renameat)
-        .long SYMBOL_NAME(sys_linkat)
-        .long SYMBOL_NAME(sys_symlinkat)
-        .long SYMBOL_NAME(sys_readlinkat)       /* 305 */
-        .long SYMBOL_NAME(sys_fchmodat)
-        .long SYMBOL_NAME(sys_faccessat)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_pselect6 */
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_ppoll */
-        .long SYMBOL_NAME(sys_unshare)          /* 310 */
-        .long SYMBOL_NAME(sys_set_robust_list)
-        .long SYMBOL_NAME(sys_get_robust_list)
-        .long SYMBOL_NAME(sys_splice)
-        .long SYMBOL_NAME(sys_sync_file_range)
-        .long SYMBOL_NAME(sys_tee)              /* 315 */
-        .long SYMBOL_NAME(sys_vmsplice)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_move_pages */
-        .long SYMBOL_NAME(sys_getcpu)
-        .long SYMBOL_NAME(sys_ni_syscall)       /* sys_epoll_pwait */
-        .long SYMBOL_NAME(sys_setns)            /* 320 */
+_sys_call_table:
+        CALL(sys_ni_syscall)            /* 0  -  old "setup()" system call*/
+        CALL(sys_exit)
+        CALL(sys_fork)
+        CALL(sys_read)
+        CALL(sys_write)
+        CALL(sys_open)                  /* 5 */
+        CALL(sys_close)
+        CALL(sys_waitpid)
+        CALL(sys_creat)
+        CALL(sys_link)
+        CALL(sys_unlink)                /* 10 */
+        CALL(sys_execve)
+        CALL(sys_chdir)
+        CALL(sys_time)
+        CALL(sys_mknod)
+        CALL(sys_chmod)                 /* 15 */
+        CALL(sys_chown16)
+        CALL(sys_ni_syscall)            /* old break syscall holder */
+        CALL(sys_stat)
+        CALL(sys_lseek)
+        CALL(sys_getpid)                /* 20 */
+        CALL(sys_mount)
+        CALL(sys_oldumount)
+        CALL(sys_setuid16)
+        CALL(sys_getuid16)
+        CALL(sys_stime)                 /* 25 */
+        CALL(sys_ptrace)
+        CALL(sys_alarm)
+        CALL(sys_fstat)
+        CALL(sys_pause)
+        CALL(sys_utime)                 /* 30 */
+        CALL(sys_ni_syscall)            /* old stty syscall holder */
+        CALL(sys_ni_syscall)            /* old gtty syscall holder */
+        CALL(sys_access)
+        CALL(sys_nice)
+        CALL(sys_ni_syscall)            /* 35 old ftime syscall holder */
+        CALL(sys_sync)
+        CALL(sys_kill)
+        CALL(sys_rename)
+        CALL(sys_mkdir)
+        CALL(sys_rmdir)                 /* 40 */
+        CALL(sys_dup)
+        CALL(sys_pipe)
+        CALL(sys_times)
+        CALL(sys_ni_syscall)            /* old prof syscall holder */
+        CALL(sys_brk)                   /* 45 */
+        CALL(sys_setgid16)
+        CALL(sys_getgid16)
+        CALL(sys_signal)
+        CALL(sys_geteuid16)
+        CALL(sys_getegid16)             /* 50 */
+        CALL(sys_acct)
+        CALL(sys_umount)                /* recycled never used phys() */
+        CALL(sys_ni_syscall)            /* old lock syscall holder */
+        CALL(sys_ioctl)
+        CALL(sys_fcntl)                 /* 55 */
+        CALL(sys_ni_syscall)            /* old mpx syscall holder */
+        CALL(sys_setpgid)
+        CALL(sys_ni_syscall)            /* old ulimit syscall holder */
+        CALL(sys_ni_syscall)
+        CALL(sys_umask)                 /* 60 */
+        CALL(sys_chroot)
+        CALL(sys_ustat)
+        CALL(sys_dup2)
+        CALL(sys_getppid)
+        CALL(sys_getpgrp)               /* 65 */
+        CALL(sys_setsid)
+        CALL(sys_sigaction)
+        CALL(sys_sgetmask)
+        CALL(sys_ssetmask)
+        CALL(sys_setreuid16)            /* 70 */
+        CALL(sys_setregid16)
+        CALL(sys_sigsuspend)
+        CALL(sys_sigpending)
+        CALL(sys_sethostname)
+        CALL(sys_setrlimit)             /* 75 */
+        CALL(sys_old_getrlimit)
+        CALL(sys_getrusage)
+        CALL(sys_gettimeofday)
+        CALL(sys_settimeofday)
+        CALL(sys_getgroups16)           /* 80 */
+        CALL(sys_setgroups16)
+        CALL(sys_old_select)
+        CALL(sys_symlink)
+        CALL(sys_lstat)
+        CALL(sys_readlink)              /* 85 */
+        CALL(sys_uselib)
+        CALL(sys_swapon)
+        CALL(sys_reboot)
+        CALL(sys_old_readdir)
+        CALL(sys_old_mmap)              /* 90 */
+        CALL(sys_munmap)
+        CALL(sys_truncate)
+        CALL(sys_ftruncate)
+        CALL(sys_fchmod)
+        CALL(sys_fchown16)              /* 95 */
+        CALL(sys_getpriority)
+        CALL(sys_setpriority)
+        CALL(sys_ni_syscall)            /* old profil syscall holder */
+        CALL(sys_statfs)
+        CALL(sys_fstatfs)               /* 100 */
+        CALL(sys_ni_syscall)            /* ioperm for i386 */
+        CALL(sys_socketcall)
+        CALL(sys_syslog)
+        CALL(sys_setitimer)
+        CALL(sys_getitimer)             /* 105 */
+        CALL(sys_newstat)
+        CALL(sys_newlstat)
+        CALL(sys_newfstat)
+        CALL(sys_ni_syscall)
+        CALL(sys_ni_syscall)            /* iopl for i386 */ /* 110 */
+        CALL(sys_vhangup)
+        CALL(sys_ni_syscall)            /* obsolete idle() syscall */
+        CALL(sys_ni_syscall)            /* vm86old for i386 */
+        CALL(sys_wait4)
+        CALL(sys_swapoff)               /* 115 */
+        CALL(sys_sysinfo)
+        CALL(sys_ipc)
+        CALL(sys_fsync)
+        CALL(sys_sigreturn)
+        CALL(sys_clone)                 /* 120 */
+        CALL(sys_setdomainname)
+        CALL(sys_newuname)
+        CALL(sys_cacheflush)            /* modify_ldt for i386 */
+        CALL(sys_adjtimex)
+        CALL(sys_ni_syscall)            /* 125 sys_mprotect */
+        CALL(sys_sigprocmask)
+        CALL(sys_ni_syscall)            /* sys_create_module */
+        CALL(sys_init_module)
+        CALL(sys_delete_module)
+        CALL(sys_ni_syscall)            /* 130 sys_get_kernel_syms */
+        CALL(sys_quotactl)
+        CALL(sys_getpgid)
+        CALL(sys_fchdir)
+        CALL(sys_bdflush)
+        CALL(sys_sysfs)                 /* 135 */
+        CALL(sys_personality)
+        CALL(sys_ni_syscall)            /* for afs_syscall */
+        CALL(sys_setfsuid16)
+        CALL(sys_setfsgid16)
+        CALL(sys_llseek)                /* 140 */
+        CALL(sys_getdents)
+        CALL(sys_select)
+        CALL(sys_flock)
+        CALL(sys_ni_syscall)            /* sys_msync */
+        CALL(sys_readv)                 /* 145 */
+        CALL(sys_writev)
+        CALL(sys_getsid)
+        CALL(sys_fdatasync)
+        CALL(sys_sysctl)
+        CALL(sys_ni_syscall)            /* 150 sys_mlock */
+        CALL(sys_ni_syscall)            /* sys_munlock */
+        CALL(sys_ni_syscall)            /* sys_mlockall */
+        CALL(sys_ni_syscall)            /* sys_munlockall */
+        CALL(sys_sched_setparam)
+        CALL(sys_sched_getparam)        /* 155 */
+        CALL(sys_sched_setscheduler)
+        CALL(sys_sched_getscheduler)
+        CALL(sys_sched_yield)
+        CALL(sys_sched_get_priority_max)
+        CALL(sys_sched_get_priority_min)  /* 160 */
+        CALL(sys_sched_rr_get_interval)
+        CALL(sys_nanosleep)
+        CALL(sys_ni_syscall)            /* sys_mremap */
+        CALL(sys_setresuid16)
+        CALL(sys_getresuid16)           /* 165 */
+        CALL(sys_ni_syscall)            /* for vm86 */
+        CALL(sys_ni_syscall)            /* sys_query_module */
+        CALL(sys_poll)
+        CALL(sys_ni_syscall)            /* old nfsservctl */
+        CALL(sys_setresgid16)           /* 170 */
+        CALL(sys_getresgid16)
+        CALL(sys_prctl)
+        CALL(sys_rt_sigreturn)
+        CALL(sys_rt_sigaction)
+        CALL(sys_rt_sigprocmask)        /* 175 */
+        CALL(sys_rt_sigpending)
+        CALL(sys_rt_sigtimedwait)
+        CALL(sys_rt_sigqueueinfo)
+        CALL(sys_rt_sigsuspend)
+        CALL(sys_pread64)               /* 180 */
+        CALL(sys_pwrite64)
+        CALL(sys_lchown16);
+        CALL(sys_getcwd)
+        CALL(sys_capget)
+        CALL(sys_capset)                /* 185 */
+        CALL(sys_sigaltstack)
+        CALL(sys_sendfile)
+        CALL(sys_ni_syscall)            /* streams1 */
+        CALL(sys_ni_syscall)            /* streams2 */
+        CALL(sys_vfork)                 /* 190 */
+        CALL(sys_getrlimit)
+        CALL(sys_mmap_pgoff)
+        CALL(sys_truncate64)
+        CALL(sys_ftruncate64)
+        CALL(sys_stat64)                /* 195 */
+        CALL(sys_lstat64)
+        CALL(sys_fstat64)
+        CALL(sys_chown)
+        CALL(sys_getuid)
+        CALL(sys_getgid)                /* 200 */
+        CALL(sys_geteuid)
+        CALL(sys_getegid)
+        CALL(sys_setreuid)
+        CALL(sys_setregid)
+        CALL(sys_getgroups)             /* 205 */
+        CALL(sys_setgroups)
+        CALL(sys_fchown)
+        CALL(sys_setresuid)
+        CALL(sys_getresuid)
+        CALL(sys_setresgid)             /* 210 */
+        CALL(sys_getresgid)
+        CALL(sys_lchown)
+        CALL(sys_setuid)
+        CALL(sys_setgid)
+        CALL(sys_setfsuid)              /* 215 */
+        CALL(sys_setfsgid)
+        CALL(sys_pivot_root)
+        CALL(sys_ni_syscall)
+        CALL(sys_ni_syscall)
+        CALL(sys_getdents64)            /* 220 */
+        CALL(sys_fcntl64)
+        CALL(sys_ni_syscall)            /* reserved TUX */
+        CALL(sys_ni_syscall)            /* reserved Security */
+        CALL(sys_gettid)
+        CALL(sys_readahead)             /* 225 */
+        CALL(sys_setxattr)
+        CALL(sys_lsetxattr)
+        CALL(sys_fsetxattr)
+        CALL(sys_getxattr)
+        CALL(sys_lgetxattr)             /* 230 */
+        CALL(sys_fgetxattr)
+        CALL(sys_listxattr)
+        CALL(sys_llistxattr)
+        CALL(sys_flistxattr)
+        CALL(sys_removexattr)           /* 235 */
+        CALL(sys_lremovexattr)
+        CALL(sys_fremovexattr)
+        CALL(sys_tkill)
+        CALL(sys_sendfile64)
+        CALL(sys_futex)                 /* 240 */
+        CALL(sys_sched_setaffinity)
+        CALL(sys_sched_getaffinity)
+        CALL(sys_ni_syscall)
+        CALL(sys_ni_syscall)
+        CALL(sys_io_setup)              /* 245 */
+        CALL(sys_io_destroy)
+        CALL(sys_io_getevents)
+        CALL(sys_io_submit)
+        CALL(sys_io_cancel)
+        CALL(sys_fadvise64)             /* 250 */
+        CALL(sys_ni_syscall)
+        CALL(sys_exit_group)
+        CALL(sys_lookup_dcookie)
+        CALL(sys_epoll_create)
+        CALL(sys_epoll_ctl)             /* 255 */
+        CALL(sys_epoll_wait)
+        CALL(sys_ni_syscall)            /* sys_remap_file_pages */
+        CALL(sys_set_tid_address)
+        CALL(sys_timer_create)
+        CALL(sys_timer_settime)         /* 260 */
+        CALL(sys_timer_gettime)
+        CALL(sys_timer_getoverrun)
+        CALL(sys_timer_delete)
+        CALL(sys_clock_settime)
+        CALL(sys_clock_gettime)         /* 265 */
+        CALL(sys_clock_getres)
+        CALL(sys_clock_nanosleep)
+        CALL(sys_statfs64)
+        CALL(sys_fstatfs64)
+        CALL(sys_tgkill)                /* 270 */
+        CALL(sys_utimes)
+        CALL(sys_fadvise64_64)
+        CALL(sys_ni_syscall)            /* sys_vserver */
+        CALL(sys_ni_syscall)
+        CALL(sys_get_mempolicy)         /* 275 */
+        CALL(sys_set_mempolicy)
+        CALL(sys_mq_open)
+        CALL(sys_mq_unlink)
+        CALL(sys_mq_timedsend)
+        CALL(sys_mq_timedreceive)       /* 280 */
+        CALL(sys_mq_notify)
+        CALL(sys_mq_getsetattr)
+        CALL(sys_waitid)
+        CALL(sys_ni_syscall)            /* sys_kexec_load */
+        CALL(sys_add_key)               /* 285 */
+        CALL(sys_request_key)
+        CALL(sys_keyctl)
+        CALL(sys_ioprio_set)
+        CALL(sys_ioprio_get)            /* 290 */
+        CALL(sys_inotify_init)
+        CALL(sys_inotify_add_watch)
+        CALL(sys_inotify_rm_watch)
+        CALL(sys_migrate_pages)
+        CALL(sys_openat)                /* 295 */
+        CALL(sys_mkdirat)
+        CALL(sys_mknodat)
+        CALL(sys_fchownat)
+        CALL(sys_futimesat)
+        CALL(sys_fstatat64)             /* 300 */
+        CALL(sys_unlinkat)
+        CALL(sys_renameat)
+        CALL(sys_linkat)
+        CALL(sys_symlinkat)
+        CALL(sys_readlinkat)            /* 305 */
+        CALL(sys_fchmodat)
+        CALL(sys_faccessat)
+        CALL(sys_ni_syscall)            /* sys_pselect6 */
+        CALL(sys_ni_syscall)            /* sys_ppoll */
+        CALL(sys_unshare)               /* 310 */
+        CALL(sys_set_robust_list)
+        CALL(sys_get_robust_list)
+        CALL(sys_splice)
+        CALL(sys_sync_file_range)
+        CALL(sys_tee)                   /* 315 */
+        CALL(sys_vmsplice)
+        CALL(sys_ni_syscall)            /* sys_move_pages */
+        CALL(sys_getcpu)
+        CALL(sys_ni_syscall)            /* sys_epoll_pwait */
+        CALL(sys_setns)                 /* 320 */
diff --git a/arch/h8300/kernel/vmlinux.lds.S b/arch/h8300/kernel/vmlinux.lds.S
index 03d356d96e5d..3253fed42ac1 100644
--- a/arch/h8300/kernel/vmlinux.lds.S
+++ b/arch/h8300/kernel/vmlinux.lds.S
@@ -132,10 +132,12 @@ SECTIONS
         {
         . = ALIGN(0x4) ;
         __sbss = . ;
+        ___bss_start = . ;
                 *(.bss*)
         . = ALIGN(0x4) ;
                 *(COMMON)
         . = ALIGN(0x4) ;
+        ___bss_stop = . ;
         __ebss = . ;
         __end = . ;
         __ramstart = .;
diff --git a/arch/h8300/lib/abs.S b/arch/h8300/lib/abs.S
index cabdd46b41db..ddd1fb3d01ad 100644
--- a/arch/h8300/lib/abs.S
+++ b/arch/h8300/lib/abs.S
@@ -9,10 +9,10 @@
         .h8300s
 #endif
         .text
-.global SYMBOL_NAME(abs)
+.global _abs
 
 ;;; int abs(int n)
-SYMBOL_NAME_LABEL(abs)
+_abs:
         mov.l   er0,er0
         bpl     1f
         neg.l   er0
diff --git a/arch/h8300/lib/memcpy.S b/arch/h8300/lib/memcpy.S
index fdcbc1ee673c..cad325e2c0e8 100644
--- a/arch/h8300/lib/memcpy.S
+++ b/arch/h8300/lib/memcpy.S
@@ -10,10 +10,10 @@
 #endif
 
         .text
-.global SYMBOL_NAME(memcpy)
+.global _memcpy
 
 ;;; void *memcpy(void *to, void *from, size_t n)
-SYMBOL_NAME_LABEL(memcpy)
+_memcpy:
         mov.l   er2,er2
         bne     1f
         rts     
diff --git a/arch/h8300/lib/memset.S b/arch/h8300/lib/memset.S
index 59abdf9485a5..4549a64c5b79 100644
--- a/arch/h8300/lib/memset.S
+++ b/arch/h8300/lib/memset.S
@@ -10,13 +10,13 @@
 #endif
         .text
 
-.global SYMBOL_NAME(memset)
+.global _memset
 
 ;;void *memset(*ptr, int c, size_t count)
 ;; ptr = er0
 ;; c   = er1(r1l)
 ;; count = er2
-SYMBOL_NAME_LABEL(memset)
+_memset:
         btst    #0,r0l
         beq     2f
 
diff --git a/arch/h8300/mm/init.c b/arch/h8300/mm/init.c
index ff349d70a29b..6c1251e491af 100644
--- a/arch/h8300/mm/init.c
+++ b/arch/h8300/mm/init.c
@@ -121,47 +121,27 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        int codek = 0, datak = 0, initk = 0;
-        /* DAVIDM look at setup memory map generically with reserved area */
-        unsigned long tmp;
-        extern unsigned long  _ramend, _ramstart;
-        unsigned long len = &_ramend - &_ramstart;
-        unsigned long start_mem = memory_start; /* DAVIDM - these must start at end of kernel */
-        unsigned long end_mem   = memory_end; /* DAVIDM - this must not include kernel stack at top */
+        unsigned long codesize = _etext - _stext;
 
-#ifdef DEBUG
-        printk(KERN_DEBUG "Mem_init: start=%lx, end=%lx\n", start_mem, end_mem);
-#endif
+        pr_devel("Mem_init: start=%lx, end=%lx\n", memory_start, memory_end);
 
-        end_mem &= PAGE_MASK;
-        high_memory = (void *) end_mem;
-
-        start_mem = PAGE_ALIGN(start_mem);
-        max_mapnr = num_physpages = MAP_NR(high_memory);
+        high_memory = (void *) (memory_end & PAGE_MASK);
+        max_mapnr = MAP_NR(high_memory);
 
         /* this will put all low memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-        codek = (_etext - _stext) >> 10;
-        datak = (__bss_stop - _sdata) >> 10;
-        initk = (__init_begin - __init_end) >> 10;
-
-        tmp = nr_free_pages() << PAGE_SHIFT;
-        printk(KERN_INFO "Memory available: %luk/%luk RAM, %luk/%luk ROM (%dk kernel code, %dk data)\n",
-               tmp >> 10,
-               len >> 10,
-               (rom_length > 0) ? ((rom_length >> 10) - codek) : 0,
-               rom_length >> 10,
-               codek,
-               datak
-               );
+        free_all_bootmem();
+
+        mem_init_print_info(NULL);
+        if (rom_length > 0 && rom_length > codesize)
+                pr_info("Memory available: %luK/%luK ROM\n",
+                        (rom_length - codesize) >> 10, rom_length >> 10);
 }
 
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
@@ -169,7 +149,7 @@ void
 free_initmem(void)
 {
 #ifdef CONFIG_RAMKERNEL
-        free_initmem_default(0);
+        free_initmem_default(-1);
 #endif
 }
 
diff --git a/arch/h8300/platform/h8300h/aki3068net/crt0_ram.S b/arch/h8300/platform/h8300h/aki3068net/crt0_ram.S
index ecaeb31ae9a4..b2ad0f2d0417 100644
--- a/arch/h8300/platform/h8300h/aki3068net/crt0_ram.S
+++ b/arch/h8300/platform/h8300h/aki3068net/crt0_ram.S
@@ -22,10 +22,10 @@
 #define RAMEND CONFIG_BLKDEV_RESERVE_ADDRESS
 #endif
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global _command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300h
 
@@ -33,7 +33,7 @@
         .file   "crt0_ram.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #RAMEND,sp
         ldc     #0x80,ccr
 
@@ -59,13 +59,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(command_line),er6
+        mov.l   #_command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* uClinux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
@@ -107,4 +107,4 @@ __target_name:
         .asciz  "AE-3068"
         
         .section .bootvec,"ax"
-        jmp     @SYMBOL_NAME(_start)
+        jmp     @__start
diff --git a/arch/h8300/platform/h8300h/generic/crt0_ram.S b/arch/h8300/platform/h8300h/generic/crt0_ram.S
index 80d0e16a4499..5ab7d9c12910 100644
--- a/arch/h8300/platform/h8300h/generic/crt0_ram.S
+++ b/arch/h8300/platform/h8300h/generic/crt0_ram.S
@@ -22,10 +22,10 @@
 #define RAMEND CONFIG_BLKDEV_RESERVE_ADDRESS
 #endif
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global _command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300h
 
@@ -33,7 +33,7 @@
         .file   "crt0_ram.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #RAMEND,sp
         ldc     #0x80,ccr
 
@@ -59,13 +59,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(command_line),er6
+        mov.l   #_command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* uClinux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
diff --git a/arch/h8300/platform/h8300h/generic/crt0_rom.S b/arch/h8300/platform/h8300h/generic/crt0_rom.S
index 120add7ca832..dda1dfa15a5e 100644
--- a/arch/h8300/platform/h8300h/generic/crt0_rom.S
+++ b/arch/h8300/platform/h8300h/generic/crt0_rom.S
@@ -12,17 +12,17 @@
 
 #include <asm/linkage.h>
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(_command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global __command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300h
         .section .text
         .file   "crt0_rom.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #__ramend,sp
         ldc     #0x80,ccr
 
@@ -60,13 +60,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(_command_line),er6
+        mov.l   #__command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* linux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
diff --git a/arch/h8300/platform/h8300h/h8max/crt0_ram.S b/arch/h8300/platform/h8300h/h8max/crt0_ram.S
index efcbefb91b67..6a0d4e2d9ec6 100644
--- a/arch/h8300/platform/h8300h/h8max/crt0_ram.S
+++ b/arch/h8300/platform/h8300h/h8max/crt0_ram.S
@@ -22,10 +22,10 @@
 #define RAMEND CONFIG_BLKDEV_RESERVE_ADDRESS
 #endif
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global _command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300h
 
@@ -33,7 +33,7 @@
         .file   "crt0_ram.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #RAMEND,sp
         ldc     #0x80,ccr
 
@@ -59,13 +59,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(command_line),er6
+        mov.l   #_command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* uClinux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
@@ -107,4 +107,4 @@ __target_name:
         .asciz  "H8MAX"
         
         .section .bootvec,"ax"
-        jmp     @SYMBOL_NAME(_start)
+        jmp     @__start
diff --git a/arch/h8300/platform/h8s/edosk2674/crt0_ram.S b/arch/h8300/platform/h8s/edosk2674/crt0_ram.S
index d12b0debe478..5ed191b37cde 100644
--- a/arch/h8300/platform/h8s/edosk2674/crt0_ram.S
+++ b/arch/h8300/platform/h8s/edosk2674/crt0_ram.S
@@ -23,10 +23,10 @@
 #define RAMEND CONFIG_BLKDEV_RESERVE_ADDRESS
 #endif
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(_command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global __command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300s
 
@@ -34,7 +34,7 @@
         .file   "crt0_ram.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #RAMEND,sp
         ldc     #0x80,ccr
         ldc     #0x00,exr
@@ -66,13 +66,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(command_line),er6
+        mov.l   #_command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* uClinux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
@@ -127,4 +127,4 @@ __target_name:
         .asciz  "EDOSK-2674"
         
         .section .bootvec,"ax"
-        jmp     @SYMBOL_NAME(_start)
+        jmp     @__start
diff --git a/arch/h8300/platform/h8s/edosk2674/crt0_rom.S b/arch/h8300/platform/h8s/edosk2674/crt0_rom.S
index c03d23c6fe12..06d1d7f324ca 100644
--- a/arch/h8300/platform/h8s/edosk2674/crt0_rom.S
+++ b/arch/h8300/platform/h8s/edosk2674/crt0_rom.S
@@ -13,17 +13,17 @@
 #include <asm/linkage.h>
 #include <asm/regs267x.h>
                 
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(_command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global __command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300s
         .section .text
         .file   "crt0_rom.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #__ramend,sp
         ldc     #0x80,ccr
         ldc     #0,exr
@@ -82,13 +82,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(_command_line),er6
+        mov.l   #__command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* linux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
diff --git a/arch/h8300/platform/h8s/generic/crt0_ram.S b/arch/h8300/platform/h8s/generic/crt0_ram.S
index b04541069976..7018915de74f 100644
--- a/arch/h8300/platform/h8s/generic/crt0_ram.S
+++ b/arch/h8300/platform/h8s/generic/crt0_ram.S
@@ -23,10 +23,10 @@
 #define RAMEND CONFIG_BLKDEV_RESERVE_ADDRESS
 #endif
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(_command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global __command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300s
 
@@ -34,7 +34,7 @@
         .file   "crt0_ram.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #RAMEND,sp
         ldc     #0x80,ccr
         ldc     #0x00,exr
@@ -63,13 +63,13 @@ SYMBOL_NAME_LABEL(_start)
 
         /* copy kernel commandline */
         mov.l   #COMMAND_START,er5
-        mov.l   #SYMBOL_NAME(command_line),er6
+        mov.l   #_command_line,er6
         mov.w   #512,r4
         eepmov.w
 
         /* uClinux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
@@ -124,4 +124,4 @@ __target_name:
         .asciz  "generic"
         
         .section .bootvec,"ax"
-        jmp     @SYMBOL_NAME(_start)
+        jmp     @__start
diff --git a/arch/h8300/platform/h8s/generic/crt0_rom.S b/arch/h8300/platform/h8s/generic/crt0_rom.S
index 95b6f2898f52..623ba7828193 100644
--- a/arch/h8300/platform/h8s/generic/crt0_rom.S
+++ b/arch/h8300/platform/h8s/generic/crt0_rom.S
@@ -13,17 +13,17 @@
 #include <asm/linkage.h>
 #include <asm/regs267x.h>
         
-        .global SYMBOL_NAME(_start)
-        .global SYMBOL_NAME(_command_line)
-        .global SYMBOL_NAME(_platform_gpio_table)
-        .global SYMBOL_NAME(_target_name)
+        .global __start
+        .global __command_line
+        .global __platform_gpio_table
+        .global __target_name
         
         .h8300s
         .section .text
         .file   "crt0_rom.S"
 
         /* CPU Reset entry */
-SYMBOL_NAME_LABEL(_start)
+__start:
         mov.l   #__ramend,sp
         ldc     #0x80,ccr
         ldc     #0,exr
@@ -61,7 +61,7 @@ SYMBOL_NAME_LABEL(_start)
 
         /* linux kernel start */
         ldc     #0x90,ccr       /* running kernel */
-        mov.l   #SYMBOL_NAME(init_thread_union),sp
+        mov.l   #_init_thread_union,sp
         add.l   #0x2000,sp
         jsr     @_start_kernel
 _exit:
diff --git a/arch/hexagon/include/asm/pgtable.h b/arch/hexagon/include/asm/pgtable.h
index 20d55f69fe55..d8bd54fa431e 100644
--- a/arch/hexagon/include/asm/pgtable.h
+++ b/arch/hexagon/include/asm/pgtable.h
@@ -452,10 +452,6 @@ static inline int pte_exec(pte_t pte)
 
 #define __pte_offset(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 
-/* Nothing special about IO remapping at this point */
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*  I think this is in case we have page table caches; needed by init/main.c  */
 #define pgtable_cache_init()    do { } while (0)
 
diff --git a/arch/hexagon/mm/init.c b/arch/hexagon/mm/init.c
index 2561d259a296..88977e42af0a 100644
--- a/arch/hexagon/mm/init.c
+++ b/arch/hexagon/mm/init.c
@@ -70,10 +70,8 @@ unsigned long long kmap_generation;
 void __init mem_init(void)
 {
         /*  No idea where this is actually declared.  Seems to evade LXR.  */
-        totalram_pages += free_all_bootmem();
-        num_physpages = bootmem_lastpg-ARCH_PFN_OFFSET;
-
-        printk(KERN_INFO "totalram_pages = %ld\n", totalram_pages);
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 
         /*
          *  To-Do:  someone somewhere should wipe out the bootmem map
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 1a2b7749b047..5a768ad8e893 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -376,7 +376,6 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
         depends on SMP
-        select HOTPLUG
         default n
         ---help---
           Say Y here to experiment with turning CPUs off and on.  CPUs
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index bcda5b2d121a..d43daf192b21 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -2042,7 +2042,8 @@ sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle)
 #endif
 
 static int __init
-acpi_sba_ioc_add(struct acpi_device *device)
+acpi_sba_ioc_add(struct acpi_device *device,
+                 const struct acpi_device_id *not_used)
 {
         struct ioc *ioc;
         acpi_status status;
@@ -2090,14 +2091,18 @@ static const struct acpi_device_id hp_ioc_iommu_device_ids[] = {
         {"HWP0004", 0},
         {"", 0},
 };
-static struct acpi_driver acpi_sba_ioc_driver = {
-        .name           = "IOC IOMMU Driver",
-        .ids            = hp_ioc_iommu_device_ids,
-        .ops            = {
-                .add    = acpi_sba_ioc_add,
-        },
+static struct acpi_scan_handler acpi_sba_ioc_handler = {
+        .ids    = hp_ioc_iommu_device_ids,
+        .attach = acpi_sba_ioc_add,
 };
 
+static int __init acpi_sba_ioc_init_acpi(void)
+{
+        return acpi_scan_add_handler(&acpi_sba_ioc_handler);
+}
+/* This has to run before acpi_scan_init(). */
+arch_initcall(acpi_sba_ioc_init_acpi);
+
 extern struct dma_map_ops swiotlb_dma_ops;
 
 static int __init
@@ -2122,7 +2127,10 @@ sba_init(void)
         }
 #endif
 
-        acpi_bus_register_driver(&acpi_sba_ioc_driver);
+        /*
+         * ioc_list should be populated by the acpi_sba_ioc_handler's .attach()
+         * routine, but that only happens if acpi_scan_init() has already run.
+         */
         if (!ioc_list) {
 #ifdef CONFIG_IA64_GENERIC
                 /*
diff --git a/arch/ia64/hp/sim/simscsi.c b/arch/ia64/hp/sim/simscsi.c
index 331de723c676..3a428f19a001 100644
--- a/arch/ia64/hp/sim/simscsi.c
+++ b/arch/ia64/hp/sim/simscsi.c
@@ -88,8 +88,8 @@ simscsi_setup (char *s)
         if (strlen(s) > MAX_ROOT_LEN) {
                 printk(KERN_ERR "simscsi_setup: prefix too long---using default %s\n",
                        simscsi_root);
-        }
-        simscsi_root = s;
+        } else
+                simscsi_root = s;
         return 1;
 }
 
diff --git a/arch/ia64/include/asm/irqflags.h b/arch/ia64/include/asm/irqflags.h
index 1bf2cf2f4ab4..cec6c06b52c0 100644
--- a/arch/ia64/include/asm/irqflags.h
+++ b/arch/ia64/include/asm/irqflags.h
@@ -11,6 +11,7 @@
 #define _ASM_IA64_IRQFLAGS_H
 
 #include <asm/pal.h>
+#include <asm/kregs.h>
 
 #ifdef CONFIG_IA64_DEBUG_IRQ
 extern unsigned long last_cli_ip;
diff --git a/arch/ia64/include/asm/mutex.h b/arch/ia64/include/asm/mutex.h
index bed73a643a56..f41e66d65e31 100644
--- a/arch/ia64/include/asm/mutex.h
+++ b/arch/ia64/include/asm/mutex.h
@@ -29,17 +29,15 @@ __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
  *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
  *                                 from 1 to a 0 value
  *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
  *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns.
+ * Change the count from 1 to a value lower than 1. This function returns 0
+ * if the fastpath succeeds, or -1 otherwise.
  */
 static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count)
 {
         if (unlikely(ia64_fetchadd4_acq(count, -1) != 1))
-                return fail_fn(count);
+                return -1;
         return 0;
 }
 
diff --git a/arch/ia64/include/asm/pci.h b/arch/ia64/include/asm/pci.h
index 5e04b591e423..80775f55f03f 100644
--- a/arch/ia64/include/asm/pci.h
+++ b/arch/ia64/include/asm/pci.h
@@ -89,9 +89,9 @@ extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
 #define pci_legacy_read platform_pci_legacy_read
 #define pci_legacy_write platform_pci_legacy_write
 
-struct pci_window {
-        struct resource resource;
-        u64 offset;
+struct iospace_resource {
+        struct list_head list;
+        struct resource res;
 };
 
 struct pci_controller {
@@ -100,12 +100,10 @@ struct pci_controller {
         int segment;
         int node;               /* nearest node with memory or -1 for global allocation */
 
-        unsigned int windows;
-        struct pci_window *window;
-
         void *platform_data;
 };
 
+
 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
 #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
 
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
index 815810cbbedc..7935115398a6 100644
--- a/arch/ia64/include/asm/pgtable.h
+++ b/arch/ia64/include/asm/pgtable.h
@@ -493,9 +493,6 @@ extern void paging_init (void);
 #define pte_to_pgoff(pte)               ((pte_val(pte) << 1) >> 3)
 #define pgoff_to_pte(off)               ((pte_t) { ((off) << 2) | _PAGE_FILE })
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
  * for zero-mapped memory areas etc..
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 335eb07480fe..5eb71d22c3d5 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -807,7 +807,7 @@ int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
  *  ACPI based hotplug CPU support
  */
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
-static __cpuinit
+static
 int acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
 {
 #ifdef CONFIG_ACPI_NUMA
@@ -882,7 +882,7 @@ __init void prefill_possible_map(void)
                 set_cpu_possible(i, true);
 }
 
-static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu)
+static int _acpi_map_lsapic(acpi_handle handle, int *pcpu)
 {
         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
         union acpi_object *obj;
diff --git a/arch/ia64/kernel/efi.c b/arch/ia64/kernel/efi.c
index f034563aeae5..51bce594eb83 100644
--- a/arch/ia64/kernel/efi.c
+++ b/arch/ia64/kernel/efi.c
@@ -1116,11 +1116,6 @@ efi_memmap_init(u64 *s, u64 *e)
                 if (!is_memory_available(md))
                         continue;
 
-#ifdef CONFIG_CRASH_DUMP
-                /* saved_max_pfn should ignore max_addr= command line arg */
-                if (saved_max_pfn < (efi_md_end(md) >> PAGE_SHIFT))
-                        saved_max_pfn = (efi_md_end(md) >> PAGE_SHIFT);
-#endif
                 /*
                  * Round ends inward to granule boundaries
                  * Give trimmings to uncached allocator
diff --git a/arch/ia64/kernel/err_inject.c b/arch/ia64/kernel/err_inject.c
index 2d67317a1ec2..f59c0b844e88 100644
--- a/arch/ia64/kernel/err_inject.c
+++ b/arch/ia64/kernel/err_inject.c
@@ -225,17 +225,17 @@ static struct attribute_group err_inject_attr_group = {
         .name = "err_inject"
 };
 /* Add/Remove err_inject interface for CPU device */
-static int __cpuinit err_inject_add_dev(struct device * sys_dev)
+static int err_inject_add_dev(struct device *sys_dev)
 {
         return sysfs_create_group(&sys_dev->kobj, &err_inject_attr_group);
 }
 
-static int __cpuinit err_inject_remove_dev(struct device * sys_dev)
+static int err_inject_remove_dev(struct device *sys_dev)
 {
         sysfs_remove_group(&sys_dev->kobj, &err_inject_attr_group);
         return 0;
 }
-static int __cpuinit err_inject_cpu_callback(struct notifier_block *nfb,
+static int err_inject_cpu_callback(struct notifier_block *nfb,
                 unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned long)hcpu;
@@ -256,7 +256,7 @@ static int __cpuinit err_inject_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata err_inject_cpu_notifier =
+static struct notifier_block err_inject_cpu_notifier =
 {
         .notifier_call = err_inject_cpu_callback,
 };
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index 9be4e497f3d3..991ca336b8a2 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -1035,7 +1035,7 @@ END(ia64_delay_loop)
  * Return a CPU-local timestamp in nano-seconds.  This timestamp is
  * NOT synchronized across CPUs its return value must never be
  * compared against the values returned on another CPU.  The usage in
- * kernel/sched.c ensures that.
+ * kernel/sched/core.c ensures that.
  *
  * The return-value of sched_clock() is NOT supposed to wrap-around.
  * If it did, it would cause some scheduling hiccups (at the worst).
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index d7396dbb07bb..b8edfa75a83f 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -631,7 +631,7 @@ ia64_mca_register_cpev (int cpev)
  * Outputs
  *      None
  */
-void __cpuinit
+void
 ia64_mca_cmc_vector_setup (void)
 {
         cmcv_reg_t      cmcv;
@@ -1814,7 +1814,7 @@ static struct irqaction mca_cpep_irqaction = {
  * format most of the fields.
  */
 
-static void __cpuinit
+static void
 format_mca_init_stack(void *mca_data, unsigned long offset,
                 const char *type, int cpu)
 {
@@ -1844,7 +1844,7 @@ static void * __init_refok mca_bootmem(void)
 }
 
 /* Do per-CPU MCA-related initialization.  */
-void __cpuinit
+void
 ia64_mca_cpu_init(void *cpu_data)
 {
         void *pal_vaddr;
@@ -1896,7 +1896,7 @@ ia64_mca_cpu_init(void *cpu_data)
                                                               PAGE_KERNEL));
 }
 
-static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
+static void ia64_mca_cmc_vector_adjust(void *dummy)
 {
         unsigned long flags;
 
@@ -1906,7 +1906,7 @@ static void __cpuinit ia64_mca_cmc_vector_adjust(void *dummy)
         local_irq_restore(flags);
 }
 
-static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
+static int mca_cpu_callback(struct notifier_block *nfb,
                                       unsigned long action,
                                       void *hcpu)
 {
@@ -1922,7 +1922,7 @@ static int __cpuinit mca_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block mca_cpu_notifier __cpuinitdata = {
+static struct notifier_block mca_cpu_notifier = {
         .notifier_call = mca_cpu_callback
 };
 
diff --git a/arch/ia64/kernel/numa.c b/arch/ia64/kernel/numa.c
index c93420c97409..d288cde93606 100644
--- a/arch/ia64/kernel/numa.c
+++ b/arch/ia64/kernel/numa.c
@@ -30,7 +30,7 @@ EXPORT_SYMBOL(cpu_to_node_map);
 cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
 EXPORT_SYMBOL(node_to_cpu_mask);
 
-void __cpuinit map_cpu_to_node(int cpu, int nid)
+void map_cpu_to_node(int cpu, int nid)
 {
         int oldnid;
         if (nid < 0) { /* just initialize by zero */
@@ -51,7 +51,7 @@ void __cpuinit map_cpu_to_node(int cpu, int nid)
         return;
 }
 
-void __cpuinit unmap_cpu_from_node(int cpu, int nid)
+void unmap_cpu_from_node(int cpu, int nid)
 {
         WARN_ON(!cpu_isset(cpu, node_to_cpu_mask[nid]));
         WARN_ON(cpu_to_node_map[cpu] != nid);
diff --git a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c
index 2b3c2d79256f..ab333284f4b2 100644
--- a/arch/ia64/kernel/palinfo.c
+++ b/arch/ia64/kernel/palinfo.c
@@ -932,7 +932,7 @@ static const struct file_operations proc_palinfo_fops = {
         .release        = single_release,
 };
 
-static void __cpuinit
+static void
 create_palinfo_proc_entries(unsigned int cpu)
 {
         pal_func_cpu_u_t f;
@@ -962,7 +962,7 @@ remove_palinfo_proc_entries(unsigned int hcpu)
         remove_proc_subtree(cpustr, palinfo_dir);
 }
 
-static int __cpuinit palinfo_cpu_callback(struct notifier_block *nfb,
+static int palinfo_cpu_callback(struct notifier_block *nfb,
                                         unsigned long action, void *hcpu)
 {
         unsigned int hotcpu = (unsigned long)hcpu;
diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c
index 1ddcfe5ef353..992c1098c522 100644
--- a/arch/ia64/kernel/pci-dma.c
+++ b/arch/ia64/kernel/pci-dma.c
@@ -33,15 +33,6 @@ int force_iommu __read_mostly;
 
 int iommu_pass_through;
 
-/* Dummy device used for NULL arguments (normally ISA). Better would
-   be probably a smaller DMA mask, but this is bug-to-bug compatible
-   to i386. */
-struct device fallback_dev = {
-        .init_name = "fallback device",
-        .coherent_dma_mask = DMA_BIT_MASK(32),
-        .dma_mask = &fallback_dev.coherent_dma_mask,
-};
-
 extern struct dma_map_ops intel_dma_ops;
 
 static int __init pci_iommu_init(void)
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 9ea25fce06d5..5a9ff1c3c3e9 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -5647,24 +5647,8 @@ pfm_proc_show_header(struct seq_file *m)
 
         list_for_each(pos, &pfm_buffer_fmt_list) {
                 entry = list_entry(pos, pfm_buffer_fmt_t, fmt_list);
-                seq_printf(m, "format                    : %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x %s\n",
-                        entry->fmt_uuid[0],
-                        entry->fmt_uuid[1],
-                        entry->fmt_uuid[2],
-                        entry->fmt_uuid[3],
-                        entry->fmt_uuid[4],
-                        entry->fmt_uuid[5],
-                        entry->fmt_uuid[6],
-                        entry->fmt_uuid[7],
-                        entry->fmt_uuid[8],
-                        entry->fmt_uuid[9],
-                        entry->fmt_uuid[10],
-                        entry->fmt_uuid[11],
-                        entry->fmt_uuid[12],
-                        entry->fmt_uuid[13],
-                        entry->fmt_uuid[14],
-                        entry->fmt_uuid[15],
-                        entry->fmt_name);
+                seq_printf(m, "format                    : %16phD %s\n",
+                           entry->fmt_uuid, entry->fmt_name);
         }
         spin_unlock(&pfm_buffer_fmt_lock);
 
diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c
index 4bc580af67b3..960a396f5929 100644
--- a/arch/ia64/kernel/salinfo.c
+++ b/arch/ia64/kernel/salinfo.c
@@ -568,7 +568,7 @@ static const struct file_operations salinfo_data_fops = {
         .llseek  = default_llseek,
 };
 
-static int __cpuinit
+static int
 salinfo_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu)
 {
         unsigned int i, cpu = (unsigned long)hcpu;
@@ -609,7 +609,7 @@ salinfo_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu
         return NOTIFY_OK;
 }
 
-static struct notifier_block salinfo_cpu_notifier __cpuinitdata =
+static struct notifier_block salinfo_cpu_notifier =
 {
         .notifier_call = salinfo_cpu_callback,
         .priority = 0,
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index 13bfdd22afc8..4fc2e9569bb2 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -748,7 +748,7 @@ const struct seq_operations cpuinfo_op = {
 #define MAX_BRANDS      8
 static char brandname[MAX_BRANDS][128];
 
-static char * __cpuinit
+static char *
 get_model_name(__u8 family, __u8 model)
 {
         static int overflow;
@@ -778,7 +778,7 @@ get_model_name(__u8 family, __u8 model)
         return "Unknown";
 }
 
-static void __cpuinit
+static void
 identify_cpu (struct cpuinfo_ia64 *c)
 {
         union {
@@ -850,7 +850,7 @@ identify_cpu (struct cpuinfo_ia64 *c)
  * 2. the minimum of the i-cache stride sizes for "flush_icache_range()".
  * 3. the minimum of the cache stride sizes for "clflush_cache_range()".
  */
-static void __cpuinit
+static void
 get_cache_info(void)
 {
         unsigned long line_size, max = 1;
@@ -915,10 +915,10 @@ get_cache_info(void)
  * cpu_init() initializes state that is per-CPU.  This function acts
  * as a 'CPU state barrier', nothing should get across.
  */
-void __cpuinit
+void
 cpu_init (void)
 {
-        extern void __cpuinit ia64_mmu_init (void *);
+        extern void ia64_mmu_init(void *);
         static unsigned long max_num_phys_stacked = IA64_NUM_PHYS_STACK_REG;
         unsigned long num_phys_stacked;
         pal_vm_info_2_u_t vmi;
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 8d87168d218d..547a48d78bd7 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -351,7 +351,7 @@ static inline void smp_setup_percpu_timer(void)
 {
 }
 
-static void __cpuinit
+static void
 smp_callin (void)
 {
         int cpuid, phys_id, itc_master;
@@ -442,7 +442,7 @@ smp_callin (void)
 /*
  * Activate a secondary processor.  head.S calls this.
  */
-int __cpuinit
+int
 start_secondary (void *unused)
 {
         /* Early console may use I/O ports */
@@ -459,7 +459,7 @@ start_secondary (void *unused)
         return 0;
 }
 
-static int __cpuinit
+static int
 do_boot_cpu (int sapicid, int cpu, struct task_struct *idle)
 {
         int timeout;
@@ -728,7 +728,7 @@ static inline void set_cpu_sibling_map(int cpu)
         }
 }
 
-int __cpuinit
+int
 __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
         int ret;
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index dc00b2c1b42a..ca69a5a96dcc 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -135,11 +135,11 @@ struct cpu_cache_info {
         struct kobject kobj;
 };
 
-static struct cpu_cache_info    all_cpu_cache_info[NR_CPUS] __cpuinitdata;
+static struct cpu_cache_info    all_cpu_cache_info[NR_CPUS];
 #define LEAF_KOBJECT_PTR(x,y)    (&all_cpu_cache_info[x].cache_leaves[y])
 
 #ifdef CONFIG_SMP
-static void __cpuinit cache_shared_cpu_map_setup( unsigned int cpu,
+static void cache_shared_cpu_map_setup(unsigned int cpu,
                 struct cache_info * this_leaf)
 {
         pal_cache_shared_info_t csi;
@@ -174,7 +174,7 @@ static void __cpuinit cache_shared_cpu_map_setup( unsigned int cpu,
                                 &csi) == PAL_STATUS_SUCCESS);
 }
 #else
-static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu,
+static void cache_shared_cpu_map_setup(unsigned int cpu,
                 struct cache_info * this_leaf)
 {
         cpu_set(cpu, this_leaf->shared_cpu_map);
@@ -298,7 +298,7 @@ static struct kobj_type cache_ktype_percpu_entry = {
         .sysfs_ops      = &cache_sysfs_ops,
 };
 
-static void __cpuinit cpu_cache_sysfs_exit(unsigned int cpu)
+static void cpu_cache_sysfs_exit(unsigned int cpu)
 {
         kfree(all_cpu_cache_info[cpu].cache_leaves);
         all_cpu_cache_info[cpu].cache_leaves = NULL;
@@ -307,7 +307,7 @@ static void __cpuinit cpu_cache_sysfs_exit(unsigned int cpu)
         return;
 }
 
-static int __cpuinit cpu_cache_sysfs_init(unsigned int cpu)
+static int cpu_cache_sysfs_init(unsigned int cpu)
 {
         unsigned long i, levels, unique_caches;
         pal_cache_config_info_t cci;
@@ -351,7 +351,7 @@ static int __cpuinit cpu_cache_sysfs_init(unsigned int cpu)
 }
 
 /* Add cache interface for CPU device */
-static int __cpuinit cache_add_dev(struct device * sys_dev)
+static int cache_add_dev(struct device *sys_dev)
 {
         unsigned int cpu = sys_dev->id;
         unsigned long i, j;
@@ -401,7 +401,7 @@ static int __cpuinit cache_add_dev(struct device * sys_dev)
 }
 
 /* Remove cache interface for CPU device */
-static int __cpuinit cache_remove_dev(struct device * sys_dev)
+static int cache_remove_dev(struct device *sys_dev)
 {
         unsigned int cpu = sys_dev->id;
         unsigned long i;
@@ -425,7 +425,7 @@ static int __cpuinit cache_remove_dev(struct device * sys_dev)
  * When a cpu is hot-plugged, do a check and initiate
  * cache kobject if necessary
  */
-static int __cpuinit cache_cpu_callback(struct notifier_block *nfb,
+static int cache_cpu_callback(struct notifier_block *nfb,
                 unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned long)hcpu;
@@ -445,7 +445,7 @@ static int __cpuinit cache_cpu_callback(struct notifier_block *nfb,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata cache_cpu_notifier =
+static struct notifier_block cache_cpu_notifier =
 {
         .notifier_call = cache_cpu_callback
 };
diff --git a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c
index f7f9f9c6caf0..d3636e67a98e 100644
--- a/arch/ia64/kernel/traps.c
+++ b/arch/ia64/kernel/traps.c
@@ -630,7 +630,7 @@ ia64_fault (unsigned long vector, unsigned long isr, unsigned long ifa,
                 printk(KERN_ERR "  iip - 0x%lx, ifa - 0x%lx, isr - 0x%lx\n",
                        iip, ifa, isr);
                 force_sig(SIGSEGV, current);
-                break;
+                return;
 
               case 46:
                 printk(KERN_ERR "Unexpected IA-32 intercept trap (Trap 46)\n");
diff --git a/arch/ia64/kvm/Makefile b/arch/ia64/kvm/Makefile
index 1a4053789d01..18e45ec49bbf 100644
--- a/arch/ia64/kvm/Makefile
+++ b/arch/ia64/kvm/Makefile
@@ -47,12 +47,13 @@ FORCE : $(obj)/$(offsets-file)
 
 ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
 asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
+KVM := ../../../virt/kvm
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-                coalesced_mmio.o irq_comm.o)
+common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+                $(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
 
 ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
-common-objs += $(addprefix ../../../virt/kvm/, assigned-dev.o iommu.o)
+common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
 endif
 
 kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index 67c59ebec899..da5237d636d6 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -156,8 +156,7 @@ static void *cpu_data;
  *
  * Allocate and setup per-cpu data areas.
  */
-void * __cpuinit
-per_cpu_init (void)
+void *per_cpu_init(void)
 {
         static bool first_time = true;
         void *cpu0_data = __cpu0_per_cpu;
@@ -295,14 +294,6 @@ find_memory (void)
         alloc_per_cpu_data();
 }
 
-static int count_pages(u64 start, u64 end, void *arg)
-{
-        unsigned long *count = arg;
-
-        *count += (end - start) >> PAGE_SHIFT;
-        return 0;
-}
-
 /*
  * Set up the page tables.
  */
@@ -313,9 +304,6 @@ paging_init (void)
         unsigned long max_dma;
         unsigned long max_zone_pfns[MAX_NR_ZONES];
 
-        num_physpages = 0;
-        efi_memmap_walk(count_pages, &num_physpages);
-
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
 #ifdef CONFIG_ZONE_DMA
         max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index ae4db4bd6d97..2de08f4d9930 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -37,7 +37,6 @@ struct early_node_data {
         struct ia64_node_data *node_data;
         unsigned long pernode_addr;
         unsigned long pernode_size;
-        unsigned long num_physpages;
 #ifdef CONFIG_ZONE_DMA
         unsigned long num_dma_physpages;
 #endif
@@ -593,7 +592,7 @@ void __init find_memory(void)
  * find_pernode_space() does most of this already, we just need to set
  * local_per_cpu_offset
  */
-void __cpuinit *per_cpu_init(void)
+void *per_cpu_init(void)
 {
         int cpu;
         static int first_time = 1;
@@ -732,7 +731,6 @@ static __init int count_node_pages(unsigned long start, unsigned long len, int n
 {
         unsigned long end = start + len;
 
-        mem_data[node].num_physpages += len >> PAGE_SHIFT;
 #ifdef CONFIG_ZONE_DMA
         if (start <= __pa(MAX_DMA_ADDRESS))
                 mem_data[node].num_dma_physpages +=
@@ -778,7 +776,6 @@ void __init paging_init(void)
 #endif
 
         for_each_online_node(node) {
-                num_physpages += mem_data[node].num_physpages;
                 pfn_offset = mem_data[node].min_pfn;
 
 #ifdef CONFIG_VIRTUAL_MEM_MAP
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index d1fe4b402601..b6f7f43424ec 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -154,9 +154,8 @@ ia64_init_addr_space (void)
 void
 free_initmem (void)
 {
-        free_reserved_area((unsigned long)ia64_imva(__init_begin),
-                           (unsigned long)ia64_imva(__init_end),
-                           0, "unused kernel");
+        free_reserved_area(ia64_imva(__init_begin), ia64_imva(__init_end),
+                           -1, "unused kernel");
 }
 
 void __init
@@ -546,19 +545,6 @@ int __init register_active_ranges(u64 start, u64 len, int nid)
         return 0;
 }
 
-static int __init
-count_reserved_pages(u64 start, u64 end, void *arg)
-{
-        unsigned long num_reserved = 0;
-        unsigned long *count = arg;
-
-        for (; start < end; start += PAGE_SIZE)
-                if (PageReserved(virt_to_page(start)))
-                        ++num_reserved;
-        *count += num_reserved;
-        return 0;
-}
-
 int
 find_max_min_low_pfn (u64 start, u64 end, void *arg)
 {
@@ -597,8 +583,6 @@ __setup("nolwsys", nolwsys_setup);
 void __init
 mem_init (void)
 {
-        long reserved_pages, codesize, datasize, initsize;
-        pg_data_t *pgdat;
         int i;
 
         BUG_ON(PTRS_PER_PGD * sizeof(pgd_t) != PAGE_SIZE);
@@ -616,27 +600,12 @@ mem_init (void)
 
 #ifdef CONFIG_FLATMEM
         BUG_ON(!mem_map);
-        max_mapnr = max_low_pfn;
 #endif
 
+        set_max_mapnr(max_low_pfn);
         high_memory = __va(max_low_pfn * PAGE_SIZE);
-
-        for_each_online_pgdat(pgdat)
-                if (pgdat->bdata->node_bootmem_map)
-                        totalram_pages += free_all_bootmem_node(pgdat);
-
-        reserved_pages = 0;
-        efi_memmap_walk(count_reserved_pages, &reserved_pages);
-
-        codesize =  (unsigned long) _etext - (unsigned long) _stext;
-        datasize =  (unsigned long) _edata - (unsigned long) _etext;
-        initsize =  (unsigned long) __init_end - (unsigned long) __init_begin;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%luk code, %luk reserved, "
-               "%luk data, %luk init)\n", nr_free_pages() << (PAGE_SHIFT - 10),
-               num_physpages << (PAGE_SHIFT - 10), codesize >> 10,
-               reserved_pages << (PAGE_SHIFT - 10), datasize >> 10, initsize >> 10);
-
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 
         /*
          * For fsyscall entrpoints with no light-weight handler, use the ordinary
diff --git a/arch/ia64/mm/numa.c b/arch/ia64/mm/numa.c
index 4248492b9321..ea21d4cad540 100644
--- a/arch/ia64/mm/numa.c
+++ b/arch/ia64/mm/numa.c
@@ -86,7 +86,7 @@ int __meminit __early_pfn_to_nid(unsigned long pfn)
         return -1;
 }
 
-void __cpuinit numa_clear_node(int cpu)
+void numa_clear_node(int cpu)
 {
         unmap_cpu_from_node(cpu, NUMA_NO_NODE);
 }
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index de1474ff0bc5..2326790b7d8b 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -134,6 +134,10 @@ struct pci_root_info {
         struct acpi_device *bridge;
         struct pci_controller *controller;
         struct list_head resources;
+        struct resource *res;
+        resource_size_t *res_offset;
+        unsigned int res_num;
+        struct list_head io_resources;
         char *name;
 };
 
@@ -153,7 +157,7 @@ new_space (u64 phys_base, int sparse)
                         return i;
 
         if (num_io_spaces == MAX_IO_SPACES) {
-                printk(KERN_ERR "PCI: Too many IO port spaces "
+                pr_err("PCI: Too many IO port spaces "
                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
                 return ~0;
         }
@@ -168,25 +172,22 @@ new_space (u64 phys_base, int sparse)
 static u64 add_io_space(struct pci_root_info *info,
                         struct acpi_resource_address64 *addr)
 {
+        struct iospace_resource *iospace;
         struct resource *resource;
         char *name;
         unsigned long base, min, max, base_port;
         unsigned int sparse = 0, space_nr, len;
 
-        resource = kzalloc(sizeof(*resource), GFP_KERNEL);
-        if (!resource) {
-                printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
-                        info->name);
+        len = strlen(info->name) + 32;
+        iospace = kzalloc(sizeof(*iospace) + len, GFP_KERNEL);
+        if (!iospace) {
+                dev_err(&info->bridge->dev,
+                                "PCI: No memory for %s I/O port space\n",
+                                info->name);
                 goto out;
         }
 
-        len = strlen(info->name) + 32;
-        name = kzalloc(len, GFP_KERNEL);
-        if (!name) {
-                printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
-                        info->name);
-                goto free_resource;
-        }
+        name = (char *)(iospace + 1);
 
         min = addr->minimum;
         max = min + addr->address_length - 1;
@@ -195,7 +196,7 @@ static u64 add_io_space(struct pci_root_info *info,
 
         space_nr = new_space(addr->translation_offset, sparse);
         if (space_nr == ~0)
-                goto free_name;
+                goto free_resource;
 
         base = __pa(io_space[space_nr].mmio_base);
         base_port = IO_SPACE_BASE(space_nr);
@@ -210,18 +211,23 @@ static u64 add_io_space(struct pci_root_info *info,
         if (space_nr == 0)
                 sparse = 1;
 
+        resource = &iospace->res;
         resource->name  = name;
         resource->flags = IORESOURCE_MEM;
         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
-        insert_resource(&iomem_resource, resource);
+        if (insert_resource(&iomem_resource, resource)) {
+                dev_err(&info->bridge->dev,
+                                "can't allocate host bridge io space resource  %pR\n",
+                                resource);
+                goto free_resource;
+        }
 
+        list_add_tail(&iospace->list, &info->io_resources);
         return base_port;
 
-free_name:
-        kfree(name);
 free_resource:
-        kfree(resource);
+        kfree(iospace);
 out:
         return ~0;
 }
@@ -265,7 +271,7 @@ static acpi_status count_window(struct acpi_resource *resource, void *data)
 static acpi_status add_window(struct acpi_resource *res, void *data)
 {
         struct pci_root_info *info = data;
-        struct pci_window *window;
+        struct resource *resource;
         struct acpi_resource_address64 addr;
         acpi_status status;
         unsigned long flags, offset = 0;
@@ -289,55 +295,146 @@ static acpi_status add_window(struct acpi_resource *res, void *data)
         } else
                 return AE_OK;
 
-        window = &info->controller->window[info->controller->windows++];
-        window->resource.name = info->name;
-        window->resource.flags = flags;
-        window->resource.start = addr.minimum + offset;
-        window->resource.end = window->resource.start + addr.address_length - 1;
-        window->offset = offset;
+        resource = &info->res[info->res_num];
+        resource->name = info->name;
+        resource->flags = flags;
+        resource->start = addr.minimum + offset;
+        resource->end = resource->start + addr.address_length - 1;
+        info->res_offset[info->res_num] = offset;
 
-        if (insert_resource(root, &window->resource)) {
+        if (insert_resource(root, resource)) {
                 dev_err(&info->bridge->dev,
                         "can't allocate host bridge window %pR\n",
-                        &window->resource);
+                        resource);
         } else {
                 if (offset)
                         dev_info(&info->bridge->dev, "host bridge window %pR "
                                  "(PCI address [%#llx-%#llx])\n",
-                                 &window->resource,
-                                 window->resource.start - offset,
-                                 window->resource.end - offset);
+                                 resource,
+                                 resource->start - offset,
+                                 resource->end - offset);
                 else
                         dev_info(&info->bridge->dev,
-                                 "host bridge window %pR\n",
-                                 &window->resource);
+                                 "host bridge window %pR\n", resource);
         }
-
         /* HP's firmware has a hack to work around a Windows bug.
          * Ignore these tiny memory ranges */
-        if (!((window->resource.flags & IORESOURCE_MEM) &&
-              (window->resource.end - window->resource.start < 16)))
-                pci_add_resource_offset(&info->resources, &window->resource,
-                                        window->offset);
+        if (!((resource->flags & IORESOURCE_MEM) &&
+              (resource->end - resource->start < 16)))
+                pci_add_resource_offset(&info->resources, resource,
+                                        info->res_offset[info->res_num]);
 
+        info->res_num++;
         return AE_OK;
 }
 
+static void free_pci_root_info_res(struct pci_root_info *info)
+{
+        struct iospace_resource *iospace, *tmp;
+
+        list_for_each_entry_safe(iospace, tmp, &info->io_resources, list)
+                kfree(iospace);
+
+        kfree(info->name);
+        kfree(info->res);
+        info->res = NULL;
+        kfree(info->res_offset);
+        info->res_offset = NULL;
+        info->res_num = 0;
+        kfree(info->controller);
+        info->controller = NULL;
+}
+
+static void __release_pci_root_info(struct pci_root_info *info)
+{
+        int i;
+        struct resource *res;
+        struct iospace_resource *iospace;
+
+        list_for_each_entry(iospace, &info->io_resources, list)
+                release_resource(&iospace->res);
+
+        for (i = 0; i < info->res_num; i++) {
+                res = &info->res[i];
+
+                if (!res->parent)
+                        continue;
+
+                if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
+                        continue;
+
+                release_resource(res);
+        }
+
+        free_pci_root_info_res(info);
+        kfree(info);
+}
+
+static void release_pci_root_info(struct pci_host_bridge *bridge)
+{
+        struct pci_root_info *info = bridge->release_data;
+
+        __release_pci_root_info(info);
+}
+
+static int
+probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
+                int busnum, int domain)
+{
+        char *name;
+
+        name = kmalloc(16, GFP_KERNEL);
+        if (!name)
+                return -ENOMEM;
+
+        sprintf(name, "PCI Bus %04x:%02x", domain, busnum);
+        info->bridge = device;
+        info->name = name;
+
+        acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
+                        &info->res_num);
+        if (info->res_num) {
+                info->res =
+                        kzalloc_node(sizeof(*info->res) * info->res_num,
+                                     GFP_KERNEL, info->controller->node);
+                if (!info->res) {
+                        kfree(name);
+                        return -ENOMEM;
+                }
+
+                info->res_offset =
+                        kzalloc_node(sizeof(*info->res_offset) * info->res_num,
+                                        GFP_KERNEL, info->controller->node);
+                if (!info->res_offset) {
+                        kfree(name);
+                        kfree(info->res);
+                        info->res = NULL;
+                        return -ENOMEM;
+                }
+
+                info->res_num = 0;
+                acpi_walk_resources(device->handle, METHOD_NAME__CRS,
+                        add_window, info);
+        } else
+                kfree(name);
+
+        return 0;
+}
+
 struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 {
         struct acpi_device *device = root->device;
         int domain = root->segment;
         int bus = root->secondary.start;
         struct pci_controller *controller;
-        unsigned int windows = 0;
-        struct pci_root_info info;
+        struct pci_root_info *info = NULL;
+        int busnum = root->secondary.start;
         struct pci_bus *pbus;
-        char *name;
-        int pxm;
+        int pxm, ret;
 
         controller = alloc_pci_controller(domain);
         if (!controller)
-                goto out1;
+                return NULL;
 
         controller->acpi_handle = device->handle;
 
@@ -347,29 +444,27 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
                 controller->node = pxm_to_node(pxm);
 #endif
 
-        INIT_LIST_HEAD(&info.resources);
-        /* insert busn resource at first */
-        pci_add_resource(&info.resources, &root->secondary);
-        acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
-                        &windows);
-        if (windows) {
-                controller->window =
-                        kzalloc_node(sizeof(*controller->window) * windows,
-                                     GFP_KERNEL, controller->node);
-                if (!controller->window)
-                        goto out2;
-
-                name = kmalloc(16, GFP_KERNEL);
-                if (!name)
-                        goto out3;
-
-                sprintf(name, "PCI Bus %04x:%02x", domain, bus);
-                info.bridge = device;
-                info.controller = controller;
-                info.name = name;
-                acpi_walk_resources(device->handle, METHOD_NAME__CRS,
-                        add_window, &info);
+        info = kzalloc(sizeof(*info), GFP_KERNEL);
+        if (!info) {
+                dev_err(&device->dev,
+                                "pci_bus %04x:%02x: ignored (out of memory)\n",
+                                domain, busnum);
+                kfree(controller);
+                return NULL;
         }
+
+        info->controller = controller;
+        INIT_LIST_HEAD(&info->io_resources);
+        INIT_LIST_HEAD(&info->resources);
+
+        ret = probe_pci_root_info(info, device, busnum, domain);
+        if (ret) {
+                kfree(info->controller);
+                kfree(info);
+                return NULL;
+        }
+        /* insert busn resource at first */
+        pci_add_resource(&info->resources, &root->secondary);
         /*
          * See arch/x86/pci/acpi.c.
          * The desired pci bus might already be scanned in a quirk. We
@@ -377,21 +472,17 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
          * such quirk. So we just ignore the case now.
          */
         pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
-                                   &info.resources);
+                                   &info->resources);
         if (!pbus) {
-                pci_free_resource_list(&info.resources);
+                pci_free_resource_list(&info->resources);
+                __release_pci_root_info(info);
                 return NULL;
         }
 
+        pci_set_host_bridge_release(to_pci_host_bridge(pbus->bridge),
+                        release_pci_root_info, info);
         pci_scan_child_bus(pbus);
         return pbus;
-
-out3:
-        kfree(controller->window);
-out2:
-        kfree(controller);
-out1:
-        return NULL;
 }
 
 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
@@ -691,7 +782,7 @@ static void __init set_pci_dfl_cacheline_size(void)
 
         status = ia64_pal_cache_summary(&levels, &unique_caches);
         if (status != 0) {
-                printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
+                pr_err("%s: ia64_pal_cache_summary() failed "
                         "(status=%ld)\n", __func__, status);
                 return;
         }
@@ -699,7 +790,7 @@ static void __init set_pci_dfl_cacheline_size(void)
         status = ia64_pal_cache_config_info(levels - 1,
                                 /* cache_type (data_or_unified)= */ 2, &cci);
         if (status != 0) {
-                printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
+                pr_err("%s: ia64_pal_cache_config_info() failed "
                         "(status=%ld)\n", __func__, status);
                 return;
         }
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 238e2c511d94..0b5ce82d203d 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -118,76 +118,26 @@ static void __init sn_fixup_ionodes(void)
 }
 
 /*
- * sn_pci_legacy_window_fixup - Create PCI controller windows for
+ * sn_pci_legacy_window_fixup - Setup PCI resources for
  *                              legacy IO and MEM space. This needs to
  *                              be done here, as the PROM does not have
  *                              ACPI support defining the root buses
  *                              and their resources (_CRS),
  */
 static void
-sn_legacy_pci_window_fixup(struct pci_controller *controller,
-                           u64 legacy_io, u64 legacy_mem)
+sn_legacy_pci_window_fixup(struct resource *res,
+                u64 legacy_io, u64 legacy_mem)
 {
-                controller->window = kcalloc(2, sizeof(struct pci_window),
-                                             GFP_KERNEL);
-                BUG_ON(controller->window == NULL);
-                controller->window[0].offset = legacy_io;
-                controller->window[0].resource.name = "legacy_io";
-                controller->window[0].resource.flags = IORESOURCE_IO;
-                controller->window[0].resource.start = legacy_io;
-                controller->window[0].resource.end =
-                                controller->window[0].resource.start + 0xffff;
-                controller->window[0].resource.parent = &ioport_resource;
-                controller->window[1].offset = legacy_mem;
-                controller->window[1].resource.name = "legacy_mem";
-                controller->window[1].resource.flags = IORESOURCE_MEM;
-                controller->window[1].resource.start = legacy_mem;
-                controller->window[1].resource.end =
-                       controller->window[1].resource.start + (1024 * 1024) - 1;
-                controller->window[1].resource.parent = &iomem_resource;
-                controller->windows = 2;
-}
-
-/*
- * sn_pci_window_fixup() - Create a pci_window for each device resource.
- *                         It will setup pci_windows for use by
- *                         pcibios_bus_to_resource(), pcibios_resource_to_bus(),
- *                         etc.
- */
-static void
-sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
-                    s64 * pci_addrs)
-{
-        struct pci_controller *controller = PCI_CONTROLLER(dev->bus);
-        unsigned int i;
-        unsigned int idx;
-        unsigned int new_count;
-        struct pci_window *new_window;
-
-        if (count == 0)
-                return;
-        idx = controller->windows;
-        new_count = controller->windows + count;
-        new_window = kcalloc(new_count, sizeof(struct pci_window), GFP_KERNEL);
-        BUG_ON(new_window == NULL);
-        if (controller->window) {
-                memcpy(new_window, controller->window,
-                       sizeof(struct pci_window) * controller->windows);
-                kfree(controller->window);
-        }
-
-        /* Setup a pci_window for each device resource. */
-        for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
-                if (pci_addrs[i] == -1)
-                        continue;
-
-                new_window[idx].offset = dev->resource[i].start - pci_addrs[i];
-                new_window[idx].resource = dev->resource[i];
-                idx++;
-        }
-
-        controller->windows = new_count;
-        controller->window = new_window;
+                res[0].name = "legacy_io";
+                res[0].flags = IORESOURCE_IO;
+                res[0].start = legacy_io;
+                res[0].end = res[0].start + 0xffff;
+                res[0].parent = &ioport_resource;
+                res[1].name = "legacy_mem";
+                res[1].flags = IORESOURCE_MEM;
+                res[1].start = legacy_mem;
+                res[1].end = res[1].start + (1024 * 1024) - 1;
+                res[1].parent = &iomem_resource;
 }
 
 /*
@@ -199,9 +149,7 @@ sn_pci_window_fixup(struct pci_dev *dev, unsigned int count,
 void
 sn_io_slot_fixup(struct pci_dev *dev)
 {
-        unsigned int count = 0;
         int idx;
-        s64 pci_addrs[PCI_ROM_RESOURCE + 1];
         unsigned long addr, end, size, start;
         struct pcidev_info *pcidev_info;
         struct sn_irq_info *sn_irq_info;
@@ -229,7 +177,6 @@ sn_io_slot_fixup(struct pci_dev *dev)
         for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
 
                 if (!pcidev_info->pdi_pio_mapped_addr[idx]) {
-                        pci_addrs[idx] = -1;
                         continue;
                 }
 
@@ -237,11 +184,8 @@ sn_io_slot_fixup(struct pci_dev *dev)
                 end = dev->resource[idx].end;
                 size = end - start;
                 if (size == 0) {
-                        pci_addrs[idx] = -1;
                         continue;
                 }
-                pci_addrs[idx] = start;
-                count++;
                 addr = pcidev_info->pdi_pio_mapped_addr[idx];
                 addr = ((addr << 4) >> 4) | __IA64_UNCACHED_OFFSET;
                 dev->resource[idx].start = addr;
@@ -276,11 +220,6 @@ sn_io_slot_fixup(struct pci_dev *dev)
                                                  IORESOURCE_ROM_BIOS_COPY;
                 }
         }
-        /* Create a pci_window in the pci_controller struct for
-         * each device resource.
-         */
-        if (count > 0)
-                sn_pci_window_fixup(dev, count, pci_addrs);
 
         sn_pci_fixup_slot(dev, pcidev_info, sn_irq_info);
 }
@@ -297,8 +236,8 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
         s64 status = 0;
         struct pci_controller *controller;
         struct pcibus_bussoft *prom_bussoft_ptr;
+        struct resource *res;
         LIST_HEAD(resources);
-        int i;
 
         status = sal_get_pcibus_info((u64) segment, (u64) busnum,
                                      (u64) ia64_tpa(&prom_bussoft_ptr));
@@ -310,32 +249,29 @@ sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
         BUG_ON(!controller);
         controller->segment = segment;
 
+        res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+        BUG_ON(!res);
+
         /*
          * Temporarily save the prom_bussoft_ptr for use by sn_bus_fixup().
          * (platform_data will be overwritten later in sn_common_bus_fixup())
          */
         controller->platform_data = prom_bussoft_ptr;
 
-        sn_legacy_pci_window_fixup(controller,
-                                   prom_bussoft_ptr->bs_legacy_io,
-                                   prom_bussoft_ptr->bs_legacy_mem);
-        for (i = 0; i < controller->windows; i++)
-                pci_add_resource_offset(&resources,
-                                        &controller->window[i].resource,
-                                        controller->window[i].offset);
+        sn_legacy_pci_window_fixup(res,
+                        prom_bussoft_ptr->bs_legacy_io,
+                        prom_bussoft_ptr->bs_legacy_mem);
+        pci_add_resource_offset(&resources,     &res[0],
+                        prom_bussoft_ptr->bs_legacy_io);
+        pci_add_resource_offset(&resources,     &res[1],
+                        prom_bussoft_ptr->bs_legacy_mem);
+
         bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, controller,
                                 &resources);
-        if (bus == NULL)
-                goto error_return; /* error, or bus already scanned */
-
-        bus->sysdata = controller;
-
-        return;
-
-error_return:
-
-        kfree(controller);
-        return;
+        if (bus == NULL) {
+                kfree(res);
+                kfree(controller);
+        }
 }
 
 /*
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index f82e7b462b7b..53b01b8e2f19 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -192,7 +192,7 @@ void __init early_sn_setup(void)
 }
 
 extern int platform_intr_list[];
-static int __cpuinitdata shub_1_1_found;
+static int shub_1_1_found;
 
 /*
  * sn_check_for_wars
@@ -200,7 +200,7 @@ static int __cpuinitdata shub_1_1_found;
  * Set flag for enabling shub specific wars
  */
 
-static inline int __cpuinit is_shub_1_1(int nasid)
+static inline int is_shub_1_1(int nasid)
 {
         unsigned long id;
         int rev;
@@ -212,7 +212,7 @@ static inline int __cpuinit is_shub_1_1(int nasid)
         return rev <= 2;
 }
 
-static void __cpuinit sn_check_for_wars(void)
+static void sn_check_for_wars(void)
 {
         int cnode;
 
@@ -558,7 +558,7 @@ static void __init sn_init_pdas(char **cmdline_p)
  * Also sets up a few fields in the nodepda.  Also known as
  * platform_cpu_init() by the ia64 machvec code.
  */
-void __cpuinit sn_cpu_init(void)
+void sn_cpu_init(void)
 {
         int cpuid;
         int cpuphyid;
diff --git a/arch/ia64/xen/hypervisor.c b/arch/ia64/xen/hypervisor.c
index 52172eee8591..fab62528a80b 100644
--- a/arch/ia64/xen/hypervisor.c
+++ b/arch/ia64/xen/hypervisor.c
@@ -74,7 +74,7 @@ void __init xen_setup_vcpu_info_placement(void)
                 xen_vcpu_setup(cpu);
 }
 
-void __cpuinit
+void
 xen_cpu_init(void)
 {
         xen_smp_intr_init();
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index bcd17b206571..29a7ef4e448b 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -16,6 +16,7 @@ config M32R
         select GENERIC_ATOMIC64
         select ARCH_USES_GETTIMEOFFSET
         select MODULES_USE_ELF_RELA
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config SBUS
         bool
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
index bb1afc1a31cc..6c612b7691b0 100644
--- a/arch/m32r/Kconfig.debug
+++ b/arch/m32r/Kconfig.debug
@@ -2,13 +2,6 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config DEBUG_PAGEALLOC
         bool "Debug page memory allocations"
         depends on DEBUG_KERNEL && BROKEN
diff --git a/arch/m32r/include/asm/pgtable.h b/arch/m32r/include/asm/pgtable.h
index 8a28cfea2729..103ce6710f07 100644
--- a/arch/m32r/include/asm/pgtable.h
+++ b/arch/m32r/include/asm/pgtable.h
@@ -347,9 +347,6 @@ static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
diff --git a/arch/m32r/include/asm/uaccess.h b/arch/m32r/include/asm/uaccess.h
index 1c7047bea200..84fe7ba53035 100644
--- a/arch/m32r/include/asm/uaccess.h
+++ b/arch/m32r/include/asm/uaccess.h
@@ -216,7 +216,7 @@ extern int fixup_exception(struct pt_regs *regs);
 ({                                                                      \
         long __gu_err = 0;                                              \
         unsigned long __gu_val;                                         \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         __get_user_size(__gu_val,(ptr),(size),__gu_err);                \
         (x) = (__typeof__(*(ptr)))__gu_val;                             \
         __gu_err;                                                       \
@@ -227,7 +227,7 @@ extern int fixup_exception(struct pt_regs *regs);
         long __gu_err = -EFAULT;                                        \
         unsigned long __gu_val = 0;                                     \
         const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         if (access_ok(VERIFY_READ,__gu_addr,size))                      \
                 __get_user_size(__gu_val,__gu_addr,(size),__gu_err);    \
         (x) = (__typeof__(*(ptr)))__gu_val;                             \
@@ -295,7 +295,7 @@ do {									\
 #define __put_user_nocheck(x,ptr,size)                                  \
 ({                                                                      \
         long __pu_err;                                                  \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         __put_user_size((x),(ptr),(size),__pu_err);                     \
         __pu_err;                                                       \
 })
@@ -305,7 +305,7 @@ do {									\
 ({                                                                      \
         long __pu_err = -EFAULT;                                        \
         __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         if (access_ok(VERIFY_WRITE,__pu_addr,size))                     \
                 __put_user_size((x),__pu_addr,(size),__pu_err);         \
         __pu_err;                                                       \
@@ -597,7 +597,7 @@ unsigned long __generic_copy_from_user(void *, const void __user *, unsigned lon
  */
 #define copy_to_user(to,from,n)                         \
 ({                                                      \
-        might_sleep();                                  \
+        might_fault();                                  \
         __generic_copy_to_user((to),(from),(n));        \
 })
 
@@ -638,7 +638,7 @@ unsigned long __generic_copy_from_user(void *, const void __user *, unsigned lon
  */
 #define copy_from_user(to,from,n)                       \
 ({                                                      \
-        might_sleep();                                  \
+        might_fault();                                  \
         __generic_copy_from_user((to),(from),(n));      \
 })
 
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 2c468e8b5853..27196303ce36 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -129,11 +129,10 @@ unsigned long __init setup_memory(void)
 #define START_PFN(nid)          (NODE_DATA(nid)->bdata->node_min_pfn)
 #define MAX_LOW_PFN(nid)        (NODE_DATA(nid)->bdata->node_low_pfn)
 
-unsigned long __init zone_sizes_init(void)
+void __init zone_sizes_init(void)
 {
         unsigned long zones_size[MAX_NR_ZONES], zholes_size[MAX_NR_ZONES];
         unsigned long low, start_pfn;
-        unsigned long holes = 0;
         int nid, i;
         mem_prof_t *mp;
 
@@ -147,7 +146,6 @@ unsigned long __init zone_sizes_init(void)
                 low = MAX_LOW_PFN(nid);
                 zones_size[ZONE_DMA] = low - start_pfn;
                 zholes_size[ZONE_DMA] = mp->holes;
-                holes += zholes_size[ZONE_DMA];
 
                 node_set_state(nid, N_NORMAL_MEMORY);
                 free_area_init_node(nid, zones_size, start_pfn, zholes_size);
@@ -161,6 +159,4 @@ unsigned long __init zone_sizes_init(void)
         NODE_DATA(1)->node_zones->watermark[WMARK_MIN] = 0;
         NODE_DATA(1)->node_zones->watermark[WMARK_LOW] = 0;
         NODE_DATA(1)->node_zones->watermark[WMARK_HIGH] = 0;
-
-        return holes;
 }
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index ab4cbce91a9b..0d4146f644dc 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -40,7 +40,6 @@ unsigned long mmu_context_cache_dat;
 #else
 unsigned long mmu_context_cache_dat[NR_CPUS];
 #endif
-static unsigned long hole_pages;
 
 /*
  * function prototype
@@ -57,7 +56,7 @@ void free_initrd_mem(unsigned long, unsigned long);
 #define MAX_LOW_PFN(nid)        (NODE_DATA(nid)->bdata->node_low_pfn)
 
 #ifndef CONFIG_DISCONTIGMEM
-unsigned long __init zone_sizes_init(void)
+void __init zone_sizes_init(void)
 {
         unsigned long  zones_size[MAX_NR_ZONES] = {0, };
         unsigned long  max_dma;
@@ -83,11 +82,9 @@ unsigned long __init zone_sizes_init(void)
 #endif /* CONFIG_MMU */
 
         free_area_init_node(0, zones_size, start_pfn, 0);
-
-        return 0;
 }
 #else   /* CONFIG_DISCONTIGMEM */
-extern unsigned long zone_sizes_init(void);
+extern void zone_sizes_init(void);
 #endif  /* CONFIG_DISCONTIGMEM */
 
 /*======================================================================*
@@ -105,24 +102,7 @@ void __init paging_init(void)
         for (i = 0 ; i < USER_PTRS_PER_PGD * 2 ; i++)
                 pgd_val(pg_dir[i]) = 0;
 #endif /* CONFIG_MMU */
-        hole_pages = zone_sizes_init();
-}
-
-int __init reservedpages_count(void)
-{
-        int reservedpages, nid, i;
-
-        reservedpages = 0;
-        for_each_online_node(nid) {
-                unsigned long flags;
-                pgdat_resize_lock(NODE_DATA(nid), &flags);
-                for (i = 0 ; i < MAX_LOW_PFN(nid) - START_PFN(nid) ; i++)
-                        if (PageReserved(nid_page_nr(nid, i)))
-                                reservedpages++;
-                pgdat_resize_unlock(NODE_DATA(nid), &flags);
-        }
-
-        return reservedpages;
+        zone_sizes_init();
 }
 
 /*======================================================================*
@@ -131,48 +111,20 @@ int __init reservedpages_count(void)
  *======================================================================*/
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-        int nid;
 #ifndef CONFIG_MMU
         extern unsigned long memory_end;
-#endif
-
-        num_physpages = 0;
-        for_each_online_node(nid)
-                num_physpages += MAX_LOW_PFN(nid) - START_PFN(nid) + 1;
-
-        num_physpages -= hole_pages;
 
-#ifndef CONFIG_DISCONTIGMEM
-        max_mapnr = num_physpages;
-#endif  /* CONFIG_DISCONTIGMEM */
-
-#ifdef CONFIG_MMU
-        high_memory = (void *)__va(PFN_PHYS(MAX_LOW_PFN(0)));
-#else
         high_memory = (void *)(memory_end & PAGE_MASK);
+#else
+        high_memory = (void *)__va(PFN_PHYS(MAX_LOW_PFN(0)));
 #endif /* CONFIG_MMU */
 
         /* clear the zero-page */
         memset(empty_zero_page, 0, PAGE_SIZE);
 
-        /* this will put all low memory onto the freelists */
-        for_each_online_node(nid)
-                totalram_pages += free_all_bootmem_node(NODE_DATA(nid));
-
-        reservedpages = reservedpages_count() - hole_pages;
-        codesize = (unsigned long) &_etext - (unsigned long)&_text;
-        datasize = (unsigned long) &_edata - (unsigned long)&_etext;
-        initsize = (unsigned long) &__init_end - (unsigned long)&__init_begin;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, "
-                "%dk reserved, %dk data, %dk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                initsize >> 10);
+        set_max_mapnr(get_num_physpages());
+        free_all_bootmem();
+        mem_init_print_info(NULL);
 }
 
 /*======================================================================*
@@ -181,7 +133,7 @@ void __init mem_init(void)
  *======================================================================*/
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -191,6 +143,6 @@ void free_initmem(void)
  *======================================================================*/
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
diff --git a/arch/m68k/Kconfig.debug b/arch/m68k/Kconfig.debug
index fa12283d58fc..229682721240 100644
--- a/arch/m68k/Kconfig.debug
+++ b/arch/m68k/Kconfig.debug
@@ -11,9 +11,8 @@ config BOOTPARAM_STRING
         depends on BOOTPARAM
 
 config EARLY_PRINTK
-        bool "Early printk" if EMBEDDED
+        bool "Early printk"
         depends on MVME16x || MAC
-        default y
         help
           Write kernel log output directly to a serial port.
 
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index 0f795d8e65fa..b17a8837f0e1 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -214,6 +214,7 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
 CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
 CONFIG_PARPORT_AMIGA=m
 CONFIG_PARPORT_MFC3=m
 CONFIG_PARPORT_ATARI=m
@@ -325,6 +326,7 @@ CONFIG_ZORRO8390=y
 # CONFIG_NET_VENDOR_SEEQ is not set
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PLIP=m
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPP_DEFLATE=m
diff --git a/arch/m68k/configs/q40_defconfig b/arch/m68k/configs/q40_defconfig
index 8982370e8b42..be1496ed9b66 100644
--- a/arch/m68k/configs/q40_defconfig
+++ b/arch/m68k/configs/q40_defconfig
@@ -199,6 +199,9 @@ CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FW_LOADER_USER_HELPER is not set
 CONFIG_CONNECTOR=m
+CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_1284=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=m
 CONFIG_BLK_DEV_DRBD=m
@@ -267,6 +270,7 @@ CONFIG_NE2000=m
 # CONFIG_NET_VENDOR_SMSC is not set
 # CONFIG_NET_VENDOR_STMICRO is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PLIP=m
 CONFIG_PPP=m
 CONFIG_PPP_BSDCOMP=m
 CONFIG_PPP_DEFLATE=m
@@ -292,9 +296,11 @@ CONFIG_SERIO_Q40KBD=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
 # CONFIG_LEGACY_PTYS is not set
 # CONFIG_DEVKMEM is not set
+CONFIG_PRINTER=m
 # CONFIG_HW_RANDOM is not set
 CONFIG_NTP_PPS=y
 CONFIG_PPS_CLIENT_LDISC=m
+CONFIG_PPS_CLIENT_PARPORT=m
 CONFIG_PTP_1588_CLOCK=m
 # CONFIG_HWMON is not set
 CONFIG_FB=y
diff --git a/arch/m68k/include/asm/parport.h b/arch/m68k/include/asm/parport.h
index 5ea75e6a7399..c85cece778e8 100644
--- a/arch/m68k/include/asm/parport.h
+++ b/arch/m68k/include/asm/parport.h
@@ -11,6 +11,8 @@
 #ifndef _ASM_M68K_PARPORT_H
 #define _ASM_M68K_PARPORT_H 1
 
+#undef insl
+#undef outsl
 #define insl(port,buf,len)   isa_insb(port,buf,(len)<<2)
 #define outsl(port,buf,len)  isa_outsb(port,buf,(len)<<2)
 
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index dc35e0e106e4..9f5abbda1ea7 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -135,9 +135,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /* MMU-specific headers */
 
 #ifdef CONFIG_SUN3
diff --git a/arch/m68k/include/asm/pgtable_no.h b/arch/m68k/include/asm/pgtable_no.h
index 037028f4ab70..c527fc2ecf82 100644
--- a/arch/m68k/include/asm/pgtable_no.h
+++ b/arch/m68k/include/asm/pgtable_no.h
@@ -55,9 +55,6 @@ extern unsigned int kobjsize(const void *objp);
  */
 #define pgtable_cache_init()    do { } while (0)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h
index 9aea9f11fa25..c30c03d98581 100644
--- a/arch/m68k/include/asm/string.h
+++ b/arch/m68k/include/asm/string.h
@@ -4,20 +4,6 @@
 #include <linux/types.h>
 #include <linux/compiler.h>
 
-static inline char *__kernel_strcpy(char *dest, const char *src)
-{
-        char *xdest = dest;
-
-        asm volatile ("\n"
-                "1:     move.b  (%1)+,(%0)+\n"
-                "       jne     1b"
-                : "+a" (dest), "+a" (src)
-                : : "memory");
-        return xdest;
-}
-
-#ifndef __IN_STRING_C
-
 #define __HAVE_ARCH_STRNLEN
 static inline size_t strnlen(const char *s, size_t count)
 {
@@ -34,16 +20,6 @@ static inline size_t strnlen(const char *s, size_t count)
         return sc - s;
 }
 
-#define __HAVE_ARCH_STRCPY
-#if __GNUC__ >= 4
-#define strcpy(d, s)    (__builtin_constant_p(s) &&     \
-                         __builtin_strlen(s) <= 32 ?    \
-                         __builtin_strcpy(d, s) :       \
-                         __kernel_strcpy(d, s))
-#else
-#define strcpy(d, s)    __kernel_strcpy(d, s)
-#endif
-
 #define __HAVE_ARCH_STRNCPY
 static inline char *strncpy(char *dest, const char *src, size_t n)
 {
@@ -61,12 +37,6 @@ static inline char *strncpy(char *dest, const char *src, size_t n)
         return xdest;
 }
 
-#define __HAVE_ARCH_STRCAT
-#define strcat(d, s)    ({                      \
-        char *__d = (d);                        \
-        strcpy(__d + strlen(__d), (s));         \
-})
-
 #ifndef CONFIG_COLDFIRE
 #define __HAVE_ARCH_STRCMP
 static inline int strcmp(const char *cs, const char *ct)
@@ -100,6 +70,4 @@ extern void *memset(void *, int, __kernel_size_t);
 extern void *memcpy(void *, const void *, __kernel_size_t);
 #define memcpy(d, s, n) __builtin_memcpy(d, s, n)
 
-#endif
-
 #endif /* _M68K_STRING_H_ */
diff --git a/arch/m68k/include/asm/uaccess_mm.h b/arch/m68k/include/asm/uaccess_mm.h
index 472c891a4aee..15901db435b9 100644
--- a/arch/m68k/include/asm/uaccess_mm.h
+++ b/arch/m68k/include/asm/uaccess_mm.h
@@ -90,7 +90,7 @@ asm volatile ("\n"					\
                 __put_user_asm(__pu_err, __pu_val, ptr, b, d, -EFAULT); \
                 break;                                                  \
         case 2:                                                         \
-                __put_user_asm(__pu_err, __pu_val, ptr, w, d, -EFAULT); \
+                __put_user_asm(__pu_err, __pu_val, ptr, w, r, -EFAULT); \
                 break;                                                  \
         case 4:                                                         \
                 __put_user_asm(__pu_err, __pu_val, ptr, l, r, -EFAULT); \
@@ -158,7 +158,7 @@ asm volatile ("\n"					\
                 __get_user_asm(__gu_err, x, ptr, u8, b, d, -EFAULT);    \
                 break;                                                  \
         case 2:                                                         \
-                __get_user_asm(__gu_err, x, ptr, u16, w, d, -EFAULT);   \
+                __get_user_asm(__gu_err, x, ptr, u16, w, r, -EFAULT);   \
                 break;                                                  \
         case 4:                                                         \
                 __get_user_asm(__gu_err, x, ptr, u32, l, r, -EFAULT);   \
@@ -245,7 +245,7 @@ __constant_copy_from_user(void *to, const void __user *from, unsigned long n)
                 __get_user_asm(res, *(u8 *)to, (u8 __user *)from, u8, b, d, 1);
                 break;
         case 2:
-                __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w, d, 2);
+                __get_user_asm(res, *(u16 *)to, (u16 __user *)from, u16, w, r, 2);
                 break;
         case 3:
                 __constant_copy_from_user_asm(res, to, from, tmp, 3, w, b,);
@@ -326,7 +326,7 @@ __constant_copy_to_user(void __user *to, const void *from, unsigned long n)
                 __put_user_asm(res, *(u8 *)from, (u8 __user *)to, b, d, 1);
                 break;
         case 2:
-                __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, d, 2);
+                __put_user_asm(res, *(u16 *)from, (u16 __user *)to, w, r, 2);
                 break;
         case 3:
                 __constant_copy_to_user_asm(res, to, from, tmp, 3, w, b,);
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index a972b00cd77d..8b7b22846366 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -77,7 +77,7 @@ int main(void)
         DEFINE(BIR_SIZE, offsetof(struct bi_record, size));
         DEFINE(BIR_DATA, offsetof(struct bi_record, data));
 
-        /* offsets into font_desc (drivers/video/console/font.h) */
+        /* offsets into the font_desc struct */
         DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx));
         DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name));
         DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width));
diff --git a/arch/m68k/kernel/ints.c b/arch/m68k/kernel/ints.c
index 6b32b64bac35..4d7da384eea0 100644
--- a/arch/m68k/kernel/ints.c
+++ b/arch/m68k/kernel/ints.c
@@ -101,7 +101,7 @@ void __init m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt)
         BUG_ON(IRQ_USER + cnt > NR_IRQS);
         m68k_first_user_vec = vec;
         for (i = 0; i < cnt; i++)
-                irq_set_chip(IRQ_USER + i, &user_irq_chip);
+                irq_set_chip_and_handler(i, &user_irq_chip, handle_simple_irq);
         *user_irqvec_fixup = vec - IRQ_USER;
         flush_icache();
 }
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index a9d782d34276..fcd8eb1d7c7d 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -6,7 +6,7 @@
 lib-y   := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
            memcpy.o memset.o memmove.o
 
-lib-$(CONFIG_MMU) += string.o uaccess.o
+lib-$(CONFIG_MMU) += uaccess.o
 lib-$(CONFIG_CPU_HAS_NO_MULDIV64) += mulsi3.o divsi3.o udivsi3.o
 lib-$(CONFIG_CPU_HAS_NO_MULDIV64) += modsi3.o umodsi3.o
 
diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c
deleted file mode 100644
index 4d61fa8a112c..000000000000
--- a/arch/m68k/lib/string.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#define __IN_STRING_C
-
-#include <linux/module.h>
-#include <linux/string.h>
-
-char *strcpy(char *dest, const char *src)
-{
-        return __kernel_strcpy(dest, src);
-}
-EXPORT_SYMBOL(strcpy);
-
-char *strcat(char *dest, const char *src)
-{
-        return __kernel_strcpy(dest + strlen(dest), src);
-}
-EXPORT_SYMBOL(strcat);
diff --git a/arch/m68k/lib/uaccess.c b/arch/m68k/lib/uaccess.c
index 5e97f2ee7c11..35d1442dee89 100644
--- a/arch/m68k/lib/uaccess.c
+++ b/arch/m68k/lib/uaccess.c
@@ -52,7 +52,7 @@ unsigned long __generic_copy_from_user(void *to, const void __user *from,
                 "       .long   3b,30b\n"
                 "       .long   5b,50b\n"
                 "       .previous"
-                : "=d" (res), "+a" (from), "+a" (to), "=&r" (tmp)
+                : "=d" (res), "+a" (from), "+a" (to), "=&d" (tmp)
                 : "0" (n / 4), "d" (n & 3));
 
         return res;
@@ -96,7 +96,7 @@ unsigned long __generic_copy_to_user(void __user *to, const void *from,
                 "       .long   7b,50b\n"
                 "       .long   8b,50b\n"
                 "       .previous"
-                : "=d" (res), "+a" (from), "+a" (to), "=&r" (tmp)
+                : "=d" (res), "+a" (from), "+a" (to), "=&d" (tmp)
                 : "0" (n / 4), "d" (n & 3));
 
         return res;
@@ -141,7 +141,7 @@ unsigned long __clear_user(void __user *to, unsigned long n)
                 "       .long   7b,40b\n"
                 "       .previous"
                 : "=d" (res), "+a" (to)
-                : "r" (0), "0" (n / 4), "d" (n & 3));
+                : "d" (0), "0" (n / 4), "d" (n & 3));
 
     return res;
 }
diff --git a/arch/m68k/math-emu/fp_arith.c b/arch/m68k/math-emu/fp_arith.c
index 08f286db3c5a..239eb1990184 100644
--- a/arch/m68k/math-emu/fp_arith.c
+++ b/arch/m68k/math-emu/fp_arith.c
@@ -519,7 +519,7 @@ static void fp_roundint(struct fp_ext *dest, int mode)
                                 return;
                         break;
                 case 0x401e:
-                        if (!(oldmant.m32[1] >= 0))
+                        if (oldmant.m32[1] & 0x80000000)
                                 return;
                         if (oldmant.m32[0] & 1)
                                 break;
diff --git a/arch/m68k/mm/init.c b/arch/m68k/mm/init.c
index 1af2ca3411f6..6b4baa6e4d31 100644
--- a/arch/m68k/mm/init.c
+++ b/arch/m68k/mm/init.c
@@ -110,7 +110,7 @@ void __init paging_init(void)
 void free_initmem(void)
 {
 #ifndef CONFIG_MMU_SUN3
-        free_initmem_default(0);
+        free_initmem_default(-1);
 #endif /* CONFIG_MMU_SUN3 */
 }
 
@@ -146,38 +146,11 @@ void __init print_memmap(void)
                 MLK_ROUNDUP(__bss_start, __bss_stop));
 }
 
-void __init mem_init(void)
+static inline void init_pointer_tables(void)
 {
-        pg_data_t *pgdat;
-        int codepages = 0;
-        int datapages = 0;
-        int initpages = 0;
+#if defined(CONFIG_MMU) && !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
         int i;
 
-        /* this will put all memory onto the freelists */
-        totalram_pages = num_physpages = 0;
-        for_each_online_pgdat(pgdat) {
-                num_physpages += pgdat->node_present_pages;
-
-                totalram_pages += free_all_bootmem_node(pgdat);
-                for (i = 0; i < pgdat->node_spanned_pages; i++) {
-                        struct page *page = pgdat->node_mem_map + i;
-                        char *addr = page_to_virt(page);
-
-                        if (!PageReserved(page))
-                                continue;
-                        if (addr >= _text &&
-                            addr < _etext)
-                                codepages++;
-                        else if (addr >= __init_begin &&
-                                 addr < __init_end)
-                                initpages++;
-                        else
-                                datapages++;
-                }
-        }
-
-#if defined(CONFIG_MMU) && !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
         /* insert pointer tables allocated so far into the tablelist */
         init_pointer_table((unsigned long)kernel_pg_dir);
         for (i = 0; i < PTRS_PER_PGD; i++) {
@@ -189,19 +162,20 @@ void __init mem_init(void)
         if (zero_pgtable)
                 init_pointer_table((unsigned long)zero_pgtable);
 #endif
+}
 
-        pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               totalram_pages << (PAGE_SHIFT-10),
-               codepages << (PAGE_SHIFT-10),
-               datapages << (PAGE_SHIFT-10),
-               initpages << (PAGE_SHIFT-10));
+void __init mem_init(void)
+{
+        /* this will put all memory onto the freelists */
+        free_all_bootmem();
+        init_pointer_tables();
+        mem_init_print_info(NULL);
         print_memmap();
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
index 8572246db84d..b33f97a13e6d 100644
--- a/arch/m68k/platform/coldfire/pci.c
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -320,7 +320,6 @@ static int __init mcf_pci_init(void)
         pci_bus_size_bridges(rootbus);
         pci_bus_assign_resources(rootbus);
         pci_enable_bridges(rootbus);
-        pci_bus_add_devices(rootbus);
         return 0;
 }
 
diff --git a/arch/m68k/sun3/sun3dvma.c b/arch/m68k/sun3/sun3dvma.c
index ca0966cac72a..cab54482ca34 100644
--- a/arch/m68k/sun3/sun3dvma.c
+++ b/arch/m68k/sun3/sun3dvma.c
@@ -275,7 +275,7 @@ void dvma_init(void)
 
 }
 
-inline unsigned long dvma_map_align(unsigned long kaddr, int len, int align)
+unsigned long dvma_map_align(unsigned long kaddr, int len, int align)
 {
 
         unsigned long baddr;
diff --git a/arch/metag/Kconfig b/arch/metag/Kconfig
index dcd94406030e..cfd831c29824 100644
--- a/arch/metag/Kconfig
+++ b/arch/metag/Kconfig
@@ -30,6 +30,7 @@ config METAG
         select OF
         select OF_EARLY_FLATTREE
         select SPARSE_IRQ
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config STACKTRACE_SUPPORT
         def_bool y
diff --git a/arch/metag/Kconfig.debug b/arch/metag/Kconfig.debug
index e45bbf6a7a5d..cb5c92860540 100644
--- a/arch/metag/Kconfig.debug
+++ b/arch/metag/Kconfig.debug
@@ -6,13 +6,6 @@ config TRACE_IRQFLAGS_SUPPORT
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config 4KSTACKS
         bool "Use 4Kb for kernel stacks instead of 8Kb"
         depends on DEBUG_KERNEL
diff --git a/arch/metag/include/asm/hugetlb.h b/arch/metag/include/asm/hugetlb.h
index f545477e61f3..471f481e67f3 100644
--- a/arch/metag/include/asm/hugetlb.h
+++ b/arch/metag/include/asm/hugetlb.h
@@ -2,6 +2,7 @@
 #define _ASM_METAG_HUGETLB_H
 
 #include <asm/page.h>
+#include <asm-generic/hugetlb.h>
 
 
 static inline int is_hugepage_only_range(struct mm_struct *mm,
diff --git a/arch/metag/include/asm/pgtable.h b/arch/metag/include/asm/pgtable.h
index 1cd13d595198..0d9dc5487296 100644
--- a/arch/metag/include/asm/pgtable.h
+++ b/arch/metag/include/asm/pgtable.h
@@ -333,9 +333,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*
  * No page table caches to initialise
  */
diff --git a/arch/metag/kernel/perf/perf_event.c b/arch/metag/kernel/perf/perf_event.c
index 366569425c52..5b18888ee364 100644
--- a/arch/metag/kernel/perf/perf_event.c
+++ b/arch/metag/kernel/perf/perf_event.c
@@ -882,7 +882,7 @@ static int __init init_hw_perf_events(void)
         }
 
         register_cpu_notifier(&metag_pmu_notifier);
-        ret = perf_pmu_register(&pmu, (char *)metag_pmu->name, PERF_TYPE_RAW);
+        ret = perf_pmu_register(&pmu, metag_pmu->name, PERF_TYPE_RAW);
 out:
         return ret;
 }
diff --git a/arch/metag/mm/init.c b/arch/metag/mm/init.c
index d05b8455c44c..28813f164730 100644
--- a/arch/metag/mm/init.c
+++ b/arch/metag/mm/init.c
@@ -376,34 +376,21 @@ void __init paging_init(unsigned long mem_end)
 
 void __init mem_init(void)
 {
-        int nid;
-
 #ifdef CONFIG_HIGHMEM
         unsigned long tmp;
+
+        /*
+         * Explicitly reset zone->managed_pages because highmem pages are
+         * freed before calling free_all_bootmem();
+         */
+        reset_all_zones_managed_pages();
         for (tmp = highstart_pfn; tmp < highend_pfn; tmp++)
                 free_highmem_page(pfn_to_page(tmp));
-        num_physpages += totalhigh_pages;
 #endif /* CONFIG_HIGHMEM */
 
-        for_each_online_node(nid) {
-                pg_data_t *pgdat = NODE_DATA(nid);
-                unsigned long node_pages = 0;
-
-                num_physpages += pgdat->node_present_pages;
-
-                if (pgdat->node_spanned_pages)
-                        node_pages = free_all_bootmem_node(pgdat);
-
-                totalram_pages += node_pages;
-        }
-
-        pr_info("Memory: %luk/%luk available\n",
-                (unsigned long)nr_free_pages() << (PAGE_SHIFT - 10),
-                num_physpages << (PAGE_SHIFT - 10));
-
+        free_all_bootmem();
+        mem_init_print_info(NULL);
         show_mem(0);
-
-        return;
 }
 
 void free_initmem(void)
@@ -414,7 +401,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 85a5ae8e9bd0..fd850879854d 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -168,7 +168,6 @@ extern int page_is_ram(unsigned long pfn);
 #  else /* CONFIG_MMU */
 #  define ARCH_PFN_OFFSET       (memory_start >> PAGE_SHIFT)
 #  define pfn_valid(pfn)        ((pfn) < (max_mapnr + ARCH_PFN_OFFSET))
-#  define VALID_PAGE(page)      ((page - mem_map) < max_mapnr)
 #  endif /* CONFIG_MMU */
 
 # endif /* __ASSEMBLY__ */
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index a7311cd9dee0..95cef0b5f836 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -13,9 +13,6 @@
 
 #include <asm/setup.h>
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #ifndef __ASSEMBLY__
 extern int mem_init_done;
 #endif
diff --git a/arch/microblaze/include/asm/uaccess.h b/arch/microblaze/include/asm/uaccess.h
index 04e49553bdf9..0aa005703a0b 100644
--- a/arch/microblaze/include/asm/uaccess.h
+++ b/arch/microblaze/include/asm/uaccess.h
@@ -145,7 +145,7 @@ static inline unsigned long __must_check __clear_user(void __user *to,
 static inline unsigned long __must_check clear_user(void __user *to,
                                                         unsigned long n)
 {
-        might_sleep();
+        might_fault();
         if (unlikely(!access_ok(VERIFY_WRITE, to, n)))
                 return n;
 
@@ -371,7 +371,7 @@ extern long __user_bad(void);
 static inline long copy_from_user(void *to,
                 const void __user *from, unsigned long n)
 {
-        might_sleep();
+        might_fault();
         if (access_ok(VERIFY_READ, from, n))
                 return __copy_from_user(to, from, n);
         return n;
@@ -385,7 +385,7 @@ static inline long copy_from_user(void *to,
 static inline long copy_to_user(void __user *to,
                 const void *from, unsigned long n)
 {
-        might_sleep();
+        might_fault();
         if (access_ok(VERIFY_WRITE, to, n))
                 return __copy_to_user(to, from, n);
         return n;
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index b38ae3acfeb4..74c7bcc1e82d 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -71,24 +71,17 @@ static void __init highmem_init(void)
         kmap_prot = PAGE_KERNEL;
 }
 
-static unsigned long highmem_setup(void)
+static void highmem_setup(void)
 {
         unsigned long pfn;
-        unsigned long reservedpages = 0;
 
         for (pfn = max_low_pfn; pfn < max_pfn; ++pfn) {
                 struct page *page = pfn_to_page(pfn);
 
                 /* FIXME not sure about */
-                if (memblock_is_reserved(pfn << PAGE_SHIFT))
-                        continue;
-                free_highmem_page(page);
-                reservedpages++;
+                if (!memblock_is_reserved(pfn << PAGE_SHIFT))
+                        free_highmem_page(page);
         }
-        pr_info("High memory: %luk\n",
-                                        totalhigh_pages << (PAGE_SHIFT-10));
-
-        return reservedpages;
 }
 #endif /* CONFIG_HIGHMEM */
 
@@ -167,13 +160,12 @@ void __init setup_memory(void)
          * min_low_pfn - the first page (mm/bootmem.c - node_boot_start)
          * max_low_pfn
          * max_mapnr - the first unused page (mm/bootmem.c - node_low_pfn)
-         * num_physpages - number of all pages
          */
 
         /* memory start is from the kernel end (aligned) to higher addr */
         min_low_pfn = memory_start >> PAGE_SHIFT; /* minimum for allocation */
         /* RAM is assumed contiguous */
-        num_physpages = max_mapnr = memory_size >> PAGE_SHIFT;
+        max_mapnr = memory_size >> PAGE_SHIFT;
         max_low_pfn = ((u64)memory_start + (u64)lowmem_size) >> PAGE_SHIFT;
         max_pfn = ((u64)memory_start + (u64)memory_size) >> PAGE_SHIFT;
 
@@ -235,57 +227,26 @@ void __init setup_memory(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 void __init mem_init(void)
 {
-        pg_data_t *pgdat;
-        unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize;
-
         high_memory = (void *)__va(memory_start + lowmem_size - 1);
 
         /* this will put all memory onto the freelists */
-        totalram_pages += free_all_bootmem();
-
-        for_each_online_pgdat(pgdat) {
-                unsigned long i;
-                struct page *page;
-
-                for (i = 0; i < pgdat->node_spanned_pages; i++) {
-                        if (!pfn_valid(pgdat->node_start_pfn + i))
-                                continue;
-                        page = pgdat_page_nr(pgdat, i);
-                        if (PageReserved(page))
-                                reservedpages++;
-                }
-        }
-
+        free_all_bootmem();
 #ifdef CONFIG_HIGHMEM
-        reservedpages -= highmem_setup();
+        highmem_setup();
 #endif
 
-        codesize = (unsigned long)&_sdata - (unsigned long)&_stext;
-        datasize = (unsigned long)&_edata - (unsigned long)&_sdata;
-        initsize = (unsigned long)&__init_end - (unsigned long)&__init_begin;
-        bsssize = (unsigned long)&__bss_stop - (unsigned long)&__bss_start;
-
-        pr_info("Memory: %luk/%luk available (%luk kernel code, ",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10);
-        pr_cont("%luk reserved, %luk data, %luk bss, %luk init)\n",
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                bsssize >> 10,
-                initsize >> 10);
-
+        mem_init_print_info(NULL);
 #ifdef CONFIG_MMU
         pr_info("Kernel virtual memory layout:\n");
         pr_info("  * 0x%08lx..0x%08lx  : fixmap\n", FIXADDR_START, FIXADDR_TOP);
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 7a58ab933b20..beeff436b22f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -42,6 +42,7 @@ config MIPS
         select MODULES_USE_ELF_REL if MODULES
         select MODULES_USE_ELF_RELA if MODULES && 64BIT
         select CLONE_BACKWARDS
+        select HAVE_DEBUG_STACKOVERFLOW
 
 menu "Machine selection"
 
@@ -962,7 +963,7 @@ config SYS_HAS_EARLY_PRINTK
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
-        depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU
+        depends on SMP && SYS_SUPPORTS_HOTPLUG_CPU
         help
           Say Y here to allow turning CPUs off and on. CPUs can be
           controlled through /sys/devices/system/cpu.
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 5a43aa0798ca..37871f0de15e 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -67,15 +67,6 @@ config CMDLINE_OVERRIDE
 
           Normally, you will choose 'N' here.
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit(2GB on MIPS). The debugging option
-          provides another way to check stack overflow happened on kernel mode
-          stack usually caused by nested interruption.
-
 config SMTC_IDLE_HOOK_DEBUG
         bool "Enable additional debug checks before going into CPU idle loop"
         depends on DEBUG_KERNEL && MIPS_MT_SMTC
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index a22f06a6f7ca..7181def6037a 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -607,7 +607,7 @@ static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
 
 static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)
 {
-        if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH)
+        if (irq_get_trigger_type(irq) & IRQ_TYPE_EDGE_BOTH)
                 handle_edge_irq(irq, desc);
         else
                 handle_level_irq(irq, desc);
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
         if (! ((asid += ASID_INC) & ASID_MASK) ) {
                 if (cpu_has_vtag_icache)
                         flush_icache_all();
-#ifdef CONFIG_VIRTUALIZATION
+#ifdef CONFIG_KVM
                 kvm_local_flush_tlb_all();      /* start new asid cycle */
 #else
                 local_flush_tlb_all();  /* start new asid cycle */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 8b8f6b393363..008324d1c261 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -394,9 +394,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
         phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
         return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
 }
-#else
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#define io_remap_pfn_range io_remap_pfn_range
 #endif
 
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 3f424f5217da..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -58,56 +58,53 @@ struct kvm_fpu {
  *  bits[2..0]   - Register 'sel' index.
  *  bits[7..3]   - Register 'rd'  index.
  *  bits[15..8]  - Must be zero.
- *  bits[63..16] - 1 -> CP0 registers.
+ *  bits[31..16] - 1 -> CP0 registers.
+ *  bits[51..32] - Must be zero.
+ *  bits[63..52] - As per linux/kvm.h
  *
  * Other sets registers may be added in the future.  Each set would
- * have its own identifier in bits[63..16].
- *
- * The addr field of struct kvm_one_reg must point to an aligned
- * 64-bit wide location.  For registers that are narrower than
- * 64-bits, the value is stored in the low order bits of the location,
- * and sign extended to 64-bits.
+ * have its own identifier in bits[31..16].
  *
  * The registers defined in struct kvm_regs are also accessible, the
  * id values for these are below.
  */
 
-#define KVM_REG_MIPS_R0 0
-#define KVM_REG_MIPS_R1 1
-#define KVM_REG_MIPS_R2 2
-#define KVM_REG_MIPS_R3 3
-#define KVM_REG_MIPS_R4 4
-#define KVM_REG_MIPS_R5 5
-#define KVM_REG_MIPS_R6 6
-#define KVM_REG_MIPS_R7 7
-#define KVM_REG_MIPS_R8 8
-#define KVM_REG_MIPS_R9 9
-#define KVM_REG_MIPS_R10 10
-#define KVM_REG_MIPS_R11 11
-#define KVM_REG_MIPS_R12 12
-#define KVM_REG_MIPS_R13 13
-#define KVM_REG_MIPS_R14 14
-#define KVM_REG_MIPS_R15 15
-#define KVM_REG_MIPS_R16 16
-#define KVM_REG_MIPS_R17 17
-#define KVM_REG_MIPS_R18 18
-#define KVM_REG_MIPS_R19 19
-#define KVM_REG_MIPS_R20 20
-#define KVM_REG_MIPS_R21 21
-#define KVM_REG_MIPS_R22 22
-#define KVM_REG_MIPS_R23 23
-#define KVM_REG_MIPS_R24 24
-#define KVM_REG_MIPS_R25 25
-#define KVM_REG_MIPS_R26 26
-#define KVM_REG_MIPS_R27 27
-#define KVM_REG_MIPS_R28 28
-#define KVM_REG_MIPS_R29 29
-#define KVM_REG_MIPS_R30 30
-#define KVM_REG_MIPS_R31 31
+#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
+#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
+#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
+#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
+#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
+#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
+#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
+#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
+#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
+#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
+#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
+#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
+#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
+#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
+#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
+#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
+#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
+#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
+#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
+#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
+#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
+#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
+#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
+#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
+#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
+#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
+#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
+#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
+#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
+#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
+#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
+#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
 
-#define KVM_REG_MIPS_HI 32
-#define KVM_REG_MIPS_LO 33
-#define KVM_REG_MIPS_PC 34
+#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
+#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
+#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
 
 /*
  * KVM MIPS specific structures and definitions
diff --git a/arch/mips/kernel/crash_dump.c b/arch/mips/kernel/crash_dump.c
index 3be9e7bb30ff..f291cf99b03a 100644
--- a/arch/mips/kernel/crash_dump.c
+++ b/arch/mips/kernel/crash_dump.c
@@ -4,16 +4,6 @@
 #include <asm/uaccess.h>
 #include <linux/slab.h>
 
-static int __init parse_savemaxmem(char *p)
-{
-        if (p)
-                saved_max_pfn = (memparse(p, &p) >> PAGE_SHIFT) - 1;
-
-        return 1;
-}
-__setup("savemaxmem=", parse_savemaxmem);
-
-
 static void *kdump_buf_page;
 
 /**
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
 #define MCOUNT_OFFSET_INSNS 4
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
+
 /* Arch override because MIPS doesn't need to run this from stop_machine() */
 void arch_ftrace_update_code(int command)
 {
         ftrace_modify_all_code(command);
 }
 
+#endif
+
 /*
  * Check if the address is in kernel space
  *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
 }
 
 /*
- * The Au1xxx wait is available only if using 32khz counter or
- * external timer source, but specifically not CP0 Counter.
- * alchemy/common/time.c may override cpu_wait!
+ * Au1 'wait' is only useful when the 32kHz counter is used as timer,
+ * since coreclock (and the cp0 counter) stops upon executing it. Only an
+ * interrupt can wake it, so they must be enabled before entering idle modes.
  */
 static void au1k_wait(void)
 {
+        unsigned long c0status = read_c0_status() | 1;  /* irqs on */
+
         __asm__(
         "       .set    mips3                   \n"
         "       cache   0x14, 0(%0)             \n"
         "       cache   0x14, 32(%0)            \n"
         "       sync                            \n"
-        "       nop                             \n"
+        "       mtc0    %1, $12                 \n" /* wr c0status */
         "       wait                            \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       nop                             \n"
         "       .set    mips0                   \n"
-        : : "r" (au1k_wait));
-        local_irq_enable();
+        : : "r" (au1k_wait), "r" (c0status));
 }
 
 static int __initdata nowait;
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index fd814e08c945..cb098628aee8 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -27,12 +27,12 @@ unsigned long mt_fpemul_threshold;
  * FPU affinity with the user's requested processor affinity.
  * This code is 98% identical with the sys_sched_setaffinity()
  * and sys_sched_getaffinity() system calls, and should be
- * updated when kernel/sched.c changes.
+ * updated when kernel/sched/core.c changes.
  */
 
 /*
  * find_process_by_pid - find a process with a matching PID value.
- * used in sys_sched_set/getaffinity() in kernel/sched.c, so
+ * used in sys_sched_set/getaffinity() in kernel/sched/core.c, so
  * cloned here.
  */
 static inline struct task_struct *find_process_by_pid(pid_t pid)
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 9b36424b03c5..e9127ec612ef 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -476,8 +476,9 @@ einval: li	v0, -ENOSYS
         /*
          * For FPU affinity scheduling on MIPS MT processors, we need to
          * intercept sys_sched_xxxaffinity() calls until we get a proper hook
-         * in kernel/sched.c.  Considered only temporary we only support these
-         * hooks for the 32-bit kernel - there is no MIPS64 MT processor atm.
+         * in kernel/sched/core.c.  Considered only temporary we only support
+         * these hooks for the 32-bit kernel - there is no MIPS64 MT processor
+         * atm.
          */
         sys     mipsmt_sys_sched_setaffinity    3
         sys     mipsmt_sys_sched_getaffinity    3
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index d934b017f479..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
         return -ENOIOCTLCMD;
 }
 
-#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0)
-#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0)
-#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2)
-#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0)
-#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1)
-#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0)
-#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0)
-#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0)
-#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0)
-#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0)
-#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0)
-#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0)
-#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0)
-#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1)
-#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0)
-#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1)
-#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2)
-#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3)
-#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7)
-#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0)
-#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0)
+#define MIPS_CP0_32(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
+
+#define MIPS_CP0_64(_R, _S)                                     \
+        (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
+
+#define KVM_REG_MIPS_CP0_INDEX          MIPS_CP0_32(0, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO0       MIPS_CP0_64(2, 0)
+#define KVM_REG_MIPS_CP0_ENTRYLO1       MIPS_CP0_64(3, 0)
+#define KVM_REG_MIPS_CP0_CONTEXT        MIPS_CP0_64(4, 0)
+#define KVM_REG_MIPS_CP0_USERLOCAL      MIPS_CP0_64(4, 2)
+#define KVM_REG_MIPS_CP0_PAGEMASK       MIPS_CP0_32(5, 0)
+#define KVM_REG_MIPS_CP0_PAGEGRAIN      MIPS_CP0_32(5, 1)
+#define KVM_REG_MIPS_CP0_WIRED          MIPS_CP0_32(6, 0)
+#define KVM_REG_MIPS_CP0_HWRENA         MIPS_CP0_32(7, 0)
+#define KVM_REG_MIPS_CP0_BADVADDR       MIPS_CP0_64(8, 0)
+#define KVM_REG_MIPS_CP0_COUNT          MIPS_CP0_32(9, 0)
+#define KVM_REG_MIPS_CP0_ENTRYHI        MIPS_CP0_64(10, 0)
+#define KVM_REG_MIPS_CP0_COMPARE        MIPS_CP0_32(11, 0)
+#define KVM_REG_MIPS_CP0_STATUS         MIPS_CP0_32(12, 0)
+#define KVM_REG_MIPS_CP0_CAUSE          MIPS_CP0_32(13, 0)
+#define KVM_REG_MIPS_CP0_EBASE          MIPS_CP0_64(15, 1)
+#define KVM_REG_MIPS_CP0_CONFIG         MIPS_CP0_32(16, 0)
+#define KVM_REG_MIPS_CP0_CONFIG1        MIPS_CP0_32(16, 1)
+#define KVM_REG_MIPS_CP0_CONFIG2        MIPS_CP0_32(16, 2)
+#define KVM_REG_MIPS_CP0_CONFIG3        MIPS_CP0_32(16, 3)
+#define KVM_REG_MIPS_CP0_CONFIG7        MIPS_CP0_32(16, 7)
+#define KVM_REG_MIPS_CP0_XCONTEXT       MIPS_CP0_64(20, 0)
+#define KVM_REG_MIPS_CP0_ERROREPC       MIPS_CP0_64(30, 0)
 
 static u64 kvm_mips_get_one_regs[] = {
         KVM_REG_MIPS_R0,
@@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = {
 static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
                             const struct kvm_one_reg *reg)
 {
-        u64 __user *uaddr = (u64 __user *)(long)reg->addr;
-
         struct mips_coproc *cop0 = vcpu->arch.cop0;
         s64 v;
 
@@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
         default:
                 return -EINVAL;
         }
-        return put_user(v, uaddr);
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+                return put_user(v, uaddr64);
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                u32 v32 = (u32)v;
+                return put_user(v32, uaddr32);
+        } else {
+                return -EINVAL;
+        }
 }
 
 static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
                             const struct kvm_one_reg *reg)
 {
-        u64 __user *uaddr = (u64 __user *)(long)reg->addr;
         struct mips_coproc *cop0 = vcpu->arch.cop0;
         u64 v;
 
-        if (get_user(v, uaddr) != 0)
-                return -EFAULT;
+        if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
+                u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
+
+                if (get_user(v, uaddr64) != 0)
+                        return -EFAULT;
+        } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
+                u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
+                s32 v32;
+
+                if (get_user(v32, uaddr32) != 0)
+                        return -EFAULT;
+                v = (s64)v32;
+        } else {
+                return -EINVAL;
+        }
 
         switch (reg->id) {
         case KVM_REG_MIPS_R0:
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index bc739d4bab2e..4dc2f5fa3f67 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -121,7 +121,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         clk->rate = rate;
 
         regval = LOONGSON_CHIPCFG0;
-        regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
+        regval = (regval & ~0x7) |
+                (loongson2_clockmod_table[i].driver_data - 1);
         LOONGSON_CHIPCFG0 = regval;
 
         return ret;
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 9b973e0af9cb..4e73f10a7519 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -359,11 +359,24 @@ void __init paging_init(void)
 static struct kcore_list kcore_kseg0;
 #endif
 
-void __init mem_init(void)
+static inline void mem_init_free_highmem(void)
 {
-        unsigned long codesize, reservedpages, datasize, initsize;
-        unsigned long tmp, ram;
+#ifdef CONFIG_HIGHMEM
+        unsigned long tmp;
 
+        for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
+                struct page *page = pfn_to_page(tmp);
+
+                if (!page_is_ram(tmp))
+                        SetPageReserved(page);
+                else
+                        free_highmem_page(page);
+        }
+#endif
+}
+
+void __init mem_init(void)
+{
 #ifdef CONFIG_HIGHMEM
 #ifdef CONFIG_DISCONTIGMEM
 #error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
@@ -374,34 +387,10 @@ void __init mem_init(void)
 #endif
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
 
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
         setup_zero_pages();     /* Setup zeroed pages.  */
-
-        reservedpages = ram = 0;
-        for (tmp = 0; tmp < max_low_pfn; tmp++)
-                if (page_is_ram(tmp) && pfn_valid(tmp)) {
-                        ram++;
-                        if (PageReserved(pfn_to_page(tmp)))
-                                reservedpages++;
-                }
-        num_physpages = ram;
-
-#ifdef CONFIG_HIGHMEM
-        for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
-                struct page *page = pfn_to_page(tmp);
-
-                if (!page_is_ram(tmp)) {
-                        SetPageReserved(page);
-                        continue;
-                }
-                free_highmem_page(page);
-        }
-        num_physpages += totalhigh_pages;
-#endif
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
+        mem_init_free_highmem();
+        mem_init_print_info(NULL);
 
 #ifdef CONFIG_64BIT
         if ((unsigned long) &_text > (unsigned long) CKSEG0)
@@ -410,16 +399,6 @@ void __init mem_init(void)
                 kclist_add(&kcore_kseg0, (void *) CKSEG0,
                                 0x80000000 - 4, KCORE_TEXT);
 #endif
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
-               "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               ram << (PAGE_SHIFT-10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10,
-               totalhigh_pages << (PAGE_SHIFT-10));
 }
 #endif /* !CONFIG_NEED_MULTIPLE_NODES */
 
@@ -440,7 +419,8 @@ void free_init_pages(const char *what, unsigned long begin, unsigned long end)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index e2e69e1e9fe1..44dd5aa2e36f 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -257,7 +257,9 @@ static int __init bcm1480_pcibios_init(void)
         register_pci_controller(&bcm1480_controller);
 
 #ifdef CONFIG_VGA_CONSOLE
-        take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
+        console_lock();
+        do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
+        console_unlock();
 #endif
         return 0;
 }
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 879077b01155..cb1ef9984069 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -89,7 +89,7 @@ static inline u32 ltq_calc_bar11mask(void)
         u32 mem, bar11mask;
 
         /* BAR11MASK value depends on available memory on system. */
-        mem = num_physpages * PAGE_SIZE;
+        mem = get_num_physpages() * PAGE_SIZE;
         bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
 
         return bar11mask;
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index cdefcc4cb8d4..fc634aeda4a5 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -283,7 +283,9 @@ static int __init sb1250_pcibios_init(void)
         register_pci_controller(&sb1250_controller);
 
 #ifdef CONFIG_VGA_CONSOLE
-        take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
+        console_lock();
+        do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
+        console_unlock();
 #endif
         return 0;
 }
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index 1230f56429d7..a95c00f5fb96 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -357,8 +357,6 @@ static void __init szmem(void)
         int slot;
         cnodeid_t node;
 
-        num_physpages = 0;
-
         for_each_online_node(node) {
                 nodebytes = 0;
                 for (slot = 0; slot < MAX_MEM_SLOTS; slot++) {
@@ -381,7 +379,6 @@ static void __init szmem(void)
                                 slot = MAX_MEM_SLOTS;
                                 continue;
                         }
-                        num_physpages += slot_psize;
                         memblock_add_node(PFN_PHYS(slot_getbasepfn(node, slot)),
                                           PFN_PHYS(slot_psize), node);
                 }
@@ -480,32 +477,8 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        unsigned long codesize, datasize, initsize, tmp;
-        unsigned node;
-
-        high_memory = (void *) __va(num_physpages << PAGE_SHIFT);
-
-        for_each_online_node(node) {
-                /*
-                 * This will free up the bootmem, ie, slot 0 memory.
-                 */
-                totalram_pages += free_all_bootmem_node(NODE_DATA(node));
-        }
-
+        high_memory = (void *) __va(get_num_physpages() << PAGE_SHIFT);
+        free_all_bootmem();
         setup_zero_pages();     /* This comes from node 0 */
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        tmp = nr_free_pages();
-        printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
-               "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
-               tmp << (PAGE_SHIFT-10),
-               num_physpages << (PAGE_SHIFT-10),
-               codesize >> 10,
-               (num_physpages - tmp) << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10,
-               totalhigh_pages << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
 }
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 428da175d073..70e4f663ebd2 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -13,6 +13,7 @@ config MN10300
         select MODULES_USE_ELF_RELA
         select OLD_SIGSUSPEND3
         select OLD_SIGACTION
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config AM33_2
         def_bool n
diff --git a/arch/mn10300/Kconfig.debug b/arch/mn10300/Kconfig.debug
index bdbfd444a9ff..94efb3ed223f 100644
--- a/arch/mn10300/Kconfig.debug
+++ b/arch/mn10300/Kconfig.debug
@@ -2,10 +2,6 @@ menu "Kernel hacking"
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-
 config DEBUG_DECOMPRESS_KERNEL
         bool "Using serial port during decompressing kernel"
         depends on DEBUG_KERNEL
diff --git a/arch/mn10300/include/asm/irqflags.h b/arch/mn10300/include/asm/irqflags.h
index 678f68d5f37b..8730c0a3c37d 100644
--- a/arch/mn10300/include/asm/irqflags.h
+++ b/arch/mn10300/include/asm/irqflags.h
@@ -13,9 +13,8 @@
 #define _ASM_IRQFLAGS_H
 
 #include <asm/cpu-regs.h>
-#ifndef __ASSEMBLY__
-#include <linux/smp.h>
-#endif
+/* linux/smp.h <- linux/irqflags.h needs asm/smp.h first */
+#include <asm/smp.h>
 
 /*
  * interrupt control
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index a1e894b5f65b..2ddaa67e7983 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -486,9 +486,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma,
 
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
-        remap_pfn_range((vma), (vaddr), (pfn), (size), (prot))
-
 #define MK_IOSPACE_PFN(space, pfn)      (pfn)
 #define GET_IOSPACE(pfn)                0
 #define GET_PFN(pfn)                    (pfn)
diff --git a/arch/mn10300/include/asm/smp.h b/arch/mn10300/include/asm/smp.h
index 6745dbe64944..56c42417d428 100644
--- a/arch/mn10300/include/asm/smp.h
+++ b/arch/mn10300/include/asm/smp.h
@@ -24,6 +24,7 @@
 #ifndef __ASSEMBLY__
 #include <linux/threads.h>
 #include <linux/cpumask.h>
+#include <linux/thread_info.h>
 #endif
 
 #ifdef CONFIG_SMP
@@ -85,7 +86,7 @@ extern cpumask_t cpu_boot_map;
 extern void smp_init_cpus(void);
 extern void smp_cache_interrupt(void);
 extern void send_IPI_allbutself(int irq);
-extern int smp_nmi_call_function(smp_call_func_t func, void *info, int wait);
+extern int smp_nmi_call_function(void (*func)(void *), void *info, int wait);
 
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
@@ -100,6 +101,7 @@ extern void __cpu_die(unsigned int cpu);
 #ifndef __ASSEMBLY__
 
 static inline void smp_init_cpus(void) {}
+#define raw_smp_processor_id() 0
 
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_SMP */
diff --git a/arch/mn10300/include/asm/uaccess.h b/arch/mn10300/include/asm/uaccess.h
index 780560b330d9..537278746a15 100644
--- a/arch/mn10300/include/asm/uaccess.h
+++ b/arch/mn10300/include/asm/uaccess.h
@@ -161,7 +161,7 @@ struct __large_struct { unsigned long buf[100]; };
 
 #define __get_user_check(x, ptr, size)                                  \
 ({                                                                      \
-        const __typeof__(ptr) __guc_ptr = (ptr);                        \
+        const __typeof__(*(ptr))* __guc_ptr = (ptr);                    \
         int _e;                                                         \
         if (likely(__access_ok((unsigned long) __guc_ptr, (size))))     \
                 _e = __get_user_nocheck((x), __guc_ptr, (size));        \
@@ -471,13 +471,13 @@ extern unsigned long __generic_copy_from_user(void *, const void __user *,
 
 #define __copy_to_user(to, from, n)                     \
 ({                                                      \
-        might_sleep();                                  \
+        might_fault();                                  \
         __copy_to_user_inatomic((to), (from), (n));     \
 })
 
 #define __copy_from_user(to, from, n)                   \
 ({                                                      \
-        might_sleep();                                  \
+        might_fault();                                  \
         __copy_from_user_inatomic((to), (from), (n));   \
 })
 
diff --git a/arch/mn10300/kernel/setup.c b/arch/mn10300/kernel/setup.c
index 33c3bd1e5c6d..ebac9c11f796 100644
--- a/arch/mn10300/kernel/setup.c
+++ b/arch/mn10300/kernel/setup.c
@@ -38,6 +38,7 @@ struct mn10300_cpuinfo boot_cpu_data;
 /* For PCI or other memory-mapped resources */
 unsigned long pci_mem_start = 0x18000000;
 
+static char __initdata cmd_line[COMMAND_LINE_SIZE];
 char redboot_command_line[COMMAND_LINE_SIZE] =
         "console=ttyS0,115200 root=/dev/mtdblock3 rw";
 
@@ -74,45 +75,19 @@ static const char *const mn10300_cputypes[] = {
 };
 
 /*
- *
+ * Pick out the memory size.  We look for mem=size,
+ * where size is "size[KkMm]"
  */
-static void __init parse_mem_cmdline(char **cmdline_p)
+static int __init early_mem(char *p)
 {
-        char *from, *to, c;
-
-        /* save unparsed command line copy for /proc/cmdline */
-        strcpy(boot_command_line, redboot_command_line);
-
-        /* see if there's an explicit memory size option */
-        from = redboot_command_line;
-        to = redboot_command_line;
-        c = ' ';
-
-        for (;;) {
-                if (c == ' ' && !memcmp(from, "mem=", 4)) {
-                        if (to != redboot_command_line)
-                                to--;
-                        memory_size = memparse(from + 4, &from);
-                }
-
-                c = *(from++);
-                if (!c)
-                        break;
-
-                *(to++) = c;
-        }
-
-        *to = '\0';
-        *cmdline_p = redboot_command_line;
+        memory_size = memparse(p, &p);
 
         if (memory_size == 0)
                 panic("Memory size not known\n");
 
-        memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS +
-                memory_size;
-        if (memory_end > phys_memory_end)
-                memory_end = phys_memory_end;
+        return 0;
 }
+early_param("mem", early_mem);
 
 /*
  * architecture specific setup
@@ -125,7 +100,20 @@ void __init setup_arch(char **cmdline_p)
         cpu_init();
         unit_setup();
         smp_init_cpus();
-        parse_mem_cmdline(cmdline_p);
+
+        /* save unparsed command line copy for /proc/cmdline */
+        strlcpy(boot_command_line, redboot_command_line, COMMAND_LINE_SIZE);
+
+        /* populate cmd_line too for later use, preserving boot_command_line */
+        strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
+        *cmdline_p = cmd_line;
+
+        parse_early_param();
+
+        memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS +
+                memory_size;
+        if (memory_end > phys_memory_end)
+                memory_end = phys_memory_end;
 
         init_mm.start_code = (unsigned long)&_text;
         init_mm.end_code = (unsigned long) &_etext;
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 5a8ace63a6b4..97a1ec0beeec 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -99,43 +99,21 @@ void __init paging_init(void)
  */
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-        int tmp;
-
         BUG_ON(!mem_map);
 
 #define START_PFN       (contig_page_data.bdata->node_min_pfn)
 #define MAX_LOW_PFN     (contig_page_data.bdata->node_low_pfn)
 
-        max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
+        max_mapnr = MAX_LOW_PFN - START_PFN;
         high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
 
         /* clear the zero-page */
         memset(empty_zero_page, 0, PAGE_SIZE);
 
         /* this will put all low memory onto the freelists */
-        totalram_pages += free_all_bootmem();
-
-        reservedpages = 0;
-        for (tmp = 0; tmp < num_physpages; tmp++)
-                if (PageReserved(&mem_map[tmp]))
-                        reservedpages++;
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_stext;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk(KERN_INFO
-               "Memory: %luk/%luk available"
-               " (%dk kernel code, %dk reserved, %dk data, %dk init,"
-               " %ldk highmem)\n",
-               nr_free_pages() << (PAGE_SHIFT - 10),
-               max_mapnr << (PAGE_SHIFT - 10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT - 10),
-               datasize >> 10,
-               initsize >> 10,
-               totalhigh_pages << (PAGE_SHIFT - 10));
+        free_all_bootmem();
+
+        mem_init_print_info(NULL);
 }
 
 /*
@@ -152,6 +130,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c
index c4e2e79281e8..febb9cd83177 100644
--- a/arch/mn10300/unit-asb2305/pci-asb2305.c
+++ b/arch/mn10300/unit-asb2305/pci-asb2305.c
@@ -221,7 +221,7 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
         /* Leave vm_pgoff as-is, the PCI space address is the physical
          * address on this platform.
          */
-        vma->vm_flags |= VM_LOCKED | VM_IO;
+        vma->vm_flags |= VM_LOCKED;
 
         prot = pgprot_val(vma->vm_page_prot);
         prot &= ~_PAGE_CACHE;
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 1072bfd18c50..99dbab1c59ac 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -22,6 +22,7 @@ config OPENRISC
         select GENERIC_STRNCPY_FROM_USER
         select GENERIC_STRNLEN_USER
         select MODULES_USE_ELF_RELA
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config MMU
         def_bool y
@@ -128,16 +129,6 @@ config CMDLINE
 
 menu "Debugging options"
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for kernel stack overflow"
-        default y
-        help
-          Make extra checks for space available on stack in some
-          critical functions. This will cause kernel to run a bit slower,
-          but will catch most of kernel stack overruns and exit gracefully.
-
-          Say Y if you are unsure.
-
 config JUMP_UPON_UNHANDLED_EXCEPTION
         bool "Try to die gracefully"
         default y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index f20d01d9aaf9..195653e851da 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -66,3 +66,4 @@ generic-y += types.h
 generic-y += ucontext.h
 generic-y += user.h
 generic-y += word-at-a-time.h
+generic-y += xor.h
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 14c900cfd30a..37bf6a3ef8f4 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -446,9 +446,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 
 #define kern_addr_valid(addr)           (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #include <asm-generic/pgtable.h>
 
 /*
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index b3cbc6703837..7f94652311d7 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -202,56 +202,20 @@ void __init paging_init(void)
 
 /* References to section boundaries */
 
-static int __init free_pages_init(void)
-{
-        int reservedpages, pfn;
-
-        /* this will put all low memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-        reservedpages = 0;
-        for (pfn = 0; pfn < max_low_pfn; pfn++) {
-                /*
-                 * Only count reserved RAM pages
-                 */
-                if (PageReserved(mem_map + pfn))
-                        reservedpages++;
-        }
-
-        return reservedpages;
-}
-
-static void __init set_max_mapnr_init(void)
-{
-        max_mapnr = num_physpages = max_low_pfn;
-}
-
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-
         BUG_ON(!mem_map);
 
-        set_max_mapnr_init();
-
+        max_mapnr = max_low_pfn;
         high_memory = (void *)__va(max_low_pfn * PAGE_SIZE);
 
         /* clear the zero-page */
         memset((void *)empty_zero_page, 0, PAGE_SIZE);
 
-        reservedpages = free_pages_init();
-
-        codesize = (unsigned long)&_etext - (unsigned long)&_stext;
-        datasize = (unsigned long)&_edata - (unsigned long)&_etext;
-        initsize = (unsigned long)&__init_end - (unsigned long)&__init_begin;
+        /* this will put all low memory onto the freelists */
+        free_all_bootmem();
 
-        printk(KERN_INFO
-               "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init, %ldk highmem)\n",
-               (unsigned long)nr_free_pages() << (PAGE_SHIFT - 10),
-               max_mapnr << (PAGE_SHIFT - 10), codesize >> 10,
-               reservedpages << (PAGE_SHIFT - 10), datasize >> 10,
-               initsize >> 10, (unsigned long)(0 << (PAGE_SHIFT - 10))
-            );
+        mem_init_print_info(NULL);
 
         printk("mem_init_done ...........................................\n");
         mem_init_done = 1;
@@ -261,11 +225,11 @@ void __init mem_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 6507dabdd5dd..aa399a5259b6 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -27,6 +27,7 @@ config PARISC
         select MODULES_USE_ELF_RELA
         select CLONE_BACKWARDS
         select TTY # Needed for pdc_cons.c
+        select HAVE_DEBUG_STACKOVERFLOW
 
         help
           The PA-RISC microprocessor is designed by Hewlett-Packard and used
@@ -254,7 +255,6 @@ config IRQSTACKS
 config HOTPLUG_CPU
         bool
         default y if SMP
-        select HOTPLUG
 
 config ARCH_SELECT_MEMORY_MODEL
         def_bool y
diff --git a/arch/parisc/Kconfig.debug b/arch/parisc/Kconfig.debug
index 08a332f6ee87..bc989e522a04 100644
--- a/arch/parisc/Kconfig.debug
+++ b/arch/parisc/Kconfig.debug
@@ -13,14 +13,3 @@ config DEBUG_RODATA
          If in doubt, say "N".
 
 endmenu
-
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        default y
-        depends on DEBUG_KERNEL
-        ---help---
-          Say Y here if you want to check the overflows of kernel, IRQ
-          and exception stacks. This option will cause messages of the
-          stacks in detail when free stack space drops below a certain
-          limit.
-          If in doubt, say "N".
diff --git a/arch/parisc/hpux/fs.c b/arch/parisc/hpux/fs.c
index 838b479a42c4..88d0962de65a 100644
--- a/arch/parisc/hpux/fs.c
+++ b/arch/parisc/hpux/fs.c
@@ -60,6 +60,7 @@ struct hpux_dirent {
 };
 
 struct getdents_callback {
+        struct dir_context ctx;
         struct hpux_dirent __user *current_dir;
         struct hpux_dirent __user *previous;
         int count;
@@ -110,24 +111,23 @@ int hpux_getdents(unsigned int fd, struct hpux_dirent __user *dirent, unsigned i
 {
         struct fd arg;
         struct hpux_dirent __user * lastdirent;
-        struct getdents_callback buf;
+        struct getdents_callback buf = {
+                .ctx.actor = filldir,
+                .current_dir = dirent,
+                .count = count
+        };
         int error;
 
         arg = fdget(fd);
         if (!arg.file)
                 return -EBADF;
 
-        buf.current_dir = dirent;
-        buf.previous = NULL;
-        buf.count = count;
-        buf.error = 0;
-
-        error = vfs_readdir(arg.file, filldir, &buf);
+        error = iterate_dir(arg.file, &buf.ctx);
         if (error >= 0)
                 error = buf.error;
         lastdirent = buf.previous;
         if (lastdirent) {
-                if (put_user(arg.file->f_pos, &lastdirent->d_off))
+                if (put_user(buf.ctx.pos, &lastdirent->d_off))
                         error = -EFAULT;
                 else
                         error = count - buf.count;
diff --git a/arch/parisc/include/asm/mmzone.h b/arch/parisc/include/asm/mmzone.h
index cc50d33b7b88..b6b34a0987e7 100644
--- a/arch/parisc/include/asm/mmzone.h
+++ b/arch/parisc/include/asm/mmzone.h
@@ -27,7 +27,7 @@ extern struct node_map_data node_data[];
 
 #define PFNNID_SHIFT (30 - PAGE_SHIFT)
 #define PFNNID_MAP_MAX  512     /* support 512GB */
-extern unsigned char pfnnid_map[PFNNID_MAP_MAX];
+extern signed char pfnnid_map[PFNNID_MAP_MAX];
 
 #ifndef CONFIG_64BIT
 #define pfn_is_io(pfn) ((pfn & (0xf0000000UL >> PAGE_SHIFT)) == (0xf0000000UL >> PAGE_SHIFT))
@@ -46,7 +46,7 @@ static inline int pfn_to_nid(unsigned long pfn)
         i = pfn >> PFNNID_SHIFT;
         BUG_ON(i >= ARRAY_SIZE(pfnnid_map));
 
-        return (int)pfnnid_map[i];
+        return pfnnid_map[i];
 }
 
 static inline int pfn_valid(int pfn)
diff --git a/arch/parisc/include/asm/pci.h b/arch/parisc/include/asm/pci.h
index 3234f492d575..465154076d23 100644
--- a/arch/parisc/include/asm/pci.h
+++ b/arch/parisc/include/asm/pci.h
@@ -225,4 +225,9 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
         return channel ? 15 : 14;
 }
 
+#define HAVE_PCI_MMAP
+
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+        enum pci_mmap_state mmap_state, int write_combine);
+
 #endif /* __ASM_PARISC_PCI_H */
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 1e40d7f86be3..34899b5d959a 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -506,9 +506,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 #endif
 
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
 
 /* We provide our own get_unmapped_area to provide cache coherency */
diff --git a/arch/parisc/include/uapi/asm/fcntl.h b/arch/parisc/include/uapi/asm/fcntl.h
index 0304b92ccfea..cc61c475f277 100644
--- a/arch/parisc/include/uapi/asm/fcntl.h
+++ b/arch/parisc/include/uapi/asm/fcntl.h
@@ -20,6 +20,7 @@
 #define O_INVISIBLE     004000000 /* invisible I/O, for DMAPI/XDSM */
 
 #define O_PATH          020000000
+#define O_TMPFILE       040000000
 
 #define F_GETLK64       8
 #define F_SETLK64       9
diff --git a/arch/parisc/kernel/hardware.c b/arch/parisc/kernel/hardware.c
index 9e2d2e408529..872275659d98 100644
--- a/arch/parisc/kernel/hardware.c
+++ b/arch/parisc/kernel/hardware.c
@@ -1205,6 +1205,7 @@ static struct hp_hardware hp_hardware_list[] = {
         {HPHW_FIO, 0x004, 0x00320, 0x0, "Metheus Frame Buffer"}, 
         {HPHW_FIO, 0x004, 0x00340, 0x0, "BARCO CX4500 VME Grphx Cnsl"}, 
         {HPHW_FIO, 0x004, 0x00360, 0x0, "Hughes TOG VME FDDI"}, 
+        {HPHW_FIO, 0x076, 0x000AD, 0x00, "Crestone Peak RS-232"},
         {HPHW_IOA, 0x185, 0x0000B, 0x00, "Java BC Summit Port"}, 
         {HPHW_IOA, 0x1FF, 0x0000B, 0x00, "Hitachi Ghostview Summit Port"}, 
         {HPHW_IOA, 0x580, 0x0000B, 0x10, "U2-IOA BC Runway Port"}, 
diff --git a/arch/parisc/kernel/pacache.S b/arch/parisc/kernel/pacache.S
index 36d7f402e48e..b743a80eaba0 100644
--- a/arch/parisc/kernel/pacache.S
+++ b/arch/parisc/kernel/pacache.S
@@ -860,7 +860,7 @@ ENTRY(flush_dcache_page_asm)
 #endif
 
         ldil            L%dcache_stride, %r1
-        ldw             R%dcache_stride(%r1), %r1
+        ldw             R%dcache_stride(%r1), r31
 
 #ifdef CONFIG_64BIT
         depdi,z         1, 63-PAGE_SHIFT,1, %r25
@@ -868,26 +868,26 @@ ENTRY(flush_dcache_page_asm)
         depwi,z         1, 31-PAGE_SHIFT,1, %r25
 #endif
         add             %r28, %r25, %r25
-        sub             %r25, %r1, %r25
-
-
-1:      fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
-        fdc,m           %r1(%r28)
+        sub             %r25, r31, %r25
+
+
+1:      fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
+        fdc,m           r31(%r28)
         cmpb,COND(<<)           %r28, %r25,1b
-        fdc,m           %r1(%r28)
+        fdc,m           r31(%r28)
 
         sync
 
@@ -936,7 +936,7 @@ ENTRY(flush_icache_page_asm)
 #endif
 
         ldil            L%icache_stride, %r1
-        ldw             R%icache_stride(%r1), %r1
+        ldw             R%icache_stride(%r1), %r31
 
 #ifdef CONFIG_64BIT
         depdi,z         1, 63-PAGE_SHIFT,1, %r25
@@ -944,28 +944,28 @@ ENTRY(flush_icache_page_asm)
         depwi,z         1, 31-PAGE_SHIFT,1, %r25
 #endif
         add             %r28, %r25, %r25
-        sub             %r25, %r1, %r25
+        sub             %r25, %r31, %r25
 
 
         /* fic only has the type 26 form on PA1.1, requiring an
          * explicit space specification, so use %sr4 */
-1:      fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
-        fic,m           %r1(%sr4,%r28)
+1:      fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
         cmpb,COND(<<)   %r28, %r25,1b
-        fic,m           %r1(%sr4,%r28)
+        fic,m           %r31(%sr4,%r28)
 
         sync
 
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index 60309051875e..64f2764a8cef 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -220,6 +220,33 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 }
 
 
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+                        enum pci_mmap_state mmap_state, int write_combine)
+{
+        unsigned long prot;
+
+        /*
+         * I/O space can be accessed via normal processor loads and stores on
+         * this platform but for now we elect not to do this and portable
+         * drivers should not do this anyway.
+         */
+        if (mmap_state == pci_mmap_io)
+                return -EINVAL;
+
+        if (write_combine)
+                return -EINVAL;
+
+        /*
+         * Ignore write-combine; for now only return uncached mappings.
+         */
+        prot = pgprot_val(vma->vm_page_prot);
+        prot |= _PAGE_NO_CACHE;
+        vma->vm_page_prot = __pgprot(prot);
+
+        return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+                vma->vm_end - vma->vm_start, vma->vm_page_prot);
+}
+
 /*
  * A driver is enabling the device.  We make sure that all the appropriate
  * bits are set to allow the device to operate as the driver is expecting.
diff --git a/arch/parisc/kernel/setup.c b/arch/parisc/kernel/setup.c
index 1e95b2000ce8..7349a3fedfc7 100644
--- a/arch/parisc/kernel/setup.c
+++ b/arch/parisc/kernel/setup.c
@@ -156,7 +156,7 @@ void __init setup_arch(char **cmdline_p)
 #endif
 
 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
-        conswitchp = &dummy_con;        /* we use take_over_console() later ! */
+        conswitchp = &dummy_con;        /* we use do_take_over_console() later ! */
 #endif
 
 }
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 1c965642068b..b0f96c0e6316 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -47,7 +47,7 @@ pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data..vm0.pt
 
 #ifdef CONFIG_DISCONTIGMEM
 struct node_map_data node_data[MAX_NUMNODES] __read_mostly;
-unsigned char pfnnid_map[PFNNID_MAP_MAX] __read_mostly;
+signed char pfnnid_map[PFNNID_MAP_MAX] __read_mostly;
 #endif
 
 static struct resource data_resource = {
@@ -214,7 +214,6 @@ static void __init setup_bootmem(void)
         mem_limit_func();       /* check for "mem=" argument */
 
         mem_max = 0;
-        num_physpages = 0;
         for (i = 0; i < npmem_ranges; i++) {
                 unsigned long rsize;
 
@@ -229,10 +228,8 @@ static void __init setup_bootmem(void)
                                 npmem_ranges = i + 1;
                                 mem_max = mem_limit;
                         }
-                num_physpages += pmem_ranges[i].pages;
                         break;
                 }
-            num_physpages += pmem_ranges[i].pages;
                 mem_max += rsize;
         }
 
@@ -532,7 +529,7 @@ void free_initmem(void)
          * pages are no-longer executable */
         flush_icache_range(init_begin, init_end);
         
-        num_physpages += free_initmem_default(0);
+        free_initmem_default(-1);
 
         /* set up a new led state on systems shipped LED State panel */
         pdc_chassis_send_status(PDC_CHASSIS_DIRECT_BCOMPLETE);
@@ -580,8 +577,6 @@ unsigned long pcxl_dma_start __read_mostly;
 
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-
         /* Do sanity checks on page table constants */
         BUILD_BUG_ON(PTE_ENTRY_SIZE != sizeof(pte_t));
         BUILD_BUG_ON(PMD_ENTRY_SIZE != sizeof(pmd_t));
@@ -590,45 +585,8 @@ void __init mem_init(void)
                         > BITS_PER_LONG);
 
         high_memory = __va((max_pfn << PAGE_SHIFT));
-
-#ifndef CONFIG_DISCONTIGMEM
-        max_mapnr = page_to_pfn(virt_to_page(high_memory - 1)) + 1;
-        totalram_pages += free_all_bootmem();
-#else
-        {
-                int i;
-
-                for (i = 0; i < npmem_ranges; i++)
-                        totalram_pages += free_all_bootmem_node(NODE_DATA(i));
-        }
-#endif
-
-        codesize = (unsigned long)_etext - (unsigned long)_text;
-        datasize = (unsigned long)_edata - (unsigned long)_etext;
-        initsize = (unsigned long)__init_end - (unsigned long)__init_begin;
-
-        reservedpages = 0;
-{
-        unsigned long pfn;
-#ifdef CONFIG_DISCONTIGMEM
-        int i;
-
-        for (i = 0; i < npmem_ranges; i++) {
-                for (pfn = node_start_pfn(i); pfn < node_end_pfn(i); pfn++) {
-                        if (PageReserved(pfn_to_page(pfn)))
-                                reservedpages++;
-                }
-        }
-#else /* !CONFIG_DISCONTIGMEM */
-        for (pfn = 0; pfn < max_pfn; pfn++) {
-                /*
-                 * Only count reserved RAM pages
-                 */
-                if (PageReserved(pfn_to_page(pfn)))
-                        reservedpages++;
-        }
-#endif
-}
+        set_max_mapnr(page_to_pfn(virt_to_page(high_memory - 1)) + 1);
+        free_all_bootmem();
 
 #ifdef CONFIG_PA11
         if (hppa_dma_ops == &pcxl_dma_ops) {
@@ -643,15 +601,7 @@ void __init mem_init(void)
         parisc_vmalloc_start = SET_MAP_OFFSET(MAP_START);
 #endif
 
-        printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                initsize >> 10
-        );
-
+        mem_init_print_info(NULL);
 #ifdef CONFIG_DEBUG_KERNEL /* double-sanity-check paranoia */
         printk("virtual kernel memory layout:\n"
                "    vmalloc : 0x%p - 0x%p   (%4ld MB)\n"
@@ -1101,6 +1051,6 @@ void flush_tlb_all(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        num_physpages += free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index c33e3ad2c8fd..bc3a0ebf16a7 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -138,6 +138,7 @@ config PPC
         select ARCH_USE_BUILTIN_BSWAP
         select OLD_SIGSUSPEND
         select OLD_SIGACTION if PPC32
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config EARLY_PRINTK
         bool
@@ -298,7 +299,7 @@ config HUGETLB_PAGE_SIZE_VARIABLE
 
 config MATH_EMULATION
         bool "Math emulation"
-        depends on 4xx || 8xx || E200 || PPC_MPC832x || E500
+        depends on 4xx || 8xx || PPC_MPC832x || BOOKE
         ---help---
           Some PowerPC chips designed for embedded applications do not have
           a floating-point unit and therefore do not implement the
@@ -307,6 +308,10 @@ config MATH_EMULATION
           unit, which will allow programs that use floating-point
           instructions to run.
 
+          This is also useful to emulate missing (optional) instructions
+          such as fsqrt on cores that do have an FPU but do not implement
+          them (such as Freescale BookE).
+
 config PPC_TRANSACTIONAL_MEM
        bool "Transactional Memory support for POWERPC"
        depends on PPC_BOOK3S_64
@@ -315,17 +320,6 @@ config PPC_TRANSACTIONAL_MEM
        ---help---
          Support user-mode Transactional Memory on POWERPC.
 
-config 8XX_MINIMAL_FPEMU
-        bool "Minimal math emulation for 8xx"
-        depends on 8xx && !MATH_EMULATION
-        help
-          Older arch/ppc kernels still emulated a few floating point
-          instructions such as load and store, even when full math
-          emulation is disabled.  Say "Y" here if you want to preserve
-          this behavior.
-
-          It is recommended that you build a soft-float userspace instead.
-
 config IOMMU_HELPER
         def_bool PPC64
 
@@ -341,7 +335,7 @@ config SWIOTLB
 
 config HOTPLUG_CPU
         bool "Support for enabling/disabling CPUs"
-        depends on SMP && HOTPLUG && (PPC_PSERIES || \
+        depends on SMP && (PPC_PSERIES || \
         PPC_PMAC || PPC_POWERNV || (PPC_85xx && !PPC_E500MC))
         ---help---
           Say Y here to be able to disable and re-enable individual
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index 863d877e0b5f..21c9f304e96c 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -28,13 +28,6 @@ config PRINT_STACK_DEPTH
           too small and stack traces cause important information to
           scroll off the screen.
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config HCALL_STATS
         bool "Hypervisor call instrumentation"
         depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS
@@ -147,6 +140,13 @@ choice
           enable debugging for the wrong type of machine your kernel
           _will not boot_.
 
+config PPC_EARLY_DEBUG_BOOTX
+        bool "BootX or OpenFirmware"
+        depends on BOOTX_TEXT
+        help
+          Select this to enable early debugging for a machine using BootX
+          or OpenFirmware.
+
 config PPC_EARLY_DEBUG_LPAR
         bool "LPAR HV Console"
         depends on PPC_PSERIES
diff --git a/arch/powerpc/boot/dts/currituck.dts b/arch/powerpc/boot/dts/currituck.dts
index b801dd06e573..d2c8a872308e 100644
--- a/arch/powerpc/boot/dts/currituck.dts
+++ b/arch/powerpc/boot/dts/currituck.dts
@@ -103,6 +103,11 @@
                                 interrupts = <34 2>;
                         };
 
+                        FPGA0: fpga@50000000 {
+                                compatible = "ibm,currituck-fpga";
+                                reg = <0x50000000 0x4>;
+                        };
+
                         IIC0: i2c@00000000 {
                                 compatible = "ibm,iic-currituck", "ibm,iic";
                                 reg = <0x0 0x00000014>;
diff --git a/arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi b/arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
new file mode 100644
index 000000000000..9cffccf4e07e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/interlaken-lac-portals.dtsi
@@ -0,0 +1,156 @@
+/* T4240 Interlaken LAC Portal device tree stub with 24 portals.
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#address-cells = <0x1>;
+#size-cells = <0x1>;
+compatible = "fsl,interlaken-lac-portals";
+
+lportal0: lac-portal@0 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x0 0x1000>;
+};
+
+lportal1: lac-portal@1000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x1000 0x1000>;
+};
+
+lportal2: lac-portal@2000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x2000 0x1000>;
+};
+
+lportal3: lac-portal@3000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x3000 0x1000>;
+};
+
+lportal4: lac-portal@4000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x4000 0x1000>;
+};
+
+lportal5: lac-portal@5000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x5000 0x1000>;
+};
+
+lportal6: lac-portal@6000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x6000 0x1000>;
+};
+
+lportal7: lac-portal@7000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x7000 0x1000>;
+};
+
+lportal8: lac-portal@8000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x8000 0x1000>;
+};
+
+lportal9: lac-portal@9000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x9000 0x1000>;
+};
+
+lportal10: lac-portal@A000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xA000 0x1000>;
+};
+
+lportal11: lac-portal@B000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xB000 0x1000>;
+};
+
+lportal12: lac-portal@C000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xC000 0x1000>;
+};
+
+lportal13: lac-portal@D000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xD000 0x1000>;
+};
+
+lportal14: lac-portal@E000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xE000 0x1000>;
+};
+
+lportal15: lac-portal@F000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0xF000 0x1000>;
+};
+
+lportal16: lac-portal@10000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x10000 0x1000>;
+};
+
+lportal17: lac-portal@11000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x11000 0x1000>;
+};
+
+lportal18: lac-portal@1200 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x12000 0x1000>;
+};
+
+lportal19: lac-portal@13000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x13000 0x1000>;
+};
+
+lportal20: lac-portal@14000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x14000 0x1000>;
+};
+
+lportal21: lac-portal@15000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x15000 0x1000>;
+};
+
+lportal22: lac-portal@16000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x16000 0x1000>;
+};
+
+lportal23: lac-portal@17000 {
+        compatible = "fsl,interlaken-lac-portal-v1.0";
+        reg = <0x17000 0x1000>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi b/arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
new file mode 100644
index 000000000000..e8208720ac0e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/interlaken-lac.dtsi
@@ -0,0 +1,45 @@
+/*
+ * T4 Interlaken Look-aside Controller (LAC) device tree stub
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+lac: lac@229000 {
+        compatible = "fsl,interlaken-lac";
+        reg = <0x229000 0x1000>;
+        interrupts = <16 2 1 18>;
+};
+
+lac-hv@228000 {
+        compatible = "fsl,interlaken-lac-hv";
+        reg = <0x228000 0x1000>;
+        fsl,non-hv-node = <&lac>;
+};
diff --git a/arch/powerpc/configs/c2k_defconfig b/arch/powerpc/configs/c2k_defconfig
index 2a84fd7f631c..671a8f960afa 100644
--- a/arch/powerpc/configs/c2k_defconfig
+++ b/arch/powerpc/configs/c2k_defconfig
@@ -423,6 +423,8 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_DEBUG_STACKOVERFLOW=y
 CONFIG_DEBUG_STACK_USAGE=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 CONFIG_SECURITY=y
diff --git a/arch/powerpc/configs/g5_defconfig b/arch/powerpc/configs/g5_defconfig
index 07b7f2af2dca..1ea22fc24ea8 100644
--- a/arch/powerpc/configs/g5_defconfig
+++ b/arch/powerpc/configs/g5_defconfig
@@ -284,6 +284,8 @@ CONFIG_DEBUG_MUTEXES=y
 CONFIG_LATENCYTOP=y
 CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_ECB=m
diff --git a/arch/powerpc/configs/maple_defconfig b/arch/powerpc/configs/maple_defconfig
index 02ac96b679b8..2a5afac29861 100644
--- a/arch/powerpc/configs/maple_defconfig
+++ b/arch/powerpc/configs/maple_defconfig
@@ -138,6 +138,8 @@ CONFIG_DEBUG_STACK_USAGE=y
 CONFIG_XMON=y
 CONFIG_XMON_DEFAULT=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig
index 0d0d981442fd..ee853a1b1b2c 100644
--- a/arch/powerpc/configs/mpc512x_defconfig
+++ b/arch/powerpc/configs/mpc512x_defconfig
@@ -1,7 +1,6 @@
-CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
-CONFIG_SPARSE_IRQ=y
+CONFIG_NO_HZ=y
 CONFIG_LOG_BUF_SHIFT=16
 CONFIG_BLK_DEV_INITRD=y
 # CONFIG_COMPAT_BRK is not set
@@ -9,6 +8,7 @@ CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_CFQ is not set
 # CONFIG_PPC_CHRP is not set
 CONFIG_PPC_MPC512x=y
@@ -16,9 +16,7 @@ CONFIG_MPC5121_ADS=y
 CONFIG_MPC512x_GENERIC=y
 CONFIG_PDM360NG=y
 # CONFIG_PPC_PMAC is not set
-CONFIG_NO_HZ=y
 CONFIG_HZ_1000=y
-# CONFIG_MIGRATION is not set
 # CONFIG_SECCOMP is not set
 # CONFIG_PCI is not set
 CONFIG_NET=y
@@ -33,8 +31,6 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_DIAG is not set
 # CONFIG_IPV6 is not set
 CONFIG_CAN=y
-CONFIG_CAN_RAW=y
-CONFIG_CAN_BCM=y
 CONFIG_CAN_VCAN=y
 CONFIG_CAN_MSCAN=y
 CONFIG_CAN_DEBUG_DEVICES=y
@@ -46,7 +42,6 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
@@ -60,7 +55,6 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=8192
 CONFIG_BLK_DEV_XIP=y
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
@@ -68,6 +62,7 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_NETDEVICES=y
+CONFIG_FS_ENET=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_QSEMI_PHY=y
@@ -83,10 +78,6 @@ CONFIG_STE10XP=y
 CONFIG_LSI_ET1011C_PHY=y
 CONFIG_FIXED_PHY=y
 CONFIG_MDIO_BITBANG=y
-CONFIG_NET_ETHERNET=y
-CONFIG_FS_ENET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
 # CONFIG_WLAN is not set
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_EVDEV=y
@@ -106,14 +97,18 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
 CONFIG_VIDEO_ADV_DEBUG=y
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_VIDEO_SAA711X=y
 CONFIG_FB=y
 CONFIG_FB_FSL_DIU=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+# CONFIG_USB_EHCI_HCD_PPC_OF is not set
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_FSL_USB2=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_M41T80=y
 CONFIG_RTC_DRV_MPC5121=y
@@ -129,9 +124,7 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 165e6b32baef..152fa05b15e4 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -131,6 +131,7 @@ CONFIG_DUMMY=y
 CONFIG_FS_ENET=y
 CONFIG_UCC_GETH=y
 CONFIG_GIANFAR=y
+CONFIG_E1000E=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_CICADA_PHY=y
diff --git a/arch/powerpc/configs/pmac32_defconfig b/arch/powerpc/configs/pmac32_defconfig
index 29767a8dfea5..a73626b09051 100644
--- a/arch/powerpc/configs/pmac32_defconfig
+++ b/arch/powerpc/configs/pmac32_defconfig
@@ -350,6 +350,8 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_XMON=y
 CONFIG_XMON_DEFAULT=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD4=m
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index aef3f71de5ad..c86fcb92358e 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -398,6 +398,8 @@ CONFIG_FTR_FIXUP_SELFTEST=y
 CONFIG_MSI_BITMAP_SELFTEST=y
 CONFIG_XMON=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index be1cb6ea3a36..20ebfaf7234b 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -1264,6 +1264,8 @@ CONFIG_DEBUG_STACKOVERFLOW=y
 CONFIG_DEBUG_STACK_USAGE=y
 CONFIG_XMON=y
 CONFIG_BOOTX_TEXT=y
+CONFIG_PPC_EARLY_DEBUG=y
+CONFIG_PPC_EARLY_DEBUG_BOOTX=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 CONFIG_SECURITY=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index c4dfbaf8b192..bea8587c3af5 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -296,6 +296,7 @@ CONFIG_SQUASHFS=m
 CONFIG_SQUASHFS_XATTR=y
 CONFIG_SQUASHFS_LZO=y
 CONFIG_SQUASHFS_XZ=y
+CONFIG_PSTORE=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 26807e5aff51..6f3887d884d2 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -176,6 +176,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 #define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 #define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
+#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -394,19 +395,20 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
             CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
-            CPU_FTR_HVMODE)
+            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | \
             CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
             CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
-            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR)
+            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
+            CPU_FTR_DABRX)
 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -415,7 +417,7 @@ extern const char *powerpc_base_platform;
             CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
             CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
             CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
-            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR)
+            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -430,14 +432,15 @@ extern const char *powerpc_base_platform;
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
-            CPU_FTR_UNALIGNED_LD_STD)
+            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
             CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
-            CPU_FTR_PURR | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
+                     CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
+                     CPU_FTR_ICSWX | CPU_FTR_DABRX )
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index a80e32b46c11..09a8743143f3 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -24,6 +24,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/string.h>
+#include <linux/time.h>
 
 struct pci_dev;
 struct pci_bus;
@@ -52,6 +53,7 @@ struct device_node;
 
 #define EEH_PE_ISOLATED         (1 << 0)        /* Isolated PE          */
 #define EEH_PE_RECOVERING       (1 << 1)        /* Recovering PE        */
+#define EEH_PE_PHB_DEAD         (1 << 2)        /* Dead PHB             */
 
 struct eeh_pe {
         int type;                       /* PE type: PHB/Bus/Device      */
@@ -59,8 +61,10 @@ struct eeh_pe {
         int config_addr;                /* Traditional PCI address      */
         int addr;                       /* PE configuration address     */
         struct pci_controller *phb;     /* Associated PHB               */
+        struct pci_bus *bus;            /* Top PCI bus for bus PE       */
         int check_count;                /* Times of ignored error       */
         int freeze_count;               /* Times of froze up            */
+        struct timeval tstamp;          /* Time on first-time freeze    */
         int false_positives;            /* Times of reported #ff's      */
         struct eeh_pe *parent;          /* Parent PE                    */
         struct list_head child_list;    /* Link PE to the child list    */
@@ -95,12 +99,12 @@ struct eeh_dev {
 
 static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
 {
-        return edev->dn;
+        return edev ? edev->dn : NULL;
 }
 
 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 {
-        return edev->pdev;
+        return edev ? edev->pdev : NULL;
 }
 
 /*
@@ -130,8 +134,9 @@ static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
 struct eeh_ops {
         char *name;
         int (*init)(void);
+        int (*post_init)(void);
         void* (*of_probe)(struct device_node *dn, void *flag);
-        void* (*dev_probe)(struct pci_dev *dev, void *flag);
+        int (*dev_probe)(struct pci_dev *dev, void *flag);
         int (*set_option)(struct eeh_pe *pe, int option);
         int (*get_pe_addr)(struct eeh_pe *pe);
         int (*get_state)(struct eeh_pe *pe, int *state);
@@ -141,11 +146,12 @@ struct eeh_ops {
         int (*configure_bridge)(struct eeh_pe *pe);
         int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
         int (*write_config)(struct device_node *dn, int where, int size, u32 val);
+        int (*next_error)(struct eeh_pe **pe);
 };
 
 extern struct eeh_ops *eeh_ops;
 extern int eeh_subsystem_enabled;
-extern struct mutex eeh_mutex;
+extern raw_spinlock_t confirm_error_lock;
 extern int eeh_probe_mode;
 
 #define EEH_PROBE_MODE_DEV      (1<<0)  /* From PCI device      */
@@ -166,14 +172,14 @@ static inline int eeh_probe_mode_dev(void)
         return (eeh_probe_mode == EEH_PROBE_MODE_DEV);
 }
 
-static inline void eeh_lock(void)
+static inline void eeh_serialize_lock(unsigned long *flags)
 {
-        mutex_lock(&eeh_mutex);
+        raw_spin_lock_irqsave(&confirm_error_lock, *flags);
 }
 
-static inline void eeh_unlock(void)
+static inline void eeh_serialize_unlock(unsigned long flags)
 {
-        mutex_unlock(&eeh_mutex);
+        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 }
 
 /*
@@ -184,8 +190,11 @@ static inline void eeh_unlock(void)
 
 typedef void *(*eeh_traverse_func)(void *data, void *flag);
 int eeh_phb_pe_create(struct pci_controller *phb);
+struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
+struct eeh_pe *eeh_pe_get(struct eeh_dev *edev);
 int eeh_add_to_parent_pe(struct eeh_dev *edev);
 int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe);
+void eeh_pe_update_time_stamp(struct eeh_pe *pe);
 void *eeh_pe_dev_traverse(struct eeh_pe *root,
                 eeh_traverse_func fn, void *flag);
 void eeh_pe_restore_bars(struct eeh_pe *pe);
@@ -193,12 +202,13 @@ struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
 
 void *eeh_dev_init(struct device_node *dn, void *data);
 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
+int eeh_init(void);
 int __init eeh_ops_register(struct eeh_ops *ops);
 int __exit eeh_ops_unregister(const char *name);
 unsigned long eeh_check_failure(const volatile void __iomem *token,
                                 unsigned long val);
 int eeh_dev_check_failure(struct eeh_dev *edev);
-void __init eeh_addr_cache_build(void);
+void eeh_addr_cache_build(void);
 void eeh_add_device_tree_early(struct device_node *);
 void eeh_add_device_tree_late(struct pci_bus *);
 void eeh_add_sysfs_files(struct pci_bus *);
@@ -221,6 +231,11 @@ void eeh_remove_bus_device(struct pci_dev *, int);
 
 #else /* !CONFIG_EEH */
 
+static inline int eeh_init(void)
+{
+        return 0;
+}
+
 static inline void *eeh_dev_init(struct device_node *dn, void *data)
 {
         return NULL;
@@ -245,9 +260,6 @@ static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
 
 static inline void eeh_remove_bus_device(struct pci_dev *dev, int purge_pe) { }
 
-static inline void eeh_lock(void) { }
-static inline void eeh_unlock(void) { }
-
 #define EEH_POSSIBLE_ERROR(val, type) (0)
 #define EEH_IO_ERROR_VALUE(size) (-1UL)
 #endif /* CONFIG_EEH */
diff --git a/arch/powerpc/include/asm/eeh_event.h b/arch/powerpc/include/asm/eeh_event.h
index de67d830151b..89d5670b2eeb 100644
--- a/arch/powerpc/include/asm/eeh_event.h
+++ b/arch/powerpc/include/asm/eeh_event.h
@@ -31,7 +31,9 @@ struct eeh_event {
         struct eeh_pe           *pe;    /* EEH PE               */
 };
 
+int eeh_event_init(void);
 int eeh_send_failure_event(struct eeh_pe *pe);
+void eeh_remove_event(struct eeh_pe *pe);
 void eeh_handle_event(struct eeh_pe *pe);
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8e5fae8beaf6..07ca627e52c0 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -358,12 +358,12 @@ label##_relon_pSeries:					\
         /* No guest interrupts come through here */     \
         SET_SCRATCH0(r13);              /* save r13 */  \
         EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
-                                       EXC_STD, KVMTEST_PR, vec)
+                                       EXC_STD, NOTEST, vec)
 
 #define STD_RELON_EXCEPTION_PSERIES_OOL(vec, label)             \
         .globl label##_relon_pSeries;                           \
 label##_relon_pSeries:                                          \
-        EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_PR, vec);        \
+        EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec);            \
         EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_STD)
 
 #define STD_RELON_EXCEPTION_HV(loc, vec, label)         \
@@ -374,12 +374,12 @@ label##_relon_hv:					\
         /* No guest interrupts come through here */     \
         SET_SCRATCH0(r13);      /* save r13 */          \
         EXCEPTION_RELON_PROLOG_PSERIES(PACA_EXGEN, label##_common, \
-                                       EXC_HV, KVMTEST, vec)
+                                       EXC_HV, NOTEST, vec)
 
 #define STD_RELON_EXCEPTION_HV_OOL(vec, label)                  \
         .globl label##_relon_hv;                                \
 label##_relon_hv:                                               \
-        EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST, vec);           \
+        EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, vec);            \
         EXCEPTION_RELON_PROLOG_PSERIES_1(label##_common, EXC_HV)
 
 /* This associate vector numbers with bits in paca->irq_happened */
@@ -513,7 +513,7 @@ label##_common:							\
  */
 #define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr)             \
         EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
-                         FINISH_NAP;RUNLATCH_ON;DISABLE_INTS)
+                         FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
 
 /*
  * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/hugetlb.h b/arch/powerpc/include/asm/hugetlb.h
index f2498c8e595d..d750336b171d 100644
--- a/arch/powerpc/include/asm/hugetlb.h
+++ b/arch/powerpc/include/asm/hugetlb.h
@@ -191,8 +191,14 @@ static inline void flush_hugetlb_page(struct vm_area_struct *vma,
                                       unsigned long vmaddr)
 {
 }
-#endif /* CONFIG_HUGETLB_PAGE */
 
+#define hugepd_shift(x) 0
+static inline pte_t *hugepte_offset(hugepd_t *hpdp, unsigned long addr,
+                                    unsigned pdshift)
+{
+        return 0;
+}
+#endif /* CONFIG_HUGETLB_PAGE */
 
 /*
  * FSL Book3E platforms require special gpage handling - the gpages
diff --git a/arch/powerpc/include/asm/ibmebus.h b/arch/powerpc/include/asm/ibmebus.h
index 1a9d9aea21fa..088f95b2e14f 100644
--- a/arch/powerpc/include/asm/ibmebus.h
+++ b/arch/powerpc/include/asm/ibmebus.h
@@ -48,8 +48,8 @@
 
 extern struct bus_type ibmebus_bus_type;
 
-int ibmebus_register_driver(struct of_platform_driver *drv);
-void ibmebus_unregister_driver(struct of_platform_driver *drv);
+int ibmebus_register_driver(struct platform_driver *drv);
+void ibmebus_unregister_driver(struct platform_driver *drv);
 
 int ibmebus_request_irq(u32 ist, irq_handler_t handler,
                         unsigned long irq_flags, const char *devname,
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index cbfe678e3dbe..c34656a8925e 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -76,6 +76,9 @@ struct iommu_table {
         struct iommu_pool large_pool;
         struct iommu_pool pools[IOMMU_NR_POOLS];
         unsigned long *it_map;       /* A simple allocation bitmap for now */
+#ifdef CONFIG_IOMMU_API
+        struct iommu_group *it_group;
+#endif
 };
 
 struct scatterlist;
@@ -98,6 +101,8 @@ extern void iommu_free_table(struct iommu_table *tbl, const char *node_name);
  */
 extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
                                             int nid);
+extern void iommu_register_group(struct iommu_table *tbl,
+                                 int pci_domain_number, unsigned long pe_num);
 
 extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                         struct scatterlist *sglist, int nelems,
@@ -125,13 +130,6 @@ extern void iommu_init_early_pSeries(void);
 extern void iommu_init_early_dart(void);
 extern void iommu_init_early_pasemi(void);
 
-#ifdef CONFIG_PCI
-extern void pci_iommu_init(void);
-extern void pci_direct_iommu_init(void);
-#else
-static inline void pci_iommu_init(void) { }
-#endif
-
 extern void alloc_dart_table(void);
 #if defined(CONFIG_PPC64) && defined(CONFIG_PM)
 static inline void iommu_save(void)
@@ -147,5 +145,26 @@ static inline void iommu_restore(void)
 }
 #endif
 
+/* The API to support IOMMU operations for VFIO */
+extern int iommu_tce_clear_param_check(struct iommu_table *tbl,
+                unsigned long ioba, unsigned long tce_value,
+                unsigned long npages);
+extern int iommu_tce_put_param_check(struct iommu_table *tbl,
+                unsigned long ioba, unsigned long tce);
+extern int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
+                unsigned long hwaddr, enum dma_data_direction direction);
+extern unsigned long iommu_clear_tce(struct iommu_table *tbl,
+                unsigned long entry);
+extern int iommu_clear_tces_and_put_pages(struct iommu_table *tbl,
+                unsigned long entry, unsigned long pages);
+extern int iommu_put_tce_user_mode(struct iommu_table *tbl,
+                unsigned long entry, unsigned long tce);
+
+extern void iommu_flush_tce(struct iommu_table *tbl);
+extern int iommu_take_ownership(struct iommu_table *tbl);
+extern void iommu_release_ownership(struct iommu_table *tbl);
+
+extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_IOMMU_H */
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index b9dd382cb349..851bac7afa4b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -54,8 +54,16 @@
 #define BOOKE_INTERRUPT_DEBUG 15
 
 /* E500 */
-#define BOOKE_INTERRUPT_SPE_UNAVAIL 32
-#define BOOKE_INTERRUPT_SPE_FP_DATA 33
+#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
+#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
+/*
+ * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
+ */
+#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
+#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
+#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
+                                BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
 #define BOOKE_INTERRUPT_SPE_FP_ROUND 34
 #define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
 #define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@
 #define BOOKE_INTERRUPT_HV_SYSCALL 40
 #define BOOKE_INTERRUPT_HV_PRIV 41
 
-/* altivec */
-#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
-#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
-
 /* book3s */
 
 #define BOOK3S_INTERRUPT_SYSTEM_RESET   0x100
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index 349ed85c7d61..08891d07aeb6 100644
--- a/arch/powerpc/include/asm/kvm_book3s.h
+++ b/arch/powerpc/include/asm/kvm_book3s.h
@@ -107,8 +107,9 @@ struct kvmppc_vcpu_book3s {
 #define CONTEXT_GUEST           1
 #define CONTEXT_GUEST_END       2
 
-#define VSID_REAL       0x1fffffffffc00000ULL
-#define VSID_BAT        0x1fffffffffb00000ULL
+#define VSID_REAL       0x0fffffffffc00000ULL
+#define VSID_BAT        0x0fffffffffb00000ULL
+#define VSID_1T         0x1000000000000000ULL
 #define VSID_REAL_DR    0x2000000000000000ULL
 #define VSID_REAL_IR    0x4000000000000000ULL
 #define VSID_PR         0x8000000000000000ULL
@@ -123,6 +124,7 @@ extern void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu);
 extern void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu);
 extern int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte);
 extern int kvmppc_mmu_map_segment(struct kvm_vcpu *vcpu, ulong eaddr);
+extern void kvmppc_mmu_flush_segment(struct kvm_vcpu *vcpu, ulong eaddr, ulong seg_size);
 extern void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu);
 extern int kvmppc_book3s_hv_page_fault(struct kvm_run *run,
                         struct kvm_vcpu *vcpu, unsigned long addr,
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index 9c1ff330c805..a1ecb14e4442 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -159,36 +159,46 @@ static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)
 }
 
 /*
- * Lock and read a linux PTE.  If it's present and writable, atomically
- * set dirty and referenced bits and return the PTE, otherwise return 0.
+ * If it's present and writable, atomically set dirty and referenced bits and
+ * return the PTE, otherwise return 0. If we find a transparent hugepage
+ * and if it is marked splitting we return 0;
  */
-static inline pte_t kvmppc_read_update_linux_pte(pte_t *p, int writing)
+static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
+                                                 unsigned int hugepage)
 {
-        pte_t pte, tmp;
-
-        /* wait until _PAGE_BUSY is clear then set it atomically */
-        __asm__ __volatile__ (
-                "1:     ldarx   %0,0,%3\n"
-                "       andi.   %1,%0,%4\n"
-                "       bne-    1b\n"
-                "       ori     %1,%0,%4\n"
-                "       stdcx.  %1,0,%3\n"
-                "       bne-    1b"
-                : "=&r" (pte), "=&r" (tmp), "=m" (*p)
-                : "r" (p), "i" (_PAGE_BUSY)
-                : "cc");
-
-        if (pte_present(pte)) {
-                pte = pte_mkyoung(pte);
-                if (writing && pte_write(pte))
-                        pte = pte_mkdirty(pte);
-        }
+        pte_t old_pte, new_pte = __pte(0);
+
+        while (1) {
+                old_pte = pte_val(*ptep);
+                /*
+                 * wait until _PAGE_BUSY is clear then set it atomically
+                 */
+                if (unlikely(old_pte & _PAGE_BUSY)) {
+                        cpu_relax();
+                        continue;
+                }
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+                /* If hugepage and is trans splitting return None */
+                if (unlikely(hugepage &&
+                             pmd_trans_splitting(pte_pmd(old_pte))))
+                        return __pte(0);
+#endif
+                /* If pte is not present return None */
+                if (unlikely(!(old_pte & _PAGE_PRESENT)))
+                        return __pte(0);
 
-        *p = pte;       /* clears _PAGE_BUSY */
+                new_pte = pte_mkyoung(old_pte);
+                if (writing && pte_write(old_pte))
+                        new_pte = pte_mkdirty(new_pte);
 
-        return pte;
+                if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte,
+                                             new_pte))
+                        break;
+        }
+        return new_pte;
 }
 
+
 /* Return HPTE cache control bits corresponding to Linux pte bits */
 static inline unsigned long hpte_cache_bits(unsigned long pte_val)
 {
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index b1e7f2af1016..9b12f88d4adb 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -66,7 +66,8 @@ struct lppaca {
 
         u8      reserved6[48];
         u8      cede_latency_hint;
-        u8      reserved7[7];
+        u8      ebb_regs_in_use;
+        u8      reserved7[6];
         u8      dtl_enable_mask;        /* Dispatch Trace Log mask */
         u8      donate_dedicated_cpu;   /* Donate dedicated CPU cycles */
         u8      fpregs_in_use;
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 92386fc4e82a..8b480901165a 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -36,13 +36,13 @@ struct machdep_calls {
 #ifdef CONFIG_PPC64
         void            (*hpte_invalidate)(unsigned long slot,
                                            unsigned long vpn,
-                                           int psize, int ssize,
-                                           int local);
+                                           int bpsize, int apsize,
+                                           int ssize, int local);
         long            (*hpte_updatepp)(unsigned long slot, 
                                          unsigned long newpp, 
                                          unsigned long vpn,
-                                         int psize, int ssize,
-                                         int local);
+                                         int bpsize, int apsize,
+                                         int ssize, int local);
         void            (*hpte_updateboltedpp)(unsigned long newpp, 
                                                unsigned long ea,
                                                int psize, int ssize);
@@ -57,6 +57,9 @@ struct machdep_calls {
         void            (*hpte_removebolted)(unsigned long ea,
                                              int psize, int ssize);
         void            (*flush_hash_range)(unsigned long number, int local);
+        void            (*hugepage_invalidate)(struct mm_struct *mm,
+                                               unsigned char *hpte_slot_array,
+                                               unsigned long addr, int psize);
 
         /* special for kexec, to be called in real mode, linear mapping is
          * destroyed as well */
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 2accc9611248..c4cf01197273 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -340,6 +340,20 @@ extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
 int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                      pte_t *ptep, unsigned long trap, int local, int ssize,
                      unsigned int shift, unsigned int mmu_psize);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+extern int __hash_page_thp(unsigned long ea, unsigned long access,
+                           unsigned long vsid, pmd_t *pmdp, unsigned long trap,
+                           int local, int ssize, unsigned int psize);
+#else
+static inline int __hash_page_thp(unsigned long ea, unsigned long access,
+                                  unsigned long vsid, pmd_t *pmdp,
+                                  unsigned long trap, int local,
+                                  int ssize, unsigned int psize)
+{
+        BUG();
+        return -1;
+}
+#endif
 extern void hash_failure_debug(unsigned long ea, unsigned long access,
                                unsigned long vsid, unsigned long trap,
                                int ssize, int psize, int lpsize,
diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h
index a73668a5f30d..b467530e2485 100644
--- a/arch/powerpc/include/asm/mmu_context.h
+++ b/arch/powerpc/include/asm/mmu_context.h
@@ -38,7 +38,7 @@ extern void drop_cop(unsigned long acop, struct mm_struct *mm);
 
 /*
  * switch_mm is the entry point called from the architecture independent
- * code in kernel/sched.c
+ * code in kernel/sched/core.c
  */
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                              struct task_struct *tsk)
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 885c040d6194..8ae133eaf9fa 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -68,6 +68,5 @@ struct mpc512x_lpc {
 };
 
 int mpc512x_cs_config(unsigned int cs, u32 val);
-int __init mpc5121_clk_init(void);
 
 #endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index 2966df604221..d0ece257d310 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -299,4 +299,53 @@ struct mpc512x_psc_fifo {
 #define rxdata_32 rxdata.rxdata_32
 };
 
+struct mpc5125_psc {
+        u8              mr1;                    /* PSC + 0x00 */
+        u8              reserved0[3];
+        u8              mr2;                    /* PSC + 0x04 */
+        u8              reserved1[3];
+        struct {
+                u16             status;         /* PSC + 0x08 */
+                u8              reserved2[2];
+                u8              clock_select;   /* PSC + 0x0c */
+                u8              reserved3[3];
+        } sr_csr;
+        u8              command;                /* PSC + 0x10 */
+        u8              reserved4[3];
+        union {                                 /* PSC + 0x14 */
+                u8              buffer_8;
+                u16             buffer_16;
+                u32             buffer_32;
+        } buffer;
+        struct {
+                u8              ipcr;           /* PSC + 0x18 */
+                u8              reserved5[3];
+                u8              acr;            /* PSC + 0x1c */
+                u8              reserved6[3];
+        } ipcr_acr;
+        struct {
+                u16             isr;            /* PSC + 0x20 */
+                u8              reserved7[2];
+                u16             imr;            /* PSC + 0x24 */
+                u8              reserved8[2];
+        } isr_imr;
+        u8              ctur;                   /* PSC + 0x28 */
+        u8              reserved9[3];
+        u8              ctlr;                   /* PSC + 0x2c */
+        u8              reserved10[3];
+        u32             ccr;                    /* PSC + 0x30 */
+        u32             ac97slots;              /* PSC + 0x34 */
+        u32             ac97cmd;                /* PSC + 0x38 */
+        u32             ac97data;               /* PSC + 0x3c */
+        u8              reserved11[4];
+        u8              ip;                     /* PSC + 0x44 */
+        u8              reserved12[3];
+        u8              op1;                    /* PSC + 0x48 */
+        u8              reserved13[3];
+        u8              op0;                    /* PSC + 0x4c */
+        u8              reserved14[3];
+        u32             sicr;                   /* PSC + 0x50 */
+        u8              reserved15[4];  /* make eq. sizeof(mpc52xx_psc) */
+};
+
 #endif  /* __ASM_MPC52xx_PSC_H__ */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c0f9ef90f0b8..4a1ac9fbf186 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -339,6 +339,8 @@ struct mpic
 #endif
 };
 
+extern struct bus_type mpic_subsys;
+
 /*
  * MPIC flags (passed to mpic_alloc)
  *
@@ -393,6 +395,9 @@ struct mpic
 #define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
 #define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 
+/* Get the version of primary MPIC */
+extern u32 fsl_mpic_primary_get_version(void);
+
 /* Allocate the controller structure and setup the linux irq descs
  * for the range if interrupts passed in. No HW initialization is
  * actually performed.
diff --git a/arch/powerpc/include/asm/mpic_timer.h b/arch/powerpc/include/asm/mpic_timer.h
new file mode 100644
index 000000000000..0e23cd4ac8aa
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_timer.h
@@ -0,0 +1,46 @@
+/*
+ * arch/powerpc/include/asm/mpic_timer.h
+ *
+ * Header file for Mpic Global Timer
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Author: Wang Dongsheng <Dongsheng.Wang@freescale.com>
+ *         Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __MPIC_TIMER__
+#define __MPIC_TIMER__
+
+#include <linux/interrupt.h>
+#include <linux/time.h>
+
+struct mpic_timer {
+        void                    *dev;
+        struct cascade_priv     *cascade_handle;
+        unsigned int            num;
+        unsigned int            irq;
+};
+
+#ifdef CONFIG_MPIC_TIMER
+struct mpic_timer *mpic_request_timer(irq_handler_t fn,  void *dev,
+                const struct timeval *time);
+void mpic_start_timer(struct mpic_timer *handle);
+void mpic_stop_timer(struct mpic_timer *handle);
+void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time);
+void mpic_free_timer(struct mpic_timer *handle);
+#else
+struct mpic_timer *mpic_request_timer(irq_handler_t fn,  void *dev,
+                const struct timeval *time) { return NULL; }
+void mpic_start_timer(struct mpic_timer *handle) { }
+void mpic_stop_timer(struct mpic_timer *handle) { }
+void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time) { }
+void mpic_free_timer(struct mpic_timer *handle) { }
+#endif
+
+#endif
diff --git a/arch/powerpc/include/asm/mutex.h b/arch/powerpc/include/asm/mutex.h
index 5399f7e18102..127ab23e1f6c 100644
--- a/arch/powerpc/include/asm/mutex.h
+++ b/arch/powerpc/include/asm/mutex.h
@@ -82,17 +82,15 @@ __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
  *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
  *                                 from 1 to a 0 value
  *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
  *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns.
+ * Change the count from 1 to a value lower than 1. This function returns 0
+ * if the fastpath succeeds, or -1 otherwise.
  */
 static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count)
 {
         if (unlikely(__mutex_dec_return_lock(count) < 0))
-                return fail_fn(count);
+                return -1;
         return 0;
 }
 
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index cbb9305ab15a..029fe85722aa 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -117,7 +117,13 @@ extern int opal_enter_rtas(struct rtas_args *args,
 #define OPAL_SET_SLOT_LED_STATUS                55
 #define OPAL_GET_EPOW_STATUS                    56
 #define OPAL_SET_SYSTEM_ATTENTION_LED           57
+#define OPAL_RESERVED1                          58
+#define OPAL_RESERVED2                          59
+#define OPAL_PCI_NEXT_ERROR                     60
+#define OPAL_PCI_EEH_FREEZE_STATUS2             61
+#define OPAL_PCI_POLL                           62
 #define OPAL_PCI_MSI_EOI                        63
+#define OPAL_PCI_GET_PHB_DIAG_DATA2             64
 
 #ifndef __ASSEMBLY__
 
@@ -125,6 +131,7 @@ extern int opal_enter_rtas(struct rtas_args *args,
 enum OpalVendorApiTokens {
         OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
 };
+
 enum OpalFreezeState {
         OPAL_EEH_STOPPED_NOT_FROZEN = 0,
         OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
@@ -134,55 +141,69 @@ enum OpalFreezeState {
         OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
         OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
 };
+
 enum OpalEehFreezeActionToken {
         OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
         OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
         OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
 };
+
 enum OpalPciStatusToken {
-        OPAL_EEH_PHB_NO_ERROR = 0,
-        OPAL_EEH_PHB_FATAL = 1,
-        OPAL_EEH_PHB_RECOVERABLE = 2,
-        OPAL_EEH_PHB_BUS_ERROR = 3,
-        OPAL_EEH_PCI_NO_DEVSEL = 4,
-        OPAL_EEH_PCI_TA = 5,
-        OPAL_EEH_PCIEX_UR = 6,
-        OPAL_EEH_PCIEX_CA = 7,
-        OPAL_EEH_PCI_MMIO_ERROR = 8,
-        OPAL_EEH_PCI_DMA_ERROR = 9
+        OPAL_EEH_NO_ERROR       = 0,
+        OPAL_EEH_IOC_ERROR      = 1,
+        OPAL_EEH_PHB_ERROR      = 2,
+        OPAL_EEH_PE_ERROR       = 3,
+        OPAL_EEH_PE_MMIO_ERROR  = 4,
+        OPAL_EEH_PE_DMA_ERROR   = 5
 };
+
+enum OpalPciErrorSeverity {
+        OPAL_EEH_SEV_NO_ERROR   = 0,
+        OPAL_EEH_SEV_IOC_DEAD   = 1,
+        OPAL_EEH_SEV_PHB_DEAD   = 2,
+        OPAL_EEH_SEV_PHB_FENCED = 3,
+        OPAL_EEH_SEV_PE_ER      = 4,
+        OPAL_EEH_SEV_INF        = 5
+};
+
 enum OpalShpcAction {
         OPAL_SHPC_GET_LINK_STATE = 0,
         OPAL_SHPC_GET_SLOT_STATE = 1
 };
+
 enum OpalShpcLinkState {
         OPAL_SHPC_LINK_DOWN = 0,
         OPAL_SHPC_LINK_UP = 1
 };
+
 enum OpalMmioWindowType {
         OPAL_M32_WINDOW_TYPE = 1,
         OPAL_M64_WINDOW_TYPE = 2,
         OPAL_IO_WINDOW_TYPE = 3
 };
+
 enum OpalShpcSlotState {
         OPAL_SHPC_DEV_NOT_PRESENT = 0,
         OPAL_SHPC_DEV_PRESENT = 1
 };
+
 enum OpalExceptionHandler {
         OPAL_MACHINE_CHECK_HANDLER = 1,
         OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
         OPAL_SOFTPATCH_HANDLER = 3
 };
+
 enum OpalPendingState {
-        OPAL_EVENT_OPAL_INTERNAL = 0x1,
-        OPAL_EVENT_NVRAM = 0x2,
-        OPAL_EVENT_RTC = 0x4,
-        OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
-        OPAL_EVENT_CONSOLE_INPUT = 0x10,
-        OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
-        OPAL_EVENT_ERROR_LOG = 0x40,
-        OPAL_EVENT_EPOW = 0x80,
-        OPAL_EVENT_LED_STATUS = 0x100
+        OPAL_EVENT_OPAL_INTERNAL        = 0x1,
+        OPAL_EVENT_NVRAM                = 0x2,
+        OPAL_EVENT_RTC                  = 0x4,
+        OPAL_EVENT_CONSOLE_OUTPUT       = 0x8,
+        OPAL_EVENT_CONSOLE_INPUT        = 0x10,
+        OPAL_EVENT_ERROR_LOG_AVAIL      = 0x20,
+        OPAL_EVENT_ERROR_LOG            = 0x40,
+        OPAL_EVENT_EPOW                 = 0x80,
+        OPAL_EVENT_LED_STATUS           = 0x100,
+        OPAL_EVENT_PCI_ERROR            = 0x200
 };
 
 /* Machine check related definitions */
@@ -364,15 +385,80 @@ struct opal_machine_check_event {
         } u;
 };
 
+enum {
+        OPAL_P7IOC_DIAG_TYPE_NONE       = 0,
+        OPAL_P7IOC_DIAG_TYPE_RGC        = 1,
+        OPAL_P7IOC_DIAG_TYPE_BI         = 2,
+        OPAL_P7IOC_DIAG_TYPE_CI         = 3,
+        OPAL_P7IOC_DIAG_TYPE_MISC       = 4,
+        OPAL_P7IOC_DIAG_TYPE_I2C        = 5,
+        OPAL_P7IOC_DIAG_TYPE_LAST       = 6
+};
+
+struct OpalIoP7IOCErrorData {
+        uint16_t type;
+
+        /* GEM */
+        uint64_t gemXfir;
+        uint64_t gemRfir;
+        uint64_t gemRirqfir;
+        uint64_t gemMask;
+        uint64_t gemRwof;
+
+        /* LEM */
+        uint64_t lemFir;
+        uint64_t lemErrMask;
+        uint64_t lemAction0;
+        uint64_t lemAction1;
+        uint64_t lemWof;
+
+        union {
+                struct OpalIoP7IOCRgcErrorData {
+                        uint64_t rgcStatus;             /* 3E1C10 */
+                        uint64_t rgcLdcp;               /* 3E1C18 */
+                }rgc;
+                struct OpalIoP7IOCBiErrorData {
+                        uint64_t biLdcp0;               /* 3C0100, 3C0118 */
+                        uint64_t biLdcp1;               /* 3C0108, 3C0120 */
+                        uint64_t biLdcp2;               /* 3C0110, 3C0128 */
+                        uint64_t biFenceStatus;         /* 3C0130, 3C0130 */
+
+                        uint8_t  biDownbound;           /* BI Downbound or Upbound */
+                }bi;
+                struct OpalIoP7IOCCiErrorData {
+                        uint64_t ciPortStatus;          /* 3Dn008 */
+                        uint64_t ciPortLdcp;            /* 3Dn010 */
+
+                        uint8_t  ciPort;                /* Index of CI port: 0/1 */
+                }ci;
+        };
+};
+
 /**
  * This structure defines the overlay which will be used to store PHB error
  * data upon request.
  */
 enum {
+        OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
+};
+
+enum {
+        OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
+};
+
+enum {
         OPAL_P7IOC_NUM_PEST_REGS = 128,
 };
 
+struct OpalIoPhbErrorCommon {
+        uint32_t version;
+        uint32_t ioType;
+        uint32_t len;
+};
+
 struct OpalIoP7IOCPhbErrorData {
+        struct OpalIoPhbErrorCommon common;
+
         uint32_t brdgCtl;
 
         // P7IOC utl regs
@@ -530,14 +616,21 @@ int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
                                         uint64_t pci_mem_size);
 int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
 
-int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer, uint64_t diag_buffer_len);
-int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer, uint64_t diag_buffer_len);
+int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
+                                   uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
+                                   uint64_t diag_buffer_len);
+int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
+                                    uint64_t diag_buffer_len);
 int64_t opal_pci_fence_phb(uint64_t phb_id);
 int64_t opal_pci_reinit(uint64_t phb_id, uint8_t reinit_scope);
 int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
 int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
 int64_t opal_get_epow_status(uint64_t *status);
 int64_t opal_set_system_attention_led(uint8_t led_action);
+int64_t opal_pci_next_error(uint64_t phb_id, uint64_t *first_frozen_pe,
+                            uint16_t *pci_error_type, uint16_t *severity);
+int64_t opal_pci_poll(uint64_t phb_id);
 
 /* Internal functions */
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
@@ -551,6 +644,11 @@ extern void hvc_opal_init_early(void);
 extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
                                    int depth, void *data);
 
+extern int opal_notifier_register(struct notifier_block *nb);
+extern void opal_notifier_enable(void);
+extern void opal_notifier_disable(void);
+extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
+
 extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
 extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
 
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index f265049dd7d6..2dd7bfc459be 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h
@@ -60,6 +60,7 @@ struct power_pmu {
 #define PPMU_HAS_SSLOT          0x00000020 /* Has sampled slot in MMCRA */
 #define PPMU_HAS_SIER           0x00000040 /* Has SIER */
 #define PPMU_BHRB               0x00000080 /* has BHRB feature enabled */
+#define PPMU_EBB                0x00000100 /* supports event based branch */
 
 /*
  * Values for flags to get_alternatives()
@@ -68,6 +69,11 @@ struct power_pmu {
 #define PPMU_LIMITED_PMC_REQD   2       /* have to put this on a limited PMC */
 #define PPMU_ONLY_COUNT_RUN     4       /* only counting in run state */
 
+/*
+ * We use the event config bit 63 as a flag to request EBB.
+ */
+#define EVENT_CONFIG_EBB_SHIFT  63
+
 extern int register_power_pmu(struct power_pmu *);
 
 struct pt_regs;
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index b66ae722a8e9..f65e27b09bd3 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -221,17 +221,17 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(PGT_CACHE(PMD_INDEX_SIZE),
+        return kmem_cache_alloc(PGT_CACHE(PMD_CACHE_INDEX),
                                 GFP_KERNEL|__GFP_REPEAT);
 }
 
 static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
 {
-        kmem_cache_free(PGT_CACHE(PMD_INDEX_SIZE), pmd);
+        kmem_cache_free(PGT_CACHE(PMD_CACHE_INDEX), pmd);
 }
 
 #define __pmd_free_tlb(tlb, pmd, addr)                \
-        pgtable_free_tlb(tlb, pmd, PMD_INDEX_SIZE)
+        pgtable_free_tlb(tlb, pmd, PMD_CACHE_INDEX)
 #ifndef CONFIG_PPC_64K_PAGES
 #define __pud_free_tlb(tlb, pud, addr)                \
         pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
index 45142d640720..a56b82fb0609 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
@@ -33,7 +33,8 @@
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
 /* Bits to mask out from a PMD to get to the PTE page */
-#define PMD_MASKED_BITS         0x1ff
+/* PMDs point to PTE table fragments which are 4K aligned.  */
+#define PMD_MASKED_BITS         0xfff
 /* Bits to mask out from a PGD/PUD to get to the PMD page */
 #define PUD_MASKED_BITS         0x1ff
 
diff --git a/arch/powerpc/include/asm/pgtable-ppc64.h b/arch/powerpc/include/asm/pgtable-ppc64.h
index e3d55f6f24fe..46db09414a10 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64.h
+++ b/arch/powerpc/include/asm/pgtable-ppc64.h
@@ -10,6 +10,7 @@
 #else
 #include <asm/pgtable-ppc64-4k.h>
 #endif
+#include <asm/barrier.h>
 
 #define FIRST_USER_ADDRESS      0
 
@@ -20,7 +21,11 @@
                             PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
 #define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
 
-
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+#define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
+#else
+#define PMD_CACHE_INDEX PMD_INDEX_SIZE
+#endif
 /*
  * Define the address range of the kernel non-linear virtual area
  */
@@ -150,7 +155,7 @@
 #define pmd_present(pmd)        (pmd_val(pmd) != 0)
 #define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
 #define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
-#define pmd_page(pmd)           virt_to_page(pmd_page_vaddr(pmd))
+extern struct page *pmd_page(pmd_t pmd);
 
 #define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
 #define pud_none(pud)           (!pud_val(pud))
@@ -339,43 +344,217 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 
 void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
 void pgtable_cache_init(void);
+#endif /* __ASSEMBLY__ */
+
+/*
+ * THP pages can't be special. So use the _PAGE_SPECIAL
+ */
+#define _PAGE_SPLITTING _PAGE_SPECIAL
+
+/*
+ * We need to differentiate between explicit huge page and THP huge
+ * page, since THP huge page also need to track real subpage details
+ */
+#define _PAGE_THP_HUGE  _PAGE_4K_PFN
 
 /*
- * find_linux_pte returns the address of a linux pte for a given
- * effective address and directory.  If not found, it returns zero.
+ * set of bits not changed in pmd_modify.
  */
-static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
+#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS |               \
+                         _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
+                         _PAGE_THP_HUGE)
+
+#ifndef __ASSEMBLY__
+/*
+ * The linux hugepage PMD now include the pmd entries followed by the address
+ * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
+ * [ 1 bit secondary | 3 bit hidx | 1 bit valid | 000]. We use one byte per
+ * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
+ * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
+ *
+ * The last three bits are intentionally left to zero. This memory location
+ * are also used as normal page PTE pointers. So if we have any pointers
+ * left around while we collapse a hugepage, we need to make sure
+ * _PAGE_PRESENT and _PAGE_FILE bits of that are zero when we look at them
+ */
+static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
 {
-        pgd_t *pg;
-        pud_t *pu;
-        pmd_t *pm;
-        pte_t *pt = NULL;
-
-        pg = pgdir + pgd_index(ea);
-        if (!pgd_none(*pg)) {
-                pu = pud_offset(pg, ea);
-                if (!pud_none(*pu)) {
-                        pm = pmd_offset(pu, ea);
-                        if (pmd_present(*pm))
-                                pt = pte_offset_kernel(pm, ea);
-                }
-        }
-        return pt;
+        return (hpte_slot_array[index] >> 3) & 0x1;
 }
 
-#ifdef CONFIG_HUGETLB_PAGE
-pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
-                                 unsigned *shift);
-#else
-static inline pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
-                                               unsigned *shift)
+static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
+                                           int index)
 {
-        if (shift)
-                *shift = 0;
-        return find_linux_pte(pgdir, ea);
+        return hpte_slot_array[index] >> 4;
 }
-#endif /* !CONFIG_HUGETLB_PAGE */
 
-#endif /* __ASSEMBLY__ */
+static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
+                                        unsigned int index, unsigned int hidx)
+{
+        hpte_slot_array[index] = hidx << 4 | 0x1 << 3;
+}
 
+static inline char *get_hpte_slot_array(pmd_t *pmdp)
+{
+        /*
+         * The hpte hindex is stored in the pgtable whose address is in the
+         * second half of the PMD
+         *
+         * Order this load with the test for pmd_trans_huge in the caller
+         */
+        smp_rmb();
+        return *(char **)(pmdp + PTRS_PER_PMD);
+
+
+}
+
+extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
+                                   pmd_t *pmdp);
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+extern pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot);
+extern pmd_t mk_pmd(struct page *page, pgprot_t pgprot);
+extern pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot);
+extern void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                       pmd_t *pmdp, pmd_t pmd);
+extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
+                                 pmd_t *pmd);
+
+static inline int pmd_trans_huge(pmd_t pmd)
+{
+        /*
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        return (pmd_val(pmd) & 0x3) && (pmd_val(pmd) & _PAGE_THP_HUGE);
+}
+
+static inline int pmd_large(pmd_t pmd)
+{
+        /*
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        if (pmd_trans_huge(pmd))
+                return pmd_val(pmd) & _PAGE_PRESENT;
+        return 0;
+}
+
+static inline int pmd_trans_splitting(pmd_t pmd)
+{
+        if (pmd_trans_huge(pmd))
+                return pmd_val(pmd) & _PAGE_SPLITTING;
+        return 0;
+}
+
+extern int has_transparent_hugepage(void);
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+
+static inline pte_t pmd_pte(pmd_t pmd)
+{
+        return __pte(pmd_val(pmd));
+}
+
+static inline pmd_t pte_pmd(pte_t pte)
+{
+        return __pmd(pte_val(pte));
+}
+
+static inline pte_t *pmdp_ptep(pmd_t *pmd)
+{
+        return (pte_t *)pmd;
+}
+
+#define pmd_pfn(pmd)            pte_pfn(pmd_pte(pmd))
+#define pmd_young(pmd)          pte_young(pmd_pte(pmd))
+#define pmd_mkold(pmd)          pte_pmd(pte_mkold(pmd_pte(pmd)))
+#define pmd_wrprotect(pmd)      pte_pmd(pte_wrprotect(pmd_pte(pmd)))
+#define pmd_mkdirty(pmd)        pte_pmd(pte_mkdirty(pmd_pte(pmd)))
+#define pmd_mkyoung(pmd)        pte_pmd(pte_mkyoung(pmd_pte(pmd)))
+#define pmd_mkwrite(pmd)        pte_pmd(pte_mkwrite(pmd_pte(pmd)))
+
+#define __HAVE_ARCH_PMD_WRITE
+#define pmd_write(pmd)          pte_write(pmd_pte(pmd))
+
+static inline pmd_t pmd_mkhuge(pmd_t pmd)
+{
+        /* Do nothing, mk_pmd() does this part.  */
+        return pmd;
+}
+
+static inline pmd_t pmd_mknotpresent(pmd_t pmd)
+{
+        pmd_val(pmd) &= ~_PAGE_PRESENT;
+        return pmd;
+}
+
+static inline pmd_t pmd_mksplitting(pmd_t pmd)
+{
+        pmd_val(pmd) |= _PAGE_SPLITTING;
+        return pmd;
+}
+
+#define __HAVE_ARCH_PMD_SAME
+static inline int pmd_same(pmd_t pmd_a, pmd_t pmd_b)
+{
+        return (((pmd_val(pmd_a) ^ pmd_val(pmd_b)) & ~_PAGE_HPTEFLAGS) == 0);
+}
+
+#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
+extern int pmdp_set_access_flags(struct vm_area_struct *vma,
+                                 unsigned long address, pmd_t *pmdp,
+                                 pmd_t entry, int dirty);
+
+extern unsigned long pmd_hugepage_update(struct mm_struct *mm,
+                                         unsigned long addr,
+                                         pmd_t *pmdp, unsigned long clr);
+
+static inline int __pmdp_test_and_clear_young(struct mm_struct *mm,
+                                              unsigned long addr, pmd_t *pmdp)
+{
+        unsigned long old;
+
+        if ((pmd_val(*pmdp) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
+                return 0;
+        old = pmd_hugepage_update(mm, addr, pmdp, _PAGE_ACCESSED);
+        return ((old & _PAGE_ACCESSED) != 0);
+}
+
+#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
+extern int pmdp_test_and_clear_young(struct vm_area_struct *vma,
+                                     unsigned long address, pmd_t *pmdp);
+#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
+extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
+                                  unsigned long address, pmd_t *pmdp);
+
+#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
+extern pmd_t pmdp_get_and_clear(struct mm_struct *mm,
+                                unsigned long addr, pmd_t *pmdp);
+
+#define __HAVE_ARCH_PMDP_CLEAR_FLUSH
+extern pmd_t pmdp_clear_flush(struct vm_area_struct *vma, unsigned long address,
+                              pmd_t *pmdp);
+
+#define __HAVE_ARCH_PMDP_SET_WRPROTECT
+static inline void pmdp_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pmd_t *pmdp)
+{
+
+        if ((pmd_val(*pmdp) & _PAGE_RW) == 0)
+                return;
+
+        pmd_hugepage_update(mm, addr, pmdp, _PAGE_RW);
+}
+
+#define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
+extern void pmdp_splitting_flush(struct vm_area_struct *vma,
+                                 unsigned long address, pmd_t *pmdp);
+
+#define __HAVE_ARCH_PGTABLE_DEPOSIT
+extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                       pgtable_t pgtable);
+#define __HAVE_ARCH_PGTABLE_WITHDRAW
+extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
+
+#define __HAVE_ARCH_PMDP_INVALIDATE
+extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
+                            pmd_t *pmdp);
+#endif /* __ASSEMBLY__ */
 #endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 7aeb9555f6ea..7d6eacf249cf 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -198,9 +198,6 @@ extern void paging_init(void);
  */
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #include <asm-generic/pgtable.h>
 
 
@@ -220,6 +217,12 @@ extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
 
 extern int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
                        unsigned long end, int write, struct page **pages, int *nr);
+#ifndef CONFIG_TRANSPARENT_HUGEPAGE
+#define pmd_large(pmd)          0
+#define has_transparent_hugepage() 0
+#endif
+pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea,
+                                 unsigned *shift);
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/probes.h b/arch/powerpc/include/asm/probes.h
index 5f1e15b68704..3421637cfd7b 100644
--- a/arch/powerpc/include/asm/probes.h
+++ b/arch/powerpc/include/asm/probes.h
@@ -38,5 +38,30 @@ typedef u32 ppc_opcode_t;
 #define is_trap(instr)          (IS_TW(instr) || IS_TWI(instr))
 #endif /* CONFIG_PPC64 */
 
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+#define MSR_SINGLESTEP  (MSR_DE)
+#else
+#define MSR_SINGLESTEP  (MSR_SE)
+#endif
+
+/* Enable single stepping for the current task */
+static inline void enable_single_step(struct pt_regs *regs)
+{
+        regs->msr |= MSR_SINGLESTEP;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+        /*
+         * We turn off Critical Input Exception(CE) to ensure that the single
+         * step will be for the instruction we have the probe on; if we don't,
+         * it is possible we'd get the single step reported for CE.
+         */
+        regs->msr &= ~MSR_CE;
+        mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
+#ifdef CONFIG_PPC_47x
+        isync();
+#endif
+#endif
+}
+
+
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_PROBES_H */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 14a658363698..47a35b08b963 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -168,10 +168,10 @@ struct thread_struct {
          * The following help to manage the use of Debug Control Registers
          * om the BookE platforms.
          */
-        unsigned long   dbcr0;
-        unsigned long   dbcr1;
+        uint32_t        dbcr0;
+        uint32_t        dbcr1;
 #ifdef CONFIG_BOOKE
-        unsigned long   dbcr2;
+        uint32_t        dbcr2;
 #endif
         /*
          * The stored value of the DBSR register will be the value at the
@@ -179,7 +179,7 @@ struct thread_struct {
          * user (will never be written to) and has value while helping to
          * describe the reason for the last debug trap.  Torez
          */
-        unsigned long   dbsr;
+        uint32_t        dbsr;
         /*
          * The following will contain addresses used by debug applications
          * to help trace and trap on particular address locations.
@@ -200,7 +200,7 @@ struct thread_struct {
 #endif
 #endif
         /* FP and VSX 0-31 register set */
-        double          fpr[32][TS_FPRWIDTH];
+        double          fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
         struct {
 
                 unsigned int pad;
@@ -287,9 +287,9 @@ struct thread_struct {
         unsigned long   siar;
         unsigned long   sdar;
         unsigned long   sier;
-        unsigned long   mmcr0;
         unsigned long   mmcr2;
-        unsigned long   mmcra;
+        unsigned        mmcr0;
+        unsigned        used_ebb;
 #endif
 };
 
@@ -404,9 +404,7 @@ static inline void prefetchw(const void *x)
 
 #define spin_lock_prefetch(x)   prefetchw(x)
 
-#ifdef CONFIG_PPC64
 #define HAVE_ARCH_PICK_MMAP_LAYOUT
-#endif
 
 #ifdef CONFIG_PPC64
 static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 4a9e408644fe..5d7d9c2a5473 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -621,11 +621,15 @@
 #define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
 #define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
 #define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_EBE     0x00100000UL /* Event based branch enable */
+#define   MMCR0_PMCC    0x000c0000UL /* PMC control */
+#define   MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
 #define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
 #define   MMCR0_PMCjCE  0x00004000UL /* PMCj count enable*/
 #define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
 #define   MMCR0_PMAO    0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
 #define   MMCR0_SHRFC   0x00000040UL /* SHRre freeze conditions between threads */
+#define   MMCR0_FC56    0x00000010UL /* freeze counters 5 and 6 */
 #define   MMCR0_FCTI    0x00000008UL /* freeze counters in tags inactive mode */
 #define   MMCR0_FCTA    0x00000004UL /* freeze counters in tags active mode */
 #define   MMCR0_FCWAIT  0x00000002UL /* freeze counter in WAIT state */
@@ -673,6 +677,11 @@
 #define   SIER_SIAR_VALID       0x0400000       /* SIAR contents valid */
 #define   SIER_SDAR_VALID       0x0200000       /* SDAR contents valid */
 
+/* When EBB is enabled, some of MMCR0/MMCR2/SIER are user accessible */
+#define MMCR0_USER_MASK (MMCR0_FC | MMCR0_PMXE | MMCR0_PMAO)
+#define MMCR2_USER_MASK 0x4020100804020000UL /* (FC1P|FC2P|FC3P|FC4P|FC5P|FC6P) */
+#define SIER_USER_MASK  0x7fffffUL
+
 #define SPRN_PA6T_MMCR0 795
 #define   PA6T_MMCR0_EN0        0x0000000000000001UL
 #define   PA6T_MMCR0_EN1        0x0000000000000002UL
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 34fd70488d83..c7a8bfc9f6f5 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -350,8 +350,8 @@ static inline u32 rtas_config_addr(int busno, int devfn, int reg)
                         (devfn << 8) | (reg & 0xff);
 }
 
-extern void __cpuinit rtas_give_timebase(void);
-extern void __cpuinit rtas_take_timebase(void);
+extern void rtas_give_timebase(void);
+extern void rtas_take_timebase(void);
 
 #ifdef CONFIG_PPC_RTAS
 static inline int page_is_rtas_user_buf(unsigned long pfn)
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 200d763a0a67..49a13e0ef234 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -67,4 +67,18 @@ static inline void flush_spe_to_thread(struct task_struct *t)
 }
 #endif
 
+static inline void clear_task_ebb(struct task_struct *t)
+{
+#ifdef CONFIG_PPC_BOOK3S_64
+    /* EBB perf events are not inherited, so clear all EBB state. */
+    t->thread.bescr = 0;
+    t->thread.mmcr2 = 0;
+    t->thread.mmcr0 = 0;
+    t->thread.siar = 0;
+    t->thread.sdar = 0;
+    t->thread.sier = 0;
+    t->thread.used_ebb = 0;
+#endif
+}
+
 #endif /* _ASM_POWERPC_SWITCH_TO_H */
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index 61a59271665b..2def01ed0cb2 100644
--- a/arch/powerpc/include/asm/tlbflush.h
+++ b/arch/powerpc/include/asm/tlbflush.h
@@ -165,7 +165,8 @@ static inline void flush_tlb_kernel_range(unsigned long start,
 /* Private function for use by PCI IO mapping code */
 extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
                                      unsigned long end);
-
+extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
+                                unsigned long addr);
 #else
 #error Unsupported MMU type
 #endif
diff --git a/arch/powerpc/include/asm/uaccess.h b/arch/powerpc/include/asm/uaccess.h
index 4db49590acf5..9485b43a7c00 100644
--- a/arch/powerpc/include/asm/uaccess.h
+++ b/arch/powerpc/include/asm/uaccess.h
@@ -178,7 +178,7 @@ do {								\
         long __pu_err;                                          \
         __typeof__(*(ptr)) __user *__pu_addr = (ptr);           \
         if (!is_kernel_addr((unsigned long)__pu_addr))          \
-                might_sleep();                                  \
+                might_fault();                                  \
         __chk_user_ptr(ptr);                                    \
         __put_user_size((x), __pu_addr, (size), __pu_err);      \
         __pu_err;                                               \
@@ -188,7 +188,7 @@ do {								\
 ({                                                                      \
         long __pu_err = -EFAULT;                                        \
         __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         if (access_ok(VERIFY_WRITE, __pu_addr, size))                   \
                 __put_user_size((x), __pu_addr, (size), __pu_err);      \
         __pu_err;                                                       \
@@ -268,7 +268,7 @@ do {								\
         const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
         __chk_user_ptr(ptr);                                    \
         if (!is_kernel_addr((unsigned long)__gu_addr))          \
-                might_sleep();                                  \
+                might_fault();                                  \
         __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
         (x) = (__typeof__(*(ptr)))__gu_val;                     \
         __gu_err;                                               \
@@ -282,7 +282,7 @@ do {								\
         const __typeof__(*(ptr)) __user *__gu_addr = (ptr);     \
         __chk_user_ptr(ptr);                                    \
         if (!is_kernel_addr((unsigned long)__gu_addr))          \
-                might_sleep();                                  \
+                might_fault();                                  \
         __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
         (x) = (__typeof__(*(ptr)))__gu_val;                     \
         __gu_err;                                               \
@@ -294,7 +294,7 @@ do {								\
         long __gu_err = -EFAULT;                                        \
         unsigned long  __gu_val = 0;                                    \
         const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
-        might_sleep();                                                  \
+        might_fault();                                                  \
         if (access_ok(VERIFY_READ, __gu_addr, (size)))                  \
                 __get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
         (x) = (__typeof__(*(ptr)))__gu_val;                             \
@@ -419,14 +419,14 @@ static inline unsigned long __copy_to_user_inatomic(void __user *to,
 static inline unsigned long __copy_from_user(void *to,
                 const void __user *from, unsigned long size)
 {
-        might_sleep();
+        might_fault();
         return __copy_from_user_inatomic(to, from, size);
 }
 
 static inline unsigned long __copy_to_user(void __user *to,
                 const void *from, unsigned long size)
 {
-        might_sleep();
+        might_fault();
         return __copy_to_user_inatomic(to, from, size);
 }
 
@@ -434,7 +434,7 @@ extern unsigned long __clear_user(void __user *addr, unsigned long size);
 
 static inline unsigned long clear_user(void __user *addr, unsigned long size)
 {
-        might_sleep();
+        might_fault();
         if (likely(access_ok(VERIFY_WRITE, addr, size)))
                 return __clear_user(addr, size);
         if ((unsigned long)addr < TASK_SIZE) {
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index 50f261bc3e95..0d9cecddf8a4 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -22,7 +22,7 @@ extern unsigned long vdso64_rt_sigtramp;
 extern unsigned long vdso32_sigtramp;
 extern unsigned long vdso32_rt_sigtramp;
 
-int __cpuinit vdso_getcpu_init(void);
+int vdso_getcpu_init(void);
 
 #else /* __ASSEMBLY__ */
 
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index f960a7944553..a8619bfe879e 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -58,6 +58,8 @@ obj-$(CONFIG_RTAS_PROC)		+= rtas-proc.o
 obj-$(CONFIG_LPARCFG)           += lparcfg.o
 obj-$(CONFIG_IBMVIO)            += vio.o
 obj-$(CONFIG_IBMEBUS)           += ibmebus.o
+obj-$(CONFIG_EEH)              += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
+                                  eeh_driver.o eeh_event.o eeh_sysfs.o
 obj-$(CONFIG_GENERIC_TBSYNC)    += smp-tbsync.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_FA_DUMP)           += fadump.o
@@ -100,7 +102,7 @@ obj-$(CONFIG_PPC_UDBG_16550)	+= legacy_serial.o udbg_16550.o
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_SWIOTLB)           += dma-swiotlb.o
 
-pci64-$(CONFIG_PPC64)           += pci_dn.o isa-bridge.o
+pci64-$(CONFIG_PPC64)           += pci_dn.o pci-hotplug.o isa-bridge.o
 obj-$(CONFIG_PCI)               += pci_$(CONFIG_WORD_SIZE).o $(pci64-y) \
                                    pci-common.o pci_of_scan.o
 obj-$(CONFIG_PCI_MSI)           += msi.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 6f16ffafa6f0..c7e8afc2ead0 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -105,9 +105,6 @@ int main(void)
         DEFINE(KSP_VSID, offsetof(struct thread_struct, ksp_vsid));
 #else /* CONFIG_PPC64 */
         DEFINE(PGDIR, offsetof(struct thread_struct, pgdir));
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
-        DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
-#endif
 #ifdef CONFIG_SPE
         DEFINE(THREAD_EVR0, offsetof(struct thread_struct, evr[0]));
         DEFINE(THREAD_ACC, offsetof(struct thread_struct, acc));
@@ -115,6 +112,9 @@ int main(void)
         DEFINE(THREAD_USED_SPE, offsetof(struct thread_struct, used_spe));
 #endif /* CONFIG_SPE */
 #endif /* CONFIG_PPC64 */
+#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+        DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0));
+#endif
 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
         DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
 #endif
@@ -132,7 +132,6 @@ int main(void)
         DEFINE(THREAD_SIER, offsetof(struct thread_struct, sier));
         DEFINE(THREAD_MMCR0, offsetof(struct thread_struct, mmcr0));
         DEFINE(THREAD_MMCR2, offsetof(struct thread_struct, mmcr2));
-        DEFINE(THREAD_MMCRA, offsetof(struct thread_struct, mmcra));
 #endif
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         DEFINE(PACATMSCRATCH, offsetof(struct paca_struct, tm_scratch));
diff --git a/arch/powerpc/kernel/cacheinfo.c b/arch/powerpc/kernel/cacheinfo.c
index 92c6b008dd2b..9262cf2bec4b 100644
--- a/arch/powerpc/kernel/cacheinfo.c
+++ b/arch/powerpc/kernel/cacheinfo.c
@@ -131,7 +131,8 @@ static const char *cache_type_string(const struct cache *cache)
         return cache_type_info[cache->type].name;
 }
 
-static void __cpuinit cache_init(struct cache *cache, int type, int level, struct device_node *ofnode)
+static void cache_init(struct cache *cache, int type, int level,
+                       struct device_node *ofnode)
 {
         cache->type = type;
         cache->level = level;
@@ -140,7 +141,7 @@ static void __cpuinit cache_init(struct cache *cache, int type, int level, struc
         list_add(&cache->list, &cache_list);
 }
 
-static struct cache *__cpuinit new_cache(int type, int level, struct device_node *ofnode)
+static struct cache *new_cache(int type, int level, struct device_node *ofnode)
 {
         struct cache *cache;
 
@@ -324,7 +325,8 @@ static bool cache_node_is_unified(const struct device_node *np)
         return of_get_property(np, "cache-unified", NULL);
 }
 
-static struct cache *__cpuinit cache_do_one_devnode_unified(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode_unified(struct device_node *node,
+                                                  int level)
 {
         struct cache *cache;
 
@@ -335,7 +337,8 @@ static struct cache *__cpuinit cache_do_one_devnode_unified(struct device_node *
         return cache;
 }
 
-static struct cache *__cpuinit cache_do_one_devnode_split(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode_split(struct device_node *node,
+                                                int level)
 {
         struct cache *dcache, *icache;
 
@@ -357,7 +360,7 @@ err:
         return NULL;
 }
 
-static struct cache *__cpuinit cache_do_one_devnode(struct device_node *node, int level)
+static struct cache *cache_do_one_devnode(struct device_node *node, int level)
 {
         struct cache *cache;
 
@@ -369,7 +372,8 @@ static struct cache *__cpuinit cache_do_one_devnode(struct device_node *node, in
         return cache;
 }
 
-static struct cache *__cpuinit cache_lookup_or_instantiate(struct device_node *node, int level)
+static struct cache *cache_lookup_or_instantiate(struct device_node *node,
+                                                 int level)
 {
         struct cache *cache;
 
@@ -385,7 +389,7 @@ static struct cache *__cpuinit cache_lookup_or_instantiate(struct device_node *n
         return cache;
 }
 
-static void __cpuinit link_cache_lists(struct cache *smaller, struct cache *bigger)
+static void link_cache_lists(struct cache *smaller, struct cache *bigger)
 {
         while (smaller->next_local) {
                 if (smaller->next_local == bigger)
@@ -396,13 +400,13 @@ static void __cpuinit link_cache_lists(struct cache *smaller, struct cache *bigg
         smaller->next_local = bigger;
 }
 
-static void __cpuinit do_subsidiary_caches_debugcheck(struct cache *cache)
+static void do_subsidiary_caches_debugcheck(struct cache *cache)
 {
         WARN_ON_ONCE(cache->level != 1);
         WARN_ON_ONCE(strcmp(cache->ofnode->type, "cpu"));
 }
 
-static void __cpuinit do_subsidiary_caches(struct cache *cache)
+static void do_subsidiary_caches(struct cache *cache)
 {
         struct device_node *subcache_node;
         int level = cache->level;
@@ -423,7 +427,7 @@ static void __cpuinit do_subsidiary_caches(struct cache *cache)
         }
 }
 
-static struct cache *__cpuinit cache_chain_instantiate(unsigned int cpu_id)
+static struct cache *cache_chain_instantiate(unsigned int cpu_id)
 {
         struct device_node *cpu_node;
         struct cache *cpu_cache = NULL;
@@ -448,7 +452,7 @@ out:
         return cpu_cache;
 }
 
-static struct cache_dir *__cpuinit cacheinfo_create_cache_dir(unsigned int cpu_id)
+static struct cache_dir *cacheinfo_create_cache_dir(unsigned int cpu_id)
 {
         struct cache_dir *cache_dir;
         struct device *dev;
@@ -653,7 +657,7 @@ static struct kobj_type cache_index_type = {
         .default_attrs = cache_index_default_attrs,
 };
 
-static void __cpuinit cacheinfo_create_index_opt_attrs(struct cache_index_dir *dir)
+static void cacheinfo_create_index_opt_attrs(struct cache_index_dir *dir)
 {
         const char *cache_name;
         const char *cache_type;
@@ -696,7 +700,8 @@ static void __cpuinit cacheinfo_create_index_opt_attrs(struct cache_index_dir *d
         kfree(buf);
 }
 
-static void __cpuinit cacheinfo_create_index_dir(struct cache *cache, int index, struct cache_dir *cache_dir)
+static void cacheinfo_create_index_dir(struct cache *cache, int index,
+                                       struct cache_dir *cache_dir)
 {
         struct cache_index_dir *index_dir;
         int rc;
@@ -722,7 +727,8 @@ err:
         kfree(index_dir);
 }
 
-static void __cpuinit cacheinfo_sysfs_populate(unsigned int cpu_id, struct cache *cache_list)
+static void cacheinfo_sysfs_populate(unsigned int cpu_id,
+                                     struct cache *cache_list)
 {
         struct cache_dir *cache_dir;
         struct cache *cache;
@@ -740,7 +746,7 @@ static void __cpuinit cacheinfo_sysfs_populate(unsigned int cpu_id, struct cache
         }
 }
 
-void __cpuinit cacheinfo_cpu_online(unsigned int cpu_id)
+void cacheinfo_cpu_online(unsigned int cpu_id)
 {
         struct cache *cache;
 
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 1f0937d7d4b5..2a45d0f04385 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .mmu_features           = MMU_FTRS_POWER8,
                 .icache_bsize           = 128,
                 .dcache_bsize           = 128,
-                .oprofile_type          = PPC_OPROFILE_POWER4,
-                .oprofile_cpu_type      = 0,
+                .oprofile_type          = PPC_OPROFILE_INVALID,
+                .oprofile_cpu_type      = "ppc64/ibm-compat-v1",
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
                 .platform               = "power8",
@@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .dcache_bsize           = 128,
                 .num_pmcs               = 6,
                 .pmc_type               = PPC_PMC_IBM,
-                .oprofile_cpu_type      = 0,
-                .oprofile_type          = PPC_OPROFILE_POWER4,
+                .oprofile_cpu_type      = "ppc64/power8",
+                .oprofile_type          = PPC_OPROFILE_INVALID,
                 .cpu_setup              = __setup_cpu_power8,
                 .cpu_restore            = __restore_cpu_power8,
                 .platform               = "power8",
diff --git a/arch/powerpc/kernel/crash_dump.c b/arch/powerpc/kernel/crash_dump.c
index 9ec3fe174cba..779a78c26435 100644
--- a/arch/powerpc/kernel/crash_dump.c
+++ b/arch/powerpc/kernel/crash_dump.c
@@ -69,16 +69,6 @@ void __init setup_kdump_trampoline(void)
 }
 #endif /* CONFIG_NONSTATIC_KERNEL */
 
-static int __init parse_savemaxmem(char *p)
-{
-        if (p)
-                saved_max_pfn = (memparse(p, &p) >> PAGE_SHIFT) - 1;
-
-        return 1;
-}
-__setup("savemaxmem=", parse_savemaxmem);
-
-
 static size_t copy_oldmem_vaddr(void *vaddr, char *buf, size_t csize,
                                unsigned long offset, int userbuf)
 {
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/kernel/eeh.c
index 6b73d6c44f51..39954fe941b8 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/kernel/eeh.c
@@ -103,11 +103,8 @@ EXPORT_SYMBOL(eeh_subsystem_enabled);
  */
 int eeh_probe_mode;
 
-/* Global EEH mutex */
-DEFINE_MUTEX(eeh_mutex);
-
 /* Lock to avoid races due to multiple reports of an error */
-static DEFINE_RAW_SPINLOCK(confirm_error_lock);
+DEFINE_RAW_SPINLOCK(confirm_error_lock);
 
 /* Buffer for reporting pci register dumps. Its here in BSS, and
  * not dynamically alloced, so that it ends up in RMO where RTAS
@@ -235,16 +232,30 @@ void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
 {
         size_t loglen = 0;
         struct eeh_dev *edev;
+        bool valid_cfg_log = true;
 
-        eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
-        eeh_ops->configure_bridge(pe);
-        eeh_pe_restore_bars(pe);
-
-        pci_regs_buf[0] = 0;
-        eeh_pe_for_each_dev(pe, edev) {
-                loglen += eeh_gather_pci_data(edev, pci_regs_buf,
-                                EEH_PCI_REGS_LOG_LEN);
-        }
+        /*
+         * When the PHB is fenced or dead, it's pointless to collect
+         * the data from PCI config space because it should return
+         * 0xFF's. For ER, we still retrieve the data from the PCI
+         * config space.
+         */
+        if (eeh_probe_mode_dev() &&
+            (pe->type & EEH_PE_PHB) &&
+            (pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)))
+                valid_cfg_log = false;
+
+        if (valid_cfg_log) {
+                eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
+                eeh_ops->configure_bridge(pe);
+                eeh_pe_restore_bars(pe);
+
+                pci_regs_buf[0] = 0;
+                eeh_pe_for_each_dev(pe, edev) {
+                        loglen += eeh_gather_pci_data(edev, pci_regs_buf + loglen,
+                                                      EEH_PCI_REGS_LOG_LEN - loglen);
+                }
+        }
 
         eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
 }
@@ -260,15 +271,74 @@ static inline unsigned long eeh_token_to_phys(unsigned long token)
 {
         pte_t *ptep;
         unsigned long pa;
+        int hugepage_shift;
 
-        ptep = find_linux_pte(init_mm.pgd, token);
+        /*
+         * We won't find hugepages here, iomem
+         */
+        ptep = find_linux_pte_or_hugepte(init_mm.pgd, token, &hugepage_shift);
         if (!ptep)
                 return token;
+        WARN_ON(hugepage_shift);
         pa = pte_pfn(*ptep) << PAGE_SHIFT;
 
         return pa | (token & (PAGE_SIZE-1));
 }
 
+/*
+ * On PowerNV platform, we might already have fenced PHB there.
+ * For that case, it's meaningless to recover frozen PE. Intead,
+ * We have to handle fenced PHB firstly.
+ */
+static int eeh_phb_check_failure(struct eeh_pe *pe)
+{
+        struct eeh_pe *phb_pe;
+        unsigned long flags;
+        int ret;
+
+        if (!eeh_probe_mode_dev())
+                return -EPERM;
+
+        /* Find the PHB PE */
+        phb_pe = eeh_phb_pe_get(pe->phb);
+        if (!phb_pe) {
+                pr_warning("%s Can't find PE for PHB#%d\n",
+                           __func__, pe->phb->global_number);
+                return -EEXIST;
+        }
+
+        /* If the PHB has been in problematic state */
+        eeh_serialize_lock(&flags);
+        if (phb_pe->state & (EEH_PE_ISOLATED | EEH_PE_PHB_DEAD)) {
+                ret = 0;
+                goto out;
+        }
+
+        /* Check PHB state */
+        ret = eeh_ops->get_state(phb_pe, NULL);
+        if ((ret < 0) ||
+            (ret == EEH_STATE_NOT_SUPPORT) ||
+            (ret & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) ==
+            (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE)) {
+                ret = 0;
+                goto out;
+        }
+
+        /* Isolate the PHB and send event */
+        eeh_pe_state_mark(phb_pe, EEH_PE_ISOLATED);
+        eeh_serialize_unlock(flags);
+        eeh_send_failure_event(phb_pe);
+
+        pr_err("EEH: PHB#%x failure detected\n",
+                phb_pe->phb->global_number);
+        dump_stack();
+
+        return 1;
+out:
+        eeh_serialize_unlock(flags);
+        return ret;
+}
+
 /**
  * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
  * @edev: eeh device
@@ -319,13 +389,21 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
                 return 0;
         }
 
+        /*
+         * On PowerNV platform, we might already have fenced PHB
+         * there and we need take care of that firstly.
+         */
+        ret = eeh_phb_check_failure(pe);
+        if (ret > 0)
+                return ret;
+
         /* If we already have a pending isolation event for this
          * slot, we know it's bad already, we don't need to check.
          * Do this checking under a lock; as multiple PCI devices
          * in one slot might report errors simultaneously, and we
          * only want one error recovery routine running.
          */
-        raw_spin_lock_irqsave(&confirm_error_lock, flags);
+        eeh_serialize_lock(&flags);
         rc = 1;
         if (pe->state & EEH_PE_ISOLATED) {
                 pe->check_count++;
@@ -368,13 +446,13 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
         }
 
         eeh_stats.slot_resets++;
- 
+
         /* Avoid repeated reports of this failure, including problems
          * with other functions on this device, and functions under
          * bridges.
          */
         eeh_pe_state_mark(pe, EEH_PE_ISOLATED);
-        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
+        eeh_serialize_unlock(flags);
 
         eeh_send_failure_event(pe);
 
@@ -382,11 +460,14 @@ int eeh_dev_check_failure(struct eeh_dev *edev)
          * a stack trace will help the device-driver authors figure
          * out what happened.  So print that out.
          */
-        WARN(1, "EEH: failure detected\n");
+        pr_err("EEH: Frozen PE#%x detected on PHB#%x\n",
+                pe->addr, pe->phb->global_number);
+        dump_stack();
+
         return 1;
 
 dn_unlock:
-        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
+        eeh_serialize_unlock(flags);
         return rc;
 }
 
@@ -525,7 +606,7 @@ static void eeh_reset_pe_once(struct eeh_pe *pe)
          * or a fundamental reset (3).
          * A fundamental reset required by any device under
          * Partitionable Endpoint trumps hot-reset.
-         */
+         */
         eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
 
         if (freset)
@@ -538,8 +619,8 @@ static void eeh_reset_pe_once(struct eeh_pe *pe)
          */
 #define PCI_BUS_RST_HOLD_TIME_MSEC 250
         msleep(PCI_BUS_RST_HOLD_TIME_MSEC);
-        
-        /* We might get hit with another EEH freeze as soon as the 
+
+        /* We might get hit with another EEH freeze as soon as the
          * pci slot reset line is dropped. Make sure we don't miss
          * these, and clear the flag now.
          */
@@ -565,6 +646,7 @@ static void eeh_reset_pe_once(struct eeh_pe *pe)
  */
 int eeh_reset_pe(struct eeh_pe *pe)
 {
+        int flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
         int i, rc;
 
         /* Take three shots at resetting the bus */
@@ -572,7 +654,7 @@ int eeh_reset_pe(struct eeh_pe *pe)
                 eeh_reset_pe_once(pe);
 
                 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
-                if (rc == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
+                if ((rc & flags) == flags)
                         return 0;
 
                 if (rc < 0) {
@@ -604,7 +686,7 @@ void eeh_save_bars(struct eeh_dev *edev)
         if (!edev)
                 return;
         dn = eeh_dev_to_of_node(edev);
-        
+
         for (i = 0; i < 16; i++)
                 eeh_ops->read_config(dn, i * 4, 4, &edev->config_space[i]);
 }
@@ -674,11 +756,21 @@ int __exit eeh_ops_unregister(const char *name)
  * Even if force-off is set, the EEH hardware is still enabled, so that
  * newer systems can boot.
  */
-static int __init eeh_init(void)
+int eeh_init(void)
 {
         struct pci_controller *hose, *tmp;
         struct device_node *phb;
-        int ret;
+        static int cnt = 0;
+        int ret = 0;
+
+        /*
+         * We have to delay the initialization on PowerNV after
+         * the PCI hierarchy tree has been built because the PEs
+         * are figured out based on PCI devices instead of device
+         * tree nodes
+         */
+        if (machine_is(powernv) && cnt++ <= 0)
+                return ret;
 
         /* call platform initialization function */
         if (!eeh_ops) {
@@ -691,7 +783,10 @@ static int __init eeh_init(void)
                 return ret;
         }
 
-        raw_spin_lock_init(&confirm_error_lock);
+        /* Initialize EEH event */
+        ret = eeh_event_init();
+        if (ret)
+                return ret;
 
         /* Enable EEH for all adapters */
         if (eeh_probe_mode_devtree()) {
@@ -700,6 +795,25 @@ static int __init eeh_init(void)
                         phb = hose->dn;
                         traverse_pci_devices(phb, eeh_ops->of_probe, NULL);
                 }
+        } else if (eeh_probe_mode_dev()) {
+                list_for_each_entry_safe(hose, tmp,
+                        &hose_list, list_node)
+                        pci_walk_bus(hose->bus, eeh_ops->dev_probe, NULL);
+        } else {
+                pr_warning("%s: Invalid probe mode %d\n",
+                           __func__, eeh_probe_mode);
+                return -EINVAL;
+        }
+
+        /*
+         * Call platform post-initialization. Actually, It's good chance
+         * to inform platform that EEH is ready to supply service if the
+         * I/O cache stuff has been built up.
+         */
+        if (eeh_ops->post_init) {
+                ret = eeh_ops->post_init();
+                if (ret)
+                        return ret;
         }
 
         if (eeh_subsystem_enabled)
@@ -728,6 +842,14 @@ static void eeh_add_device_early(struct device_node *dn)
 {
         struct pci_controller *phb;
 
+        /*
+         * If we're doing EEH probe based on PCI device, we
+         * would delay the probe until late stage because
+         * the PCI device isn't available this moment.
+         */
+        if (!eeh_probe_mode_devtree())
+                return;
+
         if (!of_node_to_eeh_dev(dn))
                 return;
         phb = of_node_to_eeh_dev(dn)->phb;
@@ -736,7 +858,6 @@ static void eeh_add_device_early(struct device_node *dn)
         if (NULL == phb || 0 == phb->buid)
                 return;
 
-        /* FIXME: hotplug support on POWERNV */
         eeh_ops->of_probe(dn, NULL);
 }
 
@@ -787,6 +908,13 @@ static void eeh_add_device_late(struct pci_dev *dev)
         edev->pdev = dev;
         dev->dev.archdata.edev = edev;
 
+        /*
+         * We have to do the EEH probe here because the PCI device
+         * hasn't been created yet in the early stage.
+         */
+        if (eeh_probe_mode_dev())
+                eeh_ops->dev_probe(dev, NULL);
+
         eeh_addr_cache_insert_dev(dev);
 }
 
@@ -803,12 +931,12 @@ void eeh_add_device_tree_late(struct pci_bus *bus)
         struct pci_dev *dev;
 
         list_for_each_entry(dev, &bus->devices, bus_list) {
-                eeh_add_device_late(dev);
-                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
-                        struct pci_bus *subbus = dev->subordinate;
-                        if (subbus)
-                                eeh_add_device_tree_late(subbus);
-                }
+                eeh_add_device_late(dev);
+                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
+                        struct pci_bus *subbus = dev->subordinate;
+                        if (subbus)
+                                eeh_add_device_tree_late(subbus);
+                }
         }
 }
 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
diff --git a/arch/powerpc/platforms/pseries/eeh_cache.c b/arch/powerpc/kernel/eeh_cache.c
index 5a4c87903057..f9ac1232a746 100644
--- a/arch/powerpc/platforms/pseries/eeh_cache.c
+++ b/arch/powerpc/kernel/eeh_cache.c
@@ -194,7 +194,7 @@ static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
         }
 
         /* Skip any devices for which EEH is not enabled. */
-        if (!edev->pe) {
+        if (!eeh_probe_mode_dev() && !edev->pe) {
 #ifdef DEBUG
                 pr_info("PCI: skip building address cache for=%s - %s\n",
                         pci_name(dev), dn->full_name);
@@ -285,7 +285,7 @@ void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
  * Must be run late in boot process, after the pci controllers
  * have been scanned for devices (after all device resources are known).
  */
-void __init eeh_addr_cache_build(void)
+void eeh_addr_cache_build(void)
 {
         struct device_node *dn;
         struct eeh_dev *edev;
@@ -294,8 +294,6 @@ void __init eeh_addr_cache_build(void)
         spin_lock_init(&pci_io_addr_cache_root.piar_lock);
 
         for_each_pci_dev(dev) {
-                eeh_addr_cache_insert_dev(dev);
-
                 dn = pci_device_to_OF_node(dev);
                 if (!dn)
                         continue;
@@ -308,6 +306,8 @@ void __init eeh_addr_cache_build(void)
                 dev->dev.archdata.edev = edev;
                 edev->pdev = dev;
 
+                eeh_addr_cache_insert_dev(dev);
+
                 eeh_sysfs_add_device(dev);
         }
 
@@ -316,4 +316,3 @@ void __init eeh_addr_cache_build(void)
         eeh_addr_cache_print(&pci_io_addr_cache_root);
 #endif
 }
-
diff --git a/arch/powerpc/platforms/pseries/eeh_dev.c b/arch/powerpc/kernel/eeh_dev.c
index 1efa28f5fc54..1efa28f5fc54 100644
--- a/arch/powerpc/platforms/pseries/eeh_dev.c
+++ b/arch/powerpc/kernel/eeh_dev.c
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/kernel/eeh_driver.c
index a3fefb61097c..2b1ce17cae50 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/kernel/eeh_driver.c
@@ -154,9 +154,9 @@ static void eeh_enable_irq(struct pci_dev *dev)
  * eeh_report_error - Report pci error to each device driver
  * @data: eeh device
  * @userdata: return value
- * 
- * Report an EEH error to each device driver, collect up and 
- * merge the device driver responses. Cumulative response 
+ *
+ * Report an EEH error to each device driver, collect up and
+ * merge the device driver responses. Cumulative response
  * passed back in "userdata".
  */
 static void *eeh_report_error(void *data, void *userdata)
@@ -349,10 +349,12 @@ static void *eeh_report_failure(void *data, void *userdata)
  */
 static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
 {
+        struct timeval tstamp;
         int cnt, rc;
 
         /* pcibios will clear the counter; save the value */
         cnt = pe->freeze_count;
+        tstamp = pe->tstamp;
 
         /*
          * We don't remove the corresponding PE instances because
@@ -376,15 +378,17 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
         eeh_pe_restore_bars(pe);
 
         /* Give the system 5 seconds to finish running the user-space
-         * hotplug shutdown scripts, e.g. ifdown for ethernet.  Yes, 
-         * this is a hack, but if we don't do this, and try to bring 
-         * the device up before the scripts have taken it down, 
+         * hotplug shutdown scripts, e.g. ifdown for ethernet.  Yes,
+         * this is a hack, but if we don't do this, and try to bring
+         * the device up before the scripts have taken it down,
          * potentially weird things happen.
          */
         if (bus) {
                 ssleep(5);
                 pcibios_add_pci_devices(bus);
         }
+
+        pe->tstamp = tstamp;
         pe->freeze_count = cnt;
 
         return 0;
@@ -395,24 +399,7 @@ static int eeh_reset_device(struct eeh_pe *pe, struct pci_bus *bus)
  */
 #define MAX_WAIT_FOR_RECOVERY 150
 
-/**
- * eeh_handle_event - Reset a PCI device after hard lockup.
- * @pe: EEH PE
- *
- * While PHB detects address or data parity errors on particular PCI
- * slot, the associated PE will be frozen. Besides, DMA's occurring
- * to wild addresses (which usually happen due to bugs in device
- * drivers or in PCI adapter firmware) can cause EEH error. #SERR,
- * #PERR or other misc PCI-related errors also can trigger EEH errors.
- *
- * Recovery process consists of unplugging the device driver (which
- * generated hotplug events to userspace), then issuing a PCI #RST to
- * the device, then reconfiguring the PCI config space for all bridges
- * & devices under this slot, and then finally restarting the device
- * drivers (which cause a second set of hotplug events to go out to
- * userspace).
- */
-void eeh_handle_event(struct eeh_pe *pe)
+static void eeh_handle_normal_event(struct eeh_pe *pe)
 {
         struct pci_bus *frozen_bus;
         int rc = 0;
@@ -425,6 +412,7 @@ void eeh_handle_event(struct eeh_pe *pe)
                 return;
         }
 
+        eeh_pe_update_time_stamp(pe);
         pe->freeze_count++;
         if (pe->freeze_count > EEH_MAX_ALLOWED_FREEZES)
                 goto excess_failures;
@@ -437,6 +425,7 @@ void eeh_handle_event(struct eeh_pe *pe)
          * status ... if any child can't handle the reset, then the entire
          * slot is dlpar removed and added.
          */
+        pr_info("EEH: Notify device drivers to shutdown\n");
         eeh_pe_dev_traverse(pe, eeh_report_error, &result);
 
         /* Get the current PCI slot state. This can take a long time,
@@ -444,7 +433,7 @@ void eeh_handle_event(struct eeh_pe *pe)
          */
         rc = eeh_ops->wait_state(pe, MAX_WAIT_FOR_RECOVERY*1000);
         if (rc < 0 || rc == EEH_STATE_NOT_SUPPORT) {
-                printk(KERN_WARNING "EEH: Permanent failure\n");
+                pr_warning("EEH: Permanent failure\n");
                 goto hard_fail;
         }
 
@@ -452,6 +441,7 @@ void eeh_handle_event(struct eeh_pe *pe)
          * don't post the error log until after all dev drivers
          * have been informed.
          */
+        pr_info("EEH: Collect temporary log\n");
         eeh_slot_error_detail(pe, EEH_LOG_TEMP);
 
         /* If all device drivers were EEH-unaware, then shut
@@ -459,15 +449,18 @@ void eeh_handle_event(struct eeh_pe *pe)
          * go down willingly, without panicing the system.
          */
         if (result == PCI_ERS_RESULT_NONE) {
+                pr_info("EEH: Reset with hotplug activity\n");
                 rc = eeh_reset_device(pe, frozen_bus);
                 if (rc) {
-                        printk(KERN_WARNING "EEH: Unable to reset, rc=%d\n", rc);
+                        pr_warning("%s: Unable to reset, err=%d\n",
+                                   __func__, rc);
                         goto hard_fail;
                 }
         }
 
         /* If all devices reported they can proceed, then re-enable MMIO */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
+                pr_info("EEH: Enable I/O for affected devices\n");
                 rc = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
 
                 if (rc < 0)
@@ -475,6 +468,7 @@ void eeh_handle_event(struct eeh_pe *pe)
                 if (rc) {
                         result = PCI_ERS_RESULT_NEED_RESET;
                 } else {
+                        pr_info("EEH: Notify device drivers to resume I/O\n");
                         result = PCI_ERS_RESULT_NONE;
                         eeh_pe_dev_traverse(pe, eeh_report_mmio_enabled, &result);
                 }
@@ -482,6 +476,7 @@ void eeh_handle_event(struct eeh_pe *pe)
 
         /* If all devices reported they can proceed, then re-enable DMA */
         if (result == PCI_ERS_RESULT_CAN_RECOVER) {
+                pr_info("EEH: Enabled DMA for affected devices\n");
                 rc = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
 
                 if (rc < 0)
@@ -494,17 +489,22 @@ void eeh_handle_event(struct eeh_pe *pe)
 
         /* If any device has a hard failure, then shut off everything. */
         if (result == PCI_ERS_RESULT_DISCONNECT) {
-                printk(KERN_WARNING "EEH: Device driver gave up\n");
+                pr_warning("EEH: Device driver gave up\n");
                 goto hard_fail;
         }
 
         /* If any device called out for a reset, then reset the slot */
         if (result == PCI_ERS_RESULT_NEED_RESET) {
+                pr_info("EEH: Reset without hotplug activity\n");
                 rc = eeh_reset_device(pe, NULL);
                 if (rc) {
-                        printk(KERN_WARNING "EEH: Cannot reset, rc=%d\n", rc);
+                        pr_warning("%s: Cannot reset, err=%d\n",
+                                   __func__, rc);
                         goto hard_fail;
                 }
+
+                pr_info("EEH: Notify device drivers "
+                        "the completion of reset\n");
                 result = PCI_ERS_RESULT_NONE;
                 eeh_pe_dev_traverse(pe, eeh_report_reset, &result);
         }
@@ -512,15 +512,16 @@ void eeh_handle_event(struct eeh_pe *pe)
         /* All devices should claim they have recovered by now. */
         if ((result != PCI_ERS_RESULT_RECOVERED) &&
             (result != PCI_ERS_RESULT_NONE)) {
-                printk(KERN_WARNING "EEH: Not recovered\n");
+                pr_warning("EEH: Not recovered\n");
                 goto hard_fail;
         }
 
         /* Tell all device drivers that they can resume operations */
+        pr_info("EEH: Notify device driver to resume\n");
         eeh_pe_dev_traverse(pe, eeh_report_resume, NULL);
 
         return;
-        
+
 excess_failures:
         /*
          * About 90% of all real-life EEH failures in the field
@@ -550,3 +551,111 @@ perm_error:
                 pcibios_remove_pci_devices(frozen_bus);
 }
 
+static void eeh_handle_special_event(void)
+{
+        struct eeh_pe *pe, *phb_pe;
+        struct pci_bus *bus;
+        struct pci_controller *hose, *tmp;
+        unsigned long flags;
+        int rc = 0;
+
+        /*
+         * The return value from next_error() has been classified as follows.
+         * It might be good to enumerate them. However, next_error() is only
+         * supported by PowerNV platform for now. So it would be fine to use
+         * integer directly:
+         *
+         * 4 - Dead IOC           3 - Dead PHB
+         * 2 - Fenced PHB         1 - Frozen PE
+         * 0 - No error found
+         *
+         */
+        rc = eeh_ops->next_error(&pe);
+        if (rc <= 0)
+                return;
+
+        switch (rc) {
+        case 4:
+                /* Mark all PHBs in dead state */
+                eeh_serialize_lock(&flags);
+                list_for_each_entry_safe(hose, tmp,
+                                &hose_list, list_node) {
+                        phb_pe = eeh_phb_pe_get(hose);
+                        if (!phb_pe) continue;
+
+                        eeh_pe_state_mark(phb_pe,
+                                EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
+                }
+                eeh_serialize_unlock(flags);
+
+                /* Purge all events */
+                eeh_remove_event(NULL);
+                break;
+        case 3:
+        case 2:
+        case 1:
+                /* Mark the PE in fenced state */
+                eeh_serialize_lock(&flags);
+                if (rc == 3)
+                        eeh_pe_state_mark(pe,
+                                EEH_PE_ISOLATED | EEH_PE_PHB_DEAD);
+                else
+                        eeh_pe_state_mark(pe,
+                                EEH_PE_ISOLATED | EEH_PE_RECOVERING);
+                eeh_serialize_unlock(flags);
+
+                /* Purge all events of the PHB */
+                eeh_remove_event(pe);
+                break;
+        default:
+                pr_err("%s: Invalid value %d from next_error()\n",
+                       __func__, rc);
+                return;
+        }
+
+        /*
+         * For fenced PHB and frozen PE, it's handled as normal
+         * event. We have to remove the affected PHBs for dead
+         * PHB and IOC
+         */
+        if (rc == 2 || rc == 1)
+                eeh_handle_normal_event(pe);
+        else {
+                list_for_each_entry_safe(hose, tmp,
+                        &hose_list, list_node) {
+                        phb_pe = eeh_phb_pe_get(hose);
+                        if (!phb_pe || !(phb_pe->state & EEH_PE_PHB_DEAD))
+                                continue;
+
+                        bus = eeh_pe_bus_get(phb_pe);
+                        /* Notify all devices that they're about to go down. */
+                        eeh_pe_dev_traverse(pe, eeh_report_failure, NULL);
+                        pcibios_remove_pci_devices(bus);
+                }
+        }
+}
+
+/**
+ * eeh_handle_event - Reset a PCI device after hard lockup.
+ * @pe: EEH PE
+ *
+ * While PHB detects address or data parity errors on particular PCI
+ * slot, the associated PE will be frozen. Besides, DMA's occurring
+ * to wild addresses (which usually happen due to bugs in device
+ * drivers or in PCI adapter firmware) can cause EEH error. #SERR,
+ * #PERR or other misc PCI-related errors also can trigger EEH errors.
+ *
+ * Recovery process consists of unplugging the device driver (which
+ * generated hotplug events to userspace), then issuing a PCI #RST to
+ * the device, then reconfiguring the PCI config space for all bridges
+ * & devices under this slot, and then finally restarting the device
+ * drivers (which cause a second set of hotplug events to go out to
+ * userspace).
+ */
+void eeh_handle_event(struct eeh_pe *pe)
+{
+        if (pe)
+                eeh_handle_normal_event(pe);
+        else
+                eeh_handle_special_event();
+}
diff --git a/arch/powerpc/platforms/pseries/eeh_event.c b/arch/powerpc/kernel/eeh_event.c
index 185bedd926df..d27c5afc90ae 100644
--- a/arch/powerpc/platforms/pseries/eeh_event.c
+++ b/arch/powerpc/kernel/eeh_event.c
@@ -18,11 +18,10 @@
 
 #include <linux/delay.h>
 #include <linux/list.h>
-#include <linux/mutex.h>
 #include <linux/sched.h>
+#include <linux/semaphore.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
-#include <linux/workqueue.h>
 #include <linux/kthread.h>
 #include <asm/eeh_event.h>
 #include <asm/ppc-pci.h>
@@ -35,14 +34,9 @@
  *  work-queue, where a worker thread can drive recovery.
  */
 
-/* EEH event workqueue setup. */
 static DEFINE_SPINLOCK(eeh_eventlist_lock);
+static struct semaphore eeh_eventlist_sem;
 LIST_HEAD(eeh_eventlist);
-static void eeh_thread_launcher(struct work_struct *);
-DECLARE_WORK(eeh_event_wq, eeh_thread_launcher);
-
-/* Serialize reset sequences for a given pci device */
-DEFINE_MUTEX(eeh_event_mutex);
 
 /**
  * eeh_event_handler - Dispatch EEH events.
@@ -60,55 +54,63 @@ static int eeh_event_handler(void * dummy)
         struct eeh_event *event;
         struct eeh_pe *pe;
 
-        spin_lock_irqsave(&eeh_eventlist_lock, flags);
-        event = NULL;
-
-        /* Unqueue the event, get ready to process. */
-        if (!list_empty(&eeh_eventlist)) {
-                event = list_entry(eeh_eventlist.next, struct eeh_event, list);
-                list_del(&event->list);
-        }
-        spin_unlock_irqrestore(&eeh_eventlist_lock, flags);
-
-        if (event == NULL)
-                return 0;
-
-        /* Serialize processing of EEH events */
-        mutex_lock(&eeh_event_mutex);
-        pe = event->pe;
-        eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
-        pr_info("EEH: Detected PCI bus error on PHB#%d-PE#%x\n",
-                pe->phb->global_number, pe->addr);
-
-        set_current_state(TASK_INTERRUPTIBLE);  /* Don't add to load average */
-        eeh_handle_event(pe);
-        eeh_pe_state_clear(pe, EEH_PE_RECOVERING);
-
-        kfree(event);
-        mutex_unlock(&eeh_event_mutex);
-
-        /* If there are no new errors after an hour, clear the counter. */
-        if (pe && pe->freeze_count > 0) {
-                msleep_interruptible(3600*1000);
-                if (pe->freeze_count > 0)
-                        pe->freeze_count--;
-
+        while (!kthread_should_stop()) {
+                if (down_interruptible(&eeh_eventlist_sem))
+                        break;
+
+                /* Fetch EEH event from the queue */
+                spin_lock_irqsave(&eeh_eventlist_lock, flags);
+                event = NULL;
+                if (!list_empty(&eeh_eventlist)) {
+                        event = list_entry(eeh_eventlist.next,
+                                           struct eeh_event, list);
+                        list_del(&event->list);
+                }
+                spin_unlock_irqrestore(&eeh_eventlist_lock, flags);
+                if (!event)
+                        continue;
+
+                /* We might have event without binding PE */
+                pe = event->pe;
+                if (pe) {
+                        eeh_pe_state_mark(pe, EEH_PE_RECOVERING);
+                        pr_info("EEH: Detected PCI bus error on PHB#%d-PE#%x\n",
+                                 pe->phb->global_number, pe->addr);
+                        eeh_handle_event(pe);
+                        eeh_pe_state_clear(pe, EEH_PE_RECOVERING);
+                } else {
+                        eeh_handle_event(NULL);
+                }
+
+                kfree(event);
         }
 
         return 0;
 }
 
 /**
- * eeh_thread_launcher - Start kernel thread to handle EEH events
- * @dummy - unused
+ * eeh_event_init - Start kernel thread to handle EEH events
  *
  * This routine is called to start the kernel thread for processing
  * EEH event.
  */
-static void eeh_thread_launcher(struct work_struct *dummy)
+int eeh_event_init(void)
 {
-        if (IS_ERR(kthread_run(eeh_event_handler, NULL, "eehd")))
-                printk(KERN_ERR "Failed to start EEH daemon\n");
+        struct task_struct *t;
+        int ret = 0;
+
+        /* Initialize semaphore */
+        sema_init(&eeh_eventlist_sem, 0);
+
+        t = kthread_run(eeh_event_handler, NULL, "eehd");
+        if (IS_ERR(t)) {
+                ret = PTR_ERR(t);
+                pr_err("%s: Failed to start EEH daemon (%d)\n",
+                        __func__, ret);
+                return ret;
+        }
+
+        return 0;
 }
 
 /**
@@ -136,7 +138,45 @@ int eeh_send_failure_event(struct eeh_pe *pe)
         list_add(&event->list, &eeh_eventlist);
         spin_unlock_irqrestore(&eeh_eventlist_lock, flags);
 
-        schedule_work(&eeh_event_wq);
+        /* For EEH deamon to knick in */
+        up(&eeh_eventlist_sem);
 
         return 0;
 }
+
+/**
+ * eeh_remove_event - Remove EEH event from the queue
+ * @pe: Event binding to the PE
+ *
+ * On PowerNV platform, we might have subsequent coming events
+ * is part of the former one. For that case, those subsequent
+ * coming events are totally duplicated and unnecessary, thus
+ * they should be removed.
+ */
+void eeh_remove_event(struct eeh_pe *pe)
+{
+        unsigned long flags;
+        struct eeh_event *event, *tmp;
+
+        spin_lock_irqsave(&eeh_eventlist_lock, flags);
+        list_for_each_entry_safe(event, tmp, &eeh_eventlist, list) {
+                /*
+                 * If we don't have valid PE passed in, that means
+                 * we already have event corresponding to dead IOC
+                 * and all events should be purged.
+                 */
+                if (!pe) {
+                        list_del(&event->list);
+                        kfree(event);
+                } else if (pe->type & EEH_PE_PHB) {
+                        if (event->pe && event->pe->phb == pe->phb) {
+                                list_del(&event->list);
+                                kfree(event);
+                        }
+                } else if (event->pe == pe) {
+                        list_del(&event->list);
+                        kfree(event);
+                }
+        }
+        spin_unlock_irqrestore(&eeh_eventlist_lock, flags);
+}
diff --git a/arch/powerpc/platforms/pseries/eeh_pe.c b/arch/powerpc/kernel/eeh_pe.c
index fe43d1aa2cf1..016588a6f5ed 100644
--- a/arch/powerpc/platforms/pseries/eeh_pe.c
+++ b/arch/powerpc/kernel/eeh_pe.c
@@ -22,6 +22,7 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
+#include <linux/delay.h>
 #include <linux/export.h>
 #include <linux/gfp.h>
 #include <linux/init.h>
@@ -78,9 +79,7 @@ int eeh_phb_pe_create(struct pci_controller *phb)
         }
 
         /* Put it into the list */
-        eeh_lock();
         list_add_tail(&pe->child, &eeh_phb_pe);
-        eeh_unlock();
 
         pr_debug("EEH: Add PE for PHB#%d\n", phb->global_number);
 
@@ -95,7 +94,7 @@ int eeh_phb_pe_create(struct pci_controller *phb)
  * hierarchy tree is composed of PHB PEs. The function is used
  * to retrieve the corresponding PHB PE according to the given PHB.
  */
-static struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
+struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb)
 {
         struct eeh_pe *pe;
 
@@ -185,21 +184,15 @@ void *eeh_pe_dev_traverse(struct eeh_pe *root,
                 return NULL;
         }
 
-        eeh_lock();
-
         /* Traverse root PE */
         for (pe = root; pe; pe = eeh_pe_next(pe, root)) {
                 eeh_pe_for_each_dev(pe, edev) {
                         ret = fn(edev, flag);
-                        if (ret) {
-                                eeh_unlock();
+                        if (ret)
                                 return ret;
-                        }
                 }
         }
 
-        eeh_unlock();
-
         return NULL;
 }
 
@@ -228,7 +221,7 @@ static void *__eeh_pe_get(void *data, void *flag)
                 return pe;
 
         /* Try BDF address */
-        if (edev->pe_config_addr &&
+        if (edev->config_addr &&
            (edev->config_addr == pe->config_addr))
                 return pe;
 
@@ -246,7 +239,7 @@ static void *__eeh_pe_get(void *data, void *flag)
  * which is composed of PCI bus/device/function number, or unified
  * PE address.
  */
-static struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
+struct eeh_pe *eeh_pe_get(struct eeh_dev *edev)
 {
         struct eeh_pe *root = eeh_phb_pe_get(edev->phb);
         struct eeh_pe *pe;
@@ -305,8 +298,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
 {
         struct eeh_pe *pe, *parent;
 
-        eeh_lock();
-
         /*
          * Search the PE has been existing or not according
          * to the PE address. If that has been existing, the
@@ -316,7 +307,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
         pe = eeh_pe_get(edev);
         if (pe && !(pe->type & EEH_PE_INVALID)) {
                 if (!edev->pe_config_addr) {
-                        eeh_unlock();
                         pr_err("%s: PE with addr 0x%x already exists\n",
                                 __func__, edev->config_addr);
                         return -EEXIST;
@@ -328,7 +318,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
 
                 /* Put the edev to PE */
                 list_add_tail(&edev->list, &pe->edevs);
-                eeh_unlock();
                 pr_debug("EEH: Add %s to Bus PE#%x\n",
                         edev->dn->full_name, pe->addr);
 
@@ -347,7 +336,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
                         parent->type &= ~EEH_PE_INVALID;
                         parent = parent->parent;
                 }
-                eeh_unlock();
                 pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
                         edev->dn->full_name, pe->addr, pe->parent->addr);
 
@@ -357,7 +345,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
         /* Create a new EEH PE */
         pe = eeh_pe_alloc(edev->phb, EEH_PE_DEVICE);
         if (!pe) {
-                eeh_unlock();
                 pr_err("%s: out of memory!\n", __func__);
                 return -ENOMEM;
         }
@@ -365,6 +352,17 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
         pe->config_addr = edev->config_addr;
 
         /*
+         * While doing PE reset, we probably hot-reset the
+         * upstream bridge. However, the PCI devices including
+         * the associated EEH devices might be removed when EEH
+         * core is doing recovery. So that won't safe to retrieve
+         * the bridge through downstream EEH device. We have to
+         * trace the parent PCI bus, then the upstream bridge.
+         */
+        if (eeh_probe_mode_dev())
+                pe->bus = eeh_dev_to_pci_dev(edev)->bus;
+
+        /*
          * Put the new EEH PE into hierarchy tree. If the parent
          * can't be found, the newly created PE will be attached
          * to PHB directly. Otherwise, we have to associate the
@@ -374,7 +372,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
         if (!parent) {
                 parent = eeh_phb_pe_get(edev->phb);
                 if (!parent) {
-                        eeh_unlock();
                         pr_err("%s: No PHB PE is found (PHB Domain=%d)\n",
                                 __func__, edev->phb->global_number);
                         edev->pe = NULL;
@@ -391,7 +388,6 @@ int eeh_add_to_parent_pe(struct eeh_dev *edev)
         list_add_tail(&pe->child, &parent->child_list);
         list_add_tail(&edev->list, &pe->edevs);
         edev->pe = pe;
-        eeh_unlock();
         pr_debug("EEH: Add %s to Device PE#%x, Parent PE#%x\n",
                 edev->dn->full_name, pe->addr, pe->parent->addr);
 
@@ -419,8 +415,6 @@ int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe)
                 return -EEXIST;
         }
 
-        eeh_lock();
-
         /* Remove the EEH device */
         pe = edev->pe;
         edev->pe = NULL;
@@ -465,12 +459,37 @@ int eeh_rmv_from_parent_pe(struct eeh_dev *edev, int purge_pe)
                 pe = parent;
         }
 
-        eeh_unlock();
-
         return 0;
 }
 
 /**
+ * eeh_pe_update_time_stamp - Update PE's frozen time stamp
+ * @pe: EEH PE
+ *
+ * We have time stamp for each PE to trace its time of getting
+ * frozen in last hour. The function should be called to update
+ * the time stamp on first error of the specific PE. On the other
+ * handle, we needn't account for errors happened in last hour.
+ */
+void eeh_pe_update_time_stamp(struct eeh_pe *pe)
+{
+        struct timeval tstamp;
+
+        if (!pe) return;
+
+        if (pe->freeze_count <= 0) {
+                pe->freeze_count = 0;
+                do_gettimeofday(&pe->tstamp);
+        } else {
+                do_gettimeofday(&tstamp);
+                if (tstamp.tv_sec - pe->tstamp.tv_sec > 3600) {
+                        pe->tstamp = tstamp;
+                        pe->freeze_count = 0;
+                }
+        }
+}
+
+/**
  * __eeh_pe_state_mark - Mark the state for the PE
  * @data: EEH PE
  * @flag: state
@@ -512,9 +531,7 @@ static void *__eeh_pe_state_mark(void *data, void *flag)
  */
 void eeh_pe_state_mark(struct eeh_pe *pe, int state)
 {
-        eeh_lock();
         eeh_pe_traverse(pe, __eeh_pe_state_mark, &state);
-        eeh_unlock();
 }
 
 /**
@@ -548,35 +565,135 @@ static void *__eeh_pe_state_clear(void *data, void *flag)
  */
 void eeh_pe_state_clear(struct eeh_pe *pe, int state)
 {
-        eeh_lock();
         eeh_pe_traverse(pe, __eeh_pe_state_clear, &state);
-        eeh_unlock();
 }
 
-/**
- * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
- * @data: EEH device
- * @flag: Unused
+/*
+ * Some PCI bridges (e.g. PLX bridges) have primary/secondary
+ * buses assigned explicitly by firmware, and we probably have
+ * lost that after reset. So we have to delay the check until
+ * the PCI-CFG registers have been restored for the parent
+ * bridge.
  *
- * Loads the PCI configuration space base address registers,
- * the expansion ROM base address, the latency timer, and etc.
- * from the saved values in the device node.
+ * Don't use normal PCI-CFG accessors, which probably has been
+ * blocked on normal path during the stage. So we need utilize
+ * eeh operations, which is always permitted.
  */
-static void *eeh_restore_one_device_bars(void *data, void *flag)
+static void eeh_bridge_check_link(struct pci_dev *pdev,
+                                  struct device_node *dn)
+{
+        int cap;
+        uint32_t val;
+        int timeout = 0;
+
+        /*
+         * We only check root port and downstream ports of
+         * PCIe switches
+         */
+        if (!pci_is_pcie(pdev) ||
+            (pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT &&
+             pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM))
+                return;
+
+        pr_debug("%s: Check PCIe link for %s ...\n",
+                 __func__, pci_name(pdev));
+
+        /* Check slot status */
+        cap = pdev->pcie_cap;
+        eeh_ops->read_config(dn, cap + PCI_EXP_SLTSTA, 2, &val);
+        if (!(val & PCI_EXP_SLTSTA_PDS)) {
+                pr_debug("  No card in the slot (0x%04x) !\n", val);
+                return;
+        }
+
+        /* Check power status if we have the capability */
+        eeh_ops->read_config(dn, cap + PCI_EXP_SLTCAP, 2, &val);
+        if (val & PCI_EXP_SLTCAP_PCP) {
+                eeh_ops->read_config(dn, cap + PCI_EXP_SLTCTL, 2, &val);
+                if (val & PCI_EXP_SLTCTL_PCC) {
+                        pr_debug("  In power-off state, power it on ...\n");
+                        val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC);
+                        val |= (0x0100 & PCI_EXP_SLTCTL_PIC);
+                        eeh_ops->write_config(dn, cap + PCI_EXP_SLTCTL, 2, val);
+                        msleep(2 * 1000);
+                }
+        }
+
+        /* Enable link */
+        eeh_ops->read_config(dn, cap + PCI_EXP_LNKCTL, 2, &val);
+        val &= ~PCI_EXP_LNKCTL_LD;
+        eeh_ops->write_config(dn, cap + PCI_EXP_LNKCTL, 2, val);
+
+        /* Check link */
+        eeh_ops->read_config(dn, cap + PCI_EXP_LNKCAP, 4, &val);
+        if (!(val & PCI_EXP_LNKCAP_DLLLARC)) {
+                pr_debug("  No link reporting capability (0x%08x) \n", val);
+                msleep(1000);
+                return;
+        }
+
+        /* Wait the link is up until timeout (5s) */
+        timeout = 0;
+        while (timeout < 5000) {
+                msleep(20);
+                timeout += 20;
+
+                eeh_ops->read_config(dn, cap + PCI_EXP_LNKSTA, 2, &val);
+                if (val & PCI_EXP_LNKSTA_DLLLA)
+                        break;
+        }
+
+        if (val & PCI_EXP_LNKSTA_DLLLA)
+                pr_debug("  Link up (%s)\n",
+                         (val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB");
+        else
+                pr_debug("  Link not ready (0x%04x)\n", val);
+}
+
+#define BYTE_SWAP(OFF)  (8*((OFF)/4)+3-(OFF))
+#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
+
+static void eeh_restore_bridge_bars(struct pci_dev *pdev,
+                                    struct eeh_dev *edev,
+                                    struct device_node *dn)
+{
+        int i;
+
+        /*
+         * Device BARs: 0x10 - 0x18
+         * Bus numbers and windows: 0x18 - 0x30
+         */
+        for (i = 4; i < 13; i++)
+                eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
+        /* Rom: 0x38 */
+        eeh_ops->write_config(dn, 14*4, 4, edev->config_space[14]);
+
+        /* Cache line & Latency timer: 0xC 0xD */
+        eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
+                SAVED_BYTE(PCI_CACHE_LINE_SIZE));
+        eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
+                SAVED_BYTE(PCI_LATENCY_TIMER));
+        /* Max latency, min grant, interrupt ping and line: 0x3C */
+        eeh_ops->write_config(dn, 15*4, 4, edev->config_space[15]);
+
+        /* PCI Command: 0x4 */
+        eeh_ops->write_config(dn, PCI_COMMAND, 4, edev->config_space[1]);
+
+        /* Check the PCIe link is ready */
+        eeh_bridge_check_link(pdev, dn);
+}
+
+static void eeh_restore_device_bars(struct eeh_dev *edev,
+                                    struct device_node *dn)
 {
         int i;
         u32 cmd;
-        struct eeh_dev *edev = (struct eeh_dev *)data;
-        struct device_node *dn = eeh_dev_to_of_node(edev);
 
         for (i = 4; i < 10; i++)
                 eeh_ops->write_config(dn, i*4, 4, edev->config_space[i]);
         /* 12 == Expansion ROM Address */
         eeh_ops->write_config(dn, 12*4, 4, edev->config_space[12]);
 
-#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
-#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)])
-
         eeh_ops->write_config(dn, PCI_CACHE_LINE_SIZE, 1,
                 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
         eeh_ops->write_config(dn, PCI_LATENCY_TIMER, 1,
@@ -599,6 +716,34 @@ static void *eeh_restore_one_device_bars(void *data, void *flag)
         else
                 cmd &= ~PCI_COMMAND_SERR;
         eeh_ops->write_config(dn, PCI_COMMAND, 4, cmd);
+}
+
+/**
+ * eeh_restore_one_device_bars - Restore the Base Address Registers for one device
+ * @data: EEH device
+ * @flag: Unused
+ *
+ * Loads the PCI configuration space base address registers,
+ * the expansion ROM base address, the latency timer, and etc.
+ * from the saved values in the device node.
+ */
+static void *eeh_restore_one_device_bars(void *data, void *flag)
+{
+        struct pci_dev *pdev = NULL;
+        struct eeh_dev *edev = (struct eeh_dev *)data;
+        struct device_node *dn = eeh_dev_to_of_node(edev);
+
+        /* Trace the PCI bridge */
+        if (eeh_probe_mode_dev()) {
+                pdev = eeh_dev_to_pci_dev(edev);
+                if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
+                        pdev = NULL;
+        }
+
+        if (pdev)
+                eeh_restore_bridge_bars(pdev, edev, dn);
+        else
+                eeh_restore_device_bars(edev, dn);
 
         return NULL;
 }
@@ -635,18 +780,21 @@ struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe)
         struct eeh_dev *edev;
         struct pci_dev *pdev;
 
-        eeh_lock();
-
         if (pe->type & EEH_PE_PHB) {
                 bus = pe->phb->bus;
-        } else if (pe->type & EEH_PE_BUS) {
+        } else if (pe->type & EEH_PE_BUS ||
+                   pe->type & EEH_PE_DEVICE) {
+                if (pe->bus) {
+                        bus = pe->bus;
+                        goto out;
+                }
+
                 edev = list_first_entry(&pe->edevs, struct eeh_dev, list);
                 pdev = eeh_dev_to_pci_dev(edev);
                 if (pdev)
                         bus = pdev->bus;
         }
 
-        eeh_unlock();
-
+out:
         return bus;
 }
diff --git a/arch/powerpc/platforms/pseries/eeh_sysfs.c b/arch/powerpc/kernel/eeh_sysfs.c
index d37708360f2e..e7ae3484918c 100644
--- a/arch/powerpc/platforms/pseries/eeh_sysfs.c
+++ b/arch/powerpc/kernel/eeh_sysfs.c
@@ -72,4 +72,3 @@ void eeh_sysfs_remove_device(struct pci_dev *pdev)
         device_remove_file(&pdev->dev, &dev_attr_eeh_config_addr);
         device_remove_file(&pdev->dev, &dev_attr_eeh_pe_config_addr);
 }
-
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 246b11c4fe7e..ab15b8d057ad 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -465,20 +465,6 @@ BEGIN_FTR_SECTION
         std     r0, THREAD_EBBHR(r3)
         mfspr   r0, SPRN_EBBRR
         std     r0, THREAD_EBBRR(r3)
-
-        /* PMU registers made user read/(write) by EBB */
-        mfspr   r0, SPRN_SIAR
-        std     r0, THREAD_SIAR(r3)
-        mfspr   r0, SPRN_SDAR
-        std     r0, THREAD_SDAR(r3)
-        mfspr   r0, SPRN_SIER
-        std     r0, THREAD_SIER(r3)
-        mfspr   r0, SPRN_MMCR0
-        std     r0, THREAD_MMCR0(r3)
-        mfspr   r0, SPRN_MMCR2
-        std     r0, THREAD_MMCR2(r3)
-        mfspr   r0, SPRN_MMCRA
-        std     r0, THREAD_MMCRA(r3)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 #endif
 
@@ -581,20 +567,6 @@ BEGIN_FTR_SECTION
         ld      r0, THREAD_EBBRR(r4)
         mtspr   SPRN_EBBRR, r0
 
-        /* PMU registers made user read/(write) by EBB */
-        ld      r0, THREAD_SIAR(r4)
-        mtspr   SPRN_SIAR, r0
-        ld      r0, THREAD_SDAR(r4)
-        mtspr   SPRN_SDAR, r0
-        ld      r0, THREAD_SIER(r4)
-        mtspr   SPRN_SIER, r0
-        ld      r0, THREAD_MMCR0(r4)
-        mtspr   SPRN_MMCR0, r0
-        ld      r0, THREAD_MMCR2(r4)
-        mtspr   SPRN_MMCR2, r0
-        ld      r0, THREAD_MMCRA(r4)
-        mtspr   SPRN_MMCRA, r0
-
         ld      r0,THREAD_TAR(r4)
         mtspr   SPRN_TAR,r0
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
@@ -657,21 +629,43 @@ _GLOBAL(ret_from_except_lite)
 
         CURRENT_THREAD_INFO(r9, r1)
         ld      r3,_MSR(r1)
+#ifdef CONFIG_PPC_BOOK3E
+        ld      r10,PACACURRENT(r13)
+#endif /* CONFIG_PPC_BOOK3E */
         ld      r4,TI_FLAGS(r9)
         andi.   r3,r3,MSR_PR
         beq     resume_kernel
+#ifdef CONFIG_PPC_BOOK3E
+        lwz     r3,(THREAD+THREAD_DBCR0)(r10)
+#endif /* CONFIG_PPC_BOOK3E */
 
         /* Check current_thread_info()->flags */
         andi.   r0,r4,_TIF_USER_WORK_MASK
+#ifdef CONFIG_PPC_BOOK3E
+        bne     1f
+        /*
+         * Check to see if the dbcr0 register is set up to debug.
+         * Use the internal debug mode bit to do this.
+         */
+        andis.  r0,r3,DBCR0_IDM@h
         beq     restore
-
-        andi.   r0,r4,_TIF_NEED_RESCHED
-        beq     1f
+        mfmsr   r0
+        rlwinm  r0,r0,0,~MSR_DE /* Clear MSR.DE */
+        mtmsr   r0
+        mtspr   SPRN_DBCR0,r3
+        li      r10, -1
+        mtspr   SPRN_DBSR,r10
+        b       restore
+#else
+        beq     restore
+#endif
+1:      andi.   r0,r4,_TIF_NEED_RESCHED
+        beq     2f
         bl      .restore_interrupts
         SCHEDULE_USER
         b       .ret_from_except_lite
 
-1:      bl      .save_nvgprs
+2:      bl      .save_nvgprs
         bl      .restore_interrupts
         addi    r3,r1,STACK_FRAME_OVERHEAD
         bl      .do_notify_resume
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index e6eba1bf61ad..4e00d223b2e3 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -341,10 +341,17 @@ vsx_unavailable_pSeries_1:
         EXCEPTION_PROLOG_0(PACA_EXGEN)
         b       vsx_unavailable_pSeries
 
+facility_unavailable_trampoline:
         . = 0xf60
         SET_SCRATCH0(r13)
         EXCEPTION_PROLOG_0(PACA_EXGEN)
-        b       tm_unavailable_pSeries
+        b       facility_unavailable_pSeries
+
+hv_facility_unavailable_trampoline:
+        . = 0xf80
+        SET_SCRATCH0(r13)
+        EXCEPTION_PROLOG_0(PACA_EXGEN)
+        b       facility_unavailable_hv
 
 #ifdef CONFIG_CBE_RAS
         STD_EXCEPTION_HV(0x1200, 0x1202, cbe_system_error)
@@ -454,38 +461,14 @@ BEGIN_FTR_SECTION
         xori    r10,r10,(MSR_FE0|MSR_FE1)
         mtmsrd  r10
         sync
-        fmr     0,0
-        fmr     1,1
-        fmr     2,2
-        fmr     3,3
-        fmr     4,4
-        fmr     5,5
-        fmr     6,6
-        fmr     7,7
-        fmr     8,8
-        fmr     9,9
-        fmr     10,10
-        fmr     11,11
-        fmr     12,12
-        fmr     13,13
-        fmr     14,14
-        fmr     15,15
-        fmr     16,16
-        fmr     17,17
-        fmr     18,18
-        fmr     19,19
-        fmr     20,20
-        fmr     21,21
-        fmr     22,22
-        fmr     23,23
-        fmr     24,24
-        fmr     25,25
-        fmr     26,26
-        fmr     27,27
-        fmr     28,28
-        fmr     29,29
-        fmr     30,30
-        fmr     31,31
+
+#define FMR2(n)  fmr (n), (n) ; fmr n+1, n+1
+#define FMR4(n)  FMR2(n) ; FMR2(n+2)
+#define FMR8(n)  FMR4(n) ; FMR4(n+4)
+#define FMR16(n) FMR8(n) ; FMR8(n+8)
+#define FMR32(n) FMR16(n) ; FMR16(n+16)
+        FMR32(0)
+
 FTR_SECTION_ELSE
 /*
  * To denormalise we need to move a copy of the register to itself.
@@ -495,39 +478,25 @@ FTR_SECTION_ELSE
         oris    r10,r10,MSR_VSX@h
         mtmsrd  r10
         sync
-        XVCPSGNDP(0,0,0)
-        XVCPSGNDP(1,1,1)
-        XVCPSGNDP(2,2,2)
-        XVCPSGNDP(3,3,3)
-        XVCPSGNDP(4,4,4)
-        XVCPSGNDP(5,5,5)
-        XVCPSGNDP(6,6,6)
-        XVCPSGNDP(7,7,7)
-        XVCPSGNDP(8,8,8)
-        XVCPSGNDP(9,9,9)
-        XVCPSGNDP(10,10,10)
-        XVCPSGNDP(11,11,11)
-        XVCPSGNDP(12,12,12)
-        XVCPSGNDP(13,13,13)
-        XVCPSGNDP(14,14,14)
-        XVCPSGNDP(15,15,15)
-        XVCPSGNDP(16,16,16)
-        XVCPSGNDP(17,17,17)
-        XVCPSGNDP(18,18,18)
-        XVCPSGNDP(19,19,19)
-        XVCPSGNDP(20,20,20)
-        XVCPSGNDP(21,21,21)
-        XVCPSGNDP(22,22,22)
-        XVCPSGNDP(23,23,23)
-        XVCPSGNDP(24,24,24)
-        XVCPSGNDP(25,25,25)
-        XVCPSGNDP(26,26,26)
-        XVCPSGNDP(27,27,27)
-        XVCPSGNDP(28,28,28)
-        XVCPSGNDP(29,29,29)
-        XVCPSGNDP(30,30,30)
-        XVCPSGNDP(31,31,31)
+
+#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
+#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
+#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
+#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
+#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
+        XVCPSGNDP32(0)
+
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+
+BEGIN_FTR_SECTION
+        b       denorm_done
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER8 we need to do that for all 64 VSX registers
+ */
+        XVCPSGNDP32(32)
+denorm_done:
         mtspr   SPRN_HSRR0,r11
         mtcrf   0x80,r9
         ld      r9,PACA_EXGEN+EX_R9(r13)
@@ -560,8 +529,10 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf20)
         STD_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf40)
-        STD_EXCEPTION_PSERIES_OOL(0xf60, tm_unavailable)
+        STD_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xf60)
+        STD_EXCEPTION_HV_OOL(0xf82, facility_unavailable)
+        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xf82)
 
 /*
  * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
@@ -721,7 +692,7 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
         STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
-        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception)
+        STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
 #ifdef CONFIG_PPC_DOORBELL
         STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
@@ -831,14 +802,10 @@ system_call_relon_pSeries:
         STD_RELON_EXCEPTION_PSERIES(0x4d00, 0xd00, single_step)
 
         . = 0x4e00
-        SET_SCRATCH0(r13)
-        EXCEPTION_PROLOG_0(PACA_EXGEN)
-        b       h_data_storage_relon_hv
+        b       .       /* Can't happen, see v2.07 Book III-S section 6.5 */
 
         . = 0x4e20
-        SET_SCRATCH0(r13)
-        EXCEPTION_PROLOG_0(PACA_EXGEN)
-        b       h_instr_storage_relon_hv
+        b       .       /* Can't happen, see v2.07 Book III-S section 6.5 */
 
         . = 0x4e40
         SET_SCRATCH0(r13)
@@ -846,9 +813,7 @@ system_call_relon_pSeries:
         b       emulation_assist_relon_hv
 
         . = 0x4e60
-        SET_SCRATCH0(r13)
-        EXCEPTION_PROLOG_0(PACA_EXGEN)
-        b       hmi_exception_relon_hv
+        b       .       /* Can't happen, see v2.07 Book III-S section 6.5 */
 
         . = 0x4e80
         SET_SCRATCH0(r13)
@@ -873,11 +838,17 @@ vsx_unavailable_relon_pSeries_1:
         EXCEPTION_PROLOG_0(PACA_EXGEN)
         b       vsx_unavailable_relon_pSeries
 
-tm_unavailable_relon_pSeries_1:
+facility_unavailable_relon_trampoline:
         . = 0x4f60
         SET_SCRATCH0(r13)
         EXCEPTION_PROLOG_0(PACA_EXGEN)
-        b       tm_unavailable_relon_pSeries
+        b       facility_unavailable_relon_pSeries
+
+hv_facility_unavailable_relon_trampoline:
+        . = 0x4f80
+        SET_SCRATCH0(r13)
+        EXCEPTION_PROLOG_0(PACA_EXGEN)
+        b       facility_unavailable_relon_hv
 
         STD_RELON_EXCEPTION_PSERIES(0x5300, 0x1300, instruction_breakpoint)
 #ifdef CONFIG_PPC_DENORMALISATION
@@ -1203,36 +1174,21 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
         bl      .vsx_unavailable_exception
         b       .ret_from_except
 
-        .align  7
-        .globl tm_unavailable_common
-tm_unavailable_common:
-        EXCEPTION_PROLOG_COMMON(0xf60, PACA_EXGEN)
-        bl      .save_nvgprs
-        DISABLE_INTS
-        addi    r3,r1,STACK_FRAME_OVERHEAD
-        bl      .tm_unavailable_exception
-        b       .ret_from_except
+        STD_EXCEPTION_COMMON(0xf60, facility_unavailable, .facility_unavailable_exception)
 
         .align  7
         .globl  __end_handlers
 __end_handlers:
 
         /* Equivalents to the above handlers for relocation-on interrupt vectors */
-        STD_RELON_EXCEPTION_HV_OOL(0xe00, h_data_storage)
-        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe00)
-        STD_RELON_EXCEPTION_HV_OOL(0xe20, h_instr_storage)
-        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe20)
         STD_RELON_EXCEPTION_HV_OOL(0xe40, emulation_assist)
-        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe40)
-        STD_RELON_EXCEPTION_HV_OOL(0xe60, hmi_exception)
-        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe60)
         MASKABLE_RELON_EXCEPTION_HV_OOL(0xe80, h_doorbell)
-        KVM_HANDLER(PACA_EXGEN, EXC_HV, 0xe80)
 
         STD_RELON_EXCEPTION_PSERIES_OOL(0xf00, performance_monitor)
         STD_RELON_EXCEPTION_PSERIES_OOL(0xf20, altivec_unavailable)
         STD_RELON_EXCEPTION_PSERIES_OOL(0xf40, vsx_unavailable)
-        STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, tm_unavailable)
+        STD_RELON_EXCEPTION_PSERIES_OOL(0xf60, facility_unavailable)
+        STD_RELON_EXCEPTION_HV_OOL(0xf80, facility_unavailable)
 
 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
 /*
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index a949bdfc9623..f0b47d1a6b0e 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -176,7 +176,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
                 length_max = 512 ; /* 64 doublewords */
                 /* DAWR region can't cross 512 boundary */
                 if ((bp->attr.bp_addr >> 10) != 
-                    ((bp->attr.bp_addr + bp->attr.bp_len) >> 10))
+                    ((bp->attr.bp_addr + bp->attr.bp_len - 1) >> 10))
                         return -EINVAL;
         }
         if (info->len >
@@ -250,6 +250,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
          * we still need to single-step the instruction, but we don't
          * generate an event.
          */
+        info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
         if (!((bp->attr.bp_addr <= dar) &&
               (dar - bp->attr.bp_addr < bp->attr.bp_len)))
                 info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
diff --git a/arch/powerpc/kernel/ibmebus.c b/arch/powerpc/kernel/ibmebus.c
index 8220baa46faf..16a7c2326d48 100644
--- a/arch/powerpc/kernel/ibmebus.c
+++ b/arch/powerpc/kernel/ibmebus.c
@@ -205,7 +205,7 @@ static int ibmebus_create_devices(const struct of_device_id *matches)
         return ret;
 }
 
-int ibmebus_register_driver(struct of_platform_driver *drv)
+int ibmebus_register_driver(struct platform_driver *drv)
 {
         /* If the driver uses devices that ibmebus doesn't know, add them */
         ibmebus_create_devices(drv->driver.of_match_table);
@@ -215,7 +215,7 @@ int ibmebus_register_driver(struct of_platform_driver *drv)
 }
 EXPORT_SYMBOL(ibmebus_register_driver);
 
-void ibmebus_unregister_driver(struct of_platform_driver *drv)
+void ibmebus_unregister_driver(struct platform_driver *drv)
 {
         driver_unregister(&drv->driver);
 }
@@ -338,11 +338,10 @@ static int ibmebus_bus_bus_match(struct device *dev, struct device_driver *drv)
 static int ibmebus_bus_device_probe(struct device *dev)
 {
         int error = -ENODEV;
-        struct of_platform_driver *drv;
+        struct platform_driver *drv;
         struct platform_device *of_dev;
-        const struct of_device_id *match;
 
-        drv = to_of_platform_driver(dev->driver);
+        drv = to_platform_driver(dev->driver);
         of_dev = to_platform_device(dev);
 
         if (!drv->probe)
@@ -350,9 +349,8 @@ static int ibmebus_bus_device_probe(struct device *dev)
 
         of_dev_get(of_dev);
 
-        match = of_match_device(drv->driver.of_match_table, dev);
-        if (match)
-                error = drv->probe(of_dev, match);
+        if (of_driver_match_device(dev, dev->driver))
+                error = drv->probe(of_dev);
         if (error)
                 of_dev_put(of_dev);
 
@@ -362,7 +360,7 @@ static int ibmebus_bus_device_probe(struct device *dev)
 static int ibmebus_bus_device_remove(struct device *dev)
 {
         struct platform_device *of_dev = to_platform_device(dev);
-        struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+        struct platform_driver *drv = to_platform_driver(dev->driver);
 
         if (dev->driver && drv->remove)
                 drv->remove(of_dev);
@@ -372,7 +370,7 @@ static int ibmebus_bus_device_remove(struct device *dev)
 static void ibmebus_bus_device_shutdown(struct device *dev)
 {
         struct platform_device *of_dev = to_platform_device(dev);
-        struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+        struct platform_driver *drv = to_platform_driver(dev->driver);
 
         if (dev->driver && drv->shutdown)
                 drv->shutdown(of_dev);
@@ -419,7 +417,7 @@ struct device_attribute ibmebus_bus_device_attrs[] = {
 static int ibmebus_bus_legacy_suspend(struct device *dev, pm_message_t mesg)
 {
         struct platform_device *of_dev = to_platform_device(dev);
-        struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+        struct platform_driver *drv = to_platform_driver(dev->driver);
         int ret = 0;
 
         if (dev->driver && drv->suspend)
@@ -430,7 +428,7 @@ static int ibmebus_bus_legacy_suspend(struct device *dev, pm_message_t mesg)
 static int ibmebus_bus_legacy_resume(struct device *dev)
 {
         struct platform_device *of_dev = to_platform_device(dev);
-        struct of_platform_driver *drv = to_of_platform_driver(dev->driver);
+        struct platform_driver *drv = to_platform_driver(dev->driver);
         int ret = 0;
 
         if (dev->driver && drv->resume)
diff --git a/arch/powerpc/kernel/idle.c b/arch/powerpc/kernel/idle.c
index 939ea7ef0dc8..d7216c9abda1 100644
--- a/arch/powerpc/kernel/idle.c
+++ b/arch/powerpc/kernel/idle.c
@@ -85,7 +85,7 @@ int powersave_nap;
 /*
  * Register the sysctl to set/clear powersave_nap.
  */
-static ctl_table powersave_nap_ctl_table[]={
+static struct ctl_table powersave_nap_ctl_table[] = {
         {
                 .procname       = "powersave-nap",
                 .data           = &powersave_nap,
@@ -95,7 +95,7 @@ static ctl_table powersave_nap_ctl_table[]={
         },
         {}
 };
-static ctl_table powersave_nap_sysctl_root[] = {
+static struct ctl_table powersave_nap_sysctl_root[] = {
         {
                 .procname       = "kernel",
                 .mode           = 0555,
diff --git a/arch/powerpc/kernel/io-workarounds.c b/arch/powerpc/kernel/io-workarounds.c
index 50e90b7e7139..fa0b54b2a362 100644
--- a/arch/powerpc/kernel/io-workarounds.c
+++ b/arch/powerpc/kernel/io-workarounds.c
@@ -55,6 +55,7 @@ static struct iowa_bus *iowa_pci_find(unsigned long vaddr, unsigned long paddr)
 
 struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
 {
+        unsigned hugepage_shift;
         struct iowa_bus *bus;
         int token;
 
@@ -70,11 +71,17 @@ struct iowa_bus *iowa_mem_find_bus(const PCI_IO_ADDR addr)
                 if (vaddr < PHB_IO_BASE || vaddr >= PHB_IO_END)
                         return NULL;
 
-                ptep = find_linux_pte(init_mm.pgd, vaddr);
+                ptep = find_linux_pte_or_hugepte(init_mm.pgd, vaddr,
+                                                 &hugepage_shift);
                 if (ptep == NULL)
                         paddr = 0;
-                else
+                else {
+                        /*
+                         * we don't have hugepages backing iomem
+                         */
+                        WARN_ON(hugepage_shift);
                         paddr = pte_pfn(*ptep) << PAGE_SHIFT;
+                }
                 bus = iowa_pci_find(vaddr, paddr);
 
                 if (bus == NULL)
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index c0d0dbddfba1..b20ff173a671 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -36,6 +36,8 @@
 #include <linux/hash.h>
 #include <linux/fault-inject.h>
 #include <linux/pci.h>
+#include <linux/iommu.h>
+#include <linux/sched.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/iommu.h>
@@ -44,6 +46,7 @@
 #include <asm/kdump.h>
 #include <asm/fadump.h>
 #include <asm/vio.h>
+#include <asm/tce.h>
 
 #define DBG(...)
 
@@ -724,6 +727,13 @@ void iommu_free_table(struct iommu_table *tbl, const char *node_name)
         if (tbl->it_offset == 0)
                 clear_bit(0, tbl->it_map);
 
+#ifdef CONFIG_IOMMU_API
+        if (tbl->it_group) {
+                iommu_group_put(tbl->it_group);
+                BUG_ON(tbl->it_group);
+        }
+#endif
+
         /* verify that table contains no entries */
         if (!bitmap_empty(tbl->it_map, tbl->it_size))
                 pr_warn("%s: Unexpected TCEs for %s\n", __func__, node_name);
@@ -860,3 +870,316 @@ void iommu_free_coherent(struct iommu_table *tbl, size_t size,
                 free_pages((unsigned long)vaddr, get_order(size));
         }
 }
+
+#ifdef CONFIG_IOMMU_API
+/*
+ * SPAPR TCE API
+ */
+static void group_release(void *iommu_data)
+{
+        struct iommu_table *tbl = iommu_data;
+        tbl->it_group = NULL;
+}
+
+void iommu_register_group(struct iommu_table *tbl,
+                int pci_domain_number, unsigned long pe_num)
+{
+        struct iommu_group *grp;
+        char *name;
+
+        grp = iommu_group_alloc();
+        if (IS_ERR(grp)) {
+                pr_warn("powerpc iommu api: cannot create new group, err=%ld\n",
+                                PTR_ERR(grp));
+                return;
+        }
+        tbl->it_group = grp;
+        iommu_group_set_iommudata(grp, tbl, group_release);
+        name = kasprintf(GFP_KERNEL, "domain%d-pe%lx",
+                        pci_domain_number, pe_num);
+        if (!name)
+                return;
+        iommu_group_set_name(grp, name);
+        kfree(name);
+}
+
+enum dma_data_direction iommu_tce_direction(unsigned long tce)
+{
+        if ((tce & TCE_PCI_READ) && (tce & TCE_PCI_WRITE))
+                return DMA_BIDIRECTIONAL;
+        else if (tce & TCE_PCI_READ)
+                return DMA_TO_DEVICE;
+        else if (tce & TCE_PCI_WRITE)
+                return DMA_FROM_DEVICE;
+        else
+                return DMA_NONE;
+}
+EXPORT_SYMBOL_GPL(iommu_tce_direction);
+
+void iommu_flush_tce(struct iommu_table *tbl)
+{
+        /* Flush/invalidate TLB caches if necessary */
+        if (ppc_md.tce_flush)
+                ppc_md.tce_flush(tbl);
+
+        /* Make sure updates are seen by hardware */
+        mb();
+}
+EXPORT_SYMBOL_GPL(iommu_flush_tce);
+
+int iommu_tce_clear_param_check(struct iommu_table *tbl,
+                unsigned long ioba, unsigned long tce_value,
+                unsigned long npages)
+{
+        /* ppc_md.tce_free() does not support any value but 0 */
+        if (tce_value)
+                return -EINVAL;
+
+        if (ioba & ~IOMMU_PAGE_MASK)
+                return -EINVAL;
+
+        ioba >>= IOMMU_PAGE_SHIFT;
+        if (ioba < tbl->it_offset)
+                return -EINVAL;
+
+        if ((ioba + npages) > (tbl->it_offset + tbl->it_size))
+                return -EINVAL;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check);
+
+int iommu_tce_put_param_check(struct iommu_table *tbl,
+                unsigned long ioba, unsigned long tce)
+{
+        if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))
+                return -EINVAL;
+
+        if (tce & ~(IOMMU_PAGE_MASK | TCE_PCI_WRITE | TCE_PCI_READ))
+                return -EINVAL;
+
+        if (ioba & ~IOMMU_PAGE_MASK)
+                return -EINVAL;
+
+        ioba >>= IOMMU_PAGE_SHIFT;
+        if (ioba < tbl->it_offset)
+                return -EINVAL;
+
+        if ((ioba + 1) > (tbl->it_offset + tbl->it_size))
+                return -EINVAL;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);
+
+unsigned long iommu_clear_tce(struct iommu_table *tbl, unsigned long entry)
+{
+        unsigned long oldtce;
+        struct iommu_pool *pool = get_pool(tbl, entry);
+
+        spin_lock(&(pool->lock));
+
+        oldtce = ppc_md.tce_get(tbl, entry);
+        if (oldtce & (TCE_PCI_WRITE | TCE_PCI_READ))
+                ppc_md.tce_free(tbl, entry, 1);
+        else
+                oldtce = 0;
+
+        spin_unlock(&(pool->lock));
+
+        return oldtce;
+}
+EXPORT_SYMBOL_GPL(iommu_clear_tce);
+
+int iommu_clear_tces_and_put_pages(struct iommu_table *tbl,
+                unsigned long entry, unsigned long pages)
+{
+        unsigned long oldtce;
+        struct page *page;
+
+        for ( ; pages; --pages, ++entry) {
+                oldtce = iommu_clear_tce(tbl, entry);
+                if (!oldtce)
+                        continue;
+
+                page = pfn_to_page(oldtce >> PAGE_SHIFT);
+                WARN_ON(!page);
+                if (page) {
+                        if (oldtce & TCE_PCI_WRITE)
+                                SetPageDirty(page);
+                        put_page(page);
+                }
+        }
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_clear_tces_and_put_pages);
+
+/*
+ * hwaddr is a kernel virtual address here (0xc... bazillion),
+ * tce_build converts it to a physical address.
+ */
+int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,
+                unsigned long hwaddr, enum dma_data_direction direction)
+{
+        int ret = -EBUSY;
+        unsigned long oldtce;
+        struct iommu_pool *pool = get_pool(tbl, entry);
+
+        spin_lock(&(pool->lock));
+
+        oldtce = ppc_md.tce_get(tbl, entry);
+        /* Add new entry if it is not busy */
+        if (!(oldtce & (TCE_PCI_WRITE | TCE_PCI_READ)))
+                ret = ppc_md.tce_build(tbl, entry, 1, hwaddr, direction, NULL);
+
+        spin_unlock(&(pool->lock));
+
+        /* if (unlikely(ret))
+                pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
+                                __func__, hwaddr, entry << IOMMU_PAGE_SHIFT,
+                                hwaddr, ret); */
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(iommu_tce_build);
+
+int iommu_put_tce_user_mode(struct iommu_table *tbl, unsigned long entry,
+                unsigned long tce)
+{
+        int ret;
+        struct page *page = NULL;
+        unsigned long hwaddr, offset = tce & IOMMU_PAGE_MASK & ~PAGE_MASK;
+        enum dma_data_direction direction = iommu_tce_direction(tce);
+
+        ret = get_user_pages_fast(tce & PAGE_MASK, 1,
+                        direction != DMA_TO_DEVICE, &page);
+        if (unlikely(ret != 1)) {
+                /* pr_err("iommu_tce: get_user_pages_fast failed tce=%lx ioba=%lx ret=%d\n",
+                                tce, entry << IOMMU_PAGE_SHIFT, ret); */
+                return -EFAULT;
+        }
+        hwaddr = (unsigned long) page_address(page) + offset;
+
+        ret = iommu_tce_build(tbl, entry, hwaddr, direction);
+        if (ret)
+                put_page(page);
+
+        if (ret < 0)
+                pr_err("iommu_tce: %s failed ioba=%lx, tce=%lx, ret=%d\n",
+                                __func__, entry << IOMMU_PAGE_SHIFT, tce, ret);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(iommu_put_tce_user_mode);
+
+int iommu_take_ownership(struct iommu_table *tbl)
+{
+        unsigned long sz = (tbl->it_size + 7) >> 3;
+
+        if (tbl->it_offset == 0)
+                clear_bit(0, tbl->it_map);
+
+        if (!bitmap_empty(tbl->it_map, tbl->it_size)) {
+                pr_err("iommu_tce: it_map is not empty");
+                return -EBUSY;
+        }
+
+        memset(tbl->it_map, 0xff, sz);
+        iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_take_ownership);
+
+void iommu_release_ownership(struct iommu_table *tbl)
+{
+        unsigned long sz = (tbl->it_size + 7) >> 3;
+
+        iommu_clear_tces_and_put_pages(tbl, tbl->it_offset, tbl->it_size);
+        memset(tbl->it_map, 0, sz);
+
+        /* Restore bit#0 set by iommu_init_table() */
+        if (tbl->it_offset == 0)
+                set_bit(0, tbl->it_map);
+}
+EXPORT_SYMBOL_GPL(iommu_release_ownership);
+
+static int iommu_add_device(struct device *dev)
+{
+        struct iommu_table *tbl;
+        int ret = 0;
+
+        if (WARN_ON(dev->iommu_group)) {
+                pr_warn("iommu_tce: device %s is already in iommu group %d, skipping\n",
+                                dev_name(dev),
+                                iommu_group_id(dev->iommu_group));
+                return -EBUSY;
+        }
+
+        tbl = get_iommu_table_base(dev);
+        if (!tbl || !tbl->it_group) {
+                pr_debug("iommu_tce: skipping device %s with no tbl\n",
+                                dev_name(dev));
+                return 0;
+        }
+
+        pr_debug("iommu_tce: adding %s to iommu group %d\n",
+                        dev_name(dev), iommu_group_id(tbl->it_group));
+
+        ret = iommu_group_add_device(tbl->it_group, dev);
+        if (ret < 0)
+                pr_err("iommu_tce: %s has not been added, ret=%d\n",
+                                dev_name(dev), ret);
+
+        return ret;
+}
+
+static void iommu_del_device(struct device *dev)
+{
+        iommu_group_remove_device(dev);
+}
+
+static int iommu_bus_notifier(struct notifier_block *nb,
+                              unsigned long action, void *data)
+{
+        struct device *dev = data;
+
+        switch (action) {
+        case BUS_NOTIFY_ADD_DEVICE:
+                return iommu_add_device(dev);
+        case BUS_NOTIFY_DEL_DEVICE:
+                iommu_del_device(dev);
+                return 0;
+        default:
+                return 0;
+        }
+}
+
+static struct notifier_block tce_iommu_bus_nb = {
+        .notifier_call = iommu_bus_notifier,
+};
+
+static int __init tce_iommu_init(void)
+{
+        struct pci_dev *pdev = NULL;
+
+        BUILD_BUG_ON(PAGE_SIZE < IOMMU_PAGE_SIZE);
+
+        for_each_pci_dev(pdev)
+                iommu_add_device(&pdev->dev);
+
+        bus_register_notifier(&pci_bus_type, &tce_iommu_bus_nb);
+        return 0;
+}
+
+subsys_initcall_sync(tce_iommu_init);
+
+#else
+
+void iommu_register_group(struct iommu_table *tbl,
+                int pci_domain_number, unsigned long pe_num)
+{
+}
+
+#endif /* CONFIG_IOMMU_API */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5cbcf4d5a808..2e51cde616d2 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -116,8 +116,6 @@ static inline notrace int decrementer_check_overflow(void)
         u64 now = get_tb_or_rtc();
         u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
  
-        if (now >= *next_tb)
-                set_dec(1);
         return now >= *next_tb;
 }
 
@@ -162,7 +160,7 @@ notrace unsigned int __check_irq_replay(void)
          * in case we also had a rollover while hard disabled
          */
         local_paca->irq_happened &= ~PACA_IRQ_DEC;
-        if (decrementer_check_overflow())
+        if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
                 return 0x900;
 
         /* Finally check if an external interrupt happened */
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index 11f5b03a0b06..2156ea90eb54 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -36,12 +36,6 @@
 #include <asm/sstep.h>
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-#define MSR_SINGLESTEP  (MSR_DE)
-#else
-#define MSR_SINGLESTEP  (MSR_SE)
-#endif
-
 DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
 DEFINE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
 
@@ -104,19 +98,7 @@ void __kprobes arch_remove_kprobe(struct kprobe *p)
 
 static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
 {
-        /* We turn off async exceptions to ensure that the single step will
-         * be for the instruction we have the kprobe on, if we dont its
-         * possible we'd get the single step reported for an exception handler
-         * like Decrementer or External Interrupt */
-        regs->msr &= ~MSR_EE;
-        regs->msr |= MSR_SINGLESTEP;
-#ifdef CONFIG_PPC_ADV_DEBUG_REGS
-        regs->msr &= ~MSR_CE;
-        mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
-#ifdef CONFIG_PPC_47x
-        isync();
-#endif
-#endif
+        enable_single_step(regs);
 
         /*
          * On powerpc we should single step on the original
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 6782221d49bd..db28032e320e 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -750,13 +750,8 @@ EXPORT_SYMBOL_GPL(kvm_hypercall);
 
 static __init void kvm_free_tmp(void)
 {
-        unsigned long start, end;
-
-        start = (ulong)&kvm_tmp[kvm_tmp_index + (PAGE_SIZE - 1)] & PAGE_MASK;
-        end = (ulong)&kvm_tmp[ARRAY_SIZE(kvm_tmp)] & PAGE_MASK;
-
-        /* Free the tmp space we don't need */
-        free_reserved_area(start, end, 0, NULL);
+        free_reserved_area(&kvm_tmp[kvm_tmp_index],
+                           &kvm_tmp[ARRAY_SIZE(kvm_tmp)], -1, NULL);
 }
 
 static int __init kvm_guest_init(void)
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index 48fbc2b97e95..8213ee1eb05a 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -84,22 +84,30 @@ static ssize_t dev_nvram_read(struct file *file, char __user *buf,
         char *tmp = NULL;
         ssize_t size;
 
-        ret = -ENODEV;
-        if (!ppc_md.nvram_size)
+        if (!ppc_md.nvram_size) {
+                ret = -ENODEV;
                 goto out;
+        }
 
-        ret = 0;
         size = ppc_md.nvram_size();
-        if (*ppos >= size || size < 0)
+        if (size < 0) {
+                ret = size;
+                goto out;
+        }
+
+        if (*ppos >= size) {
+                ret = 0;
                 goto out;
+        }
 
         count = min_t(size_t, count, size - *ppos);
         count = min(count, PAGE_SIZE);
 
-        ret = -ENOMEM;
         tmp = kmalloc(count, GFP_KERNEL);
-        if (!tmp)
+        if (!tmp) {
+                ret = -ENOMEM;
                 goto out;
+        }
 
         ret = ppc_md.nvram_read(tmp, count, ppos);
         if (ret <= 0)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 7f2273cc3c7d..f46914a0f33e 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
         }
         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
                 struct resource *res = dev->resource + i;
+                struct pci_bus_region reg;
                 if (!res->flags)
                         continue;
 
@@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
                  * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
                  * since in that case, we don't want to re-assign anything
                  */
+                pcibios_resource_to_bus(dev, &reg, res);
                 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
-                    (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
+                    (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
                         /* Only print message if not re-assigning */
                         if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
                                 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
@@ -992,7 +994,7 @@ void pcibios_setup_bus_self(struct pci_bus *bus)
                 ppc_md.pci_dma_bus_setup(bus);
 }
 
-void pcibios_setup_device(struct pci_dev *dev)
+static void pcibios_setup_device(struct pci_dev *dev)
 {
         /* Fixup NUMA node as it may not be setup yet by the generic
          * code and is needed by the DMA init
@@ -1013,6 +1015,17 @@ void pcibios_setup_device(struct pci_dev *dev)
                 ppc_md.pci_irq_fixup(dev);
 }
 
+int pcibios_add_device(struct pci_dev *dev)
+{
+        /*
+         * We can only call pcibios_setup_device() after bus setup is complete,
+         * since some of the platform specific DMA setup code depends on it.
+         */
+        if (dev->bus->is_added)
+                pcibios_setup_device(dev);
+        return 0;
+}
+
 void pcibios_setup_bus_devices(struct pci_bus *bus)
 {
         struct pci_dev *dev;
@@ -1467,10 +1480,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
                 if (ppc_md.pcibios_enable_device_hook(dev))
                         return -EINVAL;
 
-        /* avoid pcie irq fix up impact on cardbus */
-        if (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS)
-                pcibios_setup_device(dev);
-
         return pci_enable_resources(dev, mask);
 }
 
diff --git a/arch/powerpc/kernel/pci-hotplug.c b/arch/powerpc/kernel/pci-hotplug.c
new file mode 100644
index 000000000000..3f608800c06b
--- /dev/null
+++ b/arch/powerpc/kernel/pci-hotplug.c
@@ -0,0 +1,111 @@
+/*
+ * Derived from "arch/powerpc/platforms/pseries/pci_dlpar.c"
+ *
+ * Copyright (C) 2003 Linda Xie <lxie@us.ibm.com>
+ * Copyright (C) 2005 International Business Machines
+ *
+ * Updates, 2005, John Rose <johnrose@austin.ibm.com>
+ * Updates, 2005, Linas Vepstas <linas@austin.ibm.com>
+ * Updates, 2013, Gavin Shan <shangw@linux.vnet.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/pci.h>
+#include <linux/export.h>
+#include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
+#include <asm/firmware.h>
+#include <asm/eeh.h>
+
+/**
+ * __pcibios_remove_pci_devices - remove all devices under this bus
+ * @bus: the indicated PCI bus
+ * @purge_pe: destroy the PE on removal of PCI devices
+ *
+ * Remove all of the PCI devices under this bus both from the
+ * linux pci device tree, and from the powerpc EEH address cache.
+ * By default, the corresponding PE will be destroied during the
+ * normal PCI hotplug path. For PCI hotplug during EEH recovery,
+ * the corresponding PE won't be destroied and deallocated.
+ */
+void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe)
+{
+        struct pci_dev *dev, *tmp;
+        struct pci_bus *child_bus;
+
+        /* First go down child busses */
+        list_for_each_entry(child_bus, &bus->children, node)
+                __pcibios_remove_pci_devices(child_bus, purge_pe);
+
+        pr_debug("PCI: Removing devices on bus %04x:%02x\n",
+                 pci_domain_nr(bus),  bus->number);
+        list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
+                pr_debug("     * Removing %s...\n", pci_name(dev));
+                eeh_remove_bus_device(dev, purge_pe);
+                pci_stop_and_remove_bus_device(dev);
+        }
+}
+
+/**
+ * pcibios_remove_pci_devices - remove all devices under this bus
+ * @bus: the indicated PCI bus
+ *
+ * Remove all of the PCI devices under this bus both from the
+ * linux pci device tree, and from the powerpc EEH address cache.
+ */
+void pcibios_remove_pci_devices(struct pci_bus *bus)
+{
+        __pcibios_remove_pci_devices(bus, 1);
+}
+EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
+
+/**
+ * pcibios_add_pci_devices - adds new pci devices to bus
+ * @bus: the indicated PCI bus
+ *
+ * This routine will find and fixup new pci devices under
+ * the indicated bus. This routine presumes that there
+ * might already be some devices under this bridge, so
+ * it carefully tries to add only new devices.  (And that
+ * is how this routine differs from other, similar pcibios
+ * routines.)
+ */
+void pcibios_add_pci_devices(struct pci_bus * bus)
+{
+        int slotno, num, mode, pass, max;
+        struct pci_dev *dev;
+        struct device_node *dn = pci_bus_to_OF_node(bus);
+
+        eeh_add_device_tree_early(dn);
+
+        mode = PCI_PROBE_NORMAL;
+        if (ppc_md.pci_probe_mode)
+                mode = ppc_md.pci_probe_mode(bus);
+
+        if (mode == PCI_PROBE_DEVTREE) {
+                /* use ofdt-based probe */
+                of_rescan_bus(dn, bus);
+        } else if (mode == PCI_PROBE_NORMAL) {
+                /* use legacy probe */
+                slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
+                num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
+                if (!num)
+                        return;
+                pcibios_setup_bus_devices(bus);
+                max = bus->busn_res.start;
+                for (pass = 0; pass < 2; pass++) {
+                        list_for_each_entry(dev, &bus->devices, bus_list) {
+                                if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
+                                    dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
+                                        max = pci_scan_bridge(bus, dev,
+                                                              max, pass);
+                        }
+                }
+        }
+        pcibios_finish_adding_to_bus(bus);
+}
+EXPORT_SYMBOL_GPL(pcibios_add_pci_devices);
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 2a67e9baa59f..6b0ba5854d99 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -128,7 +128,7 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
         const char *type;
         struct pci_slot *slot;
 
-        dev = alloc_pci_dev();
+        dev = pci_alloc_dev(bus);
         if (!dev)
                 return NULL;
         type = of_get_property(node, "device_type", NULL);
@@ -137,7 +137,6 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
 
         pr_debug("    create device, devfn: %x, type: %s\n", devfn, type);
 
-        dev->bus = bus;
         dev->dev.of_node = of_node_get(node);
         dev->dev.parent = bus->bridge;
         dev->dev.bus = &pci_bus_type;
@@ -165,7 +164,7 @@ struct pci_dev *of_create_pci_dev(struct device_node *node,
         pr_debug("    class: 0x%x\n", dev->class);
         pr_debug("    revision: 0x%x\n", dev->revision);
 
-        dev->current_state = 4;         /* unknown power state */
+        dev->current_state = PCI_UNKNOWN;       /* unknown power state */
         dev->error_state = pci_channel_io_normal;
         dev->dma_mask = 0xffffffff;
 
diff --git a/arch/powerpc/kernel/proc_powerpc.c b/arch/powerpc/kernel/proc_powerpc.c
index feb8580fdc84..c30612aad68e 100644
--- a/arch/powerpc/kernel/proc_powerpc.c
+++ b/arch/powerpc/kernel/proc_powerpc.c
@@ -29,25 +29,9 @@
 
 #ifdef CONFIG_PPC64
 
-static loff_t page_map_seek( struct file *file, loff_t off, int whence)
+static loff_t page_map_seek(struct file *file, loff_t off, int whence)
 {
-        loff_t new;
-        switch(whence) {
-        case 0:
-                new = off;
-                break;
-        case 1:
-                new = file->f_pos + off;
-                break;
-        case 2:
-                new = PAGE_SIZE + off;
-                break;
-        default:
-                return -EINVAL;
-        }
-        if ( new < 0 || new > PAGE_SIZE )
-                return -EINVAL;
-        return (file->f_pos = new);
+        return fixed_size_llseek(file, off, whence, PAGE_SIZE);
 }
 
 static ssize_t page_map_read( struct file *file, char __user *buf, size_t nbytes,
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a902723fdc69..c517dbe705fd 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 {
         mtspr(SPRN_DABR, dabr);
-        mtspr(SPRN_DABRX, dabrx);
+        if (cpu_has_feature(CPU_FTR_DABRX))
+                mtspr(SPRN_DABRX, dabrx);
         return 0;
 }
 #else
@@ -915,7 +916,11 @@ int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
         flush_altivec_to_thread(src);
         flush_vsx_to_thread(src);
         flush_spe_to_thread(src);
+
         *dst = *src;
+
+        clear_task_ebb(dst);
+
         return 0;
 }
 
@@ -1368,7 +1373,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
 
 #ifdef CONFIG_PPC64
 /* Called with hard IRQs off */
-void __ppc64_runlatch_on(void)
+void notrace __ppc64_runlatch_on(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
@@ -1381,7 +1386,7 @@ void __ppc64_runlatch_on(void)
 }
 
 /* Called with hard IRQs off */
-void __ppc64_runlatch_off(void)
+void notrace __ppc64_runlatch_off(void)
 {
         struct thread_info *ti = current_thread_info();
         unsigned long ctrl;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 8b6f7a99cce2..eb23ac92abb9 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -559,6 +559,35 @@ void __init early_init_dt_setup_initrd_arch(unsigned long start,
 }
 #endif
 
+static void __init early_reserve_mem_dt(void)
+{
+        unsigned long i, len, dt_root;
+        const __be32 *prop;
+
+        dt_root = of_get_flat_dt_root();
+
+        prop = of_get_flat_dt_prop(dt_root, "reserved-ranges", &len);
+
+        if (!prop)
+                return;
+
+        DBG("Found new-style reserved-ranges\n");
+
+        /* Each reserved range is an (address,size) pair, 2 cells each,
+         * totalling 4 cells per range. */
+        for (i = 0; i < len / (sizeof(*prop) * 4); i++) {
+                u64 base, size;
+
+                base = of_read_number(prop + (i * 4) + 0, 2);
+                size = of_read_number(prop + (i * 4) + 2, 2);
+
+                if (size) {
+                        DBG("reserving: %llx -> %llx\n", base, size);
+                        memblock_reserve(base, size);
+                }
+        }
+}
+
 static void __init early_reserve_mem(void)
 {
         u64 base, size;
@@ -574,12 +603,16 @@ static void __init early_reserve_mem(void)
         self_size = initial_boot_params->totalsize;
         memblock_reserve(self_base, self_size);
 
+        /* Look for the new "reserved-regions" property in the DT */
+        early_reserve_mem_dt();
+
 #ifdef CONFIG_BLK_DEV_INITRD
-        /* then reserve the initrd, if any */
-        if (initrd_start && (initrd_end > initrd_start))
+        /* Then reserve the initrd, if any */
+        if (initrd_start && (initrd_end > initrd_start)) {
                 memblock_reserve(_ALIGN_DOWN(__pa(initrd_start), PAGE_SIZE),
                         _ALIGN_UP(initrd_end, PAGE_SIZE) -
                         _ALIGN_DOWN(initrd_start, PAGE_SIZE));
+        }
 #endif /* CONFIG_BLK_DEV_INITRD */
 
 #ifdef CONFIG_PPC32
@@ -591,6 +624,8 @@ static void __init early_reserve_mem(void)
                 u32 base_32, size_32;
                 u32 *reserve_map_32 = (u32 *)reserve_map;
 
+                DBG("Found old 32-bit reserve map\n");
+
                 while (1) {
                         base_32 = *(reserve_map_32++);
                         size_32 = *(reserve_map_32++);
@@ -605,6 +640,9 @@ static void __init early_reserve_mem(void)
                 return;
         }
 #endif
+        DBG("Processing reserve map\n");
+
+        /* Handle the reserve map in the fdt blob if it exists */
         while (1) {
                 base = *(reserve_map++);
                 size = *(reserve_map++);
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 98c2fc198712..64f7bd5b1b0f 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1449,7 +1449,9 @@ static long ppc_set_hwdebug(struct task_struct *child,
          */
         if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) {
                 len = bp_info->addr2 - bp_info->addr;
-        } else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
+        } else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
+                len = 1;
+        else {
                 ptrace_put_breakpoints(child);
                 return -EINVAL;
         }
diff --git a/arch/powerpc/kernel/reloc_32.S b/arch/powerpc/kernel/reloc_32.S
index ef46ba6e094f..f366fedb0872 100644
--- a/arch/powerpc/kernel/reloc_32.S
+++ b/arch/powerpc/kernel/reloc_32.S
@@ -166,7 +166,7 @@ ha16:
         /* R_PPC_ADDR16_LO */
 lo16:
         cmpwi   r4, R_PPC_ADDR16_LO
-        bne     nxtrela
+        bne     unknown_type
         lwz     r4, 0(r9)       /* r_offset */
         lwz     r0, 8(r9)       /* r_addend */
         add     r0, r0, r3
@@ -191,6 +191,7 @@ nxtrela:
         dcbst   r4,r7
         sync                    /* Ensure the data is flushed before icbi */
         icbi    r4,r7
+unknown_type:
         cmpwi   r8, 0           /* relasz = 0 ? */
         ble     done
         add     r9, r9, r6      /* move to next entry in the .rela table */
diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c
index 52add6f3e201..80b5ef403f68 100644
--- a/arch/powerpc/kernel/rtas.c
+++ b/arch/powerpc/kernel/rtas.c
@@ -1172,7 +1172,7 @@ int __init early_init_dt_scan_rtas(unsigned long node,
 static arch_spinlock_t timebase_lock;
 static u64 timebase = 0;
 
-void __cpuinit rtas_give_timebase(void)
+void rtas_give_timebase(void)
 {
         unsigned long flags;
 
@@ -1189,7 +1189,7 @@ void __cpuinit rtas_give_timebase(void)
         local_irq_restore(flags);
 }
 
-void __cpuinit rtas_take_timebase(void)
+void rtas_take_timebase(void)
 {
         while (!timebase)
                 barrier();
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index e379d3fd1694..389fb8077cc9 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -76,7 +76,7 @@
 #endif
 
 int boot_cpuid = 0;
-int __initdata spinning_secondaries;
+int spinning_secondaries;
 u64 ppc64_pft_size;
 
 /* Pick defaults since we might want to patch instructions
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 201385c3a1ae..0f83122e6676 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -407,7 +407,8 @@ inline unsigned long copy_transact_fpr_from_user(struct task_struct *task,
  * altivec/spe instructions at some point.
  */
 static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
-                int sigret, int ctx_has_vsx_region)
+                          struct mcontext __user *tm_frame, int sigret,
+                          int ctx_has_vsx_region)
 {
         unsigned long msr = regs->msr;
 
@@ -475,6 +476,12 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
 
         if (__put_user(msr, &frame->mc_gregs[PT_MSR]))
                 return 1;
+        /* We need to write 0 the MSR top 32 bits in the tm frame so that we
+         * can check it on the restore to see if TM is active
+         */
+        if (tm_frame && __put_user(0, &tm_frame->mc_gregs[PT_MSR]))
+                return 1;
+
         if (sigret) {
                 /* Set up the sigreturn trampoline: li r0,sigret; sc */
                 if (__put_user(0x38000000UL + sigret, &frame->tramp[0])
@@ -747,7 +754,7 @@ static long restore_tm_user_regs(struct pt_regs *regs,
                                  struct mcontext __user *tm_sr)
 {
         long err;
-        unsigned long msr;
+        unsigned long msr, msr_hi;
 #ifdef CONFIG_VSX
         int i;
 #endif
@@ -852,8 +859,11 @@ static long restore_tm_user_regs(struct pt_regs *regs,
         tm_enable();
         /* This loads the checkpointed FP/VEC state, if used */
         tm_recheckpoint(&current->thread, msr);
-        /* The task has moved into TM state S, so ensure MSR reflects this */
-        regs->msr = (regs->msr & ~MSR_TS_MASK) | MSR_TS_S;
+        /* Get the top half of the MSR */
+        if (__get_user(msr_hi, &tm_sr->mc_gregs[PT_MSR]))
+                return 1;
+        /* Pull in MSR TM from user context */
+        regs->msr = (regs->msr & ~MSR_TS_MASK) | ((msr_hi<<32) & MSR_TS_MASK);
 
         /* This loads the speculative FP/VEC state, if used */
         if (msr & MSR_FP) {
@@ -952,6 +962,7 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
 {
         struct rt_sigframe __user *rt_sf;
         struct mcontext __user *frame;
+        struct mcontext __user *tm_frame = NULL;
         void __user *addr;
         unsigned long newsp = 0;
         int sigret;
@@ -985,23 +996,24 @@ int handle_rt_signal32(unsigned long sig, struct k_sigaction *ka,
         }
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        tm_frame = &rt_sf->uc_transact.uc_mcontext;
         if (MSR_TM_ACTIVE(regs->msr)) {
-                if (save_tm_user_regs(regs, &rt_sf->uc.uc_mcontext,
-                                      &rt_sf->uc_transact.uc_mcontext, sigret))
+                if (save_tm_user_regs(regs, frame, tm_frame, sigret))
                         goto badframe;
         }
         else
 #endif
-                if (save_user_regs(regs, frame, sigret, 1))
+        {
+                if (save_user_regs(regs, frame, tm_frame, sigret, 1))
                         goto badframe;
+        }
         regs->link = tramp;
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         if (MSR_TM_ACTIVE(regs->msr)) {
                 if (__put_user((unsigned long)&rt_sf->uc_transact,
                                &rt_sf->uc.uc_link)
-                    || __put_user(to_user_ptr(&rt_sf->uc_transact.uc_mcontext),
-                                  &rt_sf->uc_transact.uc_regs))
+                    || __put_user((unsigned long)tm_frame, &rt_sf->uc_transact.uc_regs))
                         goto badframe;
         }
         else
@@ -1170,7 +1182,7 @@ long sys_swapcontext(struct ucontext __user *old_ctx,
                 mctx = (struct mcontext __user *)
                         ((unsigned long) &old_ctx->uc_mcontext & ~0xfUL);
                 if (!access_ok(VERIFY_WRITE, old_ctx, ctx_size)
-                    || save_user_regs(regs, mctx, 0, ctx_has_vsx_region)
+                    || save_user_regs(regs, mctx, NULL, 0, ctx_has_vsx_region)
                     || put_sigset_t(&old_ctx->uc_sigmask, &current->blocked)
                     || __put_user(to_user_ptr(mctx), &old_ctx->uc_regs))
                         return -EFAULT;
@@ -1233,7 +1245,7 @@ long sys_rt_sigreturn(int r3, int r4, int r5, int r6, int r7, int r8,
                 if (__get_user(msr_hi, &mcp->mc_gregs[PT_MSR]))
                         goto bad;
 
-                if (MSR_TM_SUSPENDED(msr_hi<<32)) {
+                if (MSR_TM_ACTIVE(msr_hi<<32)) {
                         /* We only recheckpoint on return if we're
                          * transaction.
                          */
@@ -1392,6 +1404,7 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
 {
         struct sigcontext __user *sc;
         struct sigframe __user *frame;
+        struct mcontext __user *tm_mctx = NULL;
         unsigned long newsp = 0;
         int sigret;
         unsigned long tramp;
@@ -1425,6 +1438,7 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         }
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        tm_mctx = &frame->mctx_transact;
         if (MSR_TM_ACTIVE(regs->msr)) {
                 if (save_tm_user_regs(regs, &frame->mctx, &frame->mctx_transact,
                                       sigret))
@@ -1432,8 +1446,10 @@ int handle_signal32(unsigned long sig, struct k_sigaction *ka,
         }
         else
 #endif
-                if (save_user_regs(regs, &frame->mctx, sigret, 1))
+        {
+                if (save_user_regs(regs, &frame->mctx, tm_mctx, sigret, 1))
                         goto badframe;
+        }
 
         regs->link = tramp;
 
@@ -1481,16 +1497,22 @@ badframe:
 long sys_sigreturn(int r3, int r4, int r5, int r6, int r7, int r8,
                        struct pt_regs *regs)
 {
+        struct sigframe __user *sf;
         struct sigcontext __user *sc;
         struct sigcontext sigctx;
         struct mcontext __user *sr;
         void __user *addr;
         sigset_t set;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        struct mcontext __user *mcp, *tm_mcp;
+        unsigned long msr_hi;
+#endif
 
         /* Always make any pending restarted system calls return -EINTR */
         current_thread_info()->restart_block.fn = do_no_restart_syscall;
 
-        sc = (struct sigcontext __user *)(regs->gpr[1] + __SIGNAL_FRAMESIZE);
+        sf = (struct sigframe __user *)(regs->gpr[1] + __SIGNAL_FRAMESIZE);
+        sc = &sf->sctx;
         addr = sc;
         if (copy_from_user(&sigctx, sc, sizeof(sigctx)))
                 goto badframe;
@@ -1507,11 +1529,25 @@ long sys_sigreturn(int r3, int r4, int r5, int r6, int r7, int r8,
 #endif
         set_current_blocked(&set);
 
-        sr = (struct mcontext __user *)from_user_ptr(sigctx.regs);
-        addr = sr;
-        if (!access_ok(VERIFY_READ, sr, sizeof(*sr))
-            || restore_user_regs(regs, sr, 1))
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+        mcp = (struct mcontext __user *)&sf->mctx;
+        tm_mcp = (struct mcontext __user *)&sf->mctx_transact;
+        if (__get_user(msr_hi, &tm_mcp->mc_gregs[PT_MSR]))
                 goto badframe;
+        if (MSR_TM_ACTIVE(msr_hi<<32)) {
+                if (!cpu_has_feature(CPU_FTR_TM))
+                        goto badframe;
+                if (restore_tm_user_regs(regs, mcp, tm_mcp))
+                        goto badframe;
+        } else
+#endif
+        {
+                sr = (struct mcontext __user *)from_user_ptr(sigctx.regs);
+                addr = sr;
+                if (!access_ok(VERIFY_READ, sr, sizeof(*sr))
+                    || restore_user_regs(regs, sr, 1))
+                        goto badframe;
+        }
 
         set_thread_flag(TIF_RESTOREALL);
         return 0;
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c
index 345947367ec0..887e99d85bc2 100644
--- a/arch/powerpc/kernel/signal_64.c
+++ b/arch/powerpc/kernel/signal_64.c
@@ -410,6 +410,10 @@ static long restore_tm_sigcontexts(struct pt_regs *regs,
 
         /* get MSR separately, transfer the LE bit if doing signal return */
         err |= __get_user(msr, &sc->gp_regs[PT_MSR]);
+        /* pull in MSR TM from user context */
+        regs->msr = (regs->msr & ~MSR_TS_MASK) | (msr & MSR_TS_MASK);
+
+        /* pull in MSR LE from user context */
         regs->msr = (regs->msr & ~MSR_LE) | (msr & MSR_LE);
 
         /* The following non-GPR non-FPR non-VR state is also checkpointed: */
@@ -505,8 +509,6 @@ static long restore_tm_sigcontexts(struct pt_regs *regs,
         tm_enable();
         /* This loads the checkpointed FP/VEC state, if used */
         tm_recheckpoint(&current->thread, msr);
-        /* The task has moved into TM state S, so ensure MSR reflects this: */
-        regs->msr = (regs->msr & ~MSR_TS_MASK) | __MASK(33);
 
         /* This loads the speculative FP/VEC state, if used */
         if (msr & MSR_FP) {
@@ -654,7 +656,7 @@ int sys_rt_sigreturn(unsigned long r3, unsigned long r4, unsigned long r5,
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
         if (__get_user(msr, &uc->uc_mcontext.gp_regs[PT_MSR]))
                 goto badframe;
-        if (MSR_TM_SUSPENDED(msr)) {
+        if (MSR_TM_ACTIVE(msr)) {
                 /* We recheckpoint on return. */
                 struct ucontext __user *uc_transact;
                 if (__get_user(uc_transact, &uc->uc_link))
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ee7ac5e6e28a..38b0ba65a735 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -480,7 +480,7 @@ static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
         secondary_ti = current_set[cpu] = ti;
 }
 
-int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
+int __cpu_up(unsigned int cpu, struct task_struct *tidle)
 {
         int rc, c;
 
@@ -610,7 +610,7 @@ static struct device_node *cpu_to_l2cache(int cpu)
 }
 
 /* Activate a secondary processor. */
-__cpuinit void start_secondary(void *unused)
+void start_secondary(void *unused)
 {
         unsigned int cpu = smp_processor_id();
         struct device_node *l2_cache;
@@ -637,12 +637,10 @@ __cpuinit void start_secondary(void *unused)
 
         vdso_getcpu_init();
 #endif
-        notify_cpu_starting(cpu);
-        set_cpu_online(cpu, true);
         /* Update sibling maps */
         base = cpu_first_thread_sibling(cpu);
         for (i = 0; i < threads_per_core; i++) {
-                if (cpu_is_offline(base + i))
+                if (cpu_is_offline(base + i) && (cpu != base + i))
                         continue;
                 cpumask_set_cpu(cpu, cpu_sibling_mask(base + i));
                 cpumask_set_cpu(base + i, cpu_sibling_mask(cpu));
@@ -667,6 +665,10 @@ __cpuinit void start_secondary(void *unused)
         }
         of_node_put(l2_cache);
 
+        smp_wmb();
+        notify_cpu_starting(cpu);
+        set_cpu_online(cpu, true);
+
         local_irq_enable();
 
         cpu_startup_entry(CPUHP_ONLINE);
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index e68a84568b8b..27a90b99ef67 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -341,7 +341,7 @@ static struct device_attribute pa6t_attrs[] = {
 #endif /* HAS_PPC_PMC_PA6T */
 #endif /* HAS_PPC_PMC_CLASSIC */
 
-static void __cpuinit register_cpu_online(unsigned int cpu)
+static void register_cpu_online(unsigned int cpu)
 {
         struct cpu *c = &per_cpu(cpu_devices, cpu);
         struct device *s = &c->dev;
@@ -502,7 +502,7 @@ ssize_t arch_cpu_release(const char *buf, size_t count)
 
 #endif /* CONFIG_HOTPLUG_CPU */
 
-static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
+static int sysfs_cpu_notify(struct notifier_block *self,
                                       unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned int)(long)hcpu;
@@ -522,7 +522,7 @@ static int __cpuinit sysfs_cpu_notify(struct notifier_block *self,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata sysfs_cpu_nb = {
+static struct notifier_block sysfs_cpu_nb = {
         .notifier_call  = sysfs_cpu_notify,
 };
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 5fc29ad7e26f..65ab9e909377 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -631,7 +631,6 @@ static int __init get_freq(char *name, int cells, unsigned long *val)
         return found;
 }
 
-/* should become __cpuinit when secondary_cpu_time_init also is */
 void start_cpu_decrementer(void)
 {
 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
diff --git a/arch/powerpc/kernel/tm.S b/arch/powerpc/kernel/tm.S
index 2da67e7a16d5..51be8fb24803 100644
--- a/arch/powerpc/kernel/tm.S
+++ b/arch/powerpc/kernel/tm.S
@@ -112,9 +112,18 @@ _GLOBAL(tm_reclaim)
         std     r3, STACK_PARAM(0)(r1)
         SAVE_NVGPRS(r1)
 
+        /* We need to setup MSR for VSX register save instructions.  Here we
+         * also clear the MSR RI since when we do the treclaim, we won't have a
+         * valid kernel pointer for a while.  We clear RI here as it avoids
+         * adding another mtmsr closer to the treclaim.  This makes the region
+         * maked as non-recoverable wider than it needs to be but it saves on
+         * inserting another mtmsrd later.
+         */
         mfmsr   r14
         mr      r15, r14
         ori     r15, r15, MSR_FP
+        li      r16, MSR_RI
+        andc    r15, r15, r16
         oris    r15, r15, MSR_VEC@h
 #ifdef CONFIG_VSX
         BEGIN_FTR_SECTION
@@ -349,9 +358,10 @@ restore_gprs:
         mtcr    r5
         mtxer   r6
 
-        /* MSR and flags:  We don't change CRs, and we don't need to alter
-         * MSR.
+        /* Clear the MSR RI since we are about to change R1.  EE is already off
          */
+        li      r4, 0
+        mtmsrd  r4, 1
 
         REST_4GPRS(0, r7)                       /* GPR0-3 */
         REST_GPR(4, r7)                         /* GPR4-6 */
@@ -377,6 +387,10 @@ restore_gprs:
         GET_PACA(r13)
         GET_SCRATCH0(r1)
 
+        /* R1 is restored, so we are recoverable again.  EE is still off */
+        li      r4, MSR_RI
+        mtmsrd  r4, 1
+
         REST_NVGPRS(r1)
 
         addi    r1, r1, TM_FRAME_SIZE
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f18c79c324ef..bf33c22e38a4 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -866,6 +866,10 @@ static int emulate_string_inst(struct pt_regs *regs, u32 instword)
                 u8 val;
                 u32 shift = 8 * (3 - (pos & 0x3));
 
+                /* if process is 32-bit, clear upper 32 bits of EA */
+                if ((regs->msr & MSR_64BIT) == 0)
+                        EA &= 0xFFFFFFFF;
+
                 switch ((instword & PPC_INST_STRING_MASK)) {
                         case PPC_INST_LSWX:
                         case PPC_INST_LSWI:
@@ -1125,7 +1129,17 @@ void __kprobes program_check_exception(struct pt_regs *regs)
          * ESR_DST (!?) or 0.  In the process of chasing this with the
          * hardware people - not sure if it can happen on any illegal
          * instruction or only on FP instructions, whether there is a
-         * pattern to occurrences etc. -dgibson 31/Mar/2003 */
+         * pattern to occurrences etc. -dgibson 31/Mar/2003
+         */
+
+        /*
+         * If we support a HW FPU, we need to ensure the FP state
+         * if flushed into the thread_struct before attempting
+         * emulation
+         */
+#ifdef CONFIG_PPC_FPU
+        flush_fp_to_thread(current);
+#endif
         switch (do_mathemu(regs)) {
         case 0:
                 emulate_single_step(regs);
@@ -1165,6 +1179,16 @@ bail:
         exception_exit(prev_state);
 }
 
+/*
+ * This occurs when running in hypervisor mode on POWER6 or later
+ * and an illegal instruction is encountered.
+ */
+void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
+{
+        regs->msr |= REASON_ILLEGAL;
+        program_check_exception(regs);
+}
+
 void alignment_exception(struct pt_regs *regs)
 {
         enum ctx_state prev_state = exception_enter();
@@ -1272,25 +1296,50 @@ void vsx_unavailable_exception(struct pt_regs *regs)
         die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
 }
 
-void tm_unavailable_exception(struct pt_regs *regs)
+void facility_unavailable_exception(struct pt_regs *regs)
 {
+        static char *facility_strings[] = {
+                "FPU",
+                "VMX/VSX",
+                "DSCR",
+                "PMU SPRs",
+                "BHRB",
+                "TM",
+                "AT",
+                "EBB",
+                "TAR",
+        };
+        char *facility, *prefix;
+        u64 value;
+
+        if (regs->trap == 0xf60) {
+                value = mfspr(SPRN_FSCR);
+                prefix = "";
+        } else {
+                value = mfspr(SPRN_HFSCR);
+                prefix = "Hypervisor ";
+        }
+
+        value = value >> 56;
+
         /* We restore the interrupt state now */
         if (!arch_irq_disabled_regs(regs))
                 local_irq_enable();
 
-        /* Currently we never expect a TMU exception.  Catch
-         * this and kill the process!
-         */
-        printk(KERN_EMERG "Unexpected TM unavailable exception at %lx "
-               "(msr %lx)\n",
-               regs->nip, regs->msr);
+        if (value < ARRAY_SIZE(facility_strings))
+                facility = facility_strings[value];
+        else
+                facility = "unknown";
+
+        pr_err("%sFacility '%s' unavailable, exception at 0x%lx, MSR=%lx\n",
+                prefix, facility, regs->nip, regs->msr);
 
         if (user_mode(regs)) {
                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
                 return;
         }
 
-        die("Unexpected TM unavailable exception", regs, SIGABRT);
+        die("Unexpected facility unavailable exception", regs, SIGABRT);
 }
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -1386,8 +1435,7 @@ void performance_monitor_exception(struct pt_regs *regs)
 void SoftwareEmulation(struct pt_regs *regs)
 {
         extern int do_mathemu(struct pt_regs *);
-        extern int Soft_emulate_8xx(struct pt_regs *);
-#if defined(CONFIG_MATH_EMULATION) || defined(CONFIG_8XX_MINIMAL_FPEMU)
+#if defined(CONFIG_MATH_EMULATION)
         int errcode;
 #endif
 
@@ -1420,23 +1468,6 @@ void SoftwareEmulation(struct pt_regs *regs)
                 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
                 return;
         }
-
-#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
-        errcode = Soft_emulate_8xx(regs);
-        if (errcode >= 0)
-                PPC_WARN_EMULATED(8xx, regs);
-
-        switch (errcode) {
-        case 0:
-                emulate_single_step(regs);
-                return;
-        case 1:
-                _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
-                return;
-        case -EFAULT:
-                _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
-                return;
-        }
 #else
         _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
 #endif
@@ -1786,8 +1817,6 @@ struct ppc_emulated ppc_emulated = {
         WARN_EMULATED_SETUP(unaligned),
 #ifdef CONFIG_MATH_EMULATION
         WARN_EMULATED_SETUP(math),
-#elif defined(CONFIG_8XX_MINIMAL_FPEMU)
-        WARN_EMULATED_SETUP(8xx),
 #endif
 #ifdef CONFIG_VSX
         WARN_EMULATED_SETUP(vsx),
diff --git a/arch/powerpc/kernel/udbg.c b/arch/powerpc/kernel/udbg.c
index 9d3fdcd66290..a15837519dca 100644
--- a/arch/powerpc/kernel/udbg.c
+++ b/arch/powerpc/kernel/udbg.c
@@ -50,7 +50,7 @@ void __init udbg_early_init(void)
         udbg_init_debug_beat();
 #elif defined(CONFIG_PPC_EARLY_DEBUG_PAS_REALMODE)
         udbg_init_pas_realmode();
-#elif defined(CONFIG_BOOTX_TEXT)
+#elif defined(CONFIG_PPC_EARLY_DEBUG_BOOTX)
         udbg_init_btext();
 #elif defined(CONFIG_PPC_EARLY_DEBUG_44x)
         /* PPC44x debug */
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index d4f463ac65b1..1d9c92621b36 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -711,7 +711,7 @@ static void __init vdso_setup_syscall_map(void)
 }
 
 #ifdef CONFIG_PPC64
-int __cpuinit vdso_getcpu_init(void)
+int vdso_getcpu_init(void)
 {
         unsigned long cpu, node, val;
 
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 5dd3ab469976..ed0385448148 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
         struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
         struct kvmppc_44x_tlbe *tlbe;
         unsigned int gtlb_index;
+        int idx;
 
         gtlb_index = kvmppc_get_gpr(vcpu, ra);
         if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 return EMULATE_FAIL;
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         if (tlbe_is_host_safe(vcpu, tlbe)) {
                 gva_t eaddr;
                 gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
                              tlbe->word2);
 
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 422de3f4d46c..008cd856c5b5 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -5,9 +5,10 @@
 subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 ccflags-y := -Ivirt/kvm -Iarch/powerpc/kvm
+KVM := ../../../virt/kvm
 
-common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o \
-                                                eventfd.o)
+common-objs-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o \
+                $(KVM)/eventfd.o
 
 CFLAGS_44x_tlb.o  := -I.
 CFLAGS_e500_mmu.o := -I.
@@ -53,7 +54,7 @@ kvm-e500mc-objs := \
 kvm-objs-$(CONFIG_KVM_E500MC) := $(kvm-e500mc-objs)
 
 kvm-book3s_64-objs-$(CONFIG_KVM_BOOK3S_64_PR) := \
-        ../../../virt/kvm/coalesced_mmio.o \
+        $(KVM)/coalesced_mmio.o \
         fpu.o \
         book3s_paired_singles.o \
         book3s_pr.o \
@@ -86,8 +87,8 @@ kvm-book3s_64-objs-$(CONFIG_KVM_XICS) += \
         book3s_xics.o
 
 kvm-book3s_64-module-objs := \
-        ../../../virt/kvm/kvm_main.o \
-        ../../../virt/kvm/eventfd.o \
+        $(KVM)/kvm_main.o \
+        $(KVM)/eventfd.o \
         powerpc.o \
         emulate.o \
         book3s.o \
@@ -111,7 +112,7 @@ kvm-book3s_32-objs := \
 kvm-objs-$(CONFIG_KVM_BOOK3S_32) := $(kvm-book3s_32-objs)
 
 kvm-objs-$(CONFIG_KVM_MPIC) += mpic.o
-kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(addprefix ../../../virt/kvm/, irqchip.o)
+kvm-objs-$(CONFIG_HAVE_KVM_IRQ_ROUTING) += $(KVM)/irqchip.o
 
 kvm-objs := $(kvm-objs-m) $(kvm-objs-y)
 
diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c
index b871721c0050..739bfbadb85e 100644
--- a/arch/powerpc/kvm/book3s_64_mmu.c
+++ b/arch/powerpc/kvm/book3s_64_mmu.c
@@ -26,6 +26,7 @@
 #include <asm/tlbflush.h>
 #include <asm/kvm_ppc.h>
 #include <asm/kvm_book3s.h>
+#include <asm/mmu-hash64.h>
 
 /* #define DEBUG_MMU */
 
@@ -76,6 +77,24 @@ static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe(
         return NULL;
 }
 
+static int kvmppc_slb_sid_shift(struct kvmppc_slb *slbe)
+{
+        return slbe->tb ? SID_SHIFT_1T : SID_SHIFT;
+}
+
+static u64 kvmppc_slb_offset_mask(struct kvmppc_slb *slbe)
+{
+        return (1ul << kvmppc_slb_sid_shift(slbe)) - 1;
+}
+
+static u64 kvmppc_slb_calc_vpn(struct kvmppc_slb *slb, gva_t eaddr)
+{
+        eaddr &= kvmppc_slb_offset_mask(slb);
+
+        return (eaddr >> VPN_SHIFT) |
+                ((slb->vsid) << (kvmppc_slb_sid_shift(slb) - VPN_SHIFT));
+}
+
 static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
                                          bool data)
 {
@@ -85,11 +104,7 @@ static u64 kvmppc_mmu_book3s_64_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr,
         if (!slb)
                 return 0;
 
-        if (slb->tb)
-                return (((u64)eaddr >> 12) & 0xfffffff) |
-                       (((u64)slb->vsid) << 28);
-
-        return (((u64)eaddr >> 12) & 0xffff) | (((u64)slb->vsid) << 16);
+        return kvmppc_slb_calc_vpn(slb, eaddr);
 }
 
 static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe)
@@ -100,7 +115,8 @@ static int kvmppc_mmu_book3s_64_get_pagesize(struct kvmppc_slb *slbe)
 static u32 kvmppc_mmu_book3s_64_get_page(struct kvmppc_slb *slbe, gva_t eaddr)
 {
         int p = kvmppc_mmu_book3s_64_get_pagesize(slbe);
-        return ((eaddr & 0xfffffff) >> p);
+
+        return ((eaddr & kvmppc_slb_offset_mask(slbe)) >> p);
 }
 
 static hva_t kvmppc_mmu_book3s_64_get_pteg(
@@ -109,13 +125,15 @@ static hva_t kvmppc_mmu_book3s_64_get_pteg(
                                 bool second)
 {
         u64 hash, pteg, htabsize;
-        u32 page;
+        u32 ssize;
         hva_t r;
+        u64 vpn;
 
-        page = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
         htabsize = ((1 << ((vcpu_book3s->sdr1 & 0x1f) + 11)) - 1);
 
-        hash = slbe->vsid ^ page;
+        vpn = kvmppc_slb_calc_vpn(slbe, eaddr);
+        ssize = slbe->tb ? MMU_SEGSIZE_1T : MMU_SEGSIZE_256M;
+        hash = hpt_hash(vpn, kvmppc_mmu_book3s_64_get_pagesize(slbe), ssize);
         if (second)
                 hash = ~hash;
         hash &= ((1ULL << 39ULL) - 1ULL);
@@ -146,7 +164,7 @@ static u64 kvmppc_mmu_book3s_64_get_avpn(struct kvmppc_slb *slbe, gva_t eaddr)
         u64 avpn;
 
         avpn = kvmppc_mmu_book3s_64_get_page(slbe, eaddr);
-        avpn |= slbe->vsid << (28 - p);
+        avpn |= slbe->vsid << (kvmppc_slb_sid_shift(slbe) - p);
 
         if (p < 24)
                 avpn >>= ((80 - p) - 56) - 8;
@@ -167,7 +185,6 @@ static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
         int i;
         u8 key = 0;
         bool found = false;
-        bool perm_err = false;
         int second = 0;
         ulong mp_ea = vcpu->arch.magic_page_ea;
 
@@ -190,13 +207,15 @@ static int kvmppc_mmu_book3s_64_xlate(struct kvm_vcpu *vcpu, gva_t eaddr,
         if (!slbe)
                 goto no_seg_found;
 
+        avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr);
+        if (slbe->tb)
+                avpn |= SLB_VSID_B_1T;
+
 do_second:
         ptegp = kvmppc_mmu_book3s_64_get_pteg(vcpu_book3s, slbe, eaddr, second);
         if (kvm_is_error_hva(ptegp))
                 goto no_page_found;
 
-        avpn = kvmppc_mmu_book3s_64_get_avpn(slbe, eaddr);
-
         if(copy_from_user(pteg, (void __user *)ptegp, sizeof(pteg))) {
                 printk(KERN_ERR "KVM can't copy data from 0x%lx!\n", ptegp);
                 goto no_page_found;
@@ -219,7 +238,7 @@ do_second:
                         continue;
 
                 /* AVPN compare */
-                if (HPTE_V_AVPN_VAL(avpn) == HPTE_V_AVPN_VAL(v)) {
+                if (HPTE_V_COMPARE(avpn, v)) {
                         u8 pp = (r & HPTE_R_PP) | key;
                         int eaddr_mask = 0xFFF;
 
@@ -248,11 +267,6 @@ do_second:
                                 break;
                         }
 
-                        if (!gpte->may_read) {
-                                perm_err = true;
-                                continue;
-                        }
-
                         dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx "
                                 "-> 0x%lx\n",
                                 eaddr, avpn, gpte->vpage, gpte->raddr);
@@ -281,6 +295,8 @@ do_second:
                 if (pteg[i+1] != oldr)
                         copy_to_user((void __user *)ptegp, pteg, sizeof(pteg));
 
+                if (!gpte->may_read)
+                        return -EPERM;
                 return 0;
         } else {
                 dprintk("KVM MMU: No PTE found (ea=0x%lx sdr1=0x%llx "
@@ -296,13 +312,7 @@ do_second:
                 }
         }
 
-
 no_page_found:
-
-
-        if (perm_err)
-                return -EPERM;
-
         return -ENOENT;
 
 no_seg_found:
@@ -334,7 +344,7 @@ static void kvmppc_mmu_book3s_64_slbmte(struct kvm_vcpu *vcpu, u64 rs, u64 rb)
         slbe->large = (rs & SLB_VSID_L) ? 1 : 0;
         slbe->tb    = (rs & SLB_VSID_B_1T) ? 1 : 0;
         slbe->esid  = slbe->tb ? esid_1t : esid;
-        slbe->vsid  = rs >> 12;
+        slbe->vsid  = (rs & ~SLB_VSID_B) >> (kvmppc_slb_sid_shift(slbe) - 16);
         slbe->valid = (rb & SLB_ESID_V) ? 1 : 0;
         slbe->Ks    = (rs & SLB_VSID_KS) ? 1 : 0;
         slbe->Kp    = (rs & SLB_VSID_KP) ? 1 : 0;
@@ -375,6 +385,7 @@ static u64 kvmppc_mmu_book3s_64_slbmfev(struct kvm_vcpu *vcpu, u64 slb_nr)
 static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea)
 {
         struct kvmppc_slb *slbe;
+        u64 seg_size;
 
         dprintk("KVM MMU: slbie(0x%llx)\n", ea);
 
@@ -386,8 +397,11 @@ static void kvmppc_mmu_book3s_64_slbie(struct kvm_vcpu *vcpu, u64 ea)
         dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid);
 
         slbe->valid = false;
+        slbe->orige = 0;
+        slbe->origv = 0;
 
-        kvmppc_mmu_map_segment(vcpu, ea);
+        seg_size = 1ull << kvmppc_slb_sid_shift(slbe);
+        kvmppc_mmu_flush_segment(vcpu, ea & ~(seg_size - 1), seg_size);
 }
 
 static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu)
@@ -396,8 +410,11 @@ static void kvmppc_mmu_book3s_64_slbia(struct kvm_vcpu *vcpu)
 
         dprintk("KVM MMU: slbia()\n");
 
-        for (i = 1; i < vcpu->arch.slb_nr; i++)
+        for (i = 1; i < vcpu->arch.slb_nr; i++) {
                 vcpu->arch.slb[i].valid = false;
+                vcpu->arch.slb[i].orige = 0;
+                vcpu->arch.slb[i].origv = 0;
+        }
 
         if (vcpu->arch.shared->msr & MSR_IR) {
                 kvmppc_mmu_flush_segments(vcpu);
@@ -467,8 +484,14 @@ static int kvmppc_mmu_book3s_64_esid_to_vsid(struct kvm_vcpu *vcpu, ulong esid,
 
         if (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) {
                 slb = kvmppc_mmu_book3s_64_find_slbe(vcpu, ea);
-                if (slb)
+                if (slb) {
                         gvsid = slb->vsid;
+                        if (slb->tb) {
+                                gvsid <<= SID_SHIFT_1T - SID_SHIFT;
+                                gvsid |= esid & ((1ul << (SID_SHIFT_1T - SID_SHIFT)) - 1);
+                                gvsid |= VSID_1T;
+                        }
+                }
         }
 
         switch (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) {
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 3a9a1aceb14f..e5240524bf6c 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -34,7 +34,7 @@
 void kvmppc_mmu_invalidate_pte(struct kvm_vcpu *vcpu, struct hpte_cache *pte)
 {
         ppc_md.hpte_invalidate(pte->slot, pte->host_vpn,
-                               MMU_PAGE_4K, MMU_SEGSIZE_256M,
+                               MMU_PAGE_4K, MMU_PAGE_4K, MMU_SEGSIZE_256M,
                                false);
 }
 
@@ -301,6 +301,23 @@ out:
         return r;
 }
 
+void kvmppc_mmu_flush_segment(struct kvm_vcpu *vcpu, ulong ea, ulong seg_size)
+{
+        struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
+        ulong seg_mask = -seg_size;
+        int i;
+
+        for (i = 1; i < svcpu->slb_max; i++) {
+                if ((svcpu->slb[i].esid & SLB_ESID_V) &&
+                    (svcpu->slb[i].esid & seg_mask) == ea) {
+                        /* Invalidate this entry */
+                        svcpu->slb[i].esid = 0;
+                }
+        }
+
+        svcpu_put(svcpu);
+}
+
 void kvmppc_mmu_flush_segments(struct kvm_vcpu *vcpu)
 {
         struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
@@ -325,9 +342,9 @@ int kvmppc_mmu_init(struct kvm_vcpu *vcpu)
                 return -1;
         vcpu3s->context_id[0] = err;
 
-        vcpu3s->proto_vsid_max = ((vcpu3s->context_id[0] + 1)
+        vcpu3s->proto_vsid_max = ((u64)(vcpu3s->context_id[0] + 1)
                                   << ESID_BITS) - 1;
-        vcpu3s->proto_vsid_first = vcpu3s->context_id[0] << ESID_BITS;
+        vcpu3s->proto_vsid_first = (u64)vcpu3s->context_id[0] << ESID_BITS;
         vcpu3s->proto_vsid_next = vcpu3s->proto_vsid_first;
 
         kvmppc_mmu_hpte_init(vcpu);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 5880dfb31074..710d31317d81 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -675,6 +675,7 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 }
                 /* if the guest wants write access, see if that is OK */
                 if (!writing && hpte_is_writable(r)) {
+                        unsigned int hugepage_shift;
                         pte_t *ptep, pte;
 
                         /*
@@ -683,9 +684,10 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
                          */
                         rcu_read_lock_sched();
                         ptep = find_linux_pte_or_hugepte(current->mm->pgd,
-                                                         hva, NULL);
-                        if (ptep && pte_present(*ptep)) {
-                                pte = kvmppc_read_update_linux_pte(ptep, 1);
+                                                         hva, &hugepage_shift);
+                        if (ptep) {
+                                pte = kvmppc_read_update_linux_pte(ptep, 1,
+                                                           hugepage_shift);
                                 if (pte_write(pte))
                                         write_ok = 1;
                         }
diff --git a/arch/powerpc/kvm/book3s_64_slb.S b/arch/powerpc/kvm/book3s_64_slb.S
index 56b983e7b738..4f0caecc0f9d 100644
--- a/arch/powerpc/kvm/book3s_64_slb.S
+++ b/arch/powerpc/kvm/book3s_64_slb.S
@@ -66,10 +66,6 @@ slb_exit_skip_ ## num:
 
         ld      r12, PACA_SLBSHADOWPTR(r13)
 
-        /* Save off the first entry so we can slbie it later */
-        ld      r10, SHADOW_SLB_ESID(0)(r12)
-        ld      r11, SHADOW_SLB_VSID(0)(r12)
-
         /* Remove bolted entries */
         UNBOLT_SLB_ENTRY(0)
         UNBOLT_SLB_ENTRY(1)
@@ -81,15 +77,10 @@ slb_exit_skip_ ## num:
 
         /* Flush SLB */
 
+        li      r10, 0
+        slbmte  r10, r10
         slbia
 
-        /* r0 = esid & ESID_MASK */
-        rldicr  r10, r10, 0, 35
-        /* r0 |= CLASS_BIT(VSID) */
-        rldic   r12, r11, 56 - 36, 36
-        or      r10, r10, r12
-        slbie   r10
-
         /* Fill SLB with our shadow */
 
         lbz     r12, SVCPU_SLB_MAX(r3)
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 550f5928b394..2efa9dde741a 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1864,7 +1864,7 @@ static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
 
  up_out:
         up_read(&current->mm->mmap_sem);
-        goto out;
+        goto out_srcu;
 }
 
 int kvmppc_core_init_vm(struct kvm *kvm)
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index 6dcbb49105a4..fc25689a9f35 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -27,7 +27,7 @@ static void *real_vmalloc_addr(void *x)
         unsigned long addr = (unsigned long) x;
         pte_t *p;
 
-        p = find_linux_pte(swapper_pg_dir, addr);
+        p = find_linux_pte_or_hugepte(swapper_pg_dir, addr, NULL);
         if (!p || !pte_present(*p))
                 return NULL;
         /* assume we don't have huge pages in vmalloc space... */
@@ -139,20 +139,18 @@ static pte_t lookup_linux_pte(pgd_t *pgdir, unsigned long hva,
 {
         pte_t *ptep;
         unsigned long ps = *pte_sizep;
-        unsigned int shift;
+        unsigned int hugepage_shift;
 
-        ptep = find_linux_pte_or_hugepte(pgdir, hva, &shift);
+        ptep = find_linux_pte_or_hugepte(pgdir, hva, &hugepage_shift);
         if (!ptep)
                 return __pte(0);
-        if (shift)
-                *pte_sizep = 1ul << shift;
+        if (hugepage_shift)
+                *pte_sizep = 1ul << hugepage_shift;
         else
                 *pte_sizep = PAGE_SIZE;
         if (ps > *pte_sizep)
                 return __pte(0);
-        if (!pte_present(*ptep))
-                return __pte(0);
-        return kvmppc_read_update_linux_pte(ptep, writing);
+        return kvmppc_read_update_linux_pte(ptep, writing, hugepage_shift);
 }
 
 static inline void unlock_hpte(unsigned long *hpte, unsigned long hpte_v)
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index bdc40b8e77d9..19498a567a81 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -1239,8 +1239,7 @@ out:
 #ifdef CONFIG_PPC64
 int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info)
 {
-        /* No flags */
-        info->flags = 0;
+        info->flags = KVM_PPC_1T_SEGMENTS;
 
         /* SLB is always 64 entries */
         info->slb_size = 64;
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 1020119226db..dcc94f016007 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -673,7 +673,6 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
                 ret = s;
                 goto out;
         }
-        kvmppc_lazy_ee_enable();
 
         kvm_guest_enter();
 
@@ -699,6 +698,8 @@ int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
         kvmppc_load_guest_fp(vcpu);
 #endif
 
+        kvmppc_lazy_ee_enable();
+
         ret = __kvmppc_vcpu_run(kvm_run, vcpu);
 
         /* No need for kvm_guest_exit. It's done in handle_exit.
@@ -795,7 +796,7 @@ static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
                 kvmppc_fill_pt_regs(&regs);
                 timer_interrupt(&regs);
                 break;
-#if defined(CONFIG_PPC_FSL_BOOK3E) || defined(CONFIG_PPC_BOOK3E_64)
+#if defined(CONFIG_PPC_DOORBELL)
         case BOOKE_INTERRUPT_DOORBELL:
                 kvmppc_fill_pt_regs(&regs);
                 doorbell_exception(&regs);
@@ -832,6 +833,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 {
         int r = RESUME_HOST;
         int s;
+        int idx;
+
+#ifdef CONFIG_PPC64
+        WARN_ON(local_paca->irq_happened != 0);
+#endif
+
+        /*
+         * We enter with interrupts disabled in hardware, but
+         * we need to call hard_irq_disable anyway to ensure that
+         * the software state is kept in sync.
+         */
+        hard_irq_disable();
 
         /* update before a new last_exit_type is rewritten */
         kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1066,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         break;
                 }
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1075,6 +1090,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_account_exit(vcpu, MMIO_EXITS);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
@@ -1098,6 +1114,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
 
                 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
 
+                idx = srcu_read_lock(&vcpu->kvm->srcu);
+
                 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
                 gfn = gpaddr >> PAGE_SHIFT;
 
@@ -1114,6 +1132,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
                 }
 
+                srcu_read_unlock(&vcpu->kvm->srcu, idx);
                 break;
         }
 
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index c41a5a96b558..6d6f153b6c1d 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
         struct kvm_book3e_206_tlb_entry *gtlbe;
         int tlbsel, esel;
         int recal = 0;
+        int idx;
 
         tlbsel = get_tlb_tlbsel(vcpu);
         esel = get_tlb_esel(vcpu, tlbsel);
@@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                         kvmppc_set_tlb1map_range(vcpu, gtlbe);
         }
 
+        idx = srcu_read_lock(&vcpu->kvm->srcu);
+
         /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
         if (tlbe_is_host_safe(vcpu, gtlbe)) {
                 u64 eaddr = get_tlb_eaddr(gtlbe);
@@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
         }
 
+        srcu_read_unlock(&vcpu->kvm->srcu, idx);
+
         kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
         return EMULATE_DONE;
 }
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 753cc99eff2b..19c8379575f7 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
                 r = 0;
         else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
                 r = 0;
-        else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
-                r = 0;
         else
                 r = -ENOTSUPP;
 
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index 631a2650e4e4..2c52ada30775 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -169,6 +169,9 @@ static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
                 vcpu->arch.shared->sprg3 = spr_val;
                 break;
 
+        /* PIR can legally be written, but we ignore it */
+        case SPRN_PIR: break;
+
         default:
                 emulated = kvmppc_core_emulate_mtspr(vcpu, sprn,
                                                      spr_val);
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index e15c521846ca..99c7fc16dc0d 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -580,7 +580,7 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
                 if (instr & 1)
                         regs->link = regs->nip;
                 if (branch_taken(instr, regs))
-                        regs->nip = imm;
+                        regs->nip = truncate_if_32bit(regs->msr, imm);
                 return 1;
 #ifdef CONFIG_PPC64
         case 17:        /* sc */
diff --git a/arch/powerpc/math-emu/Makefile b/arch/powerpc/math-emu/Makefile
index 7d1dba0d57f9..8d035d2d42a6 100644
--- a/arch/powerpc/math-emu/Makefile
+++ b/arch/powerpc/math-emu/Makefile
@@ -4,7 +4,8 @@ obj-$(CONFIG_MATH_EMULATION)	+= fabs.o fadd.o fadds.o fcmpo.o fcmpu.o \
                                         fmadd.o fmadds.o fmsub.o fmsubs.o \
                                         fmul.o fmuls.o fnabs.o fneg.o \
                                         fnmadd.o fnmadds.o fnmsub.o fnmsubs.o \
-                                        fres.o frsp.o frsqrte.o fsel.o lfs.o \
+                                        fres.o fre.o frsp.o fsel.o lfs.o \
+                                        frsqrte.o frsqrtes.o \
                                         fsqrt.o fsqrts.o fsub.o fsubs.o \
                                         mcrfs.o mffs.o mtfsb0.o mtfsb1.o \
                                         mtfsf.o mtfsfi.o stfiwx.o stfs.o \
diff --git a/arch/powerpc/math-emu/fre.c b/arch/powerpc/math-emu/fre.c
new file mode 100644
index 000000000000..49ccf2cc6a5a
--- /dev/null
+++ b/arch/powerpc/math-emu/fre.c
@@ -0,0 +1,11 @@
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <asm/uaccess.h>
+
+int fre(void *frD, void *frB)
+{
+#ifdef DEBUG
+        printk("%s: %p %p\n", __func__, frD, frB);
+#endif
+        return -ENOSYS;
+}
diff --git a/arch/powerpc/math-emu/frsqrtes.c b/arch/powerpc/math-emu/frsqrtes.c
new file mode 100644
index 000000000000..7e838e380314
--- /dev/null
+++ b/arch/powerpc/math-emu/frsqrtes.c
@@ -0,0 +1,11 @@
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <asm/uaccess.h>
+
+int frsqrtes(void *frD, void *frB)
+{
+#ifdef DEBUG
+        printk("%s: %p %p\n", __func__, frD, frB);
+#endif
+        return 0;
+}
diff --git a/arch/powerpc/math-emu/math.c b/arch/powerpc/math-emu/math.c
index 164d55935bd8..0328e66e0799 100644
--- a/arch/powerpc/math-emu/math.c
+++ b/arch/powerpc/math-emu/math.c
@@ -58,8 +58,10 @@ FLOATFUNC(fnabs);
 FLOATFUNC(fneg);
 
 /* Optional */
+FLOATFUNC(fre);
 FLOATFUNC(fres);
 FLOATFUNC(frsqrte);
+FLOATFUNC(frsqrtes);
 FLOATFUNC(fsel);
 FLOATFUNC(fsqrt);
 FLOATFUNC(fsqrts);
@@ -97,6 +99,7 @@ FLOATFUNC(fsqrts);
 #define FSQRTS          0x016           /*   22 */
 #define FRES            0x018           /*   24 */
 #define FMULS           0x019           /*   25 */
+#define FRSQRTES        0x01a           /*   26 */
 #define FMSUBS          0x01c           /*   28 */
 #define FMADDS          0x01d           /*   29 */
 #define FNMSUBS         0x01e           /*   30 */
@@ -109,6 +112,7 @@ FLOATFUNC(fsqrts);
 #define FADD            0x015           /*   21 */
 #define FSQRT           0x016           /*   22 */
 #define FSEL            0x017           /*   23 */
+#define FRE             0x018           /*   24 */
 #define FMUL            0x019           /*   25 */
 #define FRSQRTE         0x01a           /*   26 */
 #define FMSUB           0x01c           /*   28 */
@@ -299,9 +303,10 @@ do_mathemu(struct pt_regs *regs)
                 case FDIVS:     func = fdivs;   type = AB;      break;
                 case FSUBS:     func = fsubs;   type = AB;      break;
                 case FADDS:     func = fadds;   type = AB;      break;
-                case FSQRTS:    func = fsqrts;  type = AB;      break;
-                case FRES:      func = fres;    type = AB;      break;
+                case FSQRTS:    func = fsqrts;  type = XB;      break;
+                case FRES:      func = fres;    type = XB;      break;
                 case FMULS:     func = fmuls;   type = AC;      break;
+                case FRSQRTES:  func = frsqrtes;type = XB;      break;
                 case FMSUBS:    func = fmsubs;  type = ABC;     break;
                 case FMADDS:    func = fmadds;  type = ABC;     break;
                 case FNMSUBS:   func = fnmsubs; type = ABC;     break;
@@ -317,10 +322,11 @@ do_mathemu(struct pt_regs *regs)
                         case FDIV:      func = fdiv;    type = AB;      break;
                         case FSUB:      func = fsub;    type = AB;      break;
                         case FADD:      func = fadd;    type = AB;      break;
-                        case FSQRT:     func = fsqrt;   type = AB;      break;
+                        case FSQRT:     func = fsqrt;   type = XB;      break;
+                        case FRE:       func = fre;     type = XB;      break;
                         case FSEL:      func = fsel;    type = ABC;     break;
                         case FMUL:      func = fmul;    type = AC;      break;
-                        case FRSQRTE:   func = frsqrte; type = AB;      break;
+                        case FRSQRTE:   func = frsqrte; type = XB;      break;
                         case FMSUB:     func = fmsub;   type = ABC;     break;
                         case FMADD:     func = fmadd;   type = ABC;     break;
                         case FNMSUB:    func = fnmsub;  type = ABC;     break;
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 2c9441ee6bb8..82b1ff759e26 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -41,7 +41,7 @@ int icache_44x_need_flush;
 
 unsigned long tlb_47x_boltmap[1024/8];
 
-static void __cpuinit ppc44x_update_tlb_hwater(void)
+static void ppc44x_update_tlb_hwater(void)
 {
         extern unsigned int tlb_44x_patch_hwater_D[];
         extern unsigned int tlb_44x_patch_hwater_I[];
@@ -134,7 +134,7 @@ static void __init ppc47x_update_boltmap(void)
 /*
  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
  */
-static void __cpuinit ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
+static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
 {
         unsigned int rA;
         int bolted;
@@ -229,7 +229,7 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
 }
 
 #ifdef CONFIG_SMP
-void __cpuinit mmu_init_secondary(int cpu)
+void mmu_init_secondary(int cpu)
 {
         unsigned long addr;
         unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile
index cf16b5733eaa..51230ee6a407 100644
--- a/arch/powerpc/mm/Makefile
+++ b/arch/powerpc/mm/Makefile
@@ -6,17 +6,16 @@ subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
 
 ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC)
 
-obj-y                           := fault.o mem.o pgtable.o gup.o \
+obj-y                           := fault.o mem.o pgtable.o gup.o mmap.o \
                                    init_$(CONFIG_WORD_SIZE).o \
                                    pgtable_$(CONFIG_WORD_SIZE).o
 obj-$(CONFIG_PPC_MMU_NOHASH)    += mmu_context_nohash.o tlb_nohash.o \
                                    tlb_nohash_low.o
 obj-$(CONFIG_PPC_BOOK3E)        += tlb_low_$(CONFIG_WORD_SIZE)e.o
-obj-$(CONFIG_PPC64)             += mmap_64.o
 hash64-$(CONFIG_PPC_NATIVE)     := hash_native_64.o
 obj-$(CONFIG_PPC_STD_MMU_64)    += hash_utils_64.o \
                                    slb_low.o slb.o stab.o \
-                                   mmap_64.o $(hash64-y)
+                                   $(hash64-y)
 obj-$(CONFIG_PPC_STD_MMU_32)    += ppc_mmu_32.o
 obj-$(CONFIG_PPC_STD_MMU)       += hash_low_$(CONFIG_WORD_SIZE).o \
                                    tlb_hash$(CONFIG_WORD_SIZE).o \
@@ -28,11 +27,12 @@ obj-$(CONFIG_44x)		+= 44x_mmu.o
 obj-$(CONFIG_PPC_FSL_BOOK3E)    += fsl_booke_mmu.o
 obj-$(CONFIG_NEED_MULTIPLE_NODES) += numa.o
 obj-$(CONFIG_PPC_MM_SLICES)     += slice.o
-ifeq ($(CONFIG_HUGETLB_PAGE),y)
 obj-y                           += hugetlbpage.o
+ifeq ($(CONFIG_HUGETLB_PAGE),y)
 obj-$(CONFIG_PPC_STD_MMU_64)    += hugetlbpage-hash64.o
 obj-$(CONFIG_PPC_BOOK3E_MMU)    += hugetlbpage-book3e.o
 endif
+obj-$(CONFIG_TRANSPARENT_HUGEPAGE) += hugepage-hash64.o
 obj-$(CONFIG_PPC_SUBPAGE_PROT)  += subpage-prot.o
 obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o
 obj-$(CONFIG_HIGHMEM)           += highmem.o
diff --git a/arch/powerpc/mm/gup.c b/arch/powerpc/mm/gup.c
index 4b921affa495..49822d90ea96 100644
--- a/arch/powerpc/mm/gup.c
+++ b/arch/powerpc/mm/gup.c
@@ -34,7 +34,7 @@ static noinline int gup_pte_range(pmd_t pmd, unsigned long addr,
 
         ptep = pte_offset_kernel(&pmd, addr);
         do {
-                pte_t pte = *ptep;
+                pte_t pte = ACCESS_ONCE(*ptep);
                 struct page *page;
 
                 if ((pte_val(pte) & mask) != result)
@@ -63,12 +63,18 @@ static int gup_pmd_range(pud_t pud, unsigned long addr, unsigned long end,
 
         pmdp = pmd_offset(&pud, addr);
         do {
-                pmd_t pmd = *pmdp;
+                pmd_t pmd = ACCESS_ONCE(*pmdp);
 
                 next = pmd_addr_end(addr, end);
-                if (pmd_none(pmd))
+                /*
+                 * If we find a splitting transparent hugepage we
+                 * return zero. That will result in taking the slow
+                 * path which will call wait_split_huge_page()
+                 * if the pmd is still in splitting state
+                 */
+                if (pmd_none(pmd) || pmd_trans_splitting(pmd))
                         return 0;
-                if (pmd_huge(pmd)) {
+                if (pmd_huge(pmd) || pmd_large(pmd)) {
                         if (!gup_hugepte((pte_t *)pmdp, PMD_SIZE, addr, next,
                                          write, pages, nr))
                                 return 0;
@@ -91,7 +97,7 @@ static int gup_pud_range(pgd_t pgd, unsigned long addr, unsigned long end,
 
         pudp = pud_offset(&pgd, addr);
         do {
-                pud_t pud = *pudp;
+                pud_t pud = ACCESS_ONCE(*pudp);
 
                 next = pud_addr_end(addr, end);
                 if (pud_none(pud))
@@ -154,7 +160,7 @@ int get_user_pages_fast(unsigned long start, int nr_pages, int write,
 
         pgdp = pgd_offset(mm, addr);
         do {
-                pgd_t pgd = *pgdp;
+                pgd_t pgd = ACCESS_ONCE(*pgdp);
 
                 pr_devel("  %016lx: normal pgd %p\n", addr,
                          (void *)pgd_val(pgd));
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index 0e980acae67c..d3cbda62857b 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -289,9 +289,10 @@ htab_modify_pte:
 
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* vpn */
-        li      r6,MMU_PAGE_4K          /* page size */
-        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
-        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
+        li      r6,MMU_PAGE_4K          /* base page size */
+        li      r7,MMU_PAGE_4K          /* actual page size */
+        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(htab_call_hpte_updatepp)
         bl      .                       /* Patched by htab_finish_init() */
 
@@ -649,9 +650,10 @@ htab_modify_pte:
 
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* vpn */
-        li      r6,MMU_PAGE_4K          /* page size */
-        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
-        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
+        li      r6,MMU_PAGE_4K          /* base page size */
+        li      r7,MMU_PAGE_4K          /* actual page size */
+        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(htab_call_hpte_updatepp)
         bl      .                       /* patched by htab_finish_init() */
 
@@ -937,9 +939,10 @@ ht64_modify_pte:
 
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* vpn */
-        li      r6,MMU_PAGE_64K
-        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
-        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
+        li      r6,MMU_PAGE_64K         /* base page size */
+        li      r7,MMU_PAGE_64K         /* actual page size */
+        ld      r8,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r9,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(ht64_call_hpte_updatepp)
         bl      .                       /* patched by htab_finish_init() */
 
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 4c122c3f1623..3f0c30ae4791 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -273,61 +273,15 @@ static long native_hpte_remove(unsigned long hpte_group)
         return i;
 }
 
-static inline int __hpte_actual_psize(unsigned int lp, int psize)
-{
-        int i, shift;
-        unsigned int mask;
-
-        /* start from 1 ignoring MMU_PAGE_4K */
-        for (i = 1; i < MMU_PAGE_COUNT; i++) {
-
-                /* invalid penc */
-                if (mmu_psize_defs[psize].penc[i] == -1)
-                        continue;
-                /*
-                 * encoding bits per actual page size
-                 *        PTE LP     actual page size
-                 *    rrrr rrrz         >=8KB
-                 *    rrrr rrzz         >=16KB
-                 *    rrrr rzzz         >=32KB
-                 *    rrrr zzzz         >=64KB
-                 * .......
-                 */
-                shift = mmu_psize_defs[i].shift - LP_SHIFT;
-                if (shift > LP_BITS)
-                        shift = LP_BITS;
-                mask = (1 << shift) - 1;
-                if ((lp & mask) == mmu_psize_defs[psize].penc[i])
-                        return i;
-        }
-        return -1;
-}
-
-static inline int hpte_actual_psize(struct hash_pte *hptep, int psize)
-{
-        /* Look at the 8 bit LP value */
-        unsigned int lp = (hptep->r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
-
-        if (!(hptep->v & HPTE_V_VALID))
-                return -1;
-
-        /* First check if it is large page */
-        if (!(hptep->v & HPTE_V_LARGE))
-                return MMU_PAGE_4K;
-
-        return __hpte_actual_psize(lp, psize);
-}
-
 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
-                                 unsigned long vpn, int psize, int ssize,
-                                 int local)
+                                 unsigned long vpn, int bpsize,
+                                 int apsize, int ssize, int local)
 {
         struct hash_pte *hptep = htab_address + slot;
         unsigned long hpte_v, want_v;
         int ret = 0;
-        int actual_psize;
 
-        want_v = hpte_encode_avpn(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, bpsize, ssize);
 
         DBG_LOW("    update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
                 vpn, want_v & HPTE_V_AVPN, slot, newpp);
@@ -335,7 +289,6 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
         native_lock_hpte(hptep);
 
         hpte_v = hptep->v;
-        actual_psize = hpte_actual_psize(hptep, psize);
         /*
          * We need to invalidate the TLB always because hpte_remove doesn't do
          * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
@@ -343,12 +296,7 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
          * (hpte_remove) because we assume the old translation is still
          * technically "valid".
          */
-        if (actual_psize < 0) {
-                actual_psize = psize;
-                ret = -1;
-                goto err_out;
-        }
-        if (!HPTE_V_COMPARE(hpte_v, want_v)) {
+        if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
                 DBG_LOW(" -> miss\n");
                 ret = -1;
         } else {
@@ -357,11 +305,10 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
                 hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
                         (newpp & (HPTE_R_PP | HPTE_R_N | HPTE_R_C));
         }
-err_out:
         native_unlock_hpte(hptep);
 
         /* Ensure it is out of the tlb too. */
-        tlbie(vpn, psize, actual_psize, ssize, local);
+        tlbie(vpn, bpsize, apsize, ssize, local);
 
         return ret;
 }
@@ -402,7 +349,6 @@ static long native_hpte_find(unsigned long vpn, int psize, int ssize)
 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
                                        int psize, int ssize)
 {
-        int actual_psize;
         unsigned long vpn;
         unsigned long vsid;
         long slot;
@@ -415,36 +361,33 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
         if (slot == -1)
                 panic("could not find page to bolt\n");
         hptep = htab_address + slot;
-        actual_psize = hpte_actual_psize(hptep, psize);
-        if (actual_psize < 0)
-                actual_psize = psize;
 
         /* Update the HPTE */
         hptep->r = (hptep->r & ~(HPTE_R_PP | HPTE_R_N)) |
                 (newpp & (HPTE_R_PP | HPTE_R_N));
-
-        /* Ensure it is out of the tlb too. */
-        tlbie(vpn, psize, actual_psize, ssize, 0);
+        /*
+         * Ensure it is out of the tlb too. Bolted entries base and
+         * actual page size will be same.
+         */
+        tlbie(vpn, psize, psize, ssize, 0);
 }
 
 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
-                                   int psize, int ssize, int local)
+                                   int bpsize, int apsize, int ssize, int local)
 {
         struct hash_pte *hptep = htab_address + slot;
         unsigned long hpte_v;
         unsigned long want_v;
         unsigned long flags;
-        int actual_psize;
 
         local_irq_save(flags);
 
         DBG_LOW("    invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
 
-        want_v = hpte_encode_avpn(vpn, psize, ssize);
+        want_v = hpte_encode_avpn(vpn, bpsize, ssize);
         native_lock_hpte(hptep);
         hpte_v = hptep->v;
 
-        actual_psize = hpte_actual_psize(hptep, psize);
         /*
          * We need to invalidate the TLB always because hpte_remove doesn't do
          * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
@@ -452,23 +395,120 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
          * (hpte_remove) because we assume the old translation is still
          * technically "valid".
          */
-        if (actual_psize < 0) {
-                actual_psize = psize;
-                native_unlock_hpte(hptep);
-                goto err_out;
-        }
-        if (!HPTE_V_COMPARE(hpte_v, want_v))
+        if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
                 native_unlock_hpte(hptep);
         else
                 /* Invalidate the hpte. NOTE: this also unlocks it */
                 hptep->v = 0;
 
-err_out:
         /* Invalidate the TLB */
-        tlbie(vpn, psize, actual_psize, ssize, local);
+        tlbie(vpn, bpsize, apsize, ssize, local);
+
+        local_irq_restore(flags);
+}
+
+static void native_hugepage_invalidate(struct mm_struct *mm,
+                                       unsigned char *hpte_slot_array,
+                                       unsigned long addr, int psize)
+{
+        int ssize = 0, i;
+        int lock_tlbie;
+        struct hash_pte *hptep;
+        int actual_psize = MMU_PAGE_16M;
+        unsigned int max_hpte_count, valid;
+        unsigned long flags, s_addr = addr;
+        unsigned long hpte_v, want_v, shift;
+        unsigned long hidx, vpn = 0, vsid, hash, slot;
+
+        shift = mmu_psize_defs[psize].shift;
+        max_hpte_count = 1U << (PMD_SHIFT - shift);
+
+        local_irq_save(flags);
+        for (i = 0; i < max_hpte_count; i++) {
+                valid = hpte_valid(hpte_slot_array, i);
+                if (!valid)
+                        continue;
+                hidx =  hpte_hash_index(hpte_slot_array, i);
+
+                /* get the vpn */
+                addr = s_addr + (i * (1ul << shift));
+                if (!is_kernel_addr(addr)) {
+                        ssize = user_segment_size(addr);
+                        vsid = get_vsid(mm->context.id, addr, ssize);
+                        WARN_ON(vsid == 0);
+                } else {
+                        vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
+                        ssize = mmu_kernel_ssize;
+                }
+
+                vpn = hpt_vpn(addr, vsid, ssize);
+                hash = hpt_hash(vpn, shift, ssize);
+                if (hidx & _PTEIDX_SECONDARY)
+                        hash = ~hash;
+
+                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+                slot += hidx & _PTEIDX_GROUP_IX;
+
+                hptep = htab_address + slot;
+                want_v = hpte_encode_avpn(vpn, psize, ssize);
+                native_lock_hpte(hptep);
+                hpte_v = hptep->v;
+
+                /* Even if we miss, we need to invalidate the TLB */
+                if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
+                        native_unlock_hpte(hptep);
+                else
+                        /* Invalidate the hpte. NOTE: this also unlocks it */
+                        hptep->v = 0;
+        }
+        /*
+         * Since this is a hugepage, we just need a single tlbie.
+         * use the last vpn.
+         */
+        lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
+        if (lock_tlbie)
+                raw_spin_lock(&native_tlbie_lock);
+
+        asm volatile("ptesync":::"memory");
+        __tlbie(vpn, psize, actual_psize, ssize);
+        asm volatile("eieio; tlbsync; ptesync":::"memory");
+
+        if (lock_tlbie)
+                raw_spin_unlock(&native_tlbie_lock);
+
         local_irq_restore(flags);
 }
 
+static inline int __hpte_actual_psize(unsigned int lp, int psize)
+{
+        int i, shift;
+        unsigned int mask;
+
+        /* start from 1 ignoring MMU_PAGE_4K */
+        for (i = 1; i < MMU_PAGE_COUNT; i++) {
+
+                /* invalid penc */
+                if (mmu_psize_defs[psize].penc[i] == -1)
+                        continue;
+                /*
+                 * encoding bits per actual page size
+                 *        PTE LP     actual page size
+                 *    rrrr rrrz         >=8KB
+                 *    rrrr rrzz         >=16KB
+                 *    rrrr rzzz         >=32KB
+                 *    rrrr zzzz         >=64KB
+                 * .......
+                 */
+                shift = mmu_psize_defs[i].shift - LP_SHIFT;
+                if (shift > LP_BITS)
+                        shift = LP_BITS;
+                mask = (1 << shift) - 1;
+                if ((lp & mask) == mmu_psize_defs[psize].penc[i])
+                        return i;
+        }
+        return -1;
+}
+
 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
                         int *psize, int *apsize, int *ssize, unsigned long *vpn)
 {
@@ -672,4 +712,5 @@ void __init hpte_init_native(void)
         ppc_md.hpte_remove      = native_hpte_remove;
         ppc_md.hpte_clear_all   = native_hpte_clear;
         ppc_md.flush_hash_range = native_flush_hash_range;
+        ppc_md.hugepage_invalidate   = native_hugepage_invalidate;
 }
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index e303a6d74e3a..6ecc38bd5b24 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -807,7 +807,7 @@ void __init early_init_mmu(void)
 }
 
 #ifdef CONFIG_SMP
-void __cpuinit early_init_mmu_secondary(void)
+void early_init_mmu_secondary(void)
 {
         /* Initialize hash table for that CPU */
         if (!firmware_has_feature(FW_FEATURE_LPAR))
@@ -1050,13 +1050,26 @@ int hash_page(unsigned long ea, unsigned long access, unsigned long trap)
                 goto bail;
         }
 
-#ifdef CONFIG_HUGETLB_PAGE
         if (hugeshift) {
-                rc = __hash_page_huge(ea, access, vsid, ptep, trap, local,
-                                        ssize, hugeshift, psize);
+                if (pmd_trans_huge(*(pmd_t *)ptep))
+                        rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
+                                             trap, local, ssize, psize);
+#ifdef CONFIG_HUGETLB_PAGE
+                else
+                        rc = __hash_page_huge(ea, access, vsid, ptep, trap,
+                                              local, ssize, hugeshift, psize);
+#else
+                else {
+                        /*
+                         * if we have hugeshift, and is not transhuge with
+                         * hugetlb disabled, something is really wrong.
+                         */
+                        rc = 1;
+                        WARN_ON(1);
+                }
+#endif
                 goto bail;
         }
-#endif /* CONFIG_HUGETLB_PAGE */
 
 #ifndef CONFIG_PPC_64K_PAGES
         DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
@@ -1145,6 +1158,7 @@ EXPORT_SYMBOL_GPL(hash_page);
 void hash_preload(struct mm_struct *mm, unsigned long ea,
                   unsigned long access, unsigned long trap)
 {
+        int hugepage_shift;
         unsigned long vsid;
         pgd_t *pgdir;
         pte_t *ptep;
@@ -1166,10 +1180,27 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
         pgdir = mm->pgd;
         if (pgdir == NULL)
                 return;
-        ptep = find_linux_pte(pgdir, ea);
-        if (!ptep)
+
+        /* Get VSID */
+        ssize = user_segment_size(ea);
+        vsid = get_vsid(mm->context.id, ea, ssize);
+        if (!vsid)
                 return;
+        /*
+         * Hash doesn't like irqs. Walking linux page table with irq disabled
+         * saves us from holding multiple locks.
+         */
+        local_irq_save(flags);
+
+        /*
+         * THP pages use update_mmu_cache_pmd. We don't do
+         * hash preload there. Hence can ignore THP here
+         */
+        ptep = find_linux_pte_or_hugepte(pgdir, ea, &hugepage_shift);
+        if (!ptep)
+                goto out_exit;
 
+        WARN_ON(hugepage_shift);
 #ifdef CONFIG_PPC_64K_PAGES
         /* If either _PAGE_4K_PFN or _PAGE_NO_CACHE is set (and we are on
          * a 64K kernel), then we don't preload, hash_page() will take
@@ -1178,18 +1209,9 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
          * page size demotion here
          */
         if (pte_val(*ptep) & (_PAGE_4K_PFN | _PAGE_NO_CACHE))
-                return;
+                goto out_exit;
 #endif /* CONFIG_PPC_64K_PAGES */
 
-        /* Get VSID */
-        ssize = user_segment_size(ea);
-        vsid = get_vsid(mm->context.id, ea, ssize);
-        if (!vsid)
-                return;
-
-        /* Hash doesn't like irqs */
-        local_irq_save(flags);
-
         /* Is that local to this CPU ? */
         if (cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id())))
                 local = 1;
@@ -1211,7 +1233,7 @@ void hash_preload(struct mm_struct *mm, unsigned long ea,
                                    mm->context.user_psize,
                                    mm->context.user_psize,
                                    pte_val(*ptep));
-
+out_exit:
         local_irq_restore(flags);
 }
 
@@ -1232,7 +1254,11 @@ void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
                 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                 slot += hidx & _PTEIDX_GROUP_IX;
                 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
-                ppc_md.hpte_invalidate(slot, vpn, psize, ssize, local);
+                /*
+                 * We use same base page size and actual psize, because we don't
+                 * use these functions for hugepage
+                 */
+                ppc_md.hpte_invalidate(slot, vpn, psize, psize, ssize, local);
         } pte_iterate_hashed_end();
 
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
@@ -1365,7 +1391,8 @@ static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
                 hash = ~hash;
         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
         slot += hidx & _PTEIDX_GROUP_IX;
-        ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_kernel_ssize, 0);
+        ppc_md.hpte_invalidate(slot, vpn, mmu_linear_psize, mmu_linear_psize,
+                               mmu_kernel_ssize, 0);
 }
 
 void kernel_map_pages(struct page *page, int numpages, int enable)
diff --git a/arch/powerpc/mm/hugepage-hash64.c b/arch/powerpc/mm/hugepage-hash64.c
new file mode 100644
index 000000000000..34de9e0cdc34
--- /dev/null
+++ b/arch/powerpc/mm/hugepage-hash64.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright IBM Corporation, 2013
+ * Author Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2.1 of the GNU Lesser General Public License
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it would be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+
+/*
+ * PPC64 THP Support for hash based MMUs
+ */
+#include <linux/mm.h>
+#include <asm/machdep.h>
+
+int __hash_page_thp(unsigned long ea, unsigned long access, unsigned long vsid,
+                    pmd_t *pmdp, unsigned long trap, int local, int ssize,
+                    unsigned int psize)
+{
+        unsigned int index, valid;
+        unsigned char *hpte_slot_array;
+        unsigned long rflags, pa, hidx;
+        unsigned long old_pmd, new_pmd;
+        int ret, lpsize = MMU_PAGE_16M;
+        unsigned long vpn, hash, shift, slot;
+
+        /*
+         * atomically mark the linux large page PMD busy and dirty
+         */
+        do {
+                old_pmd = pmd_val(*pmdp);
+                /* If PMD busy, retry the access */
+                if (unlikely(old_pmd & _PAGE_BUSY))
+                        return 0;
+                /* If PMD is trans splitting retry the access */
+                if (unlikely(old_pmd & _PAGE_SPLITTING))
+                        return 0;
+                /* If PMD permissions don't match, take page fault */
+                if (unlikely(access & ~old_pmd))
+                        return 1;
+                /*
+                 * Try to lock the PTE, add ACCESSED and DIRTY if it was
+                 * a write access
+                 */
+                new_pmd = old_pmd | _PAGE_BUSY | _PAGE_ACCESSED;
+                if (access & _PAGE_RW)
+                        new_pmd |= _PAGE_DIRTY;
+        } while (old_pmd != __cmpxchg_u64((unsigned long *)pmdp,
+                                          old_pmd, new_pmd));
+        /*
+         * PP bits. _PAGE_USER is already PP bit 0x2, so we only
+         * need to add in 0x1 if it's a read-only user page
+         */
+        rflags = new_pmd & _PAGE_USER;
+        if ((new_pmd & _PAGE_USER) && !((new_pmd & _PAGE_RW) &&
+                                           (new_pmd & _PAGE_DIRTY)))
+                rflags |= 0x1;
+        /*
+         * _PAGE_EXEC -> HW_NO_EXEC since it's inverted
+         */
+        rflags |= ((new_pmd & _PAGE_EXEC) ? 0 : HPTE_R_N);
+
+#if 0
+        if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
+
+                /*
+                 * No CPU has hugepages but lacks no execute, so we
+                 * don't need to worry about that case
+                 */
+                rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);
+        }
+#endif
+        /*
+         * Find the slot index details for this ea, using base page size.
+         */
+        shift = mmu_psize_defs[psize].shift;
+        index = (ea & ~HPAGE_PMD_MASK) >> shift;
+        BUG_ON(index >= 4096);
+
+        vpn = hpt_vpn(ea, vsid, ssize);
+        hash = hpt_hash(vpn, shift, ssize);
+        hpte_slot_array = get_hpte_slot_array(pmdp);
+
+        valid = hpte_valid(hpte_slot_array, index);
+        if (valid) {
+                /* update the hpte bits */
+                hidx =  hpte_hash_index(hpte_slot_array, index);
+                if (hidx & _PTEIDX_SECONDARY)
+                        hash = ~hash;
+                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+                slot += hidx & _PTEIDX_GROUP_IX;
+
+                ret = ppc_md.hpte_updatepp(slot, rflags, vpn,
+                                           psize, lpsize, ssize, local);
+                /*
+                 * We failed to update, try to insert a new entry.
+                 */
+                if (ret == -1) {
+                        /*
+                         * large pte is marked busy, so we can be sure
+                         * nobody is looking at hpte_slot_array. hence we can
+                         * safely update this here.
+                         */
+                        valid = 0;
+                        new_pmd &= ~_PAGE_HPTEFLAGS;
+                        hpte_slot_array[index] = 0;
+                } else
+                        /* clear the busy bits and set the hash pte bits */
+                        new_pmd = (new_pmd & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
+        }
+
+        if (!valid) {
+                unsigned long hpte_group;
+
+                /* insert new entry */
+                pa = pmd_pfn(__pmd(old_pmd)) << PAGE_SHIFT;
+repeat:
+                hpte_group = ((hash & htab_hash_mask) * HPTES_PER_GROUP) & ~0x7UL;
+
+                /* clear the busy bits and set the hash pte bits */
+                new_pmd = (new_pmd & ~_PAGE_HPTEFLAGS) | _PAGE_HASHPTE;
+
+                /* Add in WIMG bits */
+                rflags |= (new_pmd & (_PAGE_WRITETHRU | _PAGE_NO_CACHE |
+                                      _PAGE_COHERENT | _PAGE_GUARDED));
+
+                /* Insert into the hash table, primary slot */
+                slot = ppc_md.hpte_insert(hpte_group, vpn, pa, rflags, 0,
+                                          psize, lpsize, ssize);
+                /*
+                 * Primary is full, try the secondary
+                 */
+                if (unlikely(slot == -1)) {
+                        hpte_group = ((~hash & htab_hash_mask) *
+                                      HPTES_PER_GROUP) & ~0x7UL;
+                        slot = ppc_md.hpte_insert(hpte_group, vpn, pa,
+                                                  rflags, HPTE_V_SECONDARY,
+                                                  psize, lpsize, ssize);
+                        if (slot == -1) {
+                                if (mftb() & 0x1)
+                                        hpte_group = ((hash & htab_hash_mask) *
+                                                      HPTES_PER_GROUP) & ~0x7UL;
+
+                                ppc_md.hpte_remove(hpte_group);
+                                goto repeat;
+                        }
+                }
+                /*
+                 * Hypervisor failure. Restore old pmd and return -1
+                 * similar to __hash_page_*
+                 */
+                if (unlikely(slot == -2)) {
+                        *pmdp = __pmd(old_pmd);
+                        hash_failure_debug(ea, access, vsid, trap, ssize,
+                                           psize, lpsize, old_pmd);
+                        return -1;
+                }
+                /*
+                 * large pte is marked busy, so we can be sure
+                 * nobody is looking at hpte_slot_array. hence we can
+                 * safely update this here.
+                 */
+                mark_hpte_slot_valid(hpte_slot_array, index, slot);
+        }
+        /*
+         * No need to use ldarx/stdcx here
+         */
+        *pmdp = __pmd(new_pmd & ~_PAGE_BUSY);
+        return 0;
+}
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index 0f1d94a1fb82..0b7fb6761015 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -81,7 +81,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
                 slot += (old_pte & _PAGE_F_GIX) >> 12;
 
                 if (ppc_md.hpte_updatepp(slot, rflags, vpn, mmu_psize,
-                                         ssize, local) == -1)
+                                         mmu_psize, ssize, local) == -1)
                         old_pte &= ~_PAGE_HPTEFLAGS;
         }
 
diff --git a/arch/powerpc/mm/hugetlbpage.c b/arch/powerpc/mm/hugetlbpage.c
index 237c8e5f2640..834ca8eb38f2 100644
--- a/arch/powerpc/mm/hugetlbpage.c
+++ b/arch/powerpc/mm/hugetlbpage.c
@@ -21,6 +21,9 @@
 #include <asm/pgalloc.h>
 #include <asm/tlb.h>
 #include <asm/setup.h>
+#include <asm/hugetlb.h>
+
+#ifdef CONFIG_HUGETLB_PAGE
 
 #define PAGE_SHIFT_64K  16
 #define PAGE_SHIFT_16M  24
@@ -100,68 +103,9 @@ int pgd_huge(pgd_t pgd)
 }
 #endif
 
-/*
- * We have 4 cases for pgds and pmds:
- * (1) invalid (all zeroes)
- * (2) pointer to next table, as normal; bottom 6 bits == 0
- * (3) leaf pte for huge page, bottom two bits != 00
- * (4) hugepd pointer, bottom two bits == 00, next 4 bits indicate size of table
- */
-pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift)
-{
-        pgd_t *pg;
-        pud_t *pu;
-        pmd_t *pm;
-        pte_t *ret_pte;
-        hugepd_t *hpdp = NULL;
-        unsigned pdshift = PGDIR_SHIFT;
-
-        if (shift)
-                *shift = 0;
-
-        pg = pgdir + pgd_index(ea);
-
-        if (pgd_huge(*pg)) {
-                ret_pte = (pte_t *) pg;
-                goto out;
-        } else if (is_hugepd(pg))
-                hpdp = (hugepd_t *)pg;
-        else if (!pgd_none(*pg)) {
-                pdshift = PUD_SHIFT;
-                pu = pud_offset(pg, ea);
-
-                if (pud_huge(*pu)) {
-                        ret_pte = (pte_t *) pu;
-                        goto out;
-                } else if (is_hugepd(pu))
-                        hpdp = (hugepd_t *)pu;
-                else if (!pud_none(*pu)) {
-                        pdshift = PMD_SHIFT;
-                        pm = pmd_offset(pu, ea);
-
-                        if (pmd_huge(*pm)) {
-                                ret_pte = (pte_t *) pm;
-                                goto out;
-                        } else if (is_hugepd(pm))
-                                hpdp = (hugepd_t *)pm;
-                        else if (!pmd_none(*pm))
-                                return pte_offset_kernel(pm, ea);
-                }
-        }
-        if (!hpdp)
-                return NULL;
-
-        ret_pte = hugepte_offset(hpdp, ea, pdshift);
-        pdshift = hugepd_shift(*hpdp);
-out:
-        if (shift)
-                *shift = pdshift;
-        return ret_pte;
-}
-EXPORT_SYMBOL_GPL(find_linux_pte_or_hugepte);
-
 pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
 {
+        /* Only called for hugetlbfs pages, hence can ignore THP */
         return find_linux_pte_or_hugepte(mm->pgd, addr, NULL);
 }
 
@@ -357,7 +301,7 @@ void add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages)
 int alloc_bootmem_huge_page(struct hstate *hstate)
 {
         struct huge_bootmem_page *m;
-        int idx = shift_to_mmu_psize(hstate->order + PAGE_SHIFT);
+        int idx = shift_to_mmu_psize(huge_page_shift(hstate));
         int nr_gpages = gpage_freearray[idx].nr_gpages;
 
         if (nr_gpages == 0)
@@ -592,8 +536,14 @@ static void hugetlb_free_pmd_range(struct mmu_gather *tlb, pud_t *pud,
         do {
                 pmd = pmd_offset(pud, addr);
                 next = pmd_addr_end(addr, end);
-                if (pmd_none_or_clear_bad(pmd))
+                if (!is_hugepd(pmd)) {
+                        /*
+                         * if it is not hugepd pointer, we should already find
+                         * it cleared.
+                         */
+                        WARN_ON(!pmd_none_or_clear_bad(pmd));
                         continue;
+                }
 #ifdef CONFIG_PPC_FSL_BOOK3E
                 /*
                  * Increment next by the size of the huge mapping since
@@ -730,11 +680,14 @@ follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
         struct page *page;
         unsigned shift;
         unsigned long mask;
-
+        /*
+         * Transparent hugepages are handled by generic code. We can skip them
+         * here.
+         */
         ptep = find_linux_pte_or_hugepte(mm->pgd, address, &shift);
 
         /* Verify it is a huge page else bail. */
-        if (!ptep || !shift)
+        if (!ptep || !shift || pmd_trans_huge(*(pmd_t *)ptep))
                 return ERR_PTR(-EINVAL);
 
         mask = (1UL << shift) - 1;
@@ -753,69 +706,6 @@ follow_huge_pmd(struct mm_struct *mm, unsigned long address,
         return NULL;
 }
 
-int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
-                unsigned long end, int write, struct page **pages, int *nr)
-{
-        unsigned long mask;
-        unsigned long pte_end;
-        struct page *head, *page, *tail;
-        pte_t pte;
-        int refs;
-
-        pte_end = (addr + sz) & ~(sz-1);
-        if (pte_end < end)
-                end = pte_end;
-
-        pte = *ptep;
-        mask = _PAGE_PRESENT | _PAGE_USER;
-        if (write)
-                mask |= _PAGE_RW;
-
-        if ((pte_val(pte) & mask) != mask)
-                return 0;
-
-        /* hugepages are never "special" */
-        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
-
-        refs = 0;
-        head = pte_page(pte);
-
-        page = head + ((addr & (sz-1)) >> PAGE_SHIFT);
-        tail = page;
-        do {
-                VM_BUG_ON(compound_head(page) != head);
-                pages[*nr] = page;
-                (*nr)++;
-                page++;
-                refs++;
-        } while (addr += PAGE_SIZE, addr != end);
-
-        if (!page_cache_add_speculative(head, refs)) {
-                *nr -= refs;
-                return 0;
-        }
-
-        if (unlikely(pte_val(pte) != pte_val(*ptep))) {
-                /* Could be optimized better */
-                *nr -= refs;
-                while (refs--)
-                        put_page(head);
-                return 0;
-        }
-
-        /*
-         * Any tail page need their mapcount reference taken before we
-         * return.
-         */
-        while (refs--) {
-                if (PageTail(tail))
-                        get_huge_page_tail(tail);
-                tail++;
-        }
-
-        return 1;
-}
-
 static unsigned long hugepte_addr_end(unsigned long addr, unsigned long end,
                                       unsigned long sz)
 {
@@ -1032,3 +922,168 @@ void flush_dcache_icache_hugepage(struct page *page)
                 }
         }
 }
+
+#endif /* CONFIG_HUGETLB_PAGE */
+
+/*
+ * We have 4 cases for pgds and pmds:
+ * (1) invalid (all zeroes)
+ * (2) pointer to next table, as normal; bottom 6 bits == 0
+ * (3) leaf pte for huge page, bottom two bits != 00
+ * (4) hugepd pointer, bottom two bits == 00, next 4 bits indicate size of table
+ *
+ * So long as we atomically load page table pointers we are safe against teardown,
+ * we can follow the address down to the the page and take a ref on it.
+ */
+
+pte_t *find_linux_pte_or_hugepte(pgd_t *pgdir, unsigned long ea, unsigned *shift)
+{
+        pgd_t pgd, *pgdp;
+        pud_t pud, *pudp;
+        pmd_t pmd, *pmdp;
+        pte_t *ret_pte;
+        hugepd_t *hpdp = NULL;
+        unsigned pdshift = PGDIR_SHIFT;
+
+        if (shift)
+                *shift = 0;
+
+        pgdp = pgdir + pgd_index(ea);
+        pgd  = ACCESS_ONCE(*pgdp);
+        /*
+         * Always operate on the local stack value. This make sure the
+         * value don't get updated by a parallel THP split/collapse,
+         * page fault or a page unmap. The return pte_t * is still not
+         * stable. So should be checked there for above conditions.
+         */
+        if (pgd_none(pgd))
+                return NULL;
+        else if (pgd_huge(pgd)) {
+                ret_pte = (pte_t *) pgdp;
+                goto out;
+        } else if (is_hugepd(&pgd))
+                hpdp = (hugepd_t *)&pgd;
+        else {
+                /*
+                 * Even if we end up with an unmap, the pgtable will not
+                 * be freed, because we do an rcu free and here we are
+                 * irq disabled
+                 */
+                pdshift = PUD_SHIFT;
+                pudp = pud_offset(&pgd, ea);
+                pud  = ACCESS_ONCE(*pudp);
+
+                if (pud_none(pud))
+                        return NULL;
+                else if (pud_huge(pud)) {
+                        ret_pte = (pte_t *) pudp;
+                        goto out;
+                } else if (is_hugepd(&pud))
+                        hpdp = (hugepd_t *)&pud;
+                else {
+                        pdshift = PMD_SHIFT;
+                        pmdp = pmd_offset(&pud, ea);
+                        pmd  = ACCESS_ONCE(*pmdp);
+                        /*
+                         * A hugepage collapse is captured by pmd_none, because
+                         * it mark the pmd none and do a hpte invalidate.
+                         *
+                         * A hugepage split is captured by pmd_trans_splitting
+                         * because we mark the pmd trans splitting and do a
+                         * hpte invalidate
+                         *
+                         */
+                        if (pmd_none(pmd) || pmd_trans_splitting(pmd))
+                                return NULL;
+
+                        if (pmd_huge(pmd) || pmd_large(pmd)) {
+                                ret_pte = (pte_t *) pmdp;
+                                goto out;
+                        } else if (is_hugepd(&pmd))
+                                hpdp = (hugepd_t *)&pmd;
+                        else
+                                return pte_offset_kernel(&pmd, ea);
+                }
+        }
+        if (!hpdp)
+                return NULL;
+
+        ret_pte = hugepte_offset(hpdp, ea, pdshift);
+        pdshift = hugepd_shift(*hpdp);
+out:
+        if (shift)
+                *shift = pdshift;
+        return ret_pte;
+}
+EXPORT_SYMBOL_GPL(find_linux_pte_or_hugepte);
+
+int gup_hugepte(pte_t *ptep, unsigned long sz, unsigned long addr,
+                unsigned long end, int write, struct page **pages, int *nr)
+{
+        unsigned long mask;
+        unsigned long pte_end;
+        struct page *head, *page, *tail;
+        pte_t pte;
+        int refs;
+
+        pte_end = (addr + sz) & ~(sz-1);
+        if (pte_end < end)
+                end = pte_end;
+
+        pte = ACCESS_ONCE(*ptep);
+        mask = _PAGE_PRESENT | _PAGE_USER;
+        if (write)
+                mask |= _PAGE_RW;
+
+        if ((pte_val(pte) & mask) != mask)
+                return 0;
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+        /*
+         * check for splitting here
+         */
+        if (pmd_trans_splitting(pte_pmd(pte)))
+                return 0;
+#endif
+
+        /* hugepages are never "special" */
+        VM_BUG_ON(!pfn_valid(pte_pfn(pte)));
+
+        refs = 0;
+        head = pte_page(pte);
+
+        page = head + ((addr & (sz-1)) >> PAGE_SHIFT);
+        tail = page;
+        do {
+                VM_BUG_ON(compound_head(page) != head);
+                pages[*nr] = page;
+                (*nr)++;
+                page++;
+                refs++;
+        } while (addr += PAGE_SIZE, addr != end);
+
+        if (!page_cache_add_speculative(head, refs)) {
+                *nr -= refs;
+                return 0;
+        }
+
+        if (unlikely(pte_val(pte) != pte_val(*ptep))) {
+                /* Could be optimized better */
+                *nr -= refs;
+                while (refs--)
+                        put_page(head);
+                return 0;
+        }
+
+        /*
+         * Any tail page need their mapcount reference taken before we
+         * return.
+         */
+        while (refs--) {
+                if (PageTail(tail))
+                        get_huge_page_tail(tail);
+                tail++;
+        }
+
+        return 1;
+}
diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c
index a90b9c458990..d0cd9e4c6837 100644
--- a/arch/powerpc/mm/init_64.c
+++ b/arch/powerpc/mm/init_64.c
@@ -88,7 +88,11 @@ static void pgd_ctor(void *addr)
 
 static void pmd_ctor(void *addr)
 {
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+        memset(addr, 0, PMD_TABLE_SIZE * 2);
+#else
         memset(addr, 0, PMD_TABLE_SIZE);
+#endif
 }
 
 struct kmem_cache *pgtable_cache[MAX_PGTABLE_INDEX_SIZE];
@@ -137,10 +141,9 @@ void pgtable_cache_add(unsigned shift, void (*ctor)(void *))
 void pgtable_cache_init(void)
 {
         pgtable_cache_add(PGD_INDEX_SIZE, pgd_ctor);
-        pgtable_cache_add(PMD_INDEX_SIZE, pmd_ctor);
-        if (!PGT_CACHE(PGD_INDEX_SIZE) || !PGT_CACHE(PMD_INDEX_SIZE))
+        pgtable_cache_add(PMD_CACHE_INDEX, pmd_ctor);
+        if (!PGT_CACHE(PGD_INDEX_SIZE) || !PGT_CACHE(PMD_CACHE_INDEX))
                 panic("Couldn't allocate pgtable caches");
-
         /* In all current configs, when the PUD index exists it's the
          * same size as either the pgd or pmd index.  Verify that the
          * initialization above has also created a PUD cache.  This
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 0988a26e0413..7f4bea162026 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -299,47 +299,13 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-        int nid;
-#endif
-        pg_data_t *pgdat;
-        unsigned long i;
-        struct page *page;
-        unsigned long reservedpages = 0, codesize, initsize, datasize, bsssize;
-
 #ifdef CONFIG_SWIOTLB
         swiotlb_init(0);
 #endif
 
-        num_physpages = memblock_phys_mem_size() >> PAGE_SHIFT;
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
-
-#ifdef CONFIG_NEED_MULTIPLE_NODES
-        for_each_online_node(nid) {
-                if (NODE_DATA(nid)->node_spanned_pages != 0) {
-                        printk("freeing bootmem node %d\n", nid);
-                        totalram_pages +=
-                                free_all_bootmem_node(NODE_DATA(nid));
-                }
-        }
-#else
-        max_mapnr = max_pfn;
-        totalram_pages += free_all_bootmem();
-#endif
-        for_each_online_pgdat(pgdat) {
-                for (i = 0; i < pgdat->node_spanned_pages; i++) {
-                        if (!pfn_valid(pgdat->node_start_pfn + i))
-                                continue;
-                        page = pgdat_page_nr(pgdat, i);
-                        if (PageReserved(page))
-                                reservedpages++;
-                }
-        }
-
-        codesize = (unsigned long)&_sdata - (unsigned long)&_stext;
-        datasize = (unsigned long)&_edata - (unsigned long)&_sdata;
-        initsize = (unsigned long)&__init_end - (unsigned long)&__init_begin;
-        bsssize = (unsigned long)&__bss_stop - (unsigned long)&__bss_start;
+        set_max_mapnr(max_pfn);
+        free_all_bootmem();
 
 #ifdef CONFIG_HIGHMEM
         {
@@ -349,13 +315,9 @@ void __init mem_init(void)
                 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
                         phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
                         struct page *page = pfn_to_page(pfn);
-                        if (memblock_is_reserved(paddr))
-                                continue;
-                        free_highmem_page(page);
-                        reservedpages--;
+                        if (!memblock_is_reserved(paddr))
+                                free_highmem_page(page);
                 }
-                printk(KERN_DEBUG "High memory: %luk\n",
-                       totalhigh_pages << (PAGE_SHIFT-10));
         }
 #endif /* CONFIG_HIGHMEM */
 
@@ -368,16 +330,7 @@ void __init mem_init(void)
                 (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
 #endif
 
-        printk(KERN_INFO "Memory: %luk/%luk available (%luk kernel code, "
-               "%luk reserved, %luk data, %luk bss, %luk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                bsssize >> 10,
-                initsize >> 10);
-
+        mem_init_print_info(NULL);
 #ifdef CONFIG_PPC32
         pr_info("Kernel virtual memory layout:\n");
         pr_info("  * 0x%08lx..0x%08lx  : fixmap\n", FIXADDR_START, FIXADDR_TOP);
@@ -407,7 +360,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
@@ -508,6 +461,10 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
                       pte_t *ptep)
 {
 #ifdef CONFIG_PPC_STD_MMU
+        /*
+         * We don't need to worry about _PAGE_PRESENT here because we are
+         * called with either mm->page_table_lock held or ptl lock held
+         */
         unsigned long access = 0, trap;
 
         /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
diff --git a/arch/powerpc/mm/mmap_64.c b/arch/powerpc/mm/mmap.c
index 67a42ed0d2fc..67a42ed0d2fc 100644
--- a/arch/powerpc/mm/mmap_64.c
+++ b/arch/powerpc/mm/mmap.c
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index e779642c25e5..af3d78e19302 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -112,8 +112,10 @@ static unsigned int steal_context_smp(unsigned int id)
                  */
                 for_each_cpu(cpu, mm_cpumask(mm)) {
                         for (i = cpu_first_thread_sibling(cpu);
-                             i <= cpu_last_thread_sibling(cpu); i++)
-                                __set_bit(id, stale_map[i]);
+                             i <= cpu_last_thread_sibling(cpu); i++) {
+                                if (stale_map[i])
+                                        __set_bit(id, stale_map[i]);
+                        }
                         cpu = i - 1;
                 }
                 return id;
@@ -272,7 +274,8 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
                 /* XXX This clear should ultimately be part of local_flush_tlb_mm */
                 for (i = cpu_first_thread_sibling(cpu);
                      i <= cpu_last_thread_sibling(cpu); i++) {
-                        __clear_bit(id, stale_map[i]);
+                        if (stale_map[i])
+                                __clear_bit(id, stale_map[i]);
                 }
         }
 
@@ -329,8 +332,8 @@ void destroy_context(struct mm_struct *mm)
 
 #ifdef CONFIG_SMP
 
-static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
-                                            unsigned long action, void *hcpu)
+static int mmu_context_cpu_notify(struct notifier_block *self,
+                                  unsigned long action, void *hcpu)
 {
         unsigned int cpu = (unsigned int)(long)hcpu;
 
@@ -363,7 +366,7 @@ static int __cpuinit mmu_context_cpu_notify(struct notifier_block *self,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata mmu_context_cpu_nb = {
+static struct notifier_block mmu_context_cpu_nb = {
         .notifier_call  = mmu_context_cpu_notify,
 };
 
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 88c0425dc0a8..08397217e8ac 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -516,7 +516,7 @@ static int of_drconf_to_nid_single(struct of_drconf_cell *drmem,
  * Figure out to which domain a cpu belongs and stick it there.
  * Return the id of the domain used.
  */
-static int __cpuinit numa_setup_cpu(unsigned long lcpu)
+static int numa_setup_cpu(unsigned long lcpu)
 {
         int nid = 0;
         struct device_node *cpu = of_get_cpu_node(lcpu, NULL);
@@ -538,8 +538,7 @@ out:
         return nid;
 }
 
-static int __cpuinit cpu_numa_callback(struct notifier_block *nfb,
-                             unsigned long action,
+static int cpu_numa_callback(struct notifier_block *nfb, unsigned long action,
                              void *hcpu)
 {
         unsigned long lcpu = (unsigned long)hcpu;
@@ -919,7 +918,7 @@ static void __init *careful_zallocation(int nid, unsigned long size,
         return ret;
 }
 
-static struct notifier_block __cpuinitdata ppc64_numa_nb = {
+static struct notifier_block ppc64_numa_nb = {
         .notifier_call = cpu_numa_callback,
         .priority = 1 /* Must run before sched domains notifier. */
 };
@@ -1433,11 +1432,9 @@ static int update_cpu_topology(void *data)
                 if (cpu != update->cpu)
                         continue;
 
-                unregister_cpu_under_node(update->cpu, update->old_nid);
                 unmap_cpu_from_node(update->cpu);
                 map_cpu_to_node(update->cpu, update->new_nid);
                 vdso_getcpu_init();
-                register_cpu_under_node(update->cpu, update->new_nid);
         }
 
         return 0;
@@ -1485,6 +1482,9 @@ int arch_update_cpu_topology(void)
         stop_machine(update_cpu_topology, &updates[0], &updated_cpus);
 
         for (ud = &updates[0]; ud; ud = ud->next) {
+                unregister_cpu_under_node(ud->cpu, ud->old_nid);
+                register_cpu_under_node(ud->cpu, ud->new_nid);
+
                 dev = get_cpu_device(ud->cpu);
                 if (dev)
                         kobject_uevent(&dev->kobj, KOBJ_CHANGE);
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 214130a4edc6..edda589795c3 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -235,6 +235,14 @@ void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
         pud = pud_offset(pgd, addr);
         BUG_ON(pud_none(*pud));
         pmd = pmd_offset(pud, addr);
+        /*
+         * khugepaged to collapse normal pages to hugepage, first set
+         * pmd to none to force page fault/gup to take mmap_sem. After
+         * pmd is set to none, we do a pte_clear which does this assertion
+         * so if we find pmd none, return.
+         */
+        if (pmd_none(*pmd))
+                return;
         BUG_ON(!pmd_present(*pmd));
         assert_spin_locked(pte_lockptr(mm, pmd));
 }
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index a854096e1023..536eec72c0f7 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -338,6 +338,19 @@ EXPORT_SYMBOL(iounmap);
 EXPORT_SYMBOL(__iounmap);
 EXPORT_SYMBOL(__iounmap_at);
 
+/*
+ * For hugepage we have pfn in the pmd, we use PTE_RPN_SHIFT bits for flags
+ * For PTE page, we have a PTE_FRAG_SIZE (4K) aligned virtual address.
+ */
+struct page *pmd_page(pmd_t pmd)
+{
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+        if (pmd_trans_huge(pmd))
+                return pfn_to_page(pmd_pfn(pmd));
+#endif
+        return virt_to_page(pmd_page_vaddr(pmd));
+}
+
 #ifdef CONFIG_PPC_64K_PAGES
 static pte_t *get_from_cache(struct mm_struct *mm)
 {
@@ -455,3 +468,404 @@ void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
 }
 #endif
 #endif /* CONFIG_PPC_64K_PAGES */
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+
+/*
+ * This is called when relaxing access to a hugepage. It's also called in the page
+ * fault path when we don't hit any of the major fault cases, ie, a minor
+ * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
+ * handled those two for us, we additionally deal with missing execute
+ * permission here on some processors
+ */
+int pmdp_set_access_flags(struct vm_area_struct *vma, unsigned long address,
+                          pmd_t *pmdp, pmd_t entry, int dirty)
+{
+        int changed;
+#ifdef CONFIG_DEBUG_VM
+        WARN_ON(!pmd_trans_huge(*pmdp));
+        assert_spin_locked(&vma->vm_mm->page_table_lock);
+#endif
+        changed = !pmd_same(*(pmdp), entry);
+        if (changed) {
+                __ptep_set_access_flags(pmdp_ptep(pmdp), pmd_pte(entry));
+                /*
+                 * Since we are not supporting SW TLB systems, we don't
+                 * have any thing similar to flush_tlb_page_nohash()
+                 */
+        }
+        return changed;
+}
+
+unsigned long pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
+                                  pmd_t *pmdp, unsigned long clr)
+{
+
+        unsigned long old, tmp;
+
+#ifdef CONFIG_DEBUG_VM
+        WARN_ON(!pmd_trans_huge(*pmdp));
+        assert_spin_locked(&mm->page_table_lock);
+#endif
+
+#ifdef PTE_ATOMIC_UPDATES
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%3\n\
+                andi.   %1,%0,%6\n\
+                bne-    1b \n\
+                andc    %1,%0,%4 \n\
+                stdcx.  %1,0,%3 \n\
+                bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*pmdp)
+        : "r" (pmdp), "r" (clr), "m" (*pmdp), "i" (_PAGE_BUSY)
+        : "cc" );
+#else
+        old = pmd_val(*pmdp);
+        *pmdp = __pmd(old & ~clr);
+#endif
+        if (old & _PAGE_HASHPTE)
+                hpte_do_hugepage_flush(mm, addr, pmdp);
+        return old;
+}
+
+pmd_t pmdp_clear_flush(struct vm_area_struct *vma, unsigned long address,
+                       pmd_t *pmdp)
+{
+        pmd_t pmd;
+
+        VM_BUG_ON(address & ~HPAGE_PMD_MASK);
+        if (pmd_trans_huge(*pmdp)) {
+                pmd = pmdp_get_and_clear(vma->vm_mm, address, pmdp);
+        } else {
+                /*
+                 * khugepaged calls this for normal pmd
+                 */
+                pmd = *pmdp;
+                pmd_clear(pmdp);
+                /*
+                 * Wait for all pending hash_page to finish. This is needed
+                 * in case of subpage collapse. When we collapse normal pages
+                 * to hugepage, we first clear the pmd, then invalidate all
+                 * the PTE entries. The assumption here is that any low level
+                 * page fault will see a none pmd and take the slow path that
+                 * will wait on mmap_sem. But we could very well be in a
+                 * hash_page with local ptep pointer value. Such a hash page
+                 * can result in adding new HPTE entries for normal subpages.
+                 * That means we could be modifying the page content as we
+                 * copy them to a huge page. So wait for parallel hash_page
+                 * to finish before invalidating HPTE entries. We can do this
+                 * by sending an IPI to all the cpus and executing a dummy
+                 * function there.
+                 */
+                kick_all_cpus_sync();
+                /*
+                 * Now invalidate the hpte entries in the range
+                 * covered by pmd. This make sure we take a
+                 * fault and will find the pmd as none, which will
+                 * result in a major fault which takes mmap_sem and
+                 * hence wait for collapse to complete. Without this
+                 * the __collapse_huge_page_copy can result in copying
+                 * the old content.
+                 */
+                flush_tlb_pmd_range(vma->vm_mm, &pmd, address);
+        }
+        return pmd;
+}
+
+int pmdp_test_and_clear_young(struct vm_area_struct *vma,
+                              unsigned long address, pmd_t *pmdp)
+{
+        return __pmdp_test_and_clear_young(vma->vm_mm, address, pmdp);
+}
+
+/*
+ * We currently remove entries from the hashtable regardless of whether
+ * the entry was young or dirty. The generic routines only flush if the
+ * entry was young or dirty which is not good enough.
+ *
+ * We should be more intelligent about this but for the moment we override
+ * these functions and force a tlb flush unconditionally
+ */
+int pmdp_clear_flush_young(struct vm_area_struct *vma,
+                                  unsigned long address, pmd_t *pmdp)
+{
+        return __pmdp_test_and_clear_young(vma->vm_mm, address, pmdp);
+}
+
+/*
+ * We mark the pmd splitting and invalidate all the hpte
+ * entries for this hugepage.
+ */
+void pmdp_splitting_flush(struct vm_area_struct *vma,
+                          unsigned long address, pmd_t *pmdp)
+{
+        unsigned long old, tmp;
+
+        VM_BUG_ON(address & ~HPAGE_PMD_MASK);
+
+#ifdef CONFIG_DEBUG_VM
+        WARN_ON(!pmd_trans_huge(*pmdp));
+        assert_spin_locked(&vma->vm_mm->page_table_lock);
+#endif
+
+#ifdef PTE_ATOMIC_UPDATES
+
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%3\n\
+                andi.   %1,%0,%6\n\
+                bne-    1b \n\
+                ori     %1,%0,%4 \n\
+                stdcx.  %1,0,%3 \n\
+                bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*pmdp)
+        : "r" (pmdp), "i" (_PAGE_SPLITTING), "m" (*pmdp), "i" (_PAGE_BUSY)
+        : "cc" );
+#else
+        old = pmd_val(*pmdp);
+        *pmdp = __pmd(old | _PAGE_SPLITTING);
+#endif
+        /*
+         * If we didn't had the splitting flag set, go and flush the
+         * HPTE entries.
+         */
+        if (!(old & _PAGE_SPLITTING)) {
+                /* We need to flush the hpte */
+                if (old & _PAGE_HASHPTE)
+                        hpte_do_hugepage_flush(vma->vm_mm, address, pmdp);
+        }
+}
+
+/*
+ * We want to put the pgtable in pmd and use pgtable for tracking
+ * the base page size hptes
+ */
+void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                pgtable_t pgtable)
+{
+        pgtable_t *pgtable_slot;
+        assert_spin_locked(&mm->page_table_lock);
+        /*
+         * we store the pgtable in the second half of PMD
+         */
+        pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
+        *pgtable_slot = pgtable;
+        /*
+         * expose the deposited pgtable to other cpus.
+         * before we set the hugepage PTE at pmd level
+         * hash fault code looks at the deposted pgtable
+         * to store hash index values.
+         */
+        smp_wmb();
+}
+
+pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
+{
+        pgtable_t pgtable;
+        pgtable_t *pgtable_slot;
+
+        assert_spin_locked(&mm->page_table_lock);
+        pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
+        pgtable = *pgtable_slot;
+        /*
+         * Once we withdraw, mark the entry NULL.
+         */
+        *pgtable_slot = NULL;
+        /*
+         * We store HPTE information in the deposited PTE fragment.
+         * zero out the content on withdraw.
+         */
+        memset(pgtable, 0, PTE_FRAG_SIZE);
+        return pgtable;
+}
+
+/*
+ * set a new huge pmd. We should not be called for updating
+ * an existing pmd entry. That should go via pmd_hugepage_update.
+ */
+void set_pmd_at(struct mm_struct *mm, unsigned long addr,
+                pmd_t *pmdp, pmd_t pmd)
+{
+#ifdef CONFIG_DEBUG_VM
+        WARN_ON(!pmd_none(*pmdp));
+        assert_spin_locked(&mm->page_table_lock);
+        WARN_ON(!pmd_trans_huge(pmd));
+#endif
+        return set_pte_at(mm, addr, pmdp_ptep(pmdp), pmd_pte(pmd));
+}
+
+void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address,
+                     pmd_t *pmdp)
+{
+        pmd_hugepage_update(vma->vm_mm, address, pmdp, _PAGE_PRESENT);
+}
+
+/*
+ * A linux hugepage PMD was changed and the corresponding hash table entries
+ * neesd to be flushed.
+ */
+void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
+                            pmd_t *pmdp)
+{
+        int ssize, i;
+        unsigned long s_addr;
+        int max_hpte_count;
+        unsigned int psize, valid;
+        unsigned char *hpte_slot_array;
+        unsigned long hidx, vpn, vsid, hash, shift, slot;
+
+        /*
+         * Flush all the hptes mapping this hugepage
+         */
+        s_addr = addr & HPAGE_PMD_MASK;
+        hpte_slot_array = get_hpte_slot_array(pmdp);
+        /*
+         * IF we try to do a HUGE PTE update after a withdraw is done.
+         * we will find the below NULL. This happens when we do
+         * split_huge_page_pmd
+         */
+        if (!hpte_slot_array)
+                return;
+
+        /* get the base page size */
+        psize = get_slice_psize(mm, s_addr);
+
+        if (ppc_md.hugepage_invalidate)
+                return ppc_md.hugepage_invalidate(mm, hpte_slot_array,
+                                                  s_addr, psize);
+        /*
+         * No bluk hpte removal support, invalidate each entry
+         */
+        shift = mmu_psize_defs[psize].shift;
+        max_hpte_count = HPAGE_PMD_SIZE >> shift;
+        for (i = 0; i < max_hpte_count; i++) {
+                /*
+                 * 8 bits per each hpte entries
+                 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
+                 */
+                valid = hpte_valid(hpte_slot_array, i);
+                if (!valid)
+                        continue;
+                hidx =  hpte_hash_index(hpte_slot_array, i);
+
+                /* get the vpn */
+                addr = s_addr + (i * (1ul << shift));
+                if (!is_kernel_addr(addr)) {
+                        ssize = user_segment_size(addr);
+                        vsid = get_vsid(mm->context.id, addr, ssize);
+                        WARN_ON(vsid == 0);
+                } else {
+                        vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
+                        ssize = mmu_kernel_ssize;
+                }
+
+                vpn = hpt_vpn(addr, vsid, ssize);
+                hash = hpt_hash(vpn, shift, ssize);
+                if (hidx & _PTEIDX_SECONDARY)
+                        hash = ~hash;
+
+                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+                slot += hidx & _PTEIDX_GROUP_IX;
+                ppc_md.hpte_invalidate(slot, vpn, psize,
+                                       MMU_PAGE_16M, ssize, 0);
+        }
+}
+
+static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot)
+{
+        pmd_val(pmd) |= pgprot_val(pgprot);
+        return pmd;
+}
+
+pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
+{
+        pmd_t pmd;
+        /*
+         * For a valid pte, we would have _PAGE_PRESENT or _PAGE_FILE always
+         * set. We use this to check THP page at pmd level.
+         * leaf pte for huge page, bottom two bits != 00
+         */
+        pmd_val(pmd) = pfn << PTE_RPN_SHIFT;
+        pmd_val(pmd) |= _PAGE_THP_HUGE;
+        pmd = pmd_set_protbits(pmd, pgprot);
+        return pmd;
+}
+
+pmd_t mk_pmd(struct page *page, pgprot_t pgprot)
+{
+        return pfn_pmd(page_to_pfn(page), pgprot);
+}
+
+pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
+{
+
+        pmd_val(pmd) &= _HPAGE_CHG_MASK;
+        pmd = pmd_set_protbits(pmd, newprot);
+        return pmd;
+}
+
+/*
+ * This is called at the end of handling a user page fault, when the
+ * fault has been handled by updating a HUGE PMD entry in the linux page tables.
+ * We use it to preload an HPTE into the hash table corresponding to
+ * the updated linux HUGE PMD entry.
+ */
+void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
+                          pmd_t *pmd)
+{
+        return;
+}
+
+pmd_t pmdp_get_and_clear(struct mm_struct *mm,
+                         unsigned long addr, pmd_t *pmdp)
+{
+        pmd_t old_pmd;
+        pgtable_t pgtable;
+        unsigned long old;
+        pgtable_t *pgtable_slot;
+
+        old = pmd_hugepage_update(mm, addr, pmdp, ~0UL);
+        old_pmd = __pmd(old);
+        /*
+         * We have pmd == none and we are holding page_table_lock.
+         * So we can safely go and clear the pgtable hash
+         * index info.
+         */
+        pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
+        pgtable = *pgtable_slot;
+        /*
+         * Let's zero out old valid and hash index details
+         * hash fault look at them.
+         */
+        memset(pgtable, 0, PTE_FRAG_SIZE);
+        return old_pmd;
+}
+
+int has_transparent_hugepage(void)
+{
+        if (!mmu_has_feature(MMU_FTR_16M_PAGE))
+                return 0;
+        /*
+         * We support THP only if PMD_SIZE is 16MB.
+         */
+        if (mmu_psize_defs[MMU_PAGE_16M].shift != PMD_SHIFT)
+                return 0;
+        /*
+         * We need to make sure that we support 16MB hugepage in a segement
+         * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE
+         * of 64K.
+         */
+        /*
+         * If we have 64K HPTE, we will be using that by default
+         */
+        if (mmu_psize_defs[MMU_PAGE_64K].shift &&
+            (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1))
+                return 0;
+        /*
+         * Ok we only have 4K HPTE
+         */
+        if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1)
+                return 0;
+
+        return 1;
+}
+#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
diff --git a/arch/powerpc/mm/subpage-prot.c b/arch/powerpc/mm/subpage-prot.c
index 7c415ddde948..aa74acb0fdfc 100644
--- a/arch/powerpc/mm/subpage-prot.c
+++ b/arch/powerpc/mm/subpage-prot.c
@@ -130,6 +130,53 @@ static void subpage_prot_clear(unsigned long addr, unsigned long len)
         up_write(&mm->mmap_sem);
 }
 
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+static int subpage_walk_pmd_entry(pmd_t *pmd, unsigned long addr,
+                                  unsigned long end, struct mm_walk *walk)
+{
+        struct vm_area_struct *vma = walk->private;
+        split_huge_page_pmd(vma, addr, pmd);
+        return 0;
+}
+
+static void subpage_mark_vma_nohuge(struct mm_struct *mm, unsigned long addr,
+                                    unsigned long len)
+{
+        struct vm_area_struct *vma;
+        struct mm_walk subpage_proto_walk = {
+                .mm = mm,
+                .pmd_entry = subpage_walk_pmd_entry,
+        };
+
+        /*
+         * We don't try too hard, we just mark all the vma in that range
+         * VM_NOHUGEPAGE and split them.
+         */
+        vma = find_vma(mm, addr);
+        /*
+         * If the range is in unmapped range, just return
+         */
+        if (vma && ((addr + len) <= vma->vm_start))
+                return;
+
+        while (vma) {
+                if (vma->vm_start >= (addr + len))
+                        break;
+                vma->vm_flags |= VM_NOHUGEPAGE;
+                subpage_proto_walk.private = vma;
+                walk_page_range(vma->vm_start, vma->vm_end,
+                                &subpage_proto_walk);
+                vma = vma->vm_next;
+        }
+}
+#else
+static void subpage_mark_vma_nohuge(struct mm_struct *mm, unsigned long addr,
+                                    unsigned long len)
+{
+        return;
+}
+#endif
+
 /*
  * Copy in a subpage protection map for an address range.
  * The map has 2 bits per 4k subpage, so 32 bits per 64k page.
@@ -168,6 +215,7 @@ long sys_subpage_prot(unsigned long addr, unsigned long len, u32 __user *map)
                 return -EFAULT;
 
         down_write(&mm->mmap_sem);
+        subpage_mark_vma_nohuge(mm, addr, len);
         for (limit = addr + len; addr < limit; addr = next) {
                 next = pmd_addr_end(addr, limit);
                 err = -ENOMEM;
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index 023ec8a13f38..36e44b4260eb 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -183,12 +183,13 @@ void tlb_flush(struct mmu_gather *tlb)
  * since 64K pages may overlap with other bridges when using 64K pages
  * with 4K HW pages on IO space.
  *
- * Because of that usage pattern, it's only available with CONFIG_HOTPLUG
- * and is implemented for small size rather than speed.
+ * Because of that usage pattern, it is implemented for small size rather
+ * than speed.
  */
 void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
                               unsigned long end)
 {
+        int hugepage_shift;
         unsigned long flags;
 
         start = _ALIGN_DOWN(start, PAGE_SIZE);
@@ -206,7 +207,8 @@ void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
         local_irq_save(flags);
         arch_enter_lazy_mmu_mode();
         for (; start < end; start += PAGE_SIZE) {
-                pte_t *ptep = find_linux_pte(mm->pgd, start);
+                pte_t *ptep = find_linux_pte_or_hugepte(mm->pgd, start,
+                                                        &hugepage_shift);
                 unsigned long pte;
 
                 if (ptep == NULL)
@@ -214,7 +216,37 @@ void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
                 pte = pte_val(*ptep);
                 if (!(pte & _PAGE_HASHPTE))
                         continue;
-                hpte_need_flush(mm, start, ptep, pte, 0);
+                if (unlikely(hugepage_shift && pmd_trans_huge(*(pmd_t *)pte)))
+                        hpte_do_hugepage_flush(mm, start, (pmd_t *)pte);
+                else
+                        hpte_need_flush(mm, start, ptep, pte, 0);
+        }
+        arch_leave_lazy_mmu_mode();
+        local_irq_restore(flags);
+}
+
+void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd, unsigned long addr)
+{
+        pte_t *pte;
+        pte_t *start_pte;
+        unsigned long flags;
+
+        addr = _ALIGN_DOWN(addr, PMD_SIZE);
+        /* Note: Normally, we should only ever use a batch within a
+         * PTE locked section. This violates the rule, but will work
+         * since we don't actually modify the PTEs, we just flush the
+         * hash while leaving the PTEs intact (including their reference
+         * to being hashed). This is not the most performance oriented
+         * way to do things but is fine for our needs here.
+         */
+        local_irq_save(flags);
+        arch_enter_lazy_mmu_mode();
+        start_pte = pte_offset_map(pmd, addr);
+        for (pte = start_pte; pte < start_pte + PTRS_PER_PTE; pte++) {
+                unsigned long pteval = pte_val(*pte);
+                if (pteval & _PAGE_HASHPTE)
+                        hpte_need_flush(mm, addr, pte, pteval, 0);
+                addr += PAGE_SIZE;
         }
         arch_leave_lazy_mmu_mode();
         local_irq_restore(flags);
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 6888cad5103d..41cd68dee681 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -648,7 +648,7 @@ void __init early_init_mmu(void)
         __early_init_mmu(1);
 }
 
-void __cpuinit early_init_mmu_secondary(void)
+void early_init_mmu_secondary(void)
 {
         __early_init_mmu(0);
 }
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 845c867444e6..a3985aee77fe 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,11 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
 
 #define MMCR0_FCHV              0
 #define MMCR0_PMCjCE            MMCR0_PMCnCE
+#define MMCR0_FC56              0
+#define MMCR0_PMAO              0
+#define MMCR0_EBE               0
+#define MMCR0_PMCC              0
+#define MMCR0_PMCC_U6           0
 
 #define SPRN_MMCRA              SPRN_MMCR2
 #define MMCRA_SAMPLE_ENABLE     0
@@ -102,6 +107,15 @@ static inline int siar_valid(struct pt_regs *regs)
         return 1;
 }
 
+static bool is_ebb_event(struct perf_event *event) { return false; }
+static int ebb_event_check(struct perf_event *event) { return 0; }
+static void ebb_event_add(struct perf_event *event) { }
+static void ebb_switch_out(unsigned long mmcr0) { }
+static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
+{
+        return mmcr0;
+}
+
 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
 void power_pmu_flush_branch_stack(void) {}
@@ -462,6 +476,89 @@ void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
         return;
 }
 
+static bool is_ebb_event(struct perf_event *event)
+{
+        /*
+         * This could be a per-PMU callback, but we'd rather avoid the cost. We
+         * check that the PMU supports EBB, meaning those that don't can still
+         * use bit 63 of the event code for something else if they wish.
+         */
+        return (ppmu->flags & PPMU_EBB) &&
+               ((event->attr.config >> EVENT_CONFIG_EBB_SHIFT) & 1);
+}
+
+static int ebb_event_check(struct perf_event *event)
+{
+        struct perf_event *leader = event->group_leader;
+
+        /* Event and group leader must agree on EBB */
+        if (is_ebb_event(leader) != is_ebb_event(event))
+                return -EINVAL;
+
+        if (is_ebb_event(event)) {
+                if (!(event->attach_state & PERF_ATTACH_TASK))
+                        return -EINVAL;
+
+                if (!leader->attr.pinned || !leader->attr.exclusive)
+                        return -EINVAL;
+
+                if (event->attr.inherit || event->attr.sample_period ||
+                    event->attr.enable_on_exec || event->attr.freq)
+                        return -EINVAL;
+        }
+
+        return 0;
+}
+
+static void ebb_event_add(struct perf_event *event)
+{
+        if (!is_ebb_event(event) || current->thread.used_ebb)
+                return;
+
+        /*
+         * IFF this is the first time we've added an EBB event, set
+         * PMXE in the user MMCR0 so we can detect when it's cleared by
+         * userspace. We need this so that we can context switch while
+         * userspace is in the EBB handler (where PMXE is 0).
+         */
+        current->thread.used_ebb = 1;
+        current->thread.mmcr0 |= MMCR0_PMXE;
+}
+
+static void ebb_switch_out(unsigned long mmcr0)
+{
+        if (!(mmcr0 & MMCR0_EBE))
+                return;
+
+        current->thread.siar  = mfspr(SPRN_SIAR);
+        current->thread.sier  = mfspr(SPRN_SIER);
+        current->thread.sdar  = mfspr(SPRN_SDAR);
+        current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
+        current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
+}
+
+static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0)
+{
+        if (!ebb)
+                goto out;
+
+        /* Enable EBB and read/write to all 6 PMCs for userspace */
+        mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6;
+
+        /* Add any bits from the user reg, FC or PMAO */
+        mmcr0 |= current->thread.mmcr0;
+
+        /* Be careful not to set PMXE if userspace had it cleared */
+        if (!(current->thread.mmcr0 & MMCR0_PMXE))
+                mmcr0 &= ~MMCR0_PMXE;
+
+        mtspr(SPRN_SIAR, current->thread.siar);
+        mtspr(SPRN_SIER, current->thread.sier);
+        mtspr(SPRN_SDAR, current->thread.sdar);
+        mtspr(SPRN_MMCR2, current->thread.mmcr2);
+out:
+        return mmcr0;
+}
 #endif /* CONFIG_PPC64 */
 
 static void perf_event_interrupt(struct pt_regs *regs);
@@ -732,6 +829,13 @@ static void power_pmu_read(struct perf_event *event)
 
         if (!event->hw.idx)
                 return;
+
+        if (is_ebb_event(event)) {
+                val = read_pmc(event->hw.idx);
+                local64_set(&event->hw.prev_count, val);
+                return;
+        }
+
         /*
          * Performance monitor interrupts come even when interrupts
          * are soft-disabled, as long as interrupts are hard-enabled.
@@ -852,7 +956,7 @@ static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
 static void power_pmu_disable(struct pmu *pmu)
 {
         struct cpu_hw_events *cpuhw;
-        unsigned long flags;
+        unsigned long flags, mmcr0, val;
 
         if (!ppmu)
                 return;
@@ -860,9 +964,6 @@ static void power_pmu_disable(struct pmu *pmu)
         cpuhw = &__get_cpu_var(cpu_hw_events);
 
         if (!cpuhw->disabled) {
-                cpuhw->disabled = 1;
-                cpuhw->n_added = 0;
-
                 /*
                  * Check if we ever enabled the PMU on this cpu.
                  */
@@ -872,6 +973,21 @@ static void power_pmu_disable(struct pmu *pmu)
                 }
 
                 /*
+                 * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56.
+                 */
+                val  = mmcr0 = mfspr(SPRN_MMCR0);
+                val |= MMCR0_FC;
+                val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56);
+
+                /*
+                 * The barrier is to make sure the mtspr has been
+                 * executed and the PMU has frozen the events etc.
+                 * before we return.
+                 */
+                write_mmcr0(cpuhw, val);
+                mb();
+
+                /*
                  * Disable instruction sampling if it was enabled
                  */
                 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
@@ -880,15 +996,12 @@ static void power_pmu_disable(struct pmu *pmu)
                         mb();
                 }
 
-                /*
-                 * Set the 'freeze counters' bit.
-                 * The barrier is to make sure the mtspr has been
-                 * executed and the PMU has frozen the events
-                 * before we return.
-                 */
-                write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
-                mb();
+                cpuhw->disabled = 1;
+                cpuhw->n_added = 0;
+
+                ebb_switch_out(mmcr0);
         }
+
         local_irq_restore(flags);
 }
 
@@ -903,23 +1016,36 @@ static void power_pmu_enable(struct pmu *pmu)
         struct cpu_hw_events *cpuhw;
         unsigned long flags;
         long i;
-        unsigned long val;
+        unsigned long val, mmcr0;
         s64 left;
         unsigned int hwc_index[MAX_HWEVENTS];
         int n_lim;
         int idx;
+        bool ebb;
 
         if (!ppmu)
                 return;
         local_irq_save(flags);
+
         cpuhw = &__get_cpu_var(cpu_hw_events);
-        if (!cpuhw->disabled) {
-                local_irq_restore(flags);
-                return;
+        if (!cpuhw->disabled)
+                goto out;
+
+        if (cpuhw->n_events == 0) {
+                ppc_set_pmu_inuse(0);
+                goto out;
         }
+
         cpuhw->disabled = 0;
 
         /*
+         * EBB requires an exclusive group and all events must have the EBB
+         * flag set, or not set, so we can just check a single event. Also we
+         * know we have at least one event.
+         */
+        ebb = is_ebb_event(cpuhw->event[0]);
+
+        /*
          * If we didn't change anything, or only removed events,
          * no need to recalculate MMCR* settings and reset the PMCs.
          * Just reenable the PMU with the current MMCR* settings
@@ -928,8 +1054,6 @@ static void power_pmu_enable(struct pmu *pmu)
         if (!cpuhw->n_added) {
                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
                 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
-                if (cpuhw->n_events == 0)
-                        ppc_set_pmu_inuse(0);
                 goto out_enable;
         }
 
@@ -996,25 +1120,34 @@ static void power_pmu_enable(struct pmu *pmu)
                         ++n_lim;
                         continue;
                 }
-                val = 0;
-                if (event->hw.sample_period) {
-                        left = local64_read(&event->hw.period_left);
-                        if (left < 0x80000000L)
-                                val = 0x80000000L - left;
+
+                if (ebb)
+                        val = local64_read(&event->hw.prev_count);
+                else {
+                        val = 0;
+                        if (event->hw.sample_period) {
+                                left = local64_read(&event->hw.period_left);
+                                if (left < 0x80000000L)
+                                        val = 0x80000000L - left;
+                        }
+                        local64_set(&event->hw.prev_count, val);
                 }
-                local64_set(&event->hw.prev_count, val);
+
                 event->hw.idx = idx;
                 if (event->hw.state & PERF_HES_STOPPED)
                         val = 0;
                 write_pmc(idx, val);
+
                 perf_event_update_userpage(event);
         }
         cpuhw->n_limited = n_lim;
         cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
 
  out_enable:
+        mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]);
+
         mb();
-        write_mmcr0(cpuhw, cpuhw->mmcr[0]);
+        write_mmcr0(cpuhw, mmcr0);
 
         /*
          * Enable instruction sampling if necessary
@@ -1112,6 +1245,8 @@ static int power_pmu_add(struct perf_event *event, int ef_flags)
         event->hw.config = cpuhw->events[n0];
 
 nocheck:
+        ebb_event_add(event);
+
         ++cpuhw->n_events;
         ++cpuhw->n_added;
 
@@ -1472,6 +1607,11 @@ static int power_pmu_event_init(struct perf_event *event)
                 }
         }
 
+        /* Extra checks for EBB */
+        err = ebb_event_check(event);
+        if (err)
+                return err;
+
         /*
          * If this is in a group, check if it can go on with all the
          * other hardware events in the group.  We assume the event
@@ -1511,6 +1651,13 @@ static int power_pmu_event_init(struct perf_event *event)
         local64_set(&event->hw.period_left, event->hw.last_period);
 
         /*
+         * For EBB events we just context switch the PMC value, we don't do any
+         * of the sample_period logic. We use hw.prev_count for this.
+         */
+        if (is_ebb_event(event))
+                local64_set(&event->hw.prev_count, 0);
+
+        /*
          * See if we need to reserve the PMU.
          * If no events are currently in use, then we have to take a
          * mutex to ensure that we don't race with another task doing
@@ -1758,7 +1905,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                         }
                 }
         }
-        if ((!found) && printk_ratelimit())
+        if (!found && !nmi && printk_ratelimit())
                 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
 
         /*
@@ -1786,7 +1933,7 @@ static void power_pmu_setup(int cpu)
         cpuhw->mmcr[0] = MMCR0_FC;
 }
 
-static int __cpuinit
+static int
 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
 {
         unsigned int cpu = (long)hcpu;
@@ -1803,7 +1950,7 @@ power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu
         return NOTIFY_OK;
 }
 
-int __cpuinit register_power_pmu(struct power_pmu *pmu)
+int register_power_pmu(struct power_pmu *pmu)
 {
         if (ppmu)
                 return -EBUSY;          /* something's already registered */
diff --git a/arch/powerpc/perf/power7-pmu.c b/arch/powerpc/perf/power7-pmu.c
index 3c475d6267c7..13c3f0e547a2 100644
--- a/arch/powerpc/perf/power7-pmu.c
+++ b/arch/powerpc/perf/power7-pmu.c
@@ -62,6 +62,29 @@
 #define PME_PM_BRU_FIN                  0x10068
 #define PME_PM_BRU_MPRED                0x400f6
 
+#define PME_PM_CMPLU_STALL_FXU                  0x20014
+#define PME_PM_CMPLU_STALL_DIV                  0x40014
+#define PME_PM_CMPLU_STALL_SCALAR               0x40012
+#define PME_PM_CMPLU_STALL_SCALAR_LONG          0x20018
+#define PME_PM_CMPLU_STALL_VECTOR               0x2001c
+#define PME_PM_CMPLU_STALL_VECTOR_LONG          0x4004a
+#define PME_PM_CMPLU_STALL_LSU                  0x20012
+#define PME_PM_CMPLU_STALL_REJECT               0x40016
+#define PME_PM_CMPLU_STALL_ERAT_MISS            0x40018
+#define PME_PM_CMPLU_STALL_DCACHE_MISS          0x20016
+#define PME_PM_CMPLU_STALL_STORE                0x2004a
+#define PME_PM_CMPLU_STALL_THRD                 0x1001c
+#define PME_PM_CMPLU_STALL_IFU                  0x4004c
+#define PME_PM_CMPLU_STALL_BRU                  0x4004e
+#define PME_PM_GCT_NOSLOT_IC_MISS               0x2001a
+#define PME_PM_GCT_NOSLOT_BR_MPRED              0x4001a
+#define PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS      0x4001c
+#define PME_PM_GRP_CMPL                         0x30004
+#define PME_PM_1PLUS_PPC_CMPL                   0x100f2
+#define PME_PM_CMPLU_STALL_DFU                  0x2003c
+#define PME_PM_RUN_CYC                          0x200f4
+#define PME_PM_RUN_INST_CMPL                    0x400fa
+
 /*
  * Layout of constraint bits:
  * 6666555555555544444444443333333333222222222211111111110000000000
@@ -393,6 +416,31 @@ POWER_EVENT_ATTR(LD_MISS_L1,			LD_MISS_L1);
 POWER_EVENT_ATTR(BRU_FIN,                       BRU_FIN)
 POWER_EVENT_ATTR(BRU_MPRED,                     BRU_MPRED);
 
+POWER_EVENT_ATTR(CMPLU_STALL_FXU,               CMPLU_STALL_FXU);
+POWER_EVENT_ATTR(CMPLU_STALL_DIV,               CMPLU_STALL_DIV);
+POWER_EVENT_ATTR(CMPLU_STALL_SCALAR,            CMPLU_STALL_SCALAR);
+POWER_EVENT_ATTR(CMPLU_STALL_SCALAR_LONG,       CMPLU_STALL_SCALAR_LONG);
+POWER_EVENT_ATTR(CMPLU_STALL_VECTOR,            CMPLU_STALL_VECTOR);
+POWER_EVENT_ATTR(CMPLU_STALL_VECTOR_LONG,       CMPLU_STALL_VECTOR_LONG);
+POWER_EVENT_ATTR(CMPLU_STALL_LSU,               CMPLU_STALL_LSU);
+POWER_EVENT_ATTR(CMPLU_STALL_REJECT,            CMPLU_STALL_REJECT);
+
+POWER_EVENT_ATTR(CMPLU_STALL_ERAT_MISS,         CMPLU_STALL_ERAT_MISS);
+POWER_EVENT_ATTR(CMPLU_STALL_DCACHE_MISS,       CMPLU_STALL_DCACHE_MISS);
+POWER_EVENT_ATTR(CMPLU_STALL_STORE,             CMPLU_STALL_STORE);
+POWER_EVENT_ATTR(CMPLU_STALL_THRD,              CMPLU_STALL_THRD);
+POWER_EVENT_ATTR(CMPLU_STALL_IFU,               CMPLU_STALL_IFU);
+POWER_EVENT_ATTR(CMPLU_STALL_BRU,               CMPLU_STALL_BRU);
+POWER_EVENT_ATTR(GCT_NOSLOT_IC_MISS,            GCT_NOSLOT_IC_MISS);
+
+POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED,           GCT_NOSLOT_BR_MPRED);
+POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED_IC_MISS,   GCT_NOSLOT_BR_MPRED_IC_MISS);
+POWER_EVENT_ATTR(GRP_CMPL,                      GRP_CMPL);
+POWER_EVENT_ATTR(1PLUS_PPC_CMPL,                1PLUS_PPC_CMPL);
+POWER_EVENT_ATTR(CMPLU_STALL_DFU,               CMPLU_STALL_DFU);
+POWER_EVENT_ATTR(RUN_CYC,                       RUN_CYC);
+POWER_EVENT_ATTR(RUN_INST_CMPL,                 RUN_INST_CMPL);
+
 static struct attribute *power7_events_attr[] = {
         GENERIC_EVENT_PTR(CYC),
         GENERIC_EVENT_PTR(GCT_NOSLOT_CYC),
@@ -411,6 +459,31 @@ static struct attribute *power7_events_attr[] = {
         POWER_EVENT_PTR(LD_MISS_L1),
         POWER_EVENT_PTR(BRU_FIN),
         POWER_EVENT_PTR(BRU_MPRED),
+
+        POWER_EVENT_PTR(CMPLU_STALL_FXU),
+        POWER_EVENT_PTR(CMPLU_STALL_DIV),
+        POWER_EVENT_PTR(CMPLU_STALL_SCALAR),
+        POWER_EVENT_PTR(CMPLU_STALL_SCALAR_LONG),
+        POWER_EVENT_PTR(CMPLU_STALL_VECTOR),
+        POWER_EVENT_PTR(CMPLU_STALL_VECTOR_LONG),
+        POWER_EVENT_PTR(CMPLU_STALL_LSU),
+        POWER_EVENT_PTR(CMPLU_STALL_REJECT),
+
+        POWER_EVENT_PTR(CMPLU_STALL_ERAT_MISS),
+        POWER_EVENT_PTR(CMPLU_STALL_DCACHE_MISS),
+        POWER_EVENT_PTR(CMPLU_STALL_STORE),
+        POWER_EVENT_PTR(CMPLU_STALL_THRD),
+        POWER_EVENT_PTR(CMPLU_STALL_IFU),
+        POWER_EVENT_PTR(CMPLU_STALL_BRU),
+        POWER_EVENT_PTR(GCT_NOSLOT_IC_MISS),
+        POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED),
+
+        POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED_IC_MISS),
+        POWER_EVENT_PTR(GRP_CMPL),
+        POWER_EVENT_PTR(1PLUS_PPC_CMPL),
+        POWER_EVENT_PTR(CMPLU_STALL_DFU),
+        POWER_EVENT_PTR(RUN_CYC),
+        POWER_EVENT_PTR(RUN_INST_CMPL),
         NULL
 };
 
diff --git a/arch/powerpc/perf/power8-pmu.c b/arch/powerpc/perf/power8-pmu.c
index f7d1c4fff303..96a64d6a8bdf 100644
--- a/arch/powerpc/perf/power8-pmu.c
+++ b/arch/powerpc/perf/power8-pmu.c
@@ -31,9 +31,9 @@
  *
  *        60        56        52        48        44        40        36        32
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *                                     [      thresh_cmp     ]   [  thresh_ctl   ]
- *                                                                       |
- *                                       thresh start/stop OR FAB match -*
+ *   |                                 [      thresh_cmp     ]   [  thresh_ctl   ]
+ *   |                                                                   |
+ *   *- EBB (Linux)                      thresh start/stop OR FAB match -*
  *
  *        28        24        20        16        12         8         4         0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
@@ -85,6 +85,7 @@
  *
  */
 
+#define EVENT_EBB_MASK          1ull
 #define EVENT_THR_CMP_SHIFT     40      /* Threshold CMP value */
 #define EVENT_THR_CMP_MASK      0x3ff
 #define EVENT_THR_CTL_SHIFT     32      /* Threshold control value (start/stop) */
@@ -109,6 +110,17 @@
 #define EVENT_IS_MARKED         (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
 #define EVENT_PSEL_MASK         0xff    /* PMCxSEL value */
 
+#define EVENT_VALID_MASK        \
+        ((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)           |       \
+         (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)           |       \
+         (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)        |       \
+         (EVENT_PMC_MASK       << EVENT_PMC_SHIFT)              |       \
+         (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)             |       \
+         (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)          |       \
+         (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)           |       \
+         (EVENT_EBB_MASK       << EVENT_CONFIG_EBB_SHIFT)       |       \
+          EVENT_PSEL_MASK)
+
 /* MMCRA IFM bits - POWER8 */
 #define POWER8_MMCRA_IFM1               0x0000000040000000UL
 #define POWER8_MMCRA_IFM2               0x0000000080000000UL
@@ -130,10 +142,10 @@
  *
  *        28        24        20        16        12         8         4         0
  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
- *                       [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
- *                        |                     |
- *      L1 I/D qualifier -*                     |      Count of events for each PMC.
- *                                              |        p1, p2, p3, p4, p5, p6.
+ *                   |   [ ]   [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
+ *              EBB -*    |                     |
+ *                        |                     |      Count of events for each PMC.
+ *      L1 I/D qualifier -*                     |        p1, p2, p3, p4, p5, p6.
  *                     nc - number of counters -*
  *
  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
@@ -149,6 +161,9 @@
 #define CNST_THRESH_VAL(v)      (((v) & EVENT_THRESH_MASK) << 32)
 #define CNST_THRESH_MASK        CNST_THRESH_VAL(EVENT_THRESH_MASK)
 
+#define CNST_EBB_VAL(v)         (((v) & EVENT_EBB_MASK) << 24)
+#define CNST_EBB_MASK           CNST_EBB_VAL(EVENT_EBB_MASK)
+
 #define CNST_L1_QUAL_VAL(v)     (((v) & 3) << 22)
 #define CNST_L1_QUAL_MASK       CNST_L1_QUAL_VAL(3)
 
@@ -207,14 +222,21 @@ static inline bool event_is_fab_match(u64 event)
 
 static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
 {
-        unsigned int unit, pmc, cache;
+        unsigned int unit, pmc, cache, ebb;
         unsigned long mask, value;
 
         mask = value = 0;
 
-        pmc   = (event >> EVENT_PMC_SHIFT)       & EVENT_PMC_MASK;
-        unit  = (event >> EVENT_UNIT_SHIFT)      & EVENT_UNIT_MASK;
-        cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK;
+        if (event & ~EVENT_VALID_MASK)
+                return -1;
+
+        pmc   = (event >> EVENT_PMC_SHIFT)        & EVENT_PMC_MASK;
+        unit  = (event >> EVENT_UNIT_SHIFT)       & EVENT_UNIT_MASK;
+        cache = (event >> EVENT_CACHE_SEL_SHIFT)  & EVENT_CACHE_SEL_MASK;
+        ebb   = (event >> EVENT_CONFIG_EBB_SHIFT) & EVENT_EBB_MASK;
+
+        /* Clear the EBB bit in the event, so event checks work below */
+        event &= ~(EVENT_EBB_MASK << EVENT_CONFIG_EBB_SHIFT);
 
         if (pmc) {
                 if (pmc > 6)
@@ -284,6 +306,18 @@ static int power8_get_constraint(u64 event, unsigned long *maskp, unsigned long
                 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT);
         }
 
+        if (!pmc && ebb)
+                /* EBB events must specify the PMC */
+                return -1;
+
+        /*
+         * All events must agree on EBB, either all request it or none.
+         * EBB events are pinned & exclusive, so this should never actually
+         * hit, but we leave it as a fallback in case.
+         */
+        mask  |= CNST_EBB_VAL(ebb);
+        value |= CNST_EBB_MASK;
+
         *maskp = mask;
         *valp = value;
 
@@ -378,6 +412,10 @@ static int power8_compute_mmcr(u64 event[], int n_ev,
         if (pmc_inuse & 0x7c)
                 mmcr[0] |= MMCR0_PMCjCE;
 
+        /* If we're not using PMC 5 or 6, freeze them */
+        if (!(pmc_inuse & 0x60))
+                mmcr[0] |= MMCR0_FC56;
+
         mmcr[1] = mmcr1;
         mmcr[2] = mmcra;
 
@@ -574,7 +612,7 @@ static struct power_pmu power8_pmu = {
         .get_constraint         = power8_get_constraint,
         .get_alternatives       = power8_get_alternatives,
         .disable_pmc            = power8_disable_pmc,
-        .flags                  = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB,
+        .flags                  = PPMU_HAS_SSLOT | PPMU_HAS_SIER | PPMU_BHRB | PPMU_EBB,
         .n_generic              = ARRAY_SIZE(power8_generic_events),
         .generic_events         = power8_generic_events,
         .attr_groups            = power8_pmu_attr_groups,
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index ecd3890c40d7..7f1b71a01c6a 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -91,12 +91,12 @@ static void __init ppc47x_init_irq(void)
 }
 
 #ifdef CONFIG_SMP
-static void __cpuinit smp_ppc47x_setup_cpu(int cpu)
+static void smp_ppc47x_setup_cpu(int cpu)
 {
         mpic_setup_this_cpu();
 }
 
-static int __cpuinit smp_ppc47x_kick_cpu(int cpu)
+static int smp_ppc47x_kick_cpu(int cpu)
 {
         struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
         const u64 *spin_table_addr_prop;
@@ -176,13 +176,48 @@ static int __init ppc47x_probe(void)
         return 1;
 }
 
+static int board_rev = -1;
+static int __init ppc47x_get_board_rev(void)
+{
+        u8 fpga_reg0;
+        void *fpga;
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "ibm,currituck-fpga");
+        if (!np)
+                goto fail;
+
+        fpga = of_iomap(np, 0);
+        of_node_put(np);
+        if (!fpga)
+                goto fail;
+
+        fpga_reg0 = ioread8(fpga);
+        board_rev = fpga_reg0 & 0x03;
+        pr_info("%s: Found board revision %d\n", __func__, board_rev);
+        iounmap(fpga);
+        return 0;
+
+fail:
+        pr_info("%s: Unable to find board revision\n", __func__);
+        return 0;
+}
+machine_arch_initcall(ppc47x, ppc47x_get_board_rev);
+
 /* Use USB controller should have been hardware swizzled but it wasn't :( */
 static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
 {
         if (dev->vendor == 0x1033 && (dev->device == 0x0035 ||
                                       dev->device == 0x00e0)) {
-                dev->irq = irq_create_mapping(NULL, 47);
-                pr_info("%s: Mapping irq 47 %d\n", __func__, dev->irq);
+                if (board_rev == 0) {
+                        dev->irq = irq_create_mapping(NULL, 47);
+                        pr_info("%s: Mapping irq %d\n", __func__, dev->irq);
+                } else if (board_rev == 2) {
+                        dev->irq = irq_create_mapping(NULL, 49);
+                        pr_info("%s: Mapping irq %d\n", __func__, dev->irq);
+                } else {
+                        pr_alert("%s: Unknown board revision\n", __func__);
+                }
         }
 }
 
diff --git a/arch/powerpc/platforms/44x/iss4xx.c b/arch/powerpc/platforms/44x/iss4xx.c
index a28a8629727e..4241bc825800 100644
--- a/arch/powerpc/platforms/44x/iss4xx.c
+++ b/arch/powerpc/platforms/44x/iss4xx.c
@@ -81,12 +81,12 @@ static void __init iss4xx_init_irq(void)
 }
 
 #ifdef CONFIG_SMP
-static void __cpuinit smp_iss4xx_setup_cpu(int cpu)
+static void smp_iss4xx_setup_cpu(int cpu)
 {
         mpic_setup_this_cpu();
 }
 
-static int __cpuinit smp_iss4xx_kick_cpu(int cpu)
+static int smp_iss4xx_kick_cpu(int cpu)
 {
         struct device_node *cpunode = of_get_cpu_node(cpu, NULL);
         const u64 *spin_table_addr_prop;
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index 0a134e0469ef..3e90ece10ae9 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -43,9 +43,7 @@ static void __init mpc5121_ads_setup_arch(void)
                 mpc83xx_add_bridge(np);
 #endif
 
-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-        mpc512x_setup_diu();
-#endif
+        mpc512x_setup_arch();
 }
 
 static void __init mpc5121_ads_init_IRQ(void)
@@ -69,7 +67,7 @@ define_machine(mpc5121_ads) {
         .probe                  = mpc5121_ads_probe,
         .setup_arch             = mpc5121_ads_setup_arch,
         .init                   = mpc512x_init,
-        .init_early             = mpc512x_init_diu,
+        .init_early             = mpc512x_init_early,
         .init_IRQ               = mpc5121_ads_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index 0a8e60023944..cc97f022d028 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -12,18 +12,12 @@
 #ifndef __MPC512X_H__
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
+extern void __init mpc512x_init_early(void);
 extern void __init mpc512x_init(void);
+extern void __init mpc512x_setup_arch(void);
 extern int __init mpc5121_clk_init(void);
-void __init mpc512x_declare_of_platform_devices(void);
 extern const char *mpc512x_select_psc_compat(void);
+extern const char *mpc512x_select_reset_compat(void);
 extern void mpc512x_restart(char *cmd);
 
-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
-void mpc512x_init_diu(void);
-void mpc512x_setup_diu(void);
-#else
-#define mpc512x_init_diu NULL
-#define mpc512x_setup_diu NULL
-#endif
-
 #endif                          /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_generic.c b/arch/powerpc/platforms/512x/mpc512x_generic.c
index 5fb919b30924..ce71408781a0 100644
--- a/arch/powerpc/platforms/512x/mpc512x_generic.c
+++ b/arch/powerpc/platforms/512x/mpc512x_generic.c
@@ -45,8 +45,8 @@ define_machine(mpc512x_generic) {
         .name                   = "MPC512x generic",
         .probe                  = mpc512x_generic_probe,
         .init                   = mpc512x_init,
-        .init_early             = mpc512x_init_diu,
-        .setup_arch             = mpc512x_setup_diu,
+        .init_early             = mpc512x_init_early,
+        .setup_arch             = mpc512x_setup_arch,
         .init_IRQ               = mpc512x_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 6eb94ab99d39..a82a41b4fd91 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -35,8 +35,10 @@ static struct mpc512x_reset_module __iomem *reset_module_base;
 static void __init mpc512x_restart_init(void)
 {
         struct device_node *np;
+        const char *reset_compat;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
+        reset_compat = mpc512x_select_reset_compat();
+        np = of_find_compatible_node(NULL, NULL, reset_compat);
         if (!np)
                 return;
 
@@ -58,7 +60,7 @@ void mpc512x_restart(char *cmd)
                 ;
 }
 
-#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
+#if IS_ENABLED(CONFIG_FB_FSL_DIU)
 
 struct fsl_diu_shared_fb {
         u8              gamma[0x300];   /* 32-bit aligned! */
@@ -355,6 +357,17 @@ const char *mpc512x_select_psc_compat(void)
         return NULL;
 }
 
+const char *mpc512x_select_reset_compat(void)
+{
+        if (of_machine_is_compatible("fsl,mpc5121"))
+                return "fsl,mpc5121-reset";
+
+        if (of_machine_is_compatible("fsl,mpc5125"))
+                return "fsl,mpc5125-reset";
+
+        return NULL;
+}
+
 static unsigned int __init get_fifo_size(struct device_node *np,
                                          char *prop_name)
 {
@@ -436,14 +449,26 @@ void __init mpc512x_psc_fifo_init(void)
         }
 }
 
+void __init mpc512x_init_early(void)
+{
+        mpc512x_restart_init();
+        if (IS_ENABLED(CONFIG_FB_FSL_DIU))
+                mpc512x_init_diu();
+}
+
 void __init mpc512x_init(void)
 {
         mpc5121_clk_init();
         mpc512x_declare_of_platform_devices();
-        mpc512x_restart_init();
         mpc512x_psc_fifo_init();
 }
 
+void __init mpc512x_setup_arch(void)
+{
+        if (IS_ENABLED(CONFIG_FB_FSL_DIU))
+                mpc512x_setup_diu();
+}
+
 /**
  * mpc512x_cs_config - Setup chip select configuration
  * @cs: chip select number
diff --git a/arch/powerpc/platforms/512x/pdm360ng.c b/arch/powerpc/platforms/512x/pdm360ng.c
index 0575e858291c..24b314d7bd5f 100644
--- a/arch/powerpc/platforms/512x/pdm360ng.c
+++ b/arch/powerpc/platforms/512x/pdm360ng.c
@@ -119,9 +119,9 @@ static int __init pdm360ng_probe(void)
 define_machine(pdm360ng) {
         .name                   = "PDM360NG",
         .probe                  = pdm360ng_probe,
-        .setup_arch             = mpc512x_setup_diu,
+        .setup_arch             = mpc512x_setup_arch,
         .init                   = pdm360ng_init,
-        .init_early             = mpc512x_init_diu,
+        .init_early             = mpc512x_init_early,
         .init_IRQ               = mpc512x_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index 624cb51d19c9..7bc315822935 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -231,17 +231,7 @@ static struct i2c_driver mcu_driver = {
         .id_table = mcu_ids,
 };
 
-static int __init mcu_init(void)
-{
-        return i2c_add_driver(&mcu_driver);
-}
-module_init(mcu_init);
-
-static void __exit mcu_exit(void)
-{
-        i2c_del_driver(&mcu_driver);
-}
-module_exit(mcu_exit);
+module_i2c_driver(mcu_driver);
 
 MODULE_DESCRIPTION("Power Management and GPIO expander driver for "
                    "MPC8349E-mITX-compatible MCU");
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
index 753a42c29d4d..39cfa4044e6c 100644
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ b/arch/powerpc/platforms/85xx/p5020_ds.c
@@ -75,12 +75,7 @@ define_machine(p5020_ds) {
 #ifdef CONFIG_PCI
         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
-        .get_irq                = mpic_get_irq,
-#else
         .get_irq                = mpic_get_coreint_irq,
-#endif
         .restart                = fsl_rstcr_restart,
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
index 11381851828e..f70e74cddf97 100644
--- a/arch/powerpc/platforms/85xx/p5040_ds.c
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -66,12 +66,7 @@ define_machine(p5040_ds) {
 #ifdef CONFIG_PCI
         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
-        .get_irq                = mpic_get_irq,
-#else
         .get_irq                = mpic_get_coreint_irq,
-#endif
         .restart                = fsl_rstcr_restart,
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 6a1759939c6b..5ced4f5bb2b2 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -99,7 +99,7 @@ static void mpc85xx_take_timebase(void)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static void __cpuinit smp_85xx_mach_cpu_die(void)
+static void smp_85xx_mach_cpu_die(void)
 {
         unsigned int cpu = smp_processor_id();
         u32 tmp;
@@ -141,7 +141,7 @@ static inline u32 read_spin_table_addr_l(void *spin_table)
         return in_be32(&((struct epapr_spin_table *)spin_table)->addr_l);
 }
 
-static int __cpuinit smp_85xx_kick_cpu(int nr)
+static int smp_85xx_kick_cpu(int nr)
 {
         unsigned long flags;
         const u64 *cpu_rel_addr;
@@ -362,7 +362,7 @@ static void mpc85xx_smp_machine_kexec(struct kimage *image)
 }
 #endif /* CONFIG_KEXEC */
 
-static void __cpuinit smp_85xx_setup_cpu(int cpu_nr)
+static void smp_85xx_setup_cpu(int cpu_nr)
 {
         if (smp_85xx_ops.probe == smp_mpic_probe)
                 mpic_setup_this_cpu();
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
index 5998e9f33304..91ead6b1b8af 100644
--- a/arch/powerpc/platforms/85xx/t4240_qds.c
+++ b/arch/powerpc/platforms/85xx/t4240_qds.c
@@ -75,12 +75,7 @@ define_machine(t4240_qds) {
 #ifdef CONFIG_PCI
         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 #endif
-/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
-#ifdef CONFIG_PPC64
-        .get_irq                = mpic_get_irq,
-#else
         .get_irq                = mpic_get_coreint_irq,
-#endif
         .restart                = fsl_rstcr_restart,
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index 1e121088826f..587a2828b06c 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -43,6 +43,7 @@ static irqreturn_t timebase_interrupt(int irq, void *dev)
 
 static struct irqaction tbint_irqaction = {
         .handler = timebase_interrupt,
+        .flags = IRQF_NO_THREAD,
         .name = "tbint",
 };
 
@@ -218,19 +219,12 @@ void mpc8xx_restart(char *cmd)
 
 static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip;
-        int cascade_irq;
-
-        if ((cascade_irq = cpm_get_irq()) >= 0) {
-                struct irq_desc *cdesc = irq_to_desc(cascade_irq);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        int cascade_irq = cpm_get_irq();
 
+        if (cascade_irq >= 0)
                 generic_handle_irq(cascade_irq);
 
-                chip = irq_desc_get_chip(cdesc);
-                chip->irq_eoi(&cdesc->irq_data);
-        }
-
-        chip = irq_desc_get_chip(desc);
         chip->irq_eoi(&desc->irq_data);
 }
 
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index b62aab3e22ec..d703775bda30 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -86,6 +86,27 @@ config MPIC
         bool
         default n
 
+config MPIC_TIMER
+        bool "MPIC Global Timer"
+        depends on MPIC && FSL_SOC
+        default n
+        help
+          The MPIC global timer is a hardware timer inside the
+          Freescale PIC complying with OpenPIC standard. When the
+          specified interval times out, the hardware timer generates
+          an interrupt. The driver currently is only tested on fsl
+          chip, but it can potentially support other global timers
+          complying with the OpenPIC standard.
+
+config FSL_MPIC_TIMER_WAKEUP
+        tristate "Freescale MPIC global timer wakeup driver"
+        depends on FSL_SOC &&  MPIC_TIMER && PM
+        default n
+        help
+          The driver provides a way to wake up the system by MPIC
+          timer.
+          e.g. "echo 5 > /sys/devices/system/mpic/timer_wakeup"
+
 config PPC_EPAPR_HV_PIC
         bool
         default n
@@ -164,6 +185,11 @@ config IBMEBUS
         help
           Bus device driver for GX bus based adapters.
 
+config EEH
+        bool
+        depends on (PPC_POWERNV || PPC_PSERIES) && PCI
+        default y
+
 config PPC_MPC106
         bool
         default n
@@ -193,37 +219,6 @@ config PPC_IO_WORKAROUNDS
 
 source "drivers/cpufreq/Kconfig"
 
-menu "CPU Frequency drivers"
-        depends on CPU_FREQ
-
-config CPU_FREQ_PMAC
-        bool "Support for Apple PowerBooks"
-        depends on ADB_PMU && PPC32
-        select CPU_FREQ_TABLE
-        help
-          This adds support for frequency switching on Apple PowerBooks,
-          this currently includes some models of iBook & Titanium
-          PowerBook.
-
-config CPU_FREQ_PMAC64
-        bool "Support for some Apple G5s"
-        depends on PPC_PMAC && PPC64
-        select CPU_FREQ_TABLE
-        help
-          This adds support for frequency switching on Apple iMac G5,
-          and some of the more recent desktop G5 machines as well.
-
-config PPC_PASEMI_CPUFREQ
-        bool "Support for PA Semi PWRficient"
-        depends on PPC_PASEMI
-        default y
-        select CPU_FREQ_TABLE
-        help
-          This adds the support for frequency switching on PA Semi
-          PWRficient processors.
-
-endmenu
-
 menu "CPUIdle driver"
 
 source "drivers/cpuidle/Kconfig"
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 54f3936001aa..47d9a03dd415 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -71,6 +71,7 @@ config PPC_BOOK3S_64
         select PPC_FPU
         select PPC_HAVE_PMU_SUPPORT
         select SYS_SUPPORTS_HUGETLBFS
+        select HAVE_ARCH_TRANSPARENT_HUGEPAGE if PPC_64K_PAGES
 
 config PPC_BOOK3E_64
         bool "Embedded processors"
@@ -158,6 +159,7 @@ config E500
 config PPC_E500MC
         bool "e500mc Support"
         select PPC_FPU
+        select COMMON_CLK
         depends on E500
         help
           This must be enabled for running on e500mc (and derivatives
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 246e1d8b3af3..c34ee4e60873 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -185,7 +185,8 @@ static void beat_lpar_hptab_clear(void)
 static long beat_lpar_hpte_updatepp(unsigned long slot,
                                     unsigned long newpp,
                                     unsigned long vpn,
-                                    int psize, int ssize, int local)
+                                    int psize, int apsize,
+                                    int ssize, int local)
 {
         unsigned long lpar_rc;
         u64 dummy0, dummy1;
@@ -274,7 +275,8 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
 }
 
 static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
-                                         int psize, int ssize, int local)
+                                      int psize, int apsize,
+                                      int ssize, int local)
 {
         unsigned long want_v;
         unsigned long lpar_rc;
@@ -364,9 +366,10 @@ static long beat_lpar_hpte_insert_v3(unsigned long hpte_group,
  * already zero.  For now I am paranoid.
  */
 static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
-                                    unsigned long newpp,
-                                    unsigned long vpn,
-                                    int psize, int ssize, int local)
+                                       unsigned long newpp,
+                                       unsigned long vpn,
+                                       int psize, int apsize,
+                                       int ssize, int local)
 {
         unsigned long lpar_rc;
         unsigned long want_v;
@@ -394,7 +397,8 @@ static long beat_lpar_hpte_updatepp_v3(unsigned long slot,
 }
 
 static void beat_lpar_hpte_invalidate_v3(unsigned long slot, unsigned long vpn,
-                                         int psize, int ssize, int local)
+                                         int psize, int apsize,
+                                         int ssize, int local)
 {
         unsigned long want_v;
         unsigned long lpar_rc;
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index d35dbbc8ec79..f75f6fcac729 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -142,7 +142,7 @@ static int smp_cell_cpu_bootable(unsigned int nr)
          * during boot if the user requests it.  Odd-numbered
          * cpus are assumed to be secondary threads.
          */
-        if (system_state < SYSTEM_RUNNING &&
+        if (system_state == SYSTEM_BOOTING &&
             cpu_has_feature(CPU_FTR_SMT) &&
             !smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
                 return 0;
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 35f77a42bedf..f3900427ffab 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -238,7 +238,7 @@ const struct file_operations spufs_context_fops = {
         .release        = spufs_dir_close,
         .llseek         = dcache_dir_lseek,
         .read           = generic_read_dir,
-        .readdir        = dcache_readdir,
+        .iterate        = dcache_readdir,
         .fsync          = noop_fsync,
 };
 EXPORT_SYMBOL_GPL(spufs_context_fops);
diff --git a/arch/powerpc/platforms/pasemi/Makefile b/arch/powerpc/platforms/pasemi/Makefile
index ce6d789e0741..8e8d4cae5ebe 100644
--- a/arch/powerpc/platforms/pasemi/Makefile
+++ b/arch/powerpc/platforms/pasemi/Makefile
@@ -1,3 +1,2 @@
 obj-y   += setup.o pci.o time.o idle.o powersave.o iommu.o dma_lib.o misc.o
 obj-$(CONFIG_PPC_PASEMI_MDIO)   += gpio_mdio.o
-obj-$(CONFIG_PPC_PASEMI_CPUFREQ) += cpufreq.o
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
deleted file mode 100644
index be1e7958909e..000000000000
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2007 PA Semi, Inc
- *
- * Authors: Egor Martovetsky <egor@pasemi.com>
- *          Olof Johansson <olof@lixom.net>
- *
- * Maintained by: Olof Johansson <olof@lixom.net>
- *
- * Based on arch/powerpc/platforms/cell/cbe_cpufreq.c:
- * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/cpufreq.h>
-#include <linux/timer.h>
-#include <linux/module.h>
-
-#include <asm/hw_irq.h>
-#include <asm/io.h>
-#include <asm/prom.h>
-#include <asm/time.h>
-#include <asm/smp.h>
-
-#define SDCASR_REG              0x0100
-#define SDCASR_REG_STRIDE       0x1000
-#define SDCPWR_CFGA0_REG        0x0100
-#define SDCPWR_PWST0_REG        0x0000
-#define SDCPWR_GIZTIME_REG      0x0440
-
-/* SDCPWR_GIZTIME_REG fields */
-#define SDCPWR_GIZTIME_GR       0x80000000
-#define SDCPWR_GIZTIME_LONGLOCK 0x000000ff
-
-/* Offset of ASR registers from SDC base */
-#define SDCASR_OFFSET           0x120000
-
-static void __iomem *sdcpwr_mapbase;
-static void __iomem *sdcasr_mapbase;
-
-static DEFINE_MUTEX(pas_switch_mutex);
-
-/* Current astate, is used when waking up from power savings on
- * one core, in case the other core has switched states during
- * the idle time.
- */
-static int current_astate;
-
-/* We support 5(A0-A4) power states excluding turbo(A5-A6) modes */
-static struct cpufreq_frequency_table pas_freqs[] = {
-        {0,     0},
-        {1,     0},
-        {2,     0},
-        {3,     0},
-        {4,     0},
-        {0,     CPUFREQ_TABLE_END},
-};
-
-static struct freq_attr *pas_cpu_freqs_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-/*
- * hardware specific functions
- */
-
-static int get_astate_freq(int astate)
-{
-        u32 ret;
-        ret = in_le32(sdcpwr_mapbase + SDCPWR_CFGA0_REG + (astate * 0x10));
-
-        return ret & 0x3f;
-}
-
-static int get_cur_astate(int cpu)
-{
-        u32 ret;
-
-        ret = in_le32(sdcpwr_mapbase + SDCPWR_PWST0_REG);
-        ret = (ret >> (cpu * 4)) & 0x7;
-
-        return ret;
-}
-
-static int get_gizmo_latency(void)
-{
-        u32 giztime, ret;
-
-        giztime = in_le32(sdcpwr_mapbase + SDCPWR_GIZTIME_REG);
-
-        /* just provide the upper bound */
-        if (giztime & SDCPWR_GIZTIME_GR)
-                ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 128000;
-        else
-                ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 1000;
-
-        return ret;
-}
-
-static void set_astate(int cpu, unsigned int astate)
-{
-        unsigned long flags;
-
-        /* Return if called before init has run */
-        if (unlikely(!sdcasr_mapbase))
-                return;
-
-        local_irq_save(flags);
-
-        out_le32(sdcasr_mapbase + SDCASR_REG + SDCASR_REG_STRIDE*cpu, astate);
-
-        local_irq_restore(flags);
-}
-
-int check_astate(void)
-{
-        return get_cur_astate(hard_smp_processor_id());
-}
-
-void restore_astate(int cpu)
-{
-        set_astate(cpu, current_astate);
-}
-
-/*
- * cpufreq functions
- */
-
-static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        const u32 *max_freqp;
-        u32 max_freq;
-        int i, cur_astate;
-        struct resource res;
-        struct device_node *cpu, *dn;
-        int err = -ENODEV;
-
-        cpu = of_get_cpu_node(policy->cpu, NULL);
-
-        if (!cpu)
-                goto out;
-
-        dn = of_find_compatible_node(NULL, NULL, "1682m-sdc");
-        if (!dn)
-                dn = of_find_compatible_node(NULL, NULL,
-                                             "pasemi,pwrficient-sdc");
-        if (!dn)
-                goto out;
-        err = of_address_to_resource(dn, 0, &res);
-        of_node_put(dn);
-        if (err)
-                goto out;
-        sdcasr_mapbase = ioremap(res.start + SDCASR_OFFSET, 0x2000);
-        if (!sdcasr_mapbase) {
-                err = -EINVAL;
-                goto out;
-        }
-
-        dn = of_find_compatible_node(NULL, NULL, "1682m-gizmo");
-        if (!dn)
-                dn = of_find_compatible_node(NULL, NULL,
-                                             "pasemi,pwrficient-gizmo");
-        if (!dn) {
-                err = -ENODEV;
-                goto out_unmap_sdcasr;
-        }
-        err = of_address_to_resource(dn, 0, &res);
-        of_node_put(dn);
-        if (err)
-                goto out_unmap_sdcasr;
-        sdcpwr_mapbase = ioremap(res.start, 0x1000);
-        if (!sdcpwr_mapbase) {
-                err = -EINVAL;
-                goto out_unmap_sdcasr;
-        }
-
-        pr_debug("init cpufreq on CPU %d\n", policy->cpu);
-
-        max_freqp = of_get_property(cpu, "clock-frequency", NULL);
-        if (!max_freqp) {
-                err = -EINVAL;
-                goto out_unmap_sdcpwr;
-        }
-
-        /* we need the freq in kHz */
-        max_freq = *max_freqp / 1000;
-
-        pr_debug("max clock-frequency is at %u kHz\n", max_freq);
-        pr_debug("initializing frequency table\n");
-
-        /* initialize frequency table */
-        for (i=0; pas_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) {
-                pas_freqs[i].frequency = get_astate_freq(pas_freqs[i].index) * 100000;
-                pr_debug("%d: %d\n", i, pas_freqs[i].frequency);
-        }
-
-        policy->cpuinfo.transition_latency = get_gizmo_latency();
-
-        cur_astate = get_cur_astate(policy->cpu);
-        pr_debug("current astate is at %d\n",cur_astate);
-
-        policy->cur = pas_freqs[cur_astate].frequency;
-        cpumask_copy(policy->cpus, cpu_online_mask);
-
-        ppc_proc_freq = policy->cur * 1000ul;
-
-        cpufreq_frequency_table_get_attr(pas_freqs, policy->cpu);
-
-        /* this ensures that policy->cpuinfo_min and policy->cpuinfo_max
-         * are set correctly
-         */
-        return cpufreq_frequency_table_cpuinfo(policy, pas_freqs);
-
-out_unmap_sdcpwr:
-        iounmap(sdcpwr_mapbase);
-
-out_unmap_sdcasr:
-        iounmap(sdcasr_mapbase);
-out:
-        return err;
-}
-
-static int pas_cpufreq_cpu_exit(struct cpufreq_policy *policy)
-{
-        /*
-         * We don't support CPU hotplug. Don't unmap after the system
-         * has already made it to a running state.
-         */
-        if (system_state != SYSTEM_BOOTING)
-                return 0;
-
-        if (sdcasr_mapbase)
-                iounmap(sdcasr_mapbase);
-        if (sdcpwr_mapbase)
-                iounmap(sdcpwr_mapbase);
-
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-static int pas_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, pas_freqs);
-}
-
-static int pas_cpufreq_target(struct cpufreq_policy *policy,
-                              unsigned int target_freq,
-                              unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        int pas_astate_new;
-        int i;
-
-        cpufreq_frequency_table_target(policy,
-                                       pas_freqs,
-                                       target_freq,
-                                       relation,
-                                       &pas_astate_new);
-
-        freqs.old = policy->cur;
-        freqs.new = pas_freqs[pas_astate_new].frequency;
-
-        mutex_lock(&pas_switch_mutex);
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
-
-        pr_debug("setting frequency for cpu %d to %d kHz, 1/%d of max frequency\n",
-                 policy->cpu,
-                 pas_freqs[pas_astate_new].frequency,
-                 pas_freqs[pas_astate_new].index);
-
-        current_astate = pas_astate_new;
-
-        for_each_online_cpu(i)
-                set_astate(i, pas_astate_new);
-
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
-        mutex_unlock(&pas_switch_mutex);
-
-        ppc_proc_freq = freqs.new * 1000ul;
-        return 0;
-}
-
-static struct cpufreq_driver pas_cpufreq_driver = {
-        .name           = "pas-cpufreq",
-        .owner          = THIS_MODULE,
-        .flags          = CPUFREQ_CONST_LOOPS,
-        .init           = pas_cpufreq_cpu_init,
-        .exit           = pas_cpufreq_cpu_exit,
-        .verify         = pas_cpufreq_verify,
-        .target         = pas_cpufreq_target,
-        .attr           = pas_cpu_freqs_attr,
-};
-
-/*
- * module init and destoy
- */
-
-static int __init pas_cpufreq_init(void)
-{
-        if (!of_machine_is_compatible("PA6T-1682M") &&
-            !of_machine_is_compatible("pasemi,pwrficient"))
-                return -ENODEV;
-
-        return cpufreq_register_driver(&pas_cpufreq_driver);
-}
-
-static void __exit pas_cpufreq_exit(void)
-{
-        cpufreq_unregister_driver(&pas_cpufreq_driver);
-}
-
-module_init(pas_cpufreq_init);
-module_exit(pas_cpufreq_exit);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>, Olof Johansson <olof@lixom.net>");
diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile
index ea47df66fee5..52c6ce1cc985 100644
--- a/arch/powerpc/platforms/powermac/Makefile
+++ b/arch/powerpc/platforms/powermac/Makefile
@@ -9,8 +9,6 @@ obj-y				+= pic.o setup.o time.o feature.o pci.o \
                                    sleep.o low_i2c.o cache.o pfunc_core.o \
                                    pfunc_base.o udbg_scc.o udbg_adb.o
 obj-$(CONFIG_PMAC_BACKLIGHT)    += backlight.o
-obj-$(CONFIG_CPU_FREQ_PMAC)     += cpufreq_32.o
-obj-$(CONFIG_CPU_FREQ_PMAC64)   += cpufreq_64.o
 # CONFIG_NVRAM is an arch. independent tristate symbol, for pmac32 we really
 # need this to be a bool.  Cheat here and pretend CONFIG_NVRAM=m is really
 # CONFIG_NVRAM=y
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
deleted file mode 100644
index 3104fad82480..000000000000
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ /dev/null
@@ -1,721 +0,0 @@
-/*
- *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *  Copyright (C) 2004        John Steele Scott <toojays@toojays.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * TODO: Need a big cleanup here. Basically, we need to have different
- * cpufreq_driver structures for the different type of HW instead of the
- * current mess. We also need to better deal with the detection of the
- * type of machine.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/adb.h>
-#include <linux/pmu.h>
-#include <linux/cpufreq.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/hardirq.h>
-#include <asm/prom.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
-#include <asm/pmac_feature.h>
-#include <asm/mmu_context.h>
-#include <asm/sections.h>
-#include <asm/cputable.h>
-#include <asm/time.h>
-#include <asm/mpic.h>
-#include <asm/keylargo.h>
-#include <asm/switch_to.h>
-
-/* WARNING !!! This will cause calibrate_delay() to be called,
- * but this is an __init function ! So you MUST go edit
- * init/main.c to make it non-init before enabling DEBUG_FREQ
- */
-#undef DEBUG_FREQ
-
-extern void low_choose_7447a_dfs(int dfs);
-extern void low_choose_750fx_pll(int pll);
-extern void low_sleep_handler(void);
-
-/*
- * Currently, PowerMac cpufreq supports only high & low frequencies
- * that are set by the firmware
- */
-static unsigned int low_freq;
-static unsigned int hi_freq;
-static unsigned int cur_freq;
-static unsigned int sleep_freq;
-static unsigned long transition_latency;
-
-/*
- * Different models uses different mechanisms to switch the frequency
- */
-static int (*set_speed_proc)(int low_speed);
-static unsigned int (*get_speed_proc)(void);
-
-/*
- * Some definitions used by the various speedprocs
- */
-static u32 voltage_gpio;
-static u32 frequency_gpio;
-static u32 slew_done_gpio;
-static int no_schedule;
-static int has_cpu_l2lve;
-static int is_pmu_based;
-
-/* There are only two frequency states for each processor. Values
- * are in kHz for the time being.
- */
-#define CPUFREQ_HIGH                  0
-#define CPUFREQ_LOW                   1
-
-static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
-        {CPUFREQ_HIGH,          0},
-        {CPUFREQ_LOW,           0},
-        {0,                     CPUFREQ_TABLE_END},
-};
-
-static struct freq_attr* pmac_cpu_freqs_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-static inline void local_delay(unsigned long ms)
-{
-        if (no_schedule)
-                mdelay(ms);
-        else
-                msleep(ms);
-}
-
-#ifdef DEBUG_FREQ
-static inline void debug_calc_bogomips(void)
-{
-        /* This will cause a recalc of bogomips and display the
-         * result. We backup/restore the value to avoid affecting the
-         * core cpufreq framework's own calculation.
-         */
-        unsigned long save_lpj = loops_per_jiffy;
-        calibrate_delay();
-        loops_per_jiffy = save_lpj;
-}
-#endif /* DEBUG_FREQ */
-
-/* Switch CPU speed under 750FX CPU control
- */
-static int cpu_750fx_cpu_speed(int low_speed)
-{
-        u32 hid2;
-
-        if (low_speed == 0) {
-                /* ramping up, set voltage first */
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-                /* Make sure we sleep for at least 1ms */
-                local_delay(10);
-
-                /* tweak L2 for high voltage */
-                if (has_cpu_l2lve) {
-                        hid2 = mfspr(SPRN_HID2);
-                        hid2 &= ~0x2000;
-                        mtspr(SPRN_HID2, hid2);
-                }
-        }
-#ifdef CONFIG_6xx
-        low_choose_750fx_pll(low_speed);
-#endif
-        if (low_speed == 1) {
-                /* tweak L2 for low voltage */
-                if (has_cpu_l2lve) {
-                        hid2 = mfspr(SPRN_HID2);
-                        hid2 |= 0x2000;
-                        mtspr(SPRN_HID2, hid2);
-                }
-
-                /* ramping down, set voltage last */
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-                local_delay(10);
-        }
-
-        return 0;
-}
-
-static unsigned int cpu_750fx_get_cpu_speed(void)
-{
-        if (mfspr(SPRN_HID1) & HID1_PS)
-                return low_freq;
-        else
-                return hi_freq;
-}
-
-/* Switch CPU speed using DFS */
-static int dfs_set_cpu_speed(int low_speed)
-{
-        if (low_speed == 0) {
-                /* ramping up, set voltage first */
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-                /* Make sure we sleep for at least 1ms */
-                local_delay(1);
-        }
-
-        /* set frequency */
-#ifdef CONFIG_6xx
-        low_choose_7447a_dfs(low_speed);
-#endif
-        udelay(100);
-
-        if (low_speed == 1) {
-                /* ramping down, set voltage last */
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-                local_delay(1);
-        }
-
-        return 0;
-}
-
-static unsigned int dfs_get_cpu_speed(void)
-{
-        if (mfspr(SPRN_HID1) & HID1_DFS)
-                return low_freq;
-        else
-                return hi_freq;
-}
-
-
-/* Switch CPU speed using slewing GPIOs
- */
-static int gpios_set_cpu_speed(int low_speed)
-{
-        int gpio, timeout = 0;
-
-        /* If ramping up, set voltage first */
-        if (low_speed == 0) {
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
-                /* Delay is way too big but it's ok, we schedule */
-                local_delay(10);
-        }
-
-        /* Set frequency */
-        gpio =  pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
-        if (low_speed == ((gpio & 0x01) == 0))
-                goto skip;
-
-        pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
-                          low_speed ? 0x04 : 0x05);
-        udelay(200);
-        do {
-                if (++timeout > 100)
-                        break;
-                local_delay(1);
-                gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
-        } while((gpio & 0x02) == 0);
- skip:
-        /* If ramping down, set voltage last */
-        if (low_speed == 1) {
-                pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
-                /* Delay is way too big but it's ok, we schedule */
-                local_delay(10);
-        }
-
-#ifdef DEBUG_FREQ
-        debug_calc_bogomips();
-#endif
-
-        return 0;
-}
-
-/* Switch CPU speed under PMU control
- */
-static int pmu_set_cpu_speed(int low_speed)
-{
-        struct adb_request req;
-        unsigned long save_l2cr;
-        unsigned long save_l3cr;
-        unsigned int pic_prio;
-        unsigned long flags;
-
-        preempt_disable();
-
-#ifdef DEBUG_FREQ
-        printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
-#endif
-        pmu_suspend();
-
-        /* Disable all interrupt sources on openpic */
-        pic_prio = mpic_cpu_get_priority();
-        mpic_cpu_set_priority(0xf);
-
-        /* Make sure the decrementer won't interrupt us */
-        asm volatile("mtdec %0" : : "r" (0x7fffffff));
-        /* Make sure any pending DEC interrupt occurring while we did
-         * the above didn't re-enable the DEC */
-        mb();
-        asm volatile("mtdec %0" : : "r" (0x7fffffff));
-
-        /* We can now disable MSR_EE */
-        local_irq_save(flags);
-
-        /* Giveup the FPU & vec */
-        enable_kernel_fp();
-
-#ifdef CONFIG_ALTIVEC
-        if (cpu_has_feature(CPU_FTR_ALTIVEC))
-                enable_kernel_altivec();
-#endif /* CONFIG_ALTIVEC */
-
-        /* Save & disable L2 and L3 caches */
-        save_l3cr = _get_L3CR();        /* (returns -1 if not available) */
-        save_l2cr = _get_L2CR();        /* (returns -1 if not available) */
-
-        /* Send the new speed command. My assumption is that this command
-         * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
-         */
-        pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
-        while (!req.complete)
-                pmu_poll();
-
-        /* Prepare the northbridge for the speed transition */
-        pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
-
-        /* Call low level code to backup CPU state and recover from
-         * hardware reset
-         */
-        low_sleep_handler();
-
-        /* Restore the northbridge */
-        pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
-
-        /* Restore L2 cache */
-        if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
-                _set_L2CR(save_l2cr);
-        /* Restore L3 cache */
-        if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
-                _set_L3CR(save_l3cr);
-
-        /* Restore userland MMU context */
-        switch_mmu_context(NULL, current->active_mm);
-
-#ifdef DEBUG_FREQ
-        printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
-#endif
-
-        /* Restore low level PMU operations */
-        pmu_unlock();
-
-        /*
-         * Restore decrementer; we'll take a decrementer interrupt
-         * as soon as interrupts are re-enabled and the generic
-         * clockevents code will reprogram it with the right value.
-         */
-        set_dec(1);
-
-        /* Restore interrupts */
-        mpic_cpu_set_priority(pic_prio);
-
-        /* Let interrupts flow again ... */
-        local_irq_restore(flags);
-
-#ifdef DEBUG_FREQ
-        debug_calc_bogomips();
-#endif
-
-        pmu_resume();
-
-        preempt_enable();
-
-        return 0;
-}
-
-static int do_set_cpu_speed(struct cpufreq_policy *policy, int speed_mode,
-                int notify)
-{
-        struct cpufreq_freqs freqs;
-        unsigned long l3cr;
-        static unsigned long prev_l3cr;
-
-        freqs.old = cur_freq;
-        freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
-
-        if (freqs.old == freqs.new)
-                return 0;
-
-        if (notify)
-                cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
-        if (speed_mode == CPUFREQ_LOW &&
-            cpu_has_feature(CPU_FTR_L3CR)) {
-                l3cr = _get_L3CR();
-                if (l3cr & L3CR_L3E) {
-                        prev_l3cr = l3cr;
-                        _set_L3CR(0);
-                }
-        }
-        set_speed_proc(speed_mode == CPUFREQ_LOW);
-        if (speed_mode == CPUFREQ_HIGH &&
-            cpu_has_feature(CPU_FTR_L3CR)) {
-                l3cr = _get_L3CR();
-                if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
-                        _set_L3CR(prev_l3cr);
-        }
-        if (notify)
-                cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
-        cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
-
-        return 0;
-}
-
-static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
-{
-        return cur_freq;
-}
-
-static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
-}
-
-static int pmac_cpufreq_target( struct cpufreq_policy *policy,
-                                        unsigned int target_freq,
-                                        unsigned int relation)
-{
-        unsigned int    newstate = 0;
-        int             rc;
-
-        if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
-                        target_freq, relation, &newstate))
-                return -EINVAL;
-
-        rc = do_set_cpu_speed(policy, newstate, 1);
-
-        ppc_proc_freq = cur_freq * 1000ul;
-        return rc;
-}
-
-static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -ENODEV;
-
-        policy->cpuinfo.transition_latency      = transition_latency;
-        policy->cur = cur_freq;
-
-        cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
-        return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
-}
-
-static u32 read_gpio(struct device_node *np)
-{
-        const u32 *reg = of_get_property(np, "reg", NULL);
-        u32 offset;
-
-        if (reg == NULL)
-                return 0;
-        /* That works for all keylargos but shall be fixed properly
-         * some day... The problem is that it seems we can't rely
-         * on the "reg" property of the GPIO nodes, they are either
-         * relative to the base of KeyLargo or to the base of the
-         * GPIO space, and the device-tree doesn't help.
-         */
-        offset = *reg;
-        if (offset < KEYLARGO_GPIO_LEVELS0)
-                offset += KEYLARGO_GPIO_LEVELS0;
-        return offset;
-}
-
-static int pmac_cpufreq_suspend(struct cpufreq_policy *policy)
-{
-        /* Ok, this could be made a bit smarter, but let's be robust for now. We
-         * always force a speed change to high speed before sleep, to make sure
-         * we have appropriate voltage and/or bus speed for the wakeup process,
-         * and to make sure our loops_per_jiffies are "good enough", that is will
-         * not cause too short delays if we sleep in low speed and wake in high
-         * speed..
-         */
-        no_schedule = 1;
-        sleep_freq = cur_freq;
-        if (cur_freq == low_freq && !is_pmu_based)
-                do_set_cpu_speed(policy, CPUFREQ_HIGH, 0);
-        return 0;
-}
-
-static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
-{
-        /* If we resume, first check if we have a get() function */
-        if (get_speed_proc)
-                cur_freq = get_speed_proc();
-        else
-                cur_freq = 0;
-
-        /* We don't, hrm... we don't really know our speed here, best
-         * is that we force a switch to whatever it was, which is
-         * probably high speed due to our suspend() routine
-         */
-        do_set_cpu_speed(policy, sleep_freq == low_freq ?
-                         CPUFREQ_LOW : CPUFREQ_HIGH, 0);
-
-        ppc_proc_freq = cur_freq * 1000ul;
-
-        no_schedule = 0;
-        return 0;
-}
-
-static struct cpufreq_driver pmac_cpufreq_driver = {
-        .verify         = pmac_cpufreq_verify,
-        .target         = pmac_cpufreq_target,
-        .get            = pmac_cpufreq_get_speed,
-        .init           = pmac_cpufreq_cpu_init,
-        .suspend        = pmac_cpufreq_suspend,
-        .resume         = pmac_cpufreq_resume,
-        .flags          = CPUFREQ_PM_NO_WARN,
-        .attr           = pmac_cpu_freqs_attr,
-        .name           = "powermac",
-        .owner          = THIS_MODULE,
-};
-
-
-static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
-{
-        struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
-                                                                "voltage-gpio");
-        struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
-                                                                "frequency-gpio");
-        struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
-                                                                     "slewing-done");
-        const u32 *value;
-
-        /*
-         * Check to see if it's GPIO driven or PMU only
-         *
-         * The way we extract the GPIO address is slightly hackish, but it
-         * works well enough for now. We need to abstract the whole GPIO
-         * stuff sooner or later anyway
-         */
-
-        if (volt_gpio_np)
-                voltage_gpio = read_gpio(volt_gpio_np);
-        if (freq_gpio_np)
-                frequency_gpio = read_gpio(freq_gpio_np);
-        if (slew_done_gpio_np)
-                slew_done_gpio = read_gpio(slew_done_gpio_np);
-
-        /* If we use the frequency GPIOs, calculate the min/max speeds based
-         * on the bus frequencies
-         */
-        if (frequency_gpio && slew_done_gpio) {
-                int lenp, rc;
-                const u32 *freqs, *ratio;
-
-                freqs = of_get_property(cpunode, "bus-frequencies", &lenp);
-                lenp /= sizeof(u32);
-                if (freqs == NULL || lenp != 2) {
-                        printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
-                        return 1;
-                }
-                ratio = of_get_property(cpunode, "processor-to-bus-ratio*2",
-                                                NULL);
-                if (ratio == NULL) {
-                        printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
-                        return 1;
-                }
-
-                /* Get the min/max bus frequencies */
-                low_freq = min(freqs[0], freqs[1]);
-                hi_freq = max(freqs[0], freqs[1]);
-
-                /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
-                 * frequency, it claims it to be around 84Mhz on some models while
-                 * it appears to be approx. 101Mhz on all. Let's hack around here...
-                 * fortunately, we don't need to be too precise
-                 */
-                if (low_freq < 98000000)
-                        low_freq = 101000000;
-
-                /* Convert those to CPU core clocks */
-                low_freq = (low_freq * (*ratio)) / 2000;
-                hi_freq = (hi_freq * (*ratio)) / 2000;
-
-                /* Now we get the frequencies, we read the GPIO to see what is out current
-                 * speed
-                 */
-                rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
-                cur_freq = (rc & 0x01) ? hi_freq : low_freq;
-
-                set_speed_proc = gpios_set_cpu_speed;
-                return 1;
-        }
-
-        /* If we use the PMU, look for the min & max frequencies in the
-         * device-tree
-         */
-        value = of_get_property(cpunode, "min-clock-frequency", NULL);
-        if (!value)
-                return 1;
-        low_freq = (*value) / 1000;
-        /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
-         * here */
-        if (low_freq < 100000)
-                low_freq *= 10;
-
-        value = of_get_property(cpunode, "max-clock-frequency", NULL);
-        if (!value)
-                return 1;
-        hi_freq = (*value) / 1000;
-        set_speed_proc = pmu_set_cpu_speed;
-        is_pmu_based = 1;
-
-        return 0;
-}
-
-static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
-{
-        struct device_node *volt_gpio_np;
-
-        if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
-                return 1;
-
-        volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
-        if (volt_gpio_np)
-                voltage_gpio = read_gpio(volt_gpio_np);
-        if (!voltage_gpio){
-                printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
-                return 1;
-        }
-
-        /* OF only reports the high frequency */
-        hi_freq = cur_freq;
-        low_freq = cur_freq/2;
-
-        /* Read actual frequency from CPU */
-        cur_freq = dfs_get_cpu_speed();
-        set_speed_proc = dfs_set_cpu_speed;
-        get_speed_proc = dfs_get_cpu_speed;
-
-        return 0;
-}
-
-static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
-{
-        struct device_node *volt_gpio_np;
-        u32 pvr;
-        const u32 *value;
-
-        if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
-                return 1;
-
-        hi_freq = cur_freq;
-        value = of_get_property(cpunode, "reduced-clock-frequency", NULL);
-        if (!value)
-                return 1;
-        low_freq = (*value) / 1000;
-
-        volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
-        if (volt_gpio_np)
-                voltage_gpio = read_gpio(volt_gpio_np);
-
-        pvr = mfspr(SPRN_PVR);
-        has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
-
-        set_speed_proc = cpu_750fx_cpu_speed;
-        get_speed_proc = cpu_750fx_get_cpu_speed;
-        cur_freq = cpu_750fx_get_cpu_speed();
-
-        return 0;
-}
-
-/* Currently, we support the following machines:
- *
- *  - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
- *  - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
- *  - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
- *  - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
- *  - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
- *  - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
- *  - Recent MacRISC3 laptops
- *  - All new machines with 7447A CPUs
- */
-static int __init pmac_cpufreq_setup(void)
-{
-        struct device_node      *cpunode;
-        const u32               *value;
-
-        if (strstr(cmd_line, "nocpufreq"))
-                return 0;
-
-        /* Assume only one CPU */
-        cpunode = of_find_node_by_type(NULL, "cpu");
-        if (!cpunode)
-                goto out;
-
-        /* Get current cpu clock freq */
-        value = of_get_property(cpunode, "clock-frequency", NULL);
-        if (!value)
-                goto out;
-        cur_freq = (*value) / 1000;
-        transition_latency = CPUFREQ_ETERNAL;
-
-        /*  Check for 7447A based MacRISC3 */
-        if (of_machine_is_compatible("MacRISC3") &&
-            of_get_property(cpunode, "dynamic-power-step", NULL) &&
-            PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
-                pmac_cpufreq_init_7447A(cpunode);
-                transition_latency = 8000000;
-        /* Check for other MacRISC3 machines */
-        } else if (of_machine_is_compatible("PowerBook3,4") ||
-                   of_machine_is_compatible("PowerBook3,5") ||
-                   of_machine_is_compatible("MacRISC3")) {
-                pmac_cpufreq_init_MacRISC3(cpunode);
-        /* Else check for iBook2 500/600 */
-        } else if (of_machine_is_compatible("PowerBook4,1")) {
-                hi_freq = cur_freq;
-                low_freq = 400000;
-                set_speed_proc = pmu_set_cpu_speed;
-                is_pmu_based = 1;
-        }
-        /* Else check for TiPb 550 */
-        else if (of_machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
-                hi_freq = cur_freq;
-                low_freq = 500000;
-                set_speed_proc = pmu_set_cpu_speed;
-                is_pmu_based = 1;
-        }
-        /* Else check for TiPb 400 & 500 */
-        else if (of_machine_is_compatible("PowerBook3,2")) {
-                /* We only know about the 400 MHz and the 500Mhz model
-                 * they both have 300 MHz as low frequency
-                 */
-                if (cur_freq < 350000 || cur_freq > 550000)
-                        goto out;
-                hi_freq = cur_freq;
-                low_freq = 300000;
-                set_speed_proc = pmu_set_cpu_speed;
-                is_pmu_based = 1;
-        }
-        /* Else check for 750FX */
-        else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
-                pmac_cpufreq_init_750FX(cpunode);
-out:
-        of_node_put(cpunode);
-        if (set_speed_proc == NULL)
-                return -ENODEV;
-
-        pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
-        pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
-        ppc_proc_freq = cur_freq * 1000ul;
-
-        printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
-        printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
-               low_freq/1000, hi_freq/1000, cur_freq/1000);
-
-        return cpufreq_register_driver(&pmac_cpufreq_driver);
-}
-
-module_init(pmac_cpufreq_setup);
-
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
deleted file mode 100644
index 7ba423431cfe..000000000000
--- a/arch/powerpc/platforms/powermac/cpufreq_64.c
+++ /dev/null
@@ -1,746 +0,0 @@
-/*
- *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
- *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
- * that is iMac G5 and latest single CPU desktop.
- */
-
-#undef DEBUG
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <linux/cpufreq.h>
-#include <linux/init.h>
-#include <linux/completion.h>
-#include <linux/mutex.h>
-#include <asm/prom.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
-#include <asm/sections.h>
-#include <asm/cputable.h>
-#include <asm/time.h>
-#include <asm/smu.h>
-#include <asm/pmac_pfunc.h>
-
-#define DBG(fmt...) pr_debug(fmt)
-
-/* see 970FX user manual */
-
-#define SCOM_PCR 0x0aa001                       /* PCR scom addr */
-
-#define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
-#define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
-#define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
-#define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
-#define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
-#define PCR_SPEED_SHIFT         17
-#define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
-#define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
-#define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
-#define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
-#define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
-#define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
-
-#define SCOM_PSR 0x408001                       /* PSR scom addr */
-/* warning: PSR is a 64 bits register */
-#define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
-#define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
-#define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
-#define PSR_CUR_SPEED_SHIFT     (56)
-
-/*
- * The G5 only supports two frequencies (Quarter speed is not supported)
- */
-#define CPUFREQ_HIGH                  0
-#define CPUFREQ_LOW                   1
-
-static struct cpufreq_frequency_table g5_cpu_freqs[] = {
-        {CPUFREQ_HIGH,          0},
-        {CPUFREQ_LOW,           0},
-        {0,                     CPUFREQ_TABLE_END},
-};
-
-static struct freq_attr* g5_cpu_freqs_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-
-/* Power mode data is an array of the 32 bits PCR values to use for
- * the various frequencies, retrieved from the device-tree
- */
-static int g5_pmode_cur;
-
-static void (*g5_switch_volt)(int speed_mode);
-static int (*g5_switch_freq)(int speed_mode);
-static int (*g5_query_freq)(void);
-
-static DEFINE_MUTEX(g5_switch_mutex);
-
-static unsigned long transition_latency;
-
-#ifdef CONFIG_PMAC_SMU
-
-static const u32 *g5_pmode_data;
-static int g5_pmode_max;
-
-static struct smu_sdbp_fvt *g5_fvt_table;       /* table of op. points */
-static int g5_fvt_count;                        /* number of op. points */
-static int g5_fvt_cur;                          /* current op. point */
-
-/*
- * SMU based voltage switching for Neo2 platforms
- */
-
-static void g5_smu_switch_volt(int speed_mode)
-{
-        struct smu_simple_cmd   cmd;
-
-        DECLARE_COMPLETION_ONSTACK(comp);
-        smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
-                         &comp, 'V', 'S', 'L', 'E', 'W',
-                         0xff, g5_fvt_cur+1, speed_mode);
-        wait_for_completion(&comp);
-}
-
-/*
- * Platform function based voltage/vdnap switching for Neo2
- */
-
-static struct pmf_function *pfunc_set_vdnap0;
-static struct pmf_function *pfunc_vdnap0_complete;
-
-static void g5_vdnap_switch_volt(int speed_mode)
-{
-        struct pmf_args args;
-        u32 slew, done = 0;
-        unsigned long timeout;
-
-        slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
-        args.count = 1;
-        args.u[0].p = &slew;
-
-        pmf_call_one(pfunc_set_vdnap0, &args);
-
-        /* It's an irq GPIO so we should be able to just block here,
-         * I'll do that later after I've properly tested the IRQ code for
-         * platform functions
-         */
-        timeout = jiffies + HZ/10;
-        while(!time_after(jiffies, timeout)) {
-                args.count = 1;
-                args.u[0].p = &done;
-                pmf_call_one(pfunc_vdnap0_complete, &args);
-                if (done)
-                        break;
-                msleep(1);
-        }
-        if (done == 0)
-                printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
-}
-
-
-/*
- * SCOM based frequency switching for 970FX rev3
- */
-static int g5_scom_switch_freq(int speed_mode)
-{
-        unsigned long flags;
-        int to;
-
-        /* If frequency is going up, first ramp up the voltage */
-        if (speed_mode < g5_pmode_cur)
-                g5_switch_volt(speed_mode);
-
-        local_irq_save(flags);
-
-        /* Clear PCR high */
-        scom970_write(SCOM_PCR, 0);
-        /* Clear PCR low */
-        scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
-        /* Set PCR low */
-        scom970_write(SCOM_PCR, PCR_HILO_SELECT |
-                      g5_pmode_data[speed_mode]);
-
-        /* Wait for completion */
-        for (to = 0; to < 10; to++) {
-                unsigned long psr = scom970_read(SCOM_PSR);
-
-                if ((psr & PSR_CMD_RECEIVED) == 0 &&
-                    (((psr >> PSR_CUR_SPEED_SHIFT) ^
-                      (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
-                    == 0)
-                        break;
-                if (psr & PSR_CMD_COMPLETED)
-                        break;
-                udelay(100);
-        }
-
-        local_irq_restore(flags);
-
-        /* If frequency is going down, last ramp the voltage */
-        if (speed_mode > g5_pmode_cur)
-                g5_switch_volt(speed_mode);
-
-        g5_pmode_cur = speed_mode;
-        ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
-
-        return 0;
-}
-
-static int g5_scom_query_freq(void)
-{
-        unsigned long psr = scom970_read(SCOM_PSR);
-        int i;
-
-        for (i = 0; i <= g5_pmode_max; i++)
-                if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
-                      (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
-                        break;
-        return i;
-}
-
-/*
- * Fake voltage switching for platforms with missing support
- */
-
-static void g5_dummy_switch_volt(int speed_mode)
-{
-}
-
-#endif /* CONFIG_PMAC_SMU */
-
-/*
- * Platform function based voltage switching for PowerMac7,2 & 7,3
- */
-
-static struct pmf_function *pfunc_cpu0_volt_high;
-static struct pmf_function *pfunc_cpu0_volt_low;
-static struct pmf_function *pfunc_cpu1_volt_high;
-static struct pmf_function *pfunc_cpu1_volt_low;
-
-static void g5_pfunc_switch_volt(int speed_mode)
-{
-        if (speed_mode == CPUFREQ_HIGH) {
-                if (pfunc_cpu0_volt_high)
-                        pmf_call_one(pfunc_cpu0_volt_high, NULL);
-                if (pfunc_cpu1_volt_high)
-                        pmf_call_one(pfunc_cpu1_volt_high, NULL);
-        } else {
-                if (pfunc_cpu0_volt_low)
-                        pmf_call_one(pfunc_cpu0_volt_low, NULL);
-                if (pfunc_cpu1_volt_low)
-                        pmf_call_one(pfunc_cpu1_volt_low, NULL);
-        }
-        msleep(10); /* should be faster , to fix */
-}
-
-/*
- * Platform function based frequency switching for PowerMac7,2 & 7,3
- */
-
-static struct pmf_function *pfunc_cpu_setfreq_high;
-static struct pmf_function *pfunc_cpu_setfreq_low;
-static struct pmf_function *pfunc_cpu_getfreq;
-static struct pmf_function *pfunc_slewing_done;
-
-static int g5_pfunc_switch_freq(int speed_mode)
-{
-        struct pmf_args args;
-        u32 done = 0;
-        unsigned long timeout;
-        int rc;
-
-        DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
-
-        /* If frequency is going up, first ramp up the voltage */
-        if (speed_mode < g5_pmode_cur)
-                g5_switch_volt(speed_mode);
-
-        /* Do it */
-        if (speed_mode == CPUFREQ_HIGH)
-                rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
-        else
-                rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
-
-        if (rc)
-                printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
-
-        /* It's an irq GPIO so we should be able to just block here,
-         * I'll do that later after I've properly tested the IRQ code for
-         * platform functions
-         */
-        timeout = jiffies + HZ/10;
-        while(!time_after(jiffies, timeout)) {
-                args.count = 1;
-                args.u[0].p = &done;
-                pmf_call_one(pfunc_slewing_done, &args);
-                if (done)
-                        break;
-                msleep(1);
-        }
-        if (done == 0)
-                printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
-
-        /* If frequency is going down, last ramp the voltage */
-        if (speed_mode > g5_pmode_cur)
-                g5_switch_volt(speed_mode);
-
-        g5_pmode_cur = speed_mode;
-        ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
-
-        return 0;
-}
-
-static int g5_pfunc_query_freq(void)
-{
-        struct pmf_args args;
-        u32 val = 0;
-
-        args.count = 1;
-        args.u[0].p = &val;
-        pmf_call_one(pfunc_cpu_getfreq, &args);
-        return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
-}
-
-
-/*
- * Common interface to the cpufreq core
- */
-
-static int g5_cpufreq_verify(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
-}
-
-static int g5_cpufreq_target(struct cpufreq_policy *policy,
-        unsigned int target_freq, unsigned int relation)
-{
-        unsigned int newstate = 0;
-        struct cpufreq_freqs freqs;
-        int rc;
-
-        if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
-                        target_freq, relation, &newstate))
-                return -EINVAL;
-
-        if (g5_pmode_cur == newstate)
-                return 0;
-
-        mutex_lock(&g5_switch_mutex);
-
-        freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
-        freqs.new = g5_cpu_freqs[newstate].frequency;
-
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
-        rc = g5_switch_freq(newstate);
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
-
-        mutex_unlock(&g5_switch_mutex);
-
-        return rc;
-}
-
-static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
-{
-        return g5_cpu_freqs[g5_pmode_cur].frequency;
-}
-
-static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
-        policy->cpuinfo.transition_latency = transition_latency;
-        policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
-        /* secondary CPUs are tied to the primary one by the
-         * cpufreq core if in the secondary policy we tell it that
-         * it actually must be one policy together with all others. */
-        cpumask_copy(policy->cpus, cpu_online_mask);
-        cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
-
-        return cpufreq_frequency_table_cpuinfo(policy,
-                g5_cpu_freqs);
-}
-
-
-static struct cpufreq_driver g5_cpufreq_driver = {
-        .name           = "powermac",
-        .owner          = THIS_MODULE,
-        .flags          = CPUFREQ_CONST_LOOPS,
-        .init           = g5_cpufreq_cpu_init,
-        .verify         = g5_cpufreq_verify,
-        .target         = g5_cpufreq_target,
-        .get            = g5_cpufreq_get_speed,
-        .attr           = g5_cpu_freqs_attr,
-};
-
-
-#ifdef CONFIG_PMAC_SMU
-
-static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
-{
-        struct device_node *cpunode;
-        unsigned int psize, ssize;
-        unsigned long max_freq;
-        char *freq_method, *volt_method;
-        const u32 *valp;
-        u32 pvr_hi;
-        int use_volts_vdnap = 0;
-        int use_volts_smu = 0;
-        int rc = -ENODEV;
-
-        /* Check supported platforms */
-        if (of_machine_is_compatible("PowerMac8,1") ||
-            of_machine_is_compatible("PowerMac8,2") ||
-            of_machine_is_compatible("PowerMac9,1"))
-                use_volts_smu = 1;
-        else if (of_machine_is_compatible("PowerMac11,2"))
-                use_volts_vdnap = 1;
-        else
-                return -ENODEV;
-
-        /* Get first CPU node */
-        for (cpunode = NULL;
-             (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
-                const u32 *reg = of_get_property(cpunode, "reg", NULL);
-                if (reg == NULL || (*reg) != 0)
-                        continue;
-                if (!strcmp(cpunode->type, "cpu"))
-                        break;
-        }
-        if (cpunode == NULL) {
-                printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
-                return -ENODEV;
-        }
-
-        /* Check 970FX for now */
-        valp = of_get_property(cpunode, "cpu-version", NULL);
-        if (!valp) {
-                DBG("No cpu-version property !\n");
-                goto bail_noprops;
-        }
-        pvr_hi = (*valp) >> 16;
-        if (pvr_hi != 0x3c && pvr_hi != 0x44) {
-                printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
-                goto bail_noprops;
-        }
-
-        /* Look for the powertune data in the device-tree */
-        g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
-        if (!g5_pmode_data) {
-                DBG("No power-mode-data !\n");
-                goto bail_noprops;
-        }
-        g5_pmode_max = psize / sizeof(u32) - 1;
-
-        if (use_volts_smu) {
-                const struct smu_sdbp_header *shdr;
-
-                /* Look for the FVT table */
-                shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
-                if (!shdr)
-                        goto bail_noprops;
-                g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
-                ssize = (shdr->len * sizeof(u32)) -
-                        sizeof(struct smu_sdbp_header);
-                g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
-                g5_fvt_cur = 0;
-
-                /* Sanity checking */
-                if (g5_fvt_count < 1 || g5_pmode_max < 1)
-                        goto bail_noprops;
-
-                g5_switch_volt = g5_smu_switch_volt;
-                volt_method = "SMU";
-        } else if (use_volts_vdnap) {
-                struct device_node *root;
-
-                root = of_find_node_by_path("/");
-                if (root == NULL) {
-                        printk(KERN_ERR "cpufreq: Can't find root of "
-                               "device tree\n");
-                        goto bail_noprops;
-                }
-                pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
-                pfunc_vdnap0_complete =
-                        pmf_find_function(root, "slewing-done");
-                if (pfunc_set_vdnap0 == NULL ||
-                    pfunc_vdnap0_complete == NULL) {
-                        printk(KERN_ERR "cpufreq: Can't find required "
-                               "platform function\n");
-                        goto bail_noprops;
-                }
-
-                g5_switch_volt = g5_vdnap_switch_volt;
-                volt_method = "GPIO";
-        } else {
-                g5_switch_volt = g5_dummy_switch_volt;
-                volt_method = "none";
-        }
-
-        /*
-         * From what I see, clock-frequency is always the maximal frequency.
-         * The current driver can not slew sysclk yet, so we really only deal
-         * with powertune steps for now. We also only implement full freq and
-         * half freq in this version. So far, I haven't yet seen a machine
-         * supporting anything else.
-         */
-        valp = of_get_property(cpunode, "clock-frequency", NULL);
-        if (!valp)
-                return -ENODEV;
-        max_freq = (*valp)/1000;
-        g5_cpu_freqs[0].frequency = max_freq;
-        g5_cpu_freqs[1].frequency = max_freq/2;
-
-        /* Set callbacks */
-        transition_latency = 12000;
-        g5_switch_freq = g5_scom_switch_freq;
-        g5_query_freq = g5_scom_query_freq;
-        freq_method = "SCOM";
-
-        /* Force apply current frequency to make sure everything is in
-         * sync (voltage is right for example). Firmware may leave us with
-         * a strange setting ...
-         */
-        g5_switch_volt(CPUFREQ_HIGH);
-        msleep(10);
-        g5_pmode_cur = -1;
-        g5_switch_freq(g5_query_freq());
-
-        printk(KERN_INFO "Registering G5 CPU frequency driver\n");
-        printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
-               freq_method, volt_method);
-        printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
-                g5_cpu_freqs[1].frequency/1000,
-                g5_cpu_freqs[0].frequency/1000,
-                g5_cpu_freqs[g5_pmode_cur].frequency/1000);
-
-        rc = cpufreq_register_driver(&g5_cpufreq_driver);
-
-        /* We keep the CPU node on hold... hopefully, Apple G5 don't have
-         * hotplug CPU with a dynamic device-tree ...
-         */
-        return rc;
-
- bail_noprops:
-        of_node_put(cpunode);
-
-        return rc;
-}
-
-#endif /* CONFIG_PMAC_SMU */
-
-
-static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
-{
-        struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
-        const u8 *eeprom = NULL;
-        const u32 *valp;
-        u64 max_freq, min_freq, ih, il;
-        int has_volt = 1, rc = 0;
-
-        DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
-            " RackMac3,1...\n");
-
-        /* Get first CPU node */
-        for (cpunode = NULL;
-             (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
-                if (!strcmp(cpunode->type, "cpu"))
-                        break;
-        }
-        if (cpunode == NULL) {
-                printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
-                return -ENODEV;
-        }
-
-        /* Lookup the cpuid eeprom node */
-        cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
-        if (cpuid != NULL)
-                eeprom = of_get_property(cpuid, "cpuid", NULL);
-        if (eeprom == NULL) {
-                printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
-                rc = -ENODEV;
-                goto bail;
-        }
-
-        /* Lookup the i2c hwclock */
-        for (hwclock = NULL;
-             (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
-                const char *loc = of_get_property(hwclock,
-                                "hwctrl-location", NULL);
-                if (loc == NULL)
-                        continue;
-                if (strcmp(loc, "CPU CLOCK"))
-                        continue;
-                if (!of_get_property(hwclock, "platform-get-frequency", NULL))
-                        continue;
-                break;
-        }
-        if (hwclock == NULL) {
-                printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
-                rc = -ENODEV;
-                goto bail;
-        }
-
-        DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
-
-        /* Now get all the platform functions */
-        pfunc_cpu_getfreq =
-                pmf_find_function(hwclock, "get-frequency");
-        pfunc_cpu_setfreq_high =
-                pmf_find_function(hwclock, "set-frequency-high");
-        pfunc_cpu_setfreq_low =
-                pmf_find_function(hwclock, "set-frequency-low");
-        pfunc_slewing_done =
-                pmf_find_function(hwclock, "slewing-done");
-        pfunc_cpu0_volt_high =
-                pmf_find_function(hwclock, "set-voltage-high-0");
-        pfunc_cpu0_volt_low =
-                pmf_find_function(hwclock, "set-voltage-low-0");
-        pfunc_cpu1_volt_high =
-                pmf_find_function(hwclock, "set-voltage-high-1");
-        pfunc_cpu1_volt_low =
-                pmf_find_function(hwclock, "set-voltage-low-1");
-
-        /* Check we have minimum requirements */
-        if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
-            pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
-                printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
-                rc = -ENODEV;
-                goto bail;
-        }
-
-        /* Check that we have complete sets */
-        if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
-                pmf_put_function(pfunc_cpu0_volt_high);
-                pmf_put_function(pfunc_cpu0_volt_low);
-                pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
-                has_volt = 0;
-        }
-        if (!has_volt ||
-            pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
-                pmf_put_function(pfunc_cpu1_volt_high);
-                pmf_put_function(pfunc_cpu1_volt_low);
-                pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
-        }
-
-        /* Note: The device tree also contains a "platform-set-values"
-         * function for which I haven't quite figured out the usage. It
-         * might have to be called on init and/or wakeup, I'm not too sure
-         * but things seem to work fine without it so far ...
-         */
-
-        /* Get max frequency from device-tree */
-        valp = of_get_property(cpunode, "clock-frequency", NULL);
-        if (!valp) {
-                printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
-                rc = -ENODEV;
-                goto bail;
-        }
-
-        max_freq = (*valp)/1000;
-
-        /* Now calculate reduced frequency by using the cpuid input freq
-         * ratio. This requires 64 bits math unless we are willing to lose
-         * some precision
-         */
-        ih = *((u32 *)(eeprom + 0x10));
-        il = *((u32 *)(eeprom + 0x20));
-
-        /* Check for machines with no useful settings */
-        if (il == ih) {
-                printk(KERN_WARNING "cpufreq: No low frequency mode available"
-                       " on this model !\n");
-                rc = -ENODEV;
-                goto bail;
-        }
-
-        min_freq = 0;
-        if (ih != 0 && il != 0)
-                min_freq = (max_freq * il) / ih;
-
-        /* Sanity check */
-        if (min_freq >= max_freq || min_freq < 1000) {
-                printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
-                rc = -ENXIO;
-                goto bail;
-        }
-        g5_cpu_freqs[0].frequency = max_freq;
-        g5_cpu_freqs[1].frequency = min_freq;
-
-        /* Set callbacks */
-        transition_latency = CPUFREQ_ETERNAL;
-        g5_switch_volt = g5_pfunc_switch_volt;
-        g5_switch_freq = g5_pfunc_switch_freq;
-        g5_query_freq = g5_pfunc_query_freq;
-
-        /* Force apply current frequency to make sure everything is in
-         * sync (voltage is right for example). Firmware may leave us with
-         * a strange setting ...
-         */
-        g5_switch_volt(CPUFREQ_HIGH);
-        msleep(10);
-        g5_pmode_cur = -1;
-        g5_switch_freq(g5_query_freq());
-
-        printk(KERN_INFO "Registering G5 CPU frequency driver\n");
-        printk(KERN_INFO "Frequency method: i2c/pfunc, "
-               "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
-        printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
-                g5_cpu_freqs[1].frequency/1000,
-                g5_cpu_freqs[0].frequency/1000,
-                g5_cpu_freqs[g5_pmode_cur].frequency/1000);
-
-        rc = cpufreq_register_driver(&g5_cpufreq_driver);
- bail:
-        if (rc != 0) {
-                pmf_put_function(pfunc_cpu_getfreq);
-                pmf_put_function(pfunc_cpu_setfreq_high);
-                pmf_put_function(pfunc_cpu_setfreq_low);
-                pmf_put_function(pfunc_slewing_done);
-                pmf_put_function(pfunc_cpu0_volt_high);
-                pmf_put_function(pfunc_cpu0_volt_low);
-                pmf_put_function(pfunc_cpu1_volt_high);
-                pmf_put_function(pfunc_cpu1_volt_low);
-        }
-        of_node_put(hwclock);
-        of_node_put(cpuid);
-        of_node_put(cpunode);
-
-        return rc;
-}
-
-static int __init g5_cpufreq_init(void)
-{
-        struct device_node *cpus;
-        int rc = 0;
-
-        cpus = of_find_node_by_path("/cpus");
-        if (cpus == NULL) {
-                DBG("No /cpus node !\n");
-                return -ENODEV;
-        }
-
-        if (of_machine_is_compatible("PowerMac7,2") ||
-            of_machine_is_compatible("PowerMac7,3") ||
-            of_machine_is_compatible("RackMac3,1"))
-                rc = g5_pm72_cpufreq_init(cpus);
-#ifdef CONFIG_PMAC_SMU
-        else
-                rc = g5_neo2_cpufreq_init(cpus);
-#endif /* CONFIG_PMAC_SMU */
-
-        of_node_put(cpus);
-        return rc;
-}
-
-module_init(g5_cpufreq_init);
-
-
-MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index f921067d924d..5cbd4d67d5c4 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -885,7 +885,7 @@ static int smp_core99_cpu_notify(struct notifier_block *self,
         return NOTIFY_OK;
 }
 
-static struct notifier_block __cpuinitdata smp_core99_cpu_nb = {
+static struct notifier_block smp_core99_cpu_nb = {
         .notifier_call  = smp_core99_cpu_notify,
 };
 #endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/powerpc/platforms/powernv/Makefile b/arch/powerpc/platforms/powernv/Makefile
index bcc3cb48a44e..7fe595152478 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -3,3 +3,4 @@ obj-y			+= opal-rtc.o opal-nvram.o
 
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_PCI)       += pci.o pci-p5ioc2.o pci-ioda.o
+obj-$(CONFIG_EEH)       += eeh-ioda.o eeh-powernv.o
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
new file mode 100644
index 000000000000..0cd1c4a71755
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/eeh-ioda.c
@@ -0,0 +1,916 @@
+/*
+ * The file intends to implement the functions needed by EEH, which is
+ * built on IODA compliant chip. Actually, lots of functions related
+ * to EEH would be built based on the OPAL APIs.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/msi.h>
+#include <linux/notifier.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+
+#include <asm/eeh.h>
+#include <asm/eeh_event.h>
+#include <asm/io.h>
+#include <asm/iommu.h>
+#include <asm/msi_bitmap.h>
+#include <asm/opal.h>
+#include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
+#include <asm/tce.h>
+
+#include "powernv.h"
+#include "pci.h"
+
+/* Debugging option */
+#ifdef IODA_EEH_DBG_ON
+#define IODA_EEH_DBG(args...)   pr_info(args)
+#else
+#define IODA_EEH_DBG(args...)
+#endif
+
+static char *hub_diag = NULL;
+static int ioda_eeh_nb_init = 0;
+
+static int ioda_eeh_event(struct notifier_block *nb,
+                          unsigned long events, void *change)
+{
+        uint64_t changed_evts = (uint64_t)change;
+
+        /* We simply send special EEH event */
+        if ((changed_evts & OPAL_EVENT_PCI_ERROR) &&
+            (events & OPAL_EVENT_PCI_ERROR))
+                eeh_send_failure_event(NULL);
+
+        return 0;
+}
+
+static struct notifier_block ioda_eeh_nb = {
+        .notifier_call  = ioda_eeh_event,
+        .next           = NULL,
+        .priority       = 0
+};
+
+#ifdef CONFIG_DEBUG_FS
+static int ioda_eeh_dbgfs_set(void *data, u64 val)
+{
+        struct pci_controller *hose = data;
+        struct pnv_phb *phb = hose->private_data;
+
+        out_be64(phb->regs + 0xD10, val);
+        return 0;
+}
+
+static int ioda_eeh_dbgfs_get(void *data, u64 *val)
+{
+        struct pci_controller *hose = data;
+        struct pnv_phb *phb = hose->private_data;
+
+        *val = in_be64(phb->regs + 0xD10);
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(ioda_eeh_dbgfs_ops, ioda_eeh_dbgfs_get,
+                        ioda_eeh_dbgfs_set, "0x%llx\n");
+#endif /* CONFIG_DEBUG_FS */
+
+/**
+ * ioda_eeh_post_init - Chip dependent post initialization
+ * @hose: PCI controller
+ *
+ * The function will be called after eeh PEs and devices
+ * have been built. That means the EEH is ready to supply
+ * service with I/O cache.
+ */
+static int ioda_eeh_post_init(struct pci_controller *hose)
+{
+        struct pnv_phb *phb = hose->private_data;
+        int ret;
+
+        /* Register OPAL event notifier */
+        if (!ioda_eeh_nb_init) {
+                ret = opal_notifier_register(&ioda_eeh_nb);
+                if (ret) {
+                        pr_err("%s: Can't register OPAL event notifier (%d)\n",
+                               __func__, ret);
+                        return ret;
+                }
+
+                ioda_eeh_nb_init = 1;
+        }
+
+        /* FIXME: Enable it for PHB3 later */
+        if (phb->type == PNV_PHB_IODA1) {
+                if (!hub_diag) {
+                        hub_diag = (char *)__get_free_page(GFP_KERNEL |
+                                                           __GFP_ZERO);
+                        if (!hub_diag) {
+                                pr_err("%s: Out of memory !\n",
+                                       __func__);
+                                return -ENOMEM;
+                        }
+                }
+
+#ifdef CONFIG_DEBUG_FS
+                if (phb->dbgfs)
+                        debugfs_create_file("err_injct", 0600,
+                                            phb->dbgfs, hose,
+                                            &ioda_eeh_dbgfs_ops);
+#endif
+
+                phb->eeh_state |= PNV_EEH_STATE_ENABLED;
+        }
+
+        return 0;
+}
+
+/**
+ * ioda_eeh_set_option - Set EEH operation or I/O setting
+ * @pe: EEH PE
+ * @option: options
+ *
+ * Enable or disable EEH option for the indicated PE. The
+ * function also can be used to enable I/O or DMA for the
+ * PE.
+ */
+static int ioda_eeh_set_option(struct eeh_pe *pe, int option)
+{
+        s64 ret;
+        u32 pe_no;
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+
+        /* Check on PE number */
+        if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
+                pr_err("%s: PE address %x out of range [0, %x] "
+                       "on PHB#%x\n",
+                        __func__, pe->addr, phb->ioda.total_pe,
+                        hose->global_number);
+                return -EINVAL;
+        }
+
+        pe_no = pe->addr;
+        switch (option) {
+        case EEH_OPT_DISABLE:
+                ret = -EEXIST;
+                break;
+        case EEH_OPT_ENABLE:
+                ret = 0;
+                break;
+        case EEH_OPT_THAW_MMIO:
+                ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
+                                OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO);
+                if (ret) {
+                        pr_warning("%s: Failed to enable MMIO for "
+                                   "PHB#%x-PE#%x, err=%lld\n",
+                                __func__, hose->global_number, pe_no, ret);
+                        return -EIO;
+                }
+
+                break;
+        case EEH_OPT_THAW_DMA:
+                ret = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
+                                OPAL_EEH_ACTION_CLEAR_FREEZE_DMA);
+                if (ret) {
+                        pr_warning("%s: Failed to enable DMA for "
+                                   "PHB#%x-PE#%x, err=%lld\n",
+                                __func__, hose->global_number, pe_no, ret);
+                        return -EIO;
+                }
+
+                break;
+        default:
+                pr_warning("%s: Invalid option %d\n", __func__, option);
+                return -EINVAL;
+        }
+
+        return ret;
+}
+
+/**
+ * ioda_eeh_get_state - Retrieve the state of PE
+ * @pe: EEH PE
+ *
+ * The PE's state should be retrieved from the PEEV, PEST
+ * IODA tables. Since the OPAL has exported the function
+ * to do it, it'd better to use that.
+ */
+static int ioda_eeh_get_state(struct eeh_pe *pe)
+{
+        s64 ret = 0;
+        u8 fstate;
+        u16 pcierr;
+        u32 pe_no;
+        int result;
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+
+        /*
+         * Sanity check on PE address. The PHB PE address should
+         * be zero.
+         */
+        if (pe->addr < 0 || pe->addr >= phb->ioda.total_pe) {
+                pr_err("%s: PE address %x out of range [0, %x] "
+                       "on PHB#%x\n",
+                       __func__, pe->addr, phb->ioda.total_pe,
+                       hose->global_number);
+                return EEH_STATE_NOT_SUPPORT;
+        }
+
+        /* Retrieve PE status through OPAL */
+        pe_no = pe->addr;
+        ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
+                        &fstate, &pcierr, NULL);
+        if (ret) {
+                pr_err("%s: Failed to get EEH status on "
+                       "PHB#%x-PE#%x\n, err=%lld\n",
+                       __func__, hose->global_number, pe_no, ret);
+                return EEH_STATE_NOT_SUPPORT;
+        }
+
+        /* Check PHB status */
+        if (pe->type & EEH_PE_PHB) {
+                result = 0;
+                result &= ~EEH_STATE_RESET_ACTIVE;
+
+                if (pcierr != OPAL_EEH_PHB_ERROR) {
+                        result |= EEH_STATE_MMIO_ACTIVE;
+                        result |= EEH_STATE_DMA_ACTIVE;
+                        result |= EEH_STATE_MMIO_ENABLED;
+                        result |= EEH_STATE_DMA_ENABLED;
+                }
+
+                return result;
+        }
+
+        /* Parse result out */
+        result = 0;
+        switch (fstate) {
+        case OPAL_EEH_STOPPED_NOT_FROZEN:
+                result &= ~EEH_STATE_RESET_ACTIVE;
+                result |= EEH_STATE_MMIO_ACTIVE;
+                result |= EEH_STATE_DMA_ACTIVE;
+                result |= EEH_STATE_MMIO_ENABLED;
+                result |= EEH_STATE_DMA_ENABLED;
+                break;
+        case OPAL_EEH_STOPPED_MMIO_FREEZE:
+                result &= ~EEH_STATE_RESET_ACTIVE;
+                result |= EEH_STATE_DMA_ACTIVE;
+                result |= EEH_STATE_DMA_ENABLED;
+                break;
+        case OPAL_EEH_STOPPED_DMA_FREEZE:
+                result &= ~EEH_STATE_RESET_ACTIVE;
+                result |= EEH_STATE_MMIO_ACTIVE;
+                result |= EEH_STATE_MMIO_ENABLED;
+                break;
+        case OPAL_EEH_STOPPED_MMIO_DMA_FREEZE:
+                result &= ~EEH_STATE_RESET_ACTIVE;
+                break;
+        case OPAL_EEH_STOPPED_RESET:
+                result |= EEH_STATE_RESET_ACTIVE;
+                break;
+        case OPAL_EEH_STOPPED_TEMP_UNAVAIL:
+                result |= EEH_STATE_UNAVAILABLE;
+                break;
+        case OPAL_EEH_STOPPED_PERM_UNAVAIL:
+                result |= EEH_STATE_NOT_SUPPORT;
+                break;
+        default:
+                pr_warning("%s: Unexpected EEH status 0x%x "
+                           "on PHB#%x-PE#%x\n",
+                           __func__, fstate, hose->global_number, pe_no);
+        }
+
+        return result;
+}
+
+static int ioda_eeh_pe_clear(struct eeh_pe *pe)
+{
+        struct pci_controller *hose;
+        struct pnv_phb *phb;
+        u32 pe_no;
+        u8 fstate;
+        u16 pcierr;
+        s64 ret;
+
+        pe_no = pe->addr;
+        hose = pe->phb;
+        phb = pe->phb->private_data;
+
+        /* Clear the EEH error on the PE */
+        ret = opal_pci_eeh_freeze_clear(phb->opal_id,
+                        pe_no, OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
+        if (ret) {
+                pr_err("%s: Failed to clear EEH error for "
+                       "PHB#%x-PE#%x, err=%lld\n",
+                       __func__, hose->global_number, pe_no, ret);
+                return -EIO;
+        }
+
+        /*
+         * Read the PE state back and verify that the frozen
+         * state has been removed.
+         */
+        ret = opal_pci_eeh_freeze_status(phb->opal_id, pe_no,
+                        &fstate, &pcierr, NULL);
+        if (ret) {
+                pr_err("%s: Failed to get EEH status on "
+                       "PHB#%x-PE#%x\n, err=%lld\n",
+                       __func__, hose->global_number, pe_no, ret);
+                return -EIO;
+        }
+
+        if (fstate != OPAL_EEH_STOPPED_NOT_FROZEN) {
+                pr_err("%s: Frozen state not cleared on "
+                       "PHB#%x-PE#%x, sts=%x\n",
+                       __func__, hose->global_number, pe_no, fstate);
+                return -EIO;
+        }
+
+        return 0;
+}
+
+static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
+{
+        s64 rc = OPAL_HARDWARE;
+
+        while (1) {
+                rc = opal_pci_poll(phb->opal_id);
+                if (rc <= 0)
+                        break;
+
+                msleep(rc);
+        }
+
+        return rc;
+}
+
+static int ioda_eeh_phb_reset(struct pci_controller *hose, int option)
+{
+        struct pnv_phb *phb = hose->private_data;
+        s64 rc = OPAL_HARDWARE;
+
+        pr_debug("%s: Reset PHB#%x, option=%d\n",
+                 __func__, hose->global_number, option);
+
+        /* Issue PHB complete reset request */
+        if (option == EEH_RESET_FUNDAMENTAL ||
+            option == EEH_RESET_HOT)
+                rc = opal_pci_reset(phb->opal_id,
+                                OPAL_PHB_COMPLETE,
+                                OPAL_ASSERT_RESET);
+        else if (option == EEH_RESET_DEACTIVATE)
+                rc = opal_pci_reset(phb->opal_id,
+                                OPAL_PHB_COMPLETE,
+                                OPAL_DEASSERT_RESET);
+        if (rc < 0)
+                goto out;
+
+        /*
+         * Poll state of the PHB until the request is done
+         * successfully.
+         */
+        rc = ioda_eeh_phb_poll(phb);
+out:
+        if (rc != OPAL_SUCCESS)
+                return -EIO;
+
+        return 0;
+}
+
+static int ioda_eeh_root_reset(struct pci_controller *hose, int option)
+{
+        struct pnv_phb *phb = hose->private_data;
+        s64 rc = OPAL_SUCCESS;
+
+        pr_debug("%s: Reset PHB#%x, option=%d\n",
+                 __func__, hose->global_number, option);
+
+        /*
+         * During the reset deassert time, we needn't care
+         * the reset scope because the firmware does nothing
+         * for fundamental or hot reset during deassert phase.
+         */
+        if (option == EEH_RESET_FUNDAMENTAL)
+                rc = opal_pci_reset(phb->opal_id,
+                                OPAL_PCI_FUNDAMENTAL_RESET,
+                                OPAL_ASSERT_RESET);
+        else if (option == EEH_RESET_HOT)
+                rc = opal_pci_reset(phb->opal_id,
+                                OPAL_PCI_HOT_RESET,
+                                OPAL_ASSERT_RESET);
+        else if (option == EEH_RESET_DEACTIVATE)
+                rc = opal_pci_reset(phb->opal_id,
+                                OPAL_PCI_HOT_RESET,
+                                OPAL_DEASSERT_RESET);
+        if (rc < 0)
+                goto out;
+
+        /* Poll state of the PHB until the request is done */
+        rc = ioda_eeh_phb_poll(phb);
+out:
+        if (rc != OPAL_SUCCESS)
+                return -EIO;
+
+        return 0;
+}
+
+static int ioda_eeh_bridge_reset(struct pci_controller *hose,
+                struct pci_dev *dev, int option)
+{
+        u16 ctrl;
+
+        pr_debug("%s: Reset device %04x:%02x:%02x.%01x with option %d\n",
+                 __func__, hose->global_number, dev->bus->number,
+                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), option);
+
+        switch (option) {
+        case EEH_RESET_FUNDAMENTAL:
+        case EEH_RESET_HOT:
+                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
+                ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
+                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+                break;
+        case EEH_RESET_DEACTIVATE:
+                pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
+                ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
+                pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
+                break;
+        }
+
+        return 0;
+}
+
+/**
+ * ioda_eeh_reset - Reset the indicated PE
+ * @pe: EEH PE
+ * @option: reset option
+ *
+ * Do reset on the indicated PE. For PCI bus sensitive PE,
+ * we need to reset the parent p2p bridge. The PHB has to
+ * be reinitialized if the p2p bridge is root bridge. For
+ * PCI device sensitive PE, we will try to reset the device
+ * through FLR. For now, we don't have OPAL APIs to do HARD
+ * reset yet, so all reset would be SOFT (HOT) reset.
+ */
+static int ioda_eeh_reset(struct eeh_pe *pe, int option)
+{
+        struct pci_controller *hose = pe->phb;
+        struct eeh_dev *edev;
+        struct pci_dev *dev;
+        int ret;
+
+        /*
+         * Anyway, we have to clear the problematic state for the
+         * corresponding PE. However, we needn't do it if the PE
+         * is PHB associated. That means the PHB is having fatal
+         * errors and it needs reset. Further more, the AIB interface
+         * isn't reliable any more.
+         */
+        if (!(pe->type & EEH_PE_PHB) &&
+            (option == EEH_RESET_HOT ||
+            option == EEH_RESET_FUNDAMENTAL)) {
+                ret = ioda_eeh_pe_clear(pe);
+                if (ret)
+                        return -EIO;
+        }
+
+        /*
+         * The rules applied to reset, either fundamental or hot reset:
+         *
+         * We always reset the direct upstream bridge of the PE. If the
+         * direct upstream bridge isn't root bridge, we always take hot
+         * reset no matter what option (fundamental or hot) is. Otherwise,
+         * we should do the reset according to the required option.
+         */
+        if (pe->type & EEH_PE_PHB) {
+                ret = ioda_eeh_phb_reset(hose, option);
+        } else {
+                if (pe->type & EEH_PE_DEVICE) {
+                        /*
+                         * If it's device PE, we didn't refer to the parent
+                         * PCI bus yet. So we have to figure it out indirectly.
+                         */
+                        edev = list_first_entry(&pe->edevs,
+                                        struct eeh_dev, list);
+                        dev = eeh_dev_to_pci_dev(edev);
+                        dev = dev->bus->self;
+                } else {
+                        /*
+                         * If it's bus PE, the parent PCI bus is already there
+                         * and just pick it up.
+                         */
+                        dev = pe->bus->self;
+                }
+
+                /*
+                 * Do reset based on the fact that the direct upstream bridge
+                 * is root bridge (port) or not.
+                 */
+                if (dev->bus->number == 0)
+                        ret = ioda_eeh_root_reset(hose, option);
+                else
+                        ret = ioda_eeh_bridge_reset(hose, dev, option);
+        }
+
+        return ret;
+}
+
+/**
+ * ioda_eeh_get_log - Retrieve error log
+ * @pe: EEH PE
+ * @severity: Severity level of the log
+ * @drv_log: buffer to store the log
+ * @len: space of the log buffer
+ *
+ * The function is used to retrieve error log from P7IOC.
+ */
+static int ioda_eeh_get_log(struct eeh_pe *pe, int severity,
+                            char *drv_log, unsigned long len)
+{
+        s64 ret;
+        unsigned long flags;
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+
+        spin_lock_irqsave(&phb->lock, flags);
+
+        ret = opal_pci_get_phb_diag_data2(phb->opal_id,
+                        phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
+        if (ret) {
+                spin_unlock_irqrestore(&phb->lock, flags);
+                pr_warning("%s: Failed to get log for PHB#%x-PE#%x\n",
+                           __func__, hose->global_number, pe->addr);
+                return -EIO;
+        }
+
+        /*
+         * FIXME: We probably need log the error in somewhere.
+         * Lets make it up in future.
+         */
+        /* pr_info("%s", phb->diag.blob); */
+
+        spin_unlock_irqrestore(&phb->lock, flags);
+
+        return 0;
+}
+
+/**
+ * ioda_eeh_configure_bridge - Configure the PCI bridges for the indicated PE
+ * @pe: EEH PE
+ *
+ * For particular PE, it might have included PCI bridges. In order
+ * to make the PE work properly, those PCI bridges should be configured
+ * correctly. However, we need do nothing on P7IOC since the reset
+ * function will do everything that should be covered by the function.
+ */
+static int ioda_eeh_configure_bridge(struct eeh_pe *pe)
+{
+        return 0;
+}
+
+static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
+{
+        /* GEM */
+        pr_info("  GEM XFIR:        %016llx\n", data->gemXfir);
+        pr_info("  GEM RFIR:        %016llx\n", data->gemRfir);
+        pr_info("  GEM RIRQFIR:     %016llx\n", data->gemRirqfir);
+        pr_info("  GEM Mask:        %016llx\n", data->gemMask);
+        pr_info("  GEM RWOF:        %016llx\n", data->gemRwof);
+
+        /* LEM */
+        pr_info("  LEM FIR:         %016llx\n", data->lemFir);
+        pr_info("  LEM Error Mask:  %016llx\n", data->lemErrMask);
+        pr_info("  LEM Action 0:    %016llx\n", data->lemAction0);
+        pr_info("  LEM Action 1:    %016llx\n", data->lemAction1);
+        pr_info("  LEM WOF:         %016llx\n", data->lemWof);
+}
+
+static void ioda_eeh_hub_diag(struct pci_controller *hose)
+{
+        struct pnv_phb *phb = hose->private_data;
+        struct OpalIoP7IOCErrorData *data;
+        long rc;
+
+        data = (struct OpalIoP7IOCErrorData *)ioda_eeh_hub_diag;
+        rc = opal_pci_get_hub_diag_data(phb->hub_id, data, PAGE_SIZE);
+        if (rc != OPAL_SUCCESS) {
+                pr_warning("%s: Failed to get HUB#%llx diag-data (%ld)\n",
+                           __func__, phb->hub_id, rc);
+                return;
+        }
+
+        switch (data->type) {
+        case OPAL_P7IOC_DIAG_TYPE_RGC:
+                pr_info("P7IOC diag-data for RGC\n\n");
+                ioda_eeh_hub_diag_common(data);
+                pr_info("  RGC Status:      %016llx\n", data->rgc.rgcStatus);
+                pr_info("  RGC LDCP:        %016llx\n", data->rgc.rgcLdcp);
+                break;
+        case OPAL_P7IOC_DIAG_TYPE_BI:
+                pr_info("P7IOC diag-data for BI %s\n\n",
+                        data->bi.biDownbound ? "Downbound" : "Upbound");
+                ioda_eeh_hub_diag_common(data);
+                pr_info("  BI LDCP 0:       %016llx\n", data->bi.biLdcp0);
+                pr_info("  BI LDCP 1:       %016llx\n", data->bi.biLdcp1);
+                pr_info("  BI LDCP 2:       %016llx\n", data->bi.biLdcp2);
+                pr_info("  BI Fence Status: %016llx\n", data->bi.biFenceStatus);
+                break;
+        case OPAL_P7IOC_DIAG_TYPE_CI:
+                pr_info("P7IOC diag-data for CI Port %d\\nn",
+                        data->ci.ciPort);
+                ioda_eeh_hub_diag_common(data);
+                pr_info("  CI Port Status:  %016llx\n", data->ci.ciPortStatus);
+                pr_info("  CI Port LDCP:    %016llx\n", data->ci.ciPortLdcp);
+                break;
+        case OPAL_P7IOC_DIAG_TYPE_MISC:
+                pr_info("P7IOC diag-data for MISC\n\n");
+                ioda_eeh_hub_diag_common(data);
+                break;
+        case OPAL_P7IOC_DIAG_TYPE_I2C:
+                pr_info("P7IOC diag-data for I2C\n\n");
+                ioda_eeh_hub_diag_common(data);
+                break;
+        default:
+                pr_warning("%s: Invalid type of HUB#%llx diag-data (%d)\n",
+                           __func__, phb->hub_id, data->type);
+        }
+}
+
+static void ioda_eeh_p7ioc_phb_diag(struct pci_controller *hose,
+                                    struct OpalIoPhbErrorCommon *common)
+{
+        struct OpalIoP7IOCPhbErrorData *data;
+        int i;
+
+        data = (struct OpalIoP7IOCPhbErrorData *)common;
+
+        pr_info("P7IOC PHB#%x Diag-data (Version: %d)\n\n",
+                hose->global_number, common->version);
+
+        pr_info("  brdgCtl:              %08x\n", data->brdgCtl);
+
+        pr_info("  portStatusReg:        %08x\n", data->portStatusReg);
+        pr_info("  rootCmplxStatus:      %08x\n", data->rootCmplxStatus);
+        pr_info("  busAgentStatus:       %08x\n", data->busAgentStatus);
+
+        pr_info("  deviceStatus:         %08x\n", data->deviceStatus);
+        pr_info("  slotStatus:           %08x\n", data->slotStatus);
+        pr_info("  linkStatus:           %08x\n", data->linkStatus);
+        pr_info("  devCmdStatus:         %08x\n", data->devCmdStatus);
+        pr_info("  devSecStatus:         %08x\n", data->devSecStatus);
+
+        pr_info("  rootErrorStatus:      %08x\n", data->rootErrorStatus);
+        pr_info("  uncorrErrorStatus:    %08x\n", data->uncorrErrorStatus);
+        pr_info("  corrErrorStatus:      %08x\n", data->corrErrorStatus);
+        pr_info("  tlpHdr1:              %08x\n", data->tlpHdr1);
+        pr_info("  tlpHdr2:              %08x\n", data->tlpHdr2);
+        pr_info("  tlpHdr3:              %08x\n", data->tlpHdr3);
+        pr_info("  tlpHdr4:              %08x\n", data->tlpHdr4);
+        pr_info("  sourceId:             %08x\n", data->sourceId);
+
+        pr_info("  errorClass:           %016llx\n", data->errorClass);
+        pr_info("  correlator:           %016llx\n", data->correlator);
+        pr_info("  p7iocPlssr:           %016llx\n", data->p7iocPlssr);
+        pr_info("  p7iocCsr:             %016llx\n", data->p7iocCsr);
+        pr_info("  lemFir:               %016llx\n", data->lemFir);
+        pr_info("  lemErrorMask:         %016llx\n", data->lemErrorMask);
+        pr_info("  lemWOF:               %016llx\n", data->lemWOF);
+        pr_info("  phbErrorStatus:       %016llx\n", data->phbErrorStatus);
+        pr_info("  phbFirstErrorStatus:  %016llx\n", data->phbFirstErrorStatus);
+        pr_info("  phbErrorLog0:         %016llx\n", data->phbErrorLog0);
+        pr_info("  phbErrorLog1:         %016llx\n", data->phbErrorLog1);
+        pr_info("  mmioErrorStatus:      %016llx\n", data->mmioErrorStatus);
+        pr_info("  mmioFirstErrorStatus: %016llx\n", data->mmioFirstErrorStatus);
+        pr_info("  mmioErrorLog0:        %016llx\n", data->mmioErrorLog0);
+        pr_info("  mmioErrorLog1:        %016llx\n", data->mmioErrorLog1);
+        pr_info("  dma0ErrorStatus:      %016llx\n", data->dma0ErrorStatus);
+        pr_info("  dma0FirstErrorStatus: %016llx\n", data->dma0FirstErrorStatus);
+        pr_info("  dma0ErrorLog0:        %016llx\n", data->dma0ErrorLog0);
+        pr_info("  dma0ErrorLog1:        %016llx\n", data->dma0ErrorLog1);
+        pr_info("  dma1ErrorStatus:      %016llx\n", data->dma1ErrorStatus);
+        pr_info("  dma1FirstErrorStatus: %016llx\n", data->dma1FirstErrorStatus);
+        pr_info("  dma1ErrorLog0:        %016llx\n", data->dma1ErrorLog0);
+        pr_info("  dma1ErrorLog1:        %016llx\n", data->dma1ErrorLog1);
+
+        for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
+                if ((data->pestA[i] >> 63) == 0 &&
+                    (data->pestB[i] >> 63) == 0)
+                        continue;
+
+                pr_info("  PE[%3d] PESTA:        %016llx\n", i, data->pestA[i]);
+                pr_info("          PESTB:        %016llx\n", data->pestB[i]);
+        }
+}
+
+static void ioda_eeh_phb_diag(struct pci_controller *hose)
+{
+        struct pnv_phb *phb = hose->private_data;
+        struct OpalIoPhbErrorCommon *common;
+        long rc;
+
+        common = (struct OpalIoPhbErrorCommon *)phb->diag.blob;
+        rc = opal_pci_get_phb_diag_data2(phb->opal_id, common, PAGE_SIZE);
+        if (rc != OPAL_SUCCESS) {
+                pr_warning("%s: Failed to get diag-data for PHB#%x (%ld)\n",
+                            __func__, hose->global_number, rc);
+                return;
+        }
+
+        switch (common->ioType) {
+        case OPAL_PHB_ERROR_DATA_TYPE_P7IOC:
+                ioda_eeh_p7ioc_phb_diag(hose, common);
+                break;
+        default:
+                pr_warning("%s: Unrecognized I/O chip %d\n",
+                           __func__, common->ioType);
+        }
+}
+
+static int ioda_eeh_get_phb_pe(struct pci_controller *hose,
+                               struct eeh_pe **pe)
+{
+        struct eeh_pe *phb_pe;
+
+        phb_pe = eeh_phb_pe_get(hose);
+        if (!phb_pe) {
+                pr_warning("%s Can't find PE for PHB#%d\n",
+                           __func__, hose->global_number);
+                return -EEXIST;
+        }
+
+        *pe = phb_pe;
+        return 0;
+}
+
+static int ioda_eeh_get_pe(struct pci_controller *hose,
+                           u16 pe_no, struct eeh_pe **pe)
+{
+        struct eeh_pe *phb_pe, *dev_pe;
+        struct eeh_dev dev;
+
+        /* Find the PHB PE */
+        if (ioda_eeh_get_phb_pe(hose, &phb_pe))
+                return -EEXIST;
+
+        /* Find the PE according to PE# */
+        memset(&dev, 0, sizeof(struct eeh_dev));
+        dev.phb = hose;
+        dev.pe_config_addr = pe_no;
+        dev_pe = eeh_pe_get(&dev);
+        if (!dev_pe) {
+                pr_warning("%s: Can't find PE for PHB#%x - PE#%x\n",
+                           __func__, hose->global_number, pe_no);
+                return -EEXIST;
+        }
+
+        *pe = dev_pe;
+        return 0;
+}
+
+/**
+ * ioda_eeh_next_error - Retrieve next error for EEH core to handle
+ * @pe: The affected PE
+ *
+ * The function is expected to be called by EEH core while it gets
+ * special EEH event (without binding PE). The function calls to
+ * OPAL APIs for next error to handle. The informational error is
+ * handled internally by platform. However, the dead IOC, dead PHB,
+ * fenced PHB and frozen PE should be handled by EEH core eventually.
+ */
+static int ioda_eeh_next_error(struct eeh_pe **pe)
+{
+        struct pci_controller *hose, *tmp;
+        struct pnv_phb *phb;
+        u64 frozen_pe_no;
+        u16 err_type, severity;
+        long rc;
+        int ret = 1;
+
+        /*
+         * While running here, it's safe to purge the event queue.
+         * And we should keep the cached OPAL notifier event sychronized
+         * between the kernel and firmware.
+         */
+        eeh_remove_event(NULL);
+        opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
+
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                /*
+                 * If the subordinate PCI buses of the PHB has been
+                 * removed, we needn't take care of it any more.
+                 */
+                phb = hose->private_data;
+                if (phb->eeh_state & PNV_EEH_STATE_REMOVED)
+                        continue;
+
+                rc = opal_pci_next_error(phb->opal_id,
+                                &frozen_pe_no, &err_type, &severity);
+
+                /* If OPAL API returns error, we needn't proceed */
+                if (rc != OPAL_SUCCESS) {
+                        IODA_EEH_DBG("%s: Invalid return value on "
+                                     "PHB#%x (0x%lx) from opal_pci_next_error",
+                                     __func__, hose->global_number, rc);
+                        continue;
+                }
+
+                /* If the PHB doesn't have error, stop processing */
+                if (err_type == OPAL_EEH_NO_ERROR ||
+                    severity == OPAL_EEH_SEV_NO_ERROR) {
+                        IODA_EEH_DBG("%s: No error found on PHB#%x\n",
+                                     __func__, hose->global_number);
+                        continue;
+                }
+
+                /*
+                 * Processing the error. We're expecting the error with
+                 * highest priority reported upon multiple errors on the
+                 * specific PHB.
+                 */
+                IODA_EEH_DBG("%s: Error (%d, %d, %d) on PHB#%x\n",
+                        err_type, severity, pe_no, hose->global_number);
+                switch (err_type) {
+                case OPAL_EEH_IOC_ERROR:
+                        if (severity == OPAL_EEH_SEV_IOC_DEAD) {
+                                list_for_each_entry_safe(hose, tmp,
+                                                &hose_list, list_node) {
+                                        phb = hose->private_data;
+                                        phb->eeh_state |= PNV_EEH_STATE_REMOVED;
+                                }
+
+                                pr_err("EEH: dead IOC detected\n");
+                                ret = 4;
+                                goto out;
+                        } else if (severity == OPAL_EEH_SEV_INF) {
+                                pr_info("EEH: IOC informative error "
+                                        "detected\n");
+                                ioda_eeh_hub_diag(hose);
+                        }
+
+                        break;
+                case OPAL_EEH_PHB_ERROR:
+                        if (severity == OPAL_EEH_SEV_PHB_DEAD) {
+                                if (ioda_eeh_get_phb_pe(hose, pe))
+                                        break;
+
+                                pr_err("EEH: dead PHB#%x detected\n",
+                                        hose->global_number);
+                                phb->eeh_state |= PNV_EEH_STATE_REMOVED;
+                                ret = 3;
+                                goto out;
+                        } else if (severity == OPAL_EEH_SEV_PHB_FENCED) {
+                                if (ioda_eeh_get_phb_pe(hose, pe))
+                                        break;
+
+                                pr_err("EEH: fenced PHB#%x detected\n",
+                                        hose->global_number);
+                                ret = 2;
+                                goto out;
+                        } else if (severity == OPAL_EEH_SEV_INF) {
+                                pr_info("EEH: PHB#%x informative error "
+                                        "detected\n",
+                                        hose->global_number);
+                                ioda_eeh_phb_diag(hose);
+                        }
+
+                        break;
+                case OPAL_EEH_PE_ERROR:
+                        if (ioda_eeh_get_pe(hose, frozen_pe_no, pe))
+                                break;
+
+                        pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
+                                (*pe)->addr, (*pe)->phb->global_number);
+                        ret = 1;
+                        goto out;
+                }
+        }
+
+        ret = 0;
+out:
+        return ret;
+}
+
+struct pnv_eeh_ops ioda_eeh_ops = {
+        .post_init              = ioda_eeh_post_init,
+        .set_option             = ioda_eeh_set_option,
+        .get_state              = ioda_eeh_get_state,
+        .reset                  = ioda_eeh_reset,
+        .get_log                = ioda_eeh_get_log,
+        .configure_bridge       = ioda_eeh_configure_bridge,
+        .next_error             = ioda_eeh_next_error
+};
diff --git a/arch/powerpc/platforms/powernv/eeh-powernv.c b/arch/powerpc/platforms/powernv/eeh-powernv.c
new file mode 100644
index 000000000000..969cce73055a
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/eeh-powernv.c
@@ -0,0 +1,379 @@
+/*
+ * The file intends to implement the platform dependent EEH operations on
+ * powernv platform. Actually, the powernv was created in order to fully
+ * hypervisor support.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/atomic.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/proc_fs.h>
+#include <linux/rbtree.h>
+#include <linux/sched.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+
+#include <asm/eeh.h>
+#include <asm/eeh_event.h>
+#include <asm/firmware.h>
+#include <asm/io.h>
+#include <asm/iommu.h>
+#include <asm/machdep.h>
+#include <asm/msi_bitmap.h>
+#include <asm/opal.h>
+#include <asm/ppc-pci.h>
+
+#include "powernv.h"
+#include "pci.h"
+
+/**
+ * powernv_eeh_init - EEH platform dependent initialization
+ *
+ * EEH platform dependent initialization on powernv
+ */
+static int powernv_eeh_init(void)
+{
+        /* We require OPALv3 */
+        if (!firmware_has_feature(FW_FEATURE_OPALv3)) {
+                pr_warning("%s: OPALv3 is required !\n", __func__);
+                return -EINVAL;
+        }
+
+        /* Set EEH probe mode */
+        eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
+
+        return 0;
+}
+
+/**
+ * powernv_eeh_post_init - EEH platform dependent post initialization
+ *
+ * EEH platform dependent post initialization on powernv. When
+ * the function is called, the EEH PEs and devices should have
+ * been built. If the I/O cache staff has been built, EEH is
+ * ready to supply service.
+ */
+static int powernv_eeh_post_init(void)
+{
+        struct pci_controller *hose;
+        struct pnv_phb *phb;
+        int ret = 0;
+
+        list_for_each_entry(hose, &hose_list, list_node) {
+                phb = hose->private_data;
+
+                if (phb->eeh_ops && phb->eeh_ops->post_init) {
+                        ret = phb->eeh_ops->post_init(hose);
+                        if (ret)
+                                break;
+                }
+        }
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_dev_probe - Do probe on PCI device
+ * @dev: PCI device
+ * @flag: unused
+ *
+ * When EEH module is installed during system boot, all PCI devices
+ * are checked one by one to see if it supports EEH. The function
+ * is introduced for the purpose. By default, EEH has been enabled
+ * on all PCI devices. That's to say, we only need do necessary
+ * initialization on the corresponding eeh device and create PE
+ * accordingly.
+ *
+ * It's notable that's unsafe to retrieve the EEH device through
+ * the corresponding PCI device. During the PCI device hotplug, which
+ * was possiblly triggered by EEH core, the binding between EEH device
+ * and the PCI device isn't built yet.
+ */
+static int powernv_eeh_dev_probe(struct pci_dev *dev, void *flag)
+{
+        struct pci_controller *hose = pci_bus_to_host(dev->bus);
+        struct pnv_phb *phb = hose->private_data;
+        struct device_node *dn = pci_device_to_OF_node(dev);
+        struct eeh_dev *edev = of_node_to_eeh_dev(dn);
+
+        /*
+         * When probing the root bridge, which doesn't have any
+         * subordinate PCI devices. We don't have OF node for
+         * the root bridge. So it's not reasonable to continue
+         * the probing.
+         */
+        if (!dn || !edev)
+                return 0;
+
+        /* Skip for PCI-ISA bridge */
+        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
+                return 0;
+
+        /* Initialize eeh device */
+        edev->class_code        = dev->class;
+        edev->mode              = 0;
+        edev->config_addr       = ((dev->bus->number << 8) | dev->devfn);
+        edev->pe_config_addr    = phb->bdfn_to_pe(phb, dev->bus, dev->devfn & 0xff);
+
+        /* Create PE */
+        eeh_add_to_parent_pe(edev);
+
+        /*
+         * Enable EEH explicitly so that we will do EEH check
+         * while accessing I/O stuff
+         *
+         * FIXME: Enable that for PHB3 later
+         */
+        if (phb->type == PNV_PHB_IODA1)
+                eeh_subsystem_enabled = 1;
+
+        /* Save memory bars */
+        eeh_save_bars(edev);
+
+        return 0;
+}
+
+/**
+ * powernv_eeh_set_option - Initialize EEH or MMIO/DMA reenable
+ * @pe: EEH PE
+ * @option: operation to be issued
+ *
+ * The function is used to control the EEH functionality globally.
+ * Currently, following options are support according to PAPR:
+ * Enable EEH, Disable EEH, Enable MMIO and Enable DMA
+ */
+static int powernv_eeh_set_option(struct eeh_pe *pe, int option)
+{
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+        int ret = -EEXIST;
+
+        /*
+         * What we need do is pass it down for hardware
+         * implementation to handle it.
+         */
+        if (phb->eeh_ops && phb->eeh_ops->set_option)
+                ret = phb->eeh_ops->set_option(pe, option);
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_get_pe_addr - Retrieve PE address
+ * @pe: EEH PE
+ *
+ * Retrieve the PE address according to the given tranditional
+ * PCI BDF (Bus/Device/Function) address.
+ */
+static int powernv_eeh_get_pe_addr(struct eeh_pe *pe)
+{
+        return pe->addr;
+}
+
+/**
+ * powernv_eeh_get_state - Retrieve PE state
+ * @pe: EEH PE
+ * @delay: delay while PE state is temporarily unavailable
+ *
+ * Retrieve the state of the specified PE. For IODA-compitable
+ * platform, it should be retrieved from IODA table. Therefore,
+ * we prefer passing down to hardware implementation to handle
+ * it.
+ */
+static int powernv_eeh_get_state(struct eeh_pe *pe, int *delay)
+{
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+        int ret = EEH_STATE_NOT_SUPPORT;
+
+        if (phb->eeh_ops && phb->eeh_ops->get_state) {
+                ret = phb->eeh_ops->get_state(pe);
+
+                /*
+                 * If the PE state is temporarily unavailable,
+                 * to inform the EEH core delay for default
+                 * period (1 second)
+                 */
+                if (delay) {
+                        *delay = 0;
+                        if (ret & EEH_STATE_UNAVAILABLE)
+                                *delay = 1000;
+                }
+        }
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_reset - Reset the specified PE
+ * @pe: EEH PE
+ * @option: reset option
+ *
+ * Reset the specified PE
+ */
+static int powernv_eeh_reset(struct eeh_pe *pe, int option)
+{
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+        int ret = -EEXIST;
+
+        if (phb->eeh_ops && phb->eeh_ops->reset)
+                ret = phb->eeh_ops->reset(pe, option);
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_wait_state - Wait for PE state
+ * @pe: EEH PE
+ * @max_wait: maximal period in microsecond
+ *
+ * Wait for the state of associated PE. It might take some time
+ * to retrieve the PE's state.
+ */
+static int powernv_eeh_wait_state(struct eeh_pe *pe, int max_wait)
+{
+        int ret;
+        int mwait;
+
+        while (1) {
+                ret = powernv_eeh_get_state(pe, &mwait);
+
+                /*
+                 * If the PE's state is temporarily unavailable,
+                 * we have to wait for the specified time. Otherwise,
+                 * the PE's state will be returned immediately.
+                 */
+                if (ret != EEH_STATE_UNAVAILABLE)
+                        return ret;
+
+                max_wait -= mwait;
+                if (max_wait <= 0) {
+                        pr_warning("%s: Timeout getting PE#%x's state (%d)\n",
+                                   __func__, pe->addr, max_wait);
+                        return EEH_STATE_NOT_SUPPORT;
+                }
+
+                msleep(mwait);
+        }
+
+        return EEH_STATE_NOT_SUPPORT;
+}
+
+/**
+ * powernv_eeh_get_log - Retrieve error log
+ * @pe: EEH PE
+ * @severity: temporary or permanent error log
+ * @drv_log: driver log to be combined with retrieved error log
+ * @len: length of driver log
+ *
+ * Retrieve the temporary or permanent error from the PE.
+ */
+static int powernv_eeh_get_log(struct eeh_pe *pe, int severity,
+                        char *drv_log, unsigned long len)
+{
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+        int ret = -EEXIST;
+
+        if (phb->eeh_ops && phb->eeh_ops->get_log)
+                ret = phb->eeh_ops->get_log(pe, severity, drv_log, len);
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_configure_bridge - Configure PCI bridges in the indicated PE
+ * @pe: EEH PE
+ *
+ * The function will be called to reconfigure the bridges included
+ * in the specified PE so that the mulfunctional PE would be recovered
+ * again.
+ */
+static int powernv_eeh_configure_bridge(struct eeh_pe *pe)
+{
+        struct pci_controller *hose = pe->phb;
+        struct pnv_phb *phb = hose->private_data;
+        int ret = 0;
+
+        if (phb->eeh_ops && phb->eeh_ops->configure_bridge)
+                ret = phb->eeh_ops->configure_bridge(pe);
+
+        return ret;
+}
+
+/**
+ * powernv_eeh_next_error - Retrieve next EEH error to handle
+ * @pe: Affected PE
+ *
+ * Using OPAL API, to retrieve next EEH error for EEH core to handle
+ */
+static int powernv_eeh_next_error(struct eeh_pe **pe)
+{
+        struct pci_controller *hose;
+        struct pnv_phb *phb = NULL;
+
+        list_for_each_entry(hose, &hose_list, list_node) {
+                phb = hose->private_data;
+                break;
+        }
+
+        if (phb && phb->eeh_ops->next_error)
+                return phb->eeh_ops->next_error(pe);
+
+        return -EEXIST;
+}
+
+static struct eeh_ops powernv_eeh_ops = {
+        .name                   = "powernv",
+        .init                   = powernv_eeh_init,
+        .post_init              = powernv_eeh_post_init,
+        .of_probe               = NULL,
+        .dev_probe              = powernv_eeh_dev_probe,
+        .set_option             = powernv_eeh_set_option,
+        .get_pe_addr            = powernv_eeh_get_pe_addr,
+        .get_state              = powernv_eeh_get_state,
+        .reset                  = powernv_eeh_reset,
+        .wait_state             = powernv_eeh_wait_state,
+        .get_log                = powernv_eeh_get_log,
+        .configure_bridge       = powernv_eeh_configure_bridge,
+        .read_config            = pnv_pci_cfg_read,
+        .write_config           = pnv_pci_cfg_write,
+        .next_error             = powernv_eeh_next_error
+};
+
+/**
+ * eeh_powernv_init - Register platform dependent EEH operations
+ *
+ * EEH initialization on powernv platform. This function should be
+ * called before any EEH related functions.
+ */
+static int __init eeh_powernv_init(void)
+{
+        int ret = -EINVAL;
+
+        if (!machine_is(powernv))
+                return ret;
+
+        ret = eeh_ops_register(&powernv_eeh_ops);
+        if (!ret)
+                pr_info("EEH: PowerNV platform initialized\n");
+        else
+                pr_info("EEH: Failed to initialize PowerNV platform (%d)\n", ret);
+
+        return ret;
+}
+
+early_initcall(eeh_powernv_init);
diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 6fabe92eafb6..e88863ffb135 100644
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -107,4 +107,7 @@ OPAL_CALL(opal_pci_mask_pe_error,		OPAL_PCI_MASK_PE_ERROR);
 OPAL_CALL(opal_set_slot_led_status,             OPAL_SET_SLOT_LED_STATUS);
 OPAL_CALL(opal_get_epow_status,                 OPAL_GET_EPOW_STATUS);
 OPAL_CALL(opal_set_system_attention_led,        OPAL_SET_SYSTEM_ATTENTION_LED);
+OPAL_CALL(opal_pci_next_error,                  OPAL_PCI_NEXT_ERROR);
+OPAL_CALL(opal_pci_poll,                        OPAL_PCI_POLL);
 OPAL_CALL(opal_pci_msi_eoi,                     OPAL_PCI_MSI_EOI);
+OPAL_CALL(opal_pci_get_phb_diag_data2,          OPAL_PCI_GET_PHB_DIAG_DATA2);
diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 628c564ceadb..106301fd2fa5 100644
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -15,6 +15,7 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/interrupt.h>
+#include <linux/notifier.h>
 #include <linux/slab.h>
 #include <asm/opal.h>
 #include <asm/firmware.h>
@@ -31,6 +32,10 @@ static DEFINE_SPINLOCK(opal_write_lock);
 extern u64 opal_mc_secondary_handler[];
 static unsigned int *opal_irqs;
 static unsigned int opal_irq_count;
+static ATOMIC_NOTIFIER_HEAD(opal_notifier_head);
+static DEFINE_SPINLOCK(opal_notifier_lock);
+static uint64_t last_notified_mask = 0x0ul;
+static atomic_t opal_notifier_hold = ATOMIC_INIT(0);
 
 int __init early_init_dt_scan_opal(unsigned long node,
                                    const char *uname, int depth, void *data)
@@ -95,6 +100,68 @@ static int __init opal_register_exception_handlers(void)
 
 early_initcall(opal_register_exception_handlers);
 
+int opal_notifier_register(struct notifier_block *nb)
+{
+        if (!nb) {
+                pr_warning("%s: Invalid argument (%p)\n",
+                           __func__, nb);
+                return -EINVAL;
+        }
+
+        atomic_notifier_chain_register(&opal_notifier_head, nb);
+        return 0;
+}
+
+static void opal_do_notifier(uint64_t events)
+{
+        unsigned long flags;
+        uint64_t changed_mask;
+
+        if (atomic_read(&opal_notifier_hold))
+                return;
+
+        spin_lock_irqsave(&opal_notifier_lock, flags);
+        changed_mask = last_notified_mask ^ events;
+        last_notified_mask = events;
+        spin_unlock_irqrestore(&opal_notifier_lock, flags);
+
+        /*
+         * We feed with the event bits and changed bits for
+         * enough information to the callback.
+         */
+        atomic_notifier_call_chain(&opal_notifier_head,
+                                   events, (void *)changed_mask);
+}
+
+void opal_notifier_update_evt(uint64_t evt_mask,
+                              uint64_t evt_val)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&opal_notifier_lock, flags);
+        last_notified_mask &= ~evt_mask;
+        last_notified_mask |= evt_val;
+        spin_unlock_irqrestore(&opal_notifier_lock, flags);
+}
+
+void opal_notifier_enable(void)
+{
+        int64_t rc;
+        uint64_t evt = 0;
+
+        atomic_set(&opal_notifier_hold, 0);
+
+        /* Process pending events */
+        rc = opal_poll_events(&evt);
+        if (rc == OPAL_SUCCESS && evt)
+                opal_do_notifier(evt);
+}
+
+void opal_notifier_disable(void)
+{
+        atomic_set(&opal_notifier_hold, 1);
+}
+
 int opal_get_chars(uint32_t vtermno, char *buf, int count)
 {
         s64 len, rc;
@@ -297,7 +364,7 @@ static irqreturn_t opal_interrupt(int irq, void *data)
 
         opal_handle_interrupt(virq_to_hw(irq), &events);
 
-        /* XXX TODO: Do something with the events */
+        opal_do_notifier(events);
 
         return IRQ_HANDLED;
 }
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index 9c9d15e4cdf2..49b57b9f835d 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/string.h>
 #include <linux/init.h>
@@ -32,6 +33,7 @@
 #include <asm/iommu.h>
 #include <asm/tce.h>
 #include <asm/xics.h>
+#include <asm/debug.h>
 
 #include "powernv.h"
 #include "pci.h"
@@ -441,6 +443,17 @@ static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev
         set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 }
 
+static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
+{
+        struct pci_dev *dev;
+
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                set_iommu_table_base(&dev->dev, &pe->tce32_table);
+                if (dev->subordinate)
+                        pnv_ioda_setup_bus_dma(pe, dev->subordinate);
+        }
+}
+
 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
                                          u64 *startp, u64 *endp)
 {
@@ -595,6 +608,12 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
                                TCE_PCI_SWINV_PAIR;
         }
         iommu_init_table(tbl, phb->hose->node);
+        iommu_register_group(tbl, pci_domain_nr(pe->pbus), pe->pe_number);
+
+        if (pe->pdev)
+                set_iommu_table_base(&pe->pdev->dev, tbl);
+        else
+                pnv_ioda_setup_bus_dma(pe, pe->pbus);
 
         return;
  fail:
@@ -667,6 +686,11 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
         }
         iommu_init_table(tbl, phb->hose->node);
 
+        if (pe->pdev)
+                set_iommu_table_base(&pe->pdev->dev, tbl);
+        else
+                pnv_ioda_setup_bus_dma(pe, pe->pbus);
+
         return;
 fail:
         if (pe->tce32_seg >= 0)
@@ -968,11 +992,38 @@ static void pnv_pci_ioda_setup_DMA(void)
         }
 }
 
+static void pnv_pci_ioda_create_dbgfs(void)
+{
+#ifdef CONFIG_DEBUG_FS
+        struct pci_controller *hose, *tmp;
+        struct pnv_phb *phb;
+        char name[16];
+
+        list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
+                phb = hose->private_data;
+
+                sprintf(name, "PCI%04x", hose->global_number);
+                phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root);
+                if (!phb->dbgfs)
+                        pr_warning("%s: Error on creating debugfs on PHB#%x\n",
+                                __func__, hose->global_number);
+        }
+#endif /* CONFIG_DEBUG_FS */
+}
+
 static void pnv_pci_ioda_fixup(void)
 {
         pnv_pci_ioda_setup_PEs();
         pnv_pci_ioda_setup_seg();
         pnv_pci_ioda_setup_DMA();
+
+        pnv_pci_ioda_create_dbgfs();
+
+#ifdef CONFIG_EEH
+        eeh_probe_mode_set(EEH_PROBE_MODE_DEV);
+        eeh_addr_cache_build();
+        eeh_init();
+#endif
 }
 
 /*
@@ -1049,7 +1100,8 @@ static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
                        OPAL_ASSERT_RESET);
 }
 
-void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
+void __init pnv_pci_init_ioda_phb(struct device_node *np,
+                                  u64 hub_id, int ioda_type)
 {
         struct pci_controller *hose;
         static int primary = 1;
@@ -1087,6 +1139,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
         hose->first_busno = 0;
         hose->last_busno = 0xff;
         hose->private_data = phb;
+        phb->hub_id = hub_id;
         phb->opal_id = phb_id;
         phb->type = ioda_type;
 
@@ -1172,6 +1225,9 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
                 phb->ioda.io_size, phb->ioda.io_segsize);
 
         phb->hose->ops = &pnv_pci_ops;
+#ifdef CONFIG_EEH
+        phb->eeh_ops = &ioda_eeh_ops;
+#endif
 
         /* Setup RID -> PE mapping function */
         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
@@ -1212,7 +1268,7 @@ void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
 
 void pnv_pci_init_ioda2_phb(struct device_node *np)
 {
-        pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2);
+        pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2);
 }
 
 void __init pnv_pci_init_ioda_hub(struct device_node *np)
@@ -1235,6 +1291,6 @@ void __init pnv_pci_init_ioda_hub(struct device_node *np)
         for_each_child_of_node(np, phbn) {
                 /* Look for IODA1 PHBs */
                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
-                        pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1);
+                        pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1);
         }
 }
diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
index 92b37a0186c9..b68db6325c1b 100644
--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
@@ -86,13 +86,16 @@ static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
 static void pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
                                          struct pci_dev *pdev)
 {
-        if (phb->p5ioc2.iommu_table.it_map == NULL)
+        if (phb->p5ioc2.iommu_table.it_map == NULL) {
                 iommu_init_table(&phb->p5ioc2.iommu_table, phb->hose->node);
+                iommu_register_group(&phb->p5ioc2.iommu_table,
+                                pci_domain_nr(phb->hose->bus), phb->opal_id);
+        }
 
         set_iommu_table_base(&pdev->dev, &phb->p5ioc2.iommu_table);
 }
 
-static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
+static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
                                            void *tce_mem, u64 tce_size)
 {
         struct pnv_phb *phb;
@@ -133,6 +136,7 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
         phb->hose->first_busno = 0;
         phb->hose->last_busno = 0xff;
         phb->hose->private_data = phb;
+        phb->hub_id = hub_id;
         phb->opal_id = phb_id;
         phb->type = PNV_PHB_P5IOC2;
         phb->model = PNV_PHB_MODEL_P5IOC2;
@@ -226,7 +230,8 @@ void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
         for_each_child_of_node(np, phbn) {
                 if (of_device_is_compatible(phbn, "ibm,p5ioc2-pcix") ||
                     of_device_is_compatible(phbn, "ibm,p5ioc2-pciex")) {
-                        pnv_pci_init_p5ioc2_phb(phbn, tce_mem, tce_per_phb);
+                        pnv_pci_init_p5ioc2_phb(phbn, hub_id,
+                                        tce_mem, tce_per_phb);
                         tce_mem += tce_per_phb;
                 }
         }
diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
index 277343cc6a3d..a28d3b5e6393 100644
--- a/arch/powerpc/platforms/powernv/pci.c
+++ b/arch/powerpc/platforms/powernv/pci.c
@@ -20,6 +20,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/msi.h>
+#include <linux/iommu.h>
 
 #include <asm/sections.h>
 #include <asm/io.h>
@@ -32,6 +33,8 @@
 #include <asm/iommu.h>
 #include <asm/tce.h>
 #include <asm/firmware.h>
+#include <asm/eeh_event.h>
+#include <asm/eeh.h>
 
 #include "powernv.h"
 #include "pci.h"
@@ -202,7 +205,8 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
 
         spin_lock_irqsave(&phb->lock, flags);
 
-        rc = opal_pci_get_phb_diag_data(phb->opal_id, phb->diag.blob, PNV_PCI_DIAG_BUF_SIZE);
+        rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
+                                         PNV_PCI_DIAG_BUF_SIZE);
         has_diag = (rc == OPAL_SUCCESS);
 
         rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
@@ -227,43 +231,50 @@ static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
         spin_unlock_irqrestore(&phb->lock, flags);
 }
 
-static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
-                                     u32 bdfn)
+static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
+                                     struct device_node *dn)
 {
         s64     rc;
         u8      fstate;
         u16     pcierr;
         u32     pe_no;
 
-        /* Get PE# if we support IODA */
-        pe_no = phb->bdfn_to_pe ? phb->bdfn_to_pe(phb, bus, bdfn & 0xff) : 0;
+        /*
+         * Get the PE#. During the PCI probe stage, we might not
+         * setup that yet. So all ER errors should be mapped to
+         * PE#0
+         */
+        pe_no = PCI_DN(dn)->pe_number;
+        if (pe_no == IODA_INVALID_PE)
+                pe_no = 0;
 
         /* Read freeze status */
         rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
                                         NULL);
         if (rc) {
-                pr_warning("PCI %d: Failed to read EEH status for PE#%d,"
-                           " err %lld\n", phb->hose->global_number, pe_no, rc);
+                pr_warning("%s: Can't read EEH status (PE#%d) for "
+                           "%s, err %lld\n",
+                           __func__, pe_no, dn->full_name, rc);
                 return;
         }
-        cfg_dbg(" -> EEH check, bdfn=%04x PE%d fstate=%x\n",
-                bdfn, pe_no, fstate);
+        cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
+                (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
+                pe_no, fstate);
         if (fstate != 0)
                 pnv_pci_handle_eeh_config(phb, pe_no);
 }
 
-static int pnv_pci_read_config(struct pci_bus *bus,
-                               unsigned int devfn,
-                               int where, int size, u32 *val)
+int pnv_pci_cfg_read(struct device_node *dn,
+                     int where, int size, u32 *val)
 {
-        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pnv_phb *phb = hose->private_data;
-        u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
+        struct pci_dn *pdn = PCI_DN(dn);
+        struct pnv_phb *phb = pdn->phb->private_data;
+        u32 bdfn = (pdn->busno << 8) | pdn->devfn;
+#ifdef CONFIG_EEH
+        struct eeh_pe *phb_pe = NULL;
+#endif
         s64 rc;
 
-        if (hose == NULL)
-                return PCIBIOS_DEVICE_NOT_FOUND;
-
         switch (size) {
         case 1: {
                 u8 v8;
@@ -287,28 +298,43 @@ static int pnv_pci_read_config(struct pci_bus *bus,
         default:
                 return PCIBIOS_FUNC_NOT_SUPPORTED;
         }
-        cfg_dbg("pnv_pci_read_config bus: %x devfn: %x +%x/%x -> %08x\n",
-                bus->number, devfn, where, size, *val);
-
-        /* Check if the PHB got frozen due to an error (no response) */
-        pnv_pci_config_check_eeh(phb, bus, bdfn);
+        cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
+                __func__, pdn->busno, pdn->devfn, where, size, *val);
+
+        /*
+         * Check if the specified PE has been put into frozen
+         * state. On the other hand, we needn't do that while
+         * the PHB has been put into frozen state because of
+         * PHB-fatal errors.
+         */
+#ifdef CONFIG_EEH
+        phb_pe = eeh_phb_pe_get(pdn->phb);
+        if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
+                return PCIBIOS_SUCCESSFUL;
+
+        if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
+                if (*val == EEH_IO_ERROR_VALUE(size) &&
+                    eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
+                        return PCIBIOS_DEVICE_NOT_FOUND;
+        } else {
+                pnv_pci_config_check_eeh(phb, dn);
+        }
+#else
+        pnv_pci_config_check_eeh(phb, dn);
+#endif
 
         return PCIBIOS_SUCCESSFUL;
 }
 
-static int pnv_pci_write_config(struct pci_bus *bus,
-                                unsigned int devfn,
-                                int where, int size, u32 val)
+int pnv_pci_cfg_write(struct device_node *dn,
+                      int where, int size, u32 val)
 {
-        struct pci_controller *hose = pci_bus_to_host(bus);
-        struct pnv_phb *phb = hose->private_data;
-        u32 bdfn = (((uint64_t)bus->number) << 8) | devfn;
-
-        if (hose == NULL)
-                return PCIBIOS_DEVICE_NOT_FOUND;
+        struct pci_dn *pdn = PCI_DN(dn);
+        struct pnv_phb *phb = pdn->phb->private_data;
+        u32 bdfn = (pdn->busno << 8) | pdn->devfn;
 
-        cfg_dbg("pnv_pci_write_config bus: %x devfn: %x +%x/%x -> %08x\n",
-                bus->number, devfn, where, size, val);
+        cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
+                pdn->busno, pdn->devfn, where, size, val);
         switch (size) {
         case 1:
                 opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
@@ -322,14 +348,54 @@ static int pnv_pci_write_config(struct pci_bus *bus,
         default:
                 return PCIBIOS_FUNC_NOT_SUPPORTED;
         }
+
         /* Check if the PHB got frozen due to an error (no response) */
-        pnv_pci_config_check_eeh(phb, bus, bdfn);
+#ifdef CONFIG_EEH
+        if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
+                pnv_pci_config_check_eeh(phb, dn);
+#else
+        pnv_pci_config_check_eeh(phb, dn);
+#endif
 
         return PCIBIOS_SUCCESSFUL;
 }
 
+static int pnv_pci_read_config(struct pci_bus *bus,
+                               unsigned int devfn,
+                               int where, int size, u32 *val)
+{
+        struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
+        struct pci_dn *pdn;
+
+        for (dn = busdn->child; dn; dn = dn->sibling) {
+                pdn = PCI_DN(dn);
+                if (pdn && pdn->devfn == devfn)
+                        return pnv_pci_cfg_read(dn, where, size, val);
+        }
+
+        *val = 0xFFFFFFFF;
+        return PCIBIOS_DEVICE_NOT_FOUND;
+
+}
+
+static int pnv_pci_write_config(struct pci_bus *bus,
+                                unsigned int devfn,
+                                int where, int size, u32 val)
+{
+        struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
+        struct pci_dn *pdn;
+
+        for (dn = busdn->child; dn; dn = dn->sibling) {
+                pdn = PCI_DN(dn);
+                if (pdn && pdn->devfn == devfn)
+                        return pnv_pci_cfg_write(dn, where, size, val);
+        }
+
+        return PCIBIOS_DEVICE_NOT_FOUND;
+}
+
 struct pci_ops pnv_pci_ops = {
-        .read = pnv_pci_read_config,
+        .read  = pnv_pci_read_config,
         .write = pnv_pci_write_config,
 };
 
@@ -412,6 +478,7 @@ static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
         pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
                                   be32_to_cpup(sizep), 0);
         iommu_init_table(tbl, hose->node);
+        iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
 
         /* Deal with SW invalidated TCEs when needed (BML way) */
         swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 25d76c4df50b..d633c64e05a1 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -66,15 +66,43 @@ struct pnv_ioda_pe {
         struct list_head        list;
 };
 
+/* IOC dependent EEH operations */
+#ifdef CONFIG_EEH
+struct pnv_eeh_ops {
+        int (*post_init)(struct pci_controller *hose);
+        int (*set_option)(struct eeh_pe *pe, int option);
+        int (*get_state)(struct eeh_pe *pe);
+        int (*reset)(struct eeh_pe *pe, int option);
+        int (*get_log)(struct eeh_pe *pe, int severity,
+                       char *drv_log, unsigned long len);
+        int (*configure_bridge)(struct eeh_pe *pe);
+        int (*next_error)(struct eeh_pe **pe);
+};
+
+#define PNV_EEH_STATE_ENABLED   (1 << 0)        /* EEH enabled  */
+#define PNV_EEH_STATE_REMOVED   (1 << 1)        /* PHB removed  */
+
+#endif /* CONFIG_EEH */
+
 struct pnv_phb {
         struct pci_controller   *hose;
         enum pnv_phb_type       type;
         enum pnv_phb_model      model;
+        u64                     hub_id;
         u64                     opal_id;
         void __iomem            *regs;
         int                     initialized;
         spinlock_t              lock;
 
+#ifdef CONFIG_EEH
+        struct pnv_eeh_ops      *eeh_ops;
+        int                     eeh_state;
+#endif
+
+#ifdef CONFIG_DEBUG_FS
+        struct dentry           *dbgfs;
+#endif
+
 #ifdef CONFIG_PCI_MSI
         unsigned int            msi_base;
         unsigned int            msi32_support;
@@ -150,7 +178,14 @@ struct pnv_phb {
 };
 
 extern struct pci_ops pnv_pci_ops;
+#ifdef CONFIG_EEH
+extern struct pnv_eeh_ops ioda_eeh_ops;
+#endif
 
+int pnv_pci_cfg_read(struct device_node *dn,
+                     int where, int size, u32 *val);
+int pnv_pci_cfg_write(struct device_node *dn,
+                      int where, int size, u32 val);
 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                       void *tce_mem, u64 tce_size,
                                       u64 dma_offset);
diff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c
index d4459bfc92f7..84438af96c05 100644
--- a/arch/powerpc/platforms/powernv/setup.c
+++ b/arch/powerpc/platforms/powernv/setup.c
@@ -93,6 +93,8 @@ static void  __noreturn pnv_restart(char *cmd)
 {
         long rc = OPAL_BUSY;
 
+        opal_notifier_disable();
+
         while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
                 rc = opal_cec_reboot();
                 if (rc == OPAL_BUSY_EVENT)
@@ -108,6 +110,8 @@ static void __noreturn pnv_power_off(void)
 {
         long rc = OPAL_BUSY;
 
+        opal_notifier_disable();
+
         while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
                 rc = opal_cec_power_down(0);
                 if (rc == OPAL_BUSY_EVENT)
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index 88c9459c3e07..89e3857af4e0 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -40,7 +40,7 @@
 #define DBG(fmt...)
 #endif
 
-static void __cpuinit pnv_smp_setup_cpu(int cpu)
+static void pnv_smp_setup_cpu(int cpu)
 {
         if (cpu != boot_cpuid)
                 xics_setup_cpu();
@@ -51,7 +51,7 @@ static int pnv_smp_cpu_bootable(unsigned int nr)
         /* Special case - we inhibit secondary thread startup
          * during boot if the user requests it.
          */
-        if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
+        if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) {
                 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
                         return 0;
                 if (smt_enabled_at_boot
diff --git a/arch/powerpc/platforms/ps3/htab.c b/arch/powerpc/platforms/ps3/htab.c
index 177a2f70700c..3e270e3412ae 100644
--- a/arch/powerpc/platforms/ps3/htab.c
+++ b/arch/powerpc/platforms/ps3/htab.c
@@ -109,7 +109,8 @@ static long ps3_hpte_remove(unsigned long hpte_group)
 }
 
 static long ps3_hpte_updatepp(unsigned long slot, unsigned long newpp,
-        unsigned long vpn, int psize, int ssize, int local)
+                              unsigned long vpn, int psize, int apsize,
+                              int ssize, int local)
 {
         int result;
         u64 hpte_v, want_v, hpte_rs;
@@ -162,7 +163,7 @@ static void ps3_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
 }
 
 static void ps3_hpte_invalidate(unsigned long slot, unsigned long vpn,
-        int psize, int ssize, int local)
+                                int psize, int apsize, int ssize, int local)
 {
         unsigned long flags;
         int result;
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index 4459eff7a75a..1bd3399146ed 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -33,11 +33,6 @@ config PPC_SPLPAR
           processors, that is, which share physical processors between
           two or more partitions.
 
-config EEH
-        bool
-        depends on PPC_PSERIES && PCI
-        default y
-
 config PSERIES_MSI
        bool
        depends on PCI_MSI && EEH
diff --git a/arch/powerpc/platforms/pseries/Makefile b/arch/powerpc/platforms/pseries/Makefile
index 53866e537a92..8ae010381316 100644
--- a/arch/powerpc/platforms/pseries/Makefile
+++ b/arch/powerpc/platforms/pseries/Makefile
@@ -6,9 +6,7 @@ obj-y			:= lpar.o hvCall.o nvram.o reconfig.o \
                            firmware.o power.o dlpar.o mobility.o
 obj-$(CONFIG_SMP)       += smp.o
 obj-$(CONFIG_SCANLOG)   += scanlog.o
-obj-$(CONFIG_EEH)       += eeh.o eeh_pe.o eeh_dev.o eeh_cache.o \
-                           eeh_driver.o eeh_event.o eeh_sysfs.o \
-                           eeh_pseries.o
+obj-$(CONFIG_EEH)       += eeh_pseries.o
 obj-$(CONFIG_KEXEC)     += kexec.o
 obj-$(CONFIG_PCI)       += pci.o pci_dlpar.o
 obj-$(CONFIG_PSERIES_MSI)       += msi.o
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 19506f935737..b456b157d33d 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -83,7 +83,11 @@ static int pseries_eeh_init(void)
         ibm_configure_pe                = rtas_token("ibm,configure-pe");
         ibm_configure_bridge            = rtas_token("ibm,configure-bridge");
 
-        /* necessary sanity check */
+        /*
+         * Necessary sanity check. We needn't check "get-config-addr-info"
+         * and its variant since the old firmware probably support address
+         * of domain/bus/slot/function for EEH RTAS operations.
+         */
         if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
                         __func__);
@@ -102,12 +106,6 @@ static int pseries_eeh_init(void)
                 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
                         __func__);
                 return -EINVAL;
-        } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
-                   ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
-                pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
-                        "<ibm,get-config-addr-info> invalid\n",
-                        __func__);
-                return -EINVAL;
         } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
                    ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
                 pr_warning("%s: RTAS service <ibm,configure-pe> and "
diff --git a/arch/powerpc/platforms/pseries/io_event_irq.c b/arch/powerpc/platforms/pseries/io_event_irq.c
index ef9d9d84c7d5..5ea88d1541f7 100644
--- a/arch/powerpc/platforms/pseries/io_event_irq.c
+++ b/arch/powerpc/platforms/pseries/io_event_irq.c
@@ -115,7 +115,7 @@ static struct pseries_io_event * ioei_find_event(struct rtas_error_log *elog)
  *   by scope or event type alone. For example, Torrent ISR route change
  *   event is reported with scope 0x00 (Not Applicatable) rather than
  *   0x3B (Torrent-hub). It is better to let the clients to identify
- *   who owns the the event.
+ *   who owns the event.
  */
 
 static irqreturn_t ioei_interrupt(int irq, void *dev_id)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 86ae364900d6..23fc1dcf4434 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -614,6 +614,7 @@ static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
 
         iommu_table_setparms(pci->phb, dn, tbl);
         pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
+        iommu_register_group(tbl, pci_domain_nr(bus), 0);
 
         /* Divide the rest (1.75GB) among the children */
         pci->phb->dma_window_size = 0x80000000ul;
@@ -658,6 +659,7 @@ static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
                                    ppci->phb->node);
                 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
                 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
+                iommu_register_group(tbl, pci_domain_nr(bus), 0);
                 pr_debug("  created table: %p\n", ppci->iommu_table);
         }
 }
@@ -684,6 +686,7 @@ static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
                                    phb->node);
                 iommu_table_setparms(phb, dn, tbl);
                 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
+                iommu_register_group(tbl, pci_domain_nr(phb->bus), 0);
                 set_iommu_table_base(&dev->dev, PCI_DN(dn)->iommu_table);
                 return;
         }
@@ -1184,6 +1187,7 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
                                    pci->phb->node);
                 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
                 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
+                iommu_register_group(tbl, pci_domain_nr(pci->phb->bus), 0);
                 pr_debug("  created table: %p\n", pci->iommu_table);
         } else {
                 pr_debug("  found DMA window, table: %p\n", pci->iommu_table);
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
index 6d62072a7d5a..02d6e21619bb 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -45,6 +45,13 @@
 #include "plpar_wrappers.h"
 #include "pseries.h"
 
+/* Flag bits for H_BULK_REMOVE */
+#define HBR_REQUEST     0x4000000000000000UL
+#define HBR_RESPONSE    0x8000000000000000UL
+#define HBR_END         0xc000000000000000UL
+#define HBR_AVPN        0x0200000000000000UL
+#define HBR_ANDCOND     0x0100000000000000UL
+
 
 /* in hvCall.S */
 EXPORT_SYMBOL(plpar_hcall);
@@ -64,6 +71,9 @@ void vpa_init(int cpu)
         if (cpu_has_feature(CPU_FTR_ALTIVEC))
                 lppaca_of(cpu).vmxregs_in_use = 1;
 
+        if (cpu_has_feature(CPU_FTR_ARCH_207S))
+                lppaca_of(cpu).ebb_regs_in_use = 1;
+
         addr = __pa(&lppaca_of(cpu));
         ret = register_vpa(hwcpu, addr);
 
@@ -240,7 +250,8 @@ static void pSeries_lpar_hptab_clear(void)
 static long pSeries_lpar_hpte_updatepp(unsigned long slot,
                                        unsigned long newpp,
                                        unsigned long vpn,
-                                       int psize, int ssize, int local)
+                                       int psize, int apsize,
+                                       int ssize, int local)
 {
         unsigned long lpar_rc;
         unsigned long flags = (newpp & 7) | H_AVPN;
@@ -328,7 +339,8 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
 }
 
 static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
-                                         int psize, int ssize, int local)
+                                         int psize, int apsize,
+                                         int ssize, int local)
 {
         unsigned long want_v;
         unsigned long lpar_rc;
@@ -345,6 +357,113 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long vpn,
         BUG_ON(lpar_rc != H_SUCCESS);
 }
 
+/*
+ * Limit iterations holding pSeries_lpar_tlbie_lock to 3. We also need
+ * to make sure that we avoid bouncing the hypervisor tlbie lock.
+ */
+#define PPC64_HUGE_HPTE_BATCH 12
+
+static void __pSeries_lpar_hugepage_invalidate(unsigned long *slot,
+                                             unsigned long *vpn, int count,
+                                             int psize, int ssize)
+{
+        unsigned long param[8];
+        int i = 0, pix = 0, rc;
+        unsigned long flags = 0;
+        int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
+
+        if (lock_tlbie)
+                spin_lock_irqsave(&pSeries_lpar_tlbie_lock, flags);
+
+        for (i = 0; i < count; i++) {
+
+                if (!firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
+                        pSeries_lpar_hpte_invalidate(slot[i], vpn[i], psize, 0,
+                                                     ssize, 0);
+                } else {
+                        param[pix] = HBR_REQUEST | HBR_AVPN | slot[i];
+                        param[pix+1] = hpte_encode_avpn(vpn[i], psize, ssize);
+                        pix += 2;
+                        if (pix == 8) {
+                                rc = plpar_hcall9(H_BULK_REMOVE, param,
+                                                  param[0], param[1], param[2],
+                                                  param[3], param[4], param[5],
+                                                  param[6], param[7]);
+                                BUG_ON(rc != H_SUCCESS);
+                                pix = 0;
+                        }
+                }
+        }
+        if (pix) {
+                param[pix] = HBR_END;
+                rc = plpar_hcall9(H_BULK_REMOVE, param, param[0], param[1],
+                                  param[2], param[3], param[4], param[5],
+                                  param[6], param[7]);
+                BUG_ON(rc != H_SUCCESS);
+        }
+
+        if (lock_tlbie)
+                spin_unlock_irqrestore(&pSeries_lpar_tlbie_lock, flags);
+}
+
+static void pSeries_lpar_hugepage_invalidate(struct mm_struct *mm,
+                                       unsigned char *hpte_slot_array,
+                                       unsigned long addr, int psize)
+{
+        int ssize = 0, i, index = 0;
+        unsigned long s_addr = addr;
+        unsigned int max_hpte_count, valid;
+        unsigned long vpn_array[PPC64_HUGE_HPTE_BATCH];
+        unsigned long slot_array[PPC64_HUGE_HPTE_BATCH];
+        unsigned long shift, hidx, vpn = 0, vsid, hash, slot;
+
+        shift = mmu_psize_defs[psize].shift;
+        max_hpte_count = 1U << (PMD_SHIFT - shift);
+
+        for (i = 0; i < max_hpte_count; i++) {
+                valid = hpte_valid(hpte_slot_array, i);
+                if (!valid)
+                        continue;
+                hidx =  hpte_hash_index(hpte_slot_array, i);
+
+                /* get the vpn */
+                addr = s_addr + (i * (1ul << shift));
+                if (!is_kernel_addr(addr)) {
+                        ssize = user_segment_size(addr);
+                        vsid = get_vsid(mm->context.id, addr, ssize);
+                        WARN_ON(vsid == 0);
+                } else {
+                        vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
+                        ssize = mmu_kernel_ssize;
+                }
+
+                vpn = hpt_vpn(addr, vsid, ssize);
+                hash = hpt_hash(vpn, shift, ssize);
+                if (hidx & _PTEIDX_SECONDARY)
+                        hash = ~hash;
+
+                slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
+                slot += hidx & _PTEIDX_GROUP_IX;
+
+                slot_array[index] = slot;
+                vpn_array[index] = vpn;
+                if (index == PPC64_HUGE_HPTE_BATCH - 1) {
+                        /*
+                         * Now do a bluk invalidate
+                         */
+                        __pSeries_lpar_hugepage_invalidate(slot_array,
+                                                           vpn_array,
+                                                           PPC64_HUGE_HPTE_BATCH,
+                                                           psize, ssize);
+                        index = 0;
+                } else
+                        index++;
+        }
+        if (index)
+                __pSeries_lpar_hugepage_invalidate(slot_array, vpn_array,
+                                                   index, psize, ssize);
+}
+
 static void pSeries_lpar_hpte_removebolted(unsigned long ea,
                                            int psize, int ssize)
 {
@@ -356,17 +475,12 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
 
         slot = pSeries_lpar_hpte_find(vpn, psize, ssize);
         BUG_ON(slot == -1);
-
-        pSeries_lpar_hpte_invalidate(slot, vpn, psize, ssize, 0);
+        /*
+         * lpar doesn't use the passed actual page size
+         */
+        pSeries_lpar_hpte_invalidate(slot, vpn, psize, 0, ssize, 0);
 }
 
-/* Flag bits for H_BULK_REMOVE */
-#define HBR_REQUEST     0x4000000000000000UL
-#define HBR_RESPONSE    0x8000000000000000UL
-#define HBR_END         0xc000000000000000UL
-#define HBR_AVPN        0x0200000000000000UL
-#define HBR_ANDCOND     0x0100000000000000UL
-
 /*
  * Take a spinlock around flushes to avoid bouncing the hypervisor tlbie
  * lock.
@@ -400,8 +514,11 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
                         slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
                         slot += hidx & _PTEIDX_GROUP_IX;
                         if (!firmware_has_feature(FW_FEATURE_BULK_REMOVE)) {
+                                /*
+                                 * lpar doesn't use the passed actual page size
+                                 */
                                 pSeries_lpar_hpte_invalidate(slot, vpn, psize,
-                                                             ssize, local);
+                                                             0, ssize, local);
                         } else {
                                 param[pix] = HBR_REQUEST | HBR_AVPN | slot;
                                 param[pix+1] = hpte_encode_avpn(vpn, psize,
@@ -452,6 +569,7 @@ void __init hpte_init_lpar(void)
         ppc_md.hpte_removebolted = pSeries_lpar_hpte_removebolted;
         ppc_md.flush_hash_range = pSeries_lpar_flush_hash_range;
         ppc_md.hpte_clear_all   = pSeries_lpar_hptab_clear;
+        ppc_md.hugepage_invalidate = pSeries_lpar_hugepage_invalidate;
 }
 
 #ifdef CONFIG_PPC_SMLPAR
diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c
index 8733a86ad52e..9f8671a44551 100644
--- a/arch/powerpc/platforms/pseries/nvram.c
+++ b/arch/powerpc/platforms/pseries/nvram.c
@@ -18,6 +18,7 @@
 #include <linux/spinlock.h>
 #include <linux/slab.h>
 #include <linux/kmsg_dump.h>
+#include <linux/pstore.h>
 #include <linux/ctype.h>
 #include <linux/zlib.h>
 #include <asm/uaccess.h>
@@ -29,6 +30,13 @@
 /* Max bytes to read/write in one go */
 #define NVRW_CNT 0x20
 
+/*
+ * Set oops header version to distingush between old and new format header.
+ * lnx,oops-log partition max size is 4000, header version > 4000 will
+ * help in identifying new header.
+ */
+#define OOPS_HDR_VERSION 5000
+
 static unsigned int nvram_size;
 static int nvram_fetch, nvram_store;
 static char nvram_buf[NVRW_CNT];        /* assume this is in the first 4GB */
@@ -45,20 +53,23 @@ struct nvram_os_partition {
         int min_size;   /* minimum acceptable size (0 means req_size) */
         long size;      /* size of data portion (excluding err_log_info) */
         long index;     /* offset of data portion of partition */
+        bool os_partition; /* partition initialized by OS, not FW */
 };
 
 static struct nvram_os_partition rtas_log_partition = {
         .name = "ibm,rtas-log",
         .req_size = 2079,
         .min_size = 1055,
-        .index = -1
+        .index = -1,
+        .os_partition = true
 };
 
 static struct nvram_os_partition oops_log_partition = {
         .name = "lnx,oops-log",
         .req_size = 4000,
         .min_size = 2000,
-        .index = -1
+        .index = -1,
+        .os_partition = true
 };
 
 static const char *pseries_nvram_os_partitions[] = {
@@ -67,6 +78,12 @@ static const char *pseries_nvram_os_partitions[] = {
         NULL
 };
 
+struct oops_log_info {
+        u16 version;
+        u16 report_length;
+        u64 timestamp;
+} __attribute__((packed));
+
 static void oops_to_nvram(struct kmsg_dumper *dumper,
                           enum kmsg_dump_reason reason);
 
@@ -83,28 +100,28 @@ static unsigned long last_unread_rtas_event;	/* timestamp */
 
  * big_oops_buf[] holds the uncompressed text we're capturing.
  *
- * oops_buf[] holds the compressed text, preceded by a prefix.
- * The prefix is just a u16 holding the length of the compressed* text.
- * (*Or uncompressed, if compression fails.)  oops_buf[] gets written
- * to NVRAM.
+ * oops_buf[] holds the compressed text, preceded by a oops header.
+ * oops header has u16 holding the version of oops header (to differentiate
+ * between old and new format header) followed by u16 holding the length of
+ * the compressed* text (*Or uncompressed, if compression fails.) and u64
+ * holding the timestamp. oops_buf[] gets written to NVRAM.
  *
- * oops_len points to the prefix.  oops_data points to the compressed text.
+ * oops_log_info points to the header. oops_data points to the compressed text.
  *
  * +- oops_buf
- * |            +- oops_data
- * v            v
- * +------------+-----------------------------------------------+
- * | length     | text                                          |
- * | (2 bytes)  | (oops_data_sz bytes)                          |
- * +------------+-----------------------------------------------+
+ * |                                   +- oops_data
+ * v                                   v
+ * +-----------+-----------+-----------+------------------------+
+ * | version   | length    | timestamp | text                   |
+ * | (2 bytes) | (2 bytes) | (8 bytes) | (oops_data_sz bytes)   |
+ * +-----------+-----------+-----------+------------------------+
  * ^
- * +- oops_len
+ * +- oops_log_info
  *
  * We preallocate these buffers during init to avoid kmalloc during oops/panic.
  */
 static size_t big_oops_buf_sz;
 static char *big_oops_buf, *oops_buf;
-static u16 *oops_len;
 static char *oops_data;
 static size_t oops_data_sz;
 
@@ -114,6 +131,30 @@ static size_t oops_data_sz;
 #define MEM_LEVEL 4
 static struct z_stream_s stream;
 
+#ifdef CONFIG_PSTORE
+static struct nvram_os_partition of_config_partition = {
+        .name = "of-config",
+        .index = -1,
+        .os_partition = false
+};
+
+static struct nvram_os_partition common_partition = {
+        .name = "common",
+        .index = -1,
+        .os_partition = false
+};
+
+static enum pstore_type_id nvram_type_ids[] = {
+        PSTORE_TYPE_DMESG,
+        PSTORE_TYPE_PPC_RTAS,
+        PSTORE_TYPE_PPC_OF,
+        PSTORE_TYPE_PPC_COMMON,
+        -1
+};
+static int read_type;
+static unsigned long last_rtas_event;
+#endif
+
 static ssize_t pSeries_nvram_read(char *buf, size_t count, loff_t *index)
 {
         unsigned int i;
@@ -275,48 +316,72 @@ int nvram_write_error_log(char * buff, int length,
 {
         int rc = nvram_write_os_partition(&rtas_log_partition, buff, length,
                                                 err_type, error_log_cnt);
-        if (!rc)
+        if (!rc) {
                 last_unread_rtas_event = get_seconds();
+#ifdef CONFIG_PSTORE
+                last_rtas_event = get_seconds();
+#endif
+        }
+
         return rc;
 }
 
-/* nvram_read_error_log
+/* nvram_read_partition
  *
- * Reads nvram for error log for at most 'length'
+ * Reads nvram partition for at most 'length'
  */
-int nvram_read_error_log(char * buff, int length,
-                         unsigned int * err_type, unsigned int * error_log_cnt)
+int nvram_read_partition(struct nvram_os_partition *part, char *buff,
+                        int length, unsigned int *err_type,
+                        unsigned int *error_log_cnt)
 {
         int rc;
         loff_t tmp_index;
         struct err_log_info info;
         
-        if (rtas_log_partition.index == -1)
+        if (part->index == -1)
                 return -1;
 
-        if (length > rtas_log_partition.size)
-                length = rtas_log_partition.size;
+        if (length > part->size)
+                length = part->size;
 
-        tmp_index = rtas_log_partition.index;
+        tmp_index = part->index;
 
-        rc = ppc_md.nvram_read((char *)&info, sizeof(struct err_log_info), &tmp_index);
-        if (rc <= 0) {
-                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
-                return rc;
+        if (part->os_partition) {
+                rc = ppc_md.nvram_read((char *)&info,
+                                        sizeof(struct err_log_info),
+                                        &tmp_index);
+                if (rc <= 0) {
+                        pr_err("%s: Failed nvram_read (%d)\n", __FUNCTION__,
+                                                                        rc);
+                        return rc;
+                }
         }
 
         rc = ppc_md.nvram_read(buff, length, &tmp_index);
         if (rc <= 0) {
-                printk(KERN_ERR "nvram_read_error_log: Failed nvram_read (%d)\n", rc);
+                pr_err("%s: Failed nvram_read (%d)\n", __FUNCTION__, rc);
                 return rc;
         }
 
-        *error_log_cnt = info.seq_num;
-        *err_type = info.error_type;
+        if (part->os_partition) {
+                *error_log_cnt = info.seq_num;
+                *err_type = info.error_type;
+        }
 
         return 0;
 }
 
+/* nvram_read_error_log
+ *
+ * Reads nvram for error log for at most 'length'
+ */
+int nvram_read_error_log(char *buff, int length,
+                        unsigned int *err_type, unsigned int *error_log_cnt)
+{
+        return nvram_read_partition(&rtas_log_partition, buff, length,
+                                                err_type, error_log_cnt);
+}
+
 /* This doesn't actually zero anything, but it sets the event_logged
  * word to tell that this event is safely in syslog.
  */
@@ -405,6 +470,349 @@ static int __init pseries_nvram_init_os_partition(struct nvram_os_partition
         return 0;
 }
 
+/*
+ * Are we using the ibm,rtas-log for oops/panic reports?  And if so,
+ * would logging this oops/panic overwrite an RTAS event that rtas_errd
+ * hasn't had a chance to read and process?  Return 1 if so, else 0.
+ *
+ * We assume that if rtas_errd hasn't read the RTAS event in
+ * NVRAM_RTAS_READ_TIMEOUT seconds, it's probably not going to.
+ */
+static int clobbering_unread_rtas_event(void)
+{
+        return (oops_log_partition.index == rtas_log_partition.index
+                && last_unread_rtas_event
+                && get_seconds() - last_unread_rtas_event <=
+                                                NVRAM_RTAS_READ_TIMEOUT);
+}
+
+/* Derived from logfs_compress() */
+static int nvram_compress(const void *in, void *out, size_t inlen,
+                                                        size_t outlen)
+{
+        int err, ret;
+
+        ret = -EIO;
+        err = zlib_deflateInit2(&stream, COMPR_LEVEL, Z_DEFLATED, WINDOW_BITS,
+                                                MEM_LEVEL, Z_DEFAULT_STRATEGY);
+        if (err != Z_OK)
+                goto error;
+
+        stream.next_in = in;
+        stream.avail_in = inlen;
+        stream.total_in = 0;
+        stream.next_out = out;
+        stream.avail_out = outlen;
+        stream.total_out = 0;
+
+        err = zlib_deflate(&stream, Z_FINISH);
+        if (err != Z_STREAM_END)
+                goto error;
+
+        err = zlib_deflateEnd(&stream);
+        if (err != Z_OK)
+                goto error;
+
+        if (stream.total_out >= stream.total_in)
+                goto error;
+
+        ret = stream.total_out;
+error:
+        return ret;
+}
+
+/* Compress the text from big_oops_buf into oops_buf. */
+static int zip_oops(size_t text_len)
+{
+        struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
+        int zipped_len = nvram_compress(big_oops_buf, oops_data, text_len,
+                                                                oops_data_sz);
+        if (zipped_len < 0) {
+                pr_err("nvram: compression failed; returned %d\n", zipped_len);
+                pr_err("nvram: logging uncompressed oops/panic report\n");
+                return -1;
+        }
+        oops_hdr->version = OOPS_HDR_VERSION;
+        oops_hdr->report_length = (u16) zipped_len;
+        oops_hdr->timestamp = get_seconds();
+        return 0;
+}
+
+#ifdef CONFIG_PSTORE
+/* Derived from logfs_uncompress */
+int nvram_decompress(void *in, void *out, size_t inlen, size_t outlen)
+{
+        int err, ret;
+
+        ret = -EIO;
+        err = zlib_inflateInit(&stream);
+        if (err != Z_OK)
+                goto error;
+
+        stream.next_in = in;
+        stream.avail_in = inlen;
+        stream.total_in = 0;
+        stream.next_out = out;
+        stream.avail_out = outlen;
+        stream.total_out = 0;
+
+        err = zlib_inflate(&stream, Z_FINISH);
+        if (err != Z_STREAM_END)
+                goto error;
+
+        err = zlib_inflateEnd(&stream);
+        if (err != Z_OK)
+                goto error;
+
+        ret = stream.total_out;
+error:
+        return ret;
+}
+
+static int unzip_oops(char *oops_buf, char *big_buf)
+{
+        struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
+        u64 timestamp = oops_hdr->timestamp;
+        char *big_oops_data = NULL;
+        char *oops_data_buf = NULL;
+        size_t big_oops_data_sz;
+        int unzipped_len;
+
+        big_oops_data = big_buf + sizeof(struct oops_log_info);
+        big_oops_data_sz = big_oops_buf_sz - sizeof(struct oops_log_info);
+        oops_data_buf = oops_buf + sizeof(struct oops_log_info);
+
+        unzipped_len = nvram_decompress(oops_data_buf, big_oops_data,
+                                        oops_hdr->report_length,
+                                        big_oops_data_sz);
+
+        if (unzipped_len < 0) {
+                pr_err("nvram: decompression failed; returned %d\n",
+                                                                unzipped_len);
+                return -1;
+        }
+        oops_hdr = (struct oops_log_info *)big_buf;
+        oops_hdr->version = OOPS_HDR_VERSION;
+        oops_hdr->report_length = (u16) unzipped_len;
+        oops_hdr->timestamp = timestamp;
+        return 0;
+}
+
+static int nvram_pstore_open(struct pstore_info *psi)
+{
+        /* Reset the iterator to start reading partitions again */
+        read_type = -1;
+        return 0;
+}
+
+/**
+ * nvram_pstore_write - pstore write callback for nvram
+ * @type:               Type of message logged
+ * @reason:             reason behind dump (oops/panic)
+ * @id:                 identifier to indicate the write performed
+ * @part:               pstore writes data to registered buffer in parts,
+ *                      part number will indicate the same.
+ * @count:              Indicates oops count
+ * @hsize:              Size of header added by pstore
+ * @size:               number of bytes written to the registered buffer
+ * @psi:                registered pstore_info structure
+ *
+ * Called by pstore_dump() when an oops or panic report is logged in the
+ * printk buffer.
+ * Returns 0 on successful write.
+ */
+static int nvram_pstore_write(enum pstore_type_id type,
+                                enum kmsg_dump_reason reason,
+                                u64 *id, unsigned int part, int count,
+                                size_t hsize, size_t size,
+                                struct pstore_info *psi)
+{
+        int rc;
+        unsigned int err_type = ERR_TYPE_KERNEL_PANIC;
+        struct oops_log_info *oops_hdr = (struct oops_log_info *) oops_buf;
+
+        /* part 1 has the recent messages from printk buffer */
+        if (part > 1 || type != PSTORE_TYPE_DMESG ||
+                                clobbering_unread_rtas_event())
+                return -1;
+
+        oops_hdr->version = OOPS_HDR_VERSION;
+        oops_hdr->report_length = (u16) size;
+        oops_hdr->timestamp = get_seconds();
+
+        if (big_oops_buf) {
+                rc = zip_oops(size);
+                /*
+                 * If compression fails copy recent log messages from
+                 * big_oops_buf to oops_data.
+                 */
+                if (rc != 0) {
+                        size_t diff = size - oops_data_sz + hsize;
+
+                        if (size > oops_data_sz) {
+                                memcpy(oops_data, big_oops_buf, hsize);
+                                memcpy(oops_data + hsize, big_oops_buf + diff,
+                                        oops_data_sz - hsize);
+
+                                oops_hdr->report_length = (u16) oops_data_sz;
+                        } else
+                                memcpy(oops_data, big_oops_buf, size);
+                } else
+                        err_type = ERR_TYPE_KERNEL_PANIC_GZ;
+        }
+
+        rc = nvram_write_os_partition(&oops_log_partition, oops_buf,
+                (int) (sizeof(*oops_hdr) + oops_hdr->report_length), err_type,
+                count);
+
+        if (rc != 0)
+                return rc;
+
+        *id = part;
+        return 0;
+}
+
+/*
+ * Reads the oops/panic report, rtas, of-config and common partition.
+ * Returns the length of the data we read from each partition.
+ * Returns 0 if we've been called before.
+ */
+static ssize_t nvram_pstore_read(u64 *id, enum pstore_type_id *type,
+                                int *count, struct timespec *time, char **buf,
+                                struct pstore_info *psi)
+{
+        struct oops_log_info *oops_hdr;
+        unsigned int err_type, id_no, size = 0;
+        struct nvram_os_partition *part = NULL;
+        char *buff = NULL, *big_buff = NULL;
+        int rc, sig = 0;
+        loff_t p;
+
+read_partition:
+        read_type++;
+
+        switch (nvram_type_ids[read_type]) {
+        case PSTORE_TYPE_DMESG:
+                part = &oops_log_partition;
+                *type = PSTORE_TYPE_DMESG;
+                break;
+        case PSTORE_TYPE_PPC_RTAS:
+                part = &rtas_log_partition;
+                *type = PSTORE_TYPE_PPC_RTAS;
+                time->tv_sec = last_rtas_event;
+                time->tv_nsec = 0;
+                break;
+        case PSTORE_TYPE_PPC_OF:
+                sig = NVRAM_SIG_OF;
+                part = &of_config_partition;
+                *type = PSTORE_TYPE_PPC_OF;
+                *id = PSTORE_TYPE_PPC_OF;
+                time->tv_sec = 0;
+                time->tv_nsec = 0;
+                break;
+        case PSTORE_TYPE_PPC_COMMON:
+                sig = NVRAM_SIG_SYS;
+                part = &common_partition;
+                *type = PSTORE_TYPE_PPC_COMMON;
+                *id = PSTORE_TYPE_PPC_COMMON;
+                time->tv_sec = 0;
+                time->tv_nsec = 0;
+                break;
+        default:
+                return 0;
+        }
+
+        if (!part->os_partition) {
+                p = nvram_find_partition(part->name, sig, &size);
+                if (p <= 0) {
+                        pr_err("nvram: Failed to find partition %s, "
+                                "err %d\n", part->name, (int)p);
+                        return 0;
+                }
+                part->index = p;
+                part->size = size;
+        }
+
+        buff = kmalloc(part->size, GFP_KERNEL);
+
+        if (!buff)
+                return -ENOMEM;
+
+        if (nvram_read_partition(part, buff, part->size, &err_type, &id_no)) {
+                kfree(buff);
+                return 0;
+        }
+
+        *count = 0;
+
+        if (part->os_partition)
+                *id = id_no;
+
+        if (nvram_type_ids[read_type] == PSTORE_TYPE_DMESG) {
+                oops_hdr = (struct oops_log_info *)buff;
+                *buf = buff + sizeof(*oops_hdr);
+
+                if (err_type == ERR_TYPE_KERNEL_PANIC_GZ) {
+                        big_buff = kmalloc(big_oops_buf_sz, GFP_KERNEL);
+                        if (!big_buff)
+                                return -ENOMEM;
+
+                        rc = unzip_oops(buff, big_buff);
+
+                        if (rc != 0) {
+                                kfree(buff);
+                                kfree(big_buff);
+                                goto read_partition;
+                        }
+
+                        oops_hdr = (struct oops_log_info *)big_buff;
+                        *buf = big_buff + sizeof(*oops_hdr);
+                        kfree(buff);
+                }
+
+                time->tv_sec = oops_hdr->timestamp;
+                time->tv_nsec = 0;
+                return oops_hdr->report_length;
+        }
+
+        *buf = buff;
+        return part->size;
+}
+
+static struct pstore_info nvram_pstore_info = {
+        .owner = THIS_MODULE,
+        .name = "nvram",
+        .open = nvram_pstore_open,
+        .read = nvram_pstore_read,
+        .write = nvram_pstore_write,
+};
+
+static int nvram_pstore_init(void)
+{
+        int rc = 0;
+
+        if (big_oops_buf) {
+                nvram_pstore_info.buf = big_oops_buf;
+                nvram_pstore_info.bufsize = big_oops_buf_sz;
+        } else {
+                nvram_pstore_info.buf = oops_data;
+                nvram_pstore_info.bufsize = oops_data_sz;
+        }
+
+        rc = pstore_register(&nvram_pstore_info);
+        if (rc != 0)
+                pr_err("nvram: pstore_register() failed, defaults to "
+                                "kmsg_dump; returned %d\n", rc);
+
+        return rc;
+}
+#else
+static int nvram_pstore_init(void)
+{
+        return -1;
+}
+#endif
+
 static void __init nvram_init_oops_partition(int rtas_partition_exists)
 {
         int rc;
@@ -425,9 +833,8 @@ static void __init nvram_init_oops_partition(int rtas_partition_exists)
                                                 oops_log_partition.name);
                 return;
         }
-        oops_len = (u16*) oops_buf;
-        oops_data = oops_buf + sizeof(u16);
-        oops_data_sz = oops_log_partition.size - sizeof(u16);
+        oops_data = oops_buf + sizeof(struct oops_log_info);
+        oops_data_sz = oops_log_partition.size - sizeof(struct oops_log_info);
 
         /*
          * Figure compression (preceded by elimination of each line's <n>
@@ -452,6 +859,11 @@ static void __init nvram_init_oops_partition(int rtas_partition_exists)
                 stream.workspace = NULL;
         }
 
+        rc = nvram_pstore_init();
+
+        if (!rc)
+                return;
+
         rc = kmsg_dump_register(&nvram_kmsg_dumper);
         if (rc != 0) {
                 pr_err("nvram: kmsg_dump_register() failed; returned %d\n", rc);
@@ -501,70 +913,6 @@ int __init pSeries_nvram_init(void)
         return 0;
 }
 
-/*
- * Are we using the ibm,rtas-log for oops/panic reports?  And if so,
- * would logging this oops/panic overwrite an RTAS event that rtas_errd
- * hasn't had a chance to read and process?  Return 1 if so, else 0.
- *
- * We assume that if rtas_errd hasn't read the RTAS event in
- * NVRAM_RTAS_READ_TIMEOUT seconds, it's probably not going to.
- */
-static int clobbering_unread_rtas_event(void)
-{
-        return (oops_log_partition.index == rtas_log_partition.index
-                && last_unread_rtas_event
-                && get_seconds() - last_unread_rtas_event <=
-                                                NVRAM_RTAS_READ_TIMEOUT);
-}
-
-/* Derived from logfs_compress() */
-static int nvram_compress(const void *in, void *out, size_t inlen,
-                                                        size_t outlen)
-{
-        int err, ret;
-
-        ret = -EIO;
-        err = zlib_deflateInit2(&stream, COMPR_LEVEL, Z_DEFLATED, WINDOW_BITS,
-                                                MEM_LEVEL, Z_DEFAULT_STRATEGY);
-        if (err != Z_OK)
-                goto error;
-
-        stream.next_in = in;
-        stream.avail_in = inlen;
-        stream.total_in = 0;
-        stream.next_out = out;
-        stream.avail_out = outlen;
-        stream.total_out = 0;
-
-        err = zlib_deflate(&stream, Z_FINISH);
-        if (err != Z_STREAM_END)
-                goto error;
-
-        err = zlib_deflateEnd(&stream);
-        if (err != Z_OK)
-                goto error;
-
-        if (stream.total_out >= stream.total_in)
-                goto error;
-
-        ret = stream.total_out;
-error:
-        return ret;
-}
-
-/* Compress the text from big_oops_buf into oops_buf. */
-static int zip_oops(size_t text_len)
-{
-        int zipped_len = nvram_compress(big_oops_buf, oops_data, text_len,
-                                                                oops_data_sz);
-        if (zipped_len < 0) {
-                pr_err("nvram: compression failed; returned %d\n", zipped_len);
-                pr_err("nvram: logging uncompressed oops/panic report\n");
-                return -1;
-        }
-        *oops_len = (u16) zipped_len;
-        return 0;
-}
 
 /*
  * This is our kmsg_dump callback, called after an oops or panic report
@@ -576,6 +924,7 @@ static int zip_oops(size_t text_len)
 static void oops_to_nvram(struct kmsg_dumper *dumper,
                           enum kmsg_dump_reason reason)
 {
+        struct oops_log_info *oops_hdr = (struct oops_log_info *)oops_buf;
         static unsigned int oops_count = 0;
         static bool panicking = false;
         static DEFINE_SPINLOCK(lock);
@@ -619,14 +968,17 @@ static void oops_to_nvram(struct kmsg_dumper *dumper,
         }
         if (rc != 0) {
                 kmsg_dump_rewind(dumper);
-                kmsg_dump_get_buffer(dumper, true,
+                kmsg_dump_get_buffer(dumper, false,
                                      oops_data, oops_data_sz, &text_len);
                 err_type = ERR_TYPE_KERNEL_PANIC;
-                *oops_len = (u16) text_len;
+                oops_hdr->version = OOPS_HDR_VERSION;
+                oops_hdr->report_length = (u16) text_len;
+                oops_hdr->timestamp = get_seconds();
         }
 
         (void) nvram_write_os_partition(&oops_log_partition, oops_buf,
-                (int) (sizeof(*oops_len) + *oops_len), err_type, ++oops_count);
+                (int) (sizeof(*oops_hdr) + oops_hdr->report_length), err_type,
+                ++oops_count);
 
         spin_unlock_irqrestore(&lock, flags);
 }
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index c91b22be9288..efe61374f6ea 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -64,91 +64,6 @@ pcibios_find_pci_bus(struct device_node *dn)
 }
 EXPORT_SYMBOL_GPL(pcibios_find_pci_bus);
 
-/**
- * __pcibios_remove_pci_devices - remove all devices under this bus
- * @bus: the indicated PCI bus
- * @purge_pe: destroy the PE on removal of PCI devices
- *
- * Remove all of the PCI devices under this bus both from the
- * linux pci device tree, and from the powerpc EEH address cache.
- * By default, the corresponding PE will be destroied during the
- * normal PCI hotplug path. For PCI hotplug during EEH recovery,
- * the corresponding PE won't be destroied and deallocated.
- */
-void __pcibios_remove_pci_devices(struct pci_bus *bus, int purge_pe)
-{
-        struct pci_dev *dev, *tmp;
-        struct pci_bus *child_bus;
-
-        /* First go down child busses */
-        list_for_each_entry(child_bus, &bus->children, node)
-                __pcibios_remove_pci_devices(child_bus, purge_pe);
-
-        pr_debug("PCI: Removing devices on bus %04x:%02x\n",
-                pci_domain_nr(bus),  bus->number);
-        list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list) {
-                pr_debug("     * Removing %s...\n", pci_name(dev));
-                eeh_remove_bus_device(dev, purge_pe);
-                pci_stop_and_remove_bus_device(dev);
-        }
-}
-
-/**
- * pcibios_remove_pci_devices - remove all devices under this bus
- *
- * Remove all of the PCI devices under this bus both from the
- * linux pci device tree, and from the powerpc EEH address cache.
- */
-void pcibios_remove_pci_devices(struct pci_bus *bus)
-{
-        __pcibios_remove_pci_devices(bus, 1);
-}
-EXPORT_SYMBOL_GPL(pcibios_remove_pci_devices);
-
-/**
- * pcibios_add_pci_devices - adds new pci devices to bus
- *
- * This routine will find and fixup new pci devices under
- * the indicated bus. This routine presumes that there
- * might already be some devices under this bridge, so
- * it carefully tries to add only new devices.  (And that
- * is how this routine differs from other, similar pcibios
- * routines.)
- */
-void pcibios_add_pci_devices(struct pci_bus * bus)
-{
-        int slotno, num, mode, pass, max;
-        struct pci_dev *dev;
-        struct device_node *dn = pci_bus_to_OF_node(bus);
-
-        eeh_add_device_tree_early(dn);
-
-        mode = PCI_PROBE_NORMAL;
-        if (ppc_md.pci_probe_mode)
-                mode = ppc_md.pci_probe_mode(bus);
-
-        if (mode == PCI_PROBE_DEVTREE) {
-                /* use ofdt-based probe */
-                of_rescan_bus(dn, bus);
-        } else if (mode == PCI_PROBE_NORMAL) {
-                /* use legacy probe */
-                slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
-                num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
-                if (!num)
-                        return;
-                pcibios_setup_bus_devices(bus);
-                max = bus->busn_res.start;
-                for (pass=0; pass < 2; pass++)
-                        list_for_each_entry(dev, &bus->devices, bus_list) {
-                        if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
-                            dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
-                                max = pci_scan_bridge(bus, dev, max, pass);
-                }
-        }
-        pcibios_finish_adding_to_bus(bus);
-}
-EXPORT_SYMBOL_GPL(pcibios_add_pci_devices);
-
 struct pci_controller *init_phb_dynamic(struct device_node *dn)
 {
         struct pci_controller *phb;
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index c4dfccd3a3d9..7b3cbde8c783 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c
@@ -83,7 +83,7 @@ static void handle_system_shutdown(char event_modifier)
         switch (event_modifier) {
         case EPOW_SHUTDOWN_NORMAL:
                 pr_emerg("Firmware initiated power off");
-                orderly_poweroff(1);
+                orderly_poweroff(true);
                 break;
 
         case EPOW_SHUTDOWN_ON_UPS:
@@ -95,13 +95,13 @@ static void handle_system_shutdown(char event_modifier)
                 pr_emerg("Loss of system critical functions reported by "
                         "firmware");
                 pr_emerg("Check RTAS error log for details");
-                orderly_poweroff(1);
+                orderly_poweroff(true);
                 break;
 
         case EPOW_SHUTDOWN_AMBIENT_TEMPERATURE_TOO_HIGH:
                 pr_emerg("Ambient temperature too high reported by firmware");
                 pr_emerg("Check RTAS error log for details");
-                orderly_poweroff(1);
+                orderly_poweroff(true);
                 break;
 
         default:
@@ -162,7 +162,7 @@ void rtas_parse_epow_errlog(struct rtas_error_log *log)
 
         case EPOW_SYSTEM_HALT:
                 pr_emerg("Firmware initiated power off");
-                orderly_poweroff(1);
+                orderly_poweroff(true);
                 break;
 
         case EPOW_MAIN_ENCLOSURE:
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index 12bc8c3663ad..306643cc9dbc 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -192,7 +192,7 @@ static int smp_pSeries_cpu_bootable(unsigned int nr)
         /* Special case - we inhibit secondary thread startup
          * during boot if the user requests it.
          */
-        if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
+        if (system_state == SYSTEM_BOOTING && cpu_has_feature(CPU_FTR_SMT)) {
                 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
                         return 0;
                 if (smt_enabled_at_boot
diff --git a/arch/powerpc/relocs_check.pl b/arch/powerpc/relocs_check.pl
index 7f5b83808862..3f46e8b9c56d 100755
--- a/arch/powerpc/relocs_check.pl
+++ b/arch/powerpc/relocs_check.pl
@@ -7,7 +7,7 @@
 # as published by the Free Software Foundation; either version
 # 2 of the License, or (at your option) any later version.
 
-# This script checks the relcoations of a vmlinux for "suspicious"
+# This script checks the relocations of a vmlinux for "suspicious"
 # relocations.
 
 use strict;
@@ -28,7 +28,7 @@ open(FD, "$objdump -R $vmlinux|") or die;
 while (<FD>) {
         study $_;
 
-        # Only look at relcoation lines.
+        # Only look at relocation lines.
         next if (!/\s+R_/);
 
         # These relocations are okay
@@ -45,7 +45,7 @@ while (<FD>) {
                  /\bR_PPC_ADDR16_HA\b/ or /\bR_PPC_RELATIVE\b/ or
                  /\bR_PPC_NONE\b/);
 
-        # If we see this type of relcoation it's an idication that
+        # If we see this type of relocation it's an idication that
         # we /may/ be using an old version of binutils.
         if (/R_PPC64_UADDR64/) {
                 $old_binutils++;
@@ -61,6 +61,6 @@ if ($bad_relocs_count) {
 }
 
 if ($old_binutils) {
-        print "WARNING: You need at binutils >= 2.19 to build a ".
-              "CONFIG_RELCOATABLE kernel\n";
+        print "WARNING: You need at least binutils >= 2.19 to build a ".
+              "CONFIG_RELOCATABLE kernel\n";
 }
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 99464a7bdb3b..f67ac900d870 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,8 @@ ccflags-$(CONFIG_PPC64)		:= $(NO_MINIMAL_TOC)
 
 mpic-msi-obj-$(CONFIG_PCI_MSI)  += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
 obj-$(CONFIG_MPIC)              += mpic.o $(mpic-msi-obj-y)
+obj-$(CONFIG_MPIC_TIMER)        += mpic_timer.o
+obj-$(CONFIG_FSL_MPIC_TIMER_WAKEUP)     += fsl_mpic_timer_wakeup.o
 mpic-msgr-obj-$(CONFIG_MPIC_MSGR)       += mpic_msgr.o
 obj-$(CONFIG_MPIC)              += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
 obj-$(CONFIG_PPC_EPAPR_HV_PIC)  += ehv_pic.o
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index d4fa03f2b6ac..5e6ff38ea69f 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -120,6 +120,7 @@ static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 
 static struct irqaction cpm_error_irqaction = {
         .handler = cpm_error_interrupt,
+        .flags = IRQF_NO_THREAD,
         .name = "error",
 };
 
diff --git a/arch/powerpc/sysdev/fsl_mpic_timer_wakeup.c b/arch/powerpc/sysdev/fsl_mpic_timer_wakeup.c
new file mode 100644
index 000000000000..1707bf04dec6
--- /dev/null
+++ b/arch/powerpc/sysdev/fsl_mpic_timer_wakeup.c
@@ -0,0 +1,161 @@
+/*
+ * MPIC timer wakeup driver
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+
+#include <asm/mpic_timer.h>
+#include <asm/mpic.h>
+
+struct fsl_mpic_timer_wakeup {
+        struct mpic_timer *timer;
+        struct work_struct free_work;
+};
+
+static struct fsl_mpic_timer_wakeup *fsl_wakeup;
+static DEFINE_MUTEX(sysfs_lock);
+
+static void fsl_free_resource(struct work_struct *ws)
+{
+        struct fsl_mpic_timer_wakeup *wakeup =
+                container_of(ws, struct fsl_mpic_timer_wakeup, free_work);
+
+        mutex_lock(&sysfs_lock);
+
+        if (wakeup->timer) {
+                disable_irq_wake(wakeup->timer->irq);
+                mpic_free_timer(wakeup->timer);
+        }
+
+        wakeup->timer = NULL;
+        mutex_unlock(&sysfs_lock);
+}
+
+static irqreturn_t fsl_mpic_timer_irq(int irq, void *dev_id)
+{
+        struct fsl_mpic_timer_wakeup *wakeup = dev_id;
+
+        schedule_work(&wakeup->free_work);
+
+        return wakeup->timer ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static ssize_t fsl_timer_wakeup_show(struct device *dev,
+                                struct device_attribute *attr,
+                                char *buf)
+{
+        struct timeval interval;
+        int val = 0;
+
+        mutex_lock(&sysfs_lock);
+        if (fsl_wakeup->timer) {
+                mpic_get_remain_time(fsl_wakeup->timer, &interval);
+                val = interval.tv_sec + 1;
+        }
+        mutex_unlock(&sysfs_lock);
+
+        return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t fsl_timer_wakeup_store(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf,
+                                size_t count)
+{
+        struct timeval interval;
+        int ret;
+
+        interval.tv_usec = 0;
+        if (kstrtol(buf, 0, &interval.tv_sec))
+                return -EINVAL;
+
+        mutex_lock(&sysfs_lock);
+
+        if (fsl_wakeup->timer) {
+                disable_irq_wake(fsl_wakeup->timer->irq);
+                mpic_free_timer(fsl_wakeup->timer);
+                fsl_wakeup->timer = NULL;
+        }
+
+        if (!interval.tv_sec) {
+                mutex_unlock(&sysfs_lock);
+                return count;
+        }
+
+        fsl_wakeup->timer = mpic_request_timer(fsl_mpic_timer_irq,
+                                                fsl_wakeup, &interval);
+        if (!fsl_wakeup->timer) {
+                mutex_unlock(&sysfs_lock);
+                return -EINVAL;
+        }
+
+        ret = enable_irq_wake(fsl_wakeup->timer->irq);
+        if (ret) {
+                mpic_free_timer(fsl_wakeup->timer);
+                fsl_wakeup->timer = NULL;
+                mutex_unlock(&sysfs_lock);
+
+                return ret;
+        }
+
+        mpic_start_timer(fsl_wakeup->timer);
+
+        mutex_unlock(&sysfs_lock);
+
+        return count;
+}
+
+static struct device_attribute mpic_attributes = __ATTR(timer_wakeup, 0644,
+                        fsl_timer_wakeup_show, fsl_timer_wakeup_store);
+
+static int __init fsl_wakeup_sys_init(void)
+{
+        int ret;
+
+        fsl_wakeup = kzalloc(sizeof(struct fsl_mpic_timer_wakeup), GFP_KERNEL);
+        if (!fsl_wakeup)
+                return -ENOMEM;
+
+        INIT_WORK(&fsl_wakeup->free_work, fsl_free_resource);
+
+        ret = device_create_file(mpic_subsys.dev_root, &mpic_attributes);
+        if (ret)
+                kfree(fsl_wakeup);
+
+        return ret;
+}
+
+static void __exit fsl_wakeup_sys_exit(void)
+{
+        device_remove_file(mpic_subsys.dev_root, &mpic_attributes);
+
+        mutex_lock(&sysfs_lock);
+
+        if (fsl_wakeup->timer) {
+                disable_irq_wake(fsl_wakeup->timer->irq);
+                mpic_free_timer(fsl_wakeup->timer);
+        }
+
+        kfree(fsl_wakeup);
+
+        mutex_unlock(&sysfs_lock);
+}
+
+module_init(fsl_wakeup_sys_init);
+module_exit(fsl_wakeup_sys_exit);
+
+MODULE_DESCRIPTION("Freescale MPIC global timer wakeup driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Wang Dongsheng <dongsheng.wang@freescale.com>");
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 028ac1f71b51..46ac1ddea683 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -97,22 +97,14 @@ static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
         return indirect_read_config(bus, devfn, offset, len, val);
 }
 
-static struct pci_ops fsl_indirect_pci_ops =
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+
+static struct pci_ops fsl_indirect_pcie_ops =
 {
         .read = fsl_indirect_read_config,
         .write = indirect_write_config,
 };
 
-static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
-                                          resource_size_t cfg_addr,
-                                          resource_size_t cfg_data, u32 flags)
-{
-        setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
-        hose->ops = &fsl_indirect_pci_ops;
-}
-
-#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
-
 #define MAX_PHYS_ADDR_BITS      40
 static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS;
 
@@ -504,13 +496,15 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
         if (!hose->private_data)
                 goto no_bridge;
 
-        fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
-                               PPC_INDIRECT_TYPE_BIG_ENDIAN);
+        setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
+                           PPC_INDIRECT_TYPE_BIG_ENDIAN);
 
         if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
                 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
 
         if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
+                /* use fsl_indirect_read_config for PCIe */
+                hose->ops = &fsl_indirect_pcie_ops;
                 /* For PCIE read HEADER_TYPE to identify controler mode */
                 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
                 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
@@ -814,8 +808,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
                 if (ret)
                         goto err0;
         } else {
-                fsl_setup_indirect_pci(hose, rsrc_cfg.start,
-                                       rsrc_cfg.start + 4, 0);
+                setup_indirect_pci(hose, rsrc_cfg.start,
+                                   rsrc_cfg.start + 4, 0);
         }
 
         printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 3cc2f9159ab1..1be54faf60dd 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -48,6 +48,12 @@
 #define DBG(fmt...)
 #endif
 
+struct bus_type mpic_subsys = {
+        .name = "mpic",
+        .dev_name = "mpic",
+};
+EXPORT_SYMBOL_GPL(mpic_subsys);
+
 static struct mpic *mpics;
 static struct mpic *mpic_primary;
 static DEFINE_RAW_SPINLOCK(mpic_lock);
@@ -920,6 +926,22 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         return IRQ_SET_MASK_OK_NOCOPY;
 }
 
+static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+        struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
+        struct mpic *mpic = mpic_from_irq_data(d);
+
+        if (!(mpic->flags & MPIC_FSL))
+                return -ENXIO;
+
+        if (on)
+                desc->action->flags |= IRQF_NO_SUSPEND;
+        else
+                desc->action->flags &= ~IRQF_NO_SUSPEND;
+
+        return 0;
+}
+
 void mpic_set_vector(unsigned int virq, unsigned int vector)
 {
         struct mpic *mpic = mpic_from_irq(virq);
@@ -957,6 +979,7 @@ static struct irq_chip mpic_irq_chip = {
         .irq_unmask     = mpic_unmask_irq,
         .irq_eoi        = mpic_end_irq,
         .irq_set_type   = mpic_set_irq_type,
+        .irq_set_wake   = mpic_irq_set_wake,
 };
 
 #ifdef CONFIG_SMP
@@ -971,6 +994,7 @@ static struct irq_chip mpic_tm_chip = {
         .irq_mask       = mpic_mask_tm,
         .irq_unmask     = mpic_unmask_tm,
         .irq_eoi        = mpic_end_irq,
+        .irq_set_wake   = mpic_irq_set_wake,
 };
 
 #ifdef CONFIG_MPIC_U3_HT_IRQS
@@ -1173,10 +1197,33 @@ static struct irq_domain_ops mpic_host_ops = {
         .xlate = mpic_host_xlate,
 };
 
+static u32 fsl_mpic_get_version(struct mpic *mpic)
+{
+        u32 brr1;
+
+        if (!(mpic->flags & MPIC_FSL))
+                return 0;
+
+        brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
+                        MPIC_FSL_BRR1);
+
+        return brr1 & MPIC_FSL_BRR1_VER;
+}
+
 /*
  * Exported functions
  */
 
+u32 fsl_mpic_primary_get_version(void)
+{
+        struct mpic *mpic = mpic_primary;
+
+        if (mpic)
+                return fsl_mpic_get_version(mpic);
+
+        return 0;
+}
+
 struct mpic * __init mpic_alloc(struct device_node *node,
                                 phys_addr_t phys_addr,
                                 unsigned int flags,
@@ -1323,7 +1370,6 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
 
         if (mpic->flags & MPIC_FSL) {
-                u32 brr1;
                 int ret;
 
                 /*
@@ -1334,9 +1380,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
                 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
                          MPIC_CPU_THISBASE, 0x1000);
 
-                brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                                MPIC_FSL_BRR1);
-                fsl_version = brr1 & MPIC_FSL_BRR1_VER;
+                fsl_version = fsl_mpic_get_version(mpic);
 
                 /* Error interrupt mask register (EIMR) is required for
                  * handling individual device error interrupts. EIMR
@@ -1526,9 +1570,7 @@ void __init mpic_init(struct mpic *mpic)
         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
 
         if (mpic->flags & MPIC_FSL) {
-                u32 brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
-                                      MPIC_FSL_BRR1);
-                u32 version = brr1 & MPIC_FSL_BRR1_VER;
+                u32 version = fsl_mpic_get_version(mpic);
 
                 /*
                  * Timer group B is present at the latest in MPIC 3.1 (e.g.
@@ -1999,6 +2041,8 @@ static struct syscore_ops mpic_syscore_ops = {
 static int mpic_init_sys(void)
 {
         register_syscore_ops(&mpic_syscore_ops);
+        subsys_system_register(&mpic_subsys, NULL);
+
         return 0;
 }
 
diff --git a/arch/powerpc/sysdev/mpic_timer.c b/arch/powerpc/sysdev/mpic_timer.c
new file mode 100644
index 000000000000..c06db92a4fb1
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_timer.c
@@ -0,0 +1,593 @@
+/*
+ * MPIC timer driver
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
+ *         Li Yang <leoli@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/syscore_ops.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/io.h>
+
+#include <asm/mpic_timer.h>
+
+#define FSL_GLOBAL_TIMER                0x1
+
+/* Clock Ratio
+ * Divide by 64 0x00000300
+ * Divide by 32 0x00000200
+ * Divide by 16 0x00000100
+ * Divide by  8 0x00000000 (Hardware default div)
+ */
+#define MPIC_TIMER_TCR_CLKDIV           0x00000300
+
+#define MPIC_TIMER_TCR_ROVR_OFFSET      24
+
+#define TIMER_STOP                      0x80000000
+#define TIMERS_PER_GROUP                4
+#define MAX_TICKS                       (~0U >> 1)
+#define MAX_TICKS_CASCADE               (~0U)
+#define TIMER_OFFSET(num)               (1 << (TIMERS_PER_GROUP - 1 - num))
+
+/* tv_usec should be less than ONE_SECOND, otherwise use tv_sec */
+#define ONE_SECOND                      1000000
+
+struct timer_regs {
+        u32     gtccr;
+        u32     res0[3];
+        u32     gtbcr;
+        u32     res1[3];
+        u32     gtvpr;
+        u32     res2[3];
+        u32     gtdr;
+        u32     res3[3];
+};
+
+struct cascade_priv {
+        u32 tcr_value;                  /* TCR register: CASC & ROVR value */
+        unsigned int cascade_map;       /* cascade map */
+        unsigned int timer_num;         /* cascade control timer */
+};
+
+struct timer_group_priv {
+        struct timer_regs __iomem       *regs;
+        struct mpic_timer               timer[TIMERS_PER_GROUP];
+        struct list_head                node;
+        unsigned int                    timerfreq;
+        unsigned int                    idle;
+        unsigned int                    flags;
+        spinlock_t                      lock;
+        void __iomem                    *group_tcr;
+};
+
+static struct cascade_priv cascade_timer[] = {
+        /* cascade timer 0 and 1 */
+        {0x1, 0xc, 0x1},
+        /* cascade timer 1 and 2 */
+        {0x2, 0x6, 0x2},
+        /* cascade timer 2 and 3 */
+        {0x4, 0x3, 0x3}
+};
+
+static LIST_HEAD(timer_group_list);
+
+static void convert_ticks_to_time(struct timer_group_priv *priv,
+                const u64 ticks, struct timeval *time)
+{
+        u64 tmp_sec;
+
+        time->tv_sec = (__kernel_time_t)div_u64(ticks, priv->timerfreq);
+        tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
+
+        time->tv_usec = (__kernel_suseconds_t)
+                div_u64((ticks - tmp_sec) * 1000000, priv->timerfreq);
+
+        return;
+}
+
+/* the time set by the user is converted to "ticks" */
+static int convert_time_to_ticks(struct timer_group_priv *priv,
+                const struct timeval *time, u64 *ticks)
+{
+        u64 max_value;          /* prevent u64 overflow */
+        u64 tmp = 0;
+
+        u64 tmp_sec;
+        u64 tmp_ms;
+        u64 tmp_us;
+
+        max_value = div_u64(ULLONG_MAX, priv->timerfreq);
+
+        if (time->tv_sec > max_value ||
+                        (time->tv_sec == max_value && time->tv_usec > 0))
+                return -EINVAL;
+
+        tmp_sec = (u64)time->tv_sec * (u64)priv->timerfreq;
+        tmp += tmp_sec;
+
+        tmp_ms = time->tv_usec / 1000;
+        tmp_ms = div_u64((u64)tmp_ms * (u64)priv->timerfreq, 1000);
+        tmp += tmp_ms;
+
+        tmp_us = time->tv_usec % 1000;
+        tmp_us = div_u64((u64)tmp_us * (u64)priv->timerfreq, 1000000);
+        tmp += tmp_us;
+
+        *ticks = tmp;
+
+        return 0;
+}
+
+/* detect whether there is a cascade timer available */
+static struct mpic_timer *detect_idle_cascade_timer(
+                                        struct timer_group_priv *priv)
+{
+        struct cascade_priv *casc_priv;
+        unsigned int map;
+        unsigned int array_size = ARRAY_SIZE(cascade_timer);
+        unsigned int num;
+        unsigned int i;
+        unsigned long flags;
+
+        casc_priv = cascade_timer;
+        for (i = 0; i < array_size; i++) {
+                spin_lock_irqsave(&priv->lock, flags);
+                map = casc_priv->cascade_map & priv->idle;
+                if (map == casc_priv->cascade_map) {
+                        num = casc_priv->timer_num;
+                        priv->timer[num].cascade_handle = casc_priv;
+
+                        /* set timer busy */
+                        priv->idle &= ~casc_priv->cascade_map;
+                        spin_unlock_irqrestore(&priv->lock, flags);
+                        return &priv->timer[num];
+                }
+                spin_unlock_irqrestore(&priv->lock, flags);
+                casc_priv++;
+        }
+
+        return NULL;
+}
+
+static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
+                unsigned int num)
+{
+        struct cascade_priv *casc_priv;
+        u32 tcr;
+        u32 tmp_ticks;
+        u32 rem_ticks;
+
+        /* set group tcr reg for cascade */
+        casc_priv = priv->timer[num].cascade_handle;
+        if (!casc_priv)
+                return -EINVAL;
+
+        tcr = casc_priv->tcr_value |
+                (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
+        setbits32(priv->group_tcr, tcr);
+
+        tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
+
+        out_be32(&priv->regs[num].gtccr, 0);
+        out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
+
+        out_be32(&priv->regs[num - 1].gtccr, 0);
+        out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
+
+        return 0;
+}
+
+static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
+                                        u64 ticks)
+{
+        struct mpic_timer *allocated_timer;
+
+        /* Two cascade timers: Support the maximum time */
+        const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
+        int ret;
+
+        if (ticks > max_ticks)
+                return NULL;
+
+        /* detect idle timer */
+        allocated_timer = detect_idle_cascade_timer(priv);
+        if (!allocated_timer)
+                return NULL;
+
+        /* set ticks to timer */
+        ret = set_cascade_timer(priv, ticks, allocated_timer->num);
+        if (ret < 0)
+                return NULL;
+
+        return allocated_timer;
+}
+
+static struct mpic_timer *get_timer(const struct timeval *time)
+{
+        struct timer_group_priv *priv;
+        struct mpic_timer *timer;
+
+        u64 ticks;
+        unsigned int num;
+        unsigned int i;
+        unsigned long flags;
+        int ret;
+
+        list_for_each_entry(priv, &timer_group_list, node) {
+                ret = convert_time_to_ticks(priv, time, &ticks);
+                if (ret < 0)
+                        return NULL;
+
+                if (ticks > MAX_TICKS) {
+                        if (!(priv->flags & FSL_GLOBAL_TIMER))
+                                return NULL;
+
+                        timer = get_cascade_timer(priv, ticks);
+                        if (!timer)
+                                continue;
+
+                        return timer;
+                }
+
+                for (i = 0; i < TIMERS_PER_GROUP; i++) {
+                        /* one timer: Reverse allocation */
+                        num = TIMERS_PER_GROUP - 1 - i;
+                        spin_lock_irqsave(&priv->lock, flags);
+                        if (priv->idle & (1 << i)) {
+                                /* set timer busy */
+                                priv->idle &= ~(1 << i);
+                                /* set ticks & stop timer */
+                                out_be32(&priv->regs[num].gtbcr,
+                                        ticks | TIMER_STOP);
+                                out_be32(&priv->regs[num].gtccr, 0);
+                                priv->timer[num].cascade_handle = NULL;
+                                spin_unlock_irqrestore(&priv->lock, flags);
+                                return &priv->timer[num];
+                        }
+                        spin_unlock_irqrestore(&priv->lock, flags);
+                }
+        }
+
+        return NULL;
+}
+
+/**
+ * mpic_start_timer - start hardware timer
+ * @handle: the timer to be started.
+ *
+ * It will do ->fn(->dev) callback from the hardware interrupt at
+ * the ->timeval point in the future.
+ */
+void mpic_start_timer(struct mpic_timer *handle)
+{
+        struct timer_group_priv *priv = container_of(handle,
+                        struct timer_group_priv, timer[handle->num]);
+
+        clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+}
+EXPORT_SYMBOL(mpic_start_timer);
+
+/**
+ * mpic_stop_timer - stop hardware timer
+ * @handle: the timer to be stoped
+ *
+ * The timer periodically generates an interrupt. Unless user stops the timer.
+ */
+void mpic_stop_timer(struct mpic_timer *handle)
+{
+        struct timer_group_priv *priv = container_of(handle,
+                        struct timer_group_priv, timer[handle->num]);
+        struct cascade_priv *casc_priv;
+
+        setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
+
+        casc_priv = priv->timer[handle->num].cascade_handle;
+        if (casc_priv) {
+                out_be32(&priv->regs[handle->num].gtccr, 0);
+                out_be32(&priv->regs[handle->num - 1].gtccr, 0);
+        } else {
+                out_be32(&priv->regs[handle->num].gtccr, 0);
+        }
+}
+EXPORT_SYMBOL(mpic_stop_timer);
+
+/**
+ * mpic_get_remain_time - get timer time
+ * @handle: the timer to be selected.
+ * @time: time for timer
+ *
+ * Query timer remaining time.
+ */
+void mpic_get_remain_time(struct mpic_timer *handle, struct timeval *time)
+{
+        struct timer_group_priv *priv = container_of(handle,
+                        struct timer_group_priv, timer[handle->num]);
+        struct cascade_priv *casc_priv;
+
+        u64 ticks;
+        u32 tmp_ticks;
+
+        casc_priv = priv->timer[handle->num].cascade_handle;
+        if (casc_priv) {
+                tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
+                ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
+                tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
+                ticks += tmp_ticks;
+        } else {
+                ticks = in_be32(&priv->regs[handle->num].gtccr);
+        }
+
+        convert_ticks_to_time(priv, ticks, time);
+}
+EXPORT_SYMBOL(mpic_get_remain_time);
+
+/**
+ * mpic_free_timer - free hardware timer
+ * @handle: the timer to be removed.
+ *
+ * Free the timer.
+ *
+ * Note: can not be used in interrupt context.
+ */
+void mpic_free_timer(struct mpic_timer *handle)
+{
+        struct timer_group_priv *priv = container_of(handle,
+                        struct timer_group_priv, timer[handle->num]);
+
+        struct cascade_priv *casc_priv;
+        unsigned long flags;
+
+        mpic_stop_timer(handle);
+
+        casc_priv = priv->timer[handle->num].cascade_handle;
+
+        free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
+
+        spin_lock_irqsave(&priv->lock, flags);
+        if (casc_priv) {
+                u32 tcr;
+                tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
+                                        MPIC_TIMER_TCR_ROVR_OFFSET);
+                clrbits32(priv->group_tcr, tcr);
+                priv->idle |= casc_priv->cascade_map;
+                priv->timer[handle->num].cascade_handle = NULL;
+        } else {
+                priv->idle |= TIMER_OFFSET(handle->num);
+        }
+        spin_unlock_irqrestore(&priv->lock, flags);
+}
+EXPORT_SYMBOL(mpic_free_timer);
+
+/**
+ * mpic_request_timer - get a hardware timer
+ * @fn: interrupt handler function
+ * @dev: callback function of the data
+ * @time: time for timer
+ *
+ * This executes the "request_irq", returning NULL
+ * else "handle" on success.
+ */
+struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
+                                        const struct timeval *time)
+{
+        struct mpic_timer *allocated_timer;
+        int ret;
+
+        if (list_empty(&timer_group_list))
+                return NULL;
+
+        if (!(time->tv_sec + time->tv_usec) ||
+                        time->tv_sec < 0 || time->tv_usec < 0)
+                return NULL;
+
+        if (time->tv_usec > ONE_SECOND)
+                return NULL;
+
+        allocated_timer = get_timer(time);
+        if (!allocated_timer)
+                return NULL;
+
+        ret = request_irq(allocated_timer->irq, fn,
+                        IRQF_TRIGGER_LOW, "global-timer", dev);
+        if (ret) {
+                mpic_free_timer(allocated_timer);
+                return NULL;
+        }
+
+        allocated_timer->dev = dev;
+
+        return allocated_timer;
+}
+EXPORT_SYMBOL(mpic_request_timer);
+
+static int timer_group_get_freq(struct device_node *np,
+                        struct timer_group_priv *priv)
+{
+        u32 div;
+
+        if (priv->flags & FSL_GLOBAL_TIMER) {
+                struct device_node *dn;
+
+                dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
+                if (dn) {
+                        of_property_read_u32(dn, "clock-frequency",
+                                        &priv->timerfreq);
+                        of_node_put(dn);
+                }
+        }
+
+        if (priv->timerfreq <= 0)
+                return -EINVAL;
+
+        if (priv->flags & FSL_GLOBAL_TIMER) {
+                div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
+                priv->timerfreq /= div;
+        }
+
+        return 0;
+}
+
+static int timer_group_get_irq(struct device_node *np,
+                struct timer_group_priv *priv)
+{
+        const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
+        const u32 *p;
+        u32 offset;
+        u32 count;
+
+        unsigned int i;
+        unsigned int j;
+        unsigned int irq_index = 0;
+        unsigned int irq;
+        int len;
+
+        p = of_get_property(np, "fsl,available-ranges", &len);
+        if (p && len % (2 * sizeof(u32)) != 0) {
+                pr_err("%s: malformed available-ranges property.\n",
+                                np->full_name);
+                return -EINVAL;
+        }
+
+        if (!p) {
+                p = all_timer;
+                len = sizeof(all_timer);
+        }
+
+        len /= 2 * sizeof(u32);
+
+        for (i = 0; i < len; i++) {
+                offset = p[i * 2];
+                count = p[i * 2 + 1];
+                for (j = 0; j < count; j++) {
+                        irq = irq_of_parse_and_map(np, irq_index);
+                        if (!irq) {
+                                pr_err("%s: irq parse and map failed.\n",
+                                                np->full_name);
+                                return -EINVAL;
+                        }
+
+                        /* Set timer idle */
+                        priv->idle |= TIMER_OFFSET((offset + j));
+                        priv->timer[offset + j].irq = irq;
+                        priv->timer[offset + j].num = offset + j;
+                        irq_index++;
+                }
+        }
+
+        return 0;
+}
+
+static void timer_group_init(struct device_node *np)
+{
+        struct timer_group_priv *priv;
+        unsigned int i = 0;
+        int ret;
+
+        priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
+        if (!priv) {
+                pr_err("%s: cannot allocate memory for group.\n",
+                                np->full_name);
+                return;
+        }
+
+        if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
+                priv->flags |= FSL_GLOBAL_TIMER;
+
+        priv->regs = of_iomap(np, i++);
+        if (!priv->regs) {
+                pr_err("%s: cannot ioremap timer register address.\n",
+                                np->full_name);
+                goto out;
+        }
+
+        if (priv->flags & FSL_GLOBAL_TIMER) {
+                priv->group_tcr = of_iomap(np, i++);
+                if (!priv->group_tcr) {
+                        pr_err("%s: cannot ioremap tcr address.\n",
+                                        np->full_name);
+                        goto out;
+                }
+        }
+
+        ret = timer_group_get_freq(np, priv);
+        if (ret < 0) {
+                pr_err("%s: cannot get timer frequency.\n", np->full_name);
+                goto out;
+        }
+
+        ret = timer_group_get_irq(np, priv);
+        if (ret < 0) {
+                pr_err("%s: cannot get timer irqs.\n", np->full_name);
+                goto out;
+        }
+
+        spin_lock_init(&priv->lock);
+
+        /* Init FSL timer hardware */
+        if (priv->flags & FSL_GLOBAL_TIMER)
+                setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+
+        list_add_tail(&priv->node, &timer_group_list);
+
+        return;
+
+out:
+        if (priv->regs)
+                iounmap(priv->regs);
+
+        if (priv->group_tcr)
+                iounmap(priv->group_tcr);
+
+        kfree(priv);
+}
+
+static void mpic_timer_resume(void)
+{
+        struct timer_group_priv *priv;
+
+        list_for_each_entry(priv, &timer_group_list, node) {
+                /* Init FSL timer hardware */
+                if (priv->flags & FSL_GLOBAL_TIMER)
+                        setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
+        }
+}
+
+static const struct of_device_id mpic_timer_ids[] = {
+        { .compatible = "fsl,mpic-global-timer", },
+        {},
+};
+
+static struct syscore_ops mpic_timer_syscore_ops = {
+        .resume = mpic_timer_resume,
+};
+
+static int __init mpic_timer_init(void)
+{
+        struct device_node *np = NULL;
+
+        for_each_matching_node(np, mpic_timer_ids)
+                timer_group_init(np);
+
+        register_syscore_ops(&mpic_timer_syscore_ops);
+
+        if (list_empty(&timer_group_list))
+                return -ENODEV;
+
+        return 0;
+}
+subsys_initcall(mpic_timer_init);
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index da183c5a103c..22f75b504f7f 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -301,7 +301,6 @@ config HOTPLUG_CPU
         def_bool y
         prompt "Support for hot-pluggable CPUs"
         depends on SMP
-        select HOTPLUG
         help
           Say Y here to be able to turn CPUs off and on. CPUs
           can be controlled through /sys/devices/system/cpu/cpu#.
diff --git a/arch/s390/appldata/appldata_mem.c b/arch/s390/appldata/appldata_mem.c
index 7ef60b52d6e0..42be53743133 100644
--- a/arch/s390/appldata/appldata_mem.c
+++ b/arch/s390/appldata/appldata_mem.c
@@ -32,7 +32,7 @@
  * book:
  * http://oss.software.ibm.com/developerworks/opensource/linux390/index.shtml
  */
-static struct appldata_mem_data {
+struct appldata_mem_data {
         u64 timestamp;
         u32 sync_count_1;       /* after VM collected the record data, */
         u32 sync_count_2;       /* sync_count_1 and sync_count_2 should be the
@@ -63,7 +63,7 @@ static struct appldata_mem_data {
         u64 pgmajfault;         /* page faults (major only) */
 // <-- New in 2.6
 
-} __attribute__((packed)) appldata_mem_data;
+} __packed;
 
 
 /*
@@ -118,7 +118,6 @@ static struct appldata_ops ops = {
         .record_nr = APPLDATA_RECORD_MEM_ID,
         .size      = sizeof(struct appldata_mem_data),
         .callback  = &appldata_get_mem_data,
-        .data      = &appldata_mem_data,
         .owner     = THIS_MODULE,
         .mod_lvl   = {0xF0, 0xF0},              /* EBCDIC "00" */
 };
@@ -131,7 +130,17 @@ static struct appldata_ops ops = {
  */
 static int __init appldata_mem_init(void)
 {
-        return appldata_register_ops(&ops);
+        int ret;
+
+        ops.data = kzalloc(sizeof(struct appldata_mem_data), GFP_KERNEL);
+        if (!ops.data)
+                return -ENOMEM;
+
+        ret = appldata_register_ops(&ops);
+        if (ret)
+                kfree(ops.data);
+
+        return ret;
 }
 
 /*
@@ -142,6 +151,7 @@ static int __init appldata_mem_init(void)
 static void __exit appldata_mem_exit(void)
 {
         appldata_unregister_ops(&ops);
+        kfree(ops.data);
 }
 
 
diff --git a/arch/s390/appldata/appldata_net_sum.c b/arch/s390/appldata/appldata_net_sum.c
index 2d224b945355..66037d2622b4 100644
--- a/arch/s390/appldata/appldata_net_sum.c
+++ b/arch/s390/appldata/appldata_net_sum.c
@@ -29,7 +29,7 @@
  * book:
  * http://oss.software.ibm.com/developerworks/opensource/linux390/index.shtml
  */
-static struct appldata_net_sum_data {
+struct appldata_net_sum_data {
         u64 timestamp;
         u32 sync_count_1;       /* after VM collected the record data, */
         u32 sync_count_2;       /* sync_count_1 and sync_count_2 should be the
@@ -51,7 +51,7 @@ static struct appldata_net_sum_data {
         u64 rx_dropped;         /* no space in linux buffers     */
         u64 tx_dropped;         /* no space available in linux   */
         u64 collisions;         /* collisions while transmitting */
-} __attribute__((packed)) appldata_net_sum_data;
+} __packed;
 
 
 /*
@@ -121,7 +121,6 @@ static struct appldata_ops ops = {
         .record_nr = APPLDATA_RECORD_NET_SUM_ID,
         .size      = sizeof(struct appldata_net_sum_data),
         .callback  = &appldata_get_net_sum_data,
-        .data      = &appldata_net_sum_data,
         .owner     = THIS_MODULE,
         .mod_lvl   = {0xF0, 0xF0},              /* EBCDIC "00" */
 };
@@ -134,7 +133,17 @@ static struct appldata_ops ops = {
  */
 static int __init appldata_net_init(void)
 {
-        return appldata_register_ops(&ops);
+        int ret;
+
+        ops.data = kzalloc(sizeof(struct appldata_net_sum_data), GFP_KERNEL);
+        if (!ops.data)
+                return -ENOMEM;
+
+        ret = appldata_register_ops(&ops);
+        if (ret)
+                kfree(ops.data);
+
+        return ret;
 }
 
 /*
@@ -145,6 +154,7 @@ static int __init appldata_net_init(void)
 static void __exit appldata_net_exit(void)
 {
         appldata_unregister_ops(&ops);
+        kfree(ops.data);
 }
 
 
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index 7fd3690b6760..138893e5f736 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -651,9 +651,7 @@ static int hypfs_create_cpu_files(struct super_block *sb,
         }
         diag224_idx2name(cpu_info__ctidx(diag204_info_type, cpu_info), buffer);
         rc = hypfs_create_str(sb, cpu_dir, "type", buffer);
-        if (IS_ERR(rc))
-                return PTR_ERR(rc);
-        return 0;
+        return PTR_RET(rc);
 }
 
 static void *hypfs_create_lpar_files(struct super_block *sb,
@@ -702,9 +700,7 @@ static int hypfs_create_phys_cpu_files(struct super_block *sb,
                 return PTR_ERR(rc);
         diag224_idx2name(phys_cpu__ctidx(diag204_info_type, cpu_info), buffer);
         rc = hypfs_create_str(sb, cpu_dir, "type", buffer);
-        if (IS_ERR(rc))
-                return PTR_ERR(rc);
-        return 0;
+        return PTR_RET(rc);
 }
 
 static void *hypfs_create_phys_files(struct super_block *sb,
diff --git a/arch/s390/include/asm/airq.h b/arch/s390/include/asm/airq.h
index 9819891ed7a2..4066cee0c2d2 100644
--- a/arch/s390/include/asm/airq.h
+++ b/arch/s390/include/asm/airq.h
@@ -9,9 +9,18 @@
 #ifndef _ASM_S390_AIRQ_H
 #define _ASM_S390_AIRQ_H
 
-typedef void (*adapter_int_handler_t)(void *, void *);
+struct airq_struct {
+        struct hlist_node list;         /* Handler queueing. */
+        void (*handler)(struct airq_struct *);  /* Thin-interrupt handler */
+        u8 *lsi_ptr;                    /* Local-Summary-Indicator pointer */
+        u8 lsi_mask;                    /* Local-Summary-Indicator mask */
+        u8 isc;                         /* Interrupt-subclass */
+        u8 flags;
+};
 
-void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8);
-void s390_unregister_adapter_interrupt(void *, u8);
+#define AIRQ_PTR_ALLOCATED      0x01
+
+int register_adapter_interrupt(struct airq_struct *airq);
+void unregister_adapter_interrupt(struct airq_struct *airq);
 
 #endif /* _ASM_S390_AIRQ_H */
diff --git a/arch/s390/include/asm/dma-mapping.h b/arch/s390/include/asm/dma-mapping.h
index 886ac7d4937a..3fbc67d9e197 100644
--- a/arch/s390/include/asm/dma-mapping.h
+++ b/arch/s390/include/asm/dma-mapping.h
@@ -50,9 +50,10 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
         struct dma_map_ops *dma_ops = get_dma_ops(dev);
 
+        debug_dma_mapping_error(dev, dma_addr);
         if (dma_ops->mapping_error)
                 return dma_ops->mapping_error(dev, dma_addr);
-        return (dma_addr == 0UL);
+        return dma_addr == DMA_ERROR_CODE;
 }
 
 static inline void *dma_alloc_coherent(struct device *dev, size_t size,
diff --git a/arch/s390/include/asm/facility.h b/arch/s390/include/asm/facility.h
index 2ee66a65f2d4..0aa6a7ed95a3 100644
--- a/arch/s390/include/asm/facility.h
+++ b/arch/s390/include/asm/facility.h
@@ -13,6 +13,16 @@
 
 #define MAX_FACILITY_BIT (256*8)        /* stfle_fac_list has 256 bytes */
 
+static inline int __test_facility(unsigned long nr, void *facilities)
+{
+        unsigned char *ptr;
+
+        if (nr >= MAX_FACILITY_BIT)
+                return 0;
+        ptr = (unsigned char *) facilities + (nr >> 3);
+        return (*ptr & (0x80 >> (nr & 7))) != 0;
+}
+
 /*
  * The test_facility function uses the bit odering where the MSB is bit 0.
  * That makes it easier to query facility bits with the bit number as
@@ -20,12 +30,7 @@
  */
 static inline int test_facility(unsigned long nr)
 {
-        unsigned char *ptr;
-
-        if (nr >= MAX_FACILITY_BIT)
-                return 0;
-        ptr = (unsigned char *) &S390_lowcore.stfle_fac_list + (nr >> 3);
-        return (*ptr & (0x80 >> (nr & 7))) != 0;
+        return __test_facility(nr, &S390_lowcore.stfle_fac_list);
 }
 
 /**
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index fd9be010f9b2..cd6b9ee7b69c 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -13,28 +13,6 @@
 #include <asm/page.h>
 #include <asm/pci_io.h>
 
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are pretty trivial
- */
-static inline unsigned long virt_to_phys(volatile void * address)
-{
-        unsigned long real_address;
-        asm volatile(
-                 "      lra     %0,0(%1)\n"
-                 "      jz      0f\n"
-                 "      la      %0,0\n"
-                 "0:"
-                 : "=a" (real_address) : "a" (address) : "cc");
-        return real_address;
-}
-#define virt_to_phys virt_to_phys
-
-static inline void * phys_to_virt(unsigned long address)
-{
-        return (void *) address;
-}
-
 void *xlate_dev_mem_ptr(unsigned long phys);
 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
 void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 16bd5d169cdb..3238d4004e84 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -62,13 +62,20 @@ struct sca_block {
 #define CPUSTAT_MCDS       0x00000100
 #define CPUSTAT_SM         0x00000080
 #define CPUSTAT_G          0x00000008
+#define CPUSTAT_GED        0x00000004
 #define CPUSTAT_J          0x00000002
 #define CPUSTAT_P          0x00000001
 
 struct kvm_s390_sie_block {
         atomic_t cpuflags;              /* 0x0000 */
         __u32   prefix;                 /* 0x0004 */
-        __u8    reserved8[32];          /* 0x0008 */
+        __u8    reserved08[4];          /* 0x0008 */
+#define PROG_IN_SIE (1<<0)
+        __u32   prog0c;                 /* 0x000c */
+        __u8    reserved10[16];         /* 0x0010 */
+#define PROG_BLOCK_SIE 0x00000001
+        atomic_t prog20;                /* 0x0020 */
+        __u8    reserved24[4];          /* 0x0024 */
         __u64   cputm;                  /* 0x0028 */
         __u64   ckc;                    /* 0x0030 */
         __u64   epoch;                  /* 0x0038 */
@@ -90,7 +97,8 @@ struct kvm_s390_sie_block {
         __u32   scaoh;                  /* 0x005c */
         __u8    reserved60;             /* 0x0060 */
         __u8    ecb;                    /* 0x0061 */
-        __u8    reserved62[2];          /* 0x0062 */
+        __u8    ecb2;                   /* 0x0062 */
+        __u8    reserved63[1];          /* 0x0063 */
         __u32   scaol;                  /* 0x0064 */
         __u8    reserved68[4];          /* 0x0068 */
         __u32   todpr;                  /* 0x006c */
@@ -130,6 +138,7 @@ struct kvm_vcpu_stat {
         u32 deliver_program_int;
         u32 deliver_io_int;
         u32 exit_wait_state;
+        u32 instruction_pfmf;
         u32 instruction_stidp;
         u32 instruction_spx;
         u32 instruction_stpx;
@@ -166,7 +175,7 @@ struct kvm_s390_ext_info {
 };
 
 #define PGM_OPERATION            0x01
-#define PGM_PRIVILEGED_OPERATION 0x02
+#define PGM_PRIVILEGED_OP        0x02
 #define PGM_EXECUTE              0x03
 #define PGM_PROTECTION           0x04
 #define PGM_ADDRESSING           0x05
@@ -219,7 +228,7 @@ struct kvm_s390_local_interrupt {
         atomic_t active;
         struct kvm_s390_float_interrupt *float_int;
         int timer_due; /* event indicator for waitqueue below */
-        wait_queue_head_t wq;
+        wait_queue_head_t *wq;
         atomic_t *cpuflags;
         unsigned int action_bits;
 };
@@ -266,4 +275,5 @@ struct kvm_arch{
 };
 
 extern int sie64a(struct kvm_s390_sie_block *, u64 *);
+extern char sie_exit;
 #endif
diff --git a/arch/s390/include/asm/pci.h b/arch/s390/include/asm/pci.h
index 6c1801235db9..6e577ba0e5da 100644
--- a/arch/s390/include/asm/pci.h
+++ b/arch/s390/include/asm/pci.h
@@ -120,7 +120,6 @@ struct zpci_dev {
 
         struct dentry   *debugfs_dev;
         struct dentry   *debugfs_perf;
-        struct dentry   *debugfs_debug;
 };
 
 struct pci_hp_callback_ops {
@@ -143,7 +142,6 @@ int zpci_enable_device(struct zpci_dev *);
 int zpci_disable_device(struct zpci_dev *);
 void zpci_stop_device(struct zpci_dev *);
 void zpci_free_device(struct zpci_dev *);
-int zpci_scan_device(struct zpci_dev *);
 int zpci_register_ioat(struct zpci_dev *, u8, u64, u64, u64);
 int zpci_unregister_ioat(struct zpci_dev *, u8);
 
diff --git a/arch/s390/include/asm/perf_event.h b/arch/s390/include/asm/perf_event.h
index 5f0173a31693..1141fb3e7b21 100644
--- a/arch/s390/include/asm/perf_event.h
+++ b/arch/s390/include/asm/perf_event.h
@@ -14,3 +14,13 @@
 /* Per-CPU flags for PMU states */
 #define PMU_F_RESERVED                  0x1000
 #define PMU_F_ENABLED                   0x2000
+
+#ifdef CONFIG_64BIT
+
+/* Perf callbacks */
+struct pt_regs;
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs) perf_misc_flags(regs)
+
+#endif /* CONFIG_64BIT */
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 590c3219c634..e1408ddb94f8 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -22,6 +22,9 @@ unsigned long *page_table_alloc(struct mm_struct *, unsigned long);
 void page_table_free(struct mm_struct *, unsigned long *);
 void page_table_free_rcu(struct mmu_gather *, unsigned long *);
 
+int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
+                          unsigned long key, bool nq);
+
 static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
 {
         typedef struct { char _[n]; } addrtype;
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index ac01463038f1..75fb726de91f 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -58,9 +58,6 @@ extern unsigned long zero_page_mask;
 #define __HAVE_COLOR_ZERO_PAGE
 
 /* TODO: s390 cannot support io_remap_pfn_range... */
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)                \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #endif /* !__ASSEMBLY__ */
 
 /*
@@ -299,18 +296,16 @@ extern unsigned long MODULES_END;
 #define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
 
 /* Page status table bits for virtualization */
-#define RCP_ACC_BITS    0xf0000000UL
-#define RCP_FP_BIT      0x08000000UL
-#define RCP_PCL_BIT     0x00800000UL
-#define RCP_HR_BIT      0x00400000UL
-#define RCP_HC_BIT      0x00200000UL
-#define RCP_GR_BIT      0x00040000UL
-#define RCP_GC_BIT      0x00020000UL
-#define RCP_IN_BIT      0x00002000UL    /* IPTE notify bit */
-
-/* User dirty / referenced bit for KVM's migration feature */
-#define KVM_UR_BIT      0x00008000UL
-#define KVM_UC_BIT      0x00004000UL
+#define PGSTE_ACC_BITS  0xf0000000UL
+#define PGSTE_FP_BIT    0x08000000UL
+#define PGSTE_PCL_BIT   0x00800000UL
+#define PGSTE_HR_BIT    0x00400000UL
+#define PGSTE_HC_BIT    0x00200000UL
+#define PGSTE_GR_BIT    0x00040000UL
+#define PGSTE_GC_BIT    0x00020000UL
+#define PGSTE_UR_BIT    0x00008000UL
+#define PGSTE_UC_BIT    0x00004000UL    /* user dirty (migration) */
+#define PGSTE_IN_BIT    0x00002000UL    /* IPTE notify bit */
 
 #else /* CONFIG_64BIT */
 
@@ -367,18 +362,16 @@ extern unsigned long MODULES_END;
                                  | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
 
 /* Page status table bits for virtualization */
-#define RCP_ACC_BITS    0xf000000000000000UL
-#define RCP_FP_BIT      0x0800000000000000UL
-#define RCP_PCL_BIT     0x0080000000000000UL
-#define RCP_HR_BIT      0x0040000000000000UL
-#define RCP_HC_BIT      0x0020000000000000UL
-#define RCP_GR_BIT      0x0004000000000000UL
-#define RCP_GC_BIT      0x0002000000000000UL
-#define RCP_IN_BIT      0x0000200000000000UL    /* IPTE notify bit */
-
-/* User dirty / referenced bit for KVM's migration feature */
-#define KVM_UR_BIT      0x0000800000000000UL
-#define KVM_UC_BIT      0x0000400000000000UL
+#define PGSTE_ACC_BITS  0xf000000000000000UL
+#define PGSTE_FP_BIT    0x0800000000000000UL
+#define PGSTE_PCL_BIT   0x0080000000000000UL
+#define PGSTE_HR_BIT    0x0040000000000000UL
+#define PGSTE_HC_BIT    0x0020000000000000UL
+#define PGSTE_GR_BIT    0x0004000000000000UL
+#define PGSTE_GC_BIT    0x0002000000000000UL
+#define PGSTE_UR_BIT    0x0000800000000000UL
+#define PGSTE_UC_BIT    0x0000400000000000UL    /* user dirty (migration) */
+#define PGSTE_IN_BIT    0x0000200000000000UL    /* IPTE notify bit */
 
 #endif /* CONFIG_64BIT */
 
@@ -618,12 +611,12 @@ static inline pgste_t pgste_get_lock(pte_t *ptep)
         asm(
                 "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       nihh    %0,0xff7f\n"    /* clear RCP_PCL_BIT in old */
-                "       oihh    %1,0x0080\n"    /* set RCP_PCL_BIT in new */
+                "       nihh    %0,0xff7f\n"    /* clear PCL bit in old */
+                "       oihh    %1,0x0080\n"    /* set PCL bit in new */
                 "       csg     %0,%1,%2\n"
                 "       jl      0b\n"
                 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
-                : "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
 #endif
         return __pgste(new);
 }
@@ -632,14 +625,22 @@ static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
         asm(
-                "       nihh    %1,0xff7f\n"    /* clear RCP_PCL_BIT */
+                "       nihh    %1,0xff7f\n"    /* clear PCL bit */
                 "       stg     %1,%0\n"
                 : "=Q" (ptep[PTRS_PER_PTE])
-                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
+                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
+                : "cc", "memory");
         preempt_enable();
 #endif
 }
 
+static inline void pgste_set(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
+#endif
+}
+
 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
@@ -657,14 +658,14 @@ static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
         else if (bits)
                 page_reset_referenced(address);
         /* Transfer page changed & referenced bit to guest bits in pgste */
-        pgste_val(pgste) |= bits << 48;         /* RCP_GR_BIT & RCP_GC_BIT */
+        pgste_val(pgste) |= bits << 48;         /* GR bit & GC bit */
         /* Get host changed & referenced bits from pgste */
-        bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
+        bits |= (pgste_val(pgste) & (PGSTE_HR_BIT | PGSTE_HC_BIT)) >> 52;
         /* Transfer page changed & referenced bit to kvm user bits */
-        pgste_val(pgste) |= bits << 45;         /* KVM_UR_BIT & KVM_UC_BIT */
+        pgste_val(pgste) |= bits << 45;         /* PGSTE_UR_BIT & PGSTE_UC_BIT */
         /* Clear relevant host bits in pgste. */
-        pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
-        pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
+        pgste_val(pgste) &= ~(PGSTE_HR_BIT | PGSTE_HC_BIT);
+        pgste_val(pgste) &= ~(PGSTE_ACC_BITS | PGSTE_FP_BIT);
         /* Copy page access key and fetch protection bit to pgste */
         pgste_val(pgste) |=
                 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
@@ -685,15 +686,15 @@ static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
         /* Get referenced bit from storage key */
         young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
         if (young)
-                pgste_val(pgste) |= RCP_GR_BIT;
+                pgste_val(pgste) |= PGSTE_GR_BIT;
         /* Get host referenced bit from pgste */
-        if (pgste_val(pgste) & RCP_HR_BIT) {
-                pgste_val(pgste) &= ~RCP_HR_BIT;
+        if (pgste_val(pgste) & PGSTE_HR_BIT) {
+                pgste_val(pgste) &= ~PGSTE_HR_BIT;
                 young = 1;
         }
         /* Transfer referenced bit to kvm user bits and pte */
         if (young) {
-                pgste_val(pgste) |= KVM_UR_BIT;
+                pgste_val(pgste) |= PGSTE_UR_BIT;
                 pte_val(*ptep) |= _PAGE_SWR;
         }
 #endif
@@ -704,17 +705,19 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
 {
 #ifdef CONFIG_PGSTE
         unsigned long address;
-        unsigned long okey, nkey;
+        unsigned long nkey;
 
         if (pte_val(entry) & _PAGE_INVALID)
                 return;
+        VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
         address = pte_val(entry) & PAGE_MASK;
-        okey = nkey = page_get_storage_key(address);
-        nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
-        /* Set page access key and fetch protection bit from pgste */
-        nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
-        if (okey != nkey)
-                page_set_storage_key(address, nkey, 0);
+        /*
+         * Set page access key and fetch protection bit from pgste.
+         * The guest C/R information is still in the PGSTE, set real
+         * key C/R to 0.
+         */
+        nkey = (pgste_val(pgste) & (PGSTE_ACC_BITS | PGSTE_FP_BIT)) >> 56;
+        page_set_storage_key(address, nkey, 0);
 #endif
 }
 
@@ -743,6 +746,7 @@ struct gmap {
         struct mm_struct *mm;
         unsigned long *table;
         unsigned long asce;
+        void *private;
         struct list_head crst_list;
 };
 
@@ -801,8 +805,8 @@ static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
                                         pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
-        if (pgste_val(pgste) & RCP_IN_BIT) {
-                pgste_val(pgste) &= ~RCP_IN_BIT;
+        if (pgste_val(pgste) & PGSTE_IN_BIT) {
+                pgste_val(pgste) &= ~PGSTE_IN_BIT;
                 gmap_do_ipte_notify(mm, addr, ptep);
         }
 #endif
@@ -970,8 +974,8 @@ static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
         if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
                 pgste = pgste_update_all(ptep, pgste);
-                dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
-                pgste_val(pgste) &= ~KVM_UC_BIT;
+                dirty = !!(pgste_val(pgste) & PGSTE_UC_BIT);
+                pgste_val(pgste) &= ~PGSTE_UC_BIT;
                 pgste_set_unlock(ptep, pgste);
                 return dirty;
         }
@@ -990,8 +994,8 @@ static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
         if (mm_has_pgste(mm)) {
                 pgste = pgste_get_lock(ptep);
                 pgste = pgste_update_young(ptep, pgste);
-                young = !!(pgste_val(pgste) & KVM_UR_BIT);
-                pgste_val(pgste) &= ~KVM_UR_BIT;
+                young = !!(pgste_val(pgste) & PGSTE_UR_BIT);
+                pgste_val(pgste) &= ~PGSTE_UR_BIT;
                 pgste_set_unlock(ptep, pgste);
         }
         return young;
@@ -1099,8 +1103,10 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
         if (!mm_exclusive(mm))
                 __ptep_ipte(address, ptep);
 
-        if (mm_has_pgste(mm))
+        if (mm_has_pgste(mm)) {
                 pgste = pgste_update_all(&pte, pgste);
+                pgste_set(ptep, pgste);
+        }
         return pte;
 }
 
@@ -1358,10 +1364,11 @@ static inline pmd_t pmd_mkwrite(pmd_t pmd)
 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 
 #define __HAVE_ARCH_PGTABLE_DEPOSIT
-extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
+extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                       pgtable_t pgtable);
 
 #define __HAVE_ARCH_PGTABLE_WITHDRAW
-extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
+extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 
 static inline int pmd_trans_splitting(pmd_t pmd)
 {
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index 559512a455da..52b56533c57c 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -24,6 +24,7 @@ struct pt_regs
         unsigned long gprs[NUM_GPRS];
         unsigned long orig_gpr2;
         unsigned int int_code;
+        unsigned int int_parm;
         unsigned long int_parm_long;
 };
 
diff --git a/arch/s390/include/uapi/asm/Kbuild b/arch/s390/include/uapi/asm/Kbuild
index 9ccd1905bdad..6a9a9eb645f5 100644
--- a/arch/s390/include/uapi/asm/Kbuild
+++ b/arch/s390/include/uapi/asm/Kbuild
@@ -35,6 +35,7 @@ header-y += siginfo.h
 header-y += signal.h
 header-y += socket.h
 header-y += sockios.h
+header-y += sclp_ctl.h
 header-y += stat.h
 header-y += statfs.h
 header-y += swab.h
diff --git a/arch/s390/include/uapi/asm/chsc.h b/arch/s390/include/uapi/asm/chsc.h
index 1c6a7f85a581..65dc694725a8 100644
--- a/arch/s390/include/uapi/asm/chsc.h
+++ b/arch/s390/include/uapi/asm/chsc.h
@@ -29,6 +29,16 @@ struct chsc_async_area {
         __u8 data[CHSC_SIZE - sizeof(struct chsc_async_header)];
 } __attribute__ ((packed));
 
+struct chsc_header {
+        __u16 length;
+        __u16 code;
+} __attribute__ ((packed));
+
+struct chsc_sync_area {
+        struct chsc_header header;
+        __u8 data[CHSC_SIZE - sizeof(struct chsc_header)];
+} __attribute__ ((packed));
+
 struct chsc_response_struct {
         __u16 length;
         __u16 code;
@@ -126,5 +136,8 @@ struct chsc_cpd_info {
 #define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list)
 #define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
 #define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
+#define CHSC_START_SYNC _IOWR(CHSC_IOCTL_MAGIC, 0x89, struct chsc_sync_area)
+#define CHSC_ON_CLOSE_SET _IOWR(CHSC_IOCTL_MAGIC, 0x8a, struct chsc_async_area)
+#define CHSC_ON_CLOSE_REMOVE _IO(CHSC_IOCTL_MAGIC, 0x8b)
 
 #endif
diff --git a/arch/s390/include/uapi/asm/dasd.h b/arch/s390/include/uapi/asm/dasd.h
index 38eca3ba40e2..5812a3b2df9e 100644
--- a/arch/s390/include/uapi/asm/dasd.h
+++ b/arch/s390/include/uapi/asm/dasd.h
@@ -261,6 +261,10 @@ struct dasd_snid_ioctl_data {
 #define BIODASDQUIESCE _IO(DASD_IOCTL_LETTER,6) 
 /* Resume IO on device */
 #define BIODASDRESUME  _IO(DASD_IOCTL_LETTER,7) 
+/* Abort all I/O on a device */
+#define BIODASDABORTIO _IO(DASD_IOCTL_LETTER, 240)
+/* Allow I/O on a device */
+#define BIODASDALLOWIO _IO(DASD_IOCTL_LETTER, 241)
 
 
 /* retrieve API version number */
diff --git a/arch/s390/include/uapi/asm/sclp_ctl.h b/arch/s390/include/uapi/asm/sclp_ctl.h
new file mode 100644
index 000000000000..f2818613ee41
--- /dev/null
+++ b/arch/s390/include/uapi/asm/sclp_ctl.h
@@ -0,0 +1,24 @@
+/*
+ * IOCTL interface for SCLP
+ *
+ * Copyright IBM Corp. 2012
+ *
+ * Author: Michael Holzheu <holzheu@linux.vnet.ibm.com>
+ */
+
+#ifndef _ASM_SCLP_CTL_H
+#define _ASM_SCLP_CTL_H
+
+#include <linux/types.h>
+
+struct sclp_ctl_sccb {
+        __u32   cmdw;
+        __u64   sccb;
+} __attribute__((packed));
+
+#define SCLP_CTL_IOCTL_MAGIC 0x10
+
+#define SCLP_CTL_SCCB \
+        _IOWR(SCLP_CTL_IOCTL_MAGIC, 0x10, struct sclp_ctl_sccb)
+
+#endif
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 7a82f9f70100..2416138ebd3e 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -7,6 +7,7 @@
 #define ASM_OFFSETS_C
 
 #include <linux/kbuild.h>
+#include <linux/kvm_host.h>
 #include <linux/sched.h>
 #include <asm/cputime.h>
 #include <asm/vdso.h>
@@ -47,6 +48,7 @@ int main(void)
         DEFINE(__PT_GPRS, offsetof(struct pt_regs, gprs));
         DEFINE(__PT_ORIG_GPR2, offsetof(struct pt_regs, orig_gpr2));
         DEFINE(__PT_INT_CODE, offsetof(struct pt_regs, int_code));
+        DEFINE(__PT_INT_PARM, offsetof(struct pt_regs, int_parm));
         DEFINE(__PT_INT_PARM_LONG, offsetof(struct pt_regs, int_parm_long));
         DEFINE(__PT_SIZE, sizeof(struct pt_regs));
         BLANK();
@@ -161,6 +163,8 @@ int main(void)
         DEFINE(__LC_PGM_TDB, offsetof(struct _lowcore, pgm_tdb));
         DEFINE(__THREAD_trap_tdb, offsetof(struct task_struct, thread.trap_tdb));
         DEFINE(__GMAP_ASCE, offsetof(struct gmap, asce));
+        DEFINE(__SIE_PROG0C, offsetof(struct kvm_s390_sie_block, prog0c));
+        DEFINE(__SIE_PROG20, offsetof(struct kvm_s390_sie_block, prog20));
 #endif /* CONFIG_32BIT */
         return 0;
 }
diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c
index 298297477257..87acc38f73c6 100644
--- a/arch/s390/kernel/dumpstack.c
+++ b/arch/s390/kernel/dumpstack.c
@@ -74,6 +74,8 @@ __show_trace(unsigned long sp, unsigned long low, unsigned long high)
 
 static void show_trace(struct task_struct *task, unsigned long *stack)
 {
+        const unsigned long frame_size =
+                STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
         register unsigned long __r15 asm ("15");
         unsigned long sp;
 
@@ -82,11 +84,13 @@ static void show_trace(struct task_struct *task, unsigned long *stack)
                 sp = task ? task->thread.ksp : __r15;
         printk("Call Trace:\n");
 #ifdef CONFIG_CHECK_STACK
-        sp = __show_trace(sp, S390_lowcore.panic_stack - 4096,
-                          S390_lowcore.panic_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.panic_stack + frame_size - 4096,
+                          S390_lowcore.panic_stack + frame_size);
 #endif
-        sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE,
-                          S390_lowcore.async_stack);
+        sp = __show_trace(sp,
+                          S390_lowcore.async_stack + frame_size - ASYNC_SIZE,
+                          S390_lowcore.async_stack + frame_size);
         if (task)
                 __show_trace(sp, (unsigned long) task_stack_page(task),
                              (unsigned long) task_stack_page(task) + THREAD_SIZE);
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 4d5e6f8a7978..be7a408be7a1 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -429,11 +429,19 @@ io_skip:
         stm     %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_ASYNC
         stm     %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
         TRACE_IRQS_OFF
         xc      __SF_BACKCHAIN(4,%r15),__SF_BACKCHAIN(%r15)
+io_loop:
         l       %r1,BASED(.Ldo_IRQ)
         lr      %r2,%r11                # pass pointer to pt_regs
         basr    %r14,%r1                # call do_IRQ
+        tm      __LC_MACHINE_FLAGS+2,0x10       # MACHINE_FLAG_LPAR
+        jz      io_return
+        tpi     0
+        jz      io_return
+        mvc     __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
+        j       io_loop
 io_return:
         LOCKDEP_SYS_EXIT
         TRACE_IRQS_ON
@@ -573,10 +581,10 @@ ext_skip:
         stm     %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(32,%r11),__LC_SAVE_AREA_ASYNC
         stm     %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
+        mvc     __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
         TRACE_IRQS_OFF
         lr      %r2,%r11                # pass pointer to pt_regs
-        l       %r3,__LC_EXT_CPU_ADDR   # get cpu address + interruption code
-        l       %r4,__LC_EXT_PARAMS     # get external parameters
         l       %r1,BASED(.Ldo_extint)
         basr    %r14,%r1                # call do_extint
         j       io_return
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index aa0ab02e9595..3ddbc26d246e 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -54,7 +54,7 @@ void handle_signal32(unsigned long sig, struct k_sigaction *ka,
 void do_notify_resume(struct pt_regs *regs);
 
 struct ext_code;
-void do_extint(struct pt_regs *regs, struct ext_code, unsigned int, unsigned long);
+void do_extint(struct pt_regs *regs);
 void do_restart(void);
 void __init startup_init(void);
 void die(struct pt_regs *regs, const char *str);
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 4c17eece707e..1c039d0c24c7 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -47,7 +47,6 @@ _TIF_WORK_INT = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
                  _TIF_MCCK_PENDING)
 _TIF_TRACE    = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
                  _TIF_SYSCALL_TRACEPOINT)
-_TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
 
 #define BASED(name) name-system_call(%r13)
 
@@ -81,23 +80,27 @@ _TIF_EXIT_SIE = (_TIF_SIGPENDING | _TIF_NEED_RESCHED | _TIF_MCCK_PENDING)
 #endif
         .endm
 
-        .macro  HANDLE_SIE_INTERCEPT scratch,pgmcheck
+        .macro  HANDLE_SIE_INTERCEPT scratch,reason
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
         tmhh    %r8,0x0001              # interrupting from user ?
-        jnz     .+42
+        jnz     .+62
         lgr     \scratch,%r9
-        slg     \scratch,BASED(.Lsie_loop)
-        clg     \scratch,BASED(.Lsie_length)
-        .if     \pgmcheck
+        slg     \scratch,BASED(.Lsie_critical)
+        clg     \scratch,BASED(.Lsie_critical_length)
+        .if     \reason==1
         # Some program interrupts are suppressing (e.g. protection).
         # We must also check the instruction after SIE in that case.
         # do_protection_exception will rewind to rewind_pad
-        jh      .+22
+        jh      .+42
         .else
-        jhe     .+22
+        jhe     .+42
         .endif
-        lg      %r9,BASED(.Lsie_loop)
-        LPP     BASED(.Lhost_id)        # set host id
+        lg      %r14,__SF_EMPTY(%r15)           # get control block pointer
+        LPP     __SF_EMPTY+16(%r15)             # set host id
+        ni      __SIE_PROG0C+3(%r14),0xfe       # no longer in SIE
+        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
+        larl    %r9,sie_exit                    # skip forward to sie_exit
+        mvi     __SF_EMPTY+31(%r15),\reason     # set exit reason
 #endif
         .endm
 
@@ -450,7 +453,7 @@ ENTRY(io_int_handler)
         lg      %r12,__LC_THREAD_INFO
         larl    %r13,system_call
         lmg     %r8,%r9,__LC_IO_OLD_PSW
-        HANDLE_SIE_INTERCEPT %r14,0
+        HANDLE_SIE_INTERCEPT %r14,2
         SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
         tmhh    %r8,0x0001              # interrupting from user?
         jz      io_skip
@@ -460,10 +463,18 @@ io_skip:
         stmg    %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
         stmg    %r8,%r9,__PT_PSW(%r11)
+        mvc     __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
         TRACE_IRQS_OFF
         xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
+io_loop:
         lgr     %r2,%r11                # pass pointer to pt_regs
         brasl   %r14,do_IRQ
+        tm      __LC_MACHINE_FLAGS+6,0x10       # MACHINE_FLAG_LPAR
+        jz      io_return
+        tpi     0
+        jz      io_return
+        mvc     __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
+        j       io_loop
 io_return:
         LOCKDEP_SYS_EXIT
         TRACE_IRQS_ON
@@ -595,7 +606,7 @@ ENTRY(ext_int_handler)
         lg      %r12,__LC_THREAD_INFO
         larl    %r13,system_call
         lmg     %r8,%r9,__LC_EXT_OLD_PSW
-        HANDLE_SIE_INTERCEPT %r14,0
+        HANDLE_SIE_INTERCEPT %r14,3
         SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_STACK,STACK_SHIFT
         tmhh    %r8,0x0001              # interrupting from user ?
         jz      ext_skip
@@ -605,13 +616,13 @@ ext_skip:
         stmg    %r0,%r7,__PT_R0(%r11)
         mvc     __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
         stmg    %r8,%r9,__PT_PSW(%r11)
+        lghi    %r1,__LC_EXT_PARAMS2
+        mvc     __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
+        mvc     __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
+        mvc     __PT_INT_PARM_LONG(8,%r11),0(%r1)
         TRACE_IRQS_OFF
         xc      __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
-        lghi    %r1,4096
         lgr     %r2,%r11                # pass pointer to pt_regs
-        llgf    %r3,__LC_EXT_CPU_ADDR   # get cpu address + interruption code
-        llgf    %r4,__LC_EXT_PARAMS     # get external parameter
-        lg      %r5,__LC_EXT_PARAMS2-4096(%r1)  # get 64 bit external parameter
         brasl   %r14,do_extint
         j       io_return
 
@@ -643,7 +654,7 @@ ENTRY(mcck_int_handler)
         lg      %r12,__LC_THREAD_INFO
         larl    %r13,system_call
         lmg     %r8,%r9,__LC_MCK_OLD_PSW
-        HANDLE_SIE_INTERCEPT %r14,0
+        HANDLE_SIE_INTERCEPT %r14,4
         tm      __LC_MCCK_CODE,0x80     # system damage?
         jo      mcck_panic              # yes -> rest of mcck code invalid
         lghi    %r14,__LC_CPU_TIMER_SAVE_AREA
@@ -937,56 +948,50 @@ ENTRY(sie64a)
         stmg    %r6,%r14,__SF_GPRS(%r15)        # save kernel registers
         stg     %r2,__SF_EMPTY(%r15)            # save control block pointer
         stg     %r3,__SF_EMPTY+8(%r15)          # save guest register save area
-        xc      __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # host id == 0
+        xc      __SF_EMPTY+16(16,%r15),__SF_EMPTY+16(%r15) # host id & reason
         lmg     %r0,%r13,0(%r3)                 # load guest gprs 0-13
-# some program checks are suppressing. C code (e.g. do_protection_exception)
-# will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
-# instructions in the sie_loop should not cause program interrupts. So
-# lets use a nop (47 00 00 00) as a landing pad.
-# See also HANDLE_SIE_INTERCEPT
-rewind_pad:
-        nop     0
-sie_loop:
-        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
-        tm      __TI_flags+7(%r14),_TIF_EXIT_SIE
-        jnz     sie_exit
         lg      %r14,__LC_GMAP                  # get gmap pointer
         ltgr    %r14,%r14
         jz      sie_gmap
         lctlg   %c1,%c1,__GMAP_ASCE(%r14)       # load primary asce
 sie_gmap:
         lg      %r14,__SF_EMPTY(%r15)           # get control block pointer
+        oi      __SIE_PROG0C+3(%r14),1          # we are going into SIE now
+        tm      __SIE_PROG20+3(%r14),1          # last exit...
+        jnz     sie_done
         LPP     __SF_EMPTY(%r15)                # set guest id
         sie     0(%r14)
 sie_done:
         LPP     __SF_EMPTY+16(%r15)             # set host id
-        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
-sie_exit:
+        ni      __SIE_PROG0C+3(%r14),0xfe       # no longer in SIE
         lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
+# some program checks are suppressing. C code (e.g. do_protection_exception)
+# will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
+# instructions beween sie64a and sie_done should not cause program
+# interrupts. So lets use a nop (47 00 00 00) as a landing pad.
+# See also HANDLE_SIE_INTERCEPT
+rewind_pad:
+        nop     0
+        .globl sie_exit
+sie_exit:
         lg      %r14,__SF_EMPTY+8(%r15)         # load guest register save area
         stmg    %r0,%r13,0(%r14)                # save guest gprs 0-13
         lmg     %r6,%r14,__SF_GPRS(%r15)        # restore kernel registers
-        lghi    %r2,0
+        lg      %r2,__SF_EMPTY+24(%r15)         # return exit reason code
         br      %r14
 sie_fault:
-        lctlg   %c1,%c1,__LC_USER_ASCE          # load primary asce
-        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
-        lg      %r14,__SF_EMPTY+8(%r15)         # load guest register save area
-        stmg    %r0,%r13,0(%r14)                # save guest gprs 0-13
-        lmg     %r6,%r14,__SF_GPRS(%r15)        # restore kernel registers
-        lghi    %r2,-EFAULT
-        br      %r14
+        lghi    %r14,-EFAULT
+        stg     %r14,__SF_EMPTY+24(%r15)        # set exit reason code
+        j       sie_exit
 
         .align  8
-.Lsie_loop:
-        .quad   sie_loop
-.Lsie_length:
-        .quad   sie_done - sie_loop
-.Lhost_id:
-        .quad   0
+.Lsie_critical:
+        .quad   sie_gmap
+.Lsie_critical_length:
+        .quad   sie_done - sie_gmap
 
         EX_TABLE(rewind_pad,sie_fault)
-        EX_TABLE(sie_loop,sie_fault)
+        EX_TABLE(sie_exit,sie_fault)
 #endif
 
                 .section .rodata, "a"
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index d8a6a385d048..feb719d3c851 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -754,9 +754,9 @@ static struct bin_attribute sys_reipl_fcp_scp_data_attr = {
         .write = reipl_fcp_scpdata_write,
 };
 
-DEFINE_IPL_ATTR_RW(reipl_fcp, wwpn, "0x%016llx\n", "%016llx\n",
+DEFINE_IPL_ATTR_RW(reipl_fcp, wwpn, "0x%016llx\n", "%llx\n",
                    reipl_block_fcp->ipl_info.fcp.wwpn);
-DEFINE_IPL_ATTR_RW(reipl_fcp, lun, "0x%016llx\n", "%016llx\n",
+DEFINE_IPL_ATTR_RW(reipl_fcp, lun, "0x%016llx\n", "%llx\n",
                    reipl_block_fcp->ipl_info.fcp.lun);
 DEFINE_IPL_ATTR_RW(reipl_fcp, bootprog, "%lld\n", "%lld\n",
                    reipl_block_fcp->ipl_info.fcp.bootprog);
@@ -1323,9 +1323,9 @@ static struct shutdown_action __refdata reipl_action = {
 
 /* FCP dump device attributes */
 
-DEFINE_IPL_ATTR_RW(dump_fcp, wwpn, "0x%016llx\n", "%016llx\n",
+DEFINE_IPL_ATTR_RW(dump_fcp, wwpn, "0x%016llx\n", "%llx\n",
                    dump_block_fcp->ipl_info.fcp.wwpn);
-DEFINE_IPL_ATTR_RW(dump_fcp, lun, "0x%016llx\n", "%016llx\n",
+DEFINE_IPL_ATTR_RW(dump_fcp, lun, "0x%016llx\n", "%llx\n",
                    dump_block_fcp->ipl_info.fcp.lun);
 DEFINE_IPL_ATTR_RW(dump_fcp, bootprog, "%lld\n", "%lld\n",
                    dump_block_fcp->ipl_info.fcp.bootprog);
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index f7fb58903f6a..54b0995514e8 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -234,9 +234,9 @@ int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
 }
 EXPORT_SYMBOL(unregister_external_interrupt);
 
-void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code,
-                           unsigned int param32, unsigned long param64)
+void __irq_entry do_extint(struct pt_regs *regs)
 {
+        struct ext_code ext_code;
         struct pt_regs *old_regs;
         struct ext_int_info *p;
         int index;
@@ -248,6 +248,7 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code,
                 clock_comparator_work();
         }
         kstat_incr_irqs_this_cpu(EXTERNAL_INTERRUPT, NULL);
+        ext_code = *(struct ext_code *) &regs->int_code;
         if (ext_code.code != 0x1004)
                 __get_cpu_var(s390_idle).nohz_delay = 1;
 
@@ -255,7 +256,8 @@ void __irq_entry do_extint(struct pt_regs *regs, struct ext_code ext_code,
         rcu_read_lock();
         list_for_each_entry_rcu(p, &ext_int_hash[index], entry)
                 if (likely(p->code == ext_code.code))
-                        p->handler(ext_code, param32, param64);
+                        p->handler(ext_code, regs->int_parm,
+                                   regs->int_parm_long);
         rcu_read_unlock();
         irq_exit();
         set_irq_regs(old_regs);
@@ -311,3 +313,69 @@ void measurement_alert_subclass_unregister(void)
         spin_unlock(&ma_subclass_lock);
 }
 EXPORT_SYMBOL(measurement_alert_subclass_unregister);
+
+#ifdef CONFIG_SMP
+void synchronize_irq(unsigned int irq)
+{
+        /*
+         * Not needed, the handler is protected by a lock and IRQs that occur
+         * after the handler is deleted are just NOPs.
+         */
+}
+EXPORT_SYMBOL_GPL(synchronize_irq);
+#endif
+
+#ifndef CONFIG_PCI
+
+/* Only PCI devices have dynamically-defined IRQ handlers */
+
+int request_irq(unsigned int irq, irq_handler_t handler,
+                unsigned long irqflags, const char *devname, void *dev_id)
+{
+        return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(request_irq);
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(free_irq);
+
+void enable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(enable_irq);
+
+void disable_irq(unsigned int irq)
+{
+        WARN_ON(1);
+}
+EXPORT_SYMBOL_GPL(disable_irq);
+
+#endif /* !CONFIG_PCI */
+
+void disable_irq_nosync(unsigned int irq)
+{
+        disable_irq(irq);
+}
+EXPORT_SYMBOL_GPL(disable_irq_nosync);
+
+unsigned long probe_irq_on(void)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_on);
+
+int probe_irq_off(unsigned long val)
+{
+        return 0;
+}
+EXPORT_SYMBOL_GPL(probe_irq_off);
+
+unsigned int probe_irq_mask(unsigned long val)
+{
+        return val;
+}
+EXPORT_SYMBOL_GPL(probe_irq_mask);
diff --git a/arch/s390/kernel/perf_event.c b/arch/s390/kernel/perf_event.c
index f58f37f66824..a6fc037671b1 100644
--- a/arch/s390/kernel/perf_event.c
+++ b/arch/s390/kernel/perf_event.c
@@ -13,6 +13,7 @@
 
 #include <linux/kernel.h>
 #include <linux/perf_event.h>
+#include <linux/kvm_host.h>
 #include <linux/percpu.h>
 #include <linux/export.h>
 #include <asm/irq.h>
@@ -39,6 +40,57 @@ int perf_num_counters(void)
 }
 EXPORT_SYMBOL(perf_num_counters);
 
+static struct kvm_s390_sie_block *sie_block(struct pt_regs *regs)
+{
+        struct stack_frame *stack = (struct stack_frame *) regs->gprs[15];
+
+        if (!stack)
+                return NULL;
+
+        return (struct kvm_s390_sie_block *) stack->empty1[0];
+}
+
+static bool is_in_guest(struct pt_regs *regs)
+{
+        unsigned long ip = instruction_pointer(regs);
+
+        if (user_mode(regs))
+                return false;
+
+        return ip == (unsigned long) &sie_exit;
+}
+
+static unsigned long guest_is_user_mode(struct pt_regs *regs)
+{
+        return sie_block(regs)->gpsw.mask & PSW_MASK_PSTATE;
+}
+
+static unsigned long instruction_pointer_guest(struct pt_regs *regs)
+{
+        return sie_block(regs)->gpsw.addr & PSW_ADDR_INSN;
+}
+
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
+        return is_in_guest(regs) ? instruction_pointer_guest(regs)
+                                 : instruction_pointer(regs);
+}
+
+static unsigned long perf_misc_guest_flags(struct pt_regs *regs)
+{
+        return guest_is_user_mode(regs) ? PERF_RECORD_MISC_GUEST_USER
+                                        : PERF_RECORD_MISC_GUEST_KERNEL;
+}
+
+unsigned long perf_misc_flags(struct pt_regs *regs)
+{
+        if (is_in_guest(regs))
+                return perf_misc_guest_flags(regs);
+
+        return user_mode(regs) ? PERF_RECORD_MISC_USER
+                               : PERF_RECORD_MISC_KERNEL;
+}
+
 void perf_event_print_debug(void)
 {
         struct cpumf_ctr_info cf_info;
diff --git a/arch/s390/kernel/s390_ksyms.c b/arch/s390/kernel/s390_ksyms.c
index 9bdbcef1da9e..3bac589844a7 100644
--- a/arch/s390/kernel/s390_ksyms.c
+++ b/arch/s390/kernel/s390_ksyms.c
@@ -7,6 +7,7 @@ EXPORT_SYMBOL(_mcount);
 #endif
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
 EXPORT_SYMBOL(sie64a);
+EXPORT_SYMBOL(sie_exit);
 #endif
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(memset);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index b6506ee32a36..29bd7bec4176 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -225,7 +225,7 @@ _sclp_print:
         ahi     %r2,1
         ltr     %r0,%r0                         # end of string?
         jz      .LfinalizemtoS4
-        chi     %r0,0x15                        # end of line (NL)?
+        chi     %r0,0x0a                        # end of line (NL)?
         jz      .LfinalizemtoS4
         stc     %r0,0(%r6,%r7)                  # copy to mto
         la      %r11,0(%r6,%r7)
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 0a49095104c9..497451ec5e26 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -719,10 +719,6 @@ static void reserve_oldmem(void)
         }
         create_mem_hole(memory_chunk, OLDMEM_BASE, OLDMEM_SIZE);
         create_mem_hole(memory_chunk, OLDMEM_SIZE, real_size - OLDMEM_SIZE);
-        if (OLDMEM_BASE + OLDMEM_SIZE == real_size)
-                saved_max_pfn = PFN_DOWN(OLDMEM_BASE) - 1;
-        else
-                saved_max_pfn = PFN_DOWN(real_size) - 1;
 #endif
 }
 
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 4f977d0d25c2..15a016c10563 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -49,7 +49,6 @@
 
 enum {
         ec_schedule = 0,
-        ec_call_function,
         ec_call_function_single,
         ec_stop_cpu,
 };
@@ -438,8 +437,6 @@ static void smp_handle_ext_call(void)
                 smp_stop_cpu();
         if (test_bit(ec_schedule, &bits))
                 scheduler_ipi();
-        if (test_bit(ec_call_function, &bits))
-                generic_smp_call_function_interrupt();
         if (test_bit(ec_call_function_single, &bits))
                 generic_smp_call_function_single_interrupt();
 }
@@ -456,7 +453,7 @@ void arch_send_call_function_ipi_mask(const struct cpumask *mask)
         int cpu;
 
         for_each_cpu(cpu, mask)
-                pcpu_ec_call(pcpu_devices + cpu, ec_call_function);
+                pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
 }
 
 void arch_send_call_function_single_ipi(int cpu)
diff --git a/arch/s390/kvm/Makefile b/arch/s390/kvm/Makefile
index 8fe9d65a4585..40b4c6470f88 100644
--- a/arch/s390/kvm/Makefile
+++ b/arch/s390/kvm/Makefile
@@ -6,7 +6,8 @@
 # it under the terms of the GNU General Public License (version 2 only)
 # as published by the Free Software Foundation.
 
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o eventfd.o)
+KVM := ../../../virt/kvm
+common-objs = $(KVM)/kvm_main.o $(KVM)/eventfd.o
 
 ccflags-y := -Ivirt/kvm -Iarch/s390/kvm
 
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 1c01a9912989..3074475c8ae0 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -132,6 +132,9 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
 {
         int code = (vcpu->arch.sie_block->ipb & 0xfff0000) >> 16;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         trace_kvm_s390_handle_diag(vcpu, code);
         switch (code) {
         case 0x10:
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index b7d1b2edeeb3..5ee56e5acc23 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -22,87 +22,6 @@
 #include "trace.h"
 #include "trace-s390.h"
 
-static int handle_lctlg(struct kvm_vcpu *vcpu)
-{
-        int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
-        int reg3 = vcpu->arch.sie_block->ipa & 0x000f;
-        u64 useraddr;
-        int reg, rc;
-
-        vcpu->stat.instruction_lctlg++;
-
-        useraddr = kvm_s390_get_base_disp_rsy(vcpu);
-
-        if (useraddr & 7)
-                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-
-        reg = reg1;
-
-        VCPU_EVENT(vcpu, 5, "lctlg r1:%x, r3:%x, addr:%llx", reg1, reg3,
-                   useraddr);
-        trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, useraddr);
-
-        do {
-                rc = get_guest(vcpu, vcpu->arch.sie_block->gcr[reg],
-                               (u64 __user *) useraddr);
-                if (rc)
-                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                useraddr += 8;
-                if (reg == reg3)
-                        break;
-                reg = (reg + 1) % 16;
-        } while (1);
-        return 0;
-}
-
-static int handle_lctl(struct kvm_vcpu *vcpu)
-{
-        int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
-        int reg3 = vcpu->arch.sie_block->ipa & 0x000f;
-        u64 useraddr;
-        u32 val = 0;
-        int reg, rc;
-
-        vcpu->stat.instruction_lctl++;
-
-        useraddr = kvm_s390_get_base_disp_rs(vcpu);
-
-        if (useraddr & 3)
-                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
-
-        VCPU_EVENT(vcpu, 5, "lctl r1:%x, r3:%x, addr:%llx", reg1, reg3,
-                   useraddr);
-        trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, useraddr);
-
-        reg = reg1;
-        do {
-                rc = get_guest(vcpu, val, (u32 __user *) useraddr);
-                if (rc)
-                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
-                vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul;
-                vcpu->arch.sie_block->gcr[reg] |= val;
-                useraddr += 4;
-                if (reg == reg3)
-                        break;
-                reg = (reg + 1) % 16;
-        } while (1);
-        return 0;
-}
-
-static const intercept_handler_t eb_handlers[256] = {
-        [0x2f] = handle_lctlg,
-        [0x8a] = kvm_s390_handle_priv_eb,
-};
-
-static int handle_eb(struct kvm_vcpu *vcpu)
-{
-        intercept_handler_t handler;
-
-        handler = eb_handlers[vcpu->arch.sie_block->ipb & 0xff];
-        if (handler)
-                return handler(vcpu);
-        return -EOPNOTSUPP;
-}
 
 static const intercept_handler_t instruction_handlers[256] = {
         [0x01] = kvm_s390_handle_01,
@@ -110,10 +29,10 @@ static const intercept_handler_t instruction_handlers[256] = {
         [0x83] = kvm_s390_handle_diag,
         [0xae] = kvm_s390_handle_sigp,
         [0xb2] = kvm_s390_handle_b2,
-        [0xb7] = handle_lctl,
+        [0xb7] = kvm_s390_handle_lctl,
         [0xb9] = kvm_s390_handle_b9,
         [0xe5] = kvm_s390_handle_e5,
-        [0xeb] = handle_eb,
+        [0xeb] = kvm_s390_handle_eb,
 };
 
 static int handle_noop(struct kvm_vcpu *vcpu)
@@ -174,47 +93,12 @@ static int handle_stop(struct kvm_vcpu *vcpu)
 
 static int handle_validity(struct kvm_vcpu *vcpu)
 {
-        unsigned long vmaddr;
         int viwhy = vcpu->arch.sie_block->ipb >> 16;
-        int rc;
 
         vcpu->stat.exit_validity++;
         trace_kvm_s390_intercept_validity(vcpu, viwhy);
-        if (viwhy == 0x37) {
-                vmaddr = gmap_fault(vcpu->arch.sie_block->prefix,
-                                    vcpu->arch.gmap);
-                if (IS_ERR_VALUE(vmaddr)) {
-                        rc = -EOPNOTSUPP;
-                        goto out;
-                }
-                rc = fault_in_pages_writeable((char __user *) vmaddr,
-                         PAGE_SIZE);
-                if (rc) {
-                        /* user will receive sigsegv, exit to user */
-                        rc = -EOPNOTSUPP;
-                        goto out;
-                }
-                vmaddr = gmap_fault(vcpu->arch.sie_block->prefix + PAGE_SIZE,
-                                    vcpu->arch.gmap);
-                if (IS_ERR_VALUE(vmaddr)) {
-                        rc = -EOPNOTSUPP;
-                        goto out;
-                }
-                rc = fault_in_pages_writeable((char __user *) vmaddr,
-                         PAGE_SIZE);
-                if (rc) {
-                        /* user will receive sigsegv, exit to user */
-                        rc = -EOPNOTSUPP;
-                        goto out;
-                }
-        } else
-                rc = -EOPNOTSUPP;
-
-out:
-        if (rc)
-                VCPU_EVENT(vcpu, 2, "unhandled validity intercept code %d",
-                           viwhy);
-        return rc;
+        WARN_ONCE(true, "kvm: unhandled validity intercept 0x%x\n", viwhy);
+        return -EOPNOTSUPP;
 }
 
 static int handle_instruction(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 5c948177529e..7f35cb33e510 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -438,7 +438,7 @@ int kvm_s390_handle_wait(struct kvm_vcpu *vcpu)
 no_timer:
         spin_lock(&vcpu->arch.local_int.float_int->lock);
         spin_lock_bh(&vcpu->arch.local_int.lock);
-        add_wait_queue(&vcpu->arch.local_int.wq, &wait);
+        add_wait_queue(&vcpu->wq, &wait);
         while (list_empty(&vcpu->arch.local_int.list) &&
                 list_empty(&vcpu->arch.local_int.float_int->list) &&
                 (!vcpu->arch.local_int.timer_due) &&
@@ -452,7 +452,7 @@ no_timer:
         }
         __unset_cpu_idle(vcpu);
         __set_current_state(TASK_RUNNING);
-        remove_wait_queue(&vcpu->arch.local_int.wq, &wait);
+        remove_wait_queue(&vcpu->wq, &wait);
         spin_unlock_bh(&vcpu->arch.local_int.lock);
         spin_unlock(&vcpu->arch.local_int.float_int->lock);
         hrtimer_try_to_cancel(&vcpu->arch.ckc_timer);
@@ -465,8 +465,8 @@ void kvm_s390_tasklet(unsigned long parm)
 
         spin_lock(&vcpu->arch.local_int.lock);
         vcpu->arch.local_int.timer_due = 1;
-        if (waitqueue_active(&vcpu->arch.local_int.wq))
-                wake_up_interruptible(&vcpu->arch.local_int.wq);
+        if (waitqueue_active(&vcpu->wq))
+                wake_up_interruptible(&vcpu->wq);
         spin_unlock(&vcpu->arch.local_int.lock);
 }
 
@@ -613,7 +613,7 @@ int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code)
         spin_lock_bh(&li->lock);
         list_add(&inti->list, &li->list);
         atomic_set(&li->active, 1);
-        BUG_ON(waitqueue_active(&li->wq));
+        BUG_ON(waitqueue_active(li->wq));
         spin_unlock_bh(&li->lock);
         return 0;
 }
@@ -746,8 +746,8 @@ int kvm_s390_inject_vm(struct kvm *kvm,
         li = fi->local_int[sigcpu];
         spin_lock_bh(&li->lock);
         atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&li->wq);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
         spin_unlock_bh(&li->lock);
         spin_unlock(&fi->lock);
         mutex_unlock(&kvm->lock);
@@ -832,8 +832,8 @@ int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
         if (inti->type == KVM_S390_SIGP_STOP)
                 li->action_bits |= ACTION_STOP_ON_STOP;
         atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&vcpu->arch.local_int.wq);
+        if (waitqueue_active(&vcpu->wq))
+                wake_up_interruptible(&vcpu->wq);
         spin_unlock_bh(&li->lock);
         mutex_unlock(&vcpu->kvm->lock);
         return 0;
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index c1c7c683fa26..ba694d2ba51e 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -59,6 +59,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
         { "deliver_restart_signal", VCPU_STAT(deliver_restart_signal) },
         { "deliver_program_interruption", VCPU_STAT(deliver_program_int) },
         { "exit_wait_state", VCPU_STAT(exit_wait_state) },
+        { "instruction_pfmf", VCPU_STAT(instruction_pfmf) },
         { "instruction_stidp", VCPU_STAT(instruction_stidp) },
         { "instruction_spx", VCPU_STAT(instruction_spx) },
         { "instruction_stpx", VCPU_STAT(instruction_stpx) },
@@ -84,6 +85,7 @@ struct kvm_stats_debugfs_item debugfs_entries[] = {
 };
 
 static unsigned long long *facilities;
+static struct gmap_notifier gmap_notifier;
 
 /* Section: not file related */
 int kvm_arch_hardware_enable(void *garbage)
@@ -96,13 +98,18 @@ void kvm_arch_hardware_disable(void *garbage)
 {
 }
 
+static void kvm_gmap_notifier(struct gmap *gmap, unsigned long address);
+
 int kvm_arch_hardware_setup(void)
 {
+        gmap_notifier.notifier_call = kvm_gmap_notifier;
+        gmap_register_ipte_notifier(&gmap_notifier);
         return 0;
 }
 
 void kvm_arch_hardware_unsetup(void)
 {
+        gmap_unregister_ipte_notifier(&gmap_notifier);
 }
 
 void kvm_arch_check_processor_compat(void *rtn)
@@ -239,6 +246,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
                 kvm->arch.gmap = gmap_alloc(current->mm);
                 if (!kvm->arch.gmap)
                         goto out_nogmap;
+                kvm->arch.gmap->private = kvm;
         }
 
         kvm->arch.css_support = 0;
@@ -270,7 +278,7 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 
         free_page((unsigned long)(vcpu->arch.sie_block));
         kvm_vcpu_uninit(vcpu);
-        kfree(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
 }
 
 static void kvm_free_vcpus(struct kvm *kvm)
@@ -309,6 +317,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
                 vcpu->arch.gmap = gmap_alloc(current->mm);
                 if (!vcpu->arch.gmap)
                         return -ENOMEM;
+                vcpu->arch.gmap->private = vcpu->kvm;
                 return 0;
         }
 
@@ -373,8 +382,10 @@ int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
         atomic_set(&vcpu->arch.sie_block->cpuflags, CPUSTAT_ZARCH |
                                                     CPUSTAT_SM |
-                                                    CPUSTAT_STOPPED);
+                                                    CPUSTAT_STOPPED |
+                                                    CPUSTAT_GED);
         vcpu->arch.sie_block->ecb   = 6;
+        vcpu->arch.sie_block->ecb2  = 8;
         vcpu->arch.sie_block->eca   = 0xC1002001U;
         vcpu->arch.sie_block->fac   = (int) (long) facilities;
         hrtimer_init(&vcpu->arch.ckc_timer, CLOCK_REALTIME, HRTIMER_MODE_ABS);
@@ -397,7 +408,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
 
         rc = -ENOMEM;
 
-        vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
+        vcpu = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
         if (!vcpu)
                 goto out;
 
@@ -427,7 +438,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
         vcpu->arch.local_int.float_int = &kvm->arch.float_int;
         spin_lock(&kvm->arch.float_int.lock);
         kvm->arch.float_int.local_int[id] = &vcpu->arch.local_int;
-        init_waitqueue_head(&vcpu->arch.local_int.wq);
+        vcpu->arch.local_int.wq = &vcpu->wq;
         vcpu->arch.local_int.cpuflags = &vcpu->arch.sie_block->cpuflags;
         spin_unlock(&kvm->arch.float_int.lock);
 
@@ -442,7 +453,7 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
 out_free_sie_block:
         free_page((unsigned long)(vcpu->arch.sie_block));
 out_free_cpu:
-        kfree(vcpu);
+        kmem_cache_free(kvm_vcpu_cache, vcpu);
 out:
         return ERR_PTR(rc);
 }
@@ -454,6 +465,50 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
         return 0;
 }
 
+void s390_vcpu_block(struct kvm_vcpu *vcpu)
+{
+        atomic_set_mask(PROG_BLOCK_SIE, &vcpu->arch.sie_block->prog20);
+}
+
+void s390_vcpu_unblock(struct kvm_vcpu *vcpu)
+{
+        atomic_clear_mask(PROG_BLOCK_SIE, &vcpu->arch.sie_block->prog20);
+}
+
+/*
+ * Kick a guest cpu out of SIE and wait until SIE is not running.
+ * If the CPU is not running (e.g. waiting as idle) the function will
+ * return immediately. */
+void exit_sie(struct kvm_vcpu *vcpu)
+{
+        atomic_set_mask(CPUSTAT_STOP_INT, &vcpu->arch.sie_block->cpuflags);
+        while (vcpu->arch.sie_block->prog0c & PROG_IN_SIE)
+                cpu_relax();
+}
+
+/* Kick a guest cpu out of SIE and prevent SIE-reentry */
+void exit_sie_sync(struct kvm_vcpu *vcpu)
+{
+        s390_vcpu_block(vcpu);
+        exit_sie(vcpu);
+}
+
+static void kvm_gmap_notifier(struct gmap *gmap, unsigned long address)
+{
+        int i;
+        struct kvm *kvm = gmap->private;
+        struct kvm_vcpu *vcpu;
+
+        kvm_for_each_vcpu(i, vcpu, kvm) {
+                /* match against both prefix pages */
+                if (vcpu->arch.sie_block->prefix == (address & ~0x1000UL)) {
+                        VCPU_EVENT(vcpu, 2, "gmap notifier for %lx", address);
+                        kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu);
+                        exit_sie_sync(vcpu);
+                }
+        }
+}
+
 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
 {
         /* kvm common code refers to this, but never calls it */
@@ -606,6 +661,27 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
         return -EINVAL; /* not implemented yet */
 }
 
+static int kvm_s390_handle_requests(struct kvm_vcpu *vcpu)
+{
+        /*
+         * We use MMU_RELOAD just to re-arm the ipte notifier for the
+         * guest prefix page. gmap_ipte_notify will wait on the ptl lock.
+         * This ensures that the ipte instruction for this request has
+         * already finished. We might race against a second unmapper that
+         * wants to set the blocking bit. Lets just retry the request loop.
+         */
+        while (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) {
+                int rc;
+                rc = gmap_ipte_notify(vcpu->arch.gmap,
+                                      vcpu->arch.sie_block->prefix,
+                                      PAGE_SIZE * 2);
+                if (rc)
+                        return rc;
+                s390_vcpu_unblock(vcpu);
+        }
+        return 0;
+}
+
 static int __vcpu_run(struct kvm_vcpu *vcpu)
 {
         int rc;
@@ -621,6 +697,10 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
         if (!kvm_is_ucontrol(vcpu->kvm))
                 kvm_s390_deliver_pending_interrupts(vcpu);
 
+        rc = kvm_s390_handle_requests(vcpu);
+        if (rc)
+                return rc;
+
         vcpu->arch.sie_block->icptcode = 0;
         preempt_disable();
         kvm_guest_enter();
@@ -630,7 +710,9 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
         trace_kvm_s390_sie_enter(vcpu,
                                  atomic_read(&vcpu->arch.sie_block->cpuflags));
         rc = sie64a(vcpu->arch.sie_block, vcpu->run->s.regs.gprs);
-        if (rc) {
+        if (rc > 0)
+                rc = 0;
+        if (rc < 0) {
                 if (kvm_is_ucontrol(vcpu->kvm)) {
                         rc = SIE_INTERCEPT_UCONTROL;
                 } else {
@@ -1046,7 +1128,7 @@ static int __init kvm_s390_init(void)
                 return -ENOMEM;
         }
         memcpy(facilities, S390_lowcore.stfle_fac_list, 16);
-        facilities[0] &= 0xff00fff3f47c0000ULL;
+        facilities[0] &= 0xff82fff3f47c0000ULL;
         facilities[1] &= 0x001c000000000000ULL;
         return 0;
 }
@@ -1059,3 +1141,12 @@ static void __exit kvm_s390_exit(void)
 
 module_init(kvm_s390_init);
 module_exit(kvm_s390_exit);
+
+/*
+ * Enable autoloading of the kvm module.
+ * Note that we add the module alias here instead of virt/kvm/kvm_main.c
+ * since x86 takes a different approach.
+ */
+#include <linux/miscdevice.h>
+MODULE_ALIAS_MISCDEV(KVM_MINOR);
+MODULE_ALIAS("devname:kvm");
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index efc14f687265..028ca9fd2158 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -63,6 +63,7 @@ static inline void kvm_s390_set_prefix(struct kvm_vcpu *vcpu, u32 prefix)
 {
         vcpu->arch.sie_block->prefix = prefix & 0x7fffe000u;
         vcpu->arch.sie_block->ihcpu  = 0xffff;
+        kvm_make_request(KVM_REQ_MMU_RELOAD, vcpu);
 }
 
 static inline u64 kvm_s390_get_base_disp_s(struct kvm_vcpu *vcpu)
@@ -85,6 +86,12 @@ static inline void kvm_s390_get_base_disp_sse(struct kvm_vcpu *vcpu,
         *address2 = (base2 ? vcpu->run->s.regs.gprs[base2] : 0) + disp2;
 }
 
+static inline void kvm_s390_get_regs_rre(struct kvm_vcpu *vcpu, int *r1, int *r2)
+{
+        *r1 = (vcpu->arch.sie_block->ipb & 0x00f00000) >> 20;
+        *r2 = (vcpu->arch.sie_block->ipb & 0x000f0000) >> 16;
+}
+
 static inline u64 kvm_s390_get_base_disp_rsy(struct kvm_vcpu *vcpu)
 {
         u32 base2 = vcpu->arch.sie_block->ipb >> 28;
@@ -125,7 +132,8 @@ int kvm_s390_handle_e5(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_01(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_b9(struct kvm_vcpu *vcpu);
 int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu);
-int kvm_s390_handle_priv_eb(struct kvm_vcpu *vcpu);
+int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu);
+int kvm_s390_handle_eb(struct kvm_vcpu *vcpu);
 
 /* implemented in sigp.c */
 int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu);
@@ -133,6 +141,10 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu);
 /* implemented in kvm-s390.c */
 int kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu,
                                  unsigned long addr);
+void s390_vcpu_block(struct kvm_vcpu *vcpu);
+void s390_vcpu_unblock(struct kvm_vcpu *vcpu);
+void exit_sie(struct kvm_vcpu *vcpu);
+void exit_sie_sync(struct kvm_vcpu *vcpu);
 /* implemented in diag.c */
 int kvm_s390_handle_diag(struct kvm_vcpu *vcpu);
 
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index 6bbd7b5a0bbe..0da3e6eb6be6 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -1,7 +1,7 @@
 /*
  * handling privileged instructions
  *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008, 2013
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
@@ -20,6 +20,9 @@
 #include <asm/debug.h>
 #include <asm/ebcdic.h>
 #include <asm/sysinfo.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/io.h>
 #include <asm/ptrace.h>
 #include <asm/compat.h>
 #include "gaccess.h"
@@ -34,6 +37,9 @@ static int handle_set_prefix(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_spx++;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
         /* must be word boundary */
@@ -65,6 +71,9 @@ static int handle_store_prefix(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_stpx++;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
         /* must be word boundary */
@@ -89,6 +98,9 @@ static int handle_store_cpu_address(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_stap++;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         useraddr = kvm_s390_get_base_disp_s(vcpu);
 
         if (useraddr & 1)
@@ -105,7 +117,12 @@ static int handle_store_cpu_address(struct kvm_vcpu *vcpu)
 static int handle_skey(struct kvm_vcpu *vcpu)
 {
         vcpu->stat.instruction_storage_key++;
-        vcpu->arch.sie_block->gpsw.addr -= 4;
+
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
+        vcpu->arch.sie_block->gpsw.addr =
+                __rewind_psw(vcpu->arch.sie_block->gpsw, 4);
         VCPU_EVENT(vcpu, 4, "%s", "retrying storage key operation");
         return 0;
 }
@@ -129,9 +146,10 @@ static int handle_tpi(struct kvm_vcpu *vcpu)
                  * Store the two-word I/O interruption code into the
                  * provided area.
                  */
-                put_guest(vcpu, inti->io.subchannel_id, (u16 __user *) addr);
-                put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *) (addr + 2));
-                put_guest(vcpu, inti->io.io_int_parm, (u32 __user *) (addr + 4));
+                if (put_guest(vcpu, inti->io.subchannel_id, (u16 __user *)addr)
+                    || put_guest(vcpu, inti->io.subchannel_nr, (u16 __user *)(addr + 2))
+                    || put_guest(vcpu, inti->io.io_int_parm, (u32 __user *)(addr + 4)))
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
         } else {
                 /*
                  * Store the three-word I/O interruption code into
@@ -182,6 +200,9 @@ static int handle_io_inst(struct kvm_vcpu *vcpu)
 {
         VCPU_EVENT(vcpu, 4, "%s", "I/O instruction");
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         if (vcpu->kvm->arch.css_support) {
                 /*
                  * Most I/O instructions will be handled by userspace.
@@ -210,8 +231,12 @@ static int handle_stfl(struct kvm_vcpu *vcpu)
         int rc;
 
         vcpu->stat.instruction_stfl++;
+
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         /* only pass the facility bits, which we can handle */
-        facility_list = S390_lowcore.stfl_fac_list & 0xff00fff3;
+        facility_list = S390_lowcore.stfl_fac_list & 0xff82fff3;
 
         rc = copy_to_guest(vcpu, offsetof(struct _lowcore, stfl_fac_list),
                            &facility_list, sizeof(facility_list));
@@ -255,8 +280,8 @@ int kvm_s390_handle_lpsw(struct kvm_vcpu *vcpu)
         u64 addr;
 
         if (gpsw->mask & PSW_MASK_PSTATE)
-                return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         addr = kvm_s390_get_base_disp_s(vcpu);
         if (addr & 7)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -278,6 +303,9 @@ static int handle_lpswe(struct kvm_vcpu *vcpu)
         psw_t new_psw;
         u64 addr;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         addr = kvm_s390_get_base_disp_s(vcpu);
         if (addr & 7)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
@@ -296,6 +324,9 @@ static int handle_stidp(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_stidp++;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         operand2 = kvm_s390_get_base_disp_s(vcpu);
 
         if (operand2 & 7)
@@ -351,16 +382,30 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
         vcpu->stat.instruction_stsi++;
         VCPU_EVENT(vcpu, 4, "stsi: fc: %x sel1: %x sel2: %x", fc, sel1, sel2);
 
-        operand2 = kvm_s390_get_base_disp_s(vcpu);
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
+        if (fc > 3) {
+                vcpu->arch.sie_block->gpsw.mask |= 3ul << 44;     /* cc 3 */
+                return 0;
+        }
 
-        if (operand2 & 0xfff && fc > 0)
+        if (vcpu->run->s.regs.gprs[0] & 0x0fffff00
+            || vcpu->run->s.regs.gprs[1] & 0xffff0000)
                 return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
 
-        switch (fc) {
-        case 0:
+        if (fc == 0) {
                 vcpu->run->s.regs.gprs[0] = 3 << 28;
-                vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);
+                vcpu->arch.sie_block->gpsw.mask &= ~(3ul << 44);  /* cc 0 */
                 return 0;
+        }
+
+        operand2 = kvm_s390_get_base_disp_s(vcpu);
+
+        if (operand2 & 0xfff)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        switch (fc) {
         case 1: /* same handling for 1 and 2 */
         case 2:
                 mem = get_zeroed_page(GFP_KERNEL);
@@ -377,8 +422,6 @@ static int handle_stsi(struct kvm_vcpu *vcpu)
                         goto out_no_data;
                 handle_stsi_3_2_2(vcpu, (void *) mem);
                 break;
-        default:
-                goto out_no_data;
         }
 
         if (copy_to_guest_absolute(vcpu, operand2, (void *) mem, PAGE_SIZE)) {
@@ -432,20 +475,14 @@ int kvm_s390_handle_b2(struct kvm_vcpu *vcpu)
         intercept_handler_t handler;
 
         /*
-         * a lot of B2 instructions are priviledged. We first check for
-         * the privileged ones, that we can handle in the kernel. If the
-         * kernel can handle this instruction, we check for the problem
-         * state bit and (a) handle the instruction or (b) send a code 2
-         * program check.
-         * Anything else goes to userspace.*/
+         * A lot of B2 instructions are priviledged. Here we check for
+         * the privileged ones, that we can handle in the kernel.
+         * Anything else goes to userspace.
+         */
         handler = b2_handlers[vcpu->arch.sie_block->ipa & 0x00ff];
-        if (handler) {
-                if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
-                        return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
-                else
-                        return handler(vcpu);
-        }
+        if (handler)
+                return handler(vcpu);
+
         return -EOPNOTSUPP;
 }
 
@@ -453,8 +490,7 @@ static int handle_epsw(struct kvm_vcpu *vcpu)
 {
         int reg1, reg2;
 
-        reg1 = (vcpu->arch.sie_block->ipb & 0x00f00000) >> 24;
-        reg2 = (vcpu->arch.sie_block->ipb & 0x000f0000) >> 16;
+        kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
 
         /* This basically extracts the mask half of the psw. */
         vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000;
@@ -467,9 +503,88 @@ static int handle_epsw(struct kvm_vcpu *vcpu)
         return 0;
 }
 
+#define PFMF_RESERVED   0xfffc0101UL
+#define PFMF_SK         0x00020000UL
+#define PFMF_CF         0x00010000UL
+#define PFMF_UI         0x00008000UL
+#define PFMF_FSC        0x00007000UL
+#define PFMF_NQ         0x00000800UL
+#define PFMF_MR         0x00000400UL
+#define PFMF_MC         0x00000200UL
+#define PFMF_KEY        0x000000feUL
+
+static int handle_pfmf(struct kvm_vcpu *vcpu)
+{
+        int reg1, reg2;
+        unsigned long start, end;
+
+        vcpu->stat.instruction_pfmf++;
+
+        kvm_s390_get_regs_rre(vcpu, &reg1, &reg2);
+
+        if (!MACHINE_HAS_PFMF)
+                return kvm_s390_inject_program_int(vcpu, PGM_OPERATION);
+
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
+        if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        /* Only provide non-quiescing support if the host supports it */
+        if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ &&
+            S390_lowcore.stfl_fac_list & 0x00020000)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        /* No support for conditional-SSKE */
+        if (vcpu->run->s.regs.gprs[reg1] & (PFMF_MR | PFMF_MC))
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK;
+        switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) {
+        case 0x00000000:
+                end = (start + (1UL << 12)) & ~((1UL << 12) - 1);
+                break;
+        case 0x00001000:
+                end = (start + (1UL << 20)) & ~((1UL << 20) - 1);
+                break;
+        /* We dont support EDAT2
+        case 0x00002000:
+                end = (start + (1UL << 31)) & ~((1UL << 31) - 1);
+                break;*/
+        default:
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+        }
+        while (start < end) {
+                unsigned long useraddr;
+
+                useraddr = gmap_translate(start, vcpu->arch.gmap);
+                if (IS_ERR((void *)useraddr))
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+
+                if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) {
+                        if (clear_user((void __user *)useraddr, PAGE_SIZE))
+                                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                }
+
+                if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) {
+                        if (set_guest_storage_key(current->mm, useraddr,
+                                        vcpu->run->s.regs.gprs[reg1] & PFMF_KEY,
+                                        vcpu->run->s.regs.gprs[reg1] & PFMF_NQ))
+                                return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                }
+
+                start += PAGE_SIZE;
+        }
+        if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC)
+                vcpu->run->s.regs.gprs[reg2] = end;
+        return 0;
+}
+
 static const intercept_handler_t b9_handlers[256] = {
         [0x8d] = handle_epsw,
         [0x9c] = handle_io_inst,
+        [0xaf] = handle_pfmf,
 };
 
 int kvm_s390_handle_b9(struct kvm_vcpu *vcpu)
@@ -478,29 +593,96 @@ int kvm_s390_handle_b9(struct kvm_vcpu *vcpu)
 
         /* This is handled just as for the B2 instructions. */
         handler = b9_handlers[vcpu->arch.sie_block->ipa & 0x00ff];
-        if (handler) {
-                if ((handler != handle_epsw) &&
-                    (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE))
-                        return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
-                else
-                        return handler(vcpu);
-        }
+        if (handler)
+                return handler(vcpu);
+
         return -EOPNOTSUPP;
 }
 
+int kvm_s390_handle_lctl(struct kvm_vcpu *vcpu)
+{
+        int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
+        int reg3 = vcpu->arch.sie_block->ipa & 0x000f;
+        u64 useraddr;
+        u32 val = 0;
+        int reg, rc;
+
+        vcpu->stat.instruction_lctl++;
+
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
+        useraddr = kvm_s390_get_base_disp_rs(vcpu);
+
+        if (useraddr & 3)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        VCPU_EVENT(vcpu, 5, "lctl r1:%x, r3:%x, addr:%llx", reg1, reg3,
+                   useraddr);
+        trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, useraddr);
+
+        reg = reg1;
+        do {
+                rc = get_guest(vcpu, val, (u32 __user *) useraddr);
+                if (rc)
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                vcpu->arch.sie_block->gcr[reg] &= 0xffffffff00000000ul;
+                vcpu->arch.sie_block->gcr[reg] |= val;
+                useraddr += 4;
+                if (reg == reg3)
+                        break;
+                reg = (reg + 1) % 16;
+        } while (1);
+
+        return 0;
+}
+
+static int handle_lctlg(struct kvm_vcpu *vcpu)
+{
+        int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4;
+        int reg3 = vcpu->arch.sie_block->ipa & 0x000f;
+        u64 useraddr;
+        int reg, rc;
+
+        vcpu->stat.instruction_lctlg++;
+
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
+        useraddr = kvm_s390_get_base_disp_rsy(vcpu);
+
+        if (useraddr & 7)
+                return kvm_s390_inject_program_int(vcpu, PGM_SPECIFICATION);
+
+        reg = reg1;
+
+        VCPU_EVENT(vcpu, 5, "lctlg r1:%x, r3:%x, addr:%llx", reg1, reg3,
+                   useraddr);
+        trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, useraddr);
+
+        do {
+                rc = get_guest(vcpu, vcpu->arch.sie_block->gcr[reg],
+                               (u64 __user *) useraddr);
+                if (rc)
+                        return kvm_s390_inject_program_int(vcpu, PGM_ADDRESSING);
+                useraddr += 8;
+                if (reg == reg3)
+                        break;
+                reg = (reg + 1) % 16;
+        } while (1);
+
+        return 0;
+}
+
 static const intercept_handler_t eb_handlers[256] = {
+        [0x2f] = handle_lctlg,
         [0x8a] = handle_io_inst,
 };
 
-int kvm_s390_handle_priv_eb(struct kvm_vcpu *vcpu)
+int kvm_s390_handle_eb(struct kvm_vcpu *vcpu)
 {
         intercept_handler_t handler;
 
-        /* All eb instructions that end up here are privileged. */
-        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
-                return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
         handler = eb_handlers[vcpu->arch.sie_block->ipb & 0xff];
         if (handler)
                 return handler(vcpu);
@@ -515,6 +697,9 @@ static int handle_tprot(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_tprot++;
 
+        if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
+
         kvm_s390_get_base_disp_sse(vcpu, &address1, &address2);
 
         /* we only handle the Linux memory detection case:
@@ -560,8 +745,7 @@ static int handle_sckpf(struct kvm_vcpu *vcpu)
         u32 value;
 
         if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
-                return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
 
         if (vcpu->run->s.regs.gprs[0] & 0x00000000ffff0000)
                 return kvm_s390_inject_program_int(vcpu,
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 1c48ab2845e0..bec398c57acf 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -79,8 +79,8 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
         list_add_tail(&inti->list, &li->list);
         atomic_set(&li->active, 1);
         atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&li->wq);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
         spin_unlock_bh(&li->lock);
         rc = SIGP_CC_ORDER_CODE_ACCEPTED;
         VCPU_EVENT(vcpu, 4, "sent sigp emerg to cpu %x", cpu_addr);
@@ -117,8 +117,8 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
         list_add_tail(&inti->list, &li->list);
         atomic_set(&li->active, 1);
         atomic_set_mask(CPUSTAT_EXT_INT, li->cpuflags);
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&li->wq);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
         spin_unlock_bh(&li->lock);
         rc = SIGP_CC_ORDER_CODE_ACCEPTED;
         VCPU_EVENT(vcpu, 4, "sent sigp ext call to cpu %x", cpu_addr);
@@ -145,8 +145,8 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
         atomic_set(&li->active, 1);
         atomic_set_mask(CPUSTAT_STOP_INT, li->cpuflags);
         li->action_bits |= action;
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&li->wq);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
 out:
         spin_unlock_bh(&li->lock);
 
@@ -250,8 +250,8 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
 
         list_add_tail(&inti->list, &li->list);
         atomic_set(&li->active, 1);
-        if (waitqueue_active(&li->wq))
-                wake_up_interruptible(&li->wq);
+        if (waitqueue_active(li->wq))
+                wake_up_interruptible(li->wq);
         rc = SIGP_CC_ORDER_CODE_ACCEPTED;
 
         VCPU_EVENT(vcpu, 4, "set prefix of cpu %02x to %x", cpu_addr, address);
@@ -333,8 +333,7 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
 
         /* sigp in userspace can exit */
         if (vcpu->arch.sie_block->gpsw.mask & PSW_MASK_PSTATE)
-                return kvm_s390_inject_program_int(vcpu,
-                                                   PGM_PRIVILEGED_OPERATION);
+                return kvm_s390_inject_program_int(vcpu, PGM_PRIVILEGED_OP);
 
         order_code = kvm_s390_get_base_disp_rs(vcpu);
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 89ebae4008f2..ce36ea80e4f9 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -135,30 +135,17 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        unsigned long codesize, reservedpages, datasize, initsize;
-
-        max_mapnr = num_physpages = max_low_pfn;
+        max_mapnr = max_low_pfn;
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
 
         /* Setup guest page hinting */
         cmma_init();
 
         /* this will put all low memory onto the freelists */
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
         setup_zero_pages();     /* Setup zeroed pages. */
 
-        reservedpages = 0;
-
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-        printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, %ldk data, %ldk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                max_mapnr << (PAGE_SHIFT-10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >>10,
-                initsize >> 10);
+        mem_init_print_info(NULL);
         printk("Write protected kernel read-only data: %#lx - %#lx\n",
                (unsigned long)&_stext,
                PFN_ALIGN((unsigned long)&_eshared) - 1);
@@ -166,13 +153,14 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/s390/mm/mem_detect.c b/arch/s390/mm/mem_detect.c
index 3cbd3b8bf311..cca388253a39 100644
--- a/arch/s390/mm/mem_detect.c
+++ b/arch/s390/mm/mem_detect.c
@@ -123,7 +123,8 @@ void create_mem_hole(struct mem_chunk mem_chunk[], unsigned long addr,
                         continue;
                 } else if ((addr <= chunk->addr) &&
                            (addr + size >= chunk->addr + chunk->size)) {
-                        memset(chunk, 0 , sizeof(*chunk));
+                        memmove(chunk, chunk + 1, (MEMORY_CHUNKS-i-1) * sizeof(*chunk));
+                        memset(&mem_chunk[MEMORY_CHUNKS-1], 0, sizeof(*chunk));
                 } else if (addr + size < chunk->addr + chunk->size) {
                         chunk->size =  chunk->addr + chunk->size - addr - size;
                         chunk->addr = addr + size;
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index a938b548f07e..a8154a1a2c94 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -689,7 +689,7 @@ int gmap_ipte_notify(struct gmap *gmap, unsigned long start, unsigned long len)
                 entry = *ptep;
                 if ((pte_val(entry) & (_PAGE_INVALID | _PAGE_RO)) == 0) {
                         pgste = pgste_get_lock(ptep);
-                        pgste_val(pgste) |= RCP_IN_BIT;
+                        pgste_val(pgste) |= PGSTE_IN_BIT;
                         pgste_set_unlock(ptep, pgste);
                         start += PAGE_SIZE;
                         len -= PAGE_SIZE;
@@ -771,6 +771,54 @@ static inline void page_table_free_pgste(unsigned long *table)
         __free_page(page);
 }
 
+int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
+                          unsigned long key, bool nq)
+{
+        spinlock_t *ptl;
+        pgste_t old, new;
+        pte_t *ptep;
+
+        down_read(&mm->mmap_sem);
+        ptep = get_locked_pte(current->mm, addr, &ptl);
+        if (unlikely(!ptep)) {
+                up_read(&mm->mmap_sem);
+                return -EFAULT;
+        }
+
+        new = old = pgste_get_lock(ptep);
+        pgste_val(new) &= ~(PGSTE_GR_BIT | PGSTE_GC_BIT |
+                            PGSTE_ACC_BITS | PGSTE_FP_BIT);
+        pgste_val(new) |= (key & (_PAGE_CHANGED | _PAGE_REFERENCED)) << 48;
+        pgste_val(new) |= (key & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
+        if (!(pte_val(*ptep) & _PAGE_INVALID)) {
+                unsigned long address, bits;
+                unsigned char skey;
+
+                address = pte_val(*ptep) & PAGE_MASK;
+                skey = page_get_storage_key(address);
+                bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
+                /* Set storage key ACC and FP */
+                page_set_storage_key(address,
+                                (key & (_PAGE_ACC_BITS | _PAGE_FP_BIT)),
+                                !nq);
+
+                /* Merge host changed & referenced into pgste  */
+                pgste_val(new) |= bits << 52;
+                /* Transfer skey changed & referenced bit to kvm user bits */
+                pgste_val(new) |= bits << 45;   /* PGSTE_UR_BIT & PGSTE_UC_BIT */
+        }
+        /* changing the guest storage key is considered a change of the page */
+        if ((pgste_val(new) ^ pgste_val(old)) &
+            (PGSTE_ACC_BITS | PGSTE_FP_BIT | PGSTE_GR_BIT | PGSTE_GC_BIT))
+                pgste_val(new) |= PGSTE_UC_BIT;
+
+        pgste_set_unlock(ptep, new);
+        pte_unmap_unlock(*ptep, ptl);
+        up_read(&mm->mmap_sem);
+        return 0;
+}
+EXPORT_SYMBOL(set_guest_storage_key);
+
 #else /* CONFIG_PGSTE */
 
 static inline unsigned long *page_table_alloc_pgste(struct mm_struct *mm,
@@ -1117,7 +1165,8 @@ void pmdp_splitting_flush(struct vm_area_struct *vma, unsigned long address,
         }
 }
 
-void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable)
+void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                pgtable_t pgtable)
 {
         struct list_head *lh = (struct list_head *) pgtable;
 
@@ -1131,7 +1180,7 @@ void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable)
         mm->pmd_huge_pte = pgtable;
 }
 
-pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm)
+pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 {
         struct list_head *lh;
         pgtable_t pgtable;
diff --git a/arch/s390/oprofile/hwsampler.h b/arch/s390/oprofile/hwsampler.h
index 1912f3bb190c..0022e1ebfbde 100644
--- a/arch/s390/oprofile/hwsampler.h
+++ b/arch/s390/oprofile/hwsampler.h
@@ -81,8 +81,8 @@ struct hws_data_entry {
         unsigned int:16;
         unsigned int prim_asn:16;   /* primary ASN                       */
         unsigned long long ia;      /* Instruction Address               */
-        unsigned long long lpp;     /* Logical-Partition Program Param.  */
-        unsigned long long vpp;     /* Virtual-Machine Program Param.    */
+        unsigned long long gpp;     /* Guest Program Parameter           */
+        unsigned long long hpp;     /* Host Program Parameter            */
 };
 
 struct hws_trailer_entry {
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index e6f15b5d8b7d..e2956ad39a4f 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -82,10 +82,13 @@ struct intr_bucket {
 
 static struct intr_bucket *bucket;
 
-/* Adapter local summary indicator */
-static u8 *zpci_irq_si;
+/* Adapter interrupt definitions */
+static void zpci_irq_handler(struct airq_struct *airq);
 
-static atomic_t irq_retries = ATOMIC_INIT(0);
+static struct airq_struct zpci_airq = {
+        .handler = zpci_irq_handler,
+        .isc = PCI_ISC,
+};
 
 /* I/O Map */
 static DEFINE_SPINLOCK(zpci_iomap_lock);
@@ -302,15 +305,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
         return rc;
 }
 
-void synchronize_irq(unsigned int irq)
-{
-        /*
-         * Not needed, the handler is protected by a lock and IRQs that occur
-         * after the handler is deleted are just NOPs.
-         */
-}
-EXPORT_SYMBOL_GPL(synchronize_irq);
-
 void enable_irq(unsigned int irq)
 {
         struct msi_desc *msi = irq_get_msi_desc(irq);
@@ -327,30 +321,6 @@ void disable_irq(unsigned int irq)
 }
 EXPORT_SYMBOL_GPL(disable_irq);
 
-void disable_irq_nosync(unsigned int irq)
-{
-        disable_irq(irq);
-}
-EXPORT_SYMBOL_GPL(disable_irq_nosync);
-
-unsigned long probe_irq_on(void)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_on);
-
-int probe_irq_off(unsigned long val)
-{
-        return 0;
-}
-EXPORT_SYMBOL_GPL(probe_irq_off);
-
-unsigned int probe_irq_mask(unsigned long val)
-{
-        return val;
-}
-EXPORT_SYMBOL_GPL(probe_irq_mask);
-
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
 }
@@ -437,7 +407,7 @@ static struct pci_ops pci_root_ops = {
 /* store the last handled bit to implement fair scheduling of devices */
 static DEFINE_PER_CPU(unsigned long, next_sbit);
 
-static void zpci_irq_handler(void *dont, void *need)
+static void zpci_irq_handler(struct airq_struct *airq)
 {
         unsigned long sbit, mbit, last = 0, start = __get_cpu_var(next_sbit);
         int rescan = 0, max = aisb_max;
@@ -485,7 +455,6 @@ scan:
         max = aisb_max;
         sbit = find_first_bit_left(bucket->aisb, max);
         if (sbit != max) {
-                atomic_inc(&irq_retries);
                 rescan++;
                 goto scan;
         }
@@ -598,7 +567,21 @@ static void zpci_map_resources(struct zpci_dev *zdev)
                 pr_debug("BAR%i: -> start: %Lx  end: %Lx\n",
                         i, pdev->resource[i].start, pdev->resource[i].end);
         }
-};
+}
+
+static void zpci_unmap_resources(struct zpci_dev *zdev)
+{
+        struct pci_dev *pdev = zdev->pdev;
+        resource_size_t len;
+        int i;
+
+        for (i = 0; i < PCI_BAR_COUNT; i++) {
+                len = pci_resource_len(pdev, i);
+                if (!len)
+                        continue;
+                pci_iounmap(pdev, (void *) pdev->resource[i].start);
+        }
+}
 
 struct zpci_dev *zpci_alloc_device(void)
 {
@@ -734,25 +717,20 @@ static int __init zpci_irq_init(void)
                 goto out_alloc;
         }
 
-        isc_register(PCI_ISC);
-        zpci_irq_si = s390_register_adapter_interrupt(&zpci_irq_handler, NULL, PCI_ISC);
-        if (IS_ERR(zpci_irq_si)) {
-                rc = PTR_ERR(zpci_irq_si);
-                zpci_irq_si = NULL;
+        rc = register_adapter_interrupt(&zpci_airq);
+        if (rc)
                 goto out_ai;
-        }
+        /* Set summary to 1 to be called every time for the ISC. */
+        *zpci_airq.lsi_ptr = 1;
 
         for_each_online_cpu(cpu)
                 per_cpu(next_sbit, cpu) = 0;
 
         spin_lock_init(&bucket->lock);
-        /* set summary to 1 to be called every time for the ISC */
-        *zpci_irq_si = 1;
         set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
         return 0;
 
 out_ai:
-        isc_unregister(PCI_ISC);
         free_page((unsigned long) bucket->alloc);
 out_alloc:
         free_page((unsigned long) bucket->aisb);
@@ -765,21 +743,10 @@ static void zpci_irq_exit(void)
 {
         free_page((unsigned long) bucket->alloc);
         free_page((unsigned long) bucket->aisb);
-        s390_unregister_adapter_interrupt(zpci_irq_si, PCI_ISC);
-        isc_unregister(PCI_ISC);
+        unregister_adapter_interrupt(&zpci_airq);
         kfree(bucket);
 }
 
-void zpci_debug_info(struct zpci_dev *zdev, struct seq_file *m)
-{
-        if (!zdev)
-                return;
-
-        seq_printf(m, "global irq retries: %u\n", atomic_read(&irq_retries));
-        seq_printf(m, "aibv[0]:%016lx  aibv[1]:%016lx  aisb:%016lx\n",
-                   get_imap(0)->aibv, get_imap(1)->aibv, *bucket->aisb);
-}
-
 static struct resource *zpci_alloc_bus_resource(unsigned long start, unsigned long size,
                                                 unsigned long flags, int domain)
 {
@@ -843,6 +810,16 @@ int pcibios_add_device(struct pci_dev *pdev)
         return 0;
 }
 
+void pcibios_release_device(struct pci_dev *pdev)
+{
+        struct zpci_dev *zdev = get_zdev(pdev);
+
+        zpci_unmap_resources(zdev);
+        zpci_fmb_disable_device(zdev);
+        zpci_debug_exit_device(zdev);
+        zdev->pdev = NULL;
+}
+
 static int zpci_scan_bus(struct zpci_dev *zdev)
 {
         struct resource *res;
@@ -983,25 +960,6 @@ void zpci_stop_device(struct zpci_dev *zdev)
 }
 EXPORT_SYMBOL_GPL(zpci_stop_device);
 
-int zpci_scan_device(struct zpci_dev *zdev)
-{
-        zdev->pdev = pci_scan_single_device(zdev->bus, ZPCI_DEVFN);
-        if (!zdev->pdev) {
-                pr_err("pci_scan_single_device failed for fid: 0x%x\n",
-                        zdev->fid);
-                goto out;
-        }
-
-        pci_bus_add_devices(zdev->bus);
-
-        return 0;
-out:
-        zpci_dma_exit_device(zdev);
-        clp_disable_fh(zdev);
-        return -EIO;
-}
-EXPORT_SYMBOL_GPL(zpci_scan_device);
-
 static inline int barsize(u8 size)
 {
         return (size) ? (1 << size) >> 10 : 0;
diff --git a/arch/s390/pci/pci_clp.c b/arch/s390/pci/pci_clp.c
index bd34359d1546..2e9539625d93 100644
--- a/arch/s390/pci/pci_clp.c
+++ b/arch/s390/pci/pci_clp.c
@@ -236,7 +236,6 @@ int clp_disable_fh(struct zpci_dev *zdev)
         if (!zdev_enabled(zdev))
                 return 0;
 
-        dev_info(&zdev->pdev->dev, "disabling fn handle: 0x%x\n", fh);
         rc = clp_set_pci_fn(&fh, 0, CLP_SET_DISABLE_PCI_FN);
         if (!rc)
                 /* Success -> store disabled handle in zdev */
diff --git a/arch/s390/pci/pci_debug.c b/arch/s390/pci/pci_debug.c
index 771b82359af4..75c69b402e05 100644
--- a/arch/s390/pci/pci_debug.c
+++ b/arch/s390/pci/pci_debug.c
@@ -115,27 +115,6 @@ static const struct file_operations debugfs_pci_perf_fops = {
         .release = single_release,
 };
 
-static int pci_debug_show(struct seq_file *m, void *v)
-{
-        struct zpci_dev *zdev = m->private;
-
-        zpci_debug_info(zdev, m);
-        return 0;
-}
-
-static int pci_debug_seq_open(struct inode *inode, struct file *filp)
-{
-        return single_open(filp, pci_debug_show,
-                           file_inode(filp)->i_private);
-}
-
-static const struct file_operations debugfs_pci_debug_fops = {
-        .open    = pci_debug_seq_open,
-        .read    = seq_read,
-        .llseek  = seq_lseek,
-        .release = single_release,
-};
-
 void zpci_debug_init_device(struct zpci_dev *zdev)
 {
         zdev->debugfs_dev = debugfs_create_dir(dev_name(&zdev->pdev->dev),
@@ -149,19 +128,11 @@ void zpci_debug_init_device(struct zpci_dev *zdev)
                                 &debugfs_pci_perf_fops);
         if (IS_ERR(zdev->debugfs_perf))
                 zdev->debugfs_perf = NULL;
-
-        zdev->debugfs_debug = debugfs_create_file("debug",
-                                S_IFREG | S_IRUGO | S_IWUSR,
-                                zdev->debugfs_dev, zdev,
-                                &debugfs_pci_debug_fops);
-        if (IS_ERR(zdev->debugfs_debug))
-                zdev->debugfs_debug = NULL;
 }
 
 void zpci_debug_exit_device(struct zpci_dev *zdev)
 {
         debugfs_remove(zdev->debugfs_perf);
-        debugfs_remove(zdev->debugfs_debug);
         debugfs_remove(zdev->debugfs_dev);
 }
 
diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c
index f8e69d5bc0a9..a2343c1f6e04 100644
--- a/arch/s390/pci/pci_dma.c
+++ b/arch/s390/pci/pci_dma.c
@@ -263,7 +263,7 @@ static dma_addr_t s390_dma_map_pages(struct device *dev, struct page *page,
                                      enum dma_data_direction direction,
                                      struct dma_attrs *attrs)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
         unsigned long nr_pages, iommu_page_index;
         unsigned long pa = page_to_phys(page) + offset;
         int flags = ZPCI_PTE_VALID;
@@ -304,7 +304,7 @@ static void s390_dma_unmap_pages(struct device *dev, dma_addr_t dma_addr,
                                  size_t size, enum dma_data_direction direction,
                                  struct dma_attrs *attrs)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
         unsigned long iommu_page_index;
         int npages;
 
@@ -323,7 +323,7 @@ static void *s390_dma_alloc(struct device *dev, size_t size,
                             dma_addr_t *dma_handle, gfp_t flag,
                             struct dma_attrs *attrs)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
         struct page *page;
         unsigned long pa;
         dma_addr_t map;
diff --git a/arch/s390/pci/pci_sysfs.c b/arch/s390/pci/pci_sysfs.c
index a42cce69d0a0..e99a2557f186 100644
--- a/arch/s390/pci/pci_sysfs.c
+++ b/arch/s390/pci/pci_sysfs.c
@@ -15,40 +15,36 @@
 static ssize_t show_fid(struct device *dev, struct device_attribute *attr,
                         char *buf)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
 
-        sprintf(buf, "0x%08x\n", zdev->fid);
-        return strlen(buf);
+        return sprintf(buf, "0x%08x\n", zdev->fid);
 }
 static DEVICE_ATTR(function_id, S_IRUGO, show_fid, NULL);
 
 static ssize_t show_fh(struct device *dev, struct device_attribute *attr,
                        char *buf)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
 
-        sprintf(buf, "0x%08x\n", zdev->fh);
-        return strlen(buf);
+        return sprintf(buf, "0x%08x\n", zdev->fh);
 }
 static DEVICE_ATTR(function_handle, S_IRUGO, show_fh, NULL);
 
 static ssize_t show_pchid(struct device *dev, struct device_attribute *attr,
                           char *buf)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
 
-        sprintf(buf, "0x%04x\n", zdev->pchid);
-        return strlen(buf);
+        return sprintf(buf, "0x%04x\n", zdev->pchid);
 }
 static DEVICE_ATTR(pchid, S_IRUGO, show_pchid, NULL);
 
 static ssize_t show_pfgid(struct device *dev, struct device_attribute *attr,
                           char *buf)
 {
-        struct zpci_dev *zdev = get_zdev(container_of(dev, struct pci_dev, dev));
+        struct zpci_dev *zdev = get_zdev(to_pci_dev(dev));
 
-        sprintf(buf, "0x%02x\n", zdev->pfgid);
-        return strlen(buf);
+        return sprintf(buf, "0x%02x\n", zdev->pfgid);
 }
 static DEVICE_ATTR(pfgid, S_IRUGO, show_pfgid, NULL);
 
diff --git a/arch/score/include/asm/Kbuild b/arch/score/include/asm/Kbuild
index cebaff8069a1..e1c7bb999b06 100644
--- a/arch/score/include/asm/Kbuild
+++ b/arch/score/include/asm/Kbuild
@@ -3,3 +3,4 @@ header-y +=
 
 generic-y += clkdev.h
 generic-y += trace_clock.h
+generic-y += xor.h
diff --git a/arch/score/include/asm/dma-mapping.h b/arch/score/include/asm/dma-mapping.h
deleted file mode 100644
index f9c0193c7a53..000000000000
--- a/arch/score/include/asm/dma-mapping.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_SCORE_DMA_MAPPING_H
-#define _ASM_SCORE_DMA_MAPPING_H
-
-#include <asm-generic/dma-mapping-broken.h>
-
-#endif /* _ASM_SCORE_DMA_MAPPING_H */
diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h
index 2fd469807683..db96ad9afc03 100644
--- a/arch/score/include/asm/pgtable.h
+++ b/arch/score/include/asm/pgtable.h
@@ -113,9 +113,6 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
 #define pte_clear(mm, addr, xp)         \
         do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 /*
  * The "pgd_xxx()" functions here are trivial for a folded two-level
  * setup: the pgd is never bad, and a pmd always exists (as it's folded
diff --git a/arch/score/kernel/vmlinux.lds.S b/arch/score/kernel/vmlinux.lds.S
index eebcbaa4e978..7274b5c4287e 100644
--- a/arch/score/kernel/vmlinux.lds.S
+++ b/arch/score/kernel/vmlinux.lds.S
@@ -49,6 +49,7 @@ SECTIONS
         }
 
         . = ALIGN(16);
+        _sdata =  .;                    /* Start of data section */
         RODATA
 
         EXCEPTION_TABLE(16)
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 0940682ab38b..9fbce49ad3bd 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -75,40 +75,19 @@ void __init paging_init(void)
 
 void __init mem_init(void)
 {
-        unsigned long codesize, reservedpages, datasize, initsize;
-        unsigned long tmp, ram = 0;
-
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
         setup_zero_page();      /* Setup zeroed pages. */
-        reservedpages = 0;
-
-        for (tmp = 0; tmp < max_low_pfn; tmp++)
-                if (page_is_ram(tmp)) {
-                        ram++;
-                        if (PageReserved(pfn_to_page(tmp)))
-                                reservedpages++;
-                }
-
-        num_physpages = ram;
-        codesize = (unsigned long) &_etext - (unsigned long) &_text;
-        datasize = (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
-                        "%ldk reserved, %ldk data, %ldk init, %ldk highmem)\n",
-                        (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-                        ram << (PAGE_SHIFT-10), codesize >> 10,
-                        reservedpages << (PAGE_SHIFT-10), datasize >> 10,
-                        initsize >> 10,
-                        totalhigh_pages << (PAGE_SHIFT-10));
+
+        mem_init_print_info(NULL);
 }
 #endif /* !CONFIG_NEED_MULTIPLE_NODES */
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, POISON_FREE_INITMEM, "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 8c868cf2cf93..1020dd85431a 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -748,7 +748,7 @@ config NR_CPUS
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
-        depends on SMP && HOTPLUG
+        depends on SMP
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
diff --git a/arch/sh/include/asm/mutex-llsc.h b/arch/sh/include/asm/mutex-llsc.h
index 090358a7e1bb..dad29b687bd3 100644
--- a/arch/sh/include/asm/mutex-llsc.h
+++ b/arch/sh/include/asm/mutex-llsc.h
@@ -37,7 +37,7 @@ __mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
 }
 
 static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count)
 {
         int __done, __res;
 
@@ -51,7 +51,7 @@ __mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
                 : "t");
 
         if (unlikely(!__done || __res != 0))
-                __res = fail_fn(count);
+                __res = -1;
 
         return __res;
 }
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index 9210e93a92c3..cf434c64408d 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -124,9 +124,6 @@ typedef pte_t *pte_addr_t;
 
 #define kern_addr_valid(addr)   (1)
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 
 /*
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 20f9ead650d3..33890fd267cb 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -407,30 +407,16 @@ unsigned int mem_init_done = 0;
 
 void __init mem_init(void)
 {
-        int codesize, datasize, initsize;
-        int nid;
+        pg_data_t *pgdat;
 
         iommu_init();
 
-        num_physpages = 0;
         high_memory = NULL;
+        for_each_online_pgdat(pgdat)
+                high_memory = max_t(void *, high_memory,
+                                    __va(pgdat_end_pfn(pgdat) << PAGE_SHIFT));
 
-        for_each_online_node(nid) {
-                pg_data_t *pgdat = NODE_DATA(nid);
-                void *node_high_memory;
-
-                num_physpages += pgdat->node_present_pages;
-
-                if (pgdat->node_spanned_pages)
-                        totalram_pages += free_all_bootmem_node(pgdat);
-
-
-                node_high_memory = (void *)__va((pgdat->node_start_pfn +
-                                                 pgdat->node_spanned_pages) <<
-                                                 PAGE_SHIFT);
-                if (node_high_memory > high_memory)
-                        high_memory = node_high_memory;
-        }
+        free_all_bootmem();
 
         /* Set this up early, so we can take care of the zero page */
         cpu_cache_init();
@@ -441,19 +427,8 @@ void __init mem_init(void)
 
         vsyscall_init();
 
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, "
-               "%dk data, %dk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                datasize >> 10,
-                initsize >> 10);
-
-        printk(KERN_INFO "virtual kernel memory layout:\n"
+        mem_init_print_info(NULL);
+        pr_info("virtual kernel memory layout:\n"
                 "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_HIGHMEM
                 "    pkmap   : 0x%08lx - 0x%08lx   (%4ld kB)\n"
@@ -499,13 +474,13 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 9ac9f1666339..a00cbd356db5 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -243,7 +243,6 @@ config SECCOMP
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
         depends on SPARC64 && SMP
-        select HOTPLUG
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu/cpu#.
diff --git a/arch/sparc/include/asm/Kbuild b/arch/sparc/include/asm/Kbuild
index ff18e3cfb6b1..7e4a97fbded4 100644
--- a/arch/sparc/include/asm/Kbuild
+++ b/arch/sparc/include/asm/Kbuild
@@ -6,6 +6,7 @@ generic-y += cputime.h
 generic-y += div64.h
 generic-y += emergency-restart.h
 generic-y += exec.h
+generic-y += linkage.h
 generic-y += local64.h
 generic-y += mutex.h
 generic-y += irq_regs.h
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
index 15a716934e4d..b836e9297f2a 100644
--- a/arch/sparc/include/asm/leon.h
+++ b/arch/sparc/include/asm/leon.h
@@ -135,7 +135,7 @@ static inline int sparc_leon3_cpuid(void)
 
 #ifdef CONFIG_SMP
 # define LEON3_IRQ_IPI_DEFAULT          13
-# define LEON3_IRQ_TICKER               (leon3_ticker_irq)
+# define LEON3_IRQ_TICKER               (leon3_gptimer_irq)
 # define LEON3_IRQ_CROSS_CALL           15
 #endif
 
diff --git a/arch/sparc/include/asm/leon_amba.h b/arch/sparc/include/asm/leon_amba.h
index f3034eddf468..24ec48c3ff90 100644
--- a/arch/sparc/include/asm/leon_amba.h
+++ b/arch/sparc/include/asm/leon_amba.h
@@ -47,6 +47,7 @@ struct amba_prom_registers {
 #define LEON3_GPTIMER_LD 4
 #define LEON3_GPTIMER_IRQEN 8
 #define LEON3_GPTIMER_SEPIRQ 8
+#define LEON3_GPTIMER_TIMERS 0x7
 
 #define LEON23_REG_TIMER_CONTROL_EN    0x00000001 /* 1 = enable counting */
 /* 0 = hold scalar and counter */
diff --git a/arch/sparc/include/asm/linkage.h b/arch/sparc/include/asm/linkage.h
deleted file mode 100644
index 291c2d01c44f..000000000000
--- a/arch/sparc/include/asm/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index 6fc13483f702..502f632f6cc7 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -443,6 +443,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 
         return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
 }
+#define io_remap_pfn_range io_remap_pfn_range 
 
 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 #define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index 7619f2f792af..36760317814f 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -853,10 +853,11 @@ extern void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
                                  pmd_t *pmd);
 
 #define __HAVE_ARCH_PGTABLE_DEPOSIT
-extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
+extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                       pgtable_t pgtable);
 
 #define __HAVE_ARCH_PGTABLE_WITHDRAW
-extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
+extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
 #endif
 
 /* Encode and de-code a swap entry */
@@ -914,6 +915,7 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
 
         return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
 }
+#define io_remap_pfn_range io_remap_pfn_range 
 
 #include <asm/tlbflush.h>
 #include <asm-generic/pgtable.h>
diff --git a/arch/sparc/include/uapi/asm/fcntl.h b/arch/sparc/include/uapi/asm/fcntl.h
index d0b83f66f356..d73e5e008b0d 100644
--- a/arch/sparc/include/uapi/asm/fcntl.h
+++ b/arch/sparc/include/uapi/asm/fcntl.h
@@ -35,6 +35,7 @@
 #define O_SYNC          (__O_SYNC|O_DSYNC)
 
 #define O_PATH          0x1000000
+#define O_TMPFILE       0x2000000
 
 #define F_GETOWN        5       /*  for sockets. */
 #define F_SETOWN        6       /*  for sockets. */
diff --git a/arch/sparc/kernel/ds.c b/arch/sparc/kernel/ds.c
index 75bb608c423e..5ef48dab5636 100644
--- a/arch/sparc/kernel/ds.c
+++ b/arch/sparc/kernel/ds.c
@@ -843,7 +843,8 @@ void ldom_reboot(const char *boot_command)
                 unsigned long len;
 
                 strcpy(full_boot_str, "boot ");
-                strcpy(full_boot_str + strlen("boot "), boot_command);
+                strlcpy(full_boot_str + strlen("boot "), boot_command,
+                        sizeof(full_boot_str + strlen("boot ")));
                 len = strlen(full_boot_str);
 
                 if (reboot_data_supported) {
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index 7c0231dabe44..b7c68976cbc7 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -38,7 +38,6 @@ static DEFINE_SPINLOCK(leon_irq_lock);
 
 unsigned long leon3_gptimer_irq; /* interrupt controller irq number */
 unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */
-int leon3_ticker_irq; /* Timer ticker IRQ */
 unsigned int sparc_leon_eirq;
 #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu])
 #define LEON_IACK (&leon3_irqctrl_regs->iclear)
@@ -278,6 +277,9 @@ irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused)
 
         leon_clear_profile_irq(cpu);
 
+        if (cpu == boot_cpu_id)
+                timer_interrupt(irq, NULL);
+
         ce = &per_cpu(sparc32_clockevent, cpu);
 
         irq_enter();
@@ -299,6 +301,7 @@ void __init leon_init_timers(void)
         int icsel;
         int ampopts;
         int err;
+        u32 config;
 
         sparc_config.get_cycles_offset = leon_cycles_offset;
         sparc_config.cs_period = 1000000 / HZ;
@@ -377,23 +380,6 @@ void __init leon_init_timers(void)
         LEON3_BYPASS_STORE_PA(
                         &leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0);
 
-#ifdef CONFIG_SMP
-        leon3_ticker_irq = leon3_gptimer_irq + 1 + leon3_gptimer_idx;
-
-        if (!(LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config) &
-              (1<<LEON3_GPTIMER_SEPIRQ))) {
-                printk(KERN_ERR "timer not configured with separate irqs\n");
-                BUG();
-        }
-
-        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].val,
-                                0);
-        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].rld,
-                                (((1000000/HZ) - 1)));
-        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl,
-                                0);
-#endif
-
         /*
          * The IRQ controller may (if implemented) consist of multiple
          * IRQ controllers, each mapped on a 4Kb boundary.
@@ -416,13 +402,6 @@ void __init leon_init_timers(void)
         if (eirq != 0)
                 leon_eirq_setup(eirq);
 
-        irq = _leon_build_device_irq(NULL, leon3_gptimer_irq+leon3_gptimer_idx);
-        err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
-        if (err) {
-                printk(KERN_ERR "unable to attach timer IRQ%d\n", irq);
-                prom_halt();
-        }
-
 #ifdef CONFIG_SMP
         {
                 unsigned long flags;
@@ -439,30 +418,31 @@ void __init leon_init_timers(void)
         }
 #endif
 
-        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl,
-                              LEON3_GPTIMER_EN |
-                              LEON3_GPTIMER_RL |
-                              LEON3_GPTIMER_LD |
-                              LEON3_GPTIMER_IRQEN);
+        config = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config);
+        if (config & (1 << LEON3_GPTIMER_SEPIRQ))
+                leon3_gptimer_irq += leon3_gptimer_idx;
+        else if ((config & LEON3_GPTIMER_TIMERS) > 1)
+                pr_warn("GPTIMER uses shared irqs, using other timers of the same core will fail.\n");
 
 #ifdef CONFIG_SMP
         /* Install per-cpu IRQ handler for broadcasted ticker */
-        irq = leon_build_device_irq(leon3_ticker_irq, handle_percpu_irq,
+        irq = leon_build_device_irq(leon3_gptimer_irq, handle_percpu_irq,
                                     "per-cpu", 0);
         err = request_irq(irq, leon_percpu_timer_ce_interrupt,
-                          IRQF_PERCPU | IRQF_TIMER, "ticker",
-                          NULL);
+                          IRQF_PERCPU | IRQF_TIMER, "timer", NULL);
+#else
+        irq = _leon_build_device_irq(NULL, leon3_gptimer_irq);
+        err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
+#endif
         if (err) {
-                printk(KERN_ERR "unable to attach ticker IRQ%d\n", irq);
+                pr_err("Unable to attach timer IRQ%d\n", irq);
                 prom_halt();
         }
-
-        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl,
+        LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl,
                               LEON3_GPTIMER_EN |
                               LEON3_GPTIMER_RL |
                               LEON3_GPTIMER_LD |
                               LEON3_GPTIMER_IRQEN);
-#endif
         return;
 bad:
         printk(KERN_ERR "No Timer/irqctrl found\n");
diff --git a/arch/sparc/kernel/leon_pci_grpci1.c b/arch/sparc/kernel/leon_pci_grpci1.c
index 7739a54315e2..6df26e37f879 100644
--- a/arch/sparc/kernel/leon_pci_grpci1.c
+++ b/arch/sparc/kernel/leon_pci_grpci1.c
@@ -536,11 +536,9 @@ static int grpci1_of_probe(struct platform_device *ofdev)
 
         /* find device register base address */
         res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
-        regs = devm_request_and_ioremap(&ofdev->dev, res);
-        if (!regs) {
-                dev_err(&ofdev->dev, "io-regs mapping failed\n");
-                return -EADDRNOTAVAIL;
-        }
+        regs = devm_ioremap_resource(&ofdev->dev, res);
+        if (IS_ERR(regs))
+                return PTR_ERR(regs);
 
         /*
          * check that we're in Host Slot and that we can act as a Host Bridge
diff --git a/arch/sparc/kernel/leon_pmc.c b/arch/sparc/kernel/leon_pmc.c
index bdf53d9a8d46..b0b3967a2dd2 100644
--- a/arch/sparc/kernel/leon_pmc.c
+++ b/arch/sparc/kernel/leon_pmc.c
@@ -47,6 +47,10 @@ void pmc_leon_idle_fixup(void)
          * MMU does not get a TLB miss here by using the MMU BYPASS ASI.
          */
         register unsigned int address = (unsigned int)leon3_irqctrl_regs;
+
+        /* Interrupts need to be enabled to not hang the CPU */
+        local_irq_enable();
+
         __asm__ __volatile__ (
                 "wr     %%g0, %%asr19\n"
                 "lda    [%0] %1, %%g0\n"
@@ -60,6 +64,9 @@ void pmc_leon_idle_fixup(void)
  */
 void pmc_leon_idle(void)
 {
+        /* Interrupts need to be enabled to not hang the CPU */
+        local_irq_enable();
+
         /* For systems without power-down, this will be no-op */
         __asm__ __volatile__ ("wr       %g0, %asr19\n\t");
 }
diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c
index 6cfc1b09ec25..d7aa524b7283 100644
--- a/arch/sparc/kernel/leon_smp.c
+++ b/arch/sparc/kernel/leon_smp.c
@@ -254,15 +254,12 @@ void __init leon_smp_done(void)
         /* Free unneeded trap tables */
         if (!cpu_present(1)) {
                 free_reserved_page(virt_to_page(&trapbase_cpu1));
-                num_physpages++;
         }
         if (!cpu_present(2)) {
                 free_reserved_page(virt_to_page(&trapbase_cpu2));
-                num_physpages++;
         }
         if (!cpu_present(3)) {
                 free_reserved_page(virt_to_page(&trapbase_cpu3));
-                num_physpages++;
         }
         /* Ok, they are spinning and ready to go. */
         smp_processors_ready = 1;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index baf4366e2d6a..bc4d3f5d2e5d 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -254,7 +254,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         const char *type;
         u32 class;
 
-        dev = alloc_pci_dev();
+        dev = pci_alloc_dev(bus);
         if (!dev)
                 return NULL;
 
@@ -281,7 +281,6 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
                 printk("    create device, devfn: %x, type: %s\n",
                        devfn, type);
 
-        dev->bus = bus;
         dev->sysdata = node;
         dev->dev.parent = bus->bridge;
         dev->dev.bus = &pci_bus_type;
@@ -327,7 +326,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
                 pci_set_master(dev);
 
-        dev->current_state = 4;         /* unknown power state */
+        dev->current_state = PCI_UNKNOWN;       /* unknown power state */
         dev->error_state = pci_channel_io_normal;
         dev->dma_mask = 0xffffffff;
 
@@ -773,15 +772,6 @@ static int __pci_mmap_make_offset(struct pci_dev *pdev,
         return 0;
 }
 
-/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
- * mapping.
- */
-static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
-                                            enum pci_mmap_state mmap_state)
-{
-        vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
-}
-
 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
  * device mapping.
  */
@@ -809,7 +799,6 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
         if (ret < 0)
                 return ret;
 
-        __pci_mmap_set_flags(dev, vma, mmap_state);
         __pci_mmap_set_pgprot(dev, vma, mmap_state);
 
         vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 9f20566b0773..79cc0d1a477d 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -54,6 +54,7 @@ EXPORT_SYMBOL(of_set_property_mutex);
 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
 {
         struct property **prevp;
+        unsigned long flags;
         void *new_val;
         int err;
 
@@ -64,7 +65,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
         err = -ENODEV;
 
         mutex_lock(&of_set_property_mutex);
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         prevp = &dp->properties;
         while (*prevp) {
                 struct property *prop = *prevp;
@@ -91,7 +92,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
                 }
                 prevp = &(*prevp)->next;
         }
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         mutex_unlock(&of_set_property_mutex);
 
         /* XXX Upate procfs if necessary... */
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 38bf80a22f02..1434526970a6 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -304,7 +304,7 @@ void __init setup_arch(char **cmdline_p)
 
         /* Initialize PROM console and command line. */
         *cmdline_p = prom_getbootargs();
-        strcpy(boot_command_line, *cmdline_p);
+        strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
         parse_early_param();
 
         boot_flags_init(*cmdline_p);
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 88a127b9c69e..13785547e435 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -555,7 +555,7 @@ void __init setup_arch(char **cmdline_p)
 {
         /* Initialize PROM console and command line. */
         *cmdline_p = prom_getbootargs();
-        strcpy(boot_command_line, *cmdline_p);
+        strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
         parse_early_param();
 
         boot_flags_init(*cmdline_p);
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index af472cf7c69a..db6987082805 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -288,10 +288,6 @@ static void map_high_region(unsigned long start_pfn, unsigned long end_pfn)
 
 void __init mem_init(void)
 {
-        int codepages = 0;
-        int datapages = 0;
-        int initpages = 0; 
-        int reservedpages = 0;
         int i;
 
         if (PKMAP_BASE+LAST_PKMAP*PAGE_SIZE >= FIXADDR_START) {
@@ -323,15 +319,12 @@ void __init mem_init(void)
 
         max_mapnr = last_valid_pfn - pfn_base;
         high_memory = __va(max_low_pfn << PAGE_SHIFT);
-
-        totalram_pages = free_all_bootmem();
+        free_all_bootmem();
 
         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
                 unsigned long start_pfn = sp_banks[i].base_addr >> PAGE_SHIFT;
                 unsigned long end_pfn = (sp_banks[i].base_addr + sp_banks[i].num_bytes) >> PAGE_SHIFT;
 
-                num_physpages += sp_banks[i].num_bytes >> PAGE_SHIFT;
-
                 if (end_pfn <= highstart_pfn)
                         continue;
 
@@ -341,39 +334,19 @@ void __init mem_init(void)
                 map_high_region(start_pfn, end_pfn);
         }
         
-        codepages = (((unsigned long) &_etext) - ((unsigned long)&_start));
-        codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
-        datapages = (((unsigned long) &_edata) - ((unsigned long)&_etext));
-        datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
-        initpages = (((unsigned long) &__init_end) - ((unsigned long) &__init_begin));
-        initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
-
-        /* Ignore memory holes for the purpose of counting reserved pages */
-        for (i=0; i < max_low_pfn; i++)
-                if (test_bit(i >> (20 - PAGE_SHIFT), sparc_valid_addr_bitmap)
-                    && PageReserved(pfn_to_page(i)))
-                        reservedpages++;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init, %ldk highmem)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               num_physpages << (PAGE_SHIFT - 10),
-               codepages << (PAGE_SHIFT-10),
-               reservedpages << (PAGE_SHIFT - 10),
-               datapages << (PAGE_SHIFT-10), 
-               initpages << (PAGE_SHIFT-10),
-               totalhigh_pages << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
 }
 
 void free_initmem (void)
 {
-        num_physpages += free_initmem_default(POISON_FREE_INITMEM);
+        free_initmem_default(POISON_FREE_INITMEM);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-                                            "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a7171997adfd..a9c42a7ffb6a 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1098,7 +1098,14 @@ static int __init grab_mblocks(struct mdesc_handle *md)
                 m->size = *val;
                 val = mdesc_get_property(md, node,
                                          "address-congruence-offset", NULL);
-                m->offset = *val;
+
+                /* The address-congruence-offset property is optional.
+                 * Explicity zero it be identifty this.
+                 */
+                if (val)
+                        m->offset = *val;
+                else
+                        m->offset = 0UL;
 
                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
                         count - 1, m->base, m->size, m->offset);
@@ -2038,7 +2045,6 @@ static void __init register_page_bootmem_info(void)
 }
 void __init mem_init(void)
 {
-        unsigned long codepages, datapages, initpages;
         unsigned long addr, last;
 
         addr = PAGE_OFFSET + kern_base;
@@ -2054,12 +2060,7 @@ void __init mem_init(void)
         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
 
         register_page_bootmem_info();
-        totalram_pages = free_all_bootmem();
-
-        /* We subtract one to account for the mem_map_zero page
-         * allocated below.
-         */
-        num_physpages = totalram_pages - 1;
+        free_all_bootmem();
 
         /*
          * Set up the zero page, mark it reserved, so that page count
@@ -2072,19 +2073,7 @@ void __init mem_init(void)
         }
         mark_page_reserved(mem_map_zero);
 
-        codepages = (((unsigned long) _etext) - ((unsigned long) _start));
-        codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
-        datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
-        datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
-        initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
-        initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
-
-        printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               codepages << (PAGE_SHIFT-10),
-               datapages << (PAGE_SHIFT-10), 
-               initpages << (PAGE_SHIFT-10), 
-               PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
+        mem_init_print_info(NULL);
 
         if (tlb_type == cheetah || tlb_type == cheetah_plus)
                 cheetah_ecache_flush_init();
@@ -2124,8 +2113,8 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
-                                            "initrd");
+        free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
+                           "initrd");
 }
 #endif
 
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index 83d89bcb44af..7a91f288c708 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -85,8 +85,8 @@ static void tlb_batch_add_one(struct mm_struct *mm, unsigned long vaddr,
         }
 
         if (!tb->active) {
-                global_flush_tlb_page(mm, vaddr);
                 flush_tsb_user_page(mm, vaddr);
+                global_flush_tlb_page(mm, vaddr);
                 goto out;
         }
 
@@ -188,7 +188,8 @@ void set_pmd_at(struct mm_struct *mm, unsigned long addr,
         }
 }
 
-void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable)
+void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
+                                pgtable_t pgtable)
 {
         struct list_head *lh = (struct list_head *) pgtable;
 
@@ -202,7 +203,7 @@ void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable)
         mm->pmd_huge_pte = pgtable;
 }
 
-pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm)
+pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 {
         struct list_head *lh;
         pgtable_t pgtable;
diff --git a/arch/sparc/prom/bootstr_32.c b/arch/sparc/prom/bootstr_32.c
index f5ec32e0d419..d2b49d2365e7 100644
--- a/arch/sparc/prom/bootstr_32.c
+++ b/arch/sparc/prom/bootstr_32.c
@@ -23,23 +23,25 @@ prom_getbootargs(void)
                 return barg_buf;
         }
 
-        switch(prom_vers) {
+        switch (prom_vers) {
         case PROM_V0:
                 cp = barg_buf;
                 /* Start from 1 and go over fd(0,0,0)kernel */
-                for(iter = 1; iter < 8; iter++) {
+                for (iter = 1; iter < 8; iter++) {
                         arg = (*(romvec->pv_v0bootargs))->argv[iter];
                         if (arg == NULL)
                                 break;
-                        while(*arg != 0) {
+                        while (*arg != 0) {
                                 /* Leave place for space and null. */
-                                if(cp >= barg_buf + BARG_LEN-2){
+                                if (cp >= barg_buf + BARG_LEN - 2)
                                         /* We might issue a warning here. */
                                         break;
-                                }
                                 *cp++ = *arg++;
                         }
                         *cp++ = ' ';
+                        if (cp >= barg_buf + BARG_LEN - 1)
+                                /* We might issue a warning here. */
+                                break;
                 }
                 *cp = 0;
                 break;
diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c
index 92204c3800b5..bd1b2a3ac34e 100644
--- a/arch/sparc/prom/tree_64.c
+++ b/arch/sparc/prom/tree_64.c
@@ -39,7 +39,7 @@ inline phandle __prom_getchild(phandle node)
         return prom_node_to_node("child", node);
 }
 
-inline phandle prom_getchild(phandle node)
+phandle prom_getchild(phandle node)
 {
         phandle cnode;
 
@@ -72,7 +72,7 @@ inline phandle __prom_getsibling(phandle node)
         return prom_node_to_node(prom_peer_name, node);
 }
 
-inline phandle prom_getsibling(phandle node)
+phandle prom_getsibling(phandle node)
 {
         phandle sibnode;
 
@@ -89,7 +89,7 @@ EXPORT_SYMBOL(prom_getsibling);
 /* Return the length in bytes of property 'prop' at node 'node'.
  * Return -1 on error.
  */
-inline int prom_getproplen(phandle node, const char *prop)
+int prom_getproplen(phandle node, const char *prop)
 {
         unsigned long args[6];
 
@@ -113,8 +113,8 @@ EXPORT_SYMBOL(prom_getproplen);
  * 'buffer' which has a size of 'bufsize'.  If the acquisition
  * was successful the length will be returned, else -1 is returned.
  */
-inline int prom_getproperty(phandle node, const char *prop,
-                            char *buffer, int bufsize)
+int prom_getproperty(phandle node, const char *prop,
+                     char *buffer, int bufsize)
 {
         unsigned long args[8];
         int plen;
@@ -141,7 +141,7 @@ EXPORT_SYMBOL(prom_getproperty);
 /* Acquire an integer property and return its value.  Returns -1
  * on failure.
  */
-inline int prom_getint(phandle node, const char *prop)
+int prom_getint(phandle node, const char *prop)
 {
         int intprop;
 
@@ -235,7 +235,7 @@ static const char *prom_nextprop_name = "nextprop";
 /* Return the first property type for node 'node'.
  * buffer should be at least 32B in length
  */
-inline char *prom_firstprop(phandle node, char *buffer)
+char *prom_firstprop(phandle node, char *buffer)
 {
         unsigned long args[7];
 
@@ -261,7 +261,7 @@ EXPORT_SYMBOL(prom_firstprop);
  * at node 'node' .  Returns NULL string if no more
  * property types for this node.
  */
-inline char *prom_nextprop(phandle node, const char *oprop, char *buffer)
+char *prom_nextprop(phandle node, const char *oprop, char *buffer)
 {
         unsigned long args[7];
         char buf[32];
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 3aa37669ff8c..24565a7ffe6d 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -25,6 +25,7 @@ config TILE
         select HAVE_ARCH_TRACEHOOK
         select HAVE_SYSCALL_TRACEPOINTS
         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
+        select HAVE_DEBUG_STACKOVERFLOW
 
 # FIXME: investigate whether we need/want these options.
 #       select HAVE_IOREMAP_PROT
diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug
index ddbfc3322d7f..9165ea979e85 100644
--- a/arch/tile/Kconfig.debug
+++ b/arch/tile/Kconfig.debug
@@ -14,13 +14,6 @@ config EARLY_PRINTK
           with klogd/syslogd. You should normally N here,
           unless you want to debug such a crash.
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        help
-          This option will cause messages to be printed if free stack space
-          drops below a certain limit.
-
 config DEBUG_EXTRA_FLAGS
         string "Additional compiler arguments when building with '-g'"
         depends on DEBUG_INFO
diff --git a/arch/tile/include/asm/pgtable.h b/arch/tile/include/asm/pgtable.h
index 73b1a4c9ad03..33587f16c152 100644
--- a/arch/tile/include/asm/pgtable.h
+++ b/arch/tile/include/asm/pgtable.h
@@ -362,9 +362,6 @@ do {						\
 #define kern_addr_valid(addr)   (1)
 #endif /* CONFIG_FLATMEM */
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 extern void vmalloc_sync_all(void);
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index 2b70dfb1442e..b3f104953da2 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -225,7 +225,7 @@ extern int do_work_pending(struct pt_regs *regs, u32 flags);
 
 /*
  * Return saved (kernel) PC of a blocked thread.
- * Only used in a printk() in kernel/sched.c, so don't work too hard.
+ * Only used in a printk() in kernel/sched/core.c, so don't work too hard.
  */
 #define thread_saved_pc(t)   ((t)->thread.pc)
 
diff --git a/arch/tile/include/asm/sections.h b/arch/tile/include/asm/sections.h
index d062d463fca9..7d8a935a9238 100644
--- a/arch/tile/include/asm/sections.h
+++ b/arch/tile/include/asm/sections.h
@@ -34,7 +34,7 @@ extern char __sys_cmpxchg_grab_lock[];
 extern char __start_atomic_asm_code[], __end_atomic_asm_code[];
 #endif
 
-/* Handle the discontiguity between _sdata and _stext. */
+/* Handle the discontiguity between _sdata and _text. */
 static inline int arch_is_kernel_data(unsigned long addr)
 {
         return addr >= (unsigned long)_sdata &&
diff --git a/arch/tile/include/asm/uaccess.h b/arch/tile/include/asm/uaccess.h
index 8a082bc6bca5..e4d44bd7df27 100644
--- a/arch/tile/include/asm/uaccess.h
+++ b/arch/tile/include/asm/uaccess.h
@@ -442,7 +442,7 @@ extern unsigned long __copy_in_user_inatomic(
 static inline unsigned long __must_check
 __copy_in_user(void __user *to, const void __user *from, unsigned long n)
 {
-        might_sleep();
+        might_fault();
         return __copy_in_user_inatomic(to, from, n);
 }
 
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 7a5aa1a7864e..68b542677f6a 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -307,8 +307,8 @@ static void __cpuinit store_permanent_mappings(void)
                 hv_store_mapping(addr, pages << PAGE_SHIFT, pa);
         }
 
-        hv_store_mapping((HV_VirtAddr)_stext,
-                         (uint32_t)(_einittext - _stext), 0);
+        hv_store_mapping((HV_VirtAddr)_text,
+                         (uint32_t)(_einittext - _text), 0);
 }
 
 /*
@@ -329,6 +329,7 @@ static void __init setup_memory(void)
 #if defined(CONFIG_HIGHMEM) || defined(__tilegx__)
         long lowmem_pages;
 #endif
+        unsigned long physpages = 0;
 
         /* We are using a char to hold the cpu_2_node[] mapping */
         BUILD_BUG_ON(MAX_NUMNODES > 127);
@@ -388,8 +389,8 @@ static void __init setup_memory(void)
                                 continue;
                         }
                 }
-                if (num_physpages + PFN_DOWN(range.size) > maxmem_pfn) {
-                        int max_size = maxmem_pfn - num_physpages;
+                if (physpages + PFN_DOWN(range.size) > maxmem_pfn) {
+                        int max_size = maxmem_pfn - physpages;
                         if (max_size > 0) {
                                 pr_err("Maxmem reduced node %d to %d pages\n",
                                        i, max_size);
@@ -446,7 +447,7 @@ static void __init setup_memory(void)
                 node_start_pfn[i] = start;
                 node_end_pfn[i] = end;
                 node_controller[i] = range.controller;
-                num_physpages += size;
+                physpages += size;
                 max_pfn = end;
 
                 /* Mark node as online */
@@ -465,7 +466,7 @@ static void __init setup_memory(void)
          * we're willing to use at 8 million pages (32GB of 4KB pages).
          */
         cap = 8 * 1024 * 1024;  /* 8 million pages */
-        if (num_physpages > cap) {
+        if (physpages > cap) {
                 int num_nodes = num_online_nodes();
                 int cap_each = cap / num_nodes;
                 unsigned long dropped_pages = 0;
@@ -476,10 +477,10 @@ static void __init setup_memory(void)
                                 node_end_pfn[i] = node_start_pfn[i] + cap_each;
                         }
                 }
-                num_physpages -= dropped_pages;
+                physpages -= dropped_pages;
                 pr_warning("Only using %ldMB memory;"
                        " ignoring %ldMB.\n",
-                       num_physpages >> (20 - PAGE_SHIFT),
+                       physpages >> (20 - PAGE_SHIFT),
                        dropped_pages >> (20 - PAGE_SHIFT));
                 pr_warning("Consider using a larger page size.\n");
         }
@@ -497,7 +498,7 @@ static void __init setup_memory(void)
 
         lowmem_pages = (mappable_physpages > MAXMEM_PFN) ?
                 MAXMEM_PFN : mappable_physpages;
-        highmem_pages = (long) (num_physpages - lowmem_pages);
+        highmem_pages = (long) (physpages - lowmem_pages);
 
         pr_notice("%ldMB HIGHMEM available.\n",
                pages_to_mb(highmem_pages > 0 ? highmem_pages : 0));
@@ -514,7 +515,6 @@ static void __init setup_memory(void)
                 pr_warning("Use a HIGHMEM enabled kernel.\n");
                 max_low_pfn = MAXMEM_PFN;
                 max_pfn = MAXMEM_PFN;
-                num_physpages = MAXMEM_PFN;
                 node_end_pfn[0] = MAXMEM_PFN;
         } else {
                 pr_notice("%ldMB memory available.\n",
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index ed258b8ae320..af8dfc9665f6 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -442,7 +442,7 @@ void _KBacktraceIterator_init_current(struct KBacktraceIterator *kbt, ulong pc,
                                 regs_to_pt_regs(&regs, pc, lr, sp, r52));
 }
 
-/* This is called only from kernel/sched.c, with esp == NULL */
+/* This is called only from kernel/sched/core.c, with esp == NULL */
 void show_stack(struct task_struct *task, unsigned long *esp)
 {
         struct KBacktraceIterator kbt;
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
index 631f10de12fe..a13ed902afbb 100644
--- a/arch/tile/kernel/vmlinux.lds.S
+++ b/arch/tile/kernel/vmlinux.lds.S
@@ -27,7 +27,6 @@ SECTIONS
   .intrpt1 (LOAD_OFFSET) : AT ( 0 )   /* put at the start of physical memory */
   {
     _text = .;
-    _stext = .;
     *(.intrpt1)
   } :intrpt1 =0
 
@@ -36,6 +35,7 @@ SECTIONS
 
   /* Now the real code */
   . = ALIGN(0x20000);
+  _stext = .;
   .text : AT (ADDR(.text) - LOAD_OFFSET) {
     HEAD_TEXT
     SCHED_TEXT
@@ -58,11 +58,13 @@ SECTIONS
   #define LOAD_OFFSET PAGE_OFFSET
 
   . = ALIGN(PAGE_SIZE);
+  __init_begin = .;
   VMLINUX_SYMBOL(_sinitdata) = .;
   INIT_DATA_SECTION(16) :data =0
   PERCPU_SECTION(L2_CACHE_BYTES)
   . = ALIGN(PAGE_SIZE);
   VMLINUX_SYMBOL(_einitdata) = .;
+  __init_end = .;
 
   _sdata = .;                   /* Start of data section */
 
diff --git a/arch/tile/lib/exports.c b/arch/tile/lib/exports.c
index 4385cb6fa00a..a93b02a25222 100644
--- a/arch/tile/lib/exports.c
+++ b/arch/tile/lib/exports.c
@@ -84,4 +84,6 @@ uint64_t __ashrdi3(uint64_t, unsigned int);
 EXPORT_SYMBOL(__ashrdi3);
 uint64_t __ashldi3(uint64_t, unsigned int);
 EXPORT_SYMBOL(__ashldi3);
+int __ffsdi2(uint64_t);
+EXPORT_SYMBOL(__ffsdi2);
 #endif
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index 2749515a0547..e182958c707d 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -562,7 +562,7 @@ static void __init kernel_physical_mapping_init(pgd_t *pgd_base)
                         prot = ktext_set_nocache(prot);
                 }
 
-                BUG_ON(address != (unsigned long)_stext);
+                BUG_ON(address != (unsigned long)_text);
                 pte = NULL;
                 for (; address < (unsigned long)_einittext;
                      pfn++, address += PAGE_SIZE) {
@@ -720,7 +720,7 @@ static void __init init_free_pfn_range(unsigned long start, unsigned long end)
                 }
                 init_page_count(page);
                 __free_pages(page, order);
-                totalram_pages += count;
+                adjust_managed_page_count(page, count);
 
                 page += count;
                 pfn += count;
@@ -821,7 +821,6 @@ static void __init set_max_mapnr_init(void)
 
 void __init mem_init(void)
 {
-        int codesize, datasize, initsize;
         int i;
 #ifndef __tilegx__
         void *last;
@@ -846,26 +845,14 @@ void __init mem_init(void)
         set_max_mapnr_init();
 
         /* this will put all bootmem onto the freelists */
-        totalram_pages += free_all_bootmem();
+        free_all_bootmem();
 
 #ifndef CONFIG_64BIT
         /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
         set_non_bootmem_pages_init();
 #endif
 
-        codesize =  (unsigned long)&_etext - (unsigned long)&_text;
-        datasize =  (unsigned long)&_end - (unsigned long)&_sdata;
-        initsize =  (unsigned long)&_einittext - (unsigned long)&_sinittext;
-        initsize += (unsigned long)&_einitdata - (unsigned long)&_sinitdata;
-
-        pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
-                (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                datasize >> 10,
-                initsize >> 10,
-                (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))
-               );
+        mem_init_print_info(NULL);
 
         /*
          * In debug mode, dump some interesting memory mappings.
@@ -1024,16 +1011,13 @@ static void free_init_pages(char *what, unsigned long begin, unsigned long end)
                         pte_clear(&init_mm, addr, ptep);
                         continue;
                 }
-                __ClearPageReserved(page);
-                init_page_count(page);
                 if (pte_huge(*ptep))
                         BUG_ON(!kdata_huge);
                 else
                         set_pte_at(&init_mm, addr, ptep,
                                    pfn_pte(pfn, PAGE_KERNEL));
                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                free_page(addr);
-                totalram_pages++;
+                free_reserved_page(page);
         }
         pr_info("Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
 }
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index d7d21851e60c..3df3bd544492 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -147,7 +147,7 @@ void mconsole_proc(struct mc_request *req)
         }
 
         do {
-                loff_t pos;
+                loff_t pos = file->f_pos;
                 mm_segment_t old_fs = get_fs();
                 set_fs(KERNEL_DS);
                 len = vfs_read(file, buf, PAGE_SIZE - 1, &pos);
diff --git a/arch/um/include/asm/common.lds.S b/arch/um/include/asm/common.lds.S
index 4938de5512d2..1dd5bd8a8c59 100644
--- a/arch/um/include/asm/common.lds.S
+++ b/arch/um/include/asm/common.lds.S
@@ -57,7 +57,6 @@
         *(.uml.initcall.init)
         __uml_initcall_end = .;
   }
-  __init_end = .;
 
   SECURITY_INIT
 
diff --git a/arch/um/include/asm/pgtable.h b/arch/um/include/asm/pgtable.h
index ae02909a1875..bf974f712af7 100644
--- a/arch/um/include/asm/pgtable.h
+++ b/arch/um/include/asm/pgtable.h
@@ -69,8 +69,6 @@ extern unsigned long end_iomem;
 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
 #define PAGE_KERNEL_EXEC        __pgprot(__PAGE_KERNEL_EXEC)
 
-#define io_remap_pfn_range      remap_pfn_range
-
 /*
  * The i386 can't do page protection for execute, and considers that the same
  * are read.
diff --git a/arch/um/kernel/dyn.lds.S b/arch/um/kernel/dyn.lds.S
index fb8fd6fb6563..adde088aeeff 100644
--- a/arch/um/kernel/dyn.lds.S
+++ b/arch/um/kernel/dyn.lds.S
@@ -14,8 +14,6 @@ SECTIONS
   __binary_start = .;
   . = ALIGN(4096);              /* Init code and data */
   _text = .;
-  _stext = .;
-  __init_begin = .;
   INIT_TEXT_SECTION(PAGE_SIZE)
 
   . = ALIGN(PAGE_SIZE);
@@ -67,6 +65,7 @@ SECTIONS
   } =0x90909090
   .plt            : { *(.plt) }
   .text           : {
+    _stext = .;
     TEXT_TEXT
     SCHED_TEXT
     LOCK_TEXT
@@ -91,7 +90,9 @@ SECTIONS
 
   #include <asm/common.lds.S>
 
+  __init_begin = .;
   init.data : { INIT_DATA }
+  __init_end = .;
 
   /* Ensure the __preinit_array_start label is properly aligned.  We
      could instead move the label definition inside the section, but
@@ -155,6 +156,7 @@ SECTIONS
    . = ALIGN(32 / 8);
   . = ALIGN(32 / 8);
   }
+   __bss_stop = .;
   _end = .;
   PROVIDE (end = .);
 
diff --git a/arch/um/kernel/mem.c b/arch/um/kernel/mem.c
index 9df292b270a8..7ddb64baf327 100644
--- a/arch/um/kernel/mem.c
+++ b/arch/um/kernel/mem.c
@@ -65,15 +65,13 @@ void __init mem_init(void)
         uml_reserved = brk_end;
 
         /* this will put all low memory onto the freelists */
-        totalram_pages = free_all_bootmem();
+        free_all_bootmem();
         max_low_pfn = totalram_pages;
 #ifdef CONFIG_HIGHMEM
         setup_highmem(end_iomem, highmem);
 #endif
-        num_physpages = totalram_pages;
         max_pfn = totalram_pages;
-        printk(KERN_INFO "Memory: %luk available\n",
-               nr_free_pages() << (PAGE_SHIFT-10));
+        mem_init_print_info(NULL);
         kmalloc_ok = 1;
 }
 
@@ -244,7 +242,7 @@ void free_initmem(void)
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        free_reserved_area(start, end, 0, "initrd");
+        free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
diff --git a/arch/um/kernel/sysrq.c b/arch/um/kernel/sysrq.c
index 7d101a2a1541..0dc4d1c6f98a 100644
--- a/arch/um/kernel/sysrq.c
+++ b/arch/um/kernel/sysrq.c
@@ -39,7 +39,7 @@ void show_trace(struct task_struct *task, unsigned long * stack)
 static const int kstack_depth_to_print = 24;
 
 /* This recently started being used in arch-independent code too, as in
- * kernel/sched.c.*/
+ * kernel/sched/core.c.*/
 void show_stack(struct task_struct *task, unsigned long *esp)
 {
         unsigned long *stack;
diff --git a/arch/um/kernel/uml.lds.S b/arch/um/kernel/uml.lds.S
index ff65fb4f1a95..6899195602b7 100644
--- a/arch/um/kernel/uml.lds.S
+++ b/arch/um/kernel/uml.lds.S
@@ -20,13 +20,12 @@ SECTIONS
   . = START + SIZEOF_HEADERS;
 
   _text = .;
-  _stext = .;
-  __init_begin = .;
   INIT_TEXT_SECTION(0)
   . = ALIGN(PAGE_SIZE);
 
   .text      :
   {
+    _stext = .;
     TEXT_TEXT
     SCHED_TEXT
     LOCK_TEXT
@@ -62,7 +61,10 @@ SECTIONS
 
   #include <asm/common.lds.S>
 
+  __init_begin = .;
   init.data : { INIT_DATA }
+  __init_end = .;
+
   .data    :
   {
     INIT_TASK_DATA(KERNEL_STACK_SIZE)
@@ -97,6 +99,7 @@ SECTIONS
   PROVIDE(_bss_start = .);
   SBSS(0)
   BSS(0)
+   __bss_stop = .;
   _end = .;
   PROVIDE (end = .);
 
diff --git a/arch/unicore32/boot/compressed/Makefile b/arch/unicore32/boot/compressed/Makefile
index 950a9afa38f8..96494fb646f7 100644
--- a/arch/unicore32/boot/compressed/Makefile
+++ b/arch/unicore32/boot/compressed/Makefile
@@ -17,7 +17,7 @@ OBJS		:= misc.o
 
 # font.c and font.o
 CFLAGS_font.o   := -Dstatic=
-$(obj)/font.c: $(srctree)/drivers/video/console/font_8x8.c
+$(obj)/font.c: $(srctree)/lib/fonts/font_8x8.c
         $(call cmd,shipped)
 
 # piggy.S and piggy.o
diff --git a/arch/unicore32/include/asm/memory.h b/arch/unicore32/include/asm/memory.h
index 5eddb997defe..debafc40200a 100644
--- a/arch/unicore32/include/asm/memory.h
+++ b/arch/unicore32/include/asm/memory.h
@@ -98,12 +98,6 @@
 /*
  * Conversion between a struct page and a physical address.
  *
- * Note: when converting an unknown physical address to a
- * struct page, the resulting pointer must be validated
- * using VALID_PAGE().  It must return an invalid struct page
- * for any physical address not corresponding to a system
- * RAM address.
- *
  *  page_to_pfn(page)   convert a struct page * to a PFN number
  *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
  *
diff --git a/arch/unicore32/include/asm/pgtable.h b/arch/unicore32/include/asm/pgtable.h
index 68b2f297ac97..233c25880df4 100644
--- a/arch/unicore32/include/asm/pgtable.h
+++ b/arch/unicore32/include/asm/pgtable.h
@@ -303,13 +303,6 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
 #include <asm-generic/pgtable.h>
 
-/*
- * remap a physical page `pfn' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-#define io_remap_pfn_range(vma, from, pfn, size, prot)  \
-                remap_pfn_range(vma, from, pfn, size, prot)
-
 #define pgtable_cache_init() do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c
index ef69c0c82825..374a055a8e6b 100644
--- a/arch/unicore32/kernel/pci.c
+++ b/arch/unicore32/kernel/pci.c
@@ -277,11 +277,6 @@ static int __init pci_common_init(void)
                 pci_bus_assign_resources(puv3_bus);
         }
 
-        /*
-         * Tell drivers about devices found.
-         */
-        pci_bus_add_devices(puv3_bus);
-
         return 0;
 }
 subsys_initcall(pci_common_init);
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 63df12d71ce3..ae6bc036db92 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -383,59 +383,14 @@ static void __init free_unused_memmap(struct meminfo *mi)
  */
 void __init mem_init(void)
 {
-        unsigned long reserved_pages, free_pages;
-        struct memblock_region *reg;
-        int i;
-
         max_mapnr   = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map;
 
         free_unused_memmap(&meminfo);
 
         /* this will put all unused low memory onto the freelists */
-        totalram_pages += free_all_bootmem();
-
-        reserved_pages = free_pages = 0;
-
-        for_each_bank(i, &meminfo) {
-                struct membank *bank = &meminfo.bank[i];
-                unsigned int pfn1, pfn2;
-                struct page *page, *end;
-
-                pfn1 = bank_pfn_start(bank);
-                pfn2 = bank_pfn_end(bank);
-
-                page = pfn_to_page(pfn1);
-                end  = pfn_to_page(pfn2 - 1) + 1;
-
-                do {
-                        if (PageReserved(page))
-                                reserved_pages++;
-                        else if (!page_count(page))
-                                free_pages++;
-                        page++;
-                } while (page < end);
-        }
-
-        /*
-         * Since our memory may not be contiguous, calculate the
-         * real number of pages we have in this system
-         */
-        printk(KERN_INFO "Memory:");
-        num_physpages = 0;
-        for_each_memblock(memory, reg) {
-                unsigned long pages = memblock_region_memory_end_pfn(reg) -
-                        memblock_region_memory_base_pfn(reg);
-                num_physpages += pages;
-                printk(" %ldMB", pages >> (20 - PAGE_SHIFT));
-        }
-        printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
-
-        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                free_pages << (PAGE_SHIFT-10),
-                reserved_pages << (PAGE_SHIFT-10),
-                totalhigh_pages << (PAGE_SHIFT-10));
+        free_all_bootmem();
 
+        mem_init_print_info(NULL);
         printk(KERN_NOTICE "Virtual kernel memory layout:\n"
                 "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
                 "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
@@ -464,7 +419,7 @@ void __init mem_init(void)
         BUILD_BUG_ON(TASK_SIZE                          > MODULES_VADDR);
         BUG_ON(TASK_SIZE                                > MODULES_VADDR);
 
-        if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
+        if (PAGE_SIZE >= 16384 && get_num_physpages() <= 128) {
                 /*
                  * On a machine this small we won't get
                  * anywhere without overcommit, so turn
@@ -476,7 +431,7 @@ void __init mem_init(void)
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -486,7 +441,7 @@ static int keep_initrd;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (!keep_initrd)
-                free_reserved_area(start, end, 0, "initrd");
+                free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 
 static int __init keepinitrd_setup(char *__unused)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 685692c94f05..265c672a2f40 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -102,6 +102,7 @@ config X86
         select HAVE_ARCH_SECCOMP_FILTER
         select BUILDTIME_EXTABLE_SORT
         select GENERIC_CMOS_UPDATE
+        select HAVE_ARCH_SOFT_DIRTY
         select CLOCKSOURCE_WATCHDOG
         select GENERIC_CLOCKEVENTS
         select ARCH_CLOCKSOURCE_DATA if X86_64
@@ -121,6 +122,7 @@ config X86
         select OLD_SIGACTION if X86_32
         select COMPAT_OLD_SIGACTION if IA32_EMULATION
         select RTC_LIB
+        select HAVE_DEBUG_STACKOVERFLOW
 
 config INSTRUCTION_DECODER
         def_bool y
@@ -207,6 +209,12 @@ config ARCH_HIBERNATION_POSSIBLE
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
 
+config ARCH_WANT_HUGE_PMD_SHARE
+        def_bool y
+
+config ARCH_WANT_GENERAL_HUGETLB
+        def_bool y
+
 config ZONE_DMA32
         bool
         default X86_64
@@ -336,6 +344,7 @@ config X86_EXTENDED_PLATFORM
 
           If you enable this option then you'll be able to select support
           for the following (non-PC) 32 bit x86 platforms:
+                Goldfish (Android emulator)
                 AMD Elan
                 NUMAQ (IBM/Sequent)
                 RDC R-321x SoC
@@ -410,6 +419,7 @@ config X86_UV
 config X86_GOLDFISH
        bool "Goldfish (Virtual Platform)"
        depends on X86_32
+       depends on X86_EXTENDED_PLATFORM
        ---help---
          Enable support for the Goldfish virtual platform used primarily
          for Android development. Unless you are building for the Android
@@ -1058,8 +1068,16 @@ config MICROCODE_INTEL_LIB
         depends on MICROCODE_INTEL
 
 config MICROCODE_INTEL_EARLY
+        def_bool n
+
+config MICROCODE_AMD_EARLY
+        def_bool n
+
+config MICROCODE_EARLY
         bool "Early load microcode"
-        depends on MICROCODE_INTEL && BLK_DEV_INITRD
+        depends on MICROCODE=y && BLK_DEV_INITRD
+        select MICROCODE_INTEL_EARLY if MICROCODE_INTEL
+        select MICROCODE_AMD_EARLY if MICROCODE_AMD
         default y
         help
           This option provides functionality to read additional microcode data
@@ -1067,10 +1085,6 @@ config MICROCODE_INTEL_EARLY
           microcode to CPU's as early as possible. No functional change if no
           microcode data is glued to the initrd, therefore it's safe to say Y.
 
-config MICROCODE_EARLY
-        def_bool y
-        depends on MICROCODE_INTEL_EARLY
-
 config X86_MSR
         tristate "/dev/cpu/*/msr - Model-specific register support"
         ---help---
@@ -1725,7 +1739,7 @@ config PHYSICAL_ALIGN
 
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs"
-        depends on SMP && HOTPLUG
+        depends on SMP
         ---help---
           Say Y here to allow turning CPUs off and on. CPUs can be
           controlled through /sys/devices/system/cpu.
@@ -2246,11 +2260,11 @@ source "drivers/pcmcia/Kconfig"
 source "drivers/pci/hotplug/Kconfig"
 
 config RAPIDIO
-        bool "RapidIO support"
+        tristate "RapidIO support"
         depends on PCI
         default n
         help
-          If you say Y here, the kernel will include drivers and
+          If enabled this option will include drivers and the core
           infrastructure code to support RapidIO interconnect devices.
 
 source "drivers/rapidio/Kconfig"
@@ -2265,6 +2279,7 @@ source "fs/Kconfig.binfmt"
 config IA32_EMULATION
         bool "IA32 Emulation"
         depends on X86_64
+        select BINFMT_ELF
         select COMPAT_BINFMT_ELF
         select HAVE_UID16
         ---help---
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index c198b7e13e7b..78d91afb8e50 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -59,16 +59,6 @@ config EARLY_PRINTK_DBGP
           with klogd/syslogd or the X server. You should normally N here,
           unless you want to debug such a crash. You need usb debug device.
 
-config DEBUG_STACKOVERFLOW
-        bool "Check for stack overflows"
-        depends on DEBUG_KERNEL
-        ---help---
-          Say Y here if you want to check the overflows of kernel, IRQ
-          and exception stacks. This option will cause messages of the
-          stacks in detail when free stack space drops below a certain
-          limit.
-          If in doubt, say "N".
-
 config X86_PTDUMP
         bool "Export kernel pagetable layout to userspace via debugfs"
         depends on DEBUG_KERNEL
@@ -122,7 +112,6 @@ config DEBUG_NX_TEST
 config DOUBLEFAULT
         default y
         bool "Enable doublefault exception handler" if EXPERT
-        depends on X86_32
         ---help---
           This option allows trapping of rare doublefault exceptions that
           would otherwise cause a system to silently reboot. Disabling this
@@ -304,4 +293,14 @@ config DEBUG_NMI_SELFTEST
 
           If unsure, say N.
 
+config X86_DEBUG_STATIC_CPU_HAS
+        bool "Debug alternatives"
+        depends on DEBUG_KERNEL
+        ---help---
+          This option causes additional code to be generated which
+          fails if static_cpu_has() is used before alternatives have
+          run.
+
+          If unsure, say N.
+
 endmenu
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 5c477260294f..07639c656fcd 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -220,6 +220,12 @@ archclean:
         $(Q)$(MAKE) $(clean)=$(boot)
         $(Q)$(MAKE) $(clean)=arch/x86/tools
 
+PHONY += kvmconfig
+kvmconfig:
+        $(if $(wildcard $(objtree)/.config),, $(error You need an existing .config for this target))
+        $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh -m -O $(objtree) $(objtree)/.config arch/x86/configs/kvm_guest.config
+        $(Q)yes "" | $(MAKE) oldconfig
+
 define archhelp
   echo  '* bzImage      - Compressed kernel image (arch/x86/boot/bzImage)'
   echo  '  install      - Install kernel using'
@@ -233,4 +239,5 @@ define archhelp
   echo  '                  bzdisk/fdimage*/isoimage also accept:'
   echo  '                  FDARGS="..."  arguments for the booted kernel'
   echo  '                  FDINITRD=file initrd for the booted kernel'
+  echo  '  kvmconfig    - Enable additional options for guest kernel support'
 endef
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 35ee62fccf98..d606463aa6d6 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -251,51 +251,6 @@ static void find_bits(unsigned long mask, u8 *pos, u8 *size)
         *size = len;
 }
 
-static efi_status_t setup_efi_vars(struct boot_params *params)
-{
-        struct setup_data *data;
-        struct efi_var_bootdata *efidata;
-        u64 store_size, remaining_size, var_size;
-        efi_status_t status;
-
-        if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION)
-                return EFI_UNSUPPORTED;
-
-        data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
-
-        while (data && data->next)
-                data = (struct setup_data *)(unsigned long)data->next;
-
-        status = efi_call_phys4((void *)sys_table->runtime->query_variable_info,
-                                EFI_VARIABLE_NON_VOLATILE |
-                                EFI_VARIABLE_BOOTSERVICE_ACCESS |
-                                EFI_VARIABLE_RUNTIME_ACCESS, &store_size,
-                                &remaining_size, &var_size);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        status = efi_call_phys3(sys_table->boottime->allocate_pool,
-                                EFI_LOADER_DATA, sizeof(*efidata), &efidata);
-
-        if (status != EFI_SUCCESS)
-                return status;
-
-        efidata->data.type = SETUP_EFI_VARS;
-        efidata->data.len = sizeof(struct efi_var_bootdata) -
-                sizeof(struct setup_data);
-        efidata->data.next = 0;
-        efidata->store_size = store_size;
-        efidata->remaining_size = remaining_size;
-        efidata->max_var_size = var_size;
-
-        if (data)
-                data->next = (unsigned long)efidata;
-        else
-                params->hdr.setup_data = (unsigned long)efidata;
-
-}
-
 static efi_status_t setup_efi_pci(struct boot_params *params)
 {
         efi_pci_io_protocol *pci;
@@ -1037,18 +992,20 @@ static efi_status_t exit_boot(struct boot_params *boot_params,
         efi_memory_desc_t *mem_map;
         efi_status_t status;
         __u32 desc_version;
+        bool called_exit = false;
         u8 nr_entries;
         int i;
 
         size = sizeof(*mem_map) * 32;
 
 again:
-        size += sizeof(*mem_map);
+        size += sizeof(*mem_map) * 2;
         _size = size;
         status = low_alloc(size, 1, (unsigned long *)&mem_map);
         if (status != EFI_SUCCESS)
                 return status;
 
+get_map:
         status = efi_call_phys5(sys_table->boottime->get_memory_map, &size,
                                 mem_map, &key, &desc_size, &desc_version);
         if (status == EFI_BUFFER_TOO_SMALL) {
@@ -1074,8 +1031,20 @@ again:
         /* Might as well exit boot services now */
         status = efi_call_phys2(sys_table->boottime->exit_boot_services,
                                 handle, key);
-        if (status != EFI_SUCCESS)
-                goto free_mem_map;
+        if (status != EFI_SUCCESS) {
+                /*
+                 * ExitBootServices() will fail if any of the event
+                 * handlers change the memory map. In which case, we
+                 * must be prepared to retry, but only once so that
+                 * we're guaranteed to exit on repeated failures instead
+                 * of spinning forever.
+                 */
+                if (called_exit)
+                        goto free_mem_map;
+
+                called_exit = true;
+                goto get_map;
+        }
 
         /* Historic? */
         boot_params->alt_mem_k = 32 * 1024;
@@ -1202,8 +1171,6 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table,
 
         setup_graphics(boot_params);
 
-        setup_efi_vars(boot_params);
-
         setup_efi_pci(boot_params);
 
         status = efi_call_phys3(sys_table->boottime->allocate_pool,
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 16f24e6dad79..06e71c2c16bf 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -27,8 +27,6 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/segment.h>
-#include <asm/pgtable_types.h>
-#include <asm/page_types.h>
 #include <asm/boot.h>
 #include <asm/msr.h>
 #include <asm/processor-flags.h>
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index 94c544650020..c941d6a8887f 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -243,6 +243,7 @@ static void parse_zoffset(char *fname)
         c = fread(buf, 1, sizeof(buf) - 1, file);
         if (ferror(file))
                 die("read-error on `zoffset.h'");
+        fclose(file);
         buf[c] = 0;
 
         p = (char *)buf;
diff --git a/arch/x86/configs/kvm_guest.config b/arch/x86/configs/kvm_guest.config
new file mode 100644
index 000000000000..f9affcc3b9f1
--- /dev/null
+++ b/arch/x86/configs/kvm_guest.config
@@ -0,0 +1,28 @@
+CONFIG_NET=y
+CONFIG_NET_CORE=y
+CONFIG_NETDEVICES=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV=y
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_INET=y
+CONFIG_TTY=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_BINFMT_ELF=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_PARAVIRT=y
+CONFIG_KVM_GUEST=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_NET=y
+CONFIG_9P_FS=y
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index a3a0ed80f17c..7d6ba9db1be9 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -3,8 +3,6 @@
 #
 
 avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no)
-avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\
-                                        $(comma)4)$(comma)%ymm2,yes,no)
 
 obj-$(CONFIG_CRYPTO_ABLK_HELPER_X86) += ablk_helper.o
 obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o
@@ -29,6 +27,7 @@ obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
 obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o
 obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o
 obj-$(CONFIG_CRYPTO_SHA512_SSSE3) += sha512-ssse3.o
+obj-$(CONFIG_CRYPTO_CRCT10DIF_PCLMUL) += crct10dif-pclmul.o
 
 # These modules require assembler to support AVX.
 ifeq ($(avx_supported),yes)
@@ -42,10 +41,8 @@ endif
 
 # These modules require assembler to support AVX2.
 ifeq ($(avx2_supported),yes)
-        obj-$(CONFIG_CRYPTO_BLOWFISH_AVX2_X86_64) += blowfish-avx2.o
         obj-$(CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64) += camellia-aesni-avx2.o
         obj-$(CONFIG_CRYPTO_SERPENT_AVX2_X86_64) += serpent-avx2.o
-        obj-$(CONFIG_CRYPTO_TWOFISH_AVX2_X86_64) += twofish-avx2.o
 endif
 
 aes-i586-y := aes-i586-asm_32.o aes_glue.o
@@ -73,10 +70,8 @@ ifeq ($(avx_supported),yes)
 endif
 
 ifeq ($(avx2_supported),yes)
-        blowfish-avx2-y := blowfish-avx2-asm_64.o blowfish_avx2_glue.o
         camellia-aesni-avx2-y := camellia-aesni-avx2-asm_64.o camellia_aesni_avx2_glue.o
         serpent-avx2-y := serpent-avx2-asm_64.o serpent_avx2_glue.o
-        twofish-avx2-y := twofish-avx2-asm_64.o twofish_avx2_glue.o
 endif
 
 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
@@ -87,3 +82,4 @@ crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
 crc32-pclmul-y := crc32-pclmul_asm.o crc32-pclmul_glue.o
 sha256-ssse3-y := sha256-ssse3-asm.o sha256-avx-asm.o sha256-avx2-asm.o sha256_ssse3_glue.o
 sha512-ssse3-y := sha512-ssse3-asm.o sha512-avx-asm.o sha512-avx2-asm.o sha512_ssse3_glue.o
+crct10dif-pclmul-y := crct10dif-pcl-asm_64.o crct10dif-pclmul_glue.o
diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S
index 62fe22cd4cba..477e9d75149b 100644
--- a/arch/x86/crypto/aesni-intel_asm.S
+++ b/arch/x86/crypto/aesni-intel_asm.S
@@ -2681,56 +2681,68 @@ ENTRY(aesni_xts_crypt8)
         addq %rcx, KEYP
 
         movdqa IV, STATE1
-        pxor 0x00(INP), STATE1
+        movdqu 0x00(INP), INC
+        pxor INC, STATE1
         movdqu IV, 0x00(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE2
-        pxor 0x10(INP), STATE2
+        movdqu 0x10(INP), INC
+        pxor INC, STATE2
         movdqu IV, 0x10(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE3
-        pxor 0x20(INP), STATE3
+        movdqu 0x20(INP), INC
+        pxor INC, STATE3
         movdqu IV, 0x20(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE4
-        pxor 0x30(INP), STATE4
+        movdqu 0x30(INP), INC
+        pxor INC, STATE4
         movdqu IV, 0x30(OUTP)
 
         call *%r11
 
-        pxor 0x00(OUTP), STATE1
+        movdqu 0x00(OUTP), INC
+        pxor INC, STATE1
         movdqu STATE1, 0x00(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE1
-        pxor 0x40(INP), STATE1
+        movdqu 0x40(INP), INC
+        pxor INC, STATE1
         movdqu IV, 0x40(OUTP)
 
-        pxor 0x10(OUTP), STATE2
+        movdqu 0x10(OUTP), INC
+        pxor INC, STATE2
         movdqu STATE2, 0x10(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE2
-        pxor 0x50(INP), STATE2
+        movdqu 0x50(INP), INC
+        pxor INC, STATE2
         movdqu IV, 0x50(OUTP)
 
-        pxor 0x20(OUTP), STATE3
+        movdqu 0x20(OUTP), INC
+        pxor INC, STATE3
         movdqu STATE3, 0x20(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE3
-        pxor 0x60(INP), STATE3
+        movdqu 0x60(INP), INC
+        pxor INC, STATE3
         movdqu IV, 0x60(OUTP)
 
-        pxor 0x30(OUTP), STATE4
+        movdqu 0x30(OUTP), INC
+        pxor INC, STATE4
         movdqu STATE4, 0x30(OUTP)
 
         _aesni_gf128mul_x_ble()
         movdqa IV, STATE4
-        pxor 0x70(INP), STATE4
+        movdqu 0x70(INP), INC
+        pxor INC, STATE4
         movdqu IV, 0x70(OUTP)
 
         _aesni_gf128mul_x_ble()
@@ -2738,16 +2750,20 @@ ENTRY(aesni_xts_crypt8)
 
         call *%r11
 
-        pxor 0x40(OUTP), STATE1
+        movdqu 0x40(OUTP), INC
+        pxor INC, STATE1
         movdqu STATE1, 0x40(OUTP)
 
-        pxor 0x50(OUTP), STATE2
+        movdqu 0x50(OUTP), INC
+        pxor INC, STATE2
         movdqu STATE2, 0x50(OUTP)
 
-        pxor 0x60(OUTP), STATE3
+        movdqu 0x60(OUTP), INC
+        pxor INC, STATE3
         movdqu STATE3, 0x60(OUTP)
 
-        pxor 0x70(OUTP), STATE4
+        movdqu 0x70(OUTP), INC
+        pxor INC, STATE4
         movdqu STATE4, 0x70(OUTP)
 
         ret
diff --git a/arch/x86/crypto/blowfish-avx2-asm_64.S b/arch/x86/crypto/blowfish-avx2-asm_64.S
deleted file mode 100644
index 784452e0d05d..000000000000
--- a/arch/x86/crypto/blowfish-avx2-asm_64.S
+++ /dev/null
@@ -1,449 +0,0 @@
-/*
- * x86_64/AVX2 assembler optimized version of Blowfish
- *
- * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/linkage.h>
-
-.file "blowfish-avx2-asm_64.S"
-
-.data
-.align 32
-
-.Lprefetch_mask:
-.long 0*64
-.long 1*64
-.long 2*64
-.long 3*64
-.long 4*64
-.long 5*64
-.long 6*64
-.long 7*64
-
-.Lbswap32_mask:
-.long 0x00010203
-.long 0x04050607
-.long 0x08090a0b
-.long 0x0c0d0e0f
-
-.Lbswap128_mask:
-        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
-.Lbswap_iv_mask:
-        .byte 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0
-
-.text
-/* structure of crypto context */
-#define p       0
-#define s0      ((16 + 2) * 4)
-#define s1      ((16 + 2 + (1 * 256)) * 4)
-#define s2      ((16 + 2 + (2 * 256)) * 4)
-#define s3      ((16 + 2 + (3 * 256)) * 4)
-
-/* register macros */
-#define CTX     %rdi
-#define RIO      %rdx
-
-#define RS0     %rax
-#define RS1     %r8
-#define RS2     %r9
-#define RS3     %r10
-
-#define RLOOP   %r11
-#define RLOOPd  %r11d
-
-#define RXr0    %ymm8
-#define RXr1    %ymm9
-#define RXr2    %ymm10
-#define RXr3    %ymm11
-#define RXl0    %ymm12
-#define RXl1    %ymm13
-#define RXl2    %ymm14
-#define RXl3    %ymm15
-
-/* temp regs */
-#define RT0     %ymm0
-#define RT0x    %xmm0
-#define RT1     %ymm1
-#define RT1x    %xmm1
-#define RIDX0   %ymm2
-#define RIDX1   %ymm3
-#define RIDX1x  %xmm3
-#define RIDX2   %ymm4
-#define RIDX3   %ymm5
-
-/* vpgatherdd mask and '-1' */
-#define RNOT    %ymm6
-
-/* byte mask, (-1 >> 24) */
-#define RBYTE   %ymm7
-
-/***********************************************************************
- * 32-way AVX2 blowfish
- ***********************************************************************/
-#define F(xl, xr) \
-        vpsrld $24, xl, RIDX0; \
-        vpsrld $16, xl, RIDX1; \
-        vpsrld $8, xl, RIDX2; \
-        vpand RBYTE, RIDX1, RIDX1; \
-        vpand RBYTE, RIDX2, RIDX2; \
-        vpand RBYTE, xl, RIDX3; \
-        \
-        vpgatherdd RNOT, (RS0, RIDX0, 4), RT0; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpcmpeqd RIDX0, RIDX0, RIDX0; \
-        \
-        vpgatherdd RNOT, (RS1, RIDX1, 4), RT1; \
-        vpcmpeqd RIDX1, RIDX1, RIDX1; \
-        vpaddd RT0, RT1, RT0; \
-        \
-        vpgatherdd RIDX0, (RS2, RIDX2, 4), RT1; \
-        vpxor RT0, RT1, RT0; \
-        \
-        vpgatherdd RIDX1, (RS3, RIDX3, 4), RT1; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpaddd RT0, RT1, RT0; \
-        \
-        vpxor RT0, xr, xr;
-
-#define add_roundkey(xl, nmem) \
-        vpbroadcastd nmem, RT0; \
-        vpxor RT0, xl ## 0, xl ## 0; \
-        vpxor RT0, xl ## 1, xl ## 1; \
-        vpxor RT0, xl ## 2, xl ## 2; \
-        vpxor RT0, xl ## 3, xl ## 3;
-
-#define round_enc() \
-        add_roundkey(RXr, p(CTX,RLOOP,4)); \
-        F(RXl0, RXr0); \
-        F(RXl1, RXr1); \
-        F(RXl2, RXr2); \
-        F(RXl3, RXr3); \
-        \
-        add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
-        F(RXr0, RXl0); \
-        F(RXr1, RXl1); \
-        F(RXr2, RXl2); \
-        F(RXr3, RXl3);
-
-#define round_dec() \
-        add_roundkey(RXr, p+4*2(CTX,RLOOP,4)); \
-        F(RXl0, RXr0); \
-        F(RXl1, RXr1); \
-        F(RXl2, RXr2); \
-        F(RXl3, RXr3); \
-        \
-        add_roundkey(RXl, p+4(CTX,RLOOP,4)); \
-        F(RXr0, RXl0); \
-        F(RXr1, RXl1); \
-        F(RXr2, RXl2); \
-        F(RXr3, RXl3);
-
-#define init_round_constants() \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        leaq s0(CTX), RS0; \
-        leaq s1(CTX), RS1; \
-        leaq s2(CTX), RS2; \
-        leaq s3(CTX), RS3; \
-        vpsrld $24, RNOT, RBYTE;
-
-#define transpose_2x2(x0, x1, t0) \
-        vpunpckldq x0, x1, t0; \
-        vpunpckhdq x0, x1, x1; \
-        \
-        vpunpcklqdq t0, x1, x0; \
-        vpunpckhqdq t0, x1, x1;
-
-#define read_block(xl, xr) \
-        vbroadcasti128 .Lbswap32_mask, RT1; \
-        \
-        vpshufb RT1, xl ## 0, xl ## 0; \
-        vpshufb RT1, xr ## 0, xr ## 0; \
-        vpshufb RT1, xl ## 1, xl ## 1; \
-        vpshufb RT1, xr ## 1, xr ## 1; \
-        vpshufb RT1, xl ## 2, xl ## 2; \
-        vpshufb RT1, xr ## 2, xr ## 2; \
-        vpshufb RT1, xl ## 3, xl ## 3; \
-        vpshufb RT1, xr ## 3, xr ## 3; \
-        \
-        transpose_2x2(xl ## 0, xr ## 0, RT0); \
-        transpose_2x2(xl ## 1, xr ## 1, RT0); \
-        transpose_2x2(xl ## 2, xr ## 2, RT0); \
-        transpose_2x2(xl ## 3, xr ## 3, RT0);
-
-#define write_block(xl, xr) \
-        vbroadcasti128 .Lbswap32_mask, RT1; \
-        \
-        transpose_2x2(xl ## 0, xr ## 0, RT0); \
-        transpose_2x2(xl ## 1, xr ## 1, RT0); \
-        transpose_2x2(xl ## 2, xr ## 2, RT0); \
-        transpose_2x2(xl ## 3, xr ## 3, RT0); \
-        \
-        vpshufb RT1, xl ## 0, xl ## 0; \
-        vpshufb RT1, xr ## 0, xr ## 0; \
-        vpshufb RT1, xl ## 1, xl ## 1; \
-        vpshufb RT1, xr ## 1, xr ## 1; \
-        vpshufb RT1, xl ## 2, xl ## 2; \
-        vpshufb RT1, xr ## 2, xr ## 2; \
-        vpshufb RT1, xl ## 3, xl ## 3; \
-        vpshufb RT1, xr ## 3, xr ## 3;
-
-.align 8
-__blowfish_enc_blk32:
-        /* input:
-         *      %rdi: ctx, CTX
-         *      RXl0..4, RXr0..4: plaintext
-         * output:
-         *      RXl0..4, RXr0..4: ciphertext (RXl <=> RXr swapped)
-         */
-        init_round_constants();
-
-        read_block(RXl, RXr);
-
-        movl $1, RLOOPd;
-        add_roundkey(RXl, p+4*(0)(CTX));
-
-.align 4
-.L__enc_loop:
-        round_enc();
-
-        leal 2(RLOOPd), RLOOPd;
-        cmpl $17, RLOOPd;
-        jne .L__enc_loop;
-
-        add_roundkey(RXr, p+4*(17)(CTX));
-
-        write_block(RXl, RXr);
-
-        ret;
-ENDPROC(__blowfish_enc_blk32)
-
-.align 8
-__blowfish_dec_blk32:
-        /* input:
-         *      %rdi: ctx, CTX
-         *      RXl0..4, RXr0..4: ciphertext
-         * output:
-         *      RXl0..4, RXr0..4: plaintext (RXl <=> RXr swapped)
-         */
-        init_round_constants();
-
-        read_block(RXl, RXr);
-
-        movl $14, RLOOPd;
-        add_roundkey(RXl, p+4*(17)(CTX));
-
-.align 4
-.L__dec_loop:
-        round_dec();
-
-        addl $-2, RLOOPd;
-        jns .L__dec_loop;
-
-        add_roundkey(RXr, p+4*(0)(CTX));
-
-        write_block(RXl, RXr);
-
-        ret;
-ENDPROC(__blowfish_dec_blk32)
-
-ENTRY(blowfish_ecb_enc_32way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-
-        vmovdqu 0*32(%rdx), RXl0;
-        vmovdqu 1*32(%rdx), RXr0;
-        vmovdqu 2*32(%rdx), RXl1;
-        vmovdqu 3*32(%rdx), RXr1;
-        vmovdqu 4*32(%rdx), RXl2;
-        vmovdqu 5*32(%rdx), RXr2;
-        vmovdqu 6*32(%rdx), RXl3;
-        vmovdqu 7*32(%rdx), RXr3;
-
-        call __blowfish_enc_blk32;
-
-        vmovdqu RXr0, 0*32(%rsi);
-        vmovdqu RXl0, 1*32(%rsi);
-        vmovdqu RXr1, 2*32(%rsi);
-        vmovdqu RXl1, 3*32(%rsi);
-        vmovdqu RXr2, 4*32(%rsi);
-        vmovdqu RXl2, 5*32(%rsi);
-        vmovdqu RXr3, 6*32(%rsi);
-        vmovdqu RXl3, 7*32(%rsi);
-
-        vzeroupper;
-
-        ret;
-ENDPROC(blowfish_ecb_enc_32way)
-
-ENTRY(blowfish_ecb_dec_32way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-
-        vmovdqu 0*32(%rdx), RXl0;
-        vmovdqu 1*32(%rdx), RXr0;
-        vmovdqu 2*32(%rdx), RXl1;
-        vmovdqu 3*32(%rdx), RXr1;
-        vmovdqu 4*32(%rdx), RXl2;
-        vmovdqu 5*32(%rdx), RXr2;
-        vmovdqu 6*32(%rdx), RXl3;
-        vmovdqu 7*32(%rdx), RXr3;
-
-        call __blowfish_dec_blk32;
-
-        vmovdqu RXr0, 0*32(%rsi);
-        vmovdqu RXl0, 1*32(%rsi);
-        vmovdqu RXr1, 2*32(%rsi);
-        vmovdqu RXl1, 3*32(%rsi);
-        vmovdqu RXr2, 4*32(%rsi);
-        vmovdqu RXl2, 5*32(%rsi);
-        vmovdqu RXr3, 6*32(%rsi);
-        vmovdqu RXl3, 7*32(%rsi);
-
-        vzeroupper;
-
-        ret;
-ENDPROC(blowfish_ecb_dec_32way)
-
-ENTRY(blowfish_cbc_dec_32way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-
-        vmovdqu 0*32(%rdx), RXl0;
-        vmovdqu 1*32(%rdx), RXr0;
-        vmovdqu 2*32(%rdx), RXl1;
-        vmovdqu 3*32(%rdx), RXr1;
-        vmovdqu 4*32(%rdx), RXl2;
-        vmovdqu 5*32(%rdx), RXr2;
-        vmovdqu 6*32(%rdx), RXl3;
-        vmovdqu 7*32(%rdx), RXr3;
-
-        call __blowfish_dec_blk32;
-
-        /* xor with src */
-        vmovq (%rdx), RT0x;
-        vpshufd $0x4f, RT0x, RT0x;
-        vinserti128 $1, 8(%rdx), RT0, RT0;
-        vpxor RT0, RXr0, RXr0;
-        vpxor 0*32+24(%rdx), RXl0, RXl0;
-        vpxor 1*32+24(%rdx), RXr1, RXr1;
-        vpxor 2*32+24(%rdx), RXl1, RXl1;
-        vpxor 3*32+24(%rdx), RXr2, RXr2;
-        vpxor 4*32+24(%rdx), RXl2, RXl2;
-        vpxor 5*32+24(%rdx), RXr3, RXr3;
-        vpxor 6*32+24(%rdx), RXl3, RXl3;
-
-        vmovdqu RXr0, (0*32)(%rsi);
-        vmovdqu RXl0, (1*32)(%rsi);
-        vmovdqu RXr1, (2*32)(%rsi);
-        vmovdqu RXl1, (3*32)(%rsi);
-        vmovdqu RXr2, (4*32)(%rsi);
-        vmovdqu RXl2, (5*32)(%rsi);
-        vmovdqu RXr3, (6*32)(%rsi);
-        vmovdqu RXl3, (7*32)(%rsi);
-
-        vzeroupper;
-
-        ret;
-ENDPROC(blowfish_cbc_dec_32way)
-
-ENTRY(blowfish_ctr_32way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         *      %rcx: iv (big endian, 64bit)
-         */
-
-        vzeroupper;
-
-        vpcmpeqd RT0, RT0, RT0;
-        vpsrldq $8, RT0, RT0; /* a: -1, b: 0, c: -1, d: 0 */
-
-        vpcmpeqd RT1x, RT1x, RT1x;
-        vpaddq RT1x, RT1x, RT1x; /* a: -2, b: -2 */
-        vpxor RIDX0, RIDX0, RIDX0;
-        vinserti128 $1, RT1x, RIDX0, RIDX0; /* a: 0, b: 0, c: -2, d: -2 */
-
-        vpaddq RIDX0, RT0, RT0; /* a: -1, b: 0, c: -3, d: -2 */
-
-        vpcmpeqd RT1, RT1, RT1;
-        vpaddq RT1, RT1, RT1; /* a: -2, b: -2, c: -2, d: -2 */
-        vpaddq RT1, RT1, RIDX2; /* a: -4, b: -4, c: -4, d: -4 */
-
-        vbroadcasti128 .Lbswap_iv_mask, RIDX0;
-        vbroadcasti128 .Lbswap128_mask, RIDX1;
-
-        /* load IV and byteswap */
-        vmovq (%rcx), RT1x;
-        vinserti128 $1, RT1x, RT1, RT1; /* a: BE, b: 0, c: BE, d: 0 */
-        vpshufb RIDX0, RT1, RT1; /* a: LE, b: LE, c: LE, d: LE */
-
-        /* construct IVs */
-        vpsubq RT0, RT1, RT1;           /* a: le1, b: le0, c: le3, d: le2 */
-        vpshufb RIDX1, RT1, RXl0;       /* a: be0, b: be1, c: be2, d: be3 */
-        vpsubq RIDX2, RT1, RT1;         /* le5, le4, le7, le6 */
-        vpshufb RIDX1, RT1, RXr0;       /* be4, be5, be6, be7 */
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXl1;
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXr1;
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXl2;
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXr2;
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXl3;
-        vpsubq RIDX2, RT1, RT1;
-        vpshufb RIDX1, RT1, RXr3;
-
-        /* store last IV */
-        vpsubq RIDX2, RT1, RT1; /* a: le33, b: le32, ... */
-        vpshufb RIDX1x, RT1x, RT1x; /* a: be32, ... */
-        vmovq RT1x, (%rcx);
-
-        call __blowfish_enc_blk32;
-
-        /* dst = src ^ iv */
-        vpxor 0*32(%rdx), RXr0, RXr0;
-        vpxor 1*32(%rdx), RXl0, RXl0;
-        vpxor 2*32(%rdx), RXr1, RXr1;
-        vpxor 3*32(%rdx), RXl1, RXl1;
-        vpxor 4*32(%rdx), RXr2, RXr2;
-        vpxor 5*32(%rdx), RXl2, RXl2;
-        vpxor 6*32(%rdx), RXr3, RXr3;
-        vpxor 7*32(%rdx), RXl3, RXl3;
-        vmovdqu RXr0, (0*32)(%rsi);
-        vmovdqu RXl0, (1*32)(%rsi);
-        vmovdqu RXr1, (2*32)(%rsi);
-        vmovdqu RXl1, (3*32)(%rsi);
-        vmovdqu RXr2, (4*32)(%rsi);
-        vmovdqu RXl2, (5*32)(%rsi);
-        vmovdqu RXr3, (6*32)(%rsi);
-        vmovdqu RXl3, (7*32)(%rsi);
-
-        vzeroupper;
-
-        ret;
-ENDPROC(blowfish_ctr_32way)
diff --git a/arch/x86/crypto/blowfish_avx2_glue.c b/arch/x86/crypto/blowfish_avx2_glue.c
deleted file mode 100644
index 4417e9aea78d..000000000000
--- a/arch/x86/crypto/blowfish_avx2_glue.c
+++ /dev/null
@@ -1,585 +0,0 @@
-/*
- * Glue Code for x86_64/AVX2 assembler optimized version of Blowfish
- *
- * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
- *
- * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
- *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
- * CTR part based on code (crypto/ctr.c) by:
- *   (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/crypto.h>
-#include <linux/err.h>
-#include <crypto/algapi.h>
-#include <crypto/blowfish.h>
-#include <crypto/cryptd.h>
-#include <crypto/ctr.h>
-#include <asm/i387.h>
-#include <asm/xcr.h>
-#include <asm/xsave.h>
-#include <asm/crypto/blowfish.h>
-#include <asm/crypto/ablk_helper.h>
-#include <crypto/scatterwalk.h>
-
-#define BF_AVX2_PARALLEL_BLOCKS 32
-
-/* 32-way AVX2 parallel cipher functions */
-asmlinkage void blowfish_ecb_enc_32way(struct bf_ctx *ctx, u8 *dst,
-                                       const u8 *src);
-asmlinkage void blowfish_ecb_dec_32way(struct bf_ctx *ctx, u8 *dst,
-                                       const u8 *src);
-asmlinkage void blowfish_cbc_dec_32way(struct bf_ctx *ctx, u8 *dst,
-                                       const u8 *src);
-asmlinkage void blowfish_ctr_32way(struct bf_ctx *ctx, u8 *dst, const u8 *src,
-                                   __be64 *iv);
-
-static inline bool bf_fpu_begin(bool fpu_enabled, unsigned int nbytes)
-{
-        if (fpu_enabled)
-                return true;
-
-        /* FPU is only used when chunk to be processed is large enough, so
-         * do not enable FPU until it is necessary.
-         */
-        if (nbytes < BF_BLOCK_SIZE * BF_AVX2_PARALLEL_BLOCKS)
-                return false;
-
-        kernel_fpu_begin();
-        return true;
-}
-
-static inline void bf_fpu_end(bool fpu_enabled)
-{
-        if (fpu_enabled)
-                kernel_fpu_end();
-}
-
-static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
-                     bool enc)
-{
-        bool fpu_enabled = false;
-        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = BF_BLOCK_SIZE;
-        unsigned int nbytes;
-        int err;
-
-        err = blkcipher_walk_virt(desc, walk);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk->nbytes)) {
-                u8 *wsrc = walk->src.virt.addr;
-                u8 *wdst = walk->dst.virt.addr;
-
-                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
-
-                /* Process multi-block AVX2 batch */
-                if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
-                        do {
-                                if (enc)
-                                        blowfish_ecb_enc_32way(ctx, wdst, wsrc);
-                                else
-                                        blowfish_ecb_dec_32way(ctx, wdst, wsrc);
-
-                                wsrc += bsize * BF_AVX2_PARALLEL_BLOCKS;
-                                wdst += bsize * BF_AVX2_PARALLEL_BLOCKS;
-                                nbytes -= bsize * BF_AVX2_PARALLEL_BLOCKS;
-                        } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
-
-                        if (nbytes < bsize)
-                                goto done;
-                }
-
-                /* Process multi-block batch */
-                if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
-                        do {
-                                if (enc)
-                                        blowfish_enc_blk_4way(ctx, wdst, wsrc);
-                                else
-                                        blowfish_dec_blk_4way(ctx, wdst, wsrc);
-
-                                wsrc += bsize * BF_PARALLEL_BLOCKS;
-                                wdst += bsize * BF_PARALLEL_BLOCKS;
-                                nbytes -= bsize * BF_PARALLEL_BLOCKS;
-                        } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
-
-                        if (nbytes < bsize)
-                                goto done;
-                }
-
-                /* Handle leftovers */
-                do {
-                        if (enc)
-                                blowfish_enc_blk(ctx, wdst, wsrc);
-                        else
-                                blowfish_dec_blk(ctx, wdst, wsrc);
-
-                        wsrc += bsize;
-                        wdst += bsize;
-                        nbytes -= bsize;
-                } while (nbytes >= bsize);
-
-done:
-                err = blkcipher_walk_done(desc, walk, nbytes);
-        }
-
-        bf_fpu_end(fpu_enabled);
-        return err;
-}
-
-static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, true);
-}
-
-static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, false);
-}
-
-static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = BF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u64 *src = (u64 *)walk->src.virt.addr;
-        u64 *dst = (u64 *)walk->dst.virt.addr;
-        u64 *iv = (u64 *)walk->iv;
-
-        do {
-                *dst = *src ^ *iv;
-                blowfish_enc_blk(ctx, (u8 *)dst, (u8 *)dst);
-                iv = dst;
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-        *(u64 *)walk->iv = *iv;
-        return nbytes;
-}
-
-static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
-
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_encrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        return err;
-}
-
-static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = BF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u64 *src = (u64 *)walk->src.virt.addr;
-        u64 *dst = (u64 *)walk->dst.virt.addr;
-        u64 last_iv;
-        int i;
-
-        /* Start of the last block. */
-        src += nbytes / bsize - 1;
-        dst += nbytes / bsize - 1;
-
-        last_iv = *src;
-
-        /* Process multi-block AVX2 batch */
-        if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
-                do {
-                        nbytes -= bsize * (BF_AVX2_PARALLEL_BLOCKS - 1);
-                        src -= BF_AVX2_PARALLEL_BLOCKS - 1;
-                        dst -= BF_AVX2_PARALLEL_BLOCKS - 1;
-
-                        blowfish_cbc_dec_32way(ctx, (u8 *)dst, (u8 *)src);
-
-                        nbytes -= bsize;
-                        if (nbytes < bsize)
-                                goto done;
-
-                        *dst ^= *(src - 1);
-                        src -= 1;
-                        dst -= 1;
-                } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Process multi-block batch */
-        if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
-                u64 ivs[BF_PARALLEL_BLOCKS - 1];
-
-                do {
-                        nbytes -= bsize * (BF_PARALLEL_BLOCKS - 1);
-                        src -= BF_PARALLEL_BLOCKS - 1;
-                        dst -= BF_PARALLEL_BLOCKS - 1;
-
-                        for (i = 0; i < BF_PARALLEL_BLOCKS - 1; i++)
-                                ivs[i] = src[i];
-
-                        blowfish_dec_blk_4way(ctx, (u8 *)dst, (u8 *)src);
-
-                        for (i = 0; i < BF_PARALLEL_BLOCKS - 1; i++)
-                                dst[i + 1] ^= ivs[i];
-
-                        nbytes -= bsize;
-                        if (nbytes < bsize)
-                                goto done;
-
-                        *dst ^= *(src - 1);
-                        src -= 1;
-                        dst -= 1;
-                } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        for (;;) {
-                blowfish_dec_blk(ctx, (u8 *)dst, (u8 *)src);
-
-                nbytes -= bsize;
-                if (nbytes < bsize)
-                        break;
-
-                *dst ^= *(src - 1);
-                src -= 1;
-                dst -= 1;
-        }
-
-done:
-        *dst ^= *(u64 *)walk->iv;
-        *(u64 *)walk->iv = last_iv;
-
-        return nbytes;
-}
-
-static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        bool fpu_enabled = false;
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk.nbytes)) {
-                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
-                nbytes = __cbc_decrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        bf_fpu_end(fpu_enabled);
-        return err;
-}
-
-static void ctr_crypt_final(struct blkcipher_desc *desc,
-                            struct blkcipher_walk *walk)
-{
-        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        u8 *ctrblk = walk->iv;
-        u8 keystream[BF_BLOCK_SIZE];
-        u8 *src = walk->src.virt.addr;
-        u8 *dst = walk->dst.virt.addr;
-        unsigned int nbytes = walk->nbytes;
-
-        blowfish_enc_blk(ctx, keystream, ctrblk);
-        crypto_xor(keystream, src, nbytes);
-        memcpy(dst, keystream, nbytes);
-
-        crypto_inc(ctrblk, BF_BLOCK_SIZE);
-}
-
-static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
-                                struct blkcipher_walk *walk)
-{
-        struct bf_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = BF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u64 *src = (u64 *)walk->src.virt.addr;
-        u64 *dst = (u64 *)walk->dst.virt.addr;
-        int i;
-
-        /* Process multi-block AVX2 batch */
-        if (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS) {
-                do {
-                        blowfish_ctr_32way(ctx, (u8 *)dst, (u8 *)src,
-                                           (__be64 *)walk->iv);
-
-                        src += BF_AVX2_PARALLEL_BLOCKS;
-                        dst += BF_AVX2_PARALLEL_BLOCKS;
-                        nbytes -= bsize * BF_AVX2_PARALLEL_BLOCKS;
-                } while (nbytes >= bsize * BF_AVX2_PARALLEL_BLOCKS);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Process four block batch */
-        if (nbytes >= bsize * BF_PARALLEL_BLOCKS) {
-                __be64 ctrblocks[BF_PARALLEL_BLOCKS];
-                u64 ctrblk = be64_to_cpu(*(__be64 *)walk->iv);
-
-                do {
-                        /* create ctrblks for parallel encrypt */
-                        for (i = 0; i < BF_PARALLEL_BLOCKS; i++) {
-                                if (dst != src)
-                                        dst[i] = src[i];
-
-                                ctrblocks[i] = cpu_to_be64(ctrblk++);
-                        }
-
-                        blowfish_enc_blk_xor_4way(ctx, (u8 *)dst,
-                                                  (u8 *)ctrblocks);
-
-                        src += BF_PARALLEL_BLOCKS;
-                        dst += BF_PARALLEL_BLOCKS;
-                        nbytes -= bsize * BF_PARALLEL_BLOCKS;
-                } while (nbytes >= bsize * BF_PARALLEL_BLOCKS);
-
-                *(__be64 *)walk->iv = cpu_to_be64(ctrblk);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        do {
-                u64 ctrblk;
-
-                if (dst != src)
-                        *dst = *src;
-
-                ctrblk = *(u64 *)walk->iv;
-                be64_add_cpu((__be64 *)walk->iv, 1);
-
-                blowfish_enc_blk_xor(ctx, (u8 *)dst, (u8 *)&ctrblk);
-
-                src += 1;
-                dst += 1;
-        } while ((nbytes -= bsize) >= bsize);
-
-done:
-        return nbytes;
-}
-
-static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                     struct scatterlist *src, unsigned int nbytes)
-{
-        bool fpu_enabled = false;
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt_block(desc, &walk, BF_BLOCK_SIZE);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk.nbytes) >= BF_BLOCK_SIZE) {
-                fpu_enabled = bf_fpu_begin(fpu_enabled, nbytes);
-                nbytes = __ctr_crypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        bf_fpu_end(fpu_enabled);
-
-        if (walk.nbytes) {
-                ctr_crypt_final(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, 0);
-        }
-
-        return err;
-}
-
-static struct crypto_alg bf_algs[6] = { {
-        .cra_name               = "__ecb-blowfish-avx2",
-        .cra_driver_name        = "__driver-ecb-blowfish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = BF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct bf_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .setkey         = blowfish_setkey,
-                        .encrypt        = ecb_encrypt,
-                        .decrypt        = ecb_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "__cbc-blowfish-avx2",
-        .cra_driver_name        = "__driver-cbc-blowfish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = BF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct bf_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .setkey         = blowfish_setkey,
-                        .encrypt        = cbc_encrypt,
-                        .decrypt        = cbc_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "__ctr-blowfish-avx2",
-        .cra_driver_name        = "__driver-ctr-blowfish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct bf_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .ivsize         = BF_BLOCK_SIZE,
-                        .setkey         = blowfish_setkey,
-                        .encrypt        = ctr_crypt,
-                        .decrypt        = ctr_crypt,
-                },
-        },
-}, {
-        .cra_name               = "ecb(blowfish)",
-        .cra_driver_name        = "ecb-blowfish-avx2",
-        .cra_priority           = 400,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = BF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "cbc(blowfish)",
-        .cra_driver_name        = "cbc-blowfish-avx2",
-        .cra_priority           = 400,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = BF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .ivsize         = BF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = __ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "ctr(blowfish)",
-        .cra_driver_name        = "ctr-blowfish-avx2",
-        .cra_priority           = 400,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = BF_MIN_KEY_SIZE,
-                        .max_keysize    = BF_MAX_KEY_SIZE,
-                        .ivsize         = BF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_encrypt,
-                        .geniv          = "chainiv",
-                },
-        },
-} };
-
-
-static int __init init(void)
-{
-        u64 xcr0;
-
-        if (!cpu_has_avx2 || !cpu_has_osxsave) {
-                pr_info("AVX2 instructions are not detected.\n");
-                return -ENODEV;
-        }
-
-        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
-        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
-                pr_info("AVX detected but unusable.\n");
-                return -ENODEV;
-        }
-
-        return crypto_register_algs(bf_algs, ARRAY_SIZE(bf_algs));
-}
-
-static void __exit fini(void)
-{
-        crypto_unregister_algs(bf_algs, ARRAY_SIZE(bf_algs));
-}
-
-module_init(init);
-module_exit(fini);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Blowfish Cipher Algorithm, AVX2 optimized");
-MODULE_ALIAS("blowfish");
-MODULE_ALIAS("blowfish-asm");
diff --git a/arch/x86/crypto/blowfish_glue.c b/arch/x86/crypto/blowfish_glue.c
index 3548d76dbaa9..50ec333b70e6 100644
--- a/arch/x86/crypto/blowfish_glue.c
+++ b/arch/x86/crypto/blowfish_glue.c
@@ -1,7 +1,7 @@
 /*
  * Glue Code for assembler optimized version of Blowfish
  *
- * Copyright © 2011-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
+ * Copyright (c) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
  *
  * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
  *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
@@ -32,24 +32,40 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <crypto/algapi.h>
-#include <asm/crypto/blowfish.h>
 
 /* regular block cipher functions */
 asmlinkage void __blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src,
                                    bool xor);
-EXPORT_SYMBOL_GPL(__blowfish_enc_blk);
-
 asmlinkage void blowfish_dec_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src);
-EXPORT_SYMBOL_GPL(blowfish_dec_blk);
 
 /* 4-way parallel cipher functions */
 asmlinkage void __blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
                                         const u8 *src, bool xor);
-EXPORT_SYMBOL_GPL(__blowfish_enc_blk_4way);
-
 asmlinkage void blowfish_dec_blk_4way(struct bf_ctx *ctx, u8 *dst,
                                       const u8 *src);
-EXPORT_SYMBOL_GPL(blowfish_dec_blk_4way);
+
+static inline void blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src)
+{
+        __blowfish_enc_blk(ctx, dst, src, false);
+}
+
+static inline void blowfish_enc_blk_xor(struct bf_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        __blowfish_enc_blk(ctx, dst, src, true);
+}
+
+static inline void blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
+                                         const u8 *src)
+{
+        __blowfish_enc_blk_4way(ctx, dst, src, false);
+}
+
+static inline void blowfish_enc_blk_xor_4way(struct bf_ctx *ctx, u8 *dst,
+                                      const u8 *src)
+{
+        __blowfish_enc_blk_4way(ctx, dst, src, true);
+}
 
 static void blowfish_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 {
diff --git a/arch/x86/crypto/camellia-aesni-avx2-asm_64.S b/arch/x86/crypto/camellia-aesni-avx2-asm_64.S
index 91a1878fcc3e..0e0b8863a34b 100644
--- a/arch/x86/crypto/camellia-aesni-avx2-asm_64.S
+++ b/arch/x86/crypto/camellia-aesni-avx2-asm_64.S
@@ -51,16 +51,6 @@
 #define ymm14_x xmm14
 #define ymm15_x xmm15
 
-/*
- * AES-NI instructions do not support ymmX registers, so we need splitting and
- * merging.
- */
-#define vaesenclast256(zero, yreg, tmp) \
-        vextracti128 $1, yreg, tmp##_x; \
-        vaesenclast zero##_x, yreg##_x, yreg##_x; \
-        vaesenclast zero##_x, tmp##_x, tmp##_x; \
-        vinserti128 $1, tmp##_x, yreg, yreg;
-
 /**********************************************************************
   32-way camellia
  **********************************************************************/
@@ -79,46 +69,70 @@
          * S-function with AES subbytes \
          */ \
         vbroadcasti128 .Linv_shift_row, t4; \
-        vpbroadcastb .L0f0f0f0f, t7; \
-        vbroadcasti128 .Lpre_tf_lo_s1, t0; \
-        vbroadcasti128 .Lpre_tf_hi_s1, t1; \
+        vpbroadcastd .L0f0f0f0f, t7; \
+        vbroadcasti128 .Lpre_tf_lo_s1, t5; \
+        vbroadcasti128 .Lpre_tf_hi_s1, t6; \
+        vbroadcasti128 .Lpre_tf_lo_s4, t2; \
+        vbroadcasti128 .Lpre_tf_hi_s4, t3; \
         \
         /* AES inverse shift rows */ \
         vpshufb t4, x0, x0; \
         vpshufb t4, x7, x7; \
-        vpshufb t4, x1, x1; \
-        vpshufb t4, x4, x4; \
-        vpshufb t4, x2, x2; \
-        vpshufb t4, x5, x5; \
         vpshufb t4, x3, x3; \
         vpshufb t4, x6, x6; \
+        vpshufb t4, x2, x2; \
+        vpshufb t4, x5, x5; \
+        vpshufb t4, x1, x1; \
+        vpshufb t4, x4, x4; \
         \
         /* prefilter sboxes 1, 2 and 3 */ \
-        vbroadcasti128 .Lpre_tf_lo_s4, t2; \
-        vbroadcasti128 .Lpre_tf_hi_s4, t3; \
-        filter_8bit(x0, t0, t1, t7, t6); \
-        filter_8bit(x7, t0, t1, t7, t6); \
-        filter_8bit(x1, t0, t1, t7, t6); \
-        filter_8bit(x4, t0, t1, t7, t6); \
-        filter_8bit(x2, t0, t1, t7, t6); \
-        filter_8bit(x5, t0, t1, t7, t6); \
-        \
         /* prefilter sbox 4 */ \
+        filter_8bit(x0, t5, t6, t7, t4); \
+        filter_8bit(x7, t5, t6, t7, t4); \
+        vextracti128 $1, x0, t0##_x; \
+        vextracti128 $1, x7, t1##_x; \
+        filter_8bit(x3, t2, t3, t7, t4); \
+        filter_8bit(x6, t2, t3, t7, t4); \
+        vextracti128 $1, x3, t3##_x; \
+        vextracti128 $1, x6, t2##_x; \
+        filter_8bit(x2, t5, t6, t7, t4); \
+        filter_8bit(x5, t5, t6, t7, t4); \
+        filter_8bit(x1, t5, t6, t7, t4); \
+        filter_8bit(x4, t5, t6, t7, t4); \
+        \
         vpxor t4##_x, t4##_x, t4##_x; \
-        filter_8bit(x3, t2, t3, t7, t6); \
-        filter_8bit(x6, t2, t3, t7, t6); \
         \
         /* AES subbytes + AES shift rows */ \
+        vextracti128 $1, x2, t6##_x; \
+        vextracti128 $1, x5, t5##_x; \
+        vaesenclast t4##_x, x0##_x, x0##_x; \
+        vaesenclast t4##_x, t0##_x, t0##_x; \
+        vinserti128 $1, t0##_x, x0, x0; \
+        vaesenclast t4##_x, x7##_x, x7##_x; \
+        vaesenclast t4##_x, t1##_x, t1##_x; \
+        vinserti128 $1, t1##_x, x7, x7; \
+        vaesenclast t4##_x, x3##_x, x3##_x; \
+        vaesenclast t4##_x, t3##_x, t3##_x; \
+        vinserti128 $1, t3##_x, x3, x3; \
+        vaesenclast t4##_x, x6##_x, x6##_x; \
+        vaesenclast t4##_x, t2##_x, t2##_x; \
+        vinserti128 $1, t2##_x, x6, x6; \
+        vextracti128 $1, x1, t3##_x; \
+        vextracti128 $1, x4, t2##_x; \
         vbroadcasti128 .Lpost_tf_lo_s1, t0; \
         vbroadcasti128 .Lpost_tf_hi_s1, t1; \
-        vaesenclast256(t4, x0, t5); \
-        vaesenclast256(t4, x7, t5); \
-        vaesenclast256(t4, x1, t5); \
-        vaesenclast256(t4, x4, t5); \
-        vaesenclast256(t4, x2, t5); \
-        vaesenclast256(t4, x5, t5); \
-        vaesenclast256(t4, x3, t5); \
-        vaesenclast256(t4, x6, t5); \
+        vaesenclast t4##_x, x2##_x, x2##_x; \
+        vaesenclast t4##_x, t6##_x, t6##_x; \
+        vinserti128 $1, t6##_x, x2, x2; \
+        vaesenclast t4##_x, x5##_x, x5##_x; \
+        vaesenclast t4##_x, t5##_x, t5##_x; \
+        vinserti128 $1, t5##_x, x5, x5; \
+        vaesenclast t4##_x, x1##_x, x1##_x; \
+        vaesenclast t4##_x, t3##_x, t3##_x; \
+        vinserti128 $1, t3##_x, x1, x1; \
+        vaesenclast t4##_x, x4##_x, x4##_x; \
+        vaesenclast t4##_x, t2##_x, t2##_x; \
+        vinserti128 $1, t2##_x, x4, x4; \
         \
         /* postfilter sboxes 1 and 4 */ \
         vbroadcasti128 .Lpost_tf_lo_s3, t2; \
@@ -139,22 +153,12 @@
         /* postfilter sbox 2 */ \
         filter_8bit(x1, t4, t5, t7, t2); \
         filter_8bit(x4, t4, t5, t7, t2); \
+        vpxor t7, t7, t7; \
         \
         vpsrldq $1, t0, t1; \
         vpsrldq $2, t0, t2; \
+        vpshufb t7, t1, t1; \
         vpsrldq $3, t0, t3; \
-        vpsrldq $4, t0, t4; \
-        vpsrldq $5, t0, t5; \
-        vpsrldq $6, t0, t6; \
-        vpsrldq $7, t0, t7; \
-        vpbroadcastb t0##_x, t0; \
-        vpbroadcastb t1##_x, t1; \
-        vpbroadcastb t2##_x, t2; \
-        vpbroadcastb t3##_x, t3; \
-        vpbroadcastb t4##_x, t4; \
-        vpbroadcastb t6##_x, t6; \
-        vpbroadcastb t5##_x, t5; \
-        vpbroadcastb t7##_x, t7; \
         \
         /* P-function */ \
         vpxor x5, x0, x0; \
@@ -162,11 +166,21 @@
         vpxor x7, x2, x2; \
         vpxor x4, x3, x3; \
         \
+        vpshufb t7, t2, t2; \
+        vpsrldq $4, t0, t4; \
+        vpshufb t7, t3, t3; \
+        vpsrldq $5, t0, t5; \
+        vpshufb t7, t4, t4; \
+        \
         vpxor x2, x4, x4; \
         vpxor x3, x5, x5; \
         vpxor x0, x6, x6; \
         vpxor x1, x7, x7; \
         \
+        vpsrldq $6, t0, t6; \
+        vpshufb t7, t5, t5; \
+        vpshufb t7, t6, t6; \
+        \
         vpxor x7, x0, x0; \
         vpxor x4, x1, x1; \
         vpxor x5, x2, x2; \
@@ -179,12 +193,16 @@
         \
         /* Add key material and result to CD (x becomes new CD) */ \
         \
-        vpxor t7, x0, x0; \
-        vpxor 4 * 32(mem_cd), x0, x0; \
-        \
         vpxor t6, x1, x1; \
         vpxor 5 * 32(mem_cd), x1, x1; \
         \
+        vpsrldq $7, t0, t6; \
+        vpshufb t7, t0, t0; \
+        vpshufb t7, t6, t7; \
+        \
+        vpxor t7, x0, x0; \
+        vpxor 4 * 32(mem_cd), x0, x0; \
+        \
         vpxor t5, x2, x2; \
         vpxor 6 * 32(mem_cd), x2, x2; \
         \
@@ -204,7 +222,7 @@
         vpxor 3 * 32(mem_cd), x7, x7;
 
 /*
- * Size optimization... with inlined roundsm16 binary would be over 5 times
+ * Size optimization... with inlined roundsm32 binary would be over 5 times
  * larger and would only marginally faster.
  */
 .align 8
@@ -324,13 +342,13 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
          */ \
         vpbroadcastd kll, t0; /* only lowest 32-bit used */ \
         vpxor tt0, tt0, tt0; \
-        vpbroadcastb t0##_x, t3; \
+        vpshufb tt0, t0, t3; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t2; \
+        vpshufb tt0, t0, t2; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t1; \
+        vpshufb tt0, t0, t1; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t0; \
+        vpshufb tt0, t0, t0; \
         \
         vpand l0, t0, t0; \
         vpand l1, t1, t1; \
@@ -340,6 +358,7 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
         rol32_1_32(t3, t2, t1, t0, tt1, tt2, tt3, tt0); \
         \
         vpxor l4, t0, l4; \
+        vpbroadcastd krr, t0; /* only lowest 32-bit used */ \
         vmovdqu l4, 4 * 32(l); \
         vpxor l5, t1, l5; \
         vmovdqu l5, 5 * 32(l); \
@@ -354,14 +373,13 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
          * rl ^= t2; \
          */ \
         \
-        vpbroadcastd krr, t0; /* only lowest 32-bit used */ \
-        vpbroadcastb t0##_x, t3; \
+        vpshufb tt0, t0, t3; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t2; \
+        vpshufb tt0, t0, t2; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t1; \
+        vpshufb tt0, t0, t1; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t0; \
+        vpshufb tt0, t0, t0; \
         \
         vpor 4 * 32(r), t0, t0; \
         vpor 5 * 32(r), t1, t1; \
@@ -373,6 +391,7 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
         vpxor 2 * 32(r), t2, t2; \
         vpxor 3 * 32(r), t3, t3; \
         vmovdqu t0, 0 * 32(r); \
+        vpbroadcastd krl, t0; /* only lowest 32-bit used */ \
         vmovdqu t1, 1 * 32(r); \
         vmovdqu t2, 2 * 32(r); \
         vmovdqu t3, 3 * 32(r); \
@@ -382,14 +401,13 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
          * t2 &= rl; \
          * rr ^= rol32(t2, 1); \
          */ \
-        vpbroadcastd krl, t0; /* only lowest 32-bit used */ \
-        vpbroadcastb t0##_x, t3; \
+        vpshufb tt0, t0, t3; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t2; \
+        vpshufb tt0, t0, t2; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t1; \
+        vpshufb tt0, t0, t1; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t0; \
+        vpshufb tt0, t0, t0; \
         \
         vpand 0 * 32(r), t0, t0; \
         vpand 1 * 32(r), t1, t1; \
@@ -403,6 +421,7 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
         vpxor 6 * 32(r), t2, t2; \
         vpxor 7 * 32(r), t3, t3; \
         vmovdqu t0, 4 * 32(r); \
+        vpbroadcastd klr, t0; /* only lowest 32-bit used */ \
         vmovdqu t1, 5 * 32(r); \
         vmovdqu t2, 6 * 32(r); \
         vmovdqu t3, 7 * 32(r); \
@@ -413,14 +432,13 @@ ENDPROC(roundsm32_x4_x5_x6_x7_x0_x1_x2_x3_y4_y5_y6_y7_y0_y1_y2_y3_ab)
          * ll ^= t0; \
          */ \
         \
-        vpbroadcastd klr, t0; /* only lowest 32-bit used */ \
-        vpbroadcastb t0##_x, t3; \
+        vpshufb tt0, t0, t3; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t2; \
+        vpshufb tt0, t0, t2; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t1; \
+        vpshufb tt0, t0, t1; \
         vpsrldq $1, t0, t0; \
-        vpbroadcastb t0##_x, t0; \
+        vpshufb tt0, t0, t0; \
         \
         vpor l4, t0, t0; \
         vpor l5, t1, t1; \
diff --git a/arch/x86/crypto/crct10dif-pcl-asm_64.S b/arch/x86/crypto/crct10dif-pcl-asm_64.S
new file mode 100644
index 000000000000..35e97569d05f
--- /dev/null
+++ b/arch/x86/crypto/crct10dif-pcl-asm_64.S
@@ -0,0 +1,643 @@
+########################################################################
+# Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
+#
+# Copyright (c) 2013, Intel Corporation
+#
+# Authors:
+#     Erdinc Ozturk <erdinc.ozturk@intel.com>
+#     Vinodh Gopal <vinodh.gopal@intel.com>
+#     James Guilford <james.guilford@intel.com>
+#     Tim Chen <tim.c.chen@linux.intel.com>
+#
+# This software is available to you under a choice of one of two
+# licenses.  You may choose to be licensed under the terms of the GNU
+# General Public License (GPL) Version 2, available from the file
+# COPYING in the main directory of this source tree, or the
+# OpenIB.org BSD license below:
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+#   notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+#   notice, this list of conditions and the following disclaimer in the
+#   documentation and/or other materials provided with the
+#   distribution.
+#
+# * Neither the name of the Intel Corporation nor the names of its
+#   contributors may be used to endorse or promote products derived from
+#   this software without specific prior written permission.
+#
+#
+# THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION ""AS IS"" AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
+#       Function API:
+#       UINT16 crc_t10dif_pcl(
+#               UINT16 init_crc, //initial CRC value, 16 bits
+#               const unsigned char *buf, //buffer pointer to calculate CRC on
+#               UINT64 len //buffer length in bytes (64-bit data)
+#       );
+#
+#       Reference paper titled "Fast CRC Computation for Generic
+#       Polynomials Using PCLMULQDQ Instruction"
+#       URL: http://www.intel.com/content/dam/www/public/us/en/documents
+#  /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
+#
+#
+
+#include <linux/linkage.h>
+
+.text
+
+#define        arg1 %rdi
+#define        arg2 %rsi
+#define        arg3 %rdx
+
+#define        arg1_low32 %edi
+
+ENTRY(crc_t10dif_pcl)
+.align 16
+
+        # adjust the 16-bit initial_crc value, scale it to 32 bits
+        shl     $16, arg1_low32
+
+        # Allocate Stack Space
+        mov     %rsp, %rcx
+        sub     $16*2, %rsp
+        # align stack to 16 byte boundary
+        and     $~(0x10 - 1), %rsp
+
+        # check if smaller than 256
+        cmp     $256, arg3
+
+        # for sizes less than 128, we can't fold 64B at a time...
+        jl      _less_than_128
+
+
+        # load the initial crc value
+        movd    arg1_low32, %xmm10      # initial crc
+
+        # crc value does not need to be byte-reflected, but it needs
+        # to be moved to the high part of the register.
+        # because data will be byte-reflected and will align with
+        # initial crc at correct place.
+        pslldq  $12, %xmm10
+
+        movdqa  SHUF_MASK(%rip), %xmm11
+        # receive the initial 64B data, xor the initial crc value
+        movdqu  16*0(arg2), %xmm0
+        movdqu  16*1(arg2), %xmm1
+        movdqu  16*2(arg2), %xmm2
+        movdqu  16*3(arg2), %xmm3
+        movdqu  16*4(arg2), %xmm4
+        movdqu  16*5(arg2), %xmm5
+        movdqu  16*6(arg2), %xmm6
+        movdqu  16*7(arg2), %xmm7
+
+        pshufb  %xmm11, %xmm0
+        # XOR the initial_crc value
+        pxor    %xmm10, %xmm0
+        pshufb  %xmm11, %xmm1
+        pshufb  %xmm11, %xmm2
+        pshufb  %xmm11, %xmm3
+        pshufb  %xmm11, %xmm4
+        pshufb  %xmm11, %xmm5
+        pshufb  %xmm11, %xmm6
+        pshufb  %xmm11, %xmm7
+
+        movdqa  rk3(%rip), %xmm10       #xmm10 has rk3 and rk4
+                                        #imm value of pclmulqdq instruction
+                                        #will determine which constant to use
+
+        #################################################################
+        # we subtract 256 instead of 128 to save one instruction from the loop
+        sub     $256, arg3
+
+        # at this section of the code, there is 64*x+y (0<=y<64) bytes of
+        # buffer. The _fold_64_B_loop will fold 64B at a time
+        # until we have 64+y Bytes of buffer
+
+
+        # fold 64B at a time. This section of the code folds 4 xmm
+        # registers in parallel
+_fold_64_B_loop:
+
+        # update the buffer pointer
+        add     $128, arg2              #    buf += 64#
+
+        movdqu  16*0(arg2), %xmm9
+        movdqu  16*1(arg2), %xmm12
+        pshufb  %xmm11, %xmm9
+        pshufb  %xmm11, %xmm12
+        movdqa  %xmm0, %xmm8
+        movdqa  %xmm1, %xmm13
+        pclmulqdq       $0x0 , %xmm10, %xmm0
+        pclmulqdq       $0x11, %xmm10, %xmm8
+        pclmulqdq       $0x0 , %xmm10, %xmm1
+        pclmulqdq       $0x11, %xmm10, %xmm13
+        pxor    %xmm9 , %xmm0
+        xorps   %xmm8 , %xmm0
+        pxor    %xmm12, %xmm1
+        xorps   %xmm13, %xmm1
+
+        movdqu  16*2(arg2), %xmm9
+        movdqu  16*3(arg2), %xmm12
+        pshufb  %xmm11, %xmm9
+        pshufb  %xmm11, %xmm12
+        movdqa  %xmm2, %xmm8
+        movdqa  %xmm3, %xmm13
+        pclmulqdq       $0x0, %xmm10, %xmm2
+        pclmulqdq       $0x11, %xmm10, %xmm8
+        pclmulqdq       $0x0, %xmm10, %xmm3
+        pclmulqdq       $0x11, %xmm10, %xmm13
+        pxor    %xmm9 , %xmm2
+        xorps   %xmm8 , %xmm2
+        pxor    %xmm12, %xmm3
+        xorps   %xmm13, %xmm3
+
+        movdqu  16*4(arg2), %xmm9
+        movdqu  16*5(arg2), %xmm12
+        pshufb  %xmm11, %xmm9
+        pshufb  %xmm11, %xmm12
+        movdqa  %xmm4, %xmm8
+        movdqa  %xmm5, %xmm13
+        pclmulqdq       $0x0,  %xmm10, %xmm4
+        pclmulqdq       $0x11, %xmm10, %xmm8
+        pclmulqdq       $0x0,  %xmm10, %xmm5
+        pclmulqdq       $0x11, %xmm10, %xmm13
+        pxor    %xmm9 ,  %xmm4
+        xorps   %xmm8 ,  %xmm4
+        pxor    %xmm12,  %xmm5
+        xorps   %xmm13,  %xmm5
+
+        movdqu  16*6(arg2), %xmm9
+        movdqu  16*7(arg2), %xmm12
+        pshufb  %xmm11, %xmm9
+        pshufb  %xmm11, %xmm12
+        movdqa  %xmm6 , %xmm8
+        movdqa  %xmm7 , %xmm13
+        pclmulqdq       $0x0 , %xmm10, %xmm6
+        pclmulqdq       $0x11, %xmm10, %xmm8
+        pclmulqdq       $0x0 , %xmm10, %xmm7
+        pclmulqdq       $0x11, %xmm10, %xmm13
+        pxor    %xmm9 , %xmm6
+        xorps   %xmm8 , %xmm6
+        pxor    %xmm12, %xmm7
+        xorps   %xmm13, %xmm7
+
+        sub     $128, arg3
+
+        # check if there is another 64B in the buffer to be able to fold
+        jge     _fold_64_B_loop
+        ##################################################################
+
+
+        add     $128, arg2
+        # at this point, the buffer pointer is pointing at the last y Bytes
+        # of the buffer the 64B of folded data is in 4 of the xmm
+        # registers: xmm0, xmm1, xmm2, xmm3
+
+
+        # fold the 8 xmm registers to 1 xmm register with different constants
+
+        movdqa  rk9(%rip), %xmm10
+        movdqa  %xmm0, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm0
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        xorps   %xmm0, %xmm7
+
+        movdqa  rk11(%rip), %xmm10
+        movdqa  %xmm1, %xmm8
+        pclmulqdq        $0x11, %xmm10, %xmm1
+        pclmulqdq        $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        xorps   %xmm1, %xmm7
+
+        movdqa  rk13(%rip), %xmm10
+        movdqa  %xmm2, %xmm8
+        pclmulqdq        $0x11, %xmm10, %xmm2
+        pclmulqdq        $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        pxor    %xmm2, %xmm7
+
+        movdqa  rk15(%rip), %xmm10
+        movdqa  %xmm3, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm3
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        xorps   %xmm3, %xmm7
+
+        movdqa  rk17(%rip), %xmm10
+        movdqa  %xmm4, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm4
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        pxor    %xmm4, %xmm7
+
+        movdqa  rk19(%rip), %xmm10
+        movdqa  %xmm5, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm5
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        xorps   %xmm5, %xmm7
+
+        movdqa  rk1(%rip), %xmm10       #xmm10 has rk1 and rk2
+                                        #imm value of pclmulqdq instruction
+                                        #will determine which constant to use
+        movdqa  %xmm6, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm6
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        pxor    %xmm6, %xmm7
+
+
+        # instead of 64, we add 48 to the loop counter to save 1 instruction
+        # from the loop instead of a cmp instruction, we use the negative
+        # flag with the jl instruction
+        add     $128-16, arg3
+        jl      _final_reduction_for_128
+
+        # now we have 16+y bytes left to reduce. 16 Bytes is in register xmm7
+        # and the rest is in memory. We can fold 16 bytes at a time if y>=16
+        # continue folding 16B at a time
+
+_16B_reduction_loop:
+        movdqa  %xmm7, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm7
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        movdqu  (arg2), %xmm0
+        pshufb  %xmm11, %xmm0
+        pxor    %xmm0 , %xmm7
+        add     $16, arg2
+        sub     $16, arg3
+        # instead of a cmp instruction, we utilize the flags with the
+        # jge instruction equivalent of: cmp arg3, 16-16
+        # check if there is any more 16B in the buffer to be able to fold
+        jge     _16B_reduction_loop
+
+        #now we have 16+z bytes left to reduce, where 0<= z < 16.
+        #first, we reduce the data in the xmm7 register
+
+
+_final_reduction_for_128:
+        # check if any more data to fold. If not, compute the CRC of
+        # the final 128 bits
+        add     $16, arg3
+        je      _128_done
+
+        # here we are getting data that is less than 16 bytes.
+        # since we know that there was data before the pointer, we can
+        # offset the input pointer before the actual point, to receive
+        # exactly 16 bytes. after that the registers need to be adjusted.
+_get_last_two_xmms:
+        movdqa  %xmm7, %xmm2
+
+        movdqu  -16(arg2, arg3), %xmm1
+        pshufb  %xmm11, %xmm1
+
+        # get rid of the extra data that was loaded before
+        # load the shift constant
+        lea     pshufb_shf_table+16(%rip), %rax
+        sub     arg3, %rax
+        movdqu  (%rax), %xmm0
+
+        # shift xmm2 to the left by arg3 bytes
+        pshufb  %xmm0, %xmm2
+
+        # shift xmm7 to the right by 16-arg3 bytes
+        pxor    mask1(%rip), %xmm0
+        pshufb  %xmm0, %xmm7
+        pblendvb        %xmm2, %xmm1    #xmm0 is implicit
+
+        # fold 16 Bytes
+        movdqa  %xmm1, %xmm2
+        movdqa  %xmm7, %xmm8
+        pclmulqdq       $0x11, %xmm10, %xmm7
+        pclmulqdq       $0x0 , %xmm10, %xmm8
+        pxor    %xmm8, %xmm7
+        pxor    %xmm2, %xmm7
+
+_128_done:
+        # compute crc of a 128-bit value
+        movdqa  rk5(%rip), %xmm10       # rk5 and rk6 in xmm10
+        movdqa  %xmm7, %xmm0
+
+        #64b fold
+        pclmulqdq       $0x1, %xmm10, %xmm7
+        pslldq  $8   ,  %xmm0
+        pxor    %xmm0,  %xmm7
+
+        #32b fold
+        movdqa  %xmm7, %xmm0
+
+        pand    mask2(%rip), %xmm0
+
+        psrldq  $12, %xmm7
+        pclmulqdq       $0x10, %xmm10, %xmm7
+        pxor    %xmm0, %xmm7
+
+        #barrett reduction
+_barrett:
+        movdqa  rk7(%rip), %xmm10       # rk7 and rk8 in xmm10
+        movdqa  %xmm7, %xmm0
+        pclmulqdq       $0x01, %xmm10, %xmm7
+        pslldq  $4, %xmm7
+        pclmulqdq       $0x11, %xmm10, %xmm7
+
+        pslldq  $4, %xmm7
+        pxor    %xmm0, %xmm7
+        pextrd  $1, %xmm7, %eax
+
+_cleanup:
+        # scale the result back to 16 bits
+        shr     $16, %eax
+        mov     %rcx, %rsp
+        ret
+
+########################################################################
+
+.align 16
+_less_than_128:
+
+        # check if there is enough buffer to be able to fold 16B at a time
+        cmp     $32, arg3
+        jl      _less_than_32
+        movdqa  SHUF_MASK(%rip), %xmm11
+
+        # now if there is, load the constants
+        movdqa  rk1(%rip), %xmm10       # rk1 and rk2 in xmm10
+
+        movd    arg1_low32, %xmm0       # get the initial crc value
+        pslldq  $12, %xmm0      # align it to its correct place
+        movdqu  (arg2), %xmm7   # load the plaintext
+        pshufb  %xmm11, %xmm7   # byte-reflect the plaintext
+        pxor    %xmm0, %xmm7
+
+
+        # update the buffer pointer
+        add     $16, arg2
+
+        # update the counter. subtract 32 instead of 16 to save one
+        # instruction from the loop
+        sub     $32, arg3
+
+        jmp     _16B_reduction_loop
+
+
+.align 16
+_less_than_32:
+        # mov initial crc to the return value. this is necessary for
+        # zero-length buffers.
+        mov     arg1_low32, %eax
+        test    arg3, arg3
+        je      _cleanup
+
+        movdqa  SHUF_MASK(%rip), %xmm11
+
+        movd    arg1_low32, %xmm0       # get the initial crc value
+        pslldq  $12, %xmm0      # align it to its correct place
+
+        cmp     $16, arg3
+        je      _exact_16_left
+        jl      _less_than_16_left
+
+        movdqu  (arg2), %xmm7   # load the plaintext
+        pshufb  %xmm11, %xmm7   # byte-reflect the plaintext
+        pxor    %xmm0 , %xmm7   # xor the initial crc value
+        add     $16, arg2
+        sub     $16, arg3
+        movdqa  rk1(%rip), %xmm10       # rk1 and rk2 in xmm10
+        jmp     _get_last_two_xmms
+
+
+.align 16
+_less_than_16_left:
+        # use stack space to load data less than 16 bytes, zero-out
+        # the 16B in memory first.
+
+        pxor    %xmm1, %xmm1
+        mov     %rsp, %r11
+        movdqa  %xmm1, (%r11)
+
+        cmp     $4, arg3
+        jl      _only_less_than_4
+
+        # backup the counter value
+        mov     arg3, %r9
+        cmp     $8, arg3
+        jl      _less_than_8_left
+
+        # load 8 Bytes
+        mov     (arg2), %rax
+        mov     %rax, (%r11)
+        add     $8, %r11
+        sub     $8, arg3
+        add     $8, arg2
+_less_than_8_left:
+
+        cmp     $4, arg3
+        jl      _less_than_4_left
+
+        # load 4 Bytes
+        mov     (arg2), %eax
+        mov     %eax, (%r11)
+        add     $4, %r11
+        sub     $4, arg3
+        add     $4, arg2
+_less_than_4_left:
+
+        cmp     $2, arg3
+        jl      _less_than_2_left
+
+        # load 2 Bytes
+        mov     (arg2), %ax
+        mov     %ax, (%r11)
+        add     $2, %r11
+        sub     $2, arg3
+        add     $2, arg2
+_less_than_2_left:
+        cmp     $1, arg3
+        jl      _zero_left
+
+        # load 1 Byte
+        mov     (arg2), %al
+        mov     %al, (%r11)
+_zero_left:
+        movdqa  (%rsp), %xmm7
+        pshufb  %xmm11, %xmm7
+        pxor    %xmm0 , %xmm7   # xor the initial crc value
+
+        # shl r9, 4
+        lea     pshufb_shf_table+16(%rip), %rax
+        sub     %r9, %rax
+        movdqu  (%rax), %xmm0
+        pxor    mask1(%rip), %xmm0
+
+        pshufb  %xmm0, %xmm7
+        jmp     _128_done
+
+.align 16
+_exact_16_left:
+        movdqu  (arg2), %xmm7
+        pshufb  %xmm11, %xmm7
+        pxor    %xmm0 , %xmm7   # xor the initial crc value
+
+        jmp     _128_done
+
+_only_less_than_4:
+        cmp     $3, arg3
+        jl      _only_less_than_3
+
+        # load 3 Bytes
+        mov     (arg2), %al
+        mov     %al, (%r11)
+
+        mov     1(arg2), %al
+        mov     %al, 1(%r11)
+
+        mov     2(arg2), %al
+        mov     %al, 2(%r11)
+
+        movdqa   (%rsp), %xmm7
+        pshufb   %xmm11, %xmm7
+        pxor     %xmm0 , %xmm7  # xor the initial crc value
+
+        psrldq  $5, %xmm7
+
+        jmp     _barrett
+_only_less_than_3:
+        cmp     $2, arg3
+        jl      _only_less_than_2
+
+        # load 2 Bytes
+        mov     (arg2), %al
+        mov     %al, (%r11)
+
+        mov     1(arg2), %al
+        mov     %al, 1(%r11)
+
+        movdqa  (%rsp), %xmm7
+        pshufb  %xmm11, %xmm7
+        pxor    %xmm0 , %xmm7   # xor the initial crc value
+
+        psrldq  $6, %xmm7
+
+        jmp     _barrett
+_only_less_than_2:
+
+        # load 1 Byte
+        mov     (arg2), %al
+        mov     %al, (%r11)
+
+        movdqa  (%rsp), %xmm7
+        pshufb  %xmm11, %xmm7
+        pxor    %xmm0 , %xmm7   # xor the initial crc value
+
+        psrldq  $7, %xmm7
+
+        jmp     _barrett
+
+ENDPROC(crc_t10dif_pcl)
+
+.data
+
+# precomputed constants
+# these constants are precomputed from the poly:
+# 0x8bb70000 (0x8bb7 scaled to 32 bits)
+.align 16
+# Q = 0x18BB70000
+# rk1 = 2^(32*3) mod Q << 32
+# rk2 = 2^(32*5) mod Q << 32
+# rk3 = 2^(32*15) mod Q << 32
+# rk4 = 2^(32*17) mod Q << 32
+# rk5 = 2^(32*3) mod Q << 32
+# rk6 = 2^(32*2) mod Q << 32
+# rk7 = floor(2^64/Q)
+# rk8 = Q
+rk1:
+.quad 0x2d56000000000000
+rk2:
+.quad 0x06df000000000000
+rk3:
+.quad 0x9d9d000000000000
+rk4:
+.quad 0x7cf5000000000000
+rk5:
+.quad 0x2d56000000000000
+rk6:
+.quad 0x1368000000000000
+rk7:
+.quad 0x00000001f65a57f8
+rk8:
+.quad 0x000000018bb70000
+
+rk9:
+.quad 0xceae000000000000
+rk10:
+.quad 0xbfd6000000000000
+rk11:
+.quad 0x1e16000000000000
+rk12:
+.quad 0x713c000000000000
+rk13:
+.quad 0xf7f9000000000000
+rk14:
+.quad 0x80a6000000000000
+rk15:
+.quad 0x044c000000000000
+rk16:
+.quad 0xe658000000000000
+rk17:
+.quad 0xad18000000000000
+rk18:
+.quad 0xa497000000000000
+rk19:
+.quad 0x6ee3000000000000
+rk20:
+.quad 0xe7b5000000000000
+
+
+
+mask1:
+.octa 0x80808080808080808080808080808080
+mask2:
+.octa 0x00000000FFFFFFFFFFFFFFFFFFFFFFFF
+
+SHUF_MASK:
+.octa 0x000102030405060708090A0B0C0D0E0F
+
+pshufb_shf_table:
+# use these values for shift constants for the pshufb instruction
+# different alignments result in values as shown:
+#       DDQ 0x008f8e8d8c8b8a898887868584838281 # shl 15 (16-1) / shr1
+#       DDQ 0x01008f8e8d8c8b8a8988878685848382 # shl 14 (16-3) / shr2
+#       DDQ 0x0201008f8e8d8c8b8a89888786858483 # shl 13 (16-4) / shr3
+#       DDQ 0x030201008f8e8d8c8b8a898887868584 # shl 12 (16-4) / shr4
+#       DDQ 0x04030201008f8e8d8c8b8a8988878685 # shl 11 (16-5) / shr5
+#       DDQ 0x0504030201008f8e8d8c8b8a89888786 # shl 10 (16-6) / shr6
+#       DDQ 0x060504030201008f8e8d8c8b8a898887 # shl 9  (16-7) / shr7
+#       DDQ 0x07060504030201008f8e8d8c8b8a8988 # shl 8  (16-8) / shr8
+#       DDQ 0x0807060504030201008f8e8d8c8b8a89 # shl 7  (16-9) / shr9
+#       DDQ 0x090807060504030201008f8e8d8c8b8a # shl 6  (16-10) / shr10
+#       DDQ 0x0a090807060504030201008f8e8d8c8b # shl 5  (16-11) / shr11
+#       DDQ 0x0b0a090807060504030201008f8e8d8c # shl 4  (16-12) / shr12
+#       DDQ 0x0c0b0a090807060504030201008f8e8d # shl 3  (16-13) / shr13
+#       DDQ 0x0d0c0b0a090807060504030201008f8e # shl 2  (16-14) / shr14
+#       DDQ 0x0e0d0c0b0a090807060504030201008f # shl 1  (16-15) / shr15
+.octa 0x8f8e8d8c8b8a89888786858483828100
+.octa 0x000e0d0c0b0a09080706050403020100
diff --git a/arch/x86/crypto/crct10dif-pclmul_glue.c b/arch/x86/crypto/crct10dif-pclmul_glue.c
new file mode 100644
index 000000000000..7845d7fd54c0
--- /dev/null
+++ b/arch/x86/crypto/crct10dif-pclmul_glue.c
@@ -0,0 +1,151 @@
+/*
+ * Cryptographic API.
+ *
+ * T10 Data Integrity Field CRC16 Crypto Transform using PCLMULQDQ Instructions
+ *
+ * Copyright (C) 2013 Intel Corporation
+ * Author: Tim Chen <tim.c.chen@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/crc-t10dif.h>
+#include <crypto/internal/hash.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <asm/i387.h>
+#include <asm/cpufeature.h>
+#include <asm/cpu_device_id.h>
+
+asmlinkage __u16 crc_t10dif_pcl(__u16 crc, const unsigned char *buf,
+                                size_t len);
+
+struct chksum_desc_ctx {
+        __u16 crc;
+};
+
+/*
+ * Steps through buffer one byte at at time, calculates reflected
+ * crc using table.
+ */
+
+static int chksum_init(struct shash_desc *desc)
+{
+        struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+        ctx->crc = 0;
+
+        return 0;
+}
+
+static int chksum_update(struct shash_desc *desc, const u8 *data,
+                         unsigned int length)
+{
+        struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+        if (irq_fpu_usable()) {
+                kernel_fpu_begin();
+                ctx->crc = crc_t10dif_pcl(ctx->crc, data, length);
+                kernel_fpu_end();
+        } else
+                ctx->crc = crc_t10dif_generic(ctx->crc, data, length);
+        return 0;
+}
+
+static int chksum_final(struct shash_desc *desc, u8 *out)
+{
+        struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+        *(__u16 *)out = ctx->crc;
+        return 0;
+}
+
+static int __chksum_finup(__u16 *crcp, const u8 *data, unsigned int len,
+                        u8 *out)
+{
+        if (irq_fpu_usable()) {
+                kernel_fpu_begin();
+                *(__u16 *)out = crc_t10dif_pcl(*crcp, data, len);
+                kernel_fpu_end();
+        } else
+                *(__u16 *)out = crc_t10dif_generic(*crcp, data, len);
+        return 0;
+}
+
+static int chksum_finup(struct shash_desc *desc, const u8 *data,
+                        unsigned int len, u8 *out)
+{
+        struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+        return __chksum_finup(&ctx->crc, data, len, out);
+}
+
+static int chksum_digest(struct shash_desc *desc, const u8 *data,
+                         unsigned int length, u8 *out)
+{
+        struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
+
+        return __chksum_finup(&ctx->crc, data, length, out);
+}
+
+static struct shash_alg alg = {
+        .digestsize             =       CRC_T10DIF_DIGEST_SIZE,
+        .init           =       chksum_init,
+        .update         =       chksum_update,
+        .final          =       chksum_final,
+        .finup          =       chksum_finup,
+        .digest         =       chksum_digest,
+        .descsize               =       sizeof(struct chksum_desc_ctx),
+        .base                   =       {
+                .cra_name               =       "crct10dif",
+                .cra_driver_name        =       "crct10dif-pclmul",
+                .cra_priority           =       200,
+                .cra_blocksize          =       CRC_T10DIF_BLOCK_SIZE,
+                .cra_module             =       THIS_MODULE,
+        }
+};
+
+static const struct x86_cpu_id crct10dif_cpu_id[] = {
+        X86_FEATURE_MATCH(X86_FEATURE_PCLMULQDQ),
+        {}
+};
+MODULE_DEVICE_TABLE(x86cpu, crct10dif_cpu_id);
+
+static int __init crct10dif_intel_mod_init(void)
+{
+        if (!x86_match_cpu(crct10dif_cpu_id))
+                return -ENODEV;
+
+        return crypto_register_shash(&alg);
+}
+
+static void __exit crct10dif_intel_mod_fini(void)
+{
+        crypto_unregister_shash(&alg);
+}
+
+module_init(crct10dif_intel_mod_init);
+module_exit(crct10dif_intel_mod_fini);
+
+MODULE_AUTHOR("Tim Chen <tim.c.chen@linux.intel.com>");
+MODULE_DESCRIPTION("T10 DIF CRC calculation accelerated with PCLMULQDQ.");
+MODULE_LICENSE("GPL");
+
+MODULE_ALIAS("crct10dif");
+MODULE_ALIAS("crct10dif-pclmul");
diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c
index 597d4da69656..50226c4b86ed 100644
--- a/arch/x86/crypto/sha256_ssse3_glue.c
+++ b/arch/x86/crypto/sha256_ssse3_glue.c
@@ -187,7 +187,36 @@ static int sha256_ssse3_import(struct shash_desc *desc, const void *in)
         return 0;
 }
 
-static struct shash_alg alg = {
+static int sha224_ssse3_init(struct shash_desc *desc)
+{
+        struct sha256_state *sctx = shash_desc_ctx(desc);
+
+        sctx->state[0] = SHA224_H0;
+        sctx->state[1] = SHA224_H1;
+        sctx->state[2] = SHA224_H2;
+        sctx->state[3] = SHA224_H3;
+        sctx->state[4] = SHA224_H4;
+        sctx->state[5] = SHA224_H5;
+        sctx->state[6] = SHA224_H6;
+        sctx->state[7] = SHA224_H7;
+        sctx->count = 0;
+
+        return 0;
+}
+
+static int sha224_ssse3_final(struct shash_desc *desc, u8 *hash)
+{
+        u8 D[SHA256_DIGEST_SIZE];
+
+        sha256_ssse3_final(desc, D);
+
+        memcpy(hash, D, SHA224_DIGEST_SIZE);
+        memset(D, 0, SHA256_DIGEST_SIZE);
+
+        return 0;
+}
+
+static struct shash_alg algs[] = { {
         .digestsize     =       SHA256_DIGEST_SIZE,
         .init           =       sha256_ssse3_init,
         .update         =       sha256_ssse3_update,
@@ -204,7 +233,24 @@ static struct shash_alg alg = {
                 .cra_blocksize  =       SHA256_BLOCK_SIZE,
                 .cra_module     =       THIS_MODULE,
         }
-};
+}, {
+        .digestsize     =       SHA224_DIGEST_SIZE,
+        .init           =       sha224_ssse3_init,
+        .update         =       sha256_ssse3_update,
+        .final          =       sha224_ssse3_final,
+        .export         =       sha256_ssse3_export,
+        .import         =       sha256_ssse3_import,
+        .descsize       =       sizeof(struct sha256_state),
+        .statesize      =       sizeof(struct sha256_state),
+        .base           =       {
+                .cra_name       =       "sha224",
+                .cra_driver_name =      "sha224-ssse3",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA224_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+} };
 
 #ifdef CONFIG_AS_AVX
 static bool __init avx_usable(void)
@@ -227,7 +273,7 @@ static bool __init avx_usable(void)
 
 static int __init sha256_ssse3_mod_init(void)
 {
-        /* test for SSE3 first */
+        /* test for SSSE3 first */
         if (cpu_has_ssse3)
                 sha256_transform_asm = sha256_transform_ssse3;
 
@@ -254,7 +300,7 @@ static int __init sha256_ssse3_mod_init(void)
                 else
 #endif
                         pr_info("Using SSSE3 optimized SHA-256 implementation\n");
-                return crypto_register_shash(&alg);
+                return crypto_register_shashes(algs, ARRAY_SIZE(algs));
         }
         pr_info("Neither AVX nor SSSE3 is available/usable.\n");
 
@@ -263,7 +309,7 @@ static int __init sha256_ssse3_mod_init(void)
 
 static void __exit sha256_ssse3_mod_fini(void)
 {
-        crypto_unregister_shash(&alg);
+        crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 }
 
 module_init(sha256_ssse3_mod_init);
@@ -273,3 +319,4 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
 
 MODULE_ALIAS("sha256");
+MODULE_ALIAS("sha384");
diff --git a/arch/x86/crypto/sha512_ssse3_glue.c b/arch/x86/crypto/sha512_ssse3_glue.c
index 6cbd8df348d2..f30cd10293f0 100644
--- a/arch/x86/crypto/sha512_ssse3_glue.c
+++ b/arch/x86/crypto/sha512_ssse3_glue.c
@@ -194,7 +194,37 @@ static int sha512_ssse3_import(struct shash_desc *desc, const void *in)
         return 0;
 }
 
-static struct shash_alg alg = {
+static int sha384_ssse3_init(struct shash_desc *desc)
+{
+        struct sha512_state *sctx = shash_desc_ctx(desc);
+
+        sctx->state[0] = SHA384_H0;
+        sctx->state[1] = SHA384_H1;
+        sctx->state[2] = SHA384_H2;
+        sctx->state[3] = SHA384_H3;
+        sctx->state[4] = SHA384_H4;
+        sctx->state[5] = SHA384_H5;
+        sctx->state[6] = SHA384_H6;
+        sctx->state[7] = SHA384_H7;
+
+        sctx->count[0] = sctx->count[1] = 0;
+
+        return 0;
+}
+
+static int sha384_ssse3_final(struct shash_desc *desc, u8 *hash)
+{
+        u8 D[SHA512_DIGEST_SIZE];
+
+        sha512_ssse3_final(desc, D);
+
+        memcpy(hash, D, SHA384_DIGEST_SIZE);
+        memset(D, 0, SHA512_DIGEST_SIZE);
+
+        return 0;
+}
+
+static struct shash_alg algs[] = { {
         .digestsize     =       SHA512_DIGEST_SIZE,
         .init           =       sha512_ssse3_init,
         .update         =       sha512_ssse3_update,
@@ -211,7 +241,24 @@ static struct shash_alg alg = {
                 .cra_blocksize  =       SHA512_BLOCK_SIZE,
                 .cra_module     =       THIS_MODULE,
         }
-};
+},  {
+        .digestsize     =       SHA384_DIGEST_SIZE,
+        .init           =       sha384_ssse3_init,
+        .update         =       sha512_ssse3_update,
+        .final          =       sha384_ssse3_final,
+        .export         =       sha512_ssse3_export,
+        .import         =       sha512_ssse3_import,
+        .descsize       =       sizeof(struct sha512_state),
+        .statesize      =       sizeof(struct sha512_state),
+        .base           =       {
+                .cra_name       =       "sha384",
+                .cra_driver_name =      "sha384-ssse3",
+                .cra_priority   =       150,
+                .cra_flags      =       CRYPTO_ALG_TYPE_SHASH,
+                .cra_blocksize  =       SHA384_BLOCK_SIZE,
+                .cra_module     =       THIS_MODULE,
+        }
+} };
 
 #ifdef CONFIG_AS_AVX
 static bool __init avx_usable(void)
@@ -234,7 +281,7 @@ static bool __init avx_usable(void)
 
 static int __init sha512_ssse3_mod_init(void)
 {
-        /* test for SSE3 first */
+        /* test for SSSE3 first */
         if (cpu_has_ssse3)
                 sha512_transform_asm = sha512_transform_ssse3;
 
@@ -261,7 +308,7 @@ static int __init sha512_ssse3_mod_init(void)
                 else
 #endif
                         pr_info("Using SSSE3 optimized SHA-512 implementation\n");
-                return crypto_register_shash(&alg);
+                return crypto_register_shashes(algs, ARRAY_SIZE(algs));
         }
         pr_info("Neither AVX nor SSSE3 is available/usable.\n");
 
@@ -270,7 +317,7 @@ static int __init sha512_ssse3_mod_init(void)
 
 static void __exit sha512_ssse3_mod_fini(void)
 {
-        crypto_unregister_shash(&alg);
+        crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
 }
 
 module_init(sha512_ssse3_mod_init);
@@ -280,3 +327,4 @@ MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("SHA512 Secure Hash Algorithm, Supplemental SSE3 accelerated");
 
 MODULE_ALIAS("sha512");
+MODULE_ALIAS("sha384");
diff --git a/arch/x86/crypto/twofish-avx2-asm_64.S b/arch/x86/crypto/twofish-avx2-asm_64.S
deleted file mode 100644
index e1a83b9cd389..000000000000
--- a/arch/x86/crypto/twofish-avx2-asm_64.S
+++ /dev/null
@@ -1,600 +0,0 @@
-/*
- * x86_64/AVX2 assembler optimized version of Twofish
- *
- * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@iki.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/linkage.h>
-#include "glue_helper-asm-avx2.S"
-
-.file "twofish-avx2-asm_64.S"
-
-.data
-.align 16
-
-.Lvpshufb_mask0:
-.long 0x80808000
-.long 0x80808004
-.long 0x80808008
-.long 0x8080800c
-
-.Lbswap128_mask:
-        .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
-.Lxts_gf128mul_and_shl1_mask_0:
-        .byte 0x87, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0
-.Lxts_gf128mul_and_shl1_mask_1:
-        .byte 0x0e, 1, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0
-
-.text
-
-/* structure of crypto context */
-#define s0      0
-#define s1      1024
-#define s2      2048
-#define s3      3072
-#define w       4096
-#define k       4128
-
-/* register macros */
-#define CTX     %rdi
-
-#define RS0     CTX
-#define RS1     %r8
-#define RS2     %r9
-#define RS3     %r10
-#define RK      %r11
-#define RW      %rax
-#define RROUND  %r12
-#define RROUNDd %r12d
-
-#define RA0     %ymm8
-#define RB0     %ymm9
-#define RC0     %ymm10
-#define RD0     %ymm11
-#define RA1     %ymm12
-#define RB1     %ymm13
-#define RC1     %ymm14
-#define RD1     %ymm15
-
-/* temp regs */
-#define RX0     %ymm0
-#define RY0     %ymm1
-#define RX1     %ymm2
-#define RY1     %ymm3
-#define RT0     %ymm4
-#define RIDX    %ymm5
-
-#define RX0x    %xmm0
-#define RY0x    %xmm1
-#define RX1x    %xmm2
-#define RY1x    %xmm3
-#define RT0x    %xmm4
-
-/* vpgatherdd mask and '-1' */
-#define RNOT    %ymm6
-
-/* byte mask, (-1 >> 24) */
-#define RBYTE   %ymm7
-
-/**********************************************************************
-  16-way AVX2 twofish
- **********************************************************************/
-#define init_round_constants() \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpsrld $24, RNOT, RBYTE; \
-        leaq k(CTX), RK; \
-        leaq w(CTX), RW; \
-        leaq s1(CTX), RS1; \
-        leaq s2(CTX), RS2; \
-        leaq s3(CTX), RS3; \
-
-#define g16(ab, rs0, rs1, rs2, rs3, xy) \
-        vpand RBYTE, ab ## 0, RIDX; \
-        vpgatherdd RNOT, (rs0, RIDX, 4), xy ## 0; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-                \
-                vpand RBYTE, ab ## 1, RIDX; \
-                vpgatherdd RNOT, (rs0, RIDX, 4), xy ## 1; \
-                vpcmpeqd RNOT, RNOT, RNOT; \
-        \
-        vpsrld $8, ab ## 0, RIDX; \
-        vpand RBYTE, RIDX, RIDX; \
-        vpgatherdd RNOT, (rs1, RIDX, 4), RT0; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpxor RT0, xy ## 0, xy ## 0; \
-                \
-                vpsrld $8, ab ## 1, RIDX; \
-                vpand RBYTE, RIDX, RIDX; \
-                vpgatherdd RNOT, (rs1, RIDX, 4), RT0; \
-                vpcmpeqd RNOT, RNOT, RNOT; \
-                vpxor RT0, xy ## 1, xy ## 1; \
-        \
-        vpsrld $16, ab ## 0, RIDX; \
-        vpand RBYTE, RIDX, RIDX; \
-        vpgatherdd RNOT, (rs2, RIDX, 4), RT0; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpxor RT0, xy ## 0, xy ## 0; \
-                \
-                vpsrld $16, ab ## 1, RIDX; \
-                vpand RBYTE, RIDX, RIDX; \
-                vpgatherdd RNOT, (rs2, RIDX, 4), RT0; \
-                vpcmpeqd RNOT, RNOT, RNOT; \
-                vpxor RT0, xy ## 1, xy ## 1; \
-        \
-        vpsrld $24, ab ## 0, RIDX; \
-        vpgatherdd RNOT, (rs3, RIDX, 4), RT0; \
-        vpcmpeqd RNOT, RNOT, RNOT; \
-        vpxor RT0, xy ## 0, xy ## 0; \
-                \
-                vpsrld $24, ab ## 1, RIDX; \
-                vpgatherdd RNOT, (rs3, RIDX, 4), RT0; \
-                vpcmpeqd RNOT, RNOT, RNOT; \
-                vpxor RT0, xy ## 1, xy ## 1;
-
-#define g1_16(a, x) \
-        g16(a, RS0, RS1, RS2, RS3, x);
-
-#define g2_16(b, y) \
-        g16(b, RS1, RS2, RS3, RS0, y);
-
-#define encrypt_round_end16(a, b, c, d, nk) \
-        vpaddd RY0, RX0, RX0; \
-        vpaddd RX0, RY0, RY0; \
-        vpbroadcastd nk(RK,RROUND,8), RT0; \
-        vpaddd RT0, RX0, RX0; \
-        vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
-        vpaddd RT0, RY0, RY0; \
-        \
-        vpxor RY0, d ## 0, d ## 0; \
-        \
-        vpxor RX0, c ## 0, c ## 0; \
-        vpsrld $1, c ## 0, RT0; \
-        vpslld $31, c ## 0, c ## 0; \
-        vpor RT0, c ## 0, c ## 0; \
-        \
-                vpaddd RY1, RX1, RX1; \
-                vpaddd RX1, RY1, RY1; \
-                vpbroadcastd nk(RK,RROUND,8), RT0; \
-                vpaddd RT0, RX1, RX1; \
-                vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
-                vpaddd RT0, RY1, RY1; \
-                \
-                vpxor RY1, d ## 1, d ## 1; \
-                \
-                vpxor RX1, c ## 1, c ## 1; \
-                vpsrld $1, c ## 1, RT0; \
-                vpslld $31, c ## 1, c ## 1; \
-                vpor RT0, c ## 1, c ## 1; \
-
-#define encrypt_round16(a, b, c, d, nk) \
-        g2_16(b, RY); \
-        \
-        vpslld $1, b ## 0, RT0; \
-        vpsrld $31, b ## 0, b ## 0; \
-        vpor RT0, b ## 0, b ## 0; \
-        \
-                vpslld $1, b ## 1, RT0; \
-                vpsrld $31, b ## 1, b ## 1; \
-                vpor RT0, b ## 1, b ## 1; \
-        \
-        g1_16(a, RX); \
-        \
-        encrypt_round_end16(a, b, c, d, nk);
-
-#define encrypt_round_first16(a, b, c, d, nk) \
-        vpslld $1, d ## 0, RT0; \
-        vpsrld $31, d ## 0, d ## 0; \
-        vpor RT0, d ## 0, d ## 0; \
-        \
-                vpslld $1, d ## 1, RT0; \
-                vpsrld $31, d ## 1, d ## 1; \
-                vpor RT0, d ## 1, d ## 1; \
-        \
-        encrypt_round16(a, b, c, d, nk);
-
-#define encrypt_round_last16(a, b, c, d, nk) \
-        g2_16(b, RY); \
-        \
-        g1_16(a, RX); \
-        \
-        encrypt_round_end16(a, b, c, d, nk);
-
-#define decrypt_round_end16(a, b, c, d, nk) \
-        vpaddd RY0, RX0, RX0; \
-        vpaddd RX0, RY0, RY0; \
-        vpbroadcastd nk(RK,RROUND,8), RT0; \
-        vpaddd RT0, RX0, RX0; \
-        vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
-        vpaddd RT0, RY0, RY0; \
-        \
-        vpxor RX0, c ## 0, c ## 0; \
-        \
-        vpxor RY0, d ## 0, d ## 0; \
-        vpsrld $1, d ## 0, RT0; \
-        vpslld $31, d ## 0, d ## 0; \
-        vpor RT0, d ## 0, d ## 0; \
-        \
-                vpaddd RY1, RX1, RX1; \
-                vpaddd RX1, RY1, RY1; \
-                vpbroadcastd nk(RK,RROUND,8), RT0; \
-                vpaddd RT0, RX1, RX1; \
-                vpbroadcastd 4+nk(RK,RROUND,8), RT0; \
-                vpaddd RT0, RY1, RY1; \
-                \
-                vpxor RX1, c ## 1, c ## 1; \
-                \
-                vpxor RY1, d ## 1, d ## 1; \
-                vpsrld $1, d ## 1, RT0; \
-                vpslld $31, d ## 1, d ## 1; \
-                vpor RT0, d ## 1, d ## 1;
-
-#define decrypt_round16(a, b, c, d, nk) \
-        g1_16(a, RX); \
-        \
-        vpslld $1, a ## 0, RT0; \
-        vpsrld $31, a ## 0, a ## 0; \
-        vpor RT0, a ## 0, a ## 0; \
-        \
-                vpslld $1, a ## 1, RT0; \
-                vpsrld $31, a ## 1, a ## 1; \
-                vpor RT0, a ## 1, a ## 1; \
-        \
-        g2_16(b, RY); \
-        \
-        decrypt_round_end16(a, b, c, d, nk);
-
-#define decrypt_round_first16(a, b, c, d, nk) \
-        vpslld $1, c ## 0, RT0; \
-        vpsrld $31, c ## 0, c ## 0; \
-        vpor RT0, c ## 0, c ## 0; \
-        \
-                vpslld $1, c ## 1, RT0; \
-                vpsrld $31, c ## 1, c ## 1; \
-                vpor RT0, c ## 1, c ## 1; \
-        \
-        decrypt_round16(a, b, c, d, nk)
-
-#define decrypt_round_last16(a, b, c, d, nk) \
-        g1_16(a, RX); \
-        \
-        g2_16(b, RY); \
-        \
-        decrypt_round_end16(a, b, c, d, nk);
-
-#define encrypt_cycle16() \
-        encrypt_round16(RA, RB, RC, RD, 0); \
-        encrypt_round16(RC, RD, RA, RB, 8);
-
-#define encrypt_cycle_first16() \
-        encrypt_round_first16(RA, RB, RC, RD, 0); \
-        encrypt_round16(RC, RD, RA, RB, 8);
-
-#define encrypt_cycle_last16() \
-        encrypt_round16(RA, RB, RC, RD, 0); \
-        encrypt_round_last16(RC, RD, RA, RB, 8);
-
-#define decrypt_cycle16(n) \
-        decrypt_round16(RC, RD, RA, RB, 8); \
-        decrypt_round16(RA, RB, RC, RD, 0);
-
-#define decrypt_cycle_first16(n) \
-        decrypt_round_first16(RC, RD, RA, RB, 8); \
-        decrypt_round16(RA, RB, RC, RD, 0);
-
-#define decrypt_cycle_last16(n) \
-        decrypt_round16(RC, RD, RA, RB, 8); \
-        decrypt_round_last16(RA, RB, RC, RD, 0);
-
-#define transpose_4x4(x0,x1,x2,x3,t1,t2) \
-        vpunpckhdq x1, x0, t2; \
-        vpunpckldq x1, x0, x0; \
-        \
-        vpunpckldq x3, x2, t1; \
-        vpunpckhdq x3, x2, x2; \
-        \
-        vpunpckhqdq t1, x0, x1; \
-        vpunpcklqdq t1, x0, x0; \
-        \
-        vpunpckhqdq x2, t2, x3; \
-        vpunpcklqdq x2, t2, x2;
-
-#define read_blocks8(offs,a,b,c,d) \
-        transpose_4x4(a, b, c, d, RX0, RY0);
-
-#define write_blocks8(offs,a,b,c,d) \
-        transpose_4x4(a, b, c, d, RX0, RY0);
-
-#define inpack_enc8(a,b,c,d) \
-        vpbroadcastd 4*0(RW), RT0; \
-        vpxor RT0, a, a; \
-        \
-        vpbroadcastd 4*1(RW), RT0; \
-        vpxor RT0, b, b; \
-        \
-        vpbroadcastd 4*2(RW), RT0; \
-        vpxor RT0, c, c; \
-        \
-        vpbroadcastd 4*3(RW), RT0; \
-        vpxor RT0, d, d;
-
-#define outunpack_enc8(a,b,c,d) \
-        vpbroadcastd 4*4(RW), RX0; \
-        vpbroadcastd 4*5(RW), RY0; \
-        vpxor RX0, c, RX0; \
-        vpxor RY0, d, RY0; \
-        \
-        vpbroadcastd 4*6(RW), RT0; \
-        vpxor RT0, a, c; \
-        vpbroadcastd 4*7(RW), RT0; \
-        vpxor RT0, b, d; \
-        \
-        vmovdqa RX0, a; \
-        vmovdqa RY0, b;
-
-#define inpack_dec8(a,b,c,d) \
-        vpbroadcastd 4*4(RW), RX0; \
-        vpbroadcastd 4*5(RW), RY0; \
-        vpxor RX0, a, RX0; \
-        vpxor RY0, b, RY0; \
-        \
-        vpbroadcastd 4*6(RW), RT0; \
-        vpxor RT0, c, a; \
-        vpbroadcastd 4*7(RW), RT0; \
-        vpxor RT0, d, b; \
-        \
-        vmovdqa RX0, c; \
-        vmovdqa RY0, d;
-
-#define outunpack_dec8(a,b,c,d) \
-        vpbroadcastd 4*0(RW), RT0; \
-        vpxor RT0, a, a; \
-        \
-        vpbroadcastd 4*1(RW), RT0; \
-        vpxor RT0, b, b; \
-        \
-        vpbroadcastd 4*2(RW), RT0; \
-        vpxor RT0, c, c; \
-        \
-        vpbroadcastd 4*3(RW), RT0; \
-        vpxor RT0, d, d;
-
-#define read_blocks16(a,b,c,d) \
-        read_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
-        read_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define write_blocks16(a,b,c,d) \
-        write_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
-        write_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define xor_blocks16(a,b,c,d) \
-        xor_blocks8(0, a ## 0, b ## 0, c ## 0, d ## 0); \
-        xor_blocks8(8, a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define inpack_enc16(a,b,c,d) \
-        inpack_enc8(a ## 0, b ## 0, c ## 0, d ## 0); \
-        inpack_enc8(a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define outunpack_enc16(a,b,c,d) \
-        outunpack_enc8(a ## 0, b ## 0, c ## 0, d ## 0); \
-        outunpack_enc8(a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define inpack_dec16(a,b,c,d) \
-        inpack_dec8(a ## 0, b ## 0, c ## 0, d ## 0); \
-        inpack_dec8(a ## 1, b ## 1, c ## 1, d ## 1);
-
-#define outunpack_dec16(a,b,c,d) \
-        outunpack_dec8(a ## 0, b ## 0, c ## 0, d ## 0); \
-        outunpack_dec8(a ## 1, b ## 1, c ## 1, d ## 1);
-
-.align 8
-__twofish_enc_blk16:
-        /* input:
-         *      %rdi: ctx, CTX
-         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: plaintext
-         * output:
-         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: ciphertext
-         */
-        init_round_constants();
-
-        read_blocks16(RA, RB, RC, RD);
-        inpack_enc16(RA, RB, RC, RD);
-
-        xorl RROUNDd, RROUNDd;
-        encrypt_cycle_first16();
-        movl $2, RROUNDd;
-
-.align 4
-.L__enc_loop:
-        encrypt_cycle16();
-
-        addl $2, RROUNDd;
-        cmpl $14, RROUNDd;
-        jne .L__enc_loop;
-
-        encrypt_cycle_last16();
-
-        outunpack_enc16(RA, RB, RC, RD);
-        write_blocks16(RA, RB, RC, RD);
-
-        ret;
-ENDPROC(__twofish_enc_blk16)
-
-.align 8
-__twofish_dec_blk16:
-        /* input:
-         *      %rdi: ctx, CTX
-         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: ciphertext
-         * output:
-         *      RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1: plaintext
-         */
-        init_round_constants();
-
-        read_blocks16(RA, RB, RC, RD);
-        inpack_dec16(RA, RB, RC, RD);
-
-        movl $14, RROUNDd;
-        decrypt_cycle_first16();
-        movl $12, RROUNDd;
-
-.align 4
-.L__dec_loop:
-        decrypt_cycle16();
-
-        addl $-2, RROUNDd;
-        jnz .L__dec_loop;
-
-        decrypt_cycle_last16();
-
-        outunpack_dec16(RA, RB, RC, RD);
-        write_blocks16(RA, RB, RC, RD);
-
-        ret;
-ENDPROC(__twofish_dec_blk16)
-
-ENTRY(twofish_ecb_enc_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-        pushq %r12;
-
-        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        call __twofish_enc_blk16;
-
-        store_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        popq %r12;
-        vzeroupper;
-
-        ret;
-ENDPROC(twofish_ecb_enc_16way)
-
-ENTRY(twofish_ecb_dec_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-        pushq %r12;
-
-        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        call __twofish_dec_blk16;
-
-        store_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        popq %r12;
-        vzeroupper;
-
-        ret;
-ENDPROC(twofish_ecb_dec_16way)
-
-ENTRY(twofish_cbc_dec_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst
-         *      %rdx: src
-         */
-
-        vzeroupper;
-        pushq %r12;
-
-        load_16way(%rdx, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        call __twofish_dec_blk16;
-
-        store_cbc_16way(%rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1,
-                        RX0);
-
-        popq %r12;
-        vzeroupper;
-
-        ret;
-ENDPROC(twofish_cbc_dec_16way)
-
-ENTRY(twofish_ctr_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst (16 blocks)
-         *      %rdx: src (16 blocks)
-         *      %rcx: iv (little endian, 128bit)
-         */
-
-        vzeroupper;
-        pushq %r12;
-
-        load_ctr_16way(%rcx, .Lbswap128_mask, RA0, RB0, RC0, RD0, RA1, RB1, RC1,
-                       RD1, RX0, RX0x, RX1, RX1x, RY0, RY0x, RY1, RY1x, RNOT,
-                       RBYTE);
-
-        call __twofish_enc_blk16;
-
-        store_ctr_16way(%rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        popq %r12;
-        vzeroupper;
-
-        ret;
-ENDPROC(twofish_ctr_16way)
-
-.align 8
-twofish_xts_crypt_16way:
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst (16 blocks)
-         *      %rdx: src (16 blocks)
-         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
-         *      %r8: pointer to __twofish_enc_blk16 or __twofish_dec_blk16
-         */
-
-        vzeroupper;
-        pushq %r12;
-
-        load_xts_16way(%rcx, %rdx, %rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1,
-                       RD1, RX0, RX0x, RX1, RX1x, RY0, RY0x, RY1, RY1x, RNOT,
-                       .Lxts_gf128mul_and_shl1_mask_0,
-                       .Lxts_gf128mul_and_shl1_mask_1);
-
-        call *%r8;
-
-        store_xts_16way(%rsi, RA0, RB0, RC0, RD0, RA1, RB1, RC1, RD1);
-
-        popq %r12;
-        vzeroupper;
-
-        ret;
-ENDPROC(twofish_xts_crypt_16way)
-
-ENTRY(twofish_xts_enc_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst (16 blocks)
-         *      %rdx: src (16 blocks)
-         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
-         */
-        leaq __twofish_enc_blk16, %r8;
-        jmp twofish_xts_crypt_16way;
-ENDPROC(twofish_xts_enc_16way)
-
-ENTRY(twofish_xts_dec_16way)
-        /* input:
-         *      %rdi: ctx, CTX
-         *      %rsi: dst (16 blocks)
-         *      %rdx: src (16 blocks)
-         *      %rcx: iv (t ⊕ αⁿ ∈ GF(2¹²⁸))
-         */
-        leaq __twofish_dec_blk16, %r8;
-        jmp twofish_xts_crypt_16way;
-ENDPROC(twofish_xts_dec_16way)
diff --git a/arch/x86/crypto/twofish_avx2_glue.c b/arch/x86/crypto/twofish_avx2_glue.c
deleted file mode 100644
index ce33b5be64ee..000000000000
--- a/arch/x86/crypto/twofish_avx2_glue.c
+++ /dev/null
@@ -1,584 +0,0 @@
-/*
- * Glue Code for x86_64/AVX2 assembler optimized version of Twofish
- *
- * Copyright © 2012-2013 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/crypto.h>
-#include <linux/err.h>
-#include <crypto/algapi.h>
-#include <crypto/ctr.h>
-#include <crypto/twofish.h>
-#include <crypto/lrw.h>
-#include <crypto/xts.h>
-#include <asm/xcr.h>
-#include <asm/xsave.h>
-#include <asm/crypto/twofish.h>
-#include <asm/crypto/ablk_helper.h>
-#include <asm/crypto/glue_helper.h>
-#include <crypto/scatterwalk.h>
-
-#define TF_AVX2_PARALLEL_BLOCKS 16
-
-/* 16-way AVX2 parallel cipher functions */
-asmlinkage void twofish_ecb_enc_16way(struct twofish_ctx *ctx, u8 *dst,
-                                      const u8 *src);
-asmlinkage void twofish_ecb_dec_16way(struct twofish_ctx *ctx, u8 *dst,
-                                      const u8 *src);
-asmlinkage void twofish_cbc_dec_16way(void *ctx, u128 *dst, const u128 *src);
-
-asmlinkage void twofish_ctr_16way(void *ctx, u128 *dst, const u128 *src,
-                                  le128 *iv);
-
-asmlinkage void twofish_xts_enc_16way(struct twofish_ctx *ctx, u8 *dst,
-                                      const u8 *src, le128 *iv);
-asmlinkage void twofish_xts_dec_16way(struct twofish_ctx *ctx, u8 *dst,
-                                      const u8 *src, le128 *iv);
-
-static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        __twofish_enc_blk_3way(ctx, dst, src, false);
-}
-
-static const struct common_glue_ctx twofish_enc = {
-        .num_funcs = 4,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_enc_16way) }
-        }, {
-                .num_blocks = 8,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_enc_8way) }
-        }, {
-                .num_blocks = 3,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_3way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk) }
-        } }
-};
-
-static const struct common_glue_ctx twofish_ctr = {
-        .num_funcs = 4,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_ctr_16way) }
-        },  {
-                .num_blocks = 8,
-                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_ctr_8way) }
-        }, {
-                .num_blocks = 3,
-                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr_3way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr) }
-        } }
-};
-
-static const struct common_glue_ctx twofish_enc_xts = {
-        .num_funcs = 3,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc_16way) }
-        }, {
-                .num_blocks = 8,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc_8way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_enc) }
-        } }
-};
-
-static const struct common_glue_ctx twofish_dec = {
-        .num_funcs = 4,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_dec_16way) }
-        }, {
-                .num_blocks = 8,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_ecb_dec_8way) }
-        }, {
-                .num_blocks = 3,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk_3way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk) }
-        } }
-};
-
-static const struct common_glue_ctx twofish_dec_cbc = {
-        .num_funcs = 4,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_cbc_dec_16way) }
-        }, {
-                .num_blocks = 8,
-                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_cbc_dec_8way) }
-        }, {
-                .num_blocks = 3,
-                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk_cbc_3way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk) }
-        } }
-};
-
-static const struct common_glue_ctx twofish_dec_xts = {
-        .num_funcs = 3,
-        .fpu_blocks_limit = 8,
-
-        .funcs = { {
-                .num_blocks = 16,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec_16way) }
-        }, {
-                .num_blocks = 8,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec_8way) }
-        }, {
-                .num_blocks = 1,
-                .fn_u = { .xts = GLUE_XTS_FUNC_CAST(twofish_xts_dec) }
-        } }
-};
-
-static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        return glue_ecb_crypt_128bit(&twofish_enc, desc, dst, src, nbytes);
-}
-
-static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        return glue_ecb_crypt_128bit(&twofish_dec, desc, dst, src, nbytes);
-}
-
-static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(twofish_enc_blk), desc,
-                                       dst, src, nbytes);
-}
-
-static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        return glue_cbc_decrypt_128bit(&twofish_dec_cbc, desc, dst, src,
-                                       nbytes);
-}
-
-static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                     struct scatterlist *src, unsigned int nbytes)
-{
-        return glue_ctr_crypt_128bit(&twofish_ctr, desc, dst, src, nbytes);
-}
-
-static inline bool twofish_fpu_begin(bool fpu_enabled, unsigned int nbytes)
-{
-        /* since reusing AVX functions, starts using FPU at 8 parallel blocks */
-        return glue_fpu_begin(TF_BLOCK_SIZE, 8, NULL, fpu_enabled, nbytes);
-}
-
-static inline void twofish_fpu_end(bool fpu_enabled)
-{
-        glue_fpu_end(fpu_enabled);
-}
-
-struct crypt_priv {
-        struct twofish_ctx *ctx;
-        bool fpu_enabled;
-};
-
-static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
-{
-        const unsigned int bsize = TF_BLOCK_SIZE;
-        struct crypt_priv *ctx = priv;
-        int i;
-
-        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
-
-        while (nbytes >= TF_AVX2_PARALLEL_BLOCKS * bsize) {
-                twofish_ecb_enc_16way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * TF_AVX2_PARALLEL_BLOCKS;
-                nbytes -= bsize * TF_AVX2_PARALLEL_BLOCKS;
-        }
-
-        while (nbytes >= 8 * bsize) {
-                twofish_ecb_enc_8way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * 8;
-                nbytes -= bsize * 8;
-        }
-
-        while (nbytes >= 3 * bsize) {
-                twofish_enc_blk_3way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * 3;
-                nbytes -= bsize * 3;
-        }
-
-        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
-                twofish_enc_blk(ctx->ctx, srcdst, srcdst);
-}
-
-static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
-{
-        const unsigned int bsize = TF_BLOCK_SIZE;
-        struct crypt_priv *ctx = priv;
-        int i;
-
-        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
-
-        while (nbytes >= TF_AVX2_PARALLEL_BLOCKS * bsize) {
-                twofish_ecb_dec_16way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * TF_AVX2_PARALLEL_BLOCKS;
-                nbytes -= bsize * TF_AVX2_PARALLEL_BLOCKS;
-        }
-
-        while (nbytes >= 8 * bsize) {
-                twofish_ecb_dec_8way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * 8;
-                nbytes -= bsize * 8;
-        }
-
-        while (nbytes >= 3 * bsize) {
-                twofish_dec_blk_3way(ctx->ctx, srcdst, srcdst);
-                srcdst += bsize * 3;
-                nbytes -= bsize * 3;
-        }
-
-        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
-                twofish_dec_blk(ctx->ctx, srcdst, srcdst);
-}
-
-static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[TF_AVX2_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->twofish_ctx,
-                .fpu_enabled = false,
-        };
-        struct lrw_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .table_ctx = &ctx->lrw_table,
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = encrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = lrw_crypt(desc, dst, src, nbytes, &req);
-        twofish_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
-}
-
-static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        be128 buf[TF_AVX2_PARALLEL_BLOCKS];
-        struct crypt_priv crypt_ctx = {
-                .ctx = &ctx->twofish_ctx,
-                .fpu_enabled = false,
-        };
-        struct lrw_crypt_req req = {
-                .tbuf = buf,
-                .tbuflen = sizeof(buf),
-
-                .table_ctx = &ctx->lrw_table,
-                .crypt_ctx = &crypt_ctx,
-                .crypt_fn = decrypt_callback,
-        };
-        int ret;
-
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-        ret = lrw_crypt(desc, dst, src, nbytes, &req);
-        twofish_fpu_end(crypt_ctx.fpu_enabled);
-
-        return ret;
-}
-
-static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-
-        return glue_xts_crypt_128bit(&twofish_enc_xts, desc, dst, src, nbytes,
-                                     XTS_TWEAK_CAST(twofish_enc_blk),
-                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
-}
-
-static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-
-        return glue_xts_crypt_128bit(&twofish_dec_xts, desc, dst, src, nbytes,
-                                     XTS_TWEAK_CAST(twofish_enc_blk),
-                                     &ctx->tweak_ctx, &ctx->crypt_ctx);
-}
-
-static struct crypto_alg tf_algs[10] = { {
-        .cra_name               = "__ecb-twofish-avx2",
-        .cra_driver_name        = "__driver-ecb-twofish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct twofish_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .setkey         = twofish_setkey,
-                        .encrypt        = ecb_encrypt,
-                        .decrypt        = ecb_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "__cbc-twofish-avx2",
-        .cra_driver_name        = "__driver-cbc-twofish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct twofish_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .setkey         = twofish_setkey,
-                        .encrypt        = cbc_encrypt,
-                        .decrypt        = cbc_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "__ctr-twofish-avx2",
-        .cra_driver_name        = "__driver-ctr-twofish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct twofish_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = twofish_setkey,
-                        .encrypt        = ctr_crypt,
-                        .decrypt        = ctr_crypt,
-                },
-        },
-}, {
-        .cra_name               = "__lrw-twofish-avx2",
-        .cra_driver_name        = "__driver-lrw-twofish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct twofish_lrw_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_exit               = lrw_twofish_exit_tfm,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE +
-                                          TF_BLOCK_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE +
-                                          TF_BLOCK_SIZE,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = lrw_twofish_setkey,
-                        .encrypt        = lrw_encrypt,
-                        .decrypt        = lrw_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "__xts-twofish-avx2",
-        .cra_driver_name        = "__driver-xts-twofish-avx2",
-        .cra_priority           = 0,
-        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct twofish_xts_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_blkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_u = {
-                .blkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
-                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = xts_twofish_setkey,
-                        .encrypt        = xts_encrypt,
-                        .decrypt        = xts_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "ecb(twofish)",
-        .cra_driver_name        = "ecb-twofish-avx2",
-        .cra_priority           = 500,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "cbc(twofish)",
-        .cra_driver_name        = "cbc-twofish-avx2",
-        .cra_priority           = 500,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = __ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "ctr(twofish)",
-        .cra_driver_name        = "ctr-twofish-avx2",
-        .cra_priority           = 500,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_encrypt,
-                        .geniv          = "chainiv",
-                },
-        },
-}, {
-        .cra_name               = "lrw(twofish)",
-        .cra_driver_name        = "lrw-twofish-avx2",
-        .cra_priority           = 500,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE +
-                                          TF_BLOCK_SIZE,
-                        .max_keysize    = TF_MAX_KEY_SIZE +
-                                          TF_BLOCK_SIZE,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-}, {
-        .cra_name               = "xts(twofish)",
-        .cra_driver_name        = "xts-twofish-avx2",
-        .cra_priority           = 500,
-        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
-        .cra_blocksize          = TF_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_helper_ctx),
-        .cra_alignmask          = 0,
-        .cra_type               = &crypto_ablkcipher_type,
-        .cra_module             = THIS_MODULE,
-        .cra_init               = ablk_init,
-        .cra_exit               = ablk_exit,
-        .cra_u = {
-                .ablkcipher = {
-                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
-                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
-                        .ivsize         = TF_BLOCK_SIZE,
-                        .setkey         = ablk_set_key,
-                        .encrypt        = ablk_encrypt,
-                        .decrypt        = ablk_decrypt,
-                },
-        },
-} };
-
-static int __init init(void)
-{
-        u64 xcr0;
-
-        if (!cpu_has_avx2 || !cpu_has_osxsave) {
-                pr_info("AVX2 instructions are not detected.\n");
-                return -ENODEV;
-        }
-
-        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
-        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
-                pr_info("AVX2 detected but unusable.\n");
-                return -ENODEV;
-        }
-
-        return crypto_register_algs(tf_algs, ARRAY_SIZE(tf_algs));
-}
-
-static void __exit fini(void)
-{
-        crypto_unregister_algs(tf_algs, ARRAY_SIZE(tf_algs));
-}
-
-module_init(init);
-module_exit(fini);
-
-MODULE_LICENSE("GPL");
-MODULE_DESCRIPTION("Twofish Cipher Algorithm, AVX2 optimized");
-MODULE_ALIAS("twofish");
-MODULE_ALIAS("twofish-asm");
diff --git a/arch/x86/crypto/twofish_avx_glue.c b/arch/x86/crypto/twofish_avx_glue.c
index 2047a562f6b3..a62ba541884e 100644
--- a/arch/x86/crypto/twofish_avx_glue.c
+++ b/arch/x86/crypto/twofish_avx_glue.c
@@ -50,26 +50,18 @@
 /* 8-way parallel cipher functions */
 asmlinkage void twofish_ecb_enc_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
-EXPORT_SYMBOL_GPL(twofish_ecb_enc_8way);
-
 asmlinkage void twofish_ecb_dec_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
-EXPORT_SYMBOL_GPL(twofish_ecb_dec_8way);
 
 asmlinkage void twofish_cbc_dec_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
-EXPORT_SYMBOL_GPL(twofish_cbc_dec_8way);
-
 asmlinkage void twofish_ctr_8way(struct twofish_ctx *ctx, u8 *dst,
                                  const u8 *src, le128 *iv);
-EXPORT_SYMBOL_GPL(twofish_ctr_8way);
 
 asmlinkage void twofish_xts_enc_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src, le128 *iv);
-EXPORT_SYMBOL_GPL(twofish_xts_enc_8way);
 asmlinkage void twofish_xts_dec_8way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src, le128 *iv);
-EXPORT_SYMBOL_GPL(twofish_xts_dec_8way);
 
 static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
                                         const u8 *src)
@@ -77,19 +69,17 @@ static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
         __twofish_enc_blk_3way(ctx, dst, src, false);
 }
 
-void twofish_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+static void twofish_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv)
 {
         glue_xts_crypt_128bit_one(ctx, dst, src, iv,
                                   GLUE_FUNC_CAST(twofish_enc_blk));
 }
-EXPORT_SYMBOL_GPL(twofish_xts_enc);
 
-void twofish_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
+static void twofish_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv)
 {
         glue_xts_crypt_128bit_one(ctx, dst, src, iv,
                                   GLUE_FUNC_CAST(twofish_dec_blk));
 }
-EXPORT_SYMBOL_GPL(twofish_xts_dec);
 
 
 static const struct common_glue_ctx twofish_enc = {
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index 805078e08013..52ff81cce008 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -192,7 +192,7 @@ static int aout_core_dump(long signr, struct pt_regs *regs, struct file *file,
         /* struct user */
         DUMP_WRITE(&dump, sizeof(dump));
         /* Now dump all of the user data.  Include malloced stuff as well */
-        DUMP_SEEK(PAGE_SIZE);
+        DUMP_SEEK(PAGE_SIZE - sizeof(dump));
         /* now we start writing out the user space info */
         set_fs(USER_DS);
         /* Dump the data area */
diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c
index cf1a471a18a2..bccfca68430e 100644
--- a/arch/x86/ia32/ia32_signal.c
+++ b/arch/x86/ia32/ia32_signal.c
@@ -34,8 +34,6 @@
 #include <asm/sys_ia32.h>
 #include <asm/smap.h>
 
-#define FIX_EFLAGS      __FIX_EFLAGS
-
 int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
 {
         int err = 0;
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index b31bf97775fc..2dfac58f3b11 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -111,7 +111,7 @@ static inline void acpi_disable_pci(void)
 }
 
 /* Low-level suspend routine. */
-extern int acpi_suspend_lowlevel(void);
+extern int (*acpi_suspend_lowlevel)(void);
 
 /* Physical address to resume after wakeup */
 #define acpi_wakeup_address ((unsigned long)(real_mode_header->wakeup_start))
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 338803422239..f8119b582c3c 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -12,6 +12,7 @@
 #include <asm/fixmap.h>
 #include <asm/mpspec.h>
 #include <asm/msr.h>
+#include <asm/idle.h>
 
 #define ARCH_APICTIMER_STOPS_ON_C3      1
 
@@ -687,5 +688,31 @@ extern int default_check_phys_apicid_present(int phys_apicid);
 #endif
 
 #endif /* CONFIG_X86_LOCAL_APIC */
+extern void irq_enter(void);
+extern void irq_exit(void);
+
+static inline void entering_irq(void)
+{
+        irq_enter();
+        exit_idle();
+}
+
+static inline void entering_ack_irq(void)
+{
+        ack_APIC_irq();
+        entering_irq();
+}
+
+static inline void exiting_irq(void)
+{
+        irq_exit();
+}
+
+static inline void exiting_ack_irq(void)
+{
+        irq_exit();
+        /* Ack only at the end to avoid potential reentry */
+        ack_APIC_irq();
+}
 
 #endif /* _ASM_X86_APIC_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index e99ac27f95b2..47538a61c91b 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -92,7 +92,7 @@
 #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
 #define X86_FEATURE_11AP        (3*32+19) /* "" Bad local APIC aka 11AP */
 #define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
-                                          /* 21 available, was AMD_C1E */
+#define X86_FEATURE_ALWAYS      (3*32+21) /* "" Always-present feature */
 #define X86_FEATURE_XTOPOLOGY   (3*32+22) /* cpu topology enum extensions */
 #define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
@@ -356,15 +356,36 @@ extern const char * const x86_power_flags[32];
 #endif /* CONFIG_X86_64 */
 
 #if __GNUC__ >= 4
+extern void warn_pre_alternatives(void);
+extern bool __static_cpu_has_safe(u16 bit);
+
 /*
  * Static testing of CPU features.  Used the same as boot_cpu_has().
  * These are only valid after alternatives have run, but will statically
  * patch the target code for additional performance.
- *
  */
 static __always_inline __pure bool __static_cpu_has(u16 bit)
 {
 #if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
+
+#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
+                /*
+                 * Catch too early usage of this before alternatives
+                 * have run.
+                 */
+                asm goto("1: jmp %l[t_warn]\n"
+                         "2:\n"
+                         ".section .altinstructions,\"a\"\n"
+                         " .long 1b - .\n"
+                         " .long 0\n"           /* no replacement */
+                         " .word %P0\n"         /* 1: do replace */
+                         " .byte 2b - 1b\n"     /* source len */
+                         " .byte 0\n"           /* replacement len */
+                         ".previous\n"
+                         /* skipping size check since replacement size = 0 */
+                         : : "i" (X86_FEATURE_ALWAYS) : : t_warn);
+#endif
+
                 asm goto("1: jmp %l[t_no]\n"
                          "2:\n"
                          ".section .altinstructions,\"a\"\n"
@@ -379,7 +400,13 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
                 return true;
         t_no:
                 return false;
-#else
+
+#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
+        t_warn:
+                warn_pre_alternatives();
+                return false;
+#endif
+#else /* GCC_VERSION >= 40500 */
                 u8 flag;
                 /* Open-coded due to __stringify() in ALTERNATIVE() */
                 asm volatile("1: movb $0,%0\n"
@@ -411,11 +438,94 @@ static __always_inline __pure bool __static_cpu_has(u16 bit)
                 __static_cpu_has(bit) :                         \
                 boot_cpu_has(bit)                               \
 )
+
+static __always_inline __pure bool _static_cpu_has_safe(u16 bit)
+{
+#if __GNUC__ > 4 || __GNUC_MINOR__ >= 5
+/*
+ * We need to spell the jumps to the compiler because, depending on the offset,
+ * the replacement jump can be bigger than the original jump, and this we cannot
+ * have. Thus, we force the jump to the widest, 4-byte, signed relative
+ * offset even though the last would often fit in less bytes.
+ */
+                asm goto("1: .byte 0xe9\n .long %l[t_dynamic] - 2f\n"
+                         "2:\n"
+                         ".section .altinstructions,\"a\"\n"
+                         " .long 1b - .\n"              /* src offset */
+                         " .long 3f - .\n"              /* repl offset */
+                         " .word %P1\n"                 /* always replace */
+                         " .byte 2b - 1b\n"             /* src len */
+                         " .byte 4f - 3f\n"             /* repl len */
+                         ".previous\n"
+                         ".section .altinstr_replacement,\"ax\"\n"
+                         "3: .byte 0xe9\n .long %l[t_no] - 2b\n"
+                         "4:\n"
+                         ".previous\n"
+                         ".section .altinstructions,\"a\"\n"
+                         " .long 1b - .\n"              /* src offset */
+                         " .long 0\n"                   /* no replacement */
+                         " .word %P0\n"                 /* feature bit */
+                         " .byte 2b - 1b\n"             /* src len */
+                         " .byte 0\n"                   /* repl len */
+                         ".previous\n"
+                         : : "i" (bit), "i" (X86_FEATURE_ALWAYS)
+                         : : t_dynamic, t_no);
+                return true;
+        t_no:
+                return false;
+        t_dynamic:
+                return __static_cpu_has_safe(bit);
+#else /* GCC_VERSION >= 40500 */
+                u8 flag;
+                /* Open-coded due to __stringify() in ALTERNATIVE() */
+                asm volatile("1: movb $2,%0\n"
+                             "2:\n"
+                             ".section .altinstructions,\"a\"\n"
+                             " .long 1b - .\n"          /* src offset */
+                             " .long 3f - .\n"          /* repl offset */
+                             " .word %P2\n"             /* always replace */
+                             " .byte 2b - 1b\n"         /* source len */
+                             " .byte 4f - 3f\n"         /* replacement len */
+                             ".previous\n"
+                             ".section .discard,\"aw\",@progbits\n"
+                             " .byte 0xff + (4f-3f) - (2b-1b)\n" /* size check */
+                             ".previous\n"
+                             ".section .altinstr_replacement,\"ax\"\n"
+                             "3: movb $0,%0\n"
+                             "4:\n"
+                             ".previous\n"
+                             ".section .altinstructions,\"a\"\n"
+                             " .long 1b - .\n"          /* src offset */
+                             " .long 5f - .\n"          /* repl offset */
+                             " .word %P1\n"             /* feature bit */
+                             " .byte 4b - 3b\n"         /* src len */
+                             " .byte 6f - 5f\n"         /* repl len */
+                             ".previous\n"
+                             ".section .discard,\"aw\",@progbits\n"
+                             " .byte 0xff + (6f-5f) - (4b-3b)\n" /* size check */
+                             ".previous\n"
+                             ".section .altinstr_replacement,\"ax\"\n"
+                             "5: movb $1,%0\n"
+                             "6:\n"
+                             ".previous\n"
+                             : "=qm" (flag)
+                             : "i" (bit), "i" (X86_FEATURE_ALWAYS));
+                return (flag == 2 ? __static_cpu_has_safe(bit) : flag);
+#endif
+}
+
+#define static_cpu_has_safe(bit)                                \
+(                                                               \
+        __builtin_constant_p(boot_cpu_has(bit)) ?               \
+                boot_cpu_has(bit) :                             \
+                _static_cpu_has_safe(bit)                       \
+)
 #else
 /*
  * gcc 3.x is too stupid to do the static test; fall back to dynamic.
  */
-#define static_cpu_has(bit) boot_cpu_has(bit)
+#define static_cpu_has(bit)             boot_cpu_has(bit)
+#define static_cpu_has_safe(bit)        boot_cpu_has(bit)
 #endif
 
 #define cpu_has_bug(c, bit)     cpu_has(c, (bit))
diff --git a/arch/x86/include/asm/crypto/blowfish.h b/arch/x86/include/asm/crypto/blowfish.h
deleted file mode 100644
index f097b2face10..000000000000
--- a/arch/x86/include/asm/crypto/blowfish.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef ASM_X86_BLOWFISH_H
-#define ASM_X86_BLOWFISH_H
-
-#include <linux/crypto.h>
-#include <crypto/blowfish.h>
-
-#define BF_PARALLEL_BLOCKS 4
-
-/* regular block cipher functions */
-asmlinkage void __blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src,
-                                   bool xor);
-asmlinkage void blowfish_dec_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src);
-
-/* 4-way parallel cipher functions */
-asmlinkage void __blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
-                                        const u8 *src, bool xor);
-asmlinkage void blowfish_dec_blk_4way(struct bf_ctx *ctx, u8 *dst,
-                                      const u8 *src);
-
-static inline void blowfish_enc_blk(struct bf_ctx *ctx, u8 *dst, const u8 *src)
-{
-        __blowfish_enc_blk(ctx, dst, src, false);
-}
-
-static inline void blowfish_enc_blk_xor(struct bf_ctx *ctx, u8 *dst,
-                                        const u8 *src)
-{
-        __blowfish_enc_blk(ctx, dst, src, true);
-}
-
-static inline void blowfish_enc_blk_4way(struct bf_ctx *ctx, u8 *dst,
-                                         const u8 *src)
-{
-        __blowfish_enc_blk_4way(ctx, dst, src, false);
-}
-
-static inline void blowfish_enc_blk_xor_4way(struct bf_ctx *ctx, u8 *dst,
-                                      const u8 *src)
-{
-        __blowfish_enc_blk_4way(ctx, dst, src, true);
-}
-
-#endif
diff --git a/arch/x86/include/asm/crypto/twofish.h b/arch/x86/include/asm/crypto/twofish.h
index e655c6029b45..878c51ceebb5 100644
--- a/arch/x86/include/asm/crypto/twofish.h
+++ b/arch/x86/include/asm/crypto/twofish.h
@@ -28,20 +28,6 @@ asmlinkage void __twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
 asmlinkage void twofish_dec_blk_3way(struct twofish_ctx *ctx, u8 *dst,
                                      const u8 *src);
 
-/* 8-way parallel cipher functions */
-asmlinkage void twofish_ecb_enc_8way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-asmlinkage void twofish_ecb_dec_8way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-asmlinkage void twofish_cbc_dec_8way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src);
-asmlinkage void twofish_ctr_8way(struct twofish_ctx *ctx, u8 *dst,
-                                 const u8 *src, le128 *iv);
-asmlinkage void twofish_xts_enc_8way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src, le128 *iv);
-asmlinkage void twofish_xts_dec_8way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src, le128 *iv);
-
 /* helpers from twofish_x86_64-3way module */
 extern void twofish_dec_blk_cbc_3way(void *ctx, u128 *dst, const u128 *src);
 extern void twofish_enc_blk_ctr(void *ctx, u128 *dst, const u128 *src,
@@ -57,8 +43,4 @@ extern void lrw_twofish_exit_tfm(struct crypto_tfm *tfm);
 extern int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
                               unsigned int keylen);
 
-/* helpers from twofish-avx module */
-extern void twofish_xts_enc(void *ctx, u128 *dst, const u128 *src, le128 *iv);
-extern void twofish_xts_dec(void *ctx, u128 *dst, const u128 *src, le128 *iv);
-
 #endif /* ASM_X86_TWOFISH_H */
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 8bf1c06070d5..b90e5dfeee46 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -36,8 +36,8 @@ static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *in
 
 extern struct desc_ptr idt_descr;
 extern gate_desc idt_table[];
-extern struct desc_ptr nmi_idt_descr;
-extern gate_desc nmi_idt_table[];
+extern struct desc_ptr debug_idt_descr;
+extern gate_desc debug_idt_table[];
 
 struct gdt_page {
         struct desc_struct gdt[GDT_ENTRIES];
@@ -316,7 +316,20 @@ static inline void set_nmi_gate(int gate, void *addr)
         gate_desc s;
 
         pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
-        write_idt_entry(nmi_idt_table, gate, &s);
+        write_idt_entry(debug_idt_table, gate, &s);
+}
+#endif
+
+#ifdef CONFIG_TRACING
+extern struct desc_ptr trace_idt_descr;
+extern gate_desc trace_idt_table[];
+static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
+{
+        write_idt_entry(trace_idt_table, entry, gate);
+}
+#else
+static inline void write_trace_idt_entry(int entry, const gate_desc *gate)
+{
 }
 #endif
 
@@ -331,6 +344,7 @@ static inline void _set_gate(int gate, unsigned type, void *addr,
          * setup time
          */
         write_idt_entry(idt_table, gate, &s);
+        write_trace_idt_entry(gate, &s);
 }
 
 /*
@@ -360,12 +374,39 @@ static inline void alloc_system_vector(int vector)
         }
 }
 
-static inline void alloc_intr_gate(unsigned int n, void *addr)
+#ifdef CONFIG_TRACING
+static inline void trace_set_intr_gate(unsigned int gate, void *addr)
+{
+        gate_desc s;
+
+        pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
+        write_idt_entry(trace_idt_table, gate, &s);
+}
+
+static inline void __trace_alloc_intr_gate(unsigned int n, void *addr)
+{
+        trace_set_intr_gate(n, addr);
+}
+#else
+static inline void trace_set_intr_gate(unsigned int gate, void *addr)
+{
+}
+
+#define __trace_alloc_intr_gate(n, addr)
+#endif
+
+static inline void __alloc_intr_gate(unsigned int n, void *addr)
 {
-        alloc_system_vector(n);
         set_intr_gate(n, addr);
 }
 
+#define alloc_intr_gate(n, addr)                                \
+        do {                                                    \
+                alloc_system_vector(n);                         \
+                __alloc_intr_gate(n, addr);                     \
+                __trace_alloc_intr_gate(n, trace_##addr);       \
+        } while (0)
+
 /*
  * This routine sets up an interrupt gate at directory privilege level 3.
  */
@@ -405,4 +446,70 @@ static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
 }
 
+#ifdef CONFIG_X86_64
+DECLARE_PER_CPU(u32, debug_idt_ctr);
+static inline bool is_debug_idt_enabled(void)
+{
+        if (this_cpu_read(debug_idt_ctr))
+                return true;
+
+        return false;
+}
+
+static inline void load_debug_idt(void)
+{
+        load_idt((const struct desc_ptr *)&debug_idt_descr);
+}
+#else
+static inline bool is_debug_idt_enabled(void)
+{
+        return false;
+}
+
+static inline void load_debug_idt(void)
+{
+}
+#endif
+
+#ifdef CONFIG_TRACING
+extern atomic_t trace_idt_ctr;
+static inline bool is_trace_idt_enabled(void)
+{
+        if (atomic_read(&trace_idt_ctr))
+                return true;
+
+        return false;
+}
+
+static inline void load_trace_idt(void)
+{
+        load_idt((const struct desc_ptr *)&trace_idt_descr);
+}
+#else
+static inline bool is_trace_idt_enabled(void)
+{
+        return false;
+}
+
+static inline void load_trace_idt(void)
+{
+}
+#endif
+
+/*
+ * The load_current_idt() must be called with interrupts disabled
+ * to avoid races. That way the IDT will always be set back to the expected
+ * descriptor. It's also called when a CPU is being initialized, and
+ * that doesn't need to disable interrupts, as nothing should be
+ * bothering the CPU then.
+ */
+static inline void load_current_idt(void)
+{
+        if (is_debug_idt_enabled())
+                load_debug_idt();
+        else if (is_trace_idt_enabled())
+                load_trace_idt();
+        else
+                load_idt((const struct desc_ptr *)&idt_descr);
+}
 #endif /* _ASM_X86_DESC_H */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 2fb5d5884e23..0062a0125041 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -52,40 +52,40 @@ extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3,
                      u64 arg4, u64 arg5, u64 arg6);
 
 #define efi_call_phys0(f)                       \
-        efi_call0((void *)(f))
+        efi_call0((f))
 #define efi_call_phys1(f, a1)                   \
-        efi_call1((void *)(f), (u64)(a1))
+        efi_call1((f), (u64)(a1))
 #define efi_call_phys2(f, a1, a2)                       \
-        efi_call2((void *)(f), (u64)(a1), (u64)(a2))
+        efi_call2((f), (u64)(a1), (u64)(a2))
 #define efi_call_phys3(f, a1, a2, a3)                           \
-        efi_call3((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3))
+        efi_call3((f), (u64)(a1), (u64)(a2), (u64)(a3))
 #define efi_call_phys4(f, a1, a2, a3, a4)                               \
-        efi_call4((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),         \
+        efi_call4((f), (u64)(a1), (u64)(a2), (u64)(a3),         \
                   (u64)(a4))
 #define efi_call_phys5(f, a1, a2, a3, a4, a5)                           \
-        efi_call5((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),         \
+        efi_call5((f), (u64)(a1), (u64)(a2), (u64)(a3),         \
                   (u64)(a4), (u64)(a5))
 #define efi_call_phys6(f, a1, a2, a3, a4, a5, a6)                       \
-        efi_call6((void *)(f), (u64)(a1), (u64)(a2), (u64)(a3),         \
+        efi_call6((f), (u64)(a1), (u64)(a2), (u64)(a3),         \
                   (u64)(a4), (u64)(a5), (u64)(a6))
 
 #define efi_call_virt0(f)                               \
-        efi_call0((void *)(efi.systab->runtime->f))
+        efi_call0((efi.systab->runtime->f))
 #define efi_call_virt1(f, a1)                                   \
-        efi_call1((void *)(efi.systab->runtime->f), (u64)(a1))
+        efi_call1((efi.systab->runtime->f), (u64)(a1))
 #define efi_call_virt2(f, a1, a2)                                       \
-        efi_call2((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2))
+        efi_call2((efi.systab->runtime->f), (u64)(a1), (u64)(a2))
 #define efi_call_virt3(f, a1, a2, a3)                                   \
-        efi_call3((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
+        efi_call3((efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
                   (u64)(a3))
 #define efi_call_virt4(f, a1, a2, a3, a4)                               \
-        efi_call4((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
+        efi_call4((efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
                   (u64)(a3), (u64)(a4))
 #define efi_call_virt5(f, a1, a2, a3, a4, a5)                           \
-        efi_call5((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
+        efi_call5((efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
                   (u64)(a3), (u64)(a4), (u64)(a5))
 #define efi_call_virt6(f, a1, a2, a3, a4, a5, a6)                       \
-        efi_call6((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
+        efi_call6((efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
                   (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6))
 
 extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size,
@@ -102,13 +102,6 @@ extern void efi_call_phys_epilog(void);
 extern void efi_unmap_memmap(void);
 extern void efi_memory_uc(u64 addr, unsigned long size);
 
-struct efi_var_bootdata {
-        struct setup_data data;
-        u64 store_size;
-        u64 remaining_size;
-        u64 max_var_size;
-};
-
 #ifdef CONFIG_EFI
 
 static inline bool efi_is_native(void)
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 9bd4ecac72be..dc5fa661465f 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -13,14 +13,16 @@
 BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
 BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
 BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
-BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
-BUILD_INTERRUPT(reboot_interrupt,REBOOT_VECTOR)
+BUILD_INTERRUPT3(irq_move_cleanup_interrupt, IRQ_MOVE_CLEANUP_VECTOR,
+                 smp_irq_move_cleanup_interrupt)
+BUILD_INTERRUPT3(reboot_interrupt, REBOOT_VECTOR, smp_reboot_interrupt)
 #endif
 
 BUILD_INTERRUPT(x86_platform_ipi, X86_PLATFORM_IPI_VECTOR)
 
 #ifdef CONFIG_HAVE_KVM
-BUILD_INTERRUPT(kvm_posted_intr_ipi, POSTED_INTR_VECTOR)
+BUILD_INTERRUPT3(kvm_posted_intr_ipi, POSTED_INTR_VECTOR,
+                 smp_kvm_posted_intr_ipi)
 #endif
 
 /*
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 0dc7d9e21c34..e846225265ed 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -81,11 +81,11 @@ enum fixed_addresses {
                             + ((VSYSCALL_END-VSYSCALL_START) >> PAGE_SHIFT) - 1,
         VVAR_PAGE,
         VSYSCALL_HPET,
-#endif
 #ifdef CONFIG_PARAVIRT_CLOCK
         PVCLOCK_FIXMAP_BEGIN,
         PVCLOCK_FIXMAP_END = PVCLOCK_FIXMAP_BEGIN+PVCLOCK_VSYSCALL_NR_PAGES-1,
 #endif
+#endif
         FIX_DBGP_BASE,
         FIX_EARLYCON_MEM_BASE,
 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
diff --git a/arch/x86/include/asm/fpu-internal.h b/arch/x86/include/asm/fpu-internal.h
index e25cc33ec54d..4d0bda7b11e3 100644
--- a/arch/x86/include/asm/fpu-internal.h
+++ b/arch/x86/include/asm/fpu-internal.h
@@ -62,10 +62,8 @@ extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
 #define xstateregs_active       fpregs_active
 
 #ifdef CONFIG_MATH_EMULATION
-# define HAVE_HWFP              (boot_cpu_data.hard_math)
 extern void finit_soft_fpu(struct i387_soft_struct *soft);
 #else
-# define HAVE_HWFP              1
 static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
 #endif
 
@@ -345,7 +343,7 @@ static inline void __thread_fpu_end(struct task_struct *tsk)
 
 static inline void __thread_fpu_begin(struct task_struct *tsk)
 {
-        if (!use_eager_fpu())
+        if (!static_cpu_has_safe(X86_FEATURE_EAGER_FPU))
                 clts();
         __thread_set_has_fpu(tsk);
 }
diff --git a/arch/x86/include/asm/hw_irq.h b/arch/x86/include/asm/hw_irq.h
index 1da97efad08a..e4ac559c4a24 100644
--- a/arch/x86/include/asm/hw_irq.h
+++ b/arch/x86/include/asm/hw_irq.h
@@ -77,6 +77,23 @@ extern void threshold_interrupt(void);
 extern void call_function_interrupt(void);
 extern void call_function_single_interrupt(void);
 
+#ifdef CONFIG_TRACING
+/* Interrupt handlers registered during init_IRQ */
+extern void trace_apic_timer_interrupt(void);
+extern void trace_x86_platform_ipi(void);
+extern void trace_error_interrupt(void);
+extern void trace_irq_work_interrupt(void);
+extern void trace_spurious_interrupt(void);
+extern void trace_thermal_interrupt(void);
+extern void trace_reschedule_interrupt(void);
+extern void trace_threshold_interrupt(void);
+extern void trace_call_function_interrupt(void);
+extern void trace_call_function_single_interrupt(void);
+#define trace_irq_move_cleanup_interrupt  irq_move_cleanup_interrupt
+#define trace_reboot_interrupt  reboot_interrupt
+#define trace_kvm_posted_intr_ipi kvm_posted_intr_ipi
+#endif /* CONFIG_TRACING */
+
 /* IOAPIC */
 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
 extern unsigned long io_apic_irqs;
diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h
index ba870bb6dd8e..57873beb3292 100644
--- a/arch/x86/include/asm/irq.h
+++ b/arch/x86/include/asm/irq.h
@@ -41,4 +41,9 @@ extern int vector_used_by_percpu_irq(unsigned int vector);
 
 extern void init_ISA_irqs(void);
 
+#ifdef CONFIG_X86_LOCAL_APIC
+void arch_trigger_all_cpu_backtrace(void);
+#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
+#endif
+
 #endif /* _ASM_X86_IRQ_H */
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index 3741c653767c..f87f7fcefa0a 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -59,7 +59,7 @@
         (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
                           | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
                           | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
-                          | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
+                          | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \
                           | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 
 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
@@ -222,14 +222,22 @@ struct kvm_mmu_page {
         int root_count;          /* Currently serving as active root */
         unsigned int unsync_children;
         unsigned long parent_ptes;      /* Reverse mapping for parent_pte */
+
+        /* The page is obsolete if mmu_valid_gen != kvm->arch.mmu_valid_gen.  */
+        unsigned long mmu_valid_gen;
+
         DECLARE_BITMAP(unsync_child_bitmap, 512);
 
 #ifdef CONFIG_X86_32
+        /*
+         * Used out of the mmu-lock to avoid reading spte values while an
+         * update is in progress; see the comments in __get_spte_lockless().
+         */
         int clear_spte_count;
 #endif
 
+        /* Number of writes since the last time traversal visited this page.  */
         int write_flooding_count;
-        bool mmio_cached;
 };
 
 struct kvm_pio_request {
@@ -529,11 +537,14 @@ struct kvm_arch {
         unsigned int n_requested_mmu_pages;
         unsigned int n_max_mmu_pages;
         unsigned int indirect_shadow_pages;
+        unsigned long mmu_valid_gen;
         struct hlist_head mmu_page_hash[KVM_NUM_MMU_PAGES];
         /*
          * Hash table of struct kvm_mmu_page.
          */
         struct list_head active_mmu_pages;
+        struct list_head zapped_obsolete_pages;
+
         struct list_head assigned_dev_head;
         struct iommu_domain *iommu_domain;
         int iommu_flags;
@@ -769,7 +780,7 @@ void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
                                      struct kvm_memory_slot *slot,
                                      gfn_t gfn_offset, unsigned long mask);
 void kvm_mmu_zap_all(struct kvm *kvm);
-void kvm_mmu_zap_mmio_sptes(struct kvm *kvm);
+void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm);
 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm);
 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages);
 
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index fa5f71e021d5..6b52980c29c1 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -61,7 +61,7 @@
 #define MCJ_CTX_IRQ             0x2  /* inject context: IRQ */
 #define MCJ_NMI_BROADCAST       0x4  /* do NMI broadcasting */
 #define MCJ_EXCEPTION           0x8  /* raise as exception */
-#define MCJ_IRQ_BRAODCAST       0x10 /* do IRQ broadcasting */
+#define MCJ_IRQ_BROADCAST       0x10 /* do IRQ broadcasting */
 
 #define MCE_OVERFLOW 0          /* bit 0 in flags means overflow */
 
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 6825e2efd1b4..6bc3985ee473 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -60,11 +60,11 @@ static inline void __exit exit_amd_microcode(void) {}
 #ifdef CONFIG_MICROCODE_EARLY
 #define MAX_UCODE_COUNT 128
 extern void __init load_ucode_bsp(void);
-extern __init void load_ucode_ap(void);
+extern void __cpuinit load_ucode_ap(void);
 extern int __init save_microcode_in_initrd(void);
 #else
 static inline void __init load_ucode_bsp(void) {}
-static inline __init void load_ucode_ap(void) {}
+static inline void __cpuinit load_ucode_ap(void) {}
 static inline int __init save_microcode_in_initrd(void)
 {
         return 0;
diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h
new file mode 100644
index 000000000000..c6b043f40271
--- /dev/null
+++ b/arch/x86/include/asm/microcode_amd.h
@@ -0,0 +1,78 @@
+#ifndef _ASM_X86_MICROCODE_AMD_H
+#define _ASM_X86_MICROCODE_AMD_H
+
+#include <asm/microcode.h>
+
+#define UCODE_MAGIC                     0x00414d44
+#define UCODE_EQUIV_CPU_TABLE_TYPE      0x00000000
+#define UCODE_UCODE_TYPE                0x00000001
+
+#define SECTION_HDR_SIZE                8
+#define CONTAINER_HDR_SZ                12
+
+struct equiv_cpu_entry {
+        u32     installed_cpu;
+        u32     fixed_errata_mask;
+        u32     fixed_errata_compare;
+        u16     equiv_cpu;
+        u16     res;
+} __attribute__((packed));
+
+struct microcode_header_amd {
+        u32     data_code;
+        u32     patch_id;
+        u16     mc_patch_data_id;
+        u8      mc_patch_data_len;
+        u8      init_flag;
+        u32     mc_patch_data_checksum;
+        u32     nb_dev_id;
+        u32     sb_dev_id;
+        u16     processor_rev_id;
+        u8      nb_rev_id;
+        u8      sb_rev_id;
+        u8      bios_api_rev;
+        u8      reserved1[3];
+        u32     match_reg[8];
+} __attribute__((packed));
+
+struct microcode_amd {
+        struct microcode_header_amd     hdr;
+        unsigned int                    mpb[0];
+};
+
+static inline u16 find_equiv_id(struct equiv_cpu_entry *equiv_cpu_table,
+                                unsigned int sig)
+{
+        int i = 0;
+
+        if (!equiv_cpu_table)
+                return 0;
+
+        while (equiv_cpu_table[i].installed_cpu != 0) {
+                if (sig == equiv_cpu_table[i].installed_cpu)
+                        return equiv_cpu_table[i].equiv_cpu;
+
+                i++;
+        }
+        return 0;
+}
+
+extern int __apply_microcode_amd(struct microcode_amd *mc_amd);
+extern int apply_microcode_amd(int cpu);
+extern enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size);
+
+#ifdef CONFIG_MICROCODE_AMD_EARLY
+#ifdef CONFIG_X86_32
+#define MPB_MAX_SIZE PAGE_SIZE
+extern u8 amd_bsp_mpb[MPB_MAX_SIZE];
+#endif
+extern void __init load_ucode_amd_bsp(void);
+extern void __cpuinit load_ucode_amd_ap(void);
+extern int __init save_microcode_in_initrd_amd(void);
+#else
+static inline void __init load_ucode_amd_bsp(void) {}
+static inline void __cpuinit load_ucode_amd_ap(void) {}
+static inline int __init save_microcode_in_initrd_amd(void) { return -EINVAL; }
+#endif
+
+#endif /* _ASM_X86_MICROCODE_AMD_H */
diff --git a/arch/x86/include/asm/microcode_intel.h b/arch/x86/include/asm/microcode_intel.h
index 5356f927d411..87a085333cbf 100644
--- a/arch/x86/include/asm/microcode_intel.h
+++ b/arch/x86/include/asm/microcode_intel.h
@@ -67,10 +67,12 @@ update_match_revision(struct microcode_header_intel *mc_header, int rev);
 extern void __init load_ucode_intel_bsp(void);
 extern void __cpuinit load_ucode_intel_ap(void);
 extern void show_ucode_info_early(void);
+extern int __init save_microcode_in_initrd_intel(void);
 #else
 static inline __init void load_ucode_intel_bsp(void) {}
 static inline __cpuinit void load_ucode_intel_ap(void) {}
 static inline void show_ucode_info_early(void) {}
+static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; }
 #endif
 
 #if defined(CONFIG_MICROCODE_INTEL_EARLY) && defined(CONFIG_HOTPLUG_CPU)
diff --git a/arch/x86/include/asm/mshyperv.h b/arch/x86/include/asm/mshyperv.h
index c2934be2446a..cd9c41938b8a 100644
--- a/arch/x86/include/asm/mshyperv.h
+++ b/arch/x86/include/asm/mshyperv.h
@@ -12,6 +12,9 @@ struct ms_hyperv_info {
 extern struct ms_hyperv_info ms_hyperv;
 
 void hyperv_callback_vector(void);
+#ifdef CONFIG_TRACING
+#define trace_hyperv_callback_vector hyperv_callback_vector
+#endif
 void hyperv_vector_handler(struct pt_regs *regs);
 void hv_register_vmbus_handler(int irq, irq_handler_t handler);
 
diff --git a/arch/x86/include/asm/mutex_32.h b/arch/x86/include/asm/mutex_32.h
index 03f90c8a5a7c..0208c3c2cbc6 100644
--- a/arch/x86/include/asm/mutex_32.h
+++ b/arch/x86/include/asm/mutex_32.h
@@ -42,17 +42,14 @@ do {								\
  *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
  *                                 from 1 to a 0 value
  *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
  *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if it
- * wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns
+ * Change the count from 1 to a value lower than 1. This function returns 0
+ * if the fastpath succeeds, or -1 otherwise.
  */
-static inline int __mutex_fastpath_lock_retval(atomic_t *count,
-                                               int (*fail_fn)(atomic_t *))
+static inline int __mutex_fastpath_lock_retval(atomic_t *count)
 {
         if (unlikely(atomic_dec_return(count) < 0))
-                return fail_fn(count);
+                return -1;
         else
                 return 0;
 }
diff --git a/arch/x86/include/asm/mutex_64.h b/arch/x86/include/asm/mutex_64.h
index 68a87b0f8e29..2c543fff241b 100644
--- a/arch/x86/include/asm/mutex_64.h
+++ b/arch/x86/include/asm/mutex_64.h
@@ -37,17 +37,14 @@ do {								\
  *  __mutex_fastpath_lock_retval - try to take the lock by moving the count
  *                                 from 1 to a 0 value
  *  @count: pointer of type atomic_t
- *  @fail_fn: function to call if the original value was not 1
  *
- * Change the count from 1 to a value lower than 1, and call <fail_fn> if
- * it wasn't 1 originally. This function returns 0 if the fastpath succeeds,
- * or anything the slow path function returns
+ * Change the count from 1 to a value lower than 1. This function returns 0
+ * if the fastpath succeeds, or -1 otherwise.
  */
-static inline int __mutex_fastpath_lock_retval(atomic_t *count,
-                                               int (*fail_fn)(atomic_t *))
+static inline int __mutex_fastpath_lock_retval(atomic_t *count)
 {
         if (unlikely(atomic_dec_return(count) < 0))
-                return fail_fn(count);
+                return -1;
         else
                 return 0;
 }
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index c0fa356e90de..86f9301903c8 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -18,9 +18,7 @@ extern int proc_nmi_enabled(struct ctl_table *, int ,
                         void __user *, size_t *, loff_t *);
 extern int unknown_nmi_panic;
 
-void arch_trigger_all_cpu_backtrace(void);
-#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
-#endif
+#endif /* CONFIG_X86_LOCAL_APIC */
 
 #define NMI_FLAG_FIRST  1
 
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 57cb63402213..8249df45d2f2 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -29,6 +29,9 @@
 #define ARCH_PERFMON_EVENTSEL_INV                       (1ULL << 23)
 #define ARCH_PERFMON_EVENTSEL_CMASK                     0xFF000000ULL
 
+#define HSW_IN_TX                                       (1ULL << 32)
+#define HSW_IN_TX_CHECKPOINTED                          (1ULL << 33)
+
 #define AMD64_EVENTSEL_INT_CORE_ENABLE                  (1ULL << 36)
 #define AMD64_EVENTSEL_GUESTONLY                        (1ULL << 40)
 #define AMD64_EVENTSEL_HOSTONLY                         (1ULL << 41)
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 1e672234c4ff..7dc305a46058 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -207,7 +207,7 @@ static inline pte_t pte_mkexec(pte_t pte)
 
 static inline pte_t pte_mkdirty(pte_t pte)
 {
-        return pte_set_flags(pte, _PAGE_DIRTY);
+        return pte_set_flags(pte, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
 }
 
 static inline pte_t pte_mkyoung(pte_t pte)
@@ -271,7 +271,7 @@ static inline pmd_t pmd_wrprotect(pmd_t pmd)
 
 static inline pmd_t pmd_mkdirty(pmd_t pmd)
 {
-        return pmd_set_flags(pmd, _PAGE_DIRTY);
+        return pmd_set_flags(pmd, _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
 }
 
 static inline pmd_t pmd_mkhuge(pmd_t pmd)
@@ -294,6 +294,26 @@ static inline pmd_t pmd_mknotpresent(pmd_t pmd)
         return pmd_clear_flags(pmd, _PAGE_PRESENT);
 }
 
+static inline int pte_soft_dirty(pte_t pte)
+{
+        return pte_flags(pte) & _PAGE_SOFT_DIRTY;
+}
+
+static inline int pmd_soft_dirty(pmd_t pmd)
+{
+        return pmd_flags(pmd) & _PAGE_SOFT_DIRTY;
+}
+
+static inline pte_t pte_mksoft_dirty(pte_t pte)
+{
+        return pte_set_flags(pte, _PAGE_SOFT_DIRTY);
+}
+
+static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
+{
+        return pmd_set_flags(pmd, _PAGE_SOFT_DIRTY);
+}
+
 /*
  * Mask out unsupported bits in a present pgprot.  Non-present pgprots
  * can use those bits for other purposes, so leave them be.
@@ -506,9 +526,6 @@ static inline unsigned long pages_to_mb(unsigned long npg)
         return npg >> (20 - PAGE_SHIFT);
 }
 
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
-        remap_pfn_range(vma, vaddr, pfn, size, prot)
-
 #if PAGETABLE_LEVELS > 2
 static inline int pud_none(pud_t pud)
 {
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index e6423002c10b..c98ac63aae48 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -55,6 +55,18 @@
 #define _PAGE_HIDDEN    (_AT(pteval_t, 0))
 #endif
 
+/*
+ * The same hidden bit is used by kmemcheck, but since kmemcheck
+ * works on kernel pages while soft-dirty engine on user space,
+ * they do not conflict with each other.
+ */
+
+#ifdef CONFIG_MEM_SOFT_DIRTY
+#define _PAGE_SOFT_DIRTY        (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
+#else
+#define _PAGE_SOFT_DIRTY        (_AT(pteval_t, 0))
+#endif
+
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 #define _PAGE_NX        (_AT(pteval_t, 1) << _PAGE_BIT_NX)
 #else
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 22224b3b43bb..29937c4f6ff8 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -89,9 +89,9 @@ struct cpuinfo_x86 {
         char                    wp_works_ok;    /* It doesn't on 386's */
 
         /* Problems on some 486Dx4's and old 386's: */
-        char                    hard_math;
         char                    rfu;
         char                    pad0;
+        char                    pad1;
 #else
         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
         int                     x86_tlbsize;
@@ -164,6 +164,7 @@ extern const struct seq_operations cpuinfo_op;
 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
 
 extern void cpu_detect(struct cpuinfo_x86 *c);
+extern void __cpuinit fpu_detect(struct cpuinfo_x86 *c);
 
 extern void early_cpu_init(void);
 extern void identify_boot_cpu(void);
@@ -981,5 +982,5 @@ bool xen_set_default_idle(void);
 #endif
 
 void stop_this_cpu(void *dummy);
-
+void df_debug(struct pt_regs *regs, long error_code);
 #endif /* _ASM_X86_PROCESSOR_H */
diff --git a/arch/x86/include/asm/sighandling.h b/arch/x86/include/asm/sighandling.h
index beff97f7df37..7a958164088c 100644
--- a/arch/x86/include/asm/sighandling.h
+++ b/arch/x86/include/asm/sighandling.h
@@ -7,10 +7,10 @@
 
 #include <asm/processor-flags.h>
 
-#define __FIX_EFLAGS    (X86_EFLAGS_AC | X86_EFLAGS_OF | \
+#define FIX_EFLAGS      (X86_EFLAGS_AC | X86_EFLAGS_OF | \
                          X86_EFLAGS_DF | X86_EFLAGS_TF | X86_EFLAGS_SF | \
                          X86_EFLAGS_ZF | X86_EFLAGS_AF | X86_EFLAGS_PF | \
-                         X86_EFLAGS_CF)
+                         X86_EFLAGS_CF | X86_EFLAGS_RF)
 
 void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
 
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h
index 41fc93a2e225..2f4d924fe6c9 100644
--- a/arch/x86/include/asm/special_insns.h
+++ b/arch/x86/include/asm/special_insns.h
@@ -16,7 +16,7 @@ static inline void native_clts(void)
  * all loads stores around it, which can hurt performance. Solution is to
  * use a variable and mimic reads and writes to it to enforce serialization
  */
-static unsigned long __force_order;
+extern unsigned long __force_order;
 
 static inline unsigned long native_read_cr0(void)
 {
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index a1df6e84691f..27811190cbd7 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -89,7 +89,6 @@ struct thread_info {
 #define TIF_FORK                18      /* ret_from_fork */
 #define TIF_NOHZ                19      /* in adaptive nohz mode */
 #define TIF_MEMDIE              20      /* is terminating due to OOM killer */
-#define TIF_DEBUG               21      /* uses debug registers */
 #define TIF_IO_BITMAP           22      /* uses I/O bitmap */
 #define TIF_FORCED_TF           24      /* true if TF in eflags artificially */
 #define TIF_BLOCKSTEP           25      /* set when we want DEBUGCTLMSR_BTF */
@@ -113,7 +112,6 @@ struct thread_info {
 #define _TIF_IA32               (1 << TIF_IA32)
 #define _TIF_FORK               (1 << TIF_FORK)
 #define _TIF_NOHZ               (1 << TIF_NOHZ)
-#define _TIF_DEBUG              (1 << TIF_DEBUG)
 #define _TIF_IO_BITMAP          (1 << TIF_IO_BITMAP)
 #define _TIF_FORCED_TF          (1 << TIF_FORCED_TF)
 #define _TIF_BLOCKSTEP          (1 << TIF_BLOCKSTEP)
@@ -154,7 +152,7 @@ struct thread_info {
         (_TIF_IO_BITMAP|_TIF_NOTSC|_TIF_BLOCKSTEP)
 
 #define _TIF_WORK_CTXSW_PREV (_TIF_WORK_CTXSW|_TIF_USER_RETURN_NOTIFY)
-#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
+#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW)
 
 #define PREEMPT_ACTIVE          0x10000000
 
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 50a7fc0f824a..cf512003e663 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -62,7 +62,7 @@ static inline void __flush_tlb_all(void)
 
 static inline void __flush_tlb_one(unsigned long addr)
 {
-                __flush_tlb_single(addr);
+        __flush_tlb_single(addr);
 }
 
 #define TLB_FLUSH_ALL   -1UL
diff --git a/arch/x86/include/asm/trace/irq_vectors.h b/arch/x86/include/asm/trace/irq_vectors.h
new file mode 100644
index 000000000000..2874df24e7a4
--- /dev/null
+++ b/arch/x86/include/asm/trace/irq_vectors.h
@@ -0,0 +1,104 @@
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM irq_vectors
+
+#if !defined(_TRACE_IRQ_VECTORS_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_IRQ_VECTORS_H
+
+#include <linux/tracepoint.h>
+
+extern void trace_irq_vector_regfunc(void);
+extern void trace_irq_vector_unregfunc(void);
+
+DECLARE_EVENT_CLASS(x86_irq_vector,
+
+        TP_PROTO(int vector),
+
+        TP_ARGS(vector),
+
+        TP_STRUCT__entry(
+                __field(                int,    vector  )
+        ),
+
+        TP_fast_assign(
+                __entry->vector = vector;
+        ),
+
+        TP_printk("vector=%d", __entry->vector) );
+
+#define DEFINE_IRQ_VECTOR_EVENT(name)           \
+DEFINE_EVENT_FN(x86_irq_vector, name##_entry,   \
+        TP_PROTO(int vector),                   \
+        TP_ARGS(vector),                        \
+        trace_irq_vector_regfunc,               \
+        trace_irq_vector_unregfunc);            \
+DEFINE_EVENT_FN(x86_irq_vector, name##_exit,    \
+        TP_PROTO(int vector),                   \
+        TP_ARGS(vector),                        \
+        trace_irq_vector_regfunc,               \
+        trace_irq_vector_unregfunc);
+
+
+/*
+ * local_timer - called when entering/exiting a local timer interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(local_timer);
+
+/*
+ * reschedule - called when entering/exiting a reschedule vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(reschedule);
+
+/*
+ * spurious_apic - called when entering/exiting a spurious apic vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(spurious_apic);
+
+/*
+ * error_apic - called when entering/exiting an error apic vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(error_apic);
+
+/*
+ * x86_platform_ipi - called when entering/exiting a x86 platform ipi interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(x86_platform_ipi);
+
+/*
+ * irq_work - called when entering/exiting a irq work interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(irq_work);
+
+/*
+ * call_function - called when entering/exiting a call function interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(call_function);
+
+/*
+ * call_function_single - called when entering/exiting a call function
+ * single interrupt vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(call_function_single);
+
+/*
+ * threshold_apic - called when entering/exiting a threshold apic interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(threshold_apic);
+
+/*
+ * thermal_apic - called when entering/exiting a thermal apic interrupt
+ * vector handler
+ */
+DEFINE_IRQ_VECTOR_EVENT(thermal_apic);
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE irq_vectors
+#endif /*  _TRACE_IRQ_VECTORS_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 142810c457dc..4f7923dd0007 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -235,7 +235,7 @@ extern long __copy_user_nocache(void *dst, const void __user *src,
 static inline int
 __copy_from_user_nocache(void *dst, const void __user *src, unsigned size)
 {
-        might_sleep();
+        might_fault();
         return __copy_user_nocache(dst, src, size, 1);
 }
 
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index a06983cdc125..0b46ef261c77 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -731,6 +731,9 @@ static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
 }
 
 extern void uv_bau_message_intr1(void);
+#ifdef CONFIG_TRACING
+#define trace_uv_bau_message_intr1 uv_bau_message_intr1
+#endif
 extern void uv_bau_timeout_intr1(void);
 
 struct atomic_short {
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index 08744242b8d2..c15ddaf90710 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -6,7 +6,6 @@
 #define SETUP_E820_EXT                  1
 #define SETUP_DTB                       2
 #define SETUP_PCI                       3
-#define SETUP_EFI_VARS                  4
 
 /* ram_size flags */
 #define RAMDISK_IMAGE_START_MASK        0x07FF
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 2af848dfa754..bb0465090ae5 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -170,6 +170,9 @@
 #define MSR_KNC_EVNTSEL0               0x00000028
 #define MSR_KNC_EVNTSEL1               0x00000029
 
+/* Alternative perfctr range with full access. */
+#define MSR_IA32_PMC0                   0x000004c1
+
 /* AMD64 MSRs. Not complete. See the architecture manual for a more
    complete list. */
 
diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h
index 54991a746043..180a0c3c224d 100644
--- a/arch/x86/include/uapi/asm/processor-flags.h
+++ b/arch/x86/include/uapi/asm/processor-flags.h
@@ -2,75 +2,129 @@
 #define _UAPI_ASM_X86_PROCESSOR_FLAGS_H
 /* Various flags defined: can be included from assembler. */
 
+#include <linux/const.h>
+
 /*
  * EFLAGS bits
  */
-#define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
-#define X86_EFLAGS_BIT1 0x00000002 /* Bit 1 - always on */
-#define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
-#define X86_EFLAGS_AF   0x00000010 /* Auxiliary carry Flag */
-#define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
-#define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
-#define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
-#define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
-#define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
-#define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
-#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
-#define X86_EFLAGS_NT   0x00004000 /* Nested Task */
-#define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
-#define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
-#define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
-#define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
-#define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
-#define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
+#define X86_EFLAGS_CF_BIT       0 /* Carry Flag */
+#define X86_EFLAGS_CF           _BITUL(X86_EFLAGS_CF_BIT)
+#define X86_EFLAGS_FIXED_BIT    1 /* Bit 1 - always on */
+#define X86_EFLAGS_FIXED        _BITUL(X86_EFLAGS_FIXED_BIT)
+#define X86_EFLAGS_PF_BIT       2 /* Parity Flag */
+#define X86_EFLAGS_PF           _BITUL(X86_EFLAGS_PF_BIT)
+#define X86_EFLAGS_AF_BIT       4 /* Auxiliary carry Flag */
+#define X86_EFLAGS_AF           _BITUL(X86_EFLAGS_AF_BIT)
+#define X86_EFLAGS_ZF_BIT       6 /* Zero Flag */
+#define X86_EFLAGS_ZF           _BITUL(X86_EFLAGS_ZF_BIT)
+#define X86_EFLAGS_SF_BIT       7 /* Sign Flag */
+#define X86_EFLAGS_SF           _BITUL(X86_EFLAGS_SF_BIT)
+#define X86_EFLAGS_TF_BIT       8 /* Trap Flag */
+#define X86_EFLAGS_TF           _BITUL(X86_EFLAGS_TF_BIT)
+#define X86_EFLAGS_IF_BIT       9 /* Interrupt Flag */
+#define X86_EFLAGS_IF           _BITUL(X86_EFLAGS_IF_BIT)
+#define X86_EFLAGS_DF_BIT       10 /* Direction Flag */
+#define X86_EFLAGS_DF           _BITUL(X86_EFLAGS_DF_BIT)
+#define X86_EFLAGS_OF_BIT       11 /* Overflow Flag */
+#define X86_EFLAGS_OF           _BITUL(X86_EFLAGS_OF_BIT)
+#define X86_EFLAGS_IOPL_BIT     12 /* I/O Privilege Level (2 bits) */
+#define X86_EFLAGS_IOPL         (_AC(3,UL) << X86_EFLAGS_IOPL_BIT)
+#define X86_EFLAGS_NT_BIT       14 /* Nested Task */
+#define X86_EFLAGS_NT           _BITUL(X86_EFLAGS_NT_BIT)
+#define X86_EFLAGS_RF_BIT       16 /* Resume Flag */
+#define X86_EFLAGS_RF           _BITUL(X86_EFLAGS_RF_BIT)
+#define X86_EFLAGS_VM_BIT       17 /* Virtual Mode */
+#define X86_EFLAGS_VM           _BITUL(X86_EFLAGS_VM_BIT)
+#define X86_EFLAGS_AC_BIT       18 /* Alignment Check/Access Control */
+#define X86_EFLAGS_AC           _BITUL(X86_EFLAGS_AC_BIT)
+#define X86_EFLAGS_AC_BIT       18 /* Alignment Check/Access Control */
+#define X86_EFLAGS_AC           _BITUL(X86_EFLAGS_AC_BIT)
+#define X86_EFLAGS_VIF_BIT      19 /* Virtual Interrupt Flag */
+#define X86_EFLAGS_VIF          _BITUL(X86_EFLAGS_VIF_BIT)
+#define X86_EFLAGS_VIP_BIT      20 /* Virtual Interrupt Pending */
+#define X86_EFLAGS_VIP          _BITUL(X86_EFLAGS_VIP_BIT)
+#define X86_EFLAGS_ID_BIT       21 /* CPUID detection */
+#define X86_EFLAGS_ID           _BITUL(X86_EFLAGS_ID_BIT)
 
 /*
  * Basic CPU control in CR0
  */
-#define X86_CR0_PE      0x00000001 /* Protection Enable */
-#define X86_CR0_MP      0x00000002 /* Monitor Coprocessor */
-#define X86_CR0_EM      0x00000004 /* Emulation */
-#define X86_CR0_TS      0x00000008 /* Task Switched */
-#define X86_CR0_ET      0x00000010 /* Extension Type */
-#define X86_CR0_NE      0x00000020 /* Numeric Error */
-#define X86_CR0_WP      0x00010000 /* Write Protect */
-#define X86_CR0_AM      0x00040000 /* Alignment Mask */
-#define X86_CR0_NW      0x20000000 /* Not Write-through */
-#define X86_CR0_CD      0x40000000 /* Cache Disable */
-#define X86_CR0_PG      0x80000000 /* Paging */
+#define X86_CR0_PE_BIT          0 /* Protection Enable */
+#define X86_CR0_PE              _BITUL(X86_CR0_PE_BIT)
+#define X86_CR0_MP_BIT          1 /* Monitor Coprocessor */
+#define X86_CR0_MP              _BITUL(X86_CR0_MP_BIT)
+#define X86_CR0_EM_BIT          2 /* Emulation */
+#define X86_CR0_EM              _BITUL(X86_CR0_EM_BIT)
+#define X86_CR0_TS_BIT          3 /* Task Switched */
+#define X86_CR0_TS              _BITUL(X86_CR0_TS_BIT)
+#define X86_CR0_ET_BIT          4 /* Extension Type */
+#define X86_CR0_ET              _BITUL(X86_CR0_ET_BIT)
+#define X86_CR0_NE_BIT          5 /* Numeric Error */
+#define X86_CR0_NE              _BITUL(X86_CR0_NE_BIT)
+#define X86_CR0_WP_BIT          16 /* Write Protect */
+#define X86_CR0_WP              _BITUL(X86_CR0_WP_BIT)
+#define X86_CR0_AM_BIT          18 /* Alignment Mask */
+#define X86_CR0_AM              _BITUL(X86_CR0_AM_BIT)
+#define X86_CR0_NW_BIT          29 /* Not Write-through */
+#define X86_CR0_NW              _BITUL(X86_CR0_NW_BIT)
+#define X86_CR0_CD_BIT          30 /* Cache Disable */
+#define X86_CR0_CD              _BITUL(X86_CR0_CD_BIT)
+#define X86_CR0_PG_BIT          31 /* Paging */
+#define X86_CR0_PG              _BITUL(X86_CR0_PG_BIT)
 
 /*
  * Paging options in CR3
  */
-#define X86_CR3_PWT     0x00000008 /* Page Write Through */
-#define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
-#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
+#define X86_CR3_PWT_BIT         3 /* Page Write Through */
+#define X86_CR3_PWT             _BITUL(X86_CR3_PWT_BIT)
+#define X86_CR3_PCD_BIT         4 /* Page Cache Disable */
+#define X86_CR3_PCD             _BITUL(X86_CR3_PCD_BIT)
+#define X86_CR3_PCID_MASK       _AC(0x00000fff,UL) /* PCID Mask */
 
 /*
  * Intel CPU features in CR4
  */
-#define X86_CR4_VME     0x00000001 /* enable vm86 extensions */
-#define X86_CR4_PVI     0x00000002 /* virtual interrupts flag enable */
-#define X86_CR4_TSD     0x00000004 /* disable time stamp at ipl 3 */
-#define X86_CR4_DE      0x00000008 /* enable debugging extensions */
-#define X86_CR4_PSE     0x00000010 /* enable page size extensions */
-#define X86_CR4_PAE     0x00000020 /* enable physical address extensions */
-#define X86_CR4_MCE     0x00000040 /* Machine check enable */
-#define X86_CR4_PGE     0x00000080 /* enable global pages */
-#define X86_CR4_PCE     0x00000100 /* enable performance counters at ipl 3 */
-#define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
-#define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
-#define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
-#define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
-#define X86_CR4_PCIDE   0x00020000 /* enable PCID support */
-#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
-#define X86_CR4_SMEP    0x00100000 /* enable SMEP support */
-#define X86_CR4_SMAP    0x00200000 /* enable SMAP support */
+#define X86_CR4_VME_BIT         0 /* enable vm86 extensions */
+#define X86_CR4_VME             _BITUL(X86_CR4_VME_BIT)
+#define X86_CR4_PVI_BIT         1 /* virtual interrupts flag enable */
+#define X86_CR4_PVI             _BITUL(X86_CR4_PVI_BIT)
+#define X86_CR4_TSD_BIT         2 /* disable time stamp at ipl 3 */
+#define X86_CR4_TSD             _BITUL(X86_CR4_TSD_BIT)
+#define X86_CR4_DE_BIT          3 /* enable debugging extensions */
+#define X86_CR4_DE              _BITUL(X86_CR4_DE_BIT)
+#define X86_CR4_PSE_BIT         4 /* enable page size extensions */
+#define X86_CR4_PSE             _BITUL(X86_CR4_PSE_BIT)
+#define X86_CR4_PAE_BIT         5 /* enable physical address extensions */
+#define X86_CR4_PAE             _BITUL(X86_CR4_PAE_BIT)
+#define X86_CR4_MCE_BIT         6 /* Machine check enable */
+#define X86_CR4_MCE             _BITUL(X86_CR4_MCE_BIT)
+#define X86_CR4_PGE_BIT         7 /* enable global pages */
+#define X86_CR4_PGE             _BITUL(X86_CR4_PGE_BIT)
+#define X86_CR4_PCE_BIT         8 /* enable performance counters at ipl 3 */
+#define X86_CR4_PCE             _BITUL(X86_CR4_PCE_BIT)
+#define X86_CR4_OSFXSR_BIT      9 /* enable fast FPU save and restore */
+#define X86_CR4_OSFXSR          _BITUL(X86_CR4_OSFXSR_BIT)
+#define X86_CR4_OSXMMEXCPT_BIT  10 /* enable unmasked SSE exceptions */
+#define X86_CR4_OSXMMEXCPT      _BITUL(X86_CR4_OSXMMEXCPT_BIT)
+#define X86_CR4_VMXE_BIT        13 /* enable VMX virtualization */
+#define X86_CR4_VMXE            _BITUL(X86_CR4_VMXE_BIT)
+#define X86_CR4_SMXE_BIT        14 /* enable safer mode (TXT) */
+#define X86_CR4_SMXE            _BITUL(X86_CR4_SMXE_BIT)
+#define X86_CR4_FSGSBASE_BIT    16 /* enable RDWRFSGS support */
+#define X86_CR4_FSGSBASE        _BITUL(X86_CR4_FSGSBASE_BIT)
+#define X86_CR4_PCIDE_BIT       17 /* enable PCID support */
+#define X86_CR4_PCIDE           _BITUL(X86_CR4_PCIDE_BIT)
+#define X86_CR4_OSXSAVE_BIT     18 /* enable xsave and xrestore */
+#define X86_CR4_OSXSAVE         _BITUL(X86_CR4_OSXSAVE_BIT)
+#define X86_CR4_SMEP_BIT        20 /* enable SMEP support */
+#define X86_CR4_SMEP            _BITUL(X86_CR4_SMEP_BIT)
+#define X86_CR4_SMAP_BIT        21 /* enable SMAP support */
+#define X86_CR4_SMAP            _BITUL(X86_CR4_SMAP_BIT)
 
 /*
  * x86-64 Task Priority Register, CR8
  */
-#define X86_CR8_TPR     0x0000000F /* task priority register */
+#define X86_CR8_TPR             _AC(0x0000000f,UL) /* task priority register */
 
 /*
  * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h>
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 7bd3bd310106..88d99ea77723 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -16,6 +16,8 @@ CFLAGS_REMOVE_ftrace.o = -pg
 CFLAGS_REMOVE_early_printk.o = -pg
 endif
 
+CFLAGS_irq.o := -I$(src)/../include/asm/trace
+
 obj-y                   := process_$(BITS).o signal.o entry_$(BITS).o
 obj-y                   += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o
 obj-y                   += time.o ioport.o ldt.o dumpstack.o nmi.o
@@ -67,7 +69,7 @@ obj-$(CONFIG_KEXEC)		+= relocate_kernel_$(BITS).o crash.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump_$(BITS).o
 obj-y                           += kprobes/
 obj-$(CONFIG_MODULES)           += module.o
-obj-$(CONFIG_DOUBLEFAULT)       += doublefault_32.o
+obj-$(CONFIG_DOUBLEFAULT)       += doublefault.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_VM86)              += vm86_32.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
@@ -93,6 +95,7 @@ obj-$(CONFIG_MICROCODE_INTEL_LIB)	+= microcode_intel_lib.o
 microcode-y                             := microcode_core.o
 microcode-$(CONFIG_MICROCODE_INTEL)     += microcode_intel.o
 microcode-$(CONFIG_MICROCODE_AMD)       += microcode_amd.o
+obj-$(CONFIG_MICROCODE_AMD_EARLY)       += microcode_amd_early.o
 obj-$(CONFIG_MICROCODE)                 += microcode.o
 
 obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o
@@ -102,6 +105,7 @@ obj-$(CONFIG_OF)			+= devicetree.o
 obj-$(CONFIG_UPROBES)                   += uprobes.o
 
 obj-$(CONFIG_PERF_EVENTS)               += perf_regs.o
+obj-$(CONFIG_TRACING)                   += tracepoint.o
 
 ###
 # 64 bit specific files
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 230c8ea878e5..d81a972dd506 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -44,6 +44,7 @@
 #include <asm/mpspec.h>
 #include <asm/smp.h>
 
+#include "sleep.h" /* To include x86_acpi_suspend_lowlevel */
 static int __initdata acpi_force = 0;
 u32 acpi_rsdt_forced;
 int acpi_disabled;
@@ -559,6 +560,12 @@ static int acpi_register_gsi_ioapic(struct device *dev, u32 gsi,
 int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
                            int trigger, int polarity) = acpi_register_gsi_pic;
 
+#ifdef CONFIG_ACPI_SLEEP
+int (*acpi_suspend_lowlevel)(void) = x86_acpi_suspend_lowlevel;
+#else
+int (*acpi_suspend_lowlevel)(void);
+#endif
+
 /*
  * success: return IRQ number (>=0)
  * failure: return < 0
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index b44577bc9744..2a34aaf3c8f1 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -26,12 +26,12 @@ static char temp_stack[4096];
 #endif
 
 /**
- * acpi_suspend_lowlevel - save kernel state
+ * x86_acpi_suspend_lowlevel - save kernel state
  *
  * Create an identity mapped page table and copy the wakeup routine to
  * low memory.
  */
-int acpi_suspend_lowlevel(void)
+int x86_acpi_suspend_lowlevel(void)
 {
         struct wakeup_header *header =
                 (struct wakeup_header *) __va(real_mode_header->wakeup_header);
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 67f59f8c6956..c9c2c982d5e4 100644
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -15,3 +15,5 @@ extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
 
 extern void do_suspend_lowlevel(void);
+
+extern int x86_acpi_suspend_lowlevel(void);
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 904611bf0e5a..99663b59123a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -35,6 +35,7 @@
 #include <linux/smp.h>
 #include <linux/mm.h>
 
+#include <asm/trace/irq_vectors.h>
 #include <asm/irq_remapping.h>
 #include <asm/perf_event.h>
 #include <asm/x86_init.h>
@@ -919,17 +920,35 @@ void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
         /*
          * NOTE! We'd better ACK the irq immediately,
          * because timer handling can be slow.
+         *
+         * update_process_times() expects us to have done irq_enter().
+         * Besides, if we don't timer interrupts ignore the global
+         * interrupt lock, which is the WrongThing (tm) to do.
          */
-        ack_APIC_irq();
+        entering_ack_irq();
+        local_apic_timer_interrupt();
+        exiting_irq();
+
+        set_irq_regs(old_regs);
+}
+
+void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
         /*
+         * NOTE! We'd better ACK the irq immediately,
+         * because timer handling can be slow.
+         *
          * update_process_times() expects us to have done irq_enter().
          * Besides, if we don't timer interrupts ignore the global
          * interrupt lock, which is the WrongThing (tm) to do.
          */
-        irq_enter();
-        exit_idle();
+        entering_ack_irq();
+        trace_local_timer_entry(LOCAL_TIMER_VECTOR);
         local_apic_timer_interrupt();
-        irq_exit();
+        trace_local_timer_exit(LOCAL_TIMER_VECTOR);
+        exiting_irq();
 
         set_irq_regs(old_regs);
 }
@@ -1907,12 +1926,10 @@ int __init APIC_init_uniprocessor(void)
 /*
  * This interrupt should _never_ happen with our APIC/SMP architecture
  */
-void smp_spurious_interrupt(struct pt_regs *regs)
+static inline void __smp_spurious_interrupt(void)
 {
         u32 v;
 
-        irq_enter();
-        exit_idle();
         /*
          * Check if this really is a spurious interrupt and ACK it
          * if it is a vectored one.  Just in case...
@@ -1927,13 +1944,28 @@ void smp_spurious_interrupt(struct pt_regs *regs)
         /* see sw-dev-man vol 3, chapter 7.4.13.5 */
         pr_info("spurious APIC interrupt on CPU#%d, "
                 "should never happen.\n", smp_processor_id());
-        irq_exit();
+}
+
+void smp_spurious_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        __smp_spurious_interrupt();
+        exiting_irq();
+}
+
+void smp_trace_spurious_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR);
+        __smp_spurious_interrupt();
+        trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR);
+        exiting_irq();
 }
 
 /*
  * This interrupt should never happen with our APIC/SMP architecture
  */
-void smp_error_interrupt(struct pt_regs *regs)
+static inline void __smp_error_interrupt(struct pt_regs *regs)
 {
         u32 v0, v1;
         u32 i = 0;
@@ -1948,8 +1980,6 @@ void smp_error_interrupt(struct pt_regs *regs)
                 "Illegal register address",     /* APIC Error Bit 7 */
         };
 
-        irq_enter();
-        exit_idle();
         /* First tickle the hardware, only then report what went on. -- REW */
         v0 = apic_read(APIC_ESR);
         apic_write(APIC_ESR, 0);
@@ -1970,7 +2000,22 @@ void smp_error_interrupt(struct pt_regs *regs)
 
         apic_printk(APIC_DEBUG, KERN_CONT "\n");
 
-        irq_exit();
+}
+
+void smp_error_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        __smp_error_interrupt(regs);
+        exiting_irq();
+}
+
+void smp_trace_error_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        trace_error_apic_entry(ERROR_APIC_VECTOR);
+        __smp_error_interrupt(regs);
+        trace_error_apic_exit(ERROR_APIC_VECTOR);
+        exiting_irq();
 }
 
 /**
@@ -2302,7 +2347,7 @@ static void lapic_resume(void)
         apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
         apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
         apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
-#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
+#if defined(CONFIG_X86_MCE_INTEL)
         if (maxlvt >= 5)
                 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
 #endif
diff --git a/arch/x86/kernel/apic/hw_nmi.c b/arch/x86/kernel/apic/hw_nmi.c
index 31cb9ae992b7..a698d7165c96 100644
--- a/arch/x86/kernel/apic/hw_nmi.c
+++ b/arch/x86/kernel/apic/hw_nmi.c
@@ -9,6 +9,7 @@
  *
  */
 #include <asm/apic.h>
+#include <asm/nmi.h>
 
 #include <linux/cpumask.h>
 #include <linux/kdebug.h>
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 794f6eb54cd3..39cc7f7acab3 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -51,6 +51,8 @@ DEFINE_PER_CPU(int, x2apic_extra_bits);
 
 static enum uv_system_type uv_system_type;
 static u64 gru_start_paddr, gru_end_paddr;
+static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
+static u64 gru_dist_lmask, gru_dist_umask;
 static union uvh_apicid uvh_apicid;
 int uv_min_hub_revision_id;
 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
@@ -72,7 +74,20 @@ static unsigned long __init uv_early_read_mmr(unsigned long addr)
 
 static inline bool is_GRU_range(u64 start, u64 end)
 {
-        return start >= gru_start_paddr && end <= gru_end_paddr;
+        if (gru_dist_base) {
+                u64 su = start & gru_dist_umask; /* upper (incl pnode) bits */
+                u64 sl = start & gru_dist_lmask; /* base offset bits */
+                u64 eu = end & gru_dist_umask;
+                u64 el = end & gru_dist_lmask;
+
+                /* Must reside completely within a single GRU range */
+                return (sl == gru_dist_base && el == gru_dist_base &&
+                        su >= gru_first_node_paddr &&
+                        su <= gru_last_node_paddr &&
+                        eu == su);
+        } else {
+                return start >= gru_start_paddr && end <= gru_end_paddr;
+        }
 }
 
 static bool uv_is_untracked_pat_range(u64 start, u64 end)
@@ -463,26 +478,63 @@ static __init void map_high(char *id, unsigned long base, int pshift,
                 pr_info("UV: Map %s_HI base address NULL\n", id);
                 return;
         }
-        pr_info("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
+        pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes);
         if (map_type == map_uc)
                 init_extra_mapping_uc(paddr, bytes);
         else
                 init_extra_mapping_wb(paddr, bytes);
 }
 
+static __init void map_gru_distributed(unsigned long c)
+{
+        union uvh_rh_gam_gru_overlay_config_mmr_u gru;
+        u64 paddr;
+        unsigned long bytes;
+        int nid;
+
+        gru.v = c;
+        /* only base bits 42:28 relevant in dist mode */
+        gru_dist_base = gru.v & 0x000007fff0000000UL;
+        if (!gru_dist_base) {
+                pr_info("UV: Map GRU_DIST base address NULL\n");
+                return;
+        }
+        bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
+        gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1);
+        gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1);
+        gru_dist_base &= gru_dist_lmask; /* Clear bits above M */
+        for_each_online_node(nid) {
+                paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) |
+                                gru_dist_base;
+                init_extra_mapping_wb(paddr, bytes);
+                gru_first_node_paddr = min(paddr, gru_first_node_paddr);
+                gru_last_node_paddr = max(paddr, gru_last_node_paddr);
+        }
+        /* Save upper (63:M) bits of address only for is_GRU_range */
+        gru_first_node_paddr &= gru_dist_umask;
+        gru_last_node_paddr &= gru_dist_umask;
+        pr_debug("UV: Map GRU_DIST base 0x%016llx  0x%016llx - 0x%016llx\n",
+                gru_dist_base, gru_first_node_paddr, gru_last_node_paddr);
+}
+
 static __init void map_gru_high(int max_pnode)
 {
         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 
         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
-        if (gru.s.enable) {
-                map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
-                gru_start_paddr = ((u64)gru.s.base << shift);
-                gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
-        } else {
+        if (!gru.s.enable) {
                 pr_info("UV: GRU disabled\n");
+                return;
+        }
+
+        if (is_uv3_hub() && gru.s3.mode) {
+                map_gru_distributed(gru.v);
+                return;
         }
+        map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
+        gru_start_paddr = ((u64)gru.s.base << shift);
+        gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 }
 
 static __init void map_mmr_high(int max_pnode)
diff --git a/arch/x86/kernel/asm-offsets_32.c b/arch/x86/kernel/asm-offsets_32.c
index 0ef4bba2acb7..d67c4be3e8b1 100644
--- a/arch/x86/kernel/asm-offsets_32.c
+++ b/arch/x86/kernel/asm-offsets_32.c
@@ -28,7 +28,6 @@ void foo(void)
         OFFSET(CPUINFO_x86_vendor, cpuinfo_x86, x86_vendor);
         OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model);
         OFFSET(CPUINFO_x86_mask, cpuinfo_x86, x86_mask);
-        OFFSET(CPUINFO_hard_math, cpuinfo_x86, hard_math);
         OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level);
         OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability);
         OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id);
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index b0684e4a73aa..47b56a7e99cb 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -31,11 +31,15 @@ obj-$(CONFIG_PERF_EVENTS)		+= perf_event.o
 
 ifdef CONFIG_PERF_EVENTS
 obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd.o perf_event_amd_uncore.o
+ifdef CONFIG_AMD_IOMMU
+obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd_iommu.o
+endif
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_knc.o perf_event_p4.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
 obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore.o
 endif
 
+
 obj-$(CONFIG_X86_MCE)                   += mcheck/
 obj-$(CONFIG_MTRR)                      += mtrr/
 
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 5013a48d1aff..c587a8757227 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -90,7 +90,7 @@ static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
 {
         u32 l, h;
-        int mbytes = num_physpages >> (20-PAGE_SHIFT);
+        int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
 
         if (c->x86_model < 6) {
                 /* Based on AMD doc 20734R - June 2000 */
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 4112be9a4659..03445346ee0a 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -17,15 +17,6 @@
 #include <asm/paravirt.h>
 #include <asm/alternative.h>
 
-static int __init no_387(char *s)
-{
-        boot_cpu_data.hard_math = 0;
-        write_cr0(X86_CR0_TS | X86_CR0_EM | X86_CR0_MP | read_cr0());
-        return 1;
-}
-
-__setup("no387", no_387);
-
 static double __initdata x = 4195835.0;
 static double __initdata y = 3145727.0;
 
@@ -44,15 +35,6 @@ static void __init check_fpu(void)
 {
         s32 fdiv_bug;
 
-        if (!boot_cpu_data.hard_math) {
-#ifndef CONFIG_MATH_EMULATION
-                pr_emerg("No coprocessor found and no math emulation present\n");
-                pr_emerg("Giving up\n");
-                for (;;) ;
-#endif
-                return;
-        }
-
         kernel_fpu_begin();
 
         /*
@@ -107,5 +89,6 @@ void __init check_bugs(void)
          * kernel_fpu_begin/end() in check_fpu() relies on the patched
          * alternative instructions.
          */
-        check_fpu();
+        if (cpu_has_fpu)
+                check_fpu();
 }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 22018f70a671..548bd039784e 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -711,10 +711,9 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
                 return;
 
         cpu_detect(c);
-
         get_cpu_vendor(c);
-
         get_cpu_cap(c);
+        fpu_detect(c);
 
         if (this_cpu->c_early_init)
                 this_cpu->c_early_init(c);
@@ -724,6 +723,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 
         if (this_cpu->c_bsp_init)
                 this_cpu->c_bsp_init(c);
+
+        setup_force_cpu_cap(X86_FEATURE_ALWAYS);
 }
 
 void __init early_cpu_init(void)
@@ -1071,8 +1072,8 @@ __setup("clearcpuid=", setup_disablecpuid);
 
 #ifdef CONFIG_X86_64
 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
-struct desc_ptr nmi_idt_descr = { NR_VECTORS * 16 - 1,
-                                    (unsigned long) nmi_idt_table };
+struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
+                                    (unsigned long) debug_idt_table };
 
 DEFINE_PER_CPU_FIRST(union irq_stack_union,
                      irq_stack_union) __aligned(PAGE_SIZE);
@@ -1148,20 +1149,20 @@ int is_debug_stack(unsigned long addr)
                  addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
 }
 
-static DEFINE_PER_CPU(u32, debug_stack_use_ctr);
+DEFINE_PER_CPU(u32, debug_idt_ctr);
 
 void debug_stack_set_zero(void)
 {
-        this_cpu_inc(debug_stack_use_ctr);
-        load_idt((const struct desc_ptr *)&nmi_idt_descr);
+        this_cpu_inc(debug_idt_ctr);
+        load_current_idt();
 }
 
 void debug_stack_reset(void)
 {
-        if (WARN_ON(!this_cpu_read(debug_stack_use_ctr)))
+        if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
                 return;
-        if (this_cpu_dec_return(debug_stack_use_ctr) == 0)
-                load_idt((const struct desc_ptr *)&idt_descr);
+        if (this_cpu_dec_return(debug_idt_ctr) == 0)
+                load_current_idt();
 }
 
 #else   /* CONFIG_X86_64 */
@@ -1257,7 +1258,7 @@ void __cpuinit cpu_init(void)
         switch_to_new_gdt(cpu);
         loadsegment(fs, 0);
 
-        load_idt((const struct desc_ptr *)&idt_descr);
+        load_current_idt();
 
         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
         syscall_init();
@@ -1334,7 +1335,7 @@ void __cpuinit cpu_init(void)
         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
-        load_idt(&idt_descr);
+        load_current_idt();
         switch_to_new_gdt(cpu);
 
         /*
@@ -1363,3 +1364,17 @@ void __cpuinit cpu_init(void)
         fpu_init();
 }
 #endif
+
+#ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
+void warn_pre_alternatives(void)
+{
+        WARN(1, "You're using static_cpu_has before alternatives have run!\n");
+}
+EXPORT_SYMBOL_GPL(warn_pre_alternatives);
+#endif
+
+inline bool __static_cpu_has_safe(u16 bit)
+{
+        return boot_cpu_has(bit);
+}
+EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index d048d5ca43c1..7582f475b163 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -333,7 +333,7 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 switch (dir0_lsn) {
                 case 0xd:  /* either a 486SLC or DLC w/o DEVID */
                         dir0_msn = 0;
-                        p = Cx486_name[(c->hard_math) ? 1 : 0];
+                        p = Cx486_name[(cpu_has_fpu ? 1 : 0)];
                         break;
 
                 case 0xe:  /* a 486S A step */
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 7c6f7d548c0f..8dc72dda66fe 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -618,36 +618,34 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                  * parameters cpuid leaf to find the cache details
                  */
                 for (i = 0; i < num_cache_leaves; i++) {
-                        struct _cpuid4_info_regs this_leaf;
+                        struct _cpuid4_info_regs this_leaf = {};
                         int retval;
 
                         retval = cpuid4_cache_lookup_regs(i, &this_leaf);
-                        if (retval >= 0) {
-                                switch (this_leaf.eax.split.level) {
-                                case 1:
-                                        if (this_leaf.eax.split.type ==
-                                                        CACHE_TYPE_DATA)
-                                                new_l1d = this_leaf.size/1024;
-                                        else if (this_leaf.eax.split.type ==
-                                                        CACHE_TYPE_INST)
-                                                new_l1i = this_leaf.size/1024;
-                                        break;
-                                case 2:
-                                        new_l2 = this_leaf.size/1024;
-                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
-                                        index_msb = get_count_order(num_threads_sharing);
-                                        l2_id = c->apicid & ~((1 << index_msb) - 1);
-                                        break;
-                                case 3:
-                                        new_l3 = this_leaf.size/1024;
-                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
-                                        index_msb = get_count_order(
-                                                        num_threads_sharing);
-                                        l3_id = c->apicid & ~((1 << index_msb) - 1);
-                                        break;
-                                default:
-                                        break;
-                                }
+                        if (retval < 0)
+                                continue;
+
+                        switch (this_leaf.eax.split.level) {
+                        case 1:
+                                if (this_leaf.eax.split.type == CACHE_TYPE_DATA)
+                                        new_l1d = this_leaf.size/1024;
+                                else if (this_leaf.eax.split.type == CACHE_TYPE_INST)
+                                        new_l1i = this_leaf.size/1024;
+                                break;
+                        case 2:
+                                new_l2 = this_leaf.size/1024;
+                                num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
+                                index_msb = get_count_order(num_threads_sharing);
+                                l2_id = c->apicid & ~((1 << index_msb) - 1);
+                                break;
+                        case 3:
+                                new_l3 = this_leaf.size/1024;
+                                num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
+                                index_msb = get_count_order(num_threads_sharing);
+                                l3_id = c->apicid & ~((1 << index_msb) - 1);
+                                break;
+                        default:
+                                break;
                         }
                 }
         }
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index ddc72f839332..5ac2d1fb28bc 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -153,7 +153,7 @@ static void raise_mce(struct mce *m)
                 return;
 
 #ifdef CONFIG_X86_LOCAL_APIC
-        if (m->inject_flags & (MCJ_IRQ_BRAODCAST | MCJ_NMI_BROADCAST)) {
+        if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) {
                 unsigned long start;
                 int cpu;
 
@@ -167,7 +167,7 @@ static void raise_mce(struct mce *m)
                                 cpumask_clear_cpu(cpu, mce_inject_cpumask);
                 }
                 if (!cpumask_empty(mce_inject_cpumask)) {
-                        if (m->inject_flags & MCJ_IRQ_BRAODCAST) {
+                        if (m->inject_flags & MCJ_IRQ_BROADCAST) {
                                 /*
                                  * don't wait because mce_irq_ipi is necessary
                                  * to be sync with following raise_local
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index beb1f1689e52..e2703520d120 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -110,22 +110,17 @@ static struct severity {
         /* known AR MCACODs: */
 #ifdef  CONFIG_MEMORY_FAILURE
         MCESEV(
-                KEEP, "HT thread notices Action required: data load error",
-                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
-                MCGMASK(MCG_STATUS_EIPV, 0)
+                KEEP, "Action required but unaffected thread is continuable",
+                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR),
+                MCGMASK(MCG_STATUS_RIPV, MCG_STATUS_RIPV)
                 ),
         MCESEV(
-                AR, "Action required: data load error",
+                AR, "Action required: data load error in a user process",
                 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
                 USER
                 ),
         MCESEV(
-                KEEP, "HT thread notices Action required: instruction fetch error",
-                SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
-                MCGMASK(MCG_STATUS_EIPV, 0)
-                ),
-        MCESEV(
-                AR, "Action required: instruction fetch error",
+                AR, "Action required: instruction fetch error in a user process",
                 SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
                 USER
                 ),
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9239504b41cb..bf49cdbb010f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -89,7 +89,10 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
 static DEFINE_PER_CPU(struct mce, mces_seen);
 static int                      cpu_missing;
 
-/* MCA banks polled by the period polling timer for corrected events */
+/*
+ * MCA banks polled by the period polling timer for corrected events.
+ * With Intel CMCI, this only has MCA banks which do not support CMCI (if any).
+ */
 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
         [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
 };
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index ae1697c2afe3..d56405309dc1 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -24,6 +24,18 @@
  * Also supports reliable discovery of shared banks.
  */
 
+/*
+ * CMCI can be delivered to multiple cpus that share a machine check bank
+ * so we need to designate a single cpu to process errors logged in each bank
+ * in the interrupt handler (otherwise we would have many races and potential
+ * double reporting of the same error).
+ * Note that this can change when a cpu is offlined or brought online since
+ * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear()
+ * disables CMCI on all banks owned by the cpu and clears this bitfield. At
+ * this point, cmci_rediscover() kicks in and a different cpu may end up
+ * taking ownership of some of the shared MCA banks that were previously
+ * owned by the offlined cpu.
+ */
 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
 
 /*
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index 47a1870279aa..98f2083832eb 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -29,6 +29,7 @@
 #include <asm/idle.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
+#include <asm/trace/irq_vectors.h>
 
 /* How long to wait between reporting thermal events */
 #define CHECK_INTERVAL          (300 * HZ)
@@ -181,11 +182,6 @@ static int therm_throt_process(bool new_event, int event, int level)
                                 this_cpu,
                                 level == CORE_LEVEL ? "Core" : "Package",
                                 state->count);
-                else
-                        printk(KERN_CRIT "CPU%d: %s power limit notification (total events = %lu)\n",
-                                this_cpu,
-                                level == CORE_LEVEL ? "Core" : "Package",
-                                state->count);
                 return 1;
         }
         if (old_event) {
@@ -193,10 +189,6 @@ static int therm_throt_process(bool new_event, int event, int level)
                         printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
                                 this_cpu,
                                 level == CORE_LEVEL ? "Core" : "Package");
-                else
-                        printk(KERN_INFO "CPU%d: %s power limit normal\n",
-                                this_cpu,
-                                level == CORE_LEVEL ? "Core" : "Package");
                 return 1;
         }
 
@@ -219,6 +211,15 @@ static int thresh_event_valid(int event)
         return 1;
 }
 
+static bool int_pln_enable;
+static int __init int_pln_enable_setup(char *s)
+{
+        int_pln_enable = true;
+
+        return 1;
+}
+__setup("int_pln_enable", int_pln_enable_setup);
+
 #ifdef CONFIG_SYSFS
 /* Add/Remove thermal_throttle interface for CPU device: */
 static __cpuinit int thermal_throttle_add_dev(struct device *dev,
@@ -231,7 +232,7 @@ static __cpuinit int thermal_throttle_add_dev(struct device *dev,
         if (err)
                 return err;
 
-        if (cpu_has(c, X86_FEATURE_PLN))
+        if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
                 err = sysfs_add_file_to_group(&dev->kobj,
                                               &dev_attr_core_power_limit_count.attr,
                                               thermal_attr_group.name);
@@ -239,7 +240,7 @@ static __cpuinit int thermal_throttle_add_dev(struct device *dev,
                 err = sysfs_add_file_to_group(&dev->kobj,
                                               &dev_attr_package_throttle_count.attr,
                                               thermal_attr_group.name);
-                if (cpu_has(c, X86_FEATURE_PLN))
+                if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
                         err = sysfs_add_file_to_group(&dev->kobj,
                                         &dev_attr_package_power_limit_count.attr,
                                         thermal_attr_group.name);
@@ -352,7 +353,7 @@ static void intel_thermal_interrupt(void)
                                 CORE_LEVEL) != 0)
                 mce_log_therm_throt_event(msr_val);
 
-        if (this_cpu_has(X86_FEATURE_PLN))
+        if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
                 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
                                         POWER_LIMIT_EVENT,
                                         CORE_LEVEL);
@@ -362,7 +363,7 @@ static void intel_thermal_interrupt(void)
                 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
                                         THERMAL_THROTTLING_EVENT,
                                         PACKAGE_LEVEL);
-                if (this_cpu_has(X86_FEATURE_PLN))
+                if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
                         therm_throt_process(msr_val &
                                         PACKAGE_THERM_STATUS_POWER_LIMIT,
                                         POWER_LIMIT_EVENT,
@@ -378,15 +379,26 @@ static void unexpected_thermal_interrupt(void)
 
 static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
 
-asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
+static inline void __smp_thermal_interrupt(void)
 {
-        irq_enter();
-        exit_idle();
         inc_irq_stat(irq_thermal_count);
         smp_thermal_vector();
-        irq_exit();
-        /* Ack only at the end to avoid potential reentry */
-        ack_APIC_irq();
+}
+
+asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        __smp_thermal_interrupt();
+        exiting_ack_irq();
+}
+
+asmlinkage void smp_trace_thermal_interrupt(struct pt_regs *regs)
+{
+        entering_irq();
+        trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
+        __smp_thermal_interrupt();
+        trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
+        exiting_ack_irq();
 }
 
 /* Thermal monitoring depends on APIC, ACPI and clock modulation */
@@ -470,9 +482,13 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
         apic_write(APIC_LVTTHMR, h);
 
         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
-        if (cpu_has(c, X86_FEATURE_PLN))
+        if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
+                wrmsr(MSR_IA32_THERM_INTERRUPT,
+                        (l | (THERM_INT_LOW_ENABLE
+                        | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
+        else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
                 wrmsr(MSR_IA32_THERM_INTERRUPT,
-                      l | (THERM_INT_LOW_ENABLE
+                        l | (THERM_INT_LOW_ENABLE
                         | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
         else
                 wrmsr(MSR_IA32_THERM_INTERRUPT,
@@ -480,9 +496,14 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
 
         if (cpu_has(c, X86_FEATURE_PTS)) {
                 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
-                if (cpu_has(c, X86_FEATURE_PLN))
+                if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
                         wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
-                              l | (PACKAGE_THERM_INT_LOW_ENABLE
+                                (l | (PACKAGE_THERM_INT_LOW_ENABLE
+                                | PACKAGE_THERM_INT_HIGH_ENABLE))
+                                & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
+                else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
+                        wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
+                                l | (PACKAGE_THERM_INT_LOW_ENABLE
                                 | PACKAGE_THERM_INT_HIGH_ENABLE
                                 | PACKAGE_THERM_INT_PLN_ENABLE), h);
                 else
diff --git a/arch/x86/kernel/cpu/mcheck/threshold.c b/arch/x86/kernel/cpu/mcheck/threshold.c
index aa578cadb940..fe6b1c86645b 100644
--- a/arch/x86/kernel/cpu/mcheck/threshold.c
+++ b/arch/x86/kernel/cpu/mcheck/threshold.c
@@ -8,6 +8,7 @@
 #include <asm/apic.h>
 #include <asm/idle.h>
 #include <asm/mce.h>
+#include <asm/trace/irq_vectors.h>
 
 static void default_threshold_interrupt(void)
 {
@@ -17,13 +18,24 @@ static void default_threshold_interrupt(void)
 
 void (*mce_threshold_vector)(void) = default_threshold_interrupt;
 
-asmlinkage void smp_threshold_interrupt(void)
+static inline void __smp_threshold_interrupt(void)
 {
-        irq_enter();
-        exit_idle();
         inc_irq_stat(irq_threshold_count);
         mce_threshold_vector();
-        irq_exit();
-        /* Ack only at the end to avoid potential reentry */
-        ack_APIC_irq();
+}
+
+asmlinkage void smp_threshold_interrupt(void)
+{
+        entering_irq();
+        __smp_threshold_interrupt();
+        exiting_ack_irq();
+}
+
+asmlinkage void smp_trace_threshold_interrupt(void)
+{
+        entering_irq();
+        trace_threshold_apic_entry(THRESHOLD_APIC_VECTOR);
+        __smp_threshold_interrupt();
+        trace_threshold_apic_exit(THRESHOLD_APIC_VECTOR);
+        exiting_ack_irq();
 }
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index 35ffda5d0727..5f90b85ff22e 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -714,15 +714,15 @@ int __init mtrr_cleanup(unsigned address_bits)
         if (mtrr_tom2)
                 x_remove_size = (mtrr_tom2 >> PAGE_SHIFT) - x_remove_base;
 
-        nr_range = x86_get_mtrr_mem_range(range, 0, x_remove_base, x_remove_size);
         /*
          * [0, 1M) should always be covered by var mtrr with WB
          * and fixed mtrrs should take effect before var mtrr for it:
          */
-        nr_range = add_range_with_merge(range, RANGE_NUM, nr_range, 0,
+        nr_range = add_range_with_merge(range, RANGE_NUM, 0, 0,
                                         1ULL<<(20 - PAGE_SHIFT));
-        /* Sort the ranges: */
-        sort_range(range, nr_range);
+        /* add from var mtrr at last */
+        nr_range = x86_get_mtrr_mem_range(range, nr_range,
+                                          x_remove_base, x_remove_size);
 
         range_sums = sum_ranges(range, nr_range);
         printk(KERN_INFO "total RAM covered: %ldM\n",
diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c
index 68a3343e5798..9e451b0876b5 100644
--- a/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ b/arch/x86/kernel/cpu/mtrr/cyrix.c
@@ -167,7 +167,7 @@ static void post_set(void)
         setCx86(CX86_CCR3, ccr3);
 
         /* Enable caches */
-        write_cr0(read_cr0() & 0xbfffffff);
+        write_cr0(read_cr0() & ~X86_CR0_CD);
 
         /* Restore value of CR4 */
         if (cpu_has_pge)
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index fa72a39e5d46..d4cdfa67509e 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -510,8 +510,9 @@ generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 static void generic_get_mtrr(unsigned int reg, unsigned long *base,
                              unsigned long *size, mtrr_type *type)
 {
-        unsigned int mask_lo, mask_hi, base_lo, base_hi;
-        unsigned int tmp, hi;
+        u32 mask_lo, mask_hi, base_lo, base_hi;
+        unsigned int hi;
+        u64 tmp, mask;
 
         /*
          * get_mtrr doesn't need to update mtrr_state, also it could be called
@@ -532,18 +533,18 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
         rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
 
         /* Work out the shifted address mask: */
-        tmp = mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
-        mask_lo = size_or_mask | tmp;
+        tmp = (u64)mask_hi << (32 - PAGE_SHIFT) | mask_lo >> PAGE_SHIFT;
+        mask = size_or_mask | tmp;
 
         /* Expand tmp with high bits to all 1s: */
-        hi = fls(tmp);
+        hi = fls64(tmp);
         if (hi > 0) {
-                tmp |= ~((1<<(hi - 1)) - 1);
+                tmp |= ~((1ULL<<(hi - 1)) - 1);
 
-                if (tmp != mask_lo) {
+                if (tmp != mask) {
                         printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
                         add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
-                        mask_lo = tmp;
+                        mask = tmp;
                 }
         }
 
@@ -551,8 +552,8 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
          * This works correctly if size is a power of two, i.e. a
          * contiguous range:
          */
-        *size = -mask_lo;
-        *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
+        *size = -mask;
+        *base = (u64)base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
         *type = base_lo & 0xff;
 
 out_put_cpu:
@@ -701,7 +702,7 @@ static void post_set(void) __releases(set_atomicity_lock)
         mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
 
         /* Enable caches */
-        write_cr0(read_cr0() & 0xbfffffff);
+        write_cr0(read_cr0() & ~X86_CR0_CD);
 
         /* Restore value of CR4 */
         if (cpu_has_pge)
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 726bf963c227..ca22b73aaa25 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -305,7 +305,8 @@ int mtrr_add_page(unsigned long base, unsigned long size,
                 return -EINVAL;
         }
 
-        if (base & size_or_mask || size & size_or_mask) {
+        if ((base | (base + size - 1)) >>
+            (boot_cpu_data.x86_phys_bits - PAGE_SHIFT)) {
                 pr_warning("mtrr: base or size exceeds the MTRR width\n");
                 return -EINVAL;
         }
@@ -583,6 +584,7 @@ static struct syscore_ops mtrr_syscore_ops = {
 
 int __initdata changed_by_mtrr_cleanup;
 
+#define SIZE_OR_MASK_BITS(n)  (~((1ULL << ((n) - PAGE_SHIFT)) - 1))
 /**
  * mtrr_bp_init - initialize mtrrs on the boot CPU
  *
@@ -600,7 +602,7 @@ void __init mtrr_bp_init(void)
 
         if (cpu_has_mtrr) {
                 mtrr_if = &generic_mtrr_ops;
-                size_or_mask = 0xff000000;                      /* 36 bits */
+                size_or_mask = SIZE_OR_MASK_BITS(36);
                 size_and_mask = 0x00f00000;
                 phys_addr = 36;
 
@@ -619,7 +621,7 @@ void __init mtrr_bp_init(void)
                              boot_cpu_data.x86_mask == 0x4))
                                 phys_addr = 36;
 
-                        size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
+                        size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
                         size_and_mask = ~size_or_mask & 0xfffff00000ULL;
                 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
                            boot_cpu_data.x86 == 6) {
@@ -627,7 +629,7 @@ void __init mtrr_bp_init(void)
                          * VIA C* family have Intel style MTRRs,
                          * but don't support PAE
                          */
-                        size_or_mask = 0xfff00000;              /* 32 bits */
+                        size_or_mask = SIZE_OR_MASK_BITS(32);
                         size_and_mask = 0;
                         phys_addr = 32;
                 }
@@ -637,21 +639,21 @@ void __init mtrr_bp_init(void)
                         if (cpu_has_k6_mtrr) {
                                 /* Pre-Athlon (K6) AMD CPU MTRRs */
                                 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;
                 case X86_VENDOR_CENTAUR:
                         if (cpu_has_centaur_mcr) {
                                 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;
                 case X86_VENDOR_CYRIX:
                         if (cpu_has_cyrix_arr) {
                                 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
-                                size_or_mask = 0xfff00000;      /* 32 bits */
+                                size_or_mask = SIZE_OR_MASK_BITS(32);
                                 size_and_mask = 0;
                         }
                         break;
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 1025f3c99d20..9e581c5cf6d0 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -403,7 +403,8 @@ int x86_pmu_hw_config(struct perf_event *event)
                  * check that PEBS LBR correction does not conflict with
                  * whatever the user is asking with attr->branch_sample_type
                  */
-                if (event->attr.precise_ip > 1) {
+                if (event->attr.precise_ip > 1 &&
+                    x86_pmu.intel_cap.pebs_format < 2) {
                         u64 *br_type = &event->attr.branch_sample_type;
 
                         if (has_branch_stack(event)) {
@@ -568,7 +569,7 @@ struct sched_state {
 struct perf_sched {
         int                     max_weight;
         int                     max_events;
-        struct event_constraint **constraints;
+        struct perf_event       **events;
         struct sched_state      state;
         int                     saved_states;
         struct sched_state      saved[SCHED_STATES_MAX];
@@ -577,7 +578,7 @@ struct perf_sched {
 /*
  * Initialize interator that runs through all events and counters.
  */
-static void perf_sched_init(struct perf_sched *sched, struct event_constraint **c,
+static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
                             int num, int wmin, int wmax)
 {
         int idx;
@@ -585,10 +586,10 @@ static void perf_sched_init(struct perf_sched *sched, struct event_constraint **
         memset(sched, 0, sizeof(*sched));
         sched->max_events       = num;
         sched->max_weight       = wmax;
-        sched->constraints      = c;
+        sched->events           = events;
 
         for (idx = 0; idx < num; idx++) {
-                if (c[idx]->weight == wmin)
+                if (events[idx]->hw.constraint->weight == wmin)
                         break;
         }
 
@@ -635,8 +636,7 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         if (sched->state.event >= sched->max_events)
                 return false;
 
-        c = sched->constraints[sched->state.event];
-
+        c = sched->events[sched->state.event]->hw.constraint;
         /* Prefer fixed purpose counters */
         if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
                 idx = INTEL_PMC_IDX_FIXED;
@@ -694,7 +694,7 @@ static bool perf_sched_next_event(struct perf_sched *sched)
                         if (sched->state.weight > sched->max_weight)
                                 return false;
                 }
-                c = sched->constraints[sched->state.event];
+                c = sched->events[sched->state.event]->hw.constraint;
         } while (c->weight != sched->state.weight);
 
         sched->state.counter = 0;       /* start with first counter */
@@ -705,12 +705,12 @@ static bool perf_sched_next_event(struct perf_sched *sched)
 /*
  * Assign a counter for each event.
  */
-int perf_assign_events(struct event_constraint **constraints, int n,
+int perf_assign_events(struct perf_event **events, int n,
                         int wmin, int wmax, int *assign)
 {
         struct perf_sched sched;
 
-        perf_sched_init(&sched, constraints, n, wmin, wmax);
+        perf_sched_init(&sched, events, n, wmin, wmax);
 
         do {
                 if (!perf_sched_find_counter(&sched))
@@ -724,16 +724,19 @@ int perf_assign_events(struct event_constraint **constraints, int n,
 
 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 {
-        struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
+        struct event_constraint *c;
         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+        struct perf_event *e;
         int i, wmin, wmax, num = 0;
         struct hw_perf_event *hwc;
 
         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 
         for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
+                hwc = &cpuc->event_list[i]->hw;
                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
-                constraints[i] = c;
+                hwc->constraint = c;
+
                 wmin = min(wmin, c->weight);
                 wmax = max(wmax, c->weight);
         }
@@ -743,7 +746,7 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
          */
         for (i = 0; i < n; i++) {
                 hwc = &cpuc->event_list[i]->hw;
-                c = constraints[i];
+                c = hwc->constraint;
 
                 /* never assigned */
                 if (hwc->idx == -1)
@@ -764,16 +767,35 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 
         /* slow path */
         if (i != n)
-                num = perf_assign_events(constraints, n, wmin, wmax, assign);
+                num = perf_assign_events(cpuc->event_list, n, wmin,
+                                         wmax, assign);
 
         /*
+         * Mark the event as committed, so we do not put_constraint()
+         * in case new events are added and fail scheduling.
+         */
+        if (!num && assign) {
+                for (i = 0; i < n; i++) {
+                        e = cpuc->event_list[i];
+                        e->hw.flags |= PERF_X86_EVENT_COMMITTED;
+                }
+        }
+        /*
          * scheduling failed or is just a simulation,
          * free resources if necessary
          */
         if (!assign || num) {
                 for (i = 0; i < n; i++) {
+                        e = cpuc->event_list[i];
+                        /*
+                         * do not put_constraint() on comitted events,
+                         * because they are good to go
+                         */
+                        if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
+                                continue;
+
                         if (x86_pmu.put_event_constraints)
-                                x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
+                                x86_pmu.put_event_constraints(cpuc, e);
                 }
         }
         return num ? -EINVAL : 0;
@@ -1153,6 +1175,11 @@ static void x86_pmu_del(struct perf_event *event, int flags)
         int i;
 
         /*
+         * event is descheduled
+         */
+        event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
+
+        /*
          * If we're called during a txn, we don't need to do anything.
          * The events never got scheduled and ->cancel_txn will truncate
          * the event_list.
@@ -1249,10 +1276,20 @@ void perf_events_lapic_init(void)
 static int __kprobes
 perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
 {
+        int ret;
+        u64 start_clock;
+        u64 finish_clock;
+
         if (!atomic_read(&active_events))
                 return NMI_DONE;
 
-        return x86_pmu.handle_irq(regs);
+        start_clock = local_clock();
+        ret = x86_pmu.handle_irq(regs);
+        finish_clock = local_clock();
+
+        perf_sample_event_took(finish_clock - start_clock);
+
+        return ret;
 }
 
 struct event_constraint emptyconstraint;
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index ba9aadfa683b..97e557bc4c91 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -63,10 +63,12 @@ struct event_constraint {
         int     flags;
 };
 /*
- * struct event_constraint flags
+ * struct hw_perf_event.flags flags
  */
 #define PERF_X86_EVENT_PEBS_LDLAT       0x1 /* ld+ldlat data address sampling */
 #define PERF_X86_EVENT_PEBS_ST          0x2 /* st data address sampling */
+#define PERF_X86_EVENT_PEBS_ST_HSW      0x4 /* haswell style st data sampling */
+#define PERF_X86_EVENT_COMMITTED        0x8 /* event passed commit_txn */
 
 struct amd_nb {
         int nb_id;  /* NorthBridge id */
@@ -227,11 +229,14 @@ struct cpu_hw_events {
  *  - inv
  *  - edge
  *  - cnt-mask
+ *  - in_tx
+ *  - in_tx_checkpointed
  *  The other filters are supported by fixed counters.
  *  The any-thread option is supported starting with v3.
  */
+#define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
 #define FIXED_EVENT_CONSTRAINT(c, n)    \
-        EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
+        EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
 
 /*
  * Constraint on the Event code + UMask
@@ -247,6 +252,11 @@ struct cpu_hw_events {
         __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
                           HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
 
+/* DataLA version of store sampling without extra enable bit. */
+#define INTEL_PST_HSW_CONSTRAINT(c, n)  \
+        __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
+                          HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
+
 #define EVENT_CONSTRAINT_END            \
         EVENT_CONSTRAINT(0, 0, 0)
 
@@ -301,6 +311,11 @@ union perf_capabilities {
                 u64     pebs_arch_reg:1;
                 u64     pebs_format:4;
                 u64     smm_freeze:1;
+                /*
+                 * PMU supports separate counter range for writing
+                 * values > 32bit.
+                 */
+                u64     full_width_write:1;
         };
         u64     capabilities;
 };
@@ -375,6 +390,7 @@ struct x86_pmu {
         struct event_constraint *event_constraints;
         struct x86_pmu_quirk *quirks;
         int             perfctr_second_write;
+        bool            late_ack;
 
         /*
          * sysfs attrs
@@ -528,7 +544,7 @@ static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 
 void x86_pmu_enable_all(int added);
 
-int perf_assign_events(struct event_constraint **constraints, int n,
+int perf_assign_events(struct perf_event **events, int n,
                         int wmin, int wmax, int *assign);
 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
 
@@ -633,6 +649,8 @@ extern struct event_constraint intel_snb_pebs_event_constraints[];
 
 extern struct event_constraint intel_ivb_pebs_event_constraints[];
 
+extern struct event_constraint intel_hsw_pebs_event_constraints[];
+
 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
 
 void intel_pmu_pebs_enable(struct perf_event *event);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 7e28d9467bb4..4cbe03287b08 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -648,48 +648,48 @@ static __initconst const struct x86_pmu amd_pmu = {
         .cpu_dead               = amd_pmu_cpu_dead,
 };
 
-static int setup_event_constraints(void)
+static int __init amd_core_pmu_init(void)
 {
-        if (boot_cpu_data.x86 == 0x15)
+        if (!cpu_has_perfctr_core)
+                return 0;
+
+        switch (boot_cpu_data.x86) {
+        case 0x15:
+                pr_cont("Fam15h ");
                 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
-        return 0;
-}
+                break;
 
-static int setup_perfctr_core(void)
-{
-        if (!cpu_has_perfctr_core) {
-                WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h,
-                     KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!");
+        default:
+                pr_err("core perfctr but no constraints; unknown hardware!\n");
                 return -ENODEV;
         }
 
-        WARN(x86_pmu.get_event_constraints == amd_get_event_constraints,
-             KERN_ERR "hw perf events core counters need constraints handler!");
-
         /*
          * If core performance counter extensions exists, we must use
          * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
-         * x86_pmu_addr_offset().
+         * amd_pmu_addr_offset().
          */
         x86_pmu.eventsel        = MSR_F15H_PERF_CTL;
         x86_pmu.perfctr         = MSR_F15H_PERF_CTR;
         x86_pmu.num_counters    = AMD64_NUM_COUNTERS_CORE;
 
-        printk(KERN_INFO "perf: AMD core performance counters detected\n");
-
+        pr_cont("core perfctr, ");
         return 0;
 }
 
 __init int amd_pmu_init(void)
 {
+        int ret;
+
         /* Performance-monitoring supported from K7 and later: */
         if (boot_cpu_data.x86 < 6)
                 return -ENODEV;
 
         x86_pmu = amd_pmu;
 
-        setup_event_constraints();
-        setup_perfctr_core();
+        ret = amd_core_pmu_init();
+        if (ret)
+                return ret;
 
         /* Events are common for all AMDs */
         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
diff --git a/arch/x86/kernel/cpu/perf_event_amd_iommu.c b/arch/x86/kernel/cpu/perf_event_amd_iommu.c
new file mode 100644
index 000000000000..0db655ef3918
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_amd_iommu.c
@@ -0,0 +1,504 @@
+/*
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ *
+ * Author: Steven Kinney <Steven.Kinney@amd.com>
+ * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
+ *
+ * Perf: amd_iommu - AMD IOMMU Performance Counter PMU implementation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/perf_event.h>
+#include <linux/module.h>
+#include <linux/cpumask.h>
+#include <linux/slab.h>
+
+#include "perf_event.h"
+#include "perf_event_amd_iommu.h"
+
+#define COUNTER_SHIFT           16
+
+#define _GET_BANK(ev)       ((u8)(ev->hw.extra_reg.reg >> 8))
+#define _GET_CNTR(ev)       ((u8)(ev->hw.extra_reg.reg))
+
+/* iommu pmu config masks */
+#define _GET_CSOURCE(ev)    ((ev->hw.config & 0xFFULL))
+#define _GET_DEVID(ev)      ((ev->hw.config >> 8)  & 0xFFFFULL)
+#define _GET_PASID(ev)      ((ev->hw.config >> 24) & 0xFFFFULL)
+#define _GET_DOMID(ev)      ((ev->hw.config >> 40) & 0xFFFFULL)
+#define _GET_DEVID_MASK(ev) ((ev->hw.extra_reg.config)  & 0xFFFFULL)
+#define _GET_PASID_MASK(ev) ((ev->hw.extra_reg.config >> 16) & 0xFFFFULL)
+#define _GET_DOMID_MASK(ev) ((ev->hw.extra_reg.config >> 32) & 0xFFFFULL)
+
+static struct perf_amd_iommu __perf_iommu;
+
+struct perf_amd_iommu {
+        struct pmu pmu;
+        u8 max_banks;
+        u8 max_counters;
+        u64 cntr_assign_mask;
+        raw_spinlock_t lock;
+        const struct attribute_group *attr_groups[4];
+};
+
+#define format_group    attr_groups[0]
+#define cpumask_group   attr_groups[1]
+#define events_group    attr_groups[2]
+#define null_group      attr_groups[3]
+
+/*---------------------------------------------
+ * sysfs format attributes
+ *---------------------------------------------*/
+PMU_FORMAT_ATTR(csource,    "config:0-7");
+PMU_FORMAT_ATTR(devid,      "config:8-23");
+PMU_FORMAT_ATTR(pasid,      "config:24-39");
+PMU_FORMAT_ATTR(domid,      "config:40-55");
+PMU_FORMAT_ATTR(devid_mask, "config1:0-15");
+PMU_FORMAT_ATTR(pasid_mask, "config1:16-31");
+PMU_FORMAT_ATTR(domid_mask, "config1:32-47");
+
+static struct attribute *iommu_format_attrs[] = {
+        &format_attr_csource.attr,
+        &format_attr_devid.attr,
+        &format_attr_pasid.attr,
+        &format_attr_domid.attr,
+        &format_attr_devid_mask.attr,
+        &format_attr_pasid_mask.attr,
+        &format_attr_domid_mask.attr,
+        NULL,
+};
+
+static struct attribute_group amd_iommu_format_group = {
+        .name = "format",
+        .attrs = iommu_format_attrs,
+};
+
+/*---------------------------------------------
+ * sysfs events attributes
+ *---------------------------------------------*/
+struct amd_iommu_event_desc {
+        struct kobj_attribute attr;
+        const char *event;
+};
+
+static ssize_t _iommu_event_show(struct kobject *kobj,
+                                struct kobj_attribute *attr, char *buf)
+{
+        struct amd_iommu_event_desc *event =
+                container_of(attr, struct amd_iommu_event_desc, attr);
+        return sprintf(buf, "%s\n", event->event);
+}
+
+#define AMD_IOMMU_EVENT_DESC(_name, _event)                     \
+{                                                               \
+        .attr  = __ATTR(_name, 0444, _iommu_event_show, NULL),  \
+        .event = _event,                                        \
+}
+
+static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
+        AMD_IOMMU_EVENT_DESC(mem_pass_untrans,        "csource=0x01"),
+        AMD_IOMMU_EVENT_DESC(mem_pass_pretrans,       "csource=0x02"),
+        AMD_IOMMU_EVENT_DESC(mem_pass_excl,           "csource=0x03"),
+        AMD_IOMMU_EVENT_DESC(mem_target_abort,        "csource=0x04"),
+        AMD_IOMMU_EVENT_DESC(mem_trans_total,         "csource=0x05"),
+        AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_hit,   "csource=0x06"),
+        AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pte_mis,   "csource=0x07"),
+        AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_hit,   "csource=0x08"),
+        AMD_IOMMU_EVENT_DESC(mem_iommu_tlb_pde_mis,   "csource=0x09"),
+        AMD_IOMMU_EVENT_DESC(mem_dte_hit,             "csource=0x0a"),
+        AMD_IOMMU_EVENT_DESC(mem_dte_mis,             "csource=0x0b"),
+        AMD_IOMMU_EVENT_DESC(page_tbl_read_tot,       "csource=0x0c"),
+        AMD_IOMMU_EVENT_DESC(page_tbl_read_nst,       "csource=0x0d"),
+        AMD_IOMMU_EVENT_DESC(page_tbl_read_gst,       "csource=0x0e"),
+        AMD_IOMMU_EVENT_DESC(int_dte_hit,             "csource=0x0f"),
+        AMD_IOMMU_EVENT_DESC(int_dte_mis,             "csource=0x10"),
+        AMD_IOMMU_EVENT_DESC(cmd_processed,           "csource=0x11"),
+        AMD_IOMMU_EVENT_DESC(cmd_processed_inv,       "csource=0x12"),
+        AMD_IOMMU_EVENT_DESC(tlb_inv,                 "csource=0x13"),
+        { /* end: all zeroes */ },
+};
+
+/*---------------------------------------------
+ * sysfs cpumask attributes
+ *---------------------------------------------*/
+static cpumask_t iommu_cpumask;
+
+static ssize_t _iommu_cpumask_show(struct device *dev,
+                                   struct device_attribute *attr,
+                                   char *buf)
+{
+        int n = cpulist_scnprintf(buf, PAGE_SIZE - 2, &iommu_cpumask);
+        buf[n++] = '\n';
+        buf[n] = '\0';
+        return n;
+}
+static DEVICE_ATTR(cpumask, S_IRUGO, _iommu_cpumask_show, NULL);
+
+static struct attribute *iommu_cpumask_attrs[] = {
+        &dev_attr_cpumask.attr,
+        NULL,
+};
+
+static struct attribute_group amd_iommu_cpumask_group = {
+        .attrs = iommu_cpumask_attrs,
+};
+
+/*---------------------------------------------*/
+
+static int get_next_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu)
+{
+        unsigned long flags;
+        int shift, bank, cntr, retval;
+        int max_banks = perf_iommu->max_banks;
+        int max_cntrs = perf_iommu->max_counters;
+
+        raw_spin_lock_irqsave(&perf_iommu->lock, flags);
+
+        for (bank = 0, shift = 0; bank < max_banks; bank++) {
+                for (cntr = 0; cntr < max_cntrs; cntr++) {
+                        shift = bank + (bank*3) + cntr;
+                        if (perf_iommu->cntr_assign_mask & (1ULL<<shift)) {
+                                continue;
+                        } else {
+                                perf_iommu->cntr_assign_mask |= (1ULL<<shift);
+                                retval = ((u16)((u16)bank<<8) | (u8)(cntr));
+                                goto out;
+                        }
+                }
+        }
+        retval = -ENOSPC;
+out:
+        raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
+        return retval;
+}
+
+static int clear_avail_iommu_bnk_cntr(struct perf_amd_iommu *perf_iommu,
+                                        u8 bank, u8 cntr)
+{
+        unsigned long flags;
+        int max_banks, max_cntrs;
+        int shift = 0;
+
+        max_banks = perf_iommu->max_banks;
+        max_cntrs = perf_iommu->max_counters;
+
+        if ((bank > max_banks) || (cntr > max_cntrs))
+                return -EINVAL;
+
+        shift = bank + cntr + (bank*3);
+
+        raw_spin_lock_irqsave(&perf_iommu->lock, flags);
+        perf_iommu->cntr_assign_mask &= ~(1ULL<<shift);
+        raw_spin_unlock_irqrestore(&perf_iommu->lock, flags);
+
+        return 0;
+}
+
+static int perf_iommu_event_init(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct perf_amd_iommu *perf_iommu;
+        u64 config, config1;
+
+        /* test the event attr type check for PMU enumeration */
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+
+        /*
+         * IOMMU counters are shared across all cores.
+         * Therefore, it does not support per-process mode.
+         * Also, it does not support event sampling mode.
+         */
+        if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
+                return -EINVAL;
+
+        /* IOMMU counters do not have usr/os/guest/host bits */
+        if (event->attr.exclude_user || event->attr.exclude_kernel ||
+            event->attr.exclude_host || event->attr.exclude_guest)
+                return -EINVAL;
+
+        if (event->cpu < 0)
+                return -EINVAL;
+
+        perf_iommu = &__perf_iommu;
+
+        if (event->pmu != &perf_iommu->pmu)
+                return -ENOENT;
+
+        if (perf_iommu) {
+                config = event->attr.config;
+                config1 = event->attr.config1;
+        } else {
+                return -EINVAL;
+        }
+
+        /* integrate with iommu base devid (0000), assume one iommu */
+        perf_iommu->max_banks =
+                amd_iommu_pc_get_max_banks(IOMMU_BASE_DEVID);
+        perf_iommu->max_counters =
+                amd_iommu_pc_get_max_counters(IOMMU_BASE_DEVID);
+        if ((perf_iommu->max_banks == 0) || (perf_iommu->max_counters == 0))
+                return -EINVAL;
+
+        /* update the hw_perf_event struct with the iommu config data */
+        hwc->config = config;
+        hwc->extra_reg.config = config1;
+
+        return 0;
+}
+
+static void perf_iommu_enable_event(struct perf_event *ev)
+{
+        u8 csource = _GET_CSOURCE(ev);
+        u16 devid = _GET_DEVID(ev);
+        u64 reg = 0ULL;
+
+        reg = csource;
+        amd_iommu_pc_get_set_reg_val(devid,
+                        _GET_BANK(ev), _GET_CNTR(ev) ,
+                         IOMMU_PC_COUNTER_SRC_REG, &reg, true);
+
+        reg = 0ULL | devid | (_GET_DEVID_MASK(ev) << 32);
+        if (reg)
+                reg |= (1UL << 31);
+        amd_iommu_pc_get_set_reg_val(devid,
+                        _GET_BANK(ev), _GET_CNTR(ev) ,
+                         IOMMU_PC_DEVID_MATCH_REG, &reg, true);
+
+        reg = 0ULL | _GET_PASID(ev) | (_GET_PASID_MASK(ev) << 32);
+        if (reg)
+                reg |= (1UL << 31);
+        amd_iommu_pc_get_set_reg_val(devid,
+                        _GET_BANK(ev), _GET_CNTR(ev) ,
+                         IOMMU_PC_PASID_MATCH_REG, &reg, true);
+
+        reg = 0ULL | _GET_DOMID(ev) | (_GET_DOMID_MASK(ev) << 32);
+        if (reg)
+                reg |= (1UL << 31);
+        amd_iommu_pc_get_set_reg_val(devid,
+                        _GET_BANK(ev), _GET_CNTR(ev) ,
+                         IOMMU_PC_DOMID_MATCH_REG, &reg, true);
+}
+
+static void perf_iommu_disable_event(struct perf_event *event)
+{
+        u64 reg = 0ULL;
+
+        amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
+                        _GET_BANK(event), _GET_CNTR(event),
+                        IOMMU_PC_COUNTER_SRC_REG, &reg, true);
+}
+
+static void perf_iommu_start(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        pr_debug("perf: amd_iommu:perf_iommu_start\n");
+        if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
+                return;
+
+        WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
+        hwc->state = 0;
+
+        if (flags & PERF_EF_RELOAD) {
+                u64 prev_raw_count =  local64_read(&hwc->prev_count);
+                amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
+                                _GET_BANK(event), _GET_CNTR(event),
+                                IOMMU_PC_COUNTER_REG, &prev_raw_count, true);
+        }
+
+        perf_iommu_enable_event(event);
+        perf_event_update_userpage(event);
+
+}
+
+static void perf_iommu_read(struct perf_event *event)
+{
+        u64 count = 0ULL;
+        u64 prev_raw_count = 0ULL;
+        u64 delta = 0ULL;
+        struct hw_perf_event *hwc = &event->hw;
+        pr_debug("perf: amd_iommu:perf_iommu_read\n");
+
+        amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
+                                _GET_BANK(event), _GET_CNTR(event),
+                                IOMMU_PC_COUNTER_REG, &count, false);
+
+        /* IOMMU pc counter register is only 48 bits */
+        count &= 0xFFFFFFFFFFFFULL;
+
+        prev_raw_count =  local64_read(&hwc->prev_count);
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                                        count) != prev_raw_count)
+                return;
+
+        /* Handling 48-bit counter overflowing */
+        delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
+        delta >>= COUNTER_SHIFT;
+        local64_add(delta, &event->count);
+
+}
+
+static void perf_iommu_stop(struct perf_event *event, int flags)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        u64 config;
+
+        pr_debug("perf: amd_iommu:perf_iommu_stop\n");
+
+        if (hwc->state & PERF_HES_UPTODATE)
+                return;
+
+        perf_iommu_disable_event(event);
+        WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+        hwc->state |= PERF_HES_STOPPED;
+
+        if (hwc->state & PERF_HES_UPTODATE)
+                return;
+
+        config = hwc->config;
+        perf_iommu_read(event);
+        hwc->state |= PERF_HES_UPTODATE;
+}
+
+static int perf_iommu_add(struct perf_event *event, int flags)
+{
+        int retval;
+        struct perf_amd_iommu *perf_iommu =
+                        container_of(event->pmu, struct perf_amd_iommu, pmu);
+
+        pr_debug("perf: amd_iommu:perf_iommu_add\n");
+        event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+
+        /* request an iommu bank/counter */
+        retval = get_next_avail_iommu_bnk_cntr(perf_iommu);
+        if (retval != -ENOSPC)
+                event->hw.extra_reg.reg = (u16)retval;
+        else
+                return retval;
+
+        if (flags & PERF_EF_START)
+                perf_iommu_start(event, PERF_EF_RELOAD);
+
+        return 0;
+}
+
+static void perf_iommu_del(struct perf_event *event, int flags)
+{
+        struct perf_amd_iommu *perf_iommu =
+                        container_of(event->pmu, struct perf_amd_iommu, pmu);
+
+        pr_debug("perf: amd_iommu:perf_iommu_del\n");
+        perf_iommu_stop(event, PERF_EF_UPDATE);
+
+        /* clear the assigned iommu bank/counter */
+        clear_avail_iommu_bnk_cntr(perf_iommu,
+                                     _GET_BANK(event),
+                                     _GET_CNTR(event));
+
+        perf_event_update_userpage(event);
+}
+
+static __init int _init_events_attrs(struct perf_amd_iommu *perf_iommu)
+{
+        struct attribute **attrs;
+        struct attribute_group *attr_group;
+        int i = 0, j;
+
+        while (amd_iommu_v2_event_descs[i].attr.attr.name)
+                i++;
+
+        attr_group = kzalloc(sizeof(struct attribute *)
+                * (i + 1) + sizeof(*attr_group), GFP_KERNEL);
+        if (!attr_group)
+                return -ENOMEM;
+
+        attrs = (struct attribute **)(attr_group + 1);
+        for (j = 0; j < i; j++)
+                attrs[j] = &amd_iommu_v2_event_descs[j].attr.attr;
+
+        attr_group->name = "events";
+        attr_group->attrs = attrs;
+        perf_iommu->events_group = attr_group;
+
+        return 0;
+}
+
+static __init void amd_iommu_pc_exit(void)
+{
+        if (__perf_iommu.events_group != NULL) {
+                kfree(__perf_iommu.events_group);
+                __perf_iommu.events_group = NULL;
+        }
+}
+
+static __init int _init_perf_amd_iommu(
+        struct perf_amd_iommu *perf_iommu, char *name)
+{
+        int ret;
+
+        raw_spin_lock_init(&perf_iommu->lock);
+
+        /* Init format attributes */
+        perf_iommu->format_group = &amd_iommu_format_group;
+
+        /* Init cpumask attributes to only core 0 */
+        cpumask_set_cpu(0, &iommu_cpumask);
+        perf_iommu->cpumask_group = &amd_iommu_cpumask_group;
+
+        /* Init events attributes */
+        if (_init_events_attrs(perf_iommu) != 0)
+                pr_err("perf: amd_iommu: Only support raw events.\n");
+
+        /* Init null attributes */
+        perf_iommu->null_group = NULL;
+        perf_iommu->pmu.attr_groups = perf_iommu->attr_groups;
+
+        ret = perf_pmu_register(&perf_iommu->pmu, name, -1);
+        if (ret) {
+                pr_err("perf: amd_iommu: Failed to initialized.\n");
+                amd_iommu_pc_exit();
+        } else {
+                pr_info("perf: amd_iommu: Detected. (%d banks, %d counters/bank)\n",
+                        amd_iommu_pc_get_max_banks(IOMMU_BASE_DEVID),
+                        amd_iommu_pc_get_max_counters(IOMMU_BASE_DEVID));
+        }
+
+        return ret;
+}
+
+static struct perf_amd_iommu __perf_iommu = {
+        .pmu = {
+                .event_init     = perf_iommu_event_init,
+                .add            = perf_iommu_add,
+                .del            = perf_iommu_del,
+                .start          = perf_iommu_start,
+                .stop           = perf_iommu_stop,
+                .read           = perf_iommu_read,
+        },
+        .max_banks              = 0x00,
+        .max_counters           = 0x00,
+        .cntr_assign_mask       = 0ULL,
+        .format_group           = NULL,
+        .cpumask_group          = NULL,
+        .events_group           = NULL,
+        .null_group             = NULL,
+};
+
+static __init int amd_iommu_pc_init(void)
+{
+        /* Make sure the IOMMU PC resource is available */
+        if (!amd_iommu_pc_supported()) {
+                pr_err("perf: amd_iommu PMU not installed. No support!\n");
+                return -ENODEV;
+        }
+
+        _init_perf_amd_iommu(&__perf_iommu, "amd_iommu");
+
+        return 0;
+}
+
+device_initcall(amd_iommu_pc_init);
diff --git a/arch/x86/kernel/cpu/perf_event_amd_iommu.h b/arch/x86/kernel/cpu/perf_event_amd_iommu.h
new file mode 100644
index 000000000000..845d173278e3
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_amd_iommu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ *
+ * Author: Steven Kinney <Steven.Kinney@amd.com>
+ * Author: Suravee Suthikulpanit <Suraveee.Suthikulpanit@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _PERF_EVENT_AMD_IOMMU_H_
+#define _PERF_EVENT_AMD_IOMMU_H_
+
+/* iommu pc mmio region register indexes */
+#define IOMMU_PC_COUNTER_REG                    0x00
+#define IOMMU_PC_COUNTER_SRC_REG                0x08
+#define IOMMU_PC_PASID_MATCH_REG                0x10
+#define IOMMU_PC_DOMID_MATCH_REG                0x18
+#define IOMMU_PC_DEVID_MATCH_REG                0x20
+#define IOMMU_PC_COUNTER_REPORT_REG             0x28
+
+/* maximun specified bank/counters */
+#define PC_MAX_SPEC_BNKS                        64
+#define PC_MAX_SPEC_CNTRS                       16
+
+/* iommu pc reg masks*/
+#define IOMMU_BASE_DEVID                        0x0000
+
+/* amd_iommu_init.c external support functions */
+extern bool amd_iommu_pc_supported(void);
+
+extern u8 amd_iommu_pc_get_max_banks(u16 devid);
+
+extern u8 amd_iommu_pc_get_max_counters(u16 devid);
+
+extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr,
+                        u8 fxn, u64 *value, bool is_write);
+
+#endif /*_PERF_EVENT_AMD_IOMMU_H_*/
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index f60d41ff9a97..fbc9210b45bc 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/export.h>
 
+#include <asm/cpufeature.h>
 #include <asm/hardirq.h>
 #include <asm/apic.h>
 
@@ -165,13 +166,13 @@ static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
         INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
-        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
         EVENT_EXTRA_END
 };
 
 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
         INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
         INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
+        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
         EVENT_EXTRA_END
 };
 
@@ -190,6 +191,22 @@ struct attribute *snb_events_attrs[] = {
         NULL,
 };
 
+static struct event_constraint intel_hsw_event_constraints[] = {
+        FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+        FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
+        FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
+        INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.* */
+        INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
+        INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
+        /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
+        INTEL_EVENT_CONSTRAINT(0x08a3, 0x4),
+        /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
+        INTEL_EVENT_CONSTRAINT(0x0ca3, 0x4),
+        /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
+        INTEL_EVENT_CONSTRAINT(0x04a3, 0xf),
+        EVENT_CONSTRAINT_END
+};
+
 static u64 intel_pmu_event_map(int hw_event)
 {
         return intel_perfmon_event_map[hw_event];
@@ -872,7 +889,8 @@ static inline bool intel_pmu_needs_lbr_smpl(struct perf_event *event)
                 return true;
 
         /* implicit branch sampling to correct PEBS skid */
-        if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
+        if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1 &&
+            x86_pmu.intel_cap.pebs_format < 2)
                 return true;
 
         return false;
@@ -1167,15 +1185,11 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         cpuc = &__get_cpu_var(cpu_hw_events);
 
         /*
-         * Some chipsets need to unmask the LVTPC in a particular spot
-         * inside the nmi handler.  As a result, the unmasking was pushed
-         * into all the nmi handlers.
-         *
-         * This handler doesn't seem to have any issues with the unmasking
-         * so it was left at the top.
+         * No known reason to not always do late ACK,
+         * but just in case do it opt-in.
          */
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-
+        if (!x86_pmu.late_ack)
+                apic_write(APIC_LVTPC, APIC_DM_NMI);
         intel_pmu_disable_all();
         handled = intel_pmu_drain_bts_buffer();
         status = intel_pmu_get_status();
@@ -1188,8 +1202,12 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
 again:
         intel_pmu_ack_status(status);
         if (++loops > 100) {
-                WARN_ONCE(1, "perfevents: irq loop stuck!\n");
-                perf_event_print_debug();
+                static bool warned = false;
+                if (!warned) {
+                        WARN(1, "perfevents: irq loop stuck!\n");
+                        perf_event_print_debug();
+                        warned = true;
+                }
                 intel_pmu_reset();
                 goto done;
         }
@@ -1235,6 +1253,13 @@ again:
 
 done:
         intel_pmu_enable_all(0);
+        /*
+         * Only unmask the NMI after the overflow counters
+         * have been reset. This avoids spurious NMIs on
+         * Haswell CPUs.
+         */
+        if (x86_pmu.late_ack)
+                apic_write(APIC_LVTPC, APIC_DM_NMI);
         return handled;
 }
 
@@ -1425,7 +1450,6 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
         if (x86_pmu.event_constraints) {
                 for_each_event_constraint(c, x86_pmu.event_constraints) {
                         if ((event->hw.config & c->cmask) == c->code) {
-                                /* hw.flags zeroed at initialization */
                                 event->hw.flags |= c->flags;
                                 return c;
                         }
@@ -1473,7 +1497,6 @@ intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
                                         struct perf_event *event)
 {
-        event->hw.flags = 0;
         intel_put_shared_regs_event_constraints(cpuc, event);
 }
 
@@ -1646,6 +1669,47 @@ static void core_pmu_enable_all(int added)
         }
 }
 
+static int hsw_hw_config(struct perf_event *event)
+{
+        int ret = intel_pmu_hw_config(event);
+
+        if (ret)
+                return ret;
+        if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
+                return 0;
+        event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
+
+        /*
+         * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
+         * PEBS or in ANY thread mode. Since the results are non-sensical forbid
+         * this combination.
+         */
+        if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
+             ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
+              event->attr.precise_ip > 0))
+                return -EOPNOTSUPP;
+
+        return 0;
+}
+
+static struct event_constraint counter2_constraint =
+                        EVENT_CONSTRAINT(0, 0x4, 0);
+
+static struct event_constraint *
+hsw_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+        struct event_constraint *c = intel_get_event_constraints(cpuc, event);
+
+        /* Handle special quirk on in_tx_checkpointed only in counter 2 */
+        if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
+                if (c->idxmsk64 & (1U << 2))
+                        return &counter2_constraint;
+                return &emptyconstraint;
+        }
+
+        return c;
+}
+
 PMU_FORMAT_ATTR(event,  "config:0-7"    );
 PMU_FORMAT_ATTR(umask,  "config:8-15"   );
 PMU_FORMAT_ATTR(edge,   "config:18"     );
@@ -1653,6 +1717,8 @@ PMU_FORMAT_ATTR(pc,	"config:19"	);
 PMU_FORMAT_ATTR(any,    "config:21"     ); /* v3 + */
 PMU_FORMAT_ATTR(inv,    "config:23"     );
 PMU_FORMAT_ATTR(cmask,  "config:24-31"  );
+PMU_FORMAT_ATTR(in_tx,  "config:32");
+PMU_FORMAT_ATTR(in_tx_cp, "config:33");
 
 static struct attribute *intel_arch_formats_attr[] = {
         &format_attr_event.attr,
@@ -1807,6 +1873,8 @@ static struct attribute *intel_arch3_formats_attr[] = {
         &format_attr_any.attr,
         &format_attr_inv.attr,
         &format_attr_cmask.attr,
+        &format_attr_in_tx.attr,
+        &format_attr_in_tx_cp.attr,
 
         &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
         &format_attr_ldlat.attr, /* PEBS load latency */
@@ -1966,6 +2034,15 @@ static __init void intel_nehalem_quirk(void)
         }
 }
 
+EVENT_ATTR_STR(mem-loads,      mem_ld_hsw,     "event=0xcd,umask=0x1,ldlat=3");
+EVENT_ATTR_STR(mem-stores,     mem_st_hsw,     "event=0xd0,umask=0x82")
+
+static struct attribute *hsw_events_attrs[] = {
+        EVENT_PTR(mem_ld_hsw),
+        EVENT_PTR(mem_st_hsw),
+        NULL
+};
+
 __init int intel_pmu_init(void)
 {
         union cpuid10_edx edx;
@@ -2189,6 +2266,30 @@ __init int intel_pmu_init(void)
                 break;
 
 
+        case 60: /* Haswell Client */
+        case 70:
+        case 71:
+        case 63:
+                x86_pmu.late_ack = true;
+                memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
+                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+
+                intel_pmu_lbr_init_snb();
+
+                x86_pmu.event_constraints = intel_hsw_event_constraints;
+                x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
+                x86_pmu.extra_regs = intel_snb_extra_regs;
+                x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
+                /* all extra regs are per-cpu when HT is on */
+                x86_pmu.er_flags |= ERF_HAS_RSP_1;
+                x86_pmu.er_flags |= ERF_NO_HT_SHARING;
+
+                x86_pmu.hw_config = hsw_hw_config;
+                x86_pmu.get_event_constraints = hsw_get_event_constraints;
+                x86_pmu.cpu_events = hsw_events_attrs;
+                pr_cont("Haswell events, ");
+                break;
+
         default:
                 switch (x86_pmu.version) {
                 case 1:
@@ -2227,7 +2328,7 @@ __init int intel_pmu_init(void)
                  * counter, so do not extend mask to generic counters
                  */
                 for_each_event_constraint(c, x86_pmu.event_constraints) {
-                        if (c->cmask != X86_RAW_EVENT_MASK
+                        if (c->cmask != FIXED_EVENT_FLAGS
                             || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
                                 continue;
                         }
@@ -2237,5 +2338,12 @@ __init int intel_pmu_init(void)
                 }
         }
 
+        /* Support full width counters using alternative MSR range */
+        if (x86_pmu.intel_cap.full_width_write) {
+                x86_pmu.max_period = x86_pmu.cntval_mask;
+                x86_pmu.perfctr = MSR_IA32_PMC0;
+                pr_cont("full-width counters, ");
+        }
+
         return 0;
 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 60250f687052..3065c57a63c1 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -107,6 +107,19 @@ static u64 precise_store_data(u64 status)
         return val;
 }
 
+static u64 precise_store_data_hsw(u64 status)
+{
+        union perf_mem_data_src dse;
+
+        dse.val = 0;
+        dse.mem_op = PERF_MEM_OP_STORE;
+        dse.mem_lvl = PERF_MEM_LVL_NA;
+        if (status & 1)
+                dse.mem_lvl = PERF_MEM_LVL_L1;
+        /* Nothing else supported. Sorry. */
+        return dse.val;
+}
+
 static u64 load_latency_data(u64 status)
 {
         union intel_x86_pebs_dse dse;
@@ -165,6 +178,22 @@ struct pebs_record_nhm {
         u64 status, dla, dse, lat;
 };
 
+/*
+ * Same as pebs_record_nhm, with two additional fields.
+ */
+struct pebs_record_hsw {
+        struct pebs_record_nhm nhm;
+        /*
+         * Real IP of the event. In the Intel documentation this
+         * is called eventingrip.
+         */
+        u64 real_ip;
+        /*
+         * TSX tuning information field: abort cycles and abort flags.
+         */
+        u64 tsx_tuning;
+};
+
 void init_debug_store_on_cpu(int cpu)
 {
         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
@@ -548,6 +577,42 @@ struct event_constraint intel_ivb_pebs_event_constraints[] = {
         EVENT_CONSTRAINT_END
 };
 
+struct event_constraint intel_hsw_pebs_event_constraints[] = {
+        INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
+        INTEL_PST_HSW_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
+        INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
+        INTEL_EVENT_CONSTRAINT(0xc4, 0xf),    /* BR_INST_RETIRED.* */
+        INTEL_UEVENT_CONSTRAINT(0x01c5, 0xf), /* BR_MISP_RETIRED.CONDITIONAL */
+        INTEL_UEVENT_CONSTRAINT(0x04c5, 0xf), /* BR_MISP_RETIRED.ALL_BRANCHES */
+        INTEL_UEVENT_CONSTRAINT(0x20c5, 0xf), /* BR_MISP_RETIRED.NEAR_TAKEN */
+        INTEL_PLD_CONSTRAINT(0x01cd, 0x8),    /* MEM_TRANS_RETIRED.* */
+        /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
+        INTEL_UEVENT_CONSTRAINT(0x11d0, 0xf),
+        /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
+        INTEL_UEVENT_CONSTRAINT(0x12d0, 0xf),
+        INTEL_UEVENT_CONSTRAINT(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
+        INTEL_UEVENT_CONSTRAINT(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
+        /* MEM_UOPS_RETIRED.SPLIT_STORES */
+        INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf),
+        INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
+        INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
+        INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */
+        INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */
+        INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */
+        /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */
+        INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf),
+        /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */
+        INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf),
+        /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */
+        INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf),
+        /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */
+        INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf),
+        INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */
+        INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */
+
+        EVENT_CONSTRAINT_END
+};
+
 struct event_constraint *intel_pebs_constraints(struct perf_event *event)
 {
         struct event_constraint *c;
@@ -588,6 +653,12 @@ void intel_pmu_pebs_disable(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
 
         cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
+
+        if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_LDLAT)
+                cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
+        else if (event->hw.constraint->flags & PERF_X86_EVENT_PEBS_ST)
+                cpuc->pebs_enabled &= ~(1ULL << 63);
+
         if (cpuc->enabled)
                 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
 
@@ -697,6 +768,7 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
          */
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct pebs_record_nhm *pebs = __pebs;
+        struct pebs_record_hsw *pebs_hsw = __pebs;
         struct perf_sample_data data;
         struct pt_regs regs;
         u64 sample_type;
@@ -706,7 +778,8 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
                 return;
 
         fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
-        fst = event->hw.flags & PERF_X86_EVENT_PEBS_ST;
+        fst = event->hw.flags & (PERF_X86_EVENT_PEBS_ST |
+                                 PERF_X86_EVENT_PEBS_ST_HSW);
 
         perf_sample_data_init(&data, 0, event->hw.last_period);
 
@@ -717,9 +790,6 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
          * if PEBS-LL or PreciseStore
          */
         if (fll || fst) {
-                if (sample_type & PERF_SAMPLE_ADDR)
-                        data.addr = pebs->dla;
-
                 /*
                  * Use latency for weight (only avail with PEBS-LL)
                  */
@@ -732,6 +802,9 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
                 if (sample_type & PERF_SAMPLE_DATA_SRC) {
                         if (fll)
                                 data.data_src.val = load_latency_data(pebs->dse);
+                        else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
+                                data.data_src.val =
+                                        precise_store_data_hsw(pebs->dse);
                         else
                                 data.data_src.val = precise_store_data(pebs->dse);
                 }
@@ -753,11 +826,18 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
         regs.bp = pebs->bp;
         regs.sp = pebs->sp;
 
-        if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
+        if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
+                regs.ip = pebs_hsw->real_ip;
+                regs.flags |= PERF_EFLAGS_EXACT;
+        } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(&regs))
                 regs.flags |= PERF_EFLAGS_EXACT;
         else
                 regs.flags &= ~PERF_EFLAGS_EXACT;
 
+        if ((event->attr.sample_type & PERF_SAMPLE_ADDR) &&
+                x86_pmu.intel_cap.pebs_format >= 1)
+                data.addr = pebs->dla;
+
         if (has_branch_stack(event))
                 data.br_stack = &cpuc->lbr_stack;
 
@@ -806,35 +886,22 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
         __intel_pmu_pebs_event(event, iregs, at);
 }
 
-static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
+static void __intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, void *at,
+                                        void *top)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct debug_store *ds = cpuc->ds;
-        struct pebs_record_nhm *at, *top;
         struct perf_event *event = NULL;
         u64 status = 0;
-        int bit, n;
-
-        if (!x86_pmu.pebs_active)
-                return;
-
-        at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
-        top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
+        int bit;
 
         ds->pebs_index = ds->pebs_buffer_base;
 
-        n = top - at;
-        if (n <= 0)
-                return;
-
-        /*
-         * Should not happen, we program the threshold at 1 and do not
-         * set a reset value.
-         */
-        WARN_ONCE(n > x86_pmu.max_pebs_events, "Unexpected number of pebs records %d\n", n);
+        for (; at < top; at += x86_pmu.pebs_record_size) {
+                struct pebs_record_nhm *p = at;
 
-        for ( ; at < top; at++) {
-                for_each_set_bit(bit, (unsigned long *)&at->status, x86_pmu.max_pebs_events) {
+                for_each_set_bit(bit, (unsigned long *)&p->status,
+                                 x86_pmu.max_pebs_events) {
                         event = cpuc->events[bit];
                         if (!test_bit(bit, cpuc->active_mask))
                                 continue;
@@ -857,6 +924,61 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
         }
 }
 
+static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct debug_store *ds = cpuc->ds;
+        struct pebs_record_nhm *at, *top;
+        int n;
+
+        if (!x86_pmu.pebs_active)
+                return;
+
+        at  = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
+        top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
+
+        ds->pebs_index = ds->pebs_buffer_base;
+
+        n = top - at;
+        if (n <= 0)
+                return;
+
+        /*
+         * Should not happen, we program the threshold at 1 and do not
+         * set a reset value.
+         */
+        WARN_ONCE(n > x86_pmu.max_pebs_events,
+                  "Unexpected number of pebs records %d\n", n);
+
+        return __intel_pmu_drain_pebs_nhm(iregs, at, top);
+}
+
+static void intel_pmu_drain_pebs_hsw(struct pt_regs *iregs)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct debug_store *ds = cpuc->ds;
+        struct pebs_record_hsw *at, *top;
+        int n;
+
+        if (!x86_pmu.pebs_active)
+                return;
+
+        at  = (struct pebs_record_hsw *)(unsigned long)ds->pebs_buffer_base;
+        top = (struct pebs_record_hsw *)(unsigned long)ds->pebs_index;
+
+        n = top - at;
+        if (n <= 0)
+                return;
+        /*
+         * Should not happen, we program the threshold at 1 and do not
+         * set a reset value.
+         */
+        WARN_ONCE(n > x86_pmu.max_pebs_events,
+                  "Unexpected number of pebs records %d\n", n);
+
+        return __intel_pmu_drain_pebs_nhm(iregs, at, top);
+}
+
 /*
  * BTS, PEBS probe and setup
  */
@@ -888,6 +1010,12 @@ void intel_ds_init(void)
                         x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
                         break;
 
+                case 2:
+                        pr_cont("PEBS fmt2%c, ", pebs_type);
+                        x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
+                        x86_pmu.drain_pebs = intel_pmu_drain_pebs_hsw;
+                        break;
+
                 default:
                         printk(KERN_CONT "no PEBS fmt%d%c, ", format, pebs_type);
                         x86_pmu.pebs = 0;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index d978353c939b..d5be06a5005e 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -12,6 +12,16 @@ enum {
         LBR_FORMAT_LIP          = 0x01,
         LBR_FORMAT_EIP          = 0x02,
         LBR_FORMAT_EIP_FLAGS    = 0x03,
+        LBR_FORMAT_EIP_FLAGS2   = 0x04,
+        LBR_FORMAT_MAX_KNOWN    = LBR_FORMAT_EIP_FLAGS2,
+};
+
+static enum {
+        LBR_EIP_FLAGS           = 1,
+        LBR_TSX                 = 2,
+} lbr_desc[LBR_FORMAT_MAX_KNOWN + 1] = {
+        [LBR_FORMAT_EIP_FLAGS]  = LBR_EIP_FLAGS,
+        [LBR_FORMAT_EIP_FLAGS2] = LBR_EIP_FLAGS | LBR_TSX,
 };
 
 /*
@@ -56,6 +66,8 @@ enum {
          LBR_FAR)
 
 #define LBR_FROM_FLAG_MISPRED  (1ULL << 63)
+#define LBR_FROM_FLAG_IN_TX    (1ULL << 62)
+#define LBR_FROM_FLAG_ABORT    (1ULL << 61)
 
 #define for_each_branch_sample_type(x) \
         for ((x) = PERF_SAMPLE_BRANCH_USER; \
@@ -81,9 +93,13 @@ enum {
         X86_BR_JMP      = 1 << 9, /* jump */
         X86_BR_IRQ      = 1 << 10,/* hw interrupt or trap or fault */
         X86_BR_IND_CALL = 1 << 11,/* indirect calls */
+        X86_BR_ABORT    = 1 << 12,/* transaction abort */
+        X86_BR_IN_TX    = 1 << 13,/* in transaction */
+        X86_BR_NO_TX    = 1 << 14,/* not in transaction */
 };
 
 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
+#define X86_BR_ANYTX (X86_BR_NO_TX | X86_BR_IN_TX)
 
 #define X86_BR_ANY       \
         (X86_BR_CALL    |\
@@ -95,6 +111,7 @@ enum {
          X86_BR_JCC     |\
          X86_BR_JMP      |\
          X86_BR_IRQ      |\
+         X86_BR_ABORT    |\
          X86_BR_IND_CALL)
 
 #define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
@@ -270,21 +287,31 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
 
         for (i = 0; i < x86_pmu.lbr_nr; i++) {
                 unsigned long lbr_idx = (tos - i) & mask;
-                u64 from, to, mis = 0, pred = 0;
+                u64 from, to, mis = 0, pred = 0, in_tx = 0, abort = 0;
+                int skip = 0;
+                int lbr_flags = lbr_desc[lbr_format];
 
                 rdmsrl(x86_pmu.lbr_from + lbr_idx, from);
                 rdmsrl(x86_pmu.lbr_to   + lbr_idx, to);
 
-                if (lbr_format == LBR_FORMAT_EIP_FLAGS) {
+                if (lbr_flags & LBR_EIP_FLAGS) {
                         mis = !!(from & LBR_FROM_FLAG_MISPRED);
                         pred = !mis;
-                        from = (u64)((((s64)from) << 1) >> 1);
+                        skip = 1;
+                }
+                if (lbr_flags & LBR_TSX) {
+                        in_tx = !!(from & LBR_FROM_FLAG_IN_TX);
+                        abort = !!(from & LBR_FROM_FLAG_ABORT);
+                        skip = 3;
                 }
+                from = (u64)((((s64)from) << skip) >> skip);
 
                 cpuc->lbr_entries[i].from       = from;
                 cpuc->lbr_entries[i].to         = to;
                 cpuc->lbr_entries[i].mispred    = mis;
                 cpuc->lbr_entries[i].predicted  = pred;
+                cpuc->lbr_entries[i].in_tx      = in_tx;
+                cpuc->lbr_entries[i].abort      = abort;
                 cpuc->lbr_entries[i].reserved   = 0;
         }
         cpuc->lbr_stack.nr = i;
@@ -310,7 +337,7 @@ void intel_pmu_lbr_read(void)
  * - in case there is no HW filter
  * - in case the HW filter has errata or limitations
  */
-static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
+static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 {
         u64 br_type = event->attr.branch_sample_type;
         int mask = 0;
@@ -318,11 +345,8 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
         if (br_type & PERF_SAMPLE_BRANCH_USER)
                 mask |= X86_BR_USER;
 
-        if (br_type & PERF_SAMPLE_BRANCH_KERNEL) {
-                if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
-                        return -EACCES;
+        if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
                 mask |= X86_BR_KERNEL;
-        }
 
         /* we ignore BRANCH_HV here */
 
@@ -337,13 +361,21 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 
         if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
                 mask |= X86_BR_IND_CALL;
+
+        if (br_type & PERF_SAMPLE_BRANCH_ABORT_TX)
+                mask |= X86_BR_ABORT;
+
+        if (br_type & PERF_SAMPLE_BRANCH_IN_TX)
+                mask |= X86_BR_IN_TX;
+
+        if (br_type & PERF_SAMPLE_BRANCH_NO_TX)
+                mask |= X86_BR_NO_TX;
+
         /*
          * stash actual user request into reg, it may
          * be used by fixup code for some CPU
          */
         event->hw.branch_reg.reg = mask;
-
-        return 0;
 }
 
 /*
@@ -391,9 +423,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
         /*
          * setup SW LBR filter
          */
-        ret = intel_pmu_setup_sw_lbr_filter(event);
-        if (ret)
-                return ret;
+        intel_pmu_setup_sw_lbr_filter(event);
 
         /*
          * setup HW LBR filter, if any
@@ -415,7 +445,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
  * decoded (e.g., text page not present), then X86_BR_NONE is
  * returned.
  */
-static int branch_type(unsigned long from, unsigned long to)
+static int branch_type(unsigned long from, unsigned long to, int abort)
 {
         struct insn insn;
         void *addr;
@@ -435,6 +465,9 @@ static int branch_type(unsigned long from, unsigned long to)
         if (from == 0 || to == 0)
                 return X86_BR_NONE;
 
+        if (abort)
+                return X86_BR_ABORT | to_plm;
+
         if (from_plm == X86_BR_USER) {
                 /*
                  * can happen if measuring at the user level only
@@ -581,7 +614,13 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
                 from = cpuc->lbr_entries[i].from;
                 to = cpuc->lbr_entries[i].to;
 
-                type = branch_type(from, to);
+                type = branch_type(from, to, cpuc->lbr_entries[i].abort);
+                if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
+                        if (cpuc->lbr_entries[i].in_tx)
+                                type |= X86_BR_IN_TX;
+                        else
+                                type |= X86_BR_NO_TX;
+                }
 
                 /* if type does not correspond, then discard */
                 if (type == X86_BR_NONE || (br_sel & type) != type) {
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index 52441a2af538..9dd99751ccf9 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -536,7 +536,7 @@ __snbep_cbox_get_constraint(struct intel_uncore_box *box, struct perf_event *eve
         if (!uncore_box_is_fake(box))
                 reg1->alloc |= alloc;
 
-        return 0;
+        return NULL;
 fail:
         for (; i >= 0; i--) {
                 if (alloc & (0x1 << i))
@@ -644,7 +644,7 @@ snbep_pcu_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
             (!uncore_box_is_fake(box) && reg1->alloc))
                 return NULL;
 again:
-        mask = 0xff << (idx * 8);
+        mask = 0xffULL << (idx * 8);
         raw_spin_lock_irqsave(&er->lock, flags);
         if (!__BITS_VALUE(atomic_read(&er->ref), idx, 8) ||
             !((config1 ^ er->config) & mask)) {
@@ -1923,7 +1923,7 @@ static u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modif
 {
         struct hw_perf_event *hwc = &event->hw;
         struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
-        int idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
+        u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
         u64 config = reg1->config;
 
         /* get the non-shared control bits and shift them */
@@ -2723,15 +2723,16 @@ static void uncore_put_event_constraint(struct intel_uncore_box *box, struct per
 static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
 {
         unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
-        struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
+        struct event_constraint *c;
         int i, wmin, wmax, ret = 0;
         struct hw_perf_event *hwc;
 
         bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
 
         for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
+                hwc = &box->event_list[i]->hw;
                 c = uncore_get_event_constraint(box, box->event_list[i]);
-                constraints[i] = c;
+                hwc->constraint = c;
                 wmin = min(wmin, c->weight);
                 wmax = max(wmax, c->weight);
         }
@@ -2739,7 +2740,7 @@ static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int
         /* fastpath, try to reuse previous register */
         for (i = 0; i < n; i++) {
                 hwc = &box->event_list[i]->hw;
-                c = constraints[i];
+                c = hwc->constraint;
 
                 /* never assigned */
                 if (hwc->idx == -1)
@@ -2759,7 +2760,8 @@ static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int
         }
         /* slow path */
         if (i != n)
-                ret = perf_assign_events(constraints, n, wmin, wmax, assign);
+                ret = perf_assign_events(box->event_list, n,
+                                         wmin, wmax, assign);
 
         if (!assign || ret) {
                 for (i = 0; i < n; i++)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
index f9528917f6e8..47b3d00c9d89 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.h
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -337,10 +337,10 @@
                  NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
 
 #define NHMEX_M_PMON_ZDP_CTL_FVC_MASK           (((1 << 11) - 1) | (1 << 23))
-#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7 << (11 + 3 * (n)))
+#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7ULL << (11 + 3 * (n)))
 
 #define WSMEX_M_PMON_ZDP_CTL_FVC_MASK           (((1 << 12) - 1) | (1 << 24))
-#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7 << (12 + 3 * (n)))
+#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7ULL << (12 + 3 * (n)))
 
 /*
  * use the 9~13 bits to select event If the 7th bit is not set,
diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerflags.c
index 7b3fe56b1c21..31f0f335ed22 100644
--- a/arch/x86/kernel/cpu/powerflags.c
+++ b/arch/x86/kernel/cpu/powerflags.c
@@ -11,10 +11,10 @@ const char *const x86_power_flags[32] = {
         "fid",  /* frequency id control */
         "vid",  /* voltage id control */
         "ttp",  /* thermal trip */
-        "tm",
-        "stc",
-        "100mhzsteps",
-        "hwpstate",
+        "tm",   /* hardware thermal control */
+        "stc",  /* software thermal control */
+        "100mhzsteps", /* 100 MHz multiplier control */
+        "hwpstate", /* hardware P-state control */
         "",     /* tsc invariant mapped to constant_tsc */
         "cpb",  /* core performance boost */
         "eff_freq_ro", /* Readonly aperf/mperf */
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 37a198bd48c8..aee6317b902f 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -37,8 +37,8 @@ static void show_cpuinfo_misc(struct seq_file *m, struct cpuinfo_x86 *c)
                    static_cpu_has_bug(X86_BUG_FDIV) ? "yes" : "no",
                    static_cpu_has_bug(X86_BUG_F00F) ? "yes" : "no",
                    static_cpu_has_bug(X86_BUG_COMA) ? "yes" : "no",
-                   c->hard_math ? "yes" : "no",
-                   c->hard_math ? "yes" : "no",
+                   static_cpu_has(X86_FEATURE_FPU) ? "yes" : "no",
+                   static_cpu_has(X86_FEATURE_FPU) ? "yes" : "no",
                    c->cpuid_level,
                    c->wp_works_ok ? "yes" : "no");
 }
diff --git a/arch/x86/kernel/doublefault_32.c b/arch/x86/kernel/doublefault.c
index 155a13f33ed8..5d3fe8d36e4a 100644
--- a/arch/x86/kernel/doublefault_32.c
+++ b/arch/x86/kernel/doublefault.c
@@ -9,6 +9,8 @@
 #include <asm/processor.h>
 #include <asm/desc.h>
 
+#ifdef CONFIG_X86_32
+
 #define DOUBLEFAULT_STACKSIZE (1024)
 static unsigned long doublefault_stack[DOUBLEFAULT_STACKSIZE];
 #define STACK_START (unsigned long)(doublefault_stack+DOUBLEFAULT_STACKSIZE)
@@ -67,3 +69,16 @@ struct tss_struct doublefault_tss __cacheline_aligned = {
                 .__cr3          = __pa_nodebug(swapper_pg_dir),
         }
 };
+
+/* dummy for do_double_fault() call */
+void df_debug(struct pt_regs *regs, long error_code) {}
+
+#else /* !CONFIG_X86_32 */
+
+void df_debug(struct pt_regs *regs, long error_code)
+{
+        pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code);
+        show_regs(regs);
+        panic("Machine halted.");
+}
+#endif
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 8f3e2dec1df3..2cfbc3a3a2dd 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -801,7 +801,17 @@ ENTRY(name)				\
         CFI_ENDPROC;                    \
 ENDPROC(name)
 
-#define BUILD_INTERRUPT(name, nr)       BUILD_INTERRUPT3(name, nr, smp_##name)
+
+#ifdef CONFIG_TRACING
+#define TRACE_BUILD_INTERRUPT(name, nr)         \
+        BUILD_INTERRUPT3(trace_##name, nr, smp_trace_##name)
+#else
+#define TRACE_BUILD_INTERRUPT(name, nr)
+#endif
+
+#define BUILD_INTERRUPT(name, nr) \
+        BUILD_INTERRUPT3(name, nr, smp_##name); \
+        TRACE_BUILD_INTERRUPT(name, nr)
 
 /* The include is where all of the SMP etc. interrupts come from */
 #include <asm/entry_arch.h>
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 727208941030..1b69951a81e2 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -365,7 +365,7 @@ ENDPROC(native_usergs_sysret64)
         /*CFI_REL_OFFSET        ss,0*/
         pushq_cfi %rax /* rsp */
         CFI_REL_OFFSET  rsp,0
-        pushq_cfi $(X86_EFLAGS_IF|X86_EFLAGS_BIT1) /* eflags - interrupts on */
+        pushq_cfi $(X86_EFLAGS_IF|X86_EFLAGS_FIXED) /* eflags - interrupts on */
         /*CFI_REL_OFFSET        rflags,0*/
         pushq_cfi $__KERNEL_CS /* cs */
         /*CFI_REL_OFFSET        cs,0*/
@@ -1138,7 +1138,7 @@ END(common_interrupt)
 /*
  * APIC interrupts.
  */
-.macro apicinterrupt num sym do_sym
+.macro apicinterrupt3 num sym do_sym
 ENTRY(\sym)
         INTR_FRAME
         ASM_CLAC
@@ -1150,15 +1150,32 @@ ENTRY(\sym)
 END(\sym)
 .endm
 
+#ifdef CONFIG_TRACING
+#define trace(sym) trace_##sym
+#define smp_trace(sym) smp_trace_##sym
+
+.macro trace_apicinterrupt num sym
+apicinterrupt3 \num trace(\sym) smp_trace(\sym)
+.endm
+#else
+.macro trace_apicinterrupt num sym do_sym
+.endm
+#endif
+
+.macro apicinterrupt num sym do_sym
+apicinterrupt3 \num \sym \do_sym
+trace_apicinterrupt \num \sym
+.endm
+
 #ifdef CONFIG_SMP
-apicinterrupt IRQ_MOVE_CLEANUP_VECTOR \
+apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR \
         irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt
-apicinterrupt REBOOT_VECTOR \
+apicinterrupt3 REBOOT_VECTOR \
         reboot_interrupt smp_reboot_interrupt
 #endif
 
 #ifdef CONFIG_X86_UV
-apicinterrupt UV_BAU_MESSAGE \
+apicinterrupt3 UV_BAU_MESSAGE \
         uv_bau_message_intr1 uv_bau_message_interrupt
 #endif
 apicinterrupt LOCAL_TIMER_VECTOR \
@@ -1167,14 +1184,19 @@ apicinterrupt X86_PLATFORM_IPI_VECTOR \
         x86_platform_ipi smp_x86_platform_ipi
 
 #ifdef CONFIG_HAVE_KVM
-apicinterrupt POSTED_INTR_VECTOR \
+apicinterrupt3 POSTED_INTR_VECTOR \
         kvm_posted_intr_ipi smp_kvm_posted_intr_ipi
 #endif
 
+#ifdef CONFIG_X86_MCE_THRESHOLD
 apicinterrupt THRESHOLD_APIC_VECTOR \
         threshold_interrupt smp_threshold_interrupt
+#endif
+
+#ifdef CONFIG_X86_THERMAL_VECTOR
 apicinterrupt THERMAL_APIC_VECTOR \
         thermal_interrupt smp_thermal_interrupt
+#endif
 
 #ifdef CONFIG_SMP
 apicinterrupt CALL_FUNCTION_SINGLE_VECTOR \
@@ -1451,13 +1473,13 @@ ENTRY(xen_failsafe_callback)
         CFI_ENDPROC
 END(xen_failsafe_callback)
 
-apicinterrupt HYPERVISOR_CALLBACK_VECTOR \
+apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
         xen_hvm_callback_vector xen_evtchn_do_upcall
 
 #endif /* CONFIG_XEN */
 
 #if IS_ENABLED(CONFIG_HYPERV)
-apicinterrupt HYPERVISOR_CALLBACK_VECTOR \
+apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \
         hyperv_callback_vector hyperv_vector_handler
 #endif /* CONFIG_HYPERV */
 
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index 73afd11799ca..e65ddc62e113 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -444,7 +444,6 @@ is486:
         orl %ecx,%eax
         movl %eax,%cr0
 
-        call check_x87
         lgdt early_gdt_descr
         lidt idt_descr
         ljmp $(__KERNEL_CS),$1f
@@ -467,26 +466,6 @@ is486:
         pushl $0                # fake return address for unwinder
         jmp *(initial_code)
 
-/*
- * We depend on ET to be correct. This checks for 287/387.
- */
-check_x87:
-        movb $0,X86_HARD_MATH
-        clts
-        fninit
-        fstsw %ax
-        cmpb $0,%al
-        je 1f
-        movl %cr0,%eax          /* no coprocessor: have to set bits */
-        xorl $4,%eax            /* set EM */
-        movl %eax,%cr0
-        ret
-        ALIGN
-1:      movb $1,X86_HARD_MATH
-        .byte 0xDB,0xE4         /* fsetpm for 287, ignored by 387 */
-        ret
-
-        
 #include "verify_cpu.S"
 
 /*
diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index 321d65ebaffe..5e4d8a8a5c40 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -518,9 +518,15 @@ ENTRY(idt_table)
         .skip IDT_ENTRIES * 16
 
         .align L1_CACHE_BYTES
-ENTRY(nmi_idt_table)
+ENTRY(debug_idt_table)
         .skip IDT_ENTRIES * 16
 
+#ifdef CONFIG_TRACING
+        .align L1_CACHE_BYTES
+ENTRY(trace_idt_table)
+        .skip IDT_ENTRIES * 16
+#endif
+
         __PAGE_ALIGNED_BSS
 NEXT_PAGE(empty_zero_page)
         .skip PAGE_SIZE
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index cb339097b9ea..b627746f6b1a 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -131,7 +131,7 @@ static void __cpuinit init_thread_xstate(void)
          * xsave_init().
          */
 
-        if (!HAVE_HWFP) {
+        if (!cpu_has_fpu) {
                 /*
                  * Disable xsave as we do not support it if i387
                  * emulation is enabled.
@@ -158,6 +158,14 @@ void __cpuinit fpu_init(void)
         unsigned long cr0;
         unsigned long cr4_mask = 0;
 
+#ifndef CONFIG_MATH_EMULATION
+        if (!cpu_has_fpu) {
+                pr_emerg("No FPU found and no math emulation present\n");
+                pr_emerg("Giving up\n");
+                for (;;)
+                        asm volatile("hlt");
+        }
+#endif
         if (cpu_has_fxsr)
                 cr4_mask |= X86_CR4_OSFXSR;
         if (cpu_has_xmm)
@@ -167,7 +175,7 @@ void __cpuinit fpu_init(void)
 
         cr0 = read_cr0();
         cr0 &= ~(X86_CR0_TS|X86_CR0_EM); /* clear TS and EM */
-        if (!HAVE_HWFP)
+        if (!cpu_has_fpu)
                 cr0 |= X86_CR0_EM;
         write_cr0(cr0);
 
@@ -185,7 +193,7 @@ void __cpuinit fpu_init(void)
 
 void fpu_finit(struct fpu *fpu)
 {
-        if (!HAVE_HWFP) {
+        if (!cpu_has_fpu) {
                 finit_soft_fpu(&fpu->state->soft);
                 return;
         }
@@ -214,7 +222,7 @@ int init_fpu(struct task_struct *tsk)
         int ret;
 
         if (tsk_used_math(tsk)) {
-                if (HAVE_HWFP && tsk == current)
+                if (cpu_has_fpu && tsk == current)
                         unlazy_fpu(tsk);
                 tsk->thread.fpu.last_cpu = ~0;
                 return 0;
@@ -511,14 +519,13 @@ int fpregs_get(struct task_struct *target, const struct user_regset *regset,
         if (ret)
                 return ret;
 
-        if (!HAVE_HWFP)
+        if (!static_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
 
-        if (!cpu_has_fxsr) {
+        if (!cpu_has_fxsr)
                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
                                            &target->thread.fpu.state->fsave, 0,
                                            -1);
-        }
 
         sanitize_i387_state(target);
 
@@ -545,13 +552,13 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
 
         sanitize_i387_state(target);
 
-        if (!HAVE_HWFP)
+        if (!static_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 
-        if (!cpu_has_fxsr) {
+        if (!cpu_has_fxsr)
                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                          &target->thread.fpu.state->fsave, 0, -1);
-        }
+                                          &target->thread.fpu.state->fsave, 0,
+                                          -1);
 
         if (pos > 0 || count < sizeof(env))
                 convert_from_fxsr(&env, target);
@@ -592,3 +599,33 @@ int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
 EXPORT_SYMBOL(dump_fpu);
 
 #endif  /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */
+
+static int __init no_387(char *s)
+{
+        setup_clear_cpu_cap(X86_FEATURE_FPU);
+        return 1;
+}
+
+__setup("no387", no_387);
+
+void __cpuinit fpu_detect(struct cpuinfo_x86 *c)
+{
+        unsigned long cr0;
+        u16 fsw, fcw;
+
+        fsw = fcw = 0xffff;
+
+        cr0 = read_cr0();
+        cr0 &= ~(X86_CR0_TS | X86_CR0_EM);
+        write_cr0(cr0);
+
+        asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
+                     : "+m" (fsw), "+m" (fcw));
+
+        if (fsw == 0 && (fcw & 0x103f) == 0x003f)
+                set_cpu_cap(c, X86_FEATURE_FPU);
+        else
+                clear_cpu_cap(c, X86_FEATURE_FPU);
+
+        /* The final cr0 value is set in fpu_init() */
+}
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index ac0631d8996f..3a8185c042a2 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -18,6 +18,9 @@
 #include <asm/mce.h>
 #include <asm/hw_irq.h>
 
+#define CREATE_TRACE_POINTS
+#include <asm/trace/irq_vectors.h>
+
 atomic_t irq_err_count;
 
 /* Function pointer for generic interrupt vector handling */
@@ -204,23 +207,21 @@ unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
 /*
  * Handler for X86_PLATFORM_IPI_VECTOR.
  */
-void smp_x86_platform_ipi(struct pt_regs *regs)
+void __smp_x86_platform_ipi(void)
 {
-        struct pt_regs *old_regs = set_irq_regs(regs);
-
-        ack_APIC_irq();
-
-        irq_enter();
-
-        exit_idle();
-
         inc_irq_stat(x86_platform_ipis);
 
         if (x86_platform_ipi_callback)
                 x86_platform_ipi_callback();
+}
 
-        irq_exit();
+void smp_x86_platform_ipi(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
 
+        entering_ack_irq();
+        __smp_x86_platform_ipi();
+        exiting_irq();
         set_irq_regs(old_regs);
 }
 
@@ -246,6 +247,18 @@ void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
 }
 #endif
 
+void smp_trace_x86_platform_ipi(struct pt_regs *regs)
+{
+        struct pt_regs *old_regs = set_irq_regs(regs);
+
+        entering_ack_irq();
+        trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
+        __smp_x86_platform_ipi();
+        trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
+        exiting_irq();
+        set_irq_regs(old_regs);
+}
+
 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
 
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/x86/kernel/irq_work.c b/arch/x86/kernel/irq_work.c
index ca8f703a1e70..636a55e4a13c 100644
--- a/arch/x86/kernel/irq_work.c
+++ b/arch/x86/kernel/irq_work.c
@@ -8,14 +8,34 @@
 #include <linux/irq_work.h>
 #include <linux/hardirq.h>
 #include <asm/apic.h>
+#include <asm/trace/irq_vectors.h>
 
-void smp_irq_work_interrupt(struct pt_regs *regs)
+static inline void irq_work_entering_irq(void)
 {
         irq_enter();
         ack_APIC_irq();
+}
+
+static inline void __smp_irq_work_interrupt(void)
+{
         inc_irq_stat(apic_irq_work_irqs);
         irq_work_run();
-        irq_exit();
+}
+
+void smp_irq_work_interrupt(struct pt_regs *regs)
+{
+        irq_work_entering_irq();
+        __smp_irq_work_interrupt();
+        exiting_irq();
+}
+
+void smp_trace_irq_work_interrupt(struct pt_regs *regs)
+{
+        irq_work_entering_irq();
+        trace_irq_work_entry(IRQ_WORK_VECTOR);
+        __smp_irq_work_interrupt();
+        trace_irq_work_exit(IRQ_WORK_VECTOR);
+        exiting_irq();
 }
 
 void arch_irq_work_raise(void)
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 9895a9a41380..211bce445522 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -365,10 +365,14 @@ int __kprobes __copy_instruction(u8 *dest, u8 *src)
         return insn.length;
 }
 
-static void __kprobes arch_copy_kprobe(struct kprobe *p)
+static int __kprobes arch_copy_kprobe(struct kprobe *p)
 {
+        int ret;
+
         /* Copy an instruction with recovering if other optprobe modifies it.*/
-        __copy_instruction(p->ainsn.insn, p->addr);
+        ret = __copy_instruction(p->ainsn.insn, p->addr);
+        if (!ret)
+                return -EINVAL;
 
         /*
          * __copy_instruction can modify the displacement of the instruction,
@@ -384,6 +388,8 @@ static void __kprobes arch_copy_kprobe(struct kprobe *p)
 
         /* Also, displacement change doesn't affect the first byte */
         p->opcode = p->ainsn.insn[0];
+
+        return 0;
 }
 
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
@@ -397,8 +403,8 @@ int __kprobes arch_prepare_kprobe(struct kprobe *p)
         p->ainsn.insn = get_insn_slot();
         if (!p->ainsn.insn)
                 return -ENOMEM;
-        arch_copy_kprobe(p);
-        return 0;
+
+        return arch_copy_kprobe(p);
 }
 
 void __kprobes arch_arm_kprobe(struct kprobe *p)
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index d2c381280e3c..3dd37ebd591b 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -242,6 +242,7 @@ void __init kvmclock_init(void)
         if (!mem)
                 return;
         hv_clock = __va(mem);
+        memset(hv_clock, 0, size);
 
         if (kvm_register_clock("boot clock")) {
                 hv_clock = NULL;
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index efdec7cd8e01..47ebb1dbfbcb 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -31,48 +31,12 @@
 #include <asm/microcode.h>
 #include <asm/processor.h>
 #include <asm/msr.h>
+#include <asm/microcode_amd.h>
 
 MODULE_DESCRIPTION("AMD Microcode Update Driver");
 MODULE_AUTHOR("Peter Oruba");
 MODULE_LICENSE("GPL v2");
 
-#define UCODE_MAGIC                0x00414d44
-#define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000
-#define UCODE_UCODE_TYPE           0x00000001
-
-struct equiv_cpu_entry {
-        u32     installed_cpu;
-        u32     fixed_errata_mask;
-        u32     fixed_errata_compare;
-        u16     equiv_cpu;
-        u16     res;
-} __attribute__((packed));
-
-struct microcode_header_amd {
-        u32     data_code;
-        u32     patch_id;
-        u16     mc_patch_data_id;
-        u8      mc_patch_data_len;
-        u8      init_flag;
-        u32     mc_patch_data_checksum;
-        u32     nb_dev_id;
-        u32     sb_dev_id;
-        u16     processor_rev_id;
-        u8      nb_rev_id;
-        u8      sb_rev_id;
-        u8      bios_api_rev;
-        u8      reserved1[3];
-        u32     match_reg[8];
-} __attribute__((packed));
-
-struct microcode_amd {
-        struct microcode_header_amd     hdr;
-        unsigned int                    mpb[0];
-};
-
-#define SECTION_HDR_SIZE        8
-#define CONTAINER_HDR_SZ        12
-
 static struct equiv_cpu_entry *equiv_cpu_table;
 
 struct ucode_patch {
@@ -84,21 +48,10 @@ struct ucode_patch {
 
 static LIST_HEAD(pcache);
 
-static u16 find_equiv_id(unsigned int cpu)
+static u16 __find_equiv_id(unsigned int cpu)
 {
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
-        int i = 0;
-
-        if (!equiv_cpu_table)
-                return 0;
-
-        while (equiv_cpu_table[i].installed_cpu != 0) {
-                if (uci->cpu_sig.sig == equiv_cpu_table[i].installed_cpu)
-                        return equiv_cpu_table[i].equiv_cpu;
-
-                i++;
-        }
-        return 0;
+        return find_equiv_id(equiv_cpu_table, uci->cpu_sig.sig);
 }
 
 static u32 find_cpu_family_by_equiv_cpu(u16 equiv_cpu)
@@ -163,7 +116,7 @@ static struct ucode_patch *find_patch(unsigned int cpu)
 {
         u16 equiv_id;
 
-        equiv_id = find_equiv_id(cpu);
+        equiv_id = __find_equiv_id(cpu);
         if (!equiv_id)
                 return NULL;
 
@@ -173,9 +126,20 @@ static struct ucode_patch *find_patch(unsigned int cpu)
 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
+        struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
+        struct ucode_patch *p;
 
         csig->sig = cpuid_eax(0x00000001);
         csig->rev = c->microcode;
+
+        /*
+         * a patch could have been loaded early, set uci->mc so that
+         * mc_bp_resume() can call apply_microcode()
+         */
+        p = find_patch(cpu);
+        if (p && (p->patch_id == csig->rev))
+                uci->mc = p->data;
+
         pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 
         return 0;
@@ -215,7 +179,21 @@ static unsigned int verify_patch_size(int cpu, u32 patch_size,
         return patch_size;
 }
 
-static int apply_microcode_amd(int cpu)
+int __apply_microcode_amd(struct microcode_amd *mc_amd)
+{
+        u32 rev, dummy;
+
+        wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
+
+        /* verify patch application was successful */
+        rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
+        if (rev != mc_amd->hdr.patch_id)
+                return -1;
+
+        return 0;
+}
+
+int apply_microcode_amd(int cpu)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
         struct microcode_amd *mc_amd;
@@ -242,19 +220,15 @@ static int apply_microcode_amd(int cpu)
                 return 0;
         }
 
-        wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc_amd->hdr.data_code);
-
-        /* verify patch application was successful */
-        rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
-        if (rev != mc_amd->hdr.patch_id) {
+        if (__apply_microcode_amd(mc_amd))
                 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
-                       cpu, mc_amd->hdr.patch_id);
-                return -1;
-        }
+                        cpu, mc_amd->hdr.patch_id);
+        else
+                pr_info("CPU%d: new patch_level=0x%08x\n", cpu,
+                        mc_amd->hdr.patch_id);
 
-        pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
-        uci->cpu_sig.rev = rev;
-        c->microcode = rev;
+        uci->cpu_sig.rev = mc_amd->hdr.patch_id;
+        c->microcode = mc_amd->hdr.patch_id;
 
         return 0;
 }
@@ -364,7 +338,7 @@ static int verify_and_add_patch(unsigned int cpu, u8 *fw, unsigned int leftover)
         return crnt_size;
 }
 
-static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
+static enum ucode_state __load_microcode_amd(int cpu, const u8 *data, size_t size)
 {
         enum ucode_state ret = UCODE_ERROR;
         unsigned int leftover;
@@ -398,6 +372,32 @@ static enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
         return UCODE_OK;
 }
 
+enum ucode_state load_microcode_amd(int cpu, const u8 *data, size_t size)
+{
+        enum ucode_state ret;
+
+        /* free old equiv table */
+        free_equiv_cpu_table();
+
+        ret = __load_microcode_amd(cpu, data, size);
+
+        if (ret != UCODE_OK)
+                cleanup();
+
+#if defined(CONFIG_MICROCODE_AMD_EARLY) && defined(CONFIG_X86_32)
+        /* save BSP's matching patch for early load */
+        if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
+                struct ucode_patch *p = find_patch(cpu);
+                if (p) {
+                        memset(amd_bsp_mpb, 0, MPB_MAX_SIZE);
+                        memcpy(amd_bsp_mpb, p->data, min_t(u32, ksize(p->data),
+                                                           MPB_MAX_SIZE));
+                }
+        }
+#endif
+        return ret;
+}
+
 /*
  * AMD microcode firmware naming convention, up to family 15h they are in
  * the legacy file:
@@ -440,12 +440,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device,
                 goto fw_release;
         }
 
-        /* free old equiv table */
-        free_equiv_cpu_table();
-
         ret = load_microcode_amd(cpu, fw->data, fw->size);
-        if (ret != UCODE_OK)
-                cleanup();
 
  fw_release:
         release_firmware(fw);
diff --git a/arch/x86/kernel/microcode_amd_early.c b/arch/x86/kernel/microcode_amd_early.c
new file mode 100644
index 000000000000..1ac6e9aee766
--- /dev/null
+++ b/arch/x86/kernel/microcode_amd_early.c
@@ -0,0 +1,302 @@
+/*
+ * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ *
+ * Author: Jacob Shin <jacob.shin@amd.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/earlycpio.h>
+#include <linux/initrd.h>
+
+#include <asm/cpu.h>
+#include <asm/setup.h>
+#include <asm/microcode_amd.h>
+
+static bool ucode_loaded;
+static u32 ucode_new_rev;
+static unsigned long ucode_offset;
+static size_t ucode_size;
+
+/*
+ * Microcode patch container file is prepended to the initrd in cpio format.
+ * See Documentation/x86/early-microcode.txt
+ */
+static __initdata char ucode_path[] = "kernel/x86/microcode/AuthenticAMD.bin";
+
+static struct cpio_data __init find_ucode_in_initrd(void)
+{
+        long offset = 0;
+        char *path;
+        void *start;
+        size_t size;
+        unsigned long *uoffset;
+        size_t *usize;
+        struct cpio_data cd;
+
+#ifdef CONFIG_X86_32
+        struct boot_params *p;
+
+        /*
+         * On 32-bit, early load occurs before paging is turned on so we need
+         * to use physical addresses.
+         */
+        p       = (struct boot_params *)__pa_nodebug(&boot_params);
+        path    = (char *)__pa_nodebug(ucode_path);
+        start   = (void *)p->hdr.ramdisk_image;
+        size    = p->hdr.ramdisk_size;
+        uoffset = (unsigned long *)__pa_nodebug(&ucode_offset);
+        usize   = (size_t *)__pa_nodebug(&ucode_size);
+#else
+        path    = ucode_path;
+        start   = (void *)(boot_params.hdr.ramdisk_image + PAGE_OFFSET);
+        size    = boot_params.hdr.ramdisk_size;
+        uoffset = &ucode_offset;
+        usize   = &ucode_size;
+#endif
+
+        cd = find_cpio_data(path, start, size, &offset);
+        if (!cd.data)
+                return cd;
+
+        if (*(u32 *)cd.data != UCODE_MAGIC) {
+                cd.data = NULL;
+                cd.size = 0;
+                return cd;
+        }
+
+        *uoffset = (u8 *)cd.data - (u8 *)start;
+        *usize   = cd.size;
+
+        return cd;
+}
+
+/*
+ * Early load occurs before we can vmalloc(). So we look for the microcode
+ * patch container file in initrd, traverse equivalent cpu table, look for a
+ * matching microcode patch, and update, all in initrd memory in place.
+ * When vmalloc() is available for use later -- on 64-bit during first AP load,
+ * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
+ * load_microcode_amd() to save equivalent cpu table and microcode patches in
+ * kernel heap memory.
+ */
+static void __cpuinit apply_ucode_in_initrd(void *ucode, size_t size)
+{
+        struct equiv_cpu_entry *eq;
+        u32 *header;
+        u8  *data;
+        u16 eq_id = 0;
+        int offset, left;
+        u32 rev, eax;
+        u32 *new_rev;
+        unsigned long *uoffset;
+        size_t *usize;
+
+#ifdef CONFIG_X86_32
+        new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
+        uoffset = (unsigned long *)__pa_nodebug(&ucode_offset);
+        usize   = (size_t *)__pa_nodebug(&ucode_size);
+#else
+        new_rev = &ucode_new_rev;
+        uoffset = &ucode_offset;
+        usize   = &ucode_size;
+#endif
+
+        data   = ucode;
+        left   = size;
+        header = (u32 *)data;
+
+        /* find equiv cpu table */
+
+        if (header[1] != UCODE_EQUIV_CPU_TABLE_TYPE || /* type */
+            header[2] == 0)                            /* size */
+                return;
+
+        eax = cpuid_eax(0x00000001);
+
+        while (left > 0) {
+                eq = (struct equiv_cpu_entry *)(data + CONTAINER_HDR_SZ);
+
+                offset = header[2] + CONTAINER_HDR_SZ;
+                data  += offset;
+                left  -= offset;
+
+                eq_id = find_equiv_id(eq, eax);
+                if (eq_id)
+                        break;
+
+                /*
+                 * support multiple container files appended together. if this
+                 * one does not have a matching equivalent cpu entry, we fast
+                 * forward to the next container file.
+                 */
+                while (left > 0) {
+                        header = (u32 *)data;
+                        if (header[0] == UCODE_MAGIC &&
+                            header[1] == UCODE_EQUIV_CPU_TABLE_TYPE)
+                                break;
+
+                        offset = header[1] + SECTION_HDR_SIZE;
+                        data  += offset;
+                        left  -= offset;
+                }
+
+                /* mark where the next microcode container file starts */
+                offset    = data - (u8 *)ucode;
+                *uoffset += offset;
+                *usize   -= offset;
+                ucode     = data;
+        }
+
+        if (!eq_id) {
+                *usize = 0;
+                return;
+        }
+
+        /* find ucode and update if needed */
+
+        rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
+
+        while (left > 0) {
+                struct microcode_amd *mc;
+
+                header = (u32 *)data;
+                if (header[0] != UCODE_UCODE_TYPE || /* type */
+                    header[1] == 0)                  /* size */
+                        break;
+
+                mc = (struct microcode_amd *)(data + SECTION_HDR_SIZE);
+                if (eq_id == mc->hdr.processor_rev_id && rev < mc->hdr.patch_id)
+                        if (__apply_microcode_amd(mc) == 0) {
+                                rev = mc->hdr.patch_id;
+                                *new_rev = rev;
+                        }
+
+                offset  = header[1] + SECTION_HDR_SIZE;
+                data   += offset;
+                left   -= offset;
+        }
+
+        /* mark where this microcode container file ends */
+        offset  = *usize - (data - (u8 *)ucode);
+        *usize -= offset;
+
+        if (!(*new_rev))
+                *usize = 0;
+}
+
+void __init load_ucode_amd_bsp(void)
+{
+        struct cpio_data cd = find_ucode_in_initrd();
+        if (!cd.data)
+                return;
+
+        apply_ucode_in_initrd(cd.data, cd.size);
+}
+
+#ifdef CONFIG_X86_32
+u8 amd_bsp_mpb[MPB_MAX_SIZE];
+
+/*
+ * On 32-bit, since AP's early load occurs before paging is turned on, we
+ * cannot traverse cpu_equiv_table and pcache in kernel heap memory. So during
+ * cold boot, AP will apply_ucode_in_initrd() just like the BSP. During
+ * save_microcode_in_initrd_amd() BSP's patch is copied to amd_bsp_mpb, which
+ * is used upon resume from suspend.
+ */
+void __cpuinit load_ucode_amd_ap(void)
+{
+        struct microcode_amd *mc;
+        unsigned long *initrd;
+        unsigned long *uoffset;
+        size_t *usize;
+        void *ucode;
+
+        mc = (struct microcode_amd *)__pa(amd_bsp_mpb);
+        if (mc->hdr.patch_id && mc->hdr.processor_rev_id) {
+                __apply_microcode_amd(mc);
+                return;
+        }
+
+        initrd  = (unsigned long *)__pa(&initrd_start);
+        uoffset = (unsigned long *)__pa(&ucode_offset);
+        usize   = (size_t *)__pa(&ucode_size);
+
+        if (!*usize || !*initrd)
+                return;
+
+        ucode = (void *)((unsigned long)__pa(*initrd) + *uoffset);
+        apply_ucode_in_initrd(ucode, *usize);
+}
+
+static void __init collect_cpu_sig_on_bsp(void *arg)
+{
+        unsigned int cpu = smp_processor_id();
+        struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
+        uci->cpu_sig.sig = cpuid_eax(0x00000001);
+}
+#else
+static void __cpuinit collect_cpu_info_amd_early(struct cpuinfo_x86 *c,
+                                                 struct ucode_cpu_info *uci)
+{
+        u32 rev, eax;
+
+        rdmsr(MSR_AMD64_PATCH_LEVEL, rev, eax);
+        eax = cpuid_eax(0x00000001);
+
+        uci->cpu_sig.sig = eax;
+        uci->cpu_sig.rev = rev;
+        c->microcode = rev;
+        c->x86 = ((eax >> 8) & 0xf) + ((eax >> 20) & 0xff);
+}
+
+void __cpuinit load_ucode_amd_ap(void)
+{
+        unsigned int cpu = smp_processor_id();
+
+        collect_cpu_info_amd_early(&cpu_data(cpu), ucode_cpu_info + cpu);
+
+        if (cpu && !ucode_loaded) {
+                void *ucode;
+
+                if (!ucode_size || !initrd_start)
+                        return;
+
+                ucode = (void *)(initrd_start + ucode_offset);
+                if (load_microcode_amd(0, ucode, ucode_size) != UCODE_OK)
+                        return;
+                ucode_loaded = true;
+        }
+
+        apply_microcode_amd(cpu);
+}
+#endif
+
+int __init save_microcode_in_initrd_amd(void)
+{
+        enum ucode_state ret;
+        void *ucode;
+#ifdef CONFIG_X86_32
+        unsigned int bsp = boot_cpu_data.cpu_index;
+        struct ucode_cpu_info *uci = ucode_cpu_info + bsp;
+
+        if (!uci->cpu_sig.sig)
+                smp_call_function_single(bsp, collect_cpu_sig_on_bsp, NULL, 1);
+#endif
+        if (ucode_new_rev)
+                pr_info("microcode: updated early to new patch_level=0x%08x\n",
+                        ucode_new_rev);
+
+        if (ucode_loaded || !ucode_size || !initrd_start)
+                return 0;
+
+        ucode = (void *)(initrd_start + ucode_offset);
+        ret = load_microcode_amd(0, ucode, ucode_size);
+        if (ret != UCODE_OK)
+                return -EINVAL;
+
+        ucode_loaded = true;
+        return 0;
+}
diff --git a/arch/x86/kernel/microcode_core_early.c b/arch/x86/kernel/microcode_core_early.c
index 833d51d6ee06..86119f63db0c 100644
--- a/arch/x86/kernel/microcode_core_early.c
+++ b/arch/x86/kernel/microcode_core_early.c
@@ -18,6 +18,7 @@
  */
 #include <linux/module.h>
 #include <asm/microcode_intel.h>
+#include <asm/microcode_amd.h>
 #include <asm/processor.h>
 
 #define QCHAR(a, b, c, d) ((a) + ((b) << 8) + ((c) << 16) + ((d) << 24))
@@ -81,8 +82,18 @@ void __init load_ucode_bsp(void)
         vendor = x86_vendor();
         x86 = x86_family();
 
-        if (vendor == X86_VENDOR_INTEL && x86 >= 6)
-                load_ucode_intel_bsp();
+        switch (vendor) {
+        case X86_VENDOR_INTEL:
+                if (x86 >= 6)
+                        load_ucode_intel_bsp();
+                break;
+        case X86_VENDOR_AMD:
+                if (x86 >= 0x10)
+                        load_ucode_amd_bsp();
+                break;
+        default:
+                break;
+        }
 }
 
 void __cpuinit load_ucode_ap(void)
@@ -95,6 +106,36 @@ void __cpuinit load_ucode_ap(void)
         vendor = x86_vendor();
         x86 = x86_family();
 
-        if (vendor == X86_VENDOR_INTEL && x86 >= 6)
-                load_ucode_intel_ap();
+        switch (vendor) {
+        case X86_VENDOR_INTEL:
+                if (x86 >= 6)
+                        load_ucode_intel_ap();
+                break;
+        case X86_VENDOR_AMD:
+                if (x86 >= 0x10)
+                        load_ucode_amd_ap();
+                break;
+        default:
+                break;
+        }
+}
+
+int __init save_microcode_in_initrd(void)
+{
+        struct cpuinfo_x86 *c = &boot_cpu_data;
+
+        switch (c->x86_vendor) {
+        case X86_VENDOR_INTEL:
+                if (c->x86 >= 6)
+                        save_microcode_in_initrd_intel();
+                break;
+        case X86_VENDOR_AMD:
+                if (c->x86 >= 0x10)
+                        save_microcode_in_initrd_amd();
+                break;
+        default:
+                break;
+        }
+
+        return 0;
 }
diff --git a/arch/x86/kernel/microcode_intel_early.c b/arch/x86/kernel/microcode_intel_early.c
index 2e9e12871c2b..dabef95506f3 100644
--- a/arch/x86/kernel/microcode_intel_early.c
+++ b/arch/x86/kernel/microcode_intel_early.c
@@ -529,7 +529,7 @@ int save_mc_for_early(u8 *mc)
          */
         ret = save_microcode(&mc_saved_data, mc_saved_tmp, mc_saved_count);
         if (ret) {
-                pr_err("Can not save microcode patch.\n");
+                pr_err("Cannot save microcode patch.\n");
                 goto out;
         }
 
@@ -699,7 +699,7 @@ static int __cpuinit apply_microcode_early(struct mc_saved_data *mc_saved_data,
  * This function converts microcode patch offsets previously stored in
  * mc_saved_in_initrd to pointers and stores the pointers in mc_saved_data.
  */
-int __init save_microcode_in_initrd(void)
+int __init save_microcode_in_initrd_intel(void)
 {
         unsigned int count = mc_saved_data.mc_saved_count;
         struct microcode_intel *mc_saved[MAX_UCODE_COUNT];
@@ -711,7 +711,7 @@ int __init save_microcode_in_initrd(void)
         microcode_pointer(mc_saved, mc_saved_in_initrd, initrd_start, count);
         ret = save_microcode(&mc_saved_data, mc_saved, count);
         if (ret)
-                pr_err("Can not save microcod patches from initrd");
+                pr_err("Cannot save microcode patches from initrd.\n");
 
         show_saved_mc();
 
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c
index 60308053fdb2..0920212e6159 100644
--- a/arch/x86/kernel/nmi.c
+++ b/arch/x86/kernel/nmi.c
@@ -14,6 +14,7 @@
 #include <linux/kprobes.h>
 #include <linux/kdebug.h>
 #include <linux/nmi.h>
+#include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/hardirq.h>
 #include <linux/slab.h>
@@ -29,6 +30,9 @@
 #include <asm/nmi.h>
 #include <asm/x86_init.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/nmi.h>
+
 struct nmi_desc {
         spinlock_t lock;
         struct list_head head;
@@ -82,6 +86,15 @@ __setup("unknown_nmi_panic", setup_unknown_nmi_panic);
 
 #define nmi_to_desc(type) (&nmi_desc[type])
 
+static u64 nmi_longest_ns = 1 * NSEC_PER_MSEC;
+static int __init nmi_warning_debugfs(void)
+{
+        debugfs_create_u64("nmi_longest_ns", 0644,
+                        arch_debugfs_dir, &nmi_longest_ns);
+        return 0;
+}
+fs_initcall(nmi_warning_debugfs);
+
 static int __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2b)
 {
         struct nmi_desc *desc = nmi_to_desc(type);
@@ -96,8 +109,27 @@ static int __kprobes nmi_handle(unsigned int type, struct pt_regs *regs, bool b2
          * can be latched at any given time.  Walk the whole list
          * to handle those situations.
          */
-        list_for_each_entry_rcu(a, &desc->head, list)
-                handled += a->handler(type, regs);
+        list_for_each_entry_rcu(a, &desc->head, list) {
+                u64 before, delta, whole_msecs;
+                int decimal_msecs, thishandled;
+
+                before = local_clock();
+                thishandled = a->handler(type, regs);
+                handled += thishandled;
+                delta = local_clock() - before;
+                trace_nmi_handler(a->handler, (int)delta, thishandled);
+
+                if (delta < nmi_longest_ns)
+                        continue;
+
+                nmi_longest_ns = delta;
+                whole_msecs = do_div(delta, (1000 * 1000));
+                decimal_msecs = do_div(delta, 1000) % 1000;
+                printk_ratelimited(KERN_INFO
+                        "INFO: NMI handler (%ps) took too long to run: "
+                        "%lld.%03d msecs\n", a->handler, whole_msecs,
+                        decimal_msecs);
+        }
 
         rcu_read_unlock();
 
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 4e7a37ff03ab..81a5f5e8f142 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -277,18 +277,6 @@ void exit_idle(void)
 }
 #endif
 
-void arch_cpu_idle_prepare(void)
-{
-        /*
-         * If we're the non-boot CPU, nothing set the stack canary up
-         * for us.  CPU0 already has it initialized but no harm in
-         * doing it again.  This is a good place for updating it, as
-         * we wont ever return from this function (so the invalid
-         * canaries already on the stack wont ever trigger).
-         */
-        boot_init_stack_canary();
-}
-
 void arch_cpu_idle_enter(void)
 {
         local_touch_nmi();
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 7305f7dfc7ab..f8adefca71dc 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -110,11 +110,16 @@ void __show_regs(struct pt_regs *regs, int all)
         get_debugreg(d1, 1);
         get_debugreg(d2, 2);
         get_debugreg(d3, 3);
-        printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
-                        d0, d1, d2, d3);
-
         get_debugreg(d6, 6);
         get_debugreg(d7, 7);
+
+        /* Only print out debug registers if they are in their non-default state. */
+        if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
+            (d6 == DR6_RESERVED) && (d7 == 0x400))
+                return;
+
+        printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
+                        d0, d1, d2, d3);
         printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
                         d6, d7);
 }
@@ -147,7 +152,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
                 childregs->bp = arg;
                 childregs->orig_ax = -1;
                 childregs->cs = __KERNEL_CS | get_kernel_rpl();
-                childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
+                childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED;
                 p->fpu_counter = 0;
                 p->thread.io_bitmap_ptr = NULL;
                 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 355ae06dbf94..05646bab4ca6 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -105,11 +105,18 @@ void __show_regs(struct pt_regs *regs, int all)
         get_debugreg(d0, 0);
         get_debugreg(d1, 1);
         get_debugreg(d2, 2);
-        printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
         get_debugreg(d3, 3);
         get_debugreg(d6, 6);
         get_debugreg(d7, 7);
+
+        /* Only print out debug registers if they are in their non-default state. */
+        if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
+            (d6 == DR6_RESERVED) && (d7 == 0x400))
+                return;
+
+        printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2);
         printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
+
 }
 
 void release_thread(struct task_struct *dead_task)
@@ -176,7 +183,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
                 childregs->bp = arg;
                 childregs->orig_ax = -1;
                 childregs->cs = __KERNEL_CS | get_kernel_rpl();
-                childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_BIT1;
+                childregs->flags = X86_EFLAGS_IF | X86_EFLAGS_FIXED;
                 return 0;
         }
         *childregs = *current_pt_regs();
diff --git a/arch/x86/kernel/relocate_kernel_32.S b/arch/x86/kernel/relocate_kernel_32.S
index 36818f8ec2be..e13f8e7c22a6 100644
--- a/arch/x86/kernel/relocate_kernel_32.S
+++ b/arch/x86/kernel/relocate_kernel_32.S
@@ -186,7 +186,7 @@ identity_mapped:
         movl    CP_PA_PGD(%ebx), %eax
         movl    %eax, %cr3
         movl    %cr0, %eax
-        orl     $(1<<31), %eax
+        orl     $X86_CR0_PG, %eax
         movl    %eax, %cr0
         lea     PAGE_SIZE(%edi), %esp
         movl    %edi, %eax
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 7a6f3b3be3cf..3fd2c693e475 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -151,21 +151,21 @@ identity_mapped:
 
         testq   %r11, %r11
         jnz 1f
-        xorq    %rax, %rax
-        xorq    %rbx, %rbx
-        xorq    %rcx, %rcx
-        xorq    %rdx, %rdx
-        xorq    %rsi, %rsi
-        xorq    %rdi, %rdi
-        xorq    %rbp, %rbp
-        xorq    %r8,  %r8
-        xorq    %r9,  %r9
-        xorq    %r10, %r9
-        xorq    %r11, %r11
-        xorq    %r12, %r12
-        xorq    %r13, %r13
-        xorq    %r14, %r14
-        xorq    %r15, %r15
+        xorl    %eax, %eax
+        xorl    %ebx, %ebx
+        xorl    %ecx, %ecx
+        xorl    %edx, %edx
+        xorl    %esi, %esi
+        xorl    %edi, %edi
+        xorl    %ebp, %ebp
+        xorl    %r8d, %r8d
+        xorl    %r9d, %r9d
+        xorl    %r10d, %r10d
+        xorl    %r11d, %r11d
+        xorl    %r12d, %r12d
+        xorl    %r13d, %r13d
+        xorl    %r14d, %r14d
+        xorl    %r15d, %r15d
 
         ret
 
@@ -212,8 +212,8 @@ virtual_mapped:
         /* Do the copies */
 swap_pages:
         movq    %rdi, %rcx      /* Put the page_list in %rcx */
-        xorq    %rdi, %rdi
-        xorq    %rsi, %rsi
+        xorl    %edi, %edi
+        xorl    %esi, %esi
         jmp     1f
 
 0:      /* top, read another word for the indirection page */
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 56f7fcfe7fa2..e68709da8251 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -1040,8 +1040,6 @@ void __init setup_arch(char **cmdline_p)
         /* max_low_pfn get updated here */
         find_low_pfn_range();
 #else
-        num_physpages = max_pfn;
-
         check_x2apic();
 
         /* How many end-of-memory variables you have, grandma! */
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 69562992e457..cf913587d4dd 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -43,12 +43,6 @@
 
 #include <asm/sigframe.h>
 
-#ifdef CONFIG_X86_32
-# define FIX_EFLAGS     (__FIX_EFLAGS | X86_EFLAGS_RF)
-#else
-# define FIX_EFLAGS     __FIX_EFLAGS
-#endif
-
 #define COPY(x)                 do {                    \
         get_user_ex(regs->x, &sc->x);                   \
 } while (0)
@@ -668,15 +662,17 @@ handle_signal(struct ksignal *ksig, struct pt_regs *regs)
         if (!failed) {
                 /*
                  * Clear the direction flag as per the ABI for function entry.
-                 */
-                regs->flags &= ~X86_EFLAGS_DF;
-                /*
+                 *
+                 * Clear RF when entering the signal handler, because
+                 * it might disable possible debug exception from the
+                 * signal handler.
+                 *
                  * Clear TF when entering the signal handler, but
                  * notify any tracer that was single-stepping it.
                  * The tracer may want to single-step inside the
                  * handler too.
                  */
-                regs->flags &= ~X86_EFLAGS_TF;
+                regs->flags &= ~(X86_EFLAGS_DF|X86_EFLAGS_RF|X86_EFLAGS_TF);
         }
         signal_setup_done(failed, ksig, test_thread_flag(TIF_SINGLESTEP));
 }
diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c
index 48d2b7ded422..f4fe0b8879e0 100644
--- a/arch/x86/kernel/smp.c
+++ b/arch/x86/kernel/smp.c
@@ -30,6 +30,7 @@
 #include <asm/proto.h>
 #include <asm/apic.h>
 #include <asm/nmi.h>
+#include <asm/trace/irq_vectors.h>
 /*
  *      Some notes on x86 processor bugs affecting SMP operation:
  *
@@ -249,32 +250,80 @@ finish:
 /*
  * Reschedule call back.
  */
-void smp_reschedule_interrupt(struct pt_regs *regs)
+static inline void __smp_reschedule_interrupt(void)
 {
-        ack_APIC_irq();
         inc_irq_stat(irq_resched_count);
         scheduler_ipi();
+}
+
+void smp_reschedule_interrupt(struct pt_regs *regs)
+{
+        ack_APIC_irq();
+        __smp_reschedule_interrupt();
         /*
          * KVM uses this interrupt to force a cpu out of guest mode
          */
 }
 
-void smp_call_function_interrupt(struct pt_regs *regs)
+void smp_trace_reschedule_interrupt(struct pt_regs *regs)
+{
+        ack_APIC_irq();
+        trace_reschedule_entry(RESCHEDULE_VECTOR);
+        __smp_reschedule_interrupt();
+        trace_reschedule_exit(RESCHEDULE_VECTOR);
+        /*
+         * KVM uses this interrupt to force a cpu out of guest mode
+         */
+}
+
+static inline void call_function_entering_irq(void)
 {
         ack_APIC_irq();
         irq_enter();
+}
+
+static inline void __smp_call_function_interrupt(void)
+{
         generic_smp_call_function_interrupt();
         inc_irq_stat(irq_call_count);
-        irq_exit();
 }
 
-void smp_call_function_single_interrupt(struct pt_regs *regs)
+void smp_call_function_interrupt(struct pt_regs *regs)
+{
+        call_function_entering_irq();
+        __smp_call_function_interrupt();
+        exiting_irq();
+}
+
+void smp_trace_call_function_interrupt(struct pt_regs *regs)
+{
+        call_function_entering_irq();
+        trace_call_function_entry(CALL_FUNCTION_VECTOR);
+        __smp_call_function_interrupt();
+        trace_call_function_exit(CALL_FUNCTION_VECTOR);
+        exiting_irq();
+}
+
+static inline void __smp_call_function_single_interrupt(void)
 {
-        ack_APIC_irq();
-        irq_enter();
         generic_smp_call_function_single_interrupt();
         inc_irq_stat(irq_call_count);
-        irq_exit();
+}
+
+void smp_call_function_single_interrupt(struct pt_regs *regs)
+{
+        call_function_entering_irq();
+        __smp_call_function_single_interrupt();
+        exiting_irq();
+}
+
+void smp_trace_call_function_single_interrupt(struct pt_regs *regs)
+{
+        call_function_entering_irq();
+        trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
+        __smp_call_function_single_interrupt();
+        trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
+        exiting_irq();
 }
 
 static int __init nonmi_ipi_setup(char *str)
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 9c73b51817e4..bfd348e99369 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -372,15 +372,15 @@ static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
 
 void __cpuinit set_cpu_sibling_map(int cpu)
 {
-        bool has_mc = boot_cpu_data.x86_max_cores > 1;
         bool has_smt = smp_num_siblings > 1;
+        bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
         struct cpuinfo_x86 *c = &cpu_data(cpu);
         struct cpuinfo_x86 *o;
         int i;
 
         cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
 
-        if (!has_smt && !has_mc) {
+        if (!has_mp) {
                 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
                 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
                 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
@@ -394,7 +394,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)
                 if ((i == cpu) || (has_smt && match_smt(c, o)))
                         link_mask(sibling, cpu, i);
 
-                if ((i == cpu) || (has_mc && match_llc(c, o)))
+                if ((i == cpu) || (has_mp && match_llc(c, o)))
                         link_mask(llc_shared, cpu, i);
 
         }
@@ -406,7 +406,7 @@ void __cpuinit set_cpu_sibling_map(int cpu)
         for_each_cpu(i, cpu_sibling_setup_mask) {
                 o = &cpu_data(i);
 
-                if ((i == cpu) || (has_mc && match_mc(c, o))) {
+                if ((i == cpu) || (has_mp && match_mc(c, o))) {
                         link_mask(core, cpu, i);
 
                         /*
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index f84fe00fad48..3ff42d2f046d 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -31,6 +31,7 @@
 #include <linux/pfn.h>
 #include <linux/mm.h>
 #include <linux/tboot.h>
+#include <linux/debugfs.h>
 
 #include <asm/realmode.h>
 #include <asm/processor.h>
@@ -338,6 +339,73 @@ static struct notifier_block tboot_cpu_notifier __cpuinitdata =
         .notifier_call = tboot_cpu_callback,
 };
 
+#ifdef CONFIG_DEBUG_FS
+
+#define TBOOT_LOG_UUID  { 0x26, 0x25, 0x19, 0xc0, 0x30, 0x6b, 0xb4, 0x4d, \
+                          0x4c, 0x84, 0xa3, 0xe9, 0x53, 0xb8, 0x81, 0x74 }
+
+#define TBOOT_SERIAL_LOG_ADDR   0x60000
+#define TBOOT_SERIAL_LOG_SIZE   0x08000
+#define LOG_MAX_SIZE_OFF        16
+#define LOG_BUF_OFF             24
+
+static uint8_t tboot_log_uuid[16] = TBOOT_LOG_UUID;
+
+static ssize_t tboot_log_read(struct file *file, char __user *user_buf, size_t count, loff_t *ppos)
+{
+        void __iomem *log_base;
+        u8 log_uuid[16];
+        u32 max_size;
+        void *kbuf;
+        int ret = -EFAULT;
+
+        log_base = ioremap_nocache(TBOOT_SERIAL_LOG_ADDR, TBOOT_SERIAL_LOG_SIZE);
+        if (!log_base)
+                return ret;
+
+        memcpy_fromio(log_uuid, log_base, sizeof(log_uuid));
+        if (memcmp(&tboot_log_uuid, log_uuid, sizeof(log_uuid)))
+                goto err_iounmap;
+
+        max_size = readl(log_base + LOG_MAX_SIZE_OFF);
+        if (*ppos >= max_size) {
+                ret = 0;
+                goto err_iounmap;
+        }
+
+        if (*ppos + count > max_size)
+                count = max_size - *ppos;
+
+        kbuf = kmalloc(count, GFP_KERNEL);
+        if (!kbuf) {
+                ret = -ENOMEM;
+                goto err_iounmap;
+        }
+
+        memcpy_fromio(kbuf, log_base + LOG_BUF_OFF + *ppos, count);
+        if (copy_to_user(user_buf, kbuf, count))
+                goto err_kfree;
+
+        *ppos += count;
+
+        ret = count;
+
+err_kfree:
+        kfree(kbuf);
+
+err_iounmap:
+        iounmap(log_base);
+
+        return ret;
+}
+
+static const struct file_operations tboot_log_fops = {
+        .read   = tboot_log_read,
+        .llseek = default_llseek,
+};
+
+#endif /* CONFIG_DEBUG_FS */
+
 static __init int tboot_late_init(void)
 {
         if (!tboot_enabled())
@@ -348,6 +416,11 @@ static __init int tboot_late_init(void)
         atomic_set(&ap_wfs_count, 0);
         register_hotcpu_notifier(&tboot_cpu_notifier);
 
+#ifdef CONFIG_DEBUG_FS
+        debugfs_create_file("tboot_log", S_IRUSR,
+                        arch_debugfs_dir, NULL, &tboot_log_fops);
+#endif
+
         acpi_os_set_prepare_sleep(&tboot_sleep);
         return 0;
 }
diff --git a/arch/x86/kernel/tracepoint.c b/arch/x86/kernel/tracepoint.c
new file mode 100644
index 000000000000..4e584a8d6edd
--- /dev/null
+++ b/arch/x86/kernel/tracepoint.c
@@ -0,0 +1,61 @@
+/*
+ * Code for supporting irq vector tracepoints.
+ *
+ * Copyright (C) 2013 Seiji Aguchi <seiji.aguchi@hds.com>
+ *
+ */
+#include <asm/hw_irq.h>
+#include <asm/desc.h>
+#include <linux/atomic.h>
+
+atomic_t trace_idt_ctr = ATOMIC_INIT(0);
+struct desc_ptr trace_idt_descr = { NR_VECTORS * 16 - 1,
+                                (unsigned long) trace_idt_table };
+
+#ifndef CONFIG_X86_64
+gate_desc trace_idt_table[NR_VECTORS] __page_aligned_data
+                                        = { { { { 0, 0 } } }, };
+#endif
+
+static int trace_irq_vector_refcount;
+static DEFINE_MUTEX(irq_vector_mutex);
+
+static void set_trace_idt_ctr(int val)
+{
+        atomic_set(&trace_idt_ctr, val);
+        /* Ensure the trace_idt_ctr is set before sending IPI */
+        wmb();
+}
+
+static void switch_idt(void *arg)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        load_current_idt();
+        local_irq_restore(flags);
+}
+
+void trace_irq_vector_regfunc(void)
+{
+        mutex_lock(&irq_vector_mutex);
+        if (!trace_irq_vector_refcount) {
+                set_trace_idt_ctr(1);
+                smp_call_function(switch_idt, NULL, 0);
+                switch_idt(NULL);
+        }
+        trace_irq_vector_refcount++;
+        mutex_unlock(&irq_vector_mutex);
+}
+
+void trace_irq_vector_unregfunc(void)
+{
+        mutex_lock(&irq_vector_mutex);
+        trace_irq_vector_refcount--;
+        if (!trace_irq_vector_refcount) {
+                set_trace_idt_ctr(0);
+                smp_call_function(switch_idt, NULL, 0);
+                switch_idt(NULL);
+        }
+        mutex_unlock(&irq_vector_mutex);
+}
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 772e2a846dec..b0865e88d3cc 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -254,6 +254,9 @@ dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code)
         tsk->thread.error_code = error_code;
         tsk->thread.trap_nr = X86_TRAP_DF;
 
+#ifdef CONFIG_DOUBLEFAULT
+        df_debug(regs, error_code);
+#endif
         /*
          * This is always a kernel trap and never fixable (and thus must
          * never return).
@@ -437,7 +440,7 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
         /* Store the virtualized DR6 value */
         tsk->thread.debugreg6 = dr6;
 
-        if (notify_die(DIE_DEBUG, "debug", regs, PTR_ERR(&dr6), error_code,
+        if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code,
                                                         SIGTRAP) == NOTIFY_STOP)
                 goto exit;
 
@@ -785,7 +788,7 @@ void __init trap_init(void)
         x86_init.irqs.trap_init();
 
 #ifdef CONFIG_X86_64
-        memcpy(&nmi_idt_table, &idt_table, IDT_ENTRIES * 16);
+        memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
         set_nmi_gate(X86_TRAP_DB, &debug);
         set_nmi_gate(X86_TRAP_BP, &int3);
 #endif
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index ada87a329edc..d6c28acdf99c 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -243,7 +243,7 @@ int save_xstate_sig(void __user *buf, void __user *buf_fx, int size)
         if (!access_ok(VERIFY_WRITE, buf, size))
                 return -EACCES;
 
-        if (!HAVE_HWFP)
+        if (!static_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_get(current, NULL, 0,
                         sizeof(struct user_i387_ia32_struct), NULL,
                         (struct _fpstate_ia32 __user *) buf) ? -1 : 1;
@@ -350,11 +350,10 @@ int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
         if (!used_math() && init_fpu(tsk))
                 return -1;
 
-        if (!HAVE_HWFP) {
+        if (!static_cpu_has(X86_FEATURE_FPU))
                 return fpregs_soft_set(current, NULL,
                                        0, sizeof(struct user_i387_ia32_struct),
                                        NULL, buf) != 0;
-        }
 
         if (use_xsave()) {
                 struct _fpx_sw_bytes fx_sw_user;
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index d609e1d84048..bf4fb04d0112 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -5,12 +5,13 @@ CFLAGS_x86.o := -I.
 CFLAGS_svm.o := -I.
 CFLAGS_vmx.o := -I.
 
-kvm-y                   += $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-                                coalesced_mmio.o irq_comm.o eventfd.o \
-                                irqchip.o)
-kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)     += $(addprefix ../../../virt/kvm/, \
-                                assigned-dev.o iommu.o)
-kvm-$(CONFIG_KVM_ASYNC_PF)      += $(addprefix ../../../virt/kvm/, async_pf.o)
+KVM := ../../../virt/kvm
+
+kvm-y                   += $(KVM)/kvm_main.o $(KVM)/ioapic.o \
+                                $(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o \
+                                $(KVM)/eventfd.o $(KVM)/irqchip.o
+kvm-$(CONFIG_KVM_DEVICE_ASSIGNMENT)     += $(KVM)/assigned-dev.o $(KVM)/iommu.o
+kvm-$(CONFIG_KVM_ASYNC_PF)      += $(KVM)/async_pf.o
 
 kvm-y                   += x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
                            i8254.o cpuid.o pmu.o
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 5953dcea752d..2bc1e81045b0 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -61,6 +61,8 @@
 #define OpMem8            26ull  /* 8-bit zero extended memory operand */
 #define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
 #define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
+#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
+#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
 
 #define OpBits             5  /* Width of operand field */
 #define OpMask             ((1ull << OpBits) - 1)
@@ -86,6 +88,7 @@
 #define DstMem64    (OpMem64 << DstShift)
 #define DstImmUByte (OpImmUByte << DstShift)
 #define DstDX       (OpDX << DstShift)
+#define DstAccLo    (OpAccLo << DstShift)
 #define DstMask     (OpMask << DstShift)
 /* Source operand type. */
 #define SrcShift    6
@@ -108,6 +111,7 @@
 #define SrcImm64    (OpImm64 << SrcShift)
 #define SrcDX       (OpDX << SrcShift)
 #define SrcMem8     (OpMem8 << SrcShift)
+#define SrcAccHi    (OpAccHi << SrcShift)
 #define SrcMask     (OpMask << SrcShift)
 #define BitOp       (1<<11)
 #define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
@@ -138,6 +142,7 @@
 /* Source 2 operand type */
 #define Src2Shift   (31)
 #define Src2None    (OpNone << Src2Shift)
+#define Src2Mem     (OpMem << Src2Shift)
 #define Src2CL      (OpCL << Src2Shift)
 #define Src2ImmByte (OpImmByte << Src2Shift)
 #define Src2One     (OpOne << Src2Shift)
@@ -155,6 +160,9 @@
 #define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
 #define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
 #define NoWrite     ((u64)1 << 45)  /* No writeback */
+#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
+
+#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
 
 #define X2(x...) x, x
 #define X3(x...) X2(x), x
@@ -171,10 +179,11 @@
 /*
  * fastop functions have a special calling convention:
  *
- * dst:    [rdx]:rax  (in/out)
- * src:    rbx        (in/out)
+ * dst:    rax        (in/out)
+ * src:    rdx        (in/out)
  * src2:   rcx        (in)
  * flags:  rflags     (in/out)
+ * ex:     rsi        (in:fastop pointer, out:zero if exception)
  *
  * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
  * different operand sizes can be reached by calculation, rather than a jump
@@ -276,174 +285,17 @@ static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
 }
 
 /*
- * Instruction emulation:
- * Most instructions are emulated directly via a fragment of inline assembly
- * code. This allows us to save/restore EFLAGS and thus very easily pick up
- * any modified flags.
- */
-
-#if defined(CONFIG_X86_64)
-#define _LO32 "k"               /* force 32-bit operand */
-#define _STK  "%%rsp"           /* stack pointer */
-#elif defined(__i386__)
-#define _LO32 ""                /* force 32-bit operand */
-#define _STK  "%%esp"           /* stack pointer */
-#endif
-
-/*
  * These EFLAGS bits are restored from saved value during emulation, and
  * any changes are written back to the saved value after emulation.
  */
 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
 
-/* Before executing instruction: restore necessary bits in EFLAGS. */
-#define _PRE_EFLAGS(_sav, _msk, _tmp)                                   \
-        /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
-        "movl %"_sav",%"_LO32 _tmp"; "                                  \
-        "push %"_tmp"; "                                                \
-        "push %"_tmp"; "                                                \
-        "movl %"_msk",%"_LO32 _tmp"; "                                  \
-        "andl %"_LO32 _tmp",("_STK"); "                                 \
-        "pushf; "                                                       \
-        "notl %"_LO32 _tmp"; "                                          \
-        "andl %"_LO32 _tmp",("_STK"); "                                 \
-        "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "   \
-        "pop  %"_tmp"; "                                                \
-        "orl  %"_LO32 _tmp",("_STK"); "                                 \
-        "popf; "                                                        \
-        "pop  %"_sav"; "
-
-/* After executing instruction: write-back necessary bits in EFLAGS. */
-#define _POST_EFLAGS(_sav, _msk, _tmp) \
-        /* _sav |= EFLAGS & _msk; */            \
-        "pushf; "                               \
-        "pop  %"_tmp"; "                        \
-        "andl %"_msk",%"_LO32 _tmp"; "          \
-        "orl  %"_LO32 _tmp",%"_sav"; "
-
 #ifdef CONFIG_X86_64
 #define ON64(x) x
 #else
 #define ON64(x)
 #endif
 
-#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype)   \
-        do {                                                            \
-                __asm__ __volatile__ (                                  \
-                        _PRE_EFLAGS("0", "4", "2")                      \
-                        _op _suffix " %"_x"3,%1; "                      \
-                        _POST_EFLAGS("0", "4", "2")                     \
-                        : "=m" ((ctxt)->eflags),                        \
-                          "+q" (*(_dsttype*)&(ctxt)->dst.val),          \
-                          "=&r" (_tmp)                                  \
-                        : _y ((ctxt)->src.val), "i" (EFLAGS_MASK));     \
-        } while (0)
-
-
-/* Raw emulation: instruction has two explicit operands. */
-#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy)          \
-        do {                                                            \
-                unsigned long _tmp;                                     \
-                                                                        \
-                switch ((ctxt)->dst.bytes) {                            \
-                case 2:                                                 \
-                        ____emulate_2op(ctxt,_op,_wx,_wy,"w",u16);      \
-                        break;                                          \
-                case 4:                                                 \
-                        ____emulate_2op(ctxt,_op,_lx,_ly,"l",u32);      \
-                        break;                                          \
-                case 8:                                                 \
-                        ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
-                        break;                                          \
-                }                                                       \
-        } while (0)
-
-#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)              \
-        do {                                                                 \
-                unsigned long _tmp;                                          \
-                switch ((ctxt)->dst.bytes) {                                 \
-                case 1:                                                      \
-                        ____emulate_2op(ctxt,_op,_bx,_by,"b",u8);            \
-                        break;                                               \
-                default:                                                     \
-                        __emulate_2op_nobyte(ctxt, _op,                      \
-                                             _wx, _wy, _lx, _ly, _qx, _qy);  \
-                        break;                                               \
-                }                                                            \
-        } while (0)
-
-/* Source operand is byte-sized and may be restricted to just %cl. */
-#define emulate_2op_SrcB(ctxt, _op)                                     \
-        __emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
-
-/* Source operand is byte, word, long or quad sized. */
-#define emulate_2op_SrcV(ctxt, _op)                                     \
-        __emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
-
-/* Source operand is word, long or quad sized. */
-#define emulate_2op_SrcV_nobyte(ctxt, _op)                              \
-        __emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
-
-/* Instruction has three operands and one operand is stored in ECX register */
-#define __emulate_2op_cl(ctxt, _op, _suffix, _type)             \
-        do {                                                            \
-                unsigned long _tmp;                                     \
-                _type _clv  = (ctxt)->src2.val;                         \
-                _type _srcv = (ctxt)->src.val;                          \
-                _type _dstv = (ctxt)->dst.val;                          \
-                                                                        \
-                __asm__ __volatile__ (                                  \
-                        _PRE_EFLAGS("0", "5", "2")                      \
-                        _op _suffix " %4,%1 \n"                         \
-                        _POST_EFLAGS("0", "5", "2")                     \
-                        : "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
-                        : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)   \
-                        );                                              \
-                                                                        \
-                (ctxt)->src2.val  = (unsigned long) _clv;               \
-                (ctxt)->src2.val = (unsigned long) _srcv;               \
-                (ctxt)->dst.val = (unsigned long) _dstv;                \
-        } while (0)
-
-#define emulate_2op_cl(ctxt, _op)                                       \
-        do {                                                            \
-                switch ((ctxt)->dst.bytes) {                            \
-                case 2:                                                 \
-                        __emulate_2op_cl(ctxt, _op, "w", u16);          \
-                        break;                                          \
-                case 4:                                                 \
-                        __emulate_2op_cl(ctxt, _op, "l", u32);          \
-                        break;                                          \
-                case 8:                                                 \
-                        ON64(__emulate_2op_cl(ctxt, _op, "q", ulong));  \
-                        break;                                          \
-                }                                                       \
-        } while (0)
-
-#define __emulate_1op(ctxt, _op, _suffix)                               \
-        do {                                                            \
-                unsigned long _tmp;                                     \
-                                                                        \
-                __asm__ __volatile__ (                                  \
-                        _PRE_EFLAGS("0", "3", "2")                      \
-                        _op _suffix " %1; "                             \
-                        _POST_EFLAGS("0", "3", "2")                     \
-                        : "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
-                          "=&r" (_tmp)                                  \
-                        : "i" (EFLAGS_MASK));                           \
-        } while (0)
-
-/* Instruction has only one explicit operand (no source operand). */
-#define emulate_1op(ctxt, _op)                                          \
-        do {                                                            \
-                switch ((ctxt)->dst.bytes) {                            \
-                case 1: __emulate_1op(ctxt, _op, "b"); break;           \
-                case 2: __emulate_1op(ctxt, _op, "w"); break;           \
-                case 4: __emulate_1op(ctxt, _op, "l"); break;           \
-                case 8: ON64(__emulate_1op(ctxt, _op, "q")); break;     \
-                }                                                       \
-        } while (0)
-
 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
 
 #define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
@@ -462,7 +314,10 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
 #define FOPNOP() FOP_ALIGN FOP_RET
 
 #define FOP1E(op,  dst) \
-        FOP_ALIGN #op " %" #dst " \n\t" FOP_RET
+        FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET
+
+#define FOP1EEX(op,  dst) \
+        FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
 
 #define FASTOP1(op) \
         FOP_START(op) \
@@ -472,24 +327,42 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
         ON64(FOP1E(op##q, rax)) \
         FOP_END
 
+/* 1-operand, using src2 (for MUL/DIV r/m) */
+#define FASTOP1SRC2(op, name) \
+        FOP_START(name) \
+        FOP1E(op, cl) \
+        FOP1E(op, cx) \
+        FOP1E(op, ecx) \
+        ON64(FOP1E(op, rcx)) \
+        FOP_END
+
+/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
+#define FASTOP1SRC2EX(op, name) \
+        FOP_START(name) \
+        FOP1EEX(op, cl) \
+        FOP1EEX(op, cx) \
+        FOP1EEX(op, ecx) \
+        ON64(FOP1EEX(op, rcx)) \
+        FOP_END
+
 #define FOP2E(op,  dst, src)       \
         FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET
 
 #define FASTOP2(op) \
         FOP_START(op) \
-        FOP2E(op##b, al, bl) \
-        FOP2E(op##w, ax, bx) \
-        FOP2E(op##l, eax, ebx) \
-        ON64(FOP2E(op##q, rax, rbx)) \
+        FOP2E(op##b, al, dl) \
+        FOP2E(op##w, ax, dx) \
+        FOP2E(op##l, eax, edx) \
+        ON64(FOP2E(op##q, rax, rdx)) \
         FOP_END
 
 /* 2 operand, word only */
 #define FASTOP2W(op) \
         FOP_START(op) \
         FOPNOP() \
-        FOP2E(op##w, ax, bx) \
-        FOP2E(op##l, eax, ebx) \
-        ON64(FOP2E(op##q, rax, rbx)) \
+        FOP2E(op##w, ax, dx) \
+        FOP2E(op##l, eax, edx) \
+        ON64(FOP2E(op##q, rax, rdx)) \
         FOP_END
 
 /* 2 operand, src is CL */
@@ -508,14 +381,17 @@ static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));
 #define FASTOP3WCL(op) \
         FOP_START(op) \
         FOPNOP() \
-        FOP3E(op##w, ax, bx, cl) \
-        FOP3E(op##l, eax, ebx, cl) \
-        ON64(FOP3E(op##q, rax, rbx, cl)) \
+        FOP3E(op##w, ax, dx, cl) \
+        FOP3E(op##l, eax, edx, cl) \
+        ON64(FOP3E(op##q, rax, rdx, cl)) \
         FOP_END
 
 /* Special case for SETcc - 1 instruction per cc */
 #define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"
 
+asm(".global kvm_fastop_exception \n"
+    "kvm_fastop_exception: xor %esi, %esi; ret");
+
 FOP_START(setcc)
 FOP_SETCC(seto)
 FOP_SETCC(setno)
@@ -538,47 +414,6 @@ FOP_END;
 FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
 FOP_END;
 
-#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex)                  \
-        do {                                                            \
-                unsigned long _tmp;                                     \
-                ulong *rax = reg_rmw((ctxt), VCPU_REGS_RAX);            \
-                ulong *rdx = reg_rmw((ctxt), VCPU_REGS_RDX);            \
-                                                                        \
-                __asm__ __volatile__ (                                  \
-                        _PRE_EFLAGS("0", "5", "1")                      \
-                        "1: \n\t"                                       \
-                        _op _suffix " %6; "                             \
-                        "2: \n\t"                                       \
-                        _POST_EFLAGS("0", "5", "1")                     \
-                        ".pushsection .fixup,\"ax\" \n\t"               \
-                        "3: movb $1, %4 \n\t"                           \
-                        "jmp 2b \n\t"                                   \
-                        ".popsection \n\t"                              \
-                        _ASM_EXTABLE(1b, 3b)                            \
-                        : "=m" ((ctxt)->eflags), "=&r" (_tmp),          \
-                          "+a" (*rax), "+d" (*rdx), "+qm"(_ex)          \
-                        : "i" (EFLAGS_MASK), "m" ((ctxt)->src.val));    \
-        } while (0)
-
-/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
-#define emulate_1op_rax_rdx(ctxt, _op, _ex)     \
-        do {                                                            \
-                switch((ctxt)->src.bytes) {                             \
-                case 1:                                                 \
-                        __emulate_1op_rax_rdx(ctxt, _op, "b", _ex);     \
-                        break;                                          \
-                case 2:                                                 \
-                        __emulate_1op_rax_rdx(ctxt, _op, "w", _ex);     \
-                        break;                                          \
-                case 4:                                                 \
-                        __emulate_1op_rax_rdx(ctxt, _op, "l", _ex);     \
-                        break;                                          \
-                case 8: ON64(                                           \
-                        __emulate_1op_rax_rdx(ctxt, _op, "q", _ex));    \
-                        break;                                          \
-                }                                                       \
-        } while (0)
-
 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
                                     enum x86_intercept intercept,
                                     enum x86_intercept_stage stage)
@@ -988,6 +823,11 @@ FASTOP2(xor);
 FASTOP2(cmp);
 FASTOP2(test);
 
+FASTOP1SRC2(mul, mul_ex);
+FASTOP1SRC2(imul, imul_ex);
+FASTOP1SRC2EX(div, div_ex);
+FASTOP1SRC2EX(idiv, idiv_ex);
+
 FASTOP3WCL(shld);
 FASTOP3WCL(shrd);
 
@@ -1013,6 +853,8 @@ FASTOP2W(bts);
 FASTOP2W(btr);
 FASTOP2W(btc);
 
+FASTOP2(xadd);
+
 static u8 test_cc(unsigned int condition, unsigned long flags)
 {
         u8 rc;
@@ -1726,45 +1568,42 @@ static void write_register_operand(struct operand *op)
         }
 }
 
-static int writeback(struct x86_emulate_ctxt *ctxt)
+static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
 {
         int rc;
 
-        if (ctxt->d & NoWrite)
-                return X86EMUL_CONTINUE;
-
-        switch (ctxt->dst.type) {
+        switch (op->type) {
         case OP_REG:
-                write_register_operand(&ctxt->dst);
+                write_register_operand(op);
                 break;
         case OP_MEM:
                 if (ctxt->lock_prefix)
                         rc = segmented_cmpxchg(ctxt,
-                                               ctxt->dst.addr.mem,
-                                               &ctxt->dst.orig_val,
-                                               &ctxt->dst.val,
-                                               ctxt->dst.bytes);
+                                               op->addr.mem,
+                                               &op->orig_val,
+                                               &op->val,
+                                               op->bytes);
                 else
                         rc = segmented_write(ctxt,
-                                             ctxt->dst.addr.mem,
-                                             &ctxt->dst.val,
-                                             ctxt->dst.bytes);
+                                             op->addr.mem,
+                                             &op->val,
+                                             op->bytes);
                 if (rc != X86EMUL_CONTINUE)
                         return rc;
                 break;
         case OP_MEM_STR:
                 rc = segmented_write(ctxt,
-                                ctxt->dst.addr.mem,
-                                ctxt->dst.data,
-                                ctxt->dst.bytes * ctxt->dst.count);
+                                op->addr.mem,
+                                op->data,
+                                op->bytes * op->count);
                 if (rc != X86EMUL_CONTINUE)
                         return rc;
                 break;
         case OP_XMM:
-                write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
+                write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
                 break;
         case OP_MM:
-                write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
+                write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
                 break;
         case OP_NONE:
                 /* no writeback */
@@ -2117,42 +1956,6 @@ static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
-static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
-{
-        u8 ex = 0;
-
-        emulate_1op_rax_rdx(ctxt, "mul", ex);
-        return X86EMUL_CONTINUE;
-}
-
-static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
-{
-        u8 ex = 0;
-
-        emulate_1op_rax_rdx(ctxt, "imul", ex);
-        return X86EMUL_CONTINUE;
-}
-
-static int em_div_ex(struct x86_emulate_ctxt *ctxt)
-{
-        u8 de = 0;
-
-        emulate_1op_rax_rdx(ctxt, "div", de);
-        if (de)
-                return emulate_de(ctxt);
-        return X86EMUL_CONTINUE;
-}
-
-static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
-{
-        u8 de = 0;
-
-        emulate_1op_rax_rdx(ctxt, "idiv", de);
-        if (de)
-                return emulate_de(ctxt);
-        return X86EMUL_CONTINUE;
-}
-
 static int em_grp45(struct x86_emulate_ctxt *ctxt)
 {
         int rc = X86EMUL_CONTINUE;
@@ -3734,10 +3537,10 @@ static const struct opcode group3[] = {
         F(DstMem | SrcImm | NoWrite, em_test),
         F(DstMem | SrcNone | Lock, em_not),
         F(DstMem | SrcNone | Lock, em_neg),
-        I(SrcMem, em_mul_ex),
-        I(SrcMem, em_imul_ex),
-        I(SrcMem, em_div_ex),
-        I(SrcMem, em_idiv_ex),
+        F(DstXacc | Src2Mem, em_mul_ex),
+        F(DstXacc | Src2Mem, em_imul_ex),
+        F(DstXacc | Src2Mem, em_div_ex),
+        F(DstXacc | Src2Mem, em_idiv_ex),
 };
 
 static const struct opcode group4[] = {
@@ -4064,7 +3867,7 @@ static const struct opcode twobyte_table[256] = {
         F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
         D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
         /* 0xC0 - 0xC7 */
-        D2bv(DstMem | SrcReg | ModRM | Lock),
+        F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
         N, D(DstMem | SrcReg | ModRM | Mov),
         N, N, N, GD(0, &group9),
         /* 0xC8 - 0xCF */
@@ -4172,6 +3975,24 @@ static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
                 fetch_register_operand(op);
                 op->orig_val = op->val;
                 break;
+        case OpAccLo:
+                op->type = OP_REG;
+                op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
+                op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
+                fetch_register_operand(op);
+                op->orig_val = op->val;
+                break;
+        case OpAccHi:
+                if (ctxt->d & ByteOp) {
+                        op->type = OP_NONE;
+                        break;
+                }
+                op->type = OP_REG;
+                op->bytes = ctxt->op_bytes;
+                op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
+                fetch_register_operand(op);
+                op->orig_val = op->val;
+                break;
         case OpDI:
                 op->type = OP_MEM;
                 op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
@@ -4553,11 +4374,15 @@ static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
 static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
 {
         ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
-        fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
+        if (!(ctxt->d & ByteOp))
+                fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
         asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
-            : "+a"(ctxt->dst.val), "+b"(ctxt->src.val), [flags]"+D"(flags)
-        : "c"(ctxt->src2.val), [fastop]"S"(fop));
+            : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
+              [fastop]"+S"(fop)
+            : "c"(ctxt->src2.val));
         ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
+        if (!fop) /* exception is returned in fop variable */
+                return emulate_de(ctxt);
         return X86EMUL_CONTINUE;
 }
 
@@ -4773,9 +4598,17 @@ special_insn:
                 goto done;
 
 writeback:
-        rc = writeback(ctxt);
-        if (rc != X86EMUL_CONTINUE)
-                goto done;
+        if (!(ctxt->d & NoWrite)) {
+                rc = writeback(ctxt, &ctxt->dst);
+                if (rc != X86EMUL_CONTINUE)
+                        goto done;
+        }
+        if (ctxt->d & SrcWrite) {
+                BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
+                rc = writeback(ctxt, &ctxt->src);
+                if (rc != X86EMUL_CONTINUE)
+                        goto done;
+        }
 
         /*
          * restore dst type in case the decoding will be reused
@@ -4872,12 +4705,6 @@ twobyte_insn:
                 ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
                                                         (s16) ctxt->src.val;
                 break;
-        case 0xc0 ... 0xc1:     /* xadd */
-                fastop(ctxt, em_add);
-                /* Write back the register source. */
-                ctxt->src.val = ctxt->dst.orig_val;
-                write_register_operand(&ctxt->src);
-                break;
         case 0xc3:              /* movnti */
                 ctxt->dst.bytes = ctxt->op_bytes;
                 ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0eee2c8b64d1..afc11245827c 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1608,8 +1608,8 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
                 return;
 
         if (atomic_read(&apic->lapic_timer.pending) > 0) {
-                if (kvm_apic_local_deliver(apic, APIC_LVTT))
-                        atomic_dec(&apic->lapic_timer.pending);
+                kvm_apic_local_deliver(apic, APIC_LVTT);
+                atomic_set(&apic->lapic_timer.pending, 0);
         }
 }
 
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 004cc87b781c..0d094da49541 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -197,15 +197,63 @@ void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 }
 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
 
-static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
+/*
+ * spte bits of bit 3 ~ bit 11 are used as low 9 bits of generation number,
+ * the bits of bits 52 ~ bit 61 are used as high 10 bits of generation
+ * number.
+ */
+#define MMIO_SPTE_GEN_LOW_SHIFT         3
+#define MMIO_SPTE_GEN_HIGH_SHIFT        52
+
+#define MMIO_GEN_SHIFT                  19
+#define MMIO_GEN_LOW_SHIFT              9
+#define MMIO_GEN_LOW_MASK               ((1 << MMIO_GEN_LOW_SHIFT) - 1)
+#define MMIO_GEN_MASK                   ((1 << MMIO_GEN_SHIFT) - 1)
+#define MMIO_MAX_GEN                    ((1 << MMIO_GEN_SHIFT) - 1)
+
+static u64 generation_mmio_spte_mask(unsigned int gen)
 {
-        struct kvm_mmu_page *sp =  page_header(__pa(sptep));
+        u64 mask;
+
+        WARN_ON(gen > MMIO_MAX_GEN);
+
+        mask = (gen & MMIO_GEN_LOW_MASK) << MMIO_SPTE_GEN_LOW_SHIFT;
+        mask |= ((u64)gen >> MMIO_GEN_LOW_SHIFT) << MMIO_SPTE_GEN_HIGH_SHIFT;
+        return mask;
+}
+
+static unsigned int get_mmio_spte_generation(u64 spte)
+{
+        unsigned int gen;
+
+        spte &= ~shadow_mmio_mask;
+
+        gen = (spte >> MMIO_SPTE_GEN_LOW_SHIFT) & MMIO_GEN_LOW_MASK;
+        gen |= (spte >> MMIO_SPTE_GEN_HIGH_SHIFT) << MMIO_GEN_LOW_SHIFT;
+        return gen;
+}
+
+static unsigned int kvm_current_mmio_generation(struct kvm *kvm)
+{
+        /*
+         * Init kvm generation close to MMIO_MAX_GEN to easily test the
+         * code of handling generation number wrap-around.
+         */
+        return (kvm_memslots(kvm)->generation +
+                      MMIO_MAX_GEN - 150) & MMIO_GEN_MASK;
+}
+
+static void mark_mmio_spte(struct kvm *kvm, u64 *sptep, u64 gfn,
+                           unsigned access)
+{
+        unsigned int gen = kvm_current_mmio_generation(kvm);
+        u64 mask = generation_mmio_spte_mask(gen);
 
         access &= ACC_WRITE_MASK | ACC_USER_MASK;
+        mask |= shadow_mmio_mask | access | gfn << PAGE_SHIFT;
 
-        sp->mmio_cached = true;
-        trace_mark_mmio_spte(sptep, gfn, access);
-        mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
+        trace_mark_mmio_spte(sptep, gfn, access, gen);
+        mmu_spte_set(sptep, mask);
 }
 
 static bool is_mmio_spte(u64 spte)
@@ -215,24 +263,38 @@ static bool is_mmio_spte(u64 spte)
 
 static gfn_t get_mmio_spte_gfn(u64 spte)
 {
-        return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
+        u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
+        return (spte & ~mask) >> PAGE_SHIFT;
 }
 
 static unsigned get_mmio_spte_access(u64 spte)
 {
-        return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
+        u64 mask = generation_mmio_spte_mask(MMIO_MAX_GEN) | shadow_mmio_mask;
+        return (spte & ~mask) & ~PAGE_MASK;
 }
 
-static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
+static bool set_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
+                          pfn_t pfn, unsigned access)
 {
         if (unlikely(is_noslot_pfn(pfn))) {
-                mark_mmio_spte(sptep, gfn, access);
+                mark_mmio_spte(kvm, sptep, gfn, access);
                 return true;
         }
 
         return false;
 }
 
+static bool check_mmio_spte(struct kvm *kvm, u64 spte)
+{
+        unsigned int kvm_gen, spte_gen;
+
+        kvm_gen = kvm_current_mmio_generation(kvm);
+        spte_gen = get_mmio_spte_generation(spte);
+
+        trace_check_mmio_spte(spte, kvm_gen, spte_gen);
+        return likely(kvm_gen == spte_gen);
+}
+
 static inline u64 rsvd_bits(int s, int e)
 {
         return ((1ULL << (e - s + 1)) - 1) << s;
@@ -404,9 +466,20 @@ static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
 /*
  * The idea using the light way get the spte on x86_32 guest is from
  * gup_get_pte(arch/x86/mm/gup.c).
- * The difference is we can not catch the spte tlb flush if we leave
- * guest mode, so we emulate it by increase clear_spte_count when spte
- * is cleared.
+ *
+ * An spte tlb flush may be pending, because kvm_set_pte_rmapp
+ * coalesces them and we are running out of the MMU lock.  Therefore
+ * we need to protect against in-progress updates of the spte.
+ *
+ * Reading the spte while an update is in progress may get the old value
+ * for the high part of the spte.  The race is fine for a present->non-present
+ * change (because the high part of the spte is ignored for non-present spte),
+ * but for a present->present change we must reread the spte.
+ *
+ * All such changes are done in two steps (present->non-present and
+ * non-present->present), hence it is enough to count the number of
+ * present->non-present updates: if it changed while reading the spte,
+ * we might have hit the race.  This is done using clear_spte_count.
  */
 static u64 __get_spte_lockless(u64 *sptep)
 {
@@ -1511,6 +1584,12 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
         if (!direct)
                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
+
+        /*
+         * The active_mmu_pages list is the FIFO list, do not move the
+         * page until it is zapped. kvm_zap_obsolete_pages depends on
+         * this feature. See the comments in kvm_zap_obsolete_pages().
+         */
         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
         sp->parent_ptes = 0;
         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
@@ -1648,6 +1727,16 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
                                     struct list_head *invalid_list);
 
+/*
+ * NOTE: we should pay more attention on the zapped-obsolete page
+ * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk
+ * since it has been deleted from active_mmu_pages but still can be found
+ * at hast list.
+ *
+ * for_each_gfn_indirect_valid_sp has skipped that kind of page and
+ * kvm_mmu_get_page(), the only user of for_each_gfn_sp(), has skipped
+ * all the obsolete pages.
+ */
 #define for_each_gfn_sp(_kvm, _sp, _gfn)                                \
         hlist_for_each_entry(_sp,                                       \
           &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \
@@ -1838,6 +1927,11 @@ static void clear_sp_write_flooding_count(u64 *spte)
         __clear_sp_write_flooding_count(sp);
 }
 
+static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
+{
+        return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
+}
+
 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                                              gfn_t gfn,
                                              gva_t gaddr,
@@ -1864,6 +1958,9 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                 role.quadrant = quadrant;
         }
         for_each_gfn_sp(vcpu->kvm, sp, gfn) {
+                if (is_obsolete_sp(vcpu->kvm, sp))
+                        continue;
+
                 if (!need_sync && sp->unsync)
                         need_sync = true;
 
@@ -1900,6 +1997,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
 
                 account_shadowed(vcpu->kvm, gfn);
         }
+        sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
         init_shadow_page_table(sp);
         trace_kvm_mmu_get_page(sp, true);
         return sp;
@@ -2070,8 +2168,10 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
         kvm_mmu_page_unlink_children(kvm, sp);
         kvm_mmu_unlink_parents(kvm, sp);
+
         if (!sp->role.invalid && !sp->role.direct)
                 unaccount_shadowed(kvm, sp->gfn);
+
         if (sp->unsync)
                 kvm_unlink_unsync_page(kvm, sp);
         if (!sp->root_count) {
@@ -2081,7 +2181,13 @@ static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
                 kvm_mod_used_mmu_pages(kvm, -1);
         } else {
                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
-                kvm_reload_remote_mmus(kvm);
+
+                /*
+                 * The obsolete pages can not be used on any vcpus.
+                 * See the comments in kvm_mmu_invalidate_zap_all_pages().
+                 */
+                if (!sp->role.invalid && !is_obsolete_sp(kvm, sp))
+                        kvm_reload_remote_mmus(kvm);
         }
 
         sp->role.invalid = 1;
@@ -2331,7 +2437,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
         u64 spte;
         int ret = 0;
 
-        if (set_mmio_spte(sptep, gfn, pfn, pte_access))
+        if (set_mmio_spte(vcpu->kvm, sptep, gfn, pfn, pte_access))
                 return 0;
 
         spte = PT_PRESENT_MASK;
@@ -2869,22 +2975,25 @@ static void mmu_free_roots(struct kvm_vcpu *vcpu)
 
         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
                 return;
-        spin_lock(&vcpu->kvm->mmu_lock);
+
         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
              vcpu->arch.mmu.direct_map)) {
                 hpa_t root = vcpu->arch.mmu.root_hpa;
 
+                spin_lock(&vcpu->kvm->mmu_lock);
                 sp = page_header(root);
                 --sp->root_count;
                 if (!sp->root_count && sp->role.invalid) {
                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
                 }
-                vcpu->arch.mmu.root_hpa = INVALID_PAGE;
                 spin_unlock(&vcpu->kvm->mmu_lock);
+                vcpu->arch.mmu.root_hpa = INVALID_PAGE;
                 return;
         }
+
+        spin_lock(&vcpu->kvm->mmu_lock);
         for (i = 0; i < 4; ++i) {
                 hpa_t root = vcpu->arch.mmu.pae_root[i];
 
@@ -3148,17 +3257,12 @@ static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
         return spte;
 }
 
-/*
- * If it is a real mmio page fault, return 1 and emulat the instruction
- * directly, return 0 to let CPU fault again on the address, -1 is
- * returned if bug is detected.
- */
 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
 {
         u64 spte;
 
         if (quickly_check_mmio_pf(vcpu, addr, direct))
-                return 1;
+                return RET_MMIO_PF_EMULATE;
 
         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
 
@@ -3166,12 +3270,15 @@ int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
                 gfn_t gfn = get_mmio_spte_gfn(spte);
                 unsigned access = get_mmio_spte_access(spte);
 
+                if (!check_mmio_spte(vcpu->kvm, spte))
+                        return RET_MMIO_PF_INVALID;
+
                 if (direct)
                         addr = 0;
 
                 trace_handle_mmio_page_fault(addr, gfn, access);
                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
-                return 1;
+                return RET_MMIO_PF_EMULATE;
         }
 
         /*
@@ -3179,13 +3286,13 @@ int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
          * it's a BUG if the gfn is not a mmio page.
          */
         if (direct && !check_direct_spte_mmio_pf(spte))
-                return -1;
+                return RET_MMIO_PF_BUG;
 
         /*
          * If the page table is zapped by other cpus, let CPU fault again on
          * the address.
          */
-        return 0;
+        return RET_MMIO_PF_RETRY;
 }
 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
 
@@ -3195,7 +3302,7 @@ static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
         int ret;
 
         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
-        WARN_ON(ret < 0);
+        WARN_ON(ret == RET_MMIO_PF_BUG);
         return ret;
 }
 
@@ -3207,8 +3314,12 @@ static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
 
         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
 
-        if (unlikely(error_code & PFERR_RSVD_MASK))
-                return handle_mmio_page_fault(vcpu, gva, error_code, true);
+        if (unlikely(error_code & PFERR_RSVD_MASK)) {
+                r = handle_mmio_page_fault(vcpu, gva, error_code, true);
+
+                if (likely(r != RET_MMIO_PF_INVALID))
+                        return r;
+        }
 
         r = mmu_topup_memory_caches(vcpu);
         if (r)
@@ -3284,8 +3395,12 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
         ASSERT(vcpu);
         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
 
-        if (unlikely(error_code & PFERR_RSVD_MASK))
-                return handle_mmio_page_fault(vcpu, gpa, error_code, true);
+        if (unlikely(error_code & PFERR_RSVD_MASK)) {
+                r = handle_mmio_page_fault(vcpu, gpa, error_code, true);
+
+                if (likely(r != RET_MMIO_PF_INVALID))
+                        return r;
+        }
 
         r = mmu_topup_memory_caches(vcpu);
         if (r)
@@ -3391,8 +3506,8 @@ static inline void protect_clean_gpte(unsigned *access, unsigned gpte)
         *access &= mask;
 }
 
-static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
-                           int *nr_present)
+static bool sync_mmio_spte(struct kvm *kvm, u64 *sptep, gfn_t gfn,
+                           unsigned access, int *nr_present)
 {
         if (unlikely(is_mmio_spte(*sptep))) {
                 if (gfn != get_mmio_spte_gfn(*sptep)) {
@@ -3401,7 +3516,7 @@ static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
                 }
 
                 (*nr_present)++;
-                mark_mmio_spte(sptep, gfn, access);
+                mark_mmio_spte(kvm, sptep, gfn, access);
                 return true;
         }
 
@@ -3764,9 +3879,7 @@ int kvm_mmu_load(struct kvm_vcpu *vcpu)
         if (r)
                 goto out;
         r = mmu_alloc_roots(vcpu);
-        spin_lock(&vcpu->kvm->mmu_lock);
-        mmu_sync_roots(vcpu);
-        spin_unlock(&vcpu->kvm->mmu_lock);
+        kvm_mmu_sync_roots(vcpu);
         if (r)
                 goto out;
         /* set_cr3() should ensure TLB has been flushed */
@@ -4179,39 +4292,107 @@ void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
         spin_unlock(&kvm->mmu_lock);
 }
 
-void kvm_mmu_zap_all(struct kvm *kvm)
+#define BATCH_ZAP_PAGES 10
+static void kvm_zap_obsolete_pages(struct kvm *kvm)
 {
         struct kvm_mmu_page *sp, *node;
-        LIST_HEAD(invalid_list);
+        int batch = 0;
 
-        spin_lock(&kvm->mmu_lock);
 restart:
-        list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
-                if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
+        list_for_each_entry_safe_reverse(sp, node,
+              &kvm->arch.active_mmu_pages, link) {
+                int ret;
+
+                /*
+                 * No obsolete page exists before new created page since
+                 * active_mmu_pages is the FIFO list.
+                 */
+                if (!is_obsolete_sp(kvm, sp))
+                        break;
+
+                /*
+                 * Since we are reversely walking the list and the invalid
+                 * list will be moved to the head, skip the invalid page
+                 * can help us to avoid the infinity list walking.
+                 */
+                if (sp->role.invalid)
+                        continue;
+
+                /*
+                 * Need not flush tlb since we only zap the sp with invalid
+                 * generation number.
+                 */
+                if (batch >= BATCH_ZAP_PAGES &&
+                      cond_resched_lock(&kvm->mmu_lock)) {
+                        batch = 0;
+                        goto restart;
+                }
+
+                ret = kvm_mmu_prepare_zap_page(kvm, sp,
+                                &kvm->arch.zapped_obsolete_pages);
+                batch += ret;
+
+                if (ret)
                         goto restart;
+        }
 
-        kvm_mmu_commit_zap_page(kvm, &invalid_list);
-        spin_unlock(&kvm->mmu_lock);
+        /*
+         * Should flush tlb before free page tables since lockless-walking
+         * may use the pages.
+         */
+        kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
 }
 
-void kvm_mmu_zap_mmio_sptes(struct kvm *kvm)
+/*
+ * Fast invalidate all shadow pages and use lock-break technique
+ * to zap obsolete pages.
+ *
+ * It's required when memslot is being deleted or VM is being
+ * destroyed, in these cases, we should ensure that KVM MMU does
+ * not use any resource of the being-deleted slot or all slots
+ * after calling the function.
+ */
+void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm)
 {
-        struct kvm_mmu_page *sp, *node;
-        LIST_HEAD(invalid_list);
-
         spin_lock(&kvm->mmu_lock);
-restart:
-        list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
-                if (!sp->mmio_cached)
-                        continue;
-                if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
-                        goto restart;
-        }
+        trace_kvm_mmu_invalidate_zap_all_pages(kvm);
+        kvm->arch.mmu_valid_gen++;
 
-        kvm_mmu_commit_zap_page(kvm, &invalid_list);
+        /*
+         * Notify all vcpus to reload its shadow page table
+         * and flush TLB. Then all vcpus will switch to new
+         * shadow page table with the new mmu_valid_gen.
+         *
+         * Note: we should do this under the protection of
+         * mmu-lock, otherwise, vcpu would purge shadow page
+         * but miss tlb flush.
+         */
+        kvm_reload_remote_mmus(kvm);
+
+        kvm_zap_obsolete_pages(kvm);
         spin_unlock(&kvm->mmu_lock);
 }
 
+static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
+{
+        return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
+}
+
+void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm)
+{
+        /*
+         * The very rare case: if the generation-number is round,
+         * zap all shadow pages.
+         *
+         * The max value is MMIO_MAX_GEN - 1 since it is not called
+         * when mark memslot invalid.
+         */
+        if (unlikely(kvm_current_mmio_generation(kvm) >= (MMIO_MAX_GEN - 1))) {
+                printk_ratelimited(KERN_INFO "kvm: zapping shadow pages for mmio generation wraparound\n");
+                kvm_mmu_invalidate_zap_all_pages(kvm);
+        }
+}
+
 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
 {
         struct kvm *kvm;
@@ -4240,15 +4421,23 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
                  * want to shrink a VM that only started to populate its MMU
                  * anyway.
                  */
-                if (!kvm->arch.n_used_mmu_pages)
+                if (!kvm->arch.n_used_mmu_pages &&
+                      !kvm_has_zapped_obsolete_pages(kvm))
                         continue;
 
                 idx = srcu_read_lock(&kvm->srcu);
                 spin_lock(&kvm->mmu_lock);
 
+                if (kvm_has_zapped_obsolete_pages(kvm)) {
+                        kvm_mmu_commit_zap_page(kvm,
+                              &kvm->arch.zapped_obsolete_pages);
+                        goto unlock;
+                }
+
                 prepare_zap_oldest_mmu_page(kvm, &invalid_list);
                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
 
+unlock:
                 spin_unlock(&kvm->mmu_lock);
                 srcu_read_unlock(&kvm->srcu, idx);
 
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 2adcbc2cac6d..5b59c573aba7 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -52,6 +52,23 @@
 
 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask);
+
+/*
+ * Return values of handle_mmio_page_fault_common:
+ * RET_MMIO_PF_EMULATE: it is a real mmio page fault, emulate the instruction
+ *                      directly.
+ * RET_MMIO_PF_INVALID: invalid spte is detected then let the real page
+ *                      fault path update the mmio spte.
+ * RET_MMIO_PF_RETRY: let CPU fault again on the address.
+ * RET_MMIO_PF_BUG: bug is detected.
+ */
+enum {
+        RET_MMIO_PF_EMULATE = 1,
+        RET_MMIO_PF_INVALID = 2,
+        RET_MMIO_PF_RETRY = 0,
+        RET_MMIO_PF_BUG = -1
+};
+
 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct);
 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context);
 
@@ -97,4 +114,5 @@ static inline bool permission_fault(struct kvm_mmu *mmu, unsigned pte_access,
         return (mmu->permissions[pfec >> 1] >> pte_access) & 1;
 }
 
+void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm);
 #endif
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
index b8f6172f4174..9d2e0ffcb190 100644
--- a/arch/x86/kvm/mmutrace.h
+++ b/arch/x86/kvm/mmutrace.h
@@ -7,16 +7,18 @@
 #undef TRACE_SYSTEM
 #define TRACE_SYSTEM kvmmmu
 
-#define KVM_MMU_PAGE_FIELDS \
-        __field(__u64, gfn) \
-        __field(__u32, role) \
-        __field(__u32, root_count) \
+#define KVM_MMU_PAGE_FIELDS                     \
+        __field(unsigned long, mmu_valid_gen)   \
+        __field(__u64, gfn)                     \
+        __field(__u32, role)                    \
+        __field(__u32, root_count)              \
         __field(bool, unsync)
 
-#define KVM_MMU_PAGE_ASSIGN(sp)                      \
-        __entry->gfn = sp->gfn;                      \
-        __entry->role = sp->role.word;               \
-        __entry->root_count = sp->root_count;        \
+#define KVM_MMU_PAGE_ASSIGN(sp)                         \
+        __entry->mmu_valid_gen = sp->mmu_valid_gen;     \
+        __entry->gfn = sp->gfn;                         \
+        __entry->role = sp->role.word;                  \
+        __entry->root_count = sp->root_count;           \
         __entry->unsync = sp->unsync;
 
 #define KVM_MMU_PAGE_PRINTK() ({                                        \
@@ -28,8 +30,8 @@
                                                                         \
         role.word = __entry->role;                                      \
                                                                         \
-        trace_seq_printf(p, "sp gfn %llx %u%s q%u%s %s%s"               \
-                         " %snxe root %u %s%c",                         \
+        trace_seq_printf(p, "sp gen %lx gfn %llx %u%s q%u%s %s%s"       \
+                         " %snxe root %u %s%c", __entry->mmu_valid_gen, \
                          __entry->gfn, role.level,                      \
                          role.cr4_pae ? " pae" : "",                    \
                          role.quadrant,                                 \
@@ -197,23 +199,25 @@ DEFINE_EVENT(kvm_mmu_page_class, kvm_mmu_prepare_zap_page,
 
 TRACE_EVENT(
         mark_mmio_spte,
-        TP_PROTO(u64 *sptep, gfn_t gfn, unsigned access),
-        TP_ARGS(sptep, gfn, access),
+        TP_PROTO(u64 *sptep, gfn_t gfn, unsigned access, unsigned int gen),
+        TP_ARGS(sptep, gfn, access, gen),
 
         TP_STRUCT__entry(
                 __field(void *, sptep)
                 __field(gfn_t, gfn)
                 __field(unsigned, access)
+                __field(unsigned int, gen)
         ),
 
         TP_fast_assign(
                 __entry->sptep = sptep;
                 __entry->gfn = gfn;
                 __entry->access = access;
+                __entry->gen = gen;
         ),
 
-        TP_printk("sptep:%p gfn %llx access %x", __entry->sptep, __entry->gfn,
-                  __entry->access)
+        TP_printk("sptep:%p gfn %llx access %x gen %x", __entry->sptep,
+                  __entry->gfn, __entry->access, __entry->gen)
 );
 
 TRACE_EVENT(
@@ -274,6 +278,50 @@ TRACE_EVENT(
                   __spte_satisfied(old_spte), __spte_satisfied(new_spte)
         )
 );
+
+TRACE_EVENT(
+        kvm_mmu_invalidate_zap_all_pages,
+        TP_PROTO(struct kvm *kvm),
+        TP_ARGS(kvm),
+
+        TP_STRUCT__entry(
+                __field(unsigned long, mmu_valid_gen)
+                __field(unsigned int, mmu_used_pages)
+        ),
+
+        TP_fast_assign(
+                __entry->mmu_valid_gen = kvm->arch.mmu_valid_gen;
+                __entry->mmu_used_pages = kvm->arch.n_used_mmu_pages;
+        ),
+
+        TP_printk("kvm-mmu-valid-gen %lx used_pages %x",
+                  __entry->mmu_valid_gen, __entry->mmu_used_pages
+        )
+);
+
+
+TRACE_EVENT(
+        check_mmio_spte,
+        TP_PROTO(u64 spte, unsigned int kvm_gen, unsigned int spte_gen),
+        TP_ARGS(spte, kvm_gen, spte_gen),
+
+        TP_STRUCT__entry(
+                __field(unsigned int, kvm_gen)
+                __field(unsigned int, spte_gen)
+                __field(u64, spte)
+        ),
+
+        TP_fast_assign(
+                __entry->kvm_gen = kvm_gen;
+                __entry->spte_gen = spte_gen;
+                __entry->spte = spte;
+        ),
+
+        TP_printk("spte %llx kvm_gen %x spte-gen %x valid %d", __entry->spte,
+                  __entry->kvm_gen, __entry->spte_gen,
+                  __entry->kvm_gen == __entry->spte_gen
+        )
+);
 #endif /* _TRACE_KVMMMU_H */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index da20860b457a..7769699d48a8 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -552,9 +552,12 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
 
         pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
 
-        if (unlikely(error_code & PFERR_RSVD_MASK))
-                return handle_mmio_page_fault(vcpu, addr, error_code,
+        if (unlikely(error_code & PFERR_RSVD_MASK)) {
+                r = handle_mmio_page_fault(vcpu, addr, error_code,
                                               mmu_is_nested(vcpu));
+                if (likely(r != RET_MMIO_PF_INVALID))
+                        return r;
+        };
 
         r = mmu_topup_memory_caches(vcpu);
         if (r)
@@ -792,7 +795,8 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                 pte_access &= gpte_access(vcpu, gpte);
                 protect_clean_gpte(&pte_access, gpte);
 
-                if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
+                if (sync_mmio_spte(vcpu->kvm, &sp->spt[i], gfn, pte_access,
+                      &nr_present))
                         continue;
 
                 if (gfn != sp->gfns[i]) {
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index a14a6eaf871d..c0bc80391e40 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1026,7 +1026,10 @@ static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
                 g_tsc_offset = svm->vmcb->control.tsc_offset -
                                svm->nested.hsave->control.tsc_offset;
                 svm->nested.hsave->control.tsc_offset = offset;
-        }
+        } else
+                trace_kvm_write_tsc_offset(vcpu->vcpu_id,
+                                           svm->vmcb->control.tsc_offset,
+                                           offset);
 
         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 
@@ -1044,6 +1047,11 @@ static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool ho
         svm->vmcb->control.tsc_offset += adjustment;
         if (is_guest_mode(vcpu))
                 svm->nested.hsave->control.tsc_offset += adjustment;
+        else
+                trace_kvm_write_tsc_offset(vcpu->vcpu_id,
+                                     svm->vmcb->control.tsc_offset - adjustment,
+                                     svm->vmcb->control.tsc_offset);
+
         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 }
 
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h
index fe5e00ed7036..545245d7cc63 100644
--- a/arch/x86/kvm/trace.h
+++ b/arch/x86/kvm/trace.h
@@ -756,6 +756,27 @@ TRACE_EVENT(
                   __entry->gpa_match ? "GPA" : "GVA")
 );
 
+TRACE_EVENT(kvm_write_tsc_offset,
+        TP_PROTO(unsigned int vcpu_id, __u64 previous_tsc_offset,
+                 __u64 next_tsc_offset),
+        TP_ARGS(vcpu_id, previous_tsc_offset, next_tsc_offset),
+
+        TP_STRUCT__entry(
+                __field( unsigned int,  vcpu_id                         )
+                __field(        __u64,  previous_tsc_offset             )
+                __field(        __u64,  next_tsc_offset                 )
+        ),
+
+        TP_fast_assign(
+                __entry->vcpu_id                = vcpu_id;
+                __entry->previous_tsc_offset    = previous_tsc_offset;
+                __entry->next_tsc_offset        = next_tsc_offset;
+        ),
+
+        TP_printk("vcpu=%u prev=%llu next=%llu", __entry->vcpu_id,
+                  __entry->previous_tsc_offset, __entry->next_tsc_offset)
+);
+
 #ifdef CONFIG_X86_64
 
 #define host_clocks                                     \
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 260a91939555..a7e18551c968 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2096,6 +2096,8 @@ static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
                          vmcs12->tsc_offset : 0));
         } else {
+                trace_kvm_write_tsc_offset(vcpu->vcpu_id,
+                                           vmcs_read64(TSC_OFFSET), offset);
                 vmcs_write64(TSC_OFFSET, offset);
         }
 }
@@ -2103,11 +2105,14 @@ static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
 {
         u64 offset = vmcs_read64(TSC_OFFSET);
+
         vmcs_write64(TSC_OFFSET, offset + adjustment);
         if (is_guest_mode(vcpu)) {
                 /* Even when running L2, the adjustment needs to apply to L1 */
                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
-        }
+        } else
+                trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
+                                           offset + adjustment);
 }
 
 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
@@ -4176,10 +4181,10 @@ static void ept_set_mmio_spte_mask(void)
         /*
          * EPT Misconfigurations can be generated if the value of bits 2:0
          * of an EPT paging-structure entry is 110b (write/execute).
-         * Also, magic bits (0xffull << 49) is set to quickly identify mmio
+         * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
          * spte.
          */
-        kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
+        kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
 }
 
 /*
@@ -5366,10 +5371,14 @@ static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
 
         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
-        if (likely(ret == 1))
+        if (likely(ret == RET_MMIO_PF_EMULATE))
                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
                                               EMULATE_DONE;
-        if (unlikely(!ret))
+
+        if (unlikely(ret == RET_MMIO_PF_INVALID))
+                return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
+
+        if (unlikely(ret == RET_MMIO_PF_RETRY))
                 return 1;
 
         /* It is the real ept misconfig */
@@ -7942,7 +7951,7 @@ static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
 
         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
-        vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
+        vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
         /*
          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
          * actually changed, because it depends on the current state of
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 094b5d96ab14..d21bce505315 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -582,8 +582,6 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
         if (index != XCR_XFEATURE_ENABLED_MASK)
                 return 1;
         xcr0 = xcr;
-        if (kvm_x86_ops->get_cpl(vcpu) != 0)
-                return 1;
         if (!(xcr0 & XSTATE_FP))
                 return 1;
         if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
@@ -597,7 +595,8 @@ int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 
 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
 {
-        if (__kvm_set_xcr(vcpu, index, xcr)) {
+        if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
+            __kvm_set_xcr(vcpu, index, xcr)) {
                 kvm_inject_gp(vcpu, 0);
                 return 1;
         }
@@ -619,7 +618,7 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
         if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
                 return 1;
 
-        if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
+        if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
                 return 1;
 
         if (is_long_mode(vcpu)) {
@@ -1194,20 +1193,37 @@ void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
         elapsed = ns - kvm->arch.last_tsc_nsec;
 
         if (vcpu->arch.virtual_tsc_khz) {
+                int faulted = 0;
+
                 /* n.b - signed multiplication and division required */
                 usdiff = data - kvm->arch.last_tsc_write;
 #ifdef CONFIG_X86_64
                 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
 #else
                 /* do_div() only does unsigned */
-                asm("idivl %2; xor %%edx, %%edx"
-                : "=A"(usdiff)
-                : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
+                asm("1: idivl %[divisor]\n"
+                    "2: xor %%edx, %%edx\n"
+                    "   movl $0, %[faulted]\n"
+                    "3:\n"
+                    ".section .fixup,\"ax\"\n"
+                    "4: movl $1, %[faulted]\n"
+                    "   jmp  3b\n"
+                    ".previous\n"
+
+                _ASM_EXTABLE(1b, 4b)
+
+                : "=A"(usdiff), [faulted] "=r" (faulted)
+                : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
+
 #endif
                 do_div(elapsed, 1000);
                 usdiff -= elapsed;
                 if (usdiff < 0)
                         usdiff = -usdiff;
+
+                /* idivl overflow => difference is larger than USEC_PER_SEC */
+                if (faulted)
+                        usdiff = USEC_PER_SEC;
         } else
                 usdiff = USEC_PER_SEC; /* disable TSC match window below */
 
@@ -1588,6 +1604,30 @@ static int kvm_guest_time_update(struct kvm_vcpu *v)
         return 0;
 }
 
+/*
+ * kvmclock updates which are isolated to a given vcpu, such as
+ * vcpu->cpu migration, should not allow system_timestamp from
+ * the rest of the vcpus to remain static. Otherwise ntp frequency
+ * correction applies to one vcpu's system_timestamp but not
+ * the others.
+ *
+ * So in those cases, request a kvmclock update for all vcpus.
+ * The worst case for a remote vcpu to update its kvmclock
+ * is then bounded by maximum nohz sleep latency.
+ */
+
+static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
+{
+        int i;
+        struct kvm *kvm = v->kvm;
+        struct kvm_vcpu *vcpu;
+
+        kvm_for_each_vcpu(i, vcpu, kvm) {
+                set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
+                kvm_vcpu_kick(vcpu);
+        }
+}
+
 static bool msr_mtrr_valid(unsigned msr)
 {
         switch (msr) {
@@ -1985,7 +2025,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                 kvmclock_reset(vcpu);
 
                 vcpu->arch.time = data;
-                kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
+                kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
 
                 /* we verify if the enable bit is set... */
                 if (!(data & 1))
@@ -2702,7 +2742,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
                  * kvmclock on vcpu->cpu migration
                  */
                 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
-                        kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
+                        kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
                 if (vcpu->cpu != cpu)
                         kvm_migrate_timers(vcpu);
                 vcpu->cpu = cpu;
@@ -5239,7 +5279,13 @@ static void kvm_set_mmio_spte_mask(void)
          * Set the reserved bits and the present bit of an paging-structure
          * entry to generate page fault with PFER.RSV = 1.
          */
-        mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
+         /* Mask the reserved physical address bits. */
+        mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
+
+        /* Bit 62 is always reserved for 32bit host. */
+        mask |= 0x3ull << 62;
+
+        /* Set the present bit. */
         mask |= 1ull;
 
 #ifdef CONFIG_X86_64
@@ -5499,13 +5545,6 @@ static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
         char instruction[3];
         unsigned long rip = kvm_rip_read(vcpu);
 
-        /*
-         * Blow out the MMU to ensure that no other VCPU has an active mapping
-         * to ensure that the updated hypercall appears atomically across all
-         * VCPUs.
-         */
-        kvm_mmu_zap_all(vcpu->kvm);
-
         kvm_x86_ops->patch_hypercall(vcpu, instruction);
 
         return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
@@ -5703,6 +5742,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                         __kvm_migrate_timers(vcpu);
                 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
                         kvm_gen_update_masterclock(vcpu->kvm);
+                if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
+                        kvm_gen_kvmclock_update(vcpu);
                 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
                         r = kvm_guest_time_update(vcpu);
                         if (unlikely(r))
@@ -6813,6 +6854,7 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
                 return -EINVAL;
 
         INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
+        INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
         INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
 
         /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
@@ -7041,22 +7083,18 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
          * If memory slot is created, or moved, we need to clear all
          * mmio sptes.
          */
-        if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
-                kvm_mmu_zap_mmio_sptes(kvm);
-                kvm_reload_remote_mmus(kvm);
-        }
+        kvm_mmu_invalidate_mmio_sptes(kvm);
 }
 
 void kvm_arch_flush_shadow_all(struct kvm *kvm)
 {
-        kvm_mmu_zap_all(kvm);
-        kvm_reload_remote_mmus(kvm);
+        kvm_mmu_invalidate_zap_all_pages(kvm);
 }
 
 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
                                    struct kvm_memory_slot *slot)
 {
-        kvm_arch_flush_shadow_all(kvm);
+        kvm_mmu_invalidate_zap_all_pages(kvm);
 }
 
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
@@ -7264,3 +7302,4 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
diff --git a/arch/x86/lguest/Makefile b/arch/x86/lguest/Makefile
index 94e0e54056a9..8f38d577a2fa 100644
--- a/arch/x86/lguest/Makefile
+++ b/arch/x86/lguest/Makefile
@@ -1,2 +1,2 @@
-obj-y           := i386_head.o boot.o
+obj-y           := head_32.o boot.o
 CFLAGS_boot.o   := $(call cc-option, -fno-stack-protector)
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 7114c63f047d..d482bcaf61c1 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -1410,7 +1410,7 @@ __init void lguest_init(void)
         new_cpu_data.x86_capability[0] = cpuid_edx(1);
 
         /* Math is always hard! */
-        new_cpu_data.hard_math = 1;
+        set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
 
         /* We don't have features.  We have puppies!  Puppies! */
 #ifdef CONFIG_X86_MCE
diff --git a/arch/x86/lguest/i386_head.S b/arch/x86/lguest/head_32.S
index 6ddfe4fc23c3..6ddfe4fc23c3 100644
--- a/arch/x86/lguest/i386_head.S
+++ b/arch/x86/lguest/head_32.S
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 252b8f5489ba..4500142bc4aa 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -1,6 +1,7 @@
 #include <linux/highmem.h>
 #include <linux/module.h>
 #include <linux/swap.h> /* for totalram_pages */
+#include <linux/bootmem.h>
 
 void *kmap(struct page *page)
 {
@@ -121,6 +122,11 @@ void __init set_highmem_pages_init(void)
         struct zone *zone;
         int nid;
 
+        /*
+         * Explicitly reset zone->managed_pages because set_highmem_pages_init()
+         * is invoked before free_all_bootmem()
+         */
+        reset_all_zones_managed_pages();
         for_each_zone(zone) {
                 unsigned long zone_start_pfn, zone_end_pfn;
 
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index ae1aa71d0115..7e73e8c69096 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -16,169 +16,6 @@
 #include <asm/tlbflush.h>
 #include <asm/pgalloc.h>
 
-static unsigned long page_table_shareable(struct vm_area_struct *svma,
-                                struct vm_area_struct *vma,
-                                unsigned long addr, pgoff_t idx)
-{
-        unsigned long saddr = ((idx - svma->vm_pgoff) << PAGE_SHIFT) +
-                                svma->vm_start;
-        unsigned long sbase = saddr & PUD_MASK;
-        unsigned long s_end = sbase + PUD_SIZE;
-
-        /* Allow segments to share if only one is marked locked */
-        unsigned long vm_flags = vma->vm_flags & ~VM_LOCKED;
-        unsigned long svm_flags = svma->vm_flags & ~VM_LOCKED;
-
-        /*
-         * match the virtual addresses, permission and the alignment of the
-         * page table page.
-         */
-        if (pmd_index(addr) != pmd_index(saddr) ||
-            vm_flags != svm_flags ||
-            sbase < svma->vm_start || svma->vm_end < s_end)
-                return 0;
-
-        return saddr;
-}
-
-static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
-{
-        unsigned long base = addr & PUD_MASK;
-        unsigned long end = base + PUD_SIZE;
-
-        /*
-         * check on proper vm_flags and page table alignment
-         */
-        if (vma->vm_flags & VM_MAYSHARE &&
-            vma->vm_start <= base && end <= vma->vm_end)
-                return 1;
-        return 0;
-}
-
-/*
- * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
- * and returns the corresponding pte. While this is not necessary for the
- * !shared pmd case because we can allocate the pmd later as well, it makes the
- * code much cleaner. pmd allocation is essential for the shared case because
- * pud has to be populated inside the same i_mmap_mutex section - otherwise
- * racing tasks could either miss the sharing (see huge_pte_offset) or select a
- * bad pmd for sharing.
- */
-static pte_t *
-huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
-{
-        struct vm_area_struct *vma = find_vma(mm, addr);
-        struct address_space *mapping = vma->vm_file->f_mapping;
-        pgoff_t idx = ((addr - vma->vm_start) >> PAGE_SHIFT) +
-                        vma->vm_pgoff;
-        struct vm_area_struct *svma;
-        unsigned long saddr;
-        pte_t *spte = NULL;
-        pte_t *pte;
-
-        if (!vma_shareable(vma, addr))
-                return (pte_t *)pmd_alloc(mm, pud, addr);
-
-        mutex_lock(&mapping->i_mmap_mutex);
-        vma_interval_tree_foreach(svma, &mapping->i_mmap, idx, idx) {
-                if (svma == vma)
-                        continue;
-
-                saddr = page_table_shareable(svma, vma, addr, idx);
-                if (saddr) {
-                        spte = huge_pte_offset(svma->vm_mm, saddr);
-                        if (spte) {
-                                get_page(virt_to_page(spte));
-                                break;
-                        }
-                }
-        }
-
-        if (!spte)
-                goto out;
-
-        spin_lock(&mm->page_table_lock);
-        if (pud_none(*pud))
-                pud_populate(mm, pud, (pmd_t *)((unsigned long)spte & PAGE_MASK));
-        else
-                put_page(virt_to_page(spte));
-        spin_unlock(&mm->page_table_lock);
-out:
-        pte = (pte_t *)pmd_alloc(mm, pud, addr);
-        mutex_unlock(&mapping->i_mmap_mutex);
-        return pte;
-}
-
-/*
- * unmap huge page backed by shared pte.
- *
- * Hugetlb pte page is ref counted at the time of mapping.  If pte is shared
- * indicated by page_count > 1, unmap is achieved by clearing pud and
- * decrementing the ref count. If count == 1, the pte page is not shared.
- *
- * called with vma->vm_mm->page_table_lock held.
- *
- * returns: 1 successfully unmapped a shared pte page
- *          0 the underlying pte page is not shared, or it is the last user
- */
-int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
-{
-        pgd_t *pgd = pgd_offset(mm, *addr);
-        pud_t *pud = pud_offset(pgd, *addr);
-
-        BUG_ON(page_count(virt_to_page(ptep)) == 0);
-        if (page_count(virt_to_page(ptep)) == 1)
-                return 0;
-
-        pud_clear(pud);
-        put_page(virt_to_page(ptep));
-        *addr = ALIGN(*addr, HPAGE_SIZE * PTRS_PER_PTE) - HPAGE_SIZE;
-        return 1;
-}
-
-pte_t *huge_pte_alloc(struct mm_struct *mm,
-                        unsigned long addr, unsigned long sz)
-{
-        pgd_t *pgd;
-        pud_t *pud;
-        pte_t *pte = NULL;
-
-        pgd = pgd_offset(mm, addr);
-        pud = pud_alloc(mm, pgd, addr);
-        if (pud) {
-                if (sz == PUD_SIZE) {
-                        pte = (pte_t *)pud;
-                } else {
-                        BUG_ON(sz != PMD_SIZE);
-                        if (pud_none(*pud))
-                                pte = huge_pmd_share(mm, addr, pud);
-                        else
-                                pte = (pte_t *)pmd_alloc(mm, pud, addr);
-                }
-        }
-        BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
-
-        return pte;
-}
-
-pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
-{
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd = NULL;
-
-        pgd = pgd_offset(mm, addr);
-        if (pgd_present(*pgd)) {
-                pud = pud_offset(pgd, addr);
-                if (pud_present(*pud)) {
-                        if (pud_large(*pud))
-                                return (pte_t *)pud;
-                        pmd = pmd_offset(pud, addr);
-                }
-        }
-        return (pte_t *) pmd;
-}
-
 #if 0   /* This is just for testing */
 struct page *
 follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
@@ -240,30 +77,6 @@ int pud_huge(pud_t pud)
         return !!(pud_val(pud) & _PAGE_PSE);
 }
 
-struct page *
-follow_huge_pmd(struct mm_struct *mm, unsigned long address,
-                pmd_t *pmd, int write)
-{
-        struct page *page;
-
-        page = pte_page(*(pte_t *)pmd);
-        if (page)
-                page += ((address & ~PMD_MASK) >> PAGE_SHIFT);
-        return page;
-}
-
-struct page *
-follow_huge_pud(struct mm_struct *mm, unsigned long address,
-                pud_t *pud, int write)
-{
-        struct page *page;
-
-        page = pte_page(*(pte_t *)pud);
-        if (page)
-                page += ((address & ~PUD_MASK) >> PAGE_SHIFT);
-        return page;
-}
-
 #endif
 
 /* x86_64 also uses this file */
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index eaac1743def7..2ec29ac78ae6 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -277,6 +277,9 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
         end_pfn = limit_pfn;
         nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
 
+        if (!after_bootmem)
+                adjust_range_page_size_mask(mr, nr_range);
+
         /* try to merge same page size and continuous */
         for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
                 unsigned long old_start;
@@ -291,9 +294,6 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
                 nr_range--;
         }
 
-        if (!after_bootmem)
-                adjust_range_page_size_mask(mr, nr_range);
-
         for (i = 0; i < nr_range; i++)
                 printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n",
                                 mr[i].start, mr[i].end - 1,
@@ -494,7 +494,6 @@ int devmem_is_allowed(unsigned long pagenr)
 
 void free_init_pages(char *what, unsigned long begin, unsigned long end)
 {
-        unsigned long addr;
         unsigned long begin_aligned, end_aligned;
 
         /* Make sure boundaries are page aligned */
@@ -509,8 +508,6 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
         if (begin >= end)
                 return;
 
-        addr = begin;
-
         /*
          * If debugging page accesses then do not free this memory but
          * mark them not present - any buggy init-section access will
@@ -529,18 +526,13 @@ void free_init_pages(char *what, unsigned long begin, unsigned long end)
         set_memory_nx(begin, (end - begin) >> PAGE_SHIFT);
         set_memory_rw(begin, (end - begin) >> PAGE_SHIFT);
 
-        printk(KERN_INFO "Freeing %s: %luk freed\n", what, (end - begin) >> 10);
-
-        for (; addr < end; addr += PAGE_SIZE) {
-                memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
-                free_reserved_page(virt_to_page(addr));
-        }
+        free_reserved_area((void *)begin, (void *)end, POISON_FREE_INITMEM, what);
 #endif
 }
 
 void free_initmem(void)
 {
-        free_init_pages("unused kernel memory",
+        free_init_pages("unused kernel",
                         (unsigned long)(&__init_begin),
                         (unsigned long)(&__init_end));
 }
@@ -566,7 +558,7 @@ void __init free_initrd_mem(unsigned long start, unsigned long end)
          *   - relocate_initrd()
          * So here We can do PAGE_ALIGN() safely to get partial page to be freed
          */
-        free_init_pages("initrd memory", start, PAGE_ALIGN(end));
+        free_init_pages("initrd", start, PAGE_ALIGN(end));
 }
 #endif
 
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 3ac7e319918d..4287f1ffba7e 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -660,10 +660,8 @@ void __init initmem_init(void)
                 highstart_pfn = max_low_pfn;
         printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
                 pages_to_mb(highend_pfn - highstart_pfn));
-        num_physpages = highend_pfn;
         high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
 #else
-        num_physpages = max_low_pfn;
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
 #endif
 
@@ -671,7 +669,7 @@ void __init initmem_init(void)
         sparse_memory_present_with_active_regions(0);
 
 #ifdef CONFIG_FLATMEM
-        max_mapnr = num_physpages;
+        max_mapnr = IS_ENABLED(CONFIG_HIGHMEM) ? highend_pfn : max_low_pfn;
 #endif
         __vmalloc_start_set = true;
 
@@ -739,9 +737,6 @@ static void __init test_wp_bit(void)
 
 void __init mem_init(void)
 {
-        int codesize, reservedpages, datasize, initsize;
-        int tmp;
-
         pci_iommu_alloc();
 
 #ifdef CONFIG_FLATMEM
@@ -759,32 +754,11 @@ void __init mem_init(void)
         set_highmem_pages_init();
 
         /* this will put all low memory onto the freelists */
-        totalram_pages += free_all_bootmem();
-
-        reservedpages = 0;
-        for (tmp = 0; tmp < max_low_pfn; tmp++)
-                /*
-                 * Only count reserved RAM pages:
-                 */
-                if (page_is_ram(tmp) && PageReserved(pfn_to_page(tmp)))
-                        reservedpages++;
+        free_all_bootmem();
 
         after_bootmem = 1;
 
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
-        printk(KERN_INFO "Memory: %luk/%luk available (%dk kernel code, "
-                        "%dk reserved, %dk data, %dk init, %ldk highmem)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                num_physpages << (PAGE_SHIFT-10),
-                codesize >> 10,
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                initsize >> 10,
-                totalhigh_pages << (PAGE_SHIFT-10));
-
+        mem_init_print_info(NULL);
         printk(KERN_INFO "virtual kernel memory layout:\n"
                 "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
 #ifdef CONFIG_HIGHMEM
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index bb00c4672ad6..104d56a9245f 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -368,7 +368,7 @@ void __init init_extra_mapping_uc(unsigned long phys, unsigned long size)
  *
  *   from __START_KERNEL_map to __START_KERNEL_map + size (== _end-_text)
  *
- * phys_addr holds the negative offset to the kernel, which is added
+ * phys_base holds the negative offset to the kernel, which is added
  * to the compile time generated pmds. This results in invalid pmds up
  * to the point where we hit the physaddr 0 mapping.
  *
@@ -712,36 +712,22 @@ EXPORT_SYMBOL_GPL(arch_add_memory);
 
 static void __meminit free_pagetable(struct page *page, int order)
 {
-        struct zone *zone;
-        bool bootmem = false;
         unsigned long magic;
         unsigned int nr_pages = 1 << order;
 
         /* bootmem page has reserved flag */
         if (PageReserved(page)) {
                 __ClearPageReserved(page);
-                bootmem = true;
 
                 magic = (unsigned long)page->lru.next;
                 if (magic == SECTION_INFO || magic == MIX_SECTION_INFO) {
                         while (nr_pages--)
                                 put_page_bootmem(page++);
                 } else
-                        __free_pages_bootmem(page, order);
+                        while (nr_pages--)
+                                free_reserved_page(page++);
         } else
                 free_pages((unsigned long)page_address(page), order);
-
-        /*
-         * SECTION_INFO pages and MIX_SECTION_INFO pages
-         * are all allocated by bootmem.
-         */
-        if (bootmem) {
-                zone = page_zone(page);
-                zone_span_writelock(zone);
-                zone->present_pages += nr_pages;
-                zone_span_writeunlock(zone);
-                totalram_pages += nr_pages;
-        }
 }
 
 static void __meminit free_pte_table(pte_t *pte_start, pmd_t *pmd)
@@ -1058,9 +1044,6 @@ static void __init register_page_bootmem_info(void)
 
 void __init mem_init(void)
 {
-        long codesize, reservedpages, datasize, initsize;
-        unsigned long absent_pages;
-
         pci_iommu_alloc();
 
         /* clear_bss() already clear the empty_zero_page */
@@ -1068,29 +1051,14 @@ void __init mem_init(void)
         register_page_bootmem_info();
 
         /* this will put all memory onto the freelists */
-        totalram_pages = free_all_bootmem();
-
-        absent_pages = absent_pages_in_range(0, max_pfn);
-        reservedpages = max_pfn - totalram_pages - absent_pages;
+        free_all_bootmem();
         after_bootmem = 1;
 
-        codesize =  (unsigned long) &_etext - (unsigned long) &_text;
-        datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
-        initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
-
         /* Register memory areas for /proc/kcore */
         kclist_add(&kcore_vsyscall, (void *)VSYSCALL_START,
                          VSYSCALL_END - VSYSCALL_START, KCORE_OTHER);
 
-        printk(KERN_INFO "Memory: %luk/%luk available (%ldk kernel code, "
-                         "%ldk absent, %ldk reserved, %ldk data, %ldk init)\n",
-                nr_free_pages() << (PAGE_SHIFT-10),
-                max_pfn << (PAGE_SHIFT-10),
-                codesize >> 10,
-                absent_pages << (PAGE_SHIFT-10),
-                reservedpages << (PAGE_SHIFT-10),
-                datasize >> 10,
-                initsize >> 10);
+        mem_init_print_info(NULL);
 }
 
 #ifdef CONFIG_DEBUG_RODATA
@@ -1166,11 +1134,10 @@ void mark_rodata_ro(void)
         set_memory_ro(start, (end-start) >> PAGE_SHIFT);
 #endif
 
-        free_init_pages("unused kernel memory",
+        free_init_pages("unused kernel",
                         (unsigned long) __va(__pa_symbol(text_end)),
                         (unsigned long) __va(__pa_symbol(rodata_start)));
-
-        free_init_pages("unused kernel memory",
+        free_init_pages("unused kernel",
                         (unsigned long) __va(__pa_symbol(rodata_end)),
                         (unsigned long) __va(__pa_symbol(_sdata)));
 }
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 9a1e6583910c..0215e2c563ef 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -501,15 +501,15 @@ __early_ioremap(resource_size_t phys_addr, unsigned long size, pgprot_t prot)
         }
 
         if (slot < 0) {
-                printk(KERN_INFO "early_iomap(%08llx, %08lx) not found slot\n",
-                         (u64)phys_addr, size);
+                printk(KERN_INFO "%s(%08llx, %08lx) not found slot\n",
+                       __func__, (u64)phys_addr, size);
                 WARN_ON(1);
                 return NULL;
         }
 
         if (early_ioremap_debug) {
-                printk(KERN_INFO "early_ioremap(%08llx, %08lx) [%d] => ",
-                       (u64)phys_addr, size, slot);
+                printk(KERN_INFO "%s(%08llx, %08lx) [%d] => ",
+                       __func__, (u64)phys_addr, size, slot);
                 dump_stack();
         }
 
diff --git a/arch/x86/mm/numa_32.c b/arch/x86/mm/numa_32.c
index 73a6d7395bd3..0342d27ca798 100644
--- a/arch/x86/mm/numa_32.c
+++ b/arch/x86/mm/numa_32.c
@@ -83,10 +83,8 @@ void __init initmem_init(void)
                 highstart_pfn = max_low_pfn;
         printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
                pages_to_mb(highend_pfn - highstart_pfn));
-        num_physpages = highend_pfn;
         high_memory = (void *) __va(highstart_pfn * PAGE_SIZE - 1) + 1;
 #else
-        num_physpages = max_low_pfn;
         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE - 1) + 1;
 #endif
         printk(KERN_NOTICE "%ldMB LOWMEM available.\n",
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 3e724256dbee..d641897a1f4e 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -324,14 +324,11 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         res->start = start;
         res->end = end;
         info->res_offset[info->res_num] = addr.translation_offset;
+        info->res_num++;
 
-        if (!pci_use_crs) {
+        if (!pci_use_crs)
                 dev_printk(KERN_DEBUG, &info->bridge->dev,
                            "host bridge window %pR (ignored)\n", res);
-                return AE_OK;
-        }
-
-        info->res_num++;
 
         return AE_OK;
 }
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 82089d8b1954..b410b71bdcf7 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -42,7 +42,6 @@
 #include <linux/io.h>
 #include <linux/reboot.h>
 #include <linux/bcd.h>
-#include <linux/ucs2_string.h>
 
 #include <asm/setup.h>
 #include <asm/efi.h>
@@ -54,12 +53,12 @@
 
 #define EFI_DEBUG       1
 
-/*
- * There's some additional metadata associated with each
- * variable. Intel's reference implementation is 60 bytes - bump that
- * to account for potential alignment constraints
- */
-#define VAR_METADATA_SIZE 64
+#define EFI_MIN_RESERVE 5120
+
+#define EFI_DUMMY_GUID \
+        EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9)
+
+static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 };
 
 struct efi __read_mostly efi = {
         .mps        = EFI_INVALID_TABLE_ADDR,
@@ -79,13 +78,6 @@ struct efi_memory_map memmap;
 static struct efi efi_phys __initdata;
 static efi_system_table_t efi_systab __initdata;
 
-static u64 efi_var_store_size;
-static u64 efi_var_remaining_size;
-static u64 efi_var_max_var_size;
-static u64 boot_used_size;
-static u64 boot_var_size;
-static u64 active_size;
-
 unsigned long x86_efi_facility;
 
 /*
@@ -188,53 +180,8 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size,
                                                efi_char16_t *name,
                                                efi_guid_t *vendor)
 {
-        efi_status_t status;
-        static bool finished = false;
-        static u64 var_size;
-
-        status = efi_call_virt3(get_next_variable,
-                                name_size, name, vendor);
-
-        if (status == EFI_NOT_FOUND) {
-                finished = true;
-                if (var_size < boot_used_size) {
-                        boot_var_size = boot_used_size - var_size;
-                        active_size += boot_var_size;
-                } else {
-                        printk(KERN_WARNING FW_BUG  "efi: Inconsistent initial sizes\n");
-                }
-        }
-
-        if (boot_used_size && !finished) {
-                unsigned long size = 0;
-                u32 attr;
-                efi_status_t s;
-                void *tmp;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, NULL);
-
-                if (s != EFI_BUFFER_TOO_SMALL || !size)
-                        return status;
-
-                tmp = kmalloc(size, GFP_ATOMIC);
-
-                if (!tmp)
-                        return status;
-
-                s = virt_efi_get_variable(name, vendor, &attr, &size, tmp);
-
-                if (s == EFI_SUCCESS && (attr & EFI_VARIABLE_NON_VOLATILE)) {
-                        var_size += size;
-                        var_size += ucs2_strsize(name, 1024);
-                        active_size += size;
-                        active_size += VAR_METADATA_SIZE;
-                        active_size += ucs2_strsize(name, 1024);
-                }
-
-                kfree(tmp);
-        }
-
-        return status;
+        return efi_call_virt3(get_next_variable,
+                              name_size, name, vendor);
 }
 
 static efi_status_t virt_efi_set_variable(efi_char16_t *name,
@@ -243,34 +190,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name,
                                           unsigned long data_size,
                                           void *data)
 {
-        efi_status_t status;
-        u32 orig_attr = 0;
-        unsigned long orig_size = 0;
-
-        status = virt_efi_get_variable(name, vendor, &orig_attr, &orig_size,
-                                       NULL);
-
-        if (status != EFI_BUFFER_TOO_SMALL)
-                orig_size = 0;
-
-        status = efi_call_virt5(set_variable,
-                                name, vendor, attr,
-                                data_size, data);
-
-        if (status == EFI_SUCCESS) {
-                if (orig_size) {
-                        active_size -= orig_size;
-                        active_size -= ucs2_strsize(name, 1024);
-                        active_size -= VAR_METADATA_SIZE;
-                }
-                if (data_size) {
-                        active_size += data_size;
-                        active_size += ucs2_strsize(name, 1024);
-                        active_size += VAR_METADATA_SIZE;
-                }
-        }
-
-        return status;
+        return efi_call_virt5(set_variable,
+                              name, vendor, attr,
+                              data_size, data);
 }
 
 static efi_status_t virt_efi_query_variable_info(u32 attr,
@@ -786,9 +708,6 @@ void __init efi_init(void)
         char vendor[100] = "unknown";
         int i = 0;
         void *tmp;
-        struct setup_data *data;
-        struct efi_var_bootdata *efi_var_data;
-        u64 pa_data;
 
 #ifdef CONFIG_X86_32
         if (boot_params.efi_info.efi_systab_hi ||
@@ -806,22 +725,6 @@ void __init efi_init(void)
         if (efi_systab_init(efi_phys.systab))
                 return;
 
-        pa_data = boot_params.hdr.setup_data;
-        while (pa_data) {
-                data = early_ioremap(pa_data, sizeof(*efi_var_data));
-                if (data->type == SETUP_EFI_VARS) {
-                        efi_var_data = (struct efi_var_bootdata *)data;
-
-                        efi_var_store_size = efi_var_data->store_size;
-                        efi_var_remaining_size = efi_var_data->remaining_size;
-                        efi_var_max_var_size = efi_var_data->max_var_size;
-                }
-                pa_data = data->next;
-                early_iounmap(data, sizeof(*efi_var_data));
-        }
-
-        boot_used_size = efi_var_store_size - efi_var_remaining_size;
-
         set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility);
 
         /*
@@ -1026,6 +929,13 @@ void __init efi_enter_virtual_mode(void)
                         va = efi_ioremap(md->phys_addr, size,
                                          md->type, md->attribute);
 
+                if (!(md->attribute & EFI_MEMORY_RUNTIME)) {
+                        if (!va)
+                                pr_err("ioremap of 0x%llX failed!\n",
+                                       (unsigned long long)md->phys_addr);
+                        continue;
+                }
+
                 md->virt_addr = (u64) (unsigned long) va;
 
                 if (!va) {
@@ -1085,6 +995,13 @@ void __init efi_enter_virtual_mode(void)
                 runtime_code_page_mkexec();
 
         kfree(new_memmap);
+
+        /* clean DUMMY object */
+        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                         EFI_VARIABLE_NON_VOLATILE |
+                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                         EFI_VARIABLE_RUNTIME_ACCESS,
+                         0, NULL);
 }
 
 /*
@@ -1136,33 +1053,70 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size)
         efi_status_t status;
         u64 storage_size, remaining_size, max_size;
 
+        if (!(attributes & EFI_VARIABLE_NON_VOLATILE))
+                return 0;
+
         status = efi.query_variable_info(attributes, &storage_size,
                                          &remaining_size, &max_size);
         if (status != EFI_SUCCESS)
                 return status;
 
-        if (!max_size && remaining_size > size)
-                printk_once(KERN_ERR FW_BUG "Broken EFI implementation"
-                            " is returning MaxVariableSize=0\n");
         /*
          * Some firmware implementations refuse to boot if there's insufficient
          * space in the variable store. We account for that by refusing the
          * write if permitting it would reduce the available space to under
-         * 50%. However, some firmware won't reclaim variable space until
-         * after the used (not merely the actively used) space drops below
-         * a threshold. We can approximate that case with the value calculated
-         * above. If both the firmware and our calculations indicate that the
-         * available space would drop below 50%, refuse the write.
+         * 5KB. This figure was provided by Samsung, so should be safe.
          */
+        if ((remaining_size - size < EFI_MIN_RESERVE) &&
+                !efi_no_storage_paranoia) {
+
+                /*
+                 * Triggering garbage collection may require that the firmware
+                 * generate a real EFI_OUT_OF_RESOURCES error. We can force
+                 * that by attempting to use more space than is available.
+                 */
+                unsigned long dummy_size = remaining_size + 1024;
+                void *dummy = kzalloc(dummy_size, GFP_ATOMIC);
+
+                if (!dummy)
+                        return EFI_OUT_OF_RESOURCES;
+
+                status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                          EFI_VARIABLE_NON_VOLATILE |
+                                          EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                          EFI_VARIABLE_RUNTIME_ACCESS,
+                                          dummy_size, dummy);
+
+                if (status == EFI_SUCCESS) {
+                        /*
+                         * This should have failed, so if it didn't make sure
+                         * that we delete it...
+                         */
+                        efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
+                                         EFI_VARIABLE_NON_VOLATILE |
+                                         EFI_VARIABLE_BOOTSERVICE_ACCESS |
+                                         EFI_VARIABLE_RUNTIME_ACCESS,
+                                         0, dummy);
+                }
+
+                kfree(dummy);
 
-        if (!storage_size || size > remaining_size ||
-            (max_size && size > max_size))
-                return EFI_OUT_OF_RESOURCES;
+                /*
+                 * The runtime code may now have triggered a garbage collection
+                 * run, so check the variable info again
+                 */
+                status = efi.query_variable_info(attributes, &storage_size,
+                                                 &remaining_size, &max_size);
 
-        if (!efi_no_storage_paranoia &&
-            ((active_size + size + VAR_METADATA_SIZE > storage_size / 2) &&
-             (remaining_size - size < storage_size / 2)))
-                return EFI_OUT_OF_RESOURCES;
+                if (status != EFI_SUCCESS)
+                        return status;
+
+                /*
+                 * There still isn't enough room, so return an error
+                 */
+                if (remaining_size - size < EFI_MIN_RESERVE)
+                        return EFI_OUT_OF_RESOURCES;
+        }
 
         return EFI_SUCCESS;
 }
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 590be1090892..f7bab68a4b83 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -42,9 +42,6 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "^(xen_irq_disable_direct_reloc$|"
         "xen_save_fl_direct_reloc$|"
         "VDSO|"
-#if ELF_BITS == 64
-        "__vvar_page|"
-#endif
         "__crc_)",
 
 /*
@@ -72,6 +69,7 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
         "__per_cpu_load|"
         "init_per_cpu__.*|"
         "__end_rodata_hpage_align|"
+        "__vvar_page|"
 #endif
         "_end)$"
 };
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index 0faad646f5fd..d6bfb876cfb0 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -372,7 +372,7 @@ subsys_initcall(sysenter_setup);
 /* Register vsyscall32 into the ABI table */
 #include <linux/sysctl.h>
 
-static ctl_table abi_table2[] = {
+static struct ctl_table abi_table2[] = {
         {
                 .procname       = "vsyscall32",
                 .data           = &sysctl_vsyscall32,
@@ -383,7 +383,7 @@ static ctl_table abi_table2[] = {
         {}
 };
 
-static ctl_table abi_root_table2[] = {
+static struct ctl_table abi_root_table2[] = {
         {
                 .procname = "abi",
                 .mode = 0555,
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index a492be2635ac..2fa02bc50034 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1557,7 +1557,7 @@ asmlinkage void __init xen_start_kernel(void)
 #ifdef CONFIG_X86_32
         /* set up basic CPUID stuff */
         cpu_detect(&new_cpu_data);
-        new_cpu_data.hard_math = 1;
+        set_cpu_cap(&new_cpu_data, X86_FEATURE_FPU);
         new_cpu_data.wp_works_ok = 1;
         new_cpu_data.x86_capability[0] = cpuid_edx(1);
 #endif
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index fb44426fe931..c1367b29c3b1 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -17,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/smp.h>
 #include <linux/irq_work.h>
+#include <linux/tick.h>
 
 #include <asm/paravirt.h>
 #include <asm/desc.h>
@@ -39,11 +40,15 @@
 
 cpumask_var_t xen_cpu_initialized_map;
 
-static DEFINE_PER_CPU(int, xen_resched_irq);
-static DEFINE_PER_CPU(int, xen_callfunc_irq);
-static DEFINE_PER_CPU(int, xen_callfuncsingle_irq);
-static DEFINE_PER_CPU(int, xen_irq_work);
-static DEFINE_PER_CPU(int, xen_debug_irq) = -1;
+struct xen_common_irq {
+        int irq;
+        char *name;
+};
+static DEFINE_PER_CPU(struct xen_common_irq, xen_resched_irq) = { .irq = -1 };
+static DEFINE_PER_CPU(struct xen_common_irq, xen_callfunc_irq) = { .irq = -1 };
+static DEFINE_PER_CPU(struct xen_common_irq, xen_callfuncsingle_irq) = { .irq = -1 };
+static DEFINE_PER_CPU(struct xen_common_irq, xen_irq_work) = { .irq = -1 };
+static DEFINE_PER_CPU(struct xen_common_irq, xen_debug_irq) = { .irq = -1 };
 
 static irqreturn_t xen_call_function_interrupt(int irq, void *dev_id);
 static irqreturn_t xen_call_function_single_interrupt(int irq, void *dev_id);
@@ -98,10 +103,47 @@ static void __cpuinit cpu_bringup_and_idle(void)
         cpu_startup_entry(CPUHP_ONLINE);
 }
 
+static void xen_smp_intr_free(unsigned int cpu)
+{
+        if (per_cpu(xen_resched_irq, cpu).irq >= 0) {
+                unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu).irq, NULL);
+                per_cpu(xen_resched_irq, cpu).irq = -1;
+                kfree(per_cpu(xen_resched_irq, cpu).name);
+                per_cpu(xen_resched_irq, cpu).name = NULL;
+        }
+        if (per_cpu(xen_callfunc_irq, cpu).irq >= 0) {
+                unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu).irq, NULL);
+                per_cpu(xen_callfunc_irq, cpu).irq = -1;
+                kfree(per_cpu(xen_callfunc_irq, cpu).name);
+                per_cpu(xen_callfunc_irq, cpu).name = NULL;
+        }
+        if (per_cpu(xen_debug_irq, cpu).irq >= 0) {
+                unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu).irq, NULL);
+                per_cpu(xen_debug_irq, cpu).irq = -1;
+                kfree(per_cpu(xen_debug_irq, cpu).name);
+                per_cpu(xen_debug_irq, cpu).name = NULL;
+        }
+        if (per_cpu(xen_callfuncsingle_irq, cpu).irq >= 0) {
+                unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu).irq,
+                                       NULL);
+                per_cpu(xen_callfuncsingle_irq, cpu).irq = -1;
+                kfree(per_cpu(xen_callfuncsingle_irq, cpu).name);
+                per_cpu(xen_callfuncsingle_irq, cpu).name = NULL;
+        }
+        if (xen_hvm_domain())
+                return;
+
+        if (per_cpu(xen_irq_work, cpu).irq >= 0) {
+                unbind_from_irqhandler(per_cpu(xen_irq_work, cpu).irq, NULL);
+                per_cpu(xen_irq_work, cpu).irq = -1;
+                kfree(per_cpu(xen_irq_work, cpu).name);
+                per_cpu(xen_irq_work, cpu).name = NULL;
+        }
+};
 static int xen_smp_intr_init(unsigned int cpu)
 {
         int rc;
-        const char *resched_name, *callfunc_name, *debug_name;
+        char *resched_name, *callfunc_name, *debug_name;
 
         resched_name = kasprintf(GFP_KERNEL, "resched%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_RESCHEDULE_VECTOR,
@@ -112,7 +154,8 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(xen_resched_irq, cpu) = rc;
+        per_cpu(xen_resched_irq, cpu).irq = rc;
+        per_cpu(xen_resched_irq, cpu).name = resched_name;
 
         callfunc_name = kasprintf(GFP_KERNEL, "callfunc%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_VECTOR,
@@ -123,7 +166,8 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(xen_callfunc_irq, cpu) = rc;
+        per_cpu(xen_callfunc_irq, cpu).irq = rc;
+        per_cpu(xen_callfunc_irq, cpu).name = callfunc_name;
 
         debug_name = kasprintf(GFP_KERNEL, "debug%d", cpu);
         rc = bind_virq_to_irqhandler(VIRQ_DEBUG, cpu, xen_debug_interrupt,
@@ -131,7 +175,8 @@ static int xen_smp_intr_init(unsigned int cpu)
                                      debug_name, NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(xen_debug_irq, cpu) = rc;
+        per_cpu(xen_debug_irq, cpu).irq = rc;
+        per_cpu(xen_debug_irq, cpu).name = debug_name;
 
         callfunc_name = kasprintf(GFP_KERNEL, "callfuncsingle%d", cpu);
         rc = bind_ipi_to_irqhandler(XEN_CALL_FUNCTION_SINGLE_VECTOR,
@@ -142,7 +187,8 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(xen_callfuncsingle_irq, cpu) = rc;
+        per_cpu(xen_callfuncsingle_irq, cpu).irq = rc;
+        per_cpu(xen_callfuncsingle_irq, cpu).name = callfunc_name;
 
         /*
          * The IRQ worker on PVHVM goes through the native path and uses the
@@ -160,26 +206,13 @@ static int xen_smp_intr_init(unsigned int cpu)
                                     NULL);
         if (rc < 0)
                 goto fail;
-        per_cpu(xen_irq_work, cpu) = rc;
+        per_cpu(xen_irq_work, cpu).irq = rc;
+        per_cpu(xen_irq_work, cpu).name = callfunc_name;
 
         return 0;
 
  fail:
-        if (per_cpu(xen_resched_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu), NULL);
-        if (per_cpu(xen_callfunc_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
-        if (per_cpu(xen_debug_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
-        if (per_cpu(xen_callfuncsingle_irq, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu),
-                                       NULL);
-        if (xen_hvm_domain())
-                return rc;
-
-        if (per_cpu(xen_irq_work, cpu) >= 0)
-                unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
-
+        xen_smp_intr_free(cpu);
         return rc;
 }
 
@@ -432,12 +465,7 @@ static void xen_cpu_die(unsigned int cpu)
                 current->state = TASK_UNINTERRUPTIBLE;
                 schedule_timeout(HZ/10);
         }
-        unbind_from_irqhandler(per_cpu(xen_resched_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_callfunc_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
-        unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu), NULL);
-        if (!xen_hvm_domain())
-                unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
+        xen_smp_intr_free(cpu);
         xen_uninit_lock_cpu(cpu);
         xen_teardown_timer(cpu);
 }
@@ -447,6 +475,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */
         play_dead_common();
         HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
         cpu_bringup();
+        /*
+         * commit 4b0c0f294 (tick: Cleanup NOHZ per cpu data on cpu down)
+         * clears certain data that the cpu_idle loop (which called us
+         * and that we return from) expects. The only way to get that
+         * data back is to call:
+         */
+        tick_nohz_idle_enter();
 }
 
 #else /* !CONFIG_HOTPLUG_CPU */
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 3002ec1bb71a..a40f8508e760 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -7,6 +7,7 @@
 #include <linux/debugfs.h>
 #include <linux/log2.h>
 #include <linux/gfp.h>
+#include <linux/slab.h>
 
 #include <asm/paravirt.h>
 
@@ -165,6 +166,7 @@ static int xen_spin_trylock(struct arch_spinlock *lock)
         return old == 0;
 }
 
+static DEFINE_PER_CPU(char *, irq_name);
 static DEFINE_PER_CPU(int, lock_kicker_irq) = -1;
 static DEFINE_PER_CPU(struct xen_spinlock *, lock_spinners);
 
@@ -362,7 +364,7 @@ static irqreturn_t dummy_handler(int irq, void *dev_id)
 void __cpuinit xen_init_lock_cpu(int cpu)
 {
         int irq;
-        const char *name;
+        char *name;
 
         WARN(per_cpu(lock_kicker_irq, cpu) >= 0, "spinlock on CPU%d exists on IRQ%d!\n",
              cpu, per_cpu(lock_kicker_irq, cpu));
@@ -385,6 +387,7 @@ void __cpuinit xen_init_lock_cpu(int cpu)
         if (irq >= 0) {
                 disable_irq(irq); /* make sure it's never delivered */
                 per_cpu(lock_kicker_irq, cpu) = irq;
+                per_cpu(irq_name, cpu) = name;
         }
 
         printk("cpu %d spinlock event irq %d\n", cpu, irq);
@@ -401,6 +404,8 @@ void xen_uninit_lock_cpu(int cpu)
 
         unbind_from_irqhandler(per_cpu(lock_kicker_irq, cpu), NULL);
         per_cpu(lock_kicker_irq, cpu) = -1;
+        kfree(per_cpu(irq_name, cpu));
+        per_cpu(irq_name, cpu) = NULL;
 }
 
 void __init xen_init_spinlocks(void)
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 3d88bfdf9e1c..a690868be837 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -14,6 +14,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/math64.h>
 #include <linux/gfp.h>
+#include <linux/slab.h>
 
 #include <asm/pvclock.h>
 #include <asm/xen/hypervisor.h>
@@ -36,9 +37,8 @@ static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate);
 /* snapshots of runstate info */
 static DEFINE_PER_CPU(struct vcpu_runstate_info, xen_runstate_snapshot);
 
-/* unused ns of stolen and blocked time */
+/* unused ns of stolen time */
 static DEFINE_PER_CPU(u64, xen_residual_stolen);
-static DEFINE_PER_CPU(u64, xen_residual_blocked);
 
 /* return an consistent snapshot of 64-bit time/counter value */
 static u64 get64(const u64 *p)
@@ -115,7 +115,7 @@ static void do_stolen_accounting(void)
 {
         struct vcpu_runstate_info state;
         struct vcpu_runstate_info *snap;
-        s64 blocked, runnable, offline, stolen;
+        s64 runnable, offline, stolen;
         cputime_t ticks;
 
         get_runstate_snapshot(&state);
@@ -125,7 +125,6 @@ static void do_stolen_accounting(void)
         snap = &__get_cpu_var(xen_runstate_snapshot);
 
         /* work out how much time the VCPU has not been runn*ing*  */
-        blocked = state.time[RUNSTATE_blocked] - snap->time[RUNSTATE_blocked];
         runnable = state.time[RUNSTATE_runnable] - snap->time[RUNSTATE_runnable];
         offline = state.time[RUNSTATE_offline] - snap->time[RUNSTATE_offline];
 
@@ -141,17 +140,6 @@ static void do_stolen_accounting(void)
         ticks = iter_div_u64_rem(stolen, NS_PER_TICK, &stolen);
         __this_cpu_write(xen_residual_stolen, stolen);
         account_steal_ticks(ticks);
-
-        /* Add the appropriate number of ticks of blocked time,
-           including any left-overs from last time. */
-        blocked += __this_cpu_read(xen_residual_blocked);
-
-        if (blocked < 0)
-                blocked = 0;
-
-        ticks = iter_div_u64_rem(blocked, NS_PER_TICK, &blocked);
-        __this_cpu_write(xen_residual_blocked, blocked);
-        account_idle_ticks(ticks);
 }
 
 /* Get the TSC speed from Xen */
@@ -377,11 +365,16 @@ static const struct clock_event_device xen_vcpuop_clockevent = {
 
 static const struct clock_event_device *xen_clockevent =
         &xen_timerop_clockevent;
-static DEFINE_PER_CPU(struct clock_event_device, xen_clock_events) = { .irq = -1 };
+
+struct xen_clock_event_device {
+        struct clock_event_device evt;
+        char *name;
+};
+static DEFINE_PER_CPU(struct xen_clock_event_device, xen_clock_events) = { .evt.irq = -1 };
 
 static irqreturn_t xen_timer_interrupt(int irq, void *dev_id)
 {
-        struct clock_event_device *evt = &__get_cpu_var(xen_clock_events);
+        struct clock_event_device *evt = &__get_cpu_var(xen_clock_events).evt;
         irqreturn_t ret;
 
         ret = IRQ_NONE;
@@ -395,14 +388,30 @@ static irqreturn_t xen_timer_interrupt(int irq, void *dev_id)
         return ret;
 }
 
+void xen_teardown_timer(int cpu)
+{
+        struct clock_event_device *evt;
+        BUG_ON(cpu == 0);
+        evt = &per_cpu(xen_clock_events, cpu).evt;
+
+        if (evt->irq >= 0) {
+                unbind_from_irqhandler(evt->irq, NULL);
+                evt->irq = -1;
+                kfree(per_cpu(xen_clock_events, cpu).name);
+                per_cpu(xen_clock_events, cpu).name = NULL;
+        }
+}
+
 void xen_setup_timer(int cpu)
 {
-        const char *name;
+        char *name;
         struct clock_event_device *evt;
         int irq;
 
-        evt = &per_cpu(xen_clock_events, cpu);
+        evt = &per_cpu(xen_clock_events, cpu).evt;
         WARN(evt->irq >= 0, "IRQ%d for CPU%d is already allocated\n", evt->irq, cpu);
+        if (evt->irq >= 0)
+                xen_teardown_timer(cpu);
 
         printk(KERN_INFO "installing Xen timer for CPU %d\n", cpu);
 
@@ -420,22 +429,15 @@ void xen_setup_timer(int cpu)
 
         evt->cpumask = cpumask_of(cpu);
         evt->irq = irq;
+        per_cpu(xen_clock_events, cpu).name = name;
 }
 
-void xen_teardown_timer(int cpu)
-{
-        struct clock_event_device *evt;
-        BUG_ON(cpu == 0);
-        evt = &per_cpu(xen_clock_events, cpu);
-        unbind_from_irqhandler(evt->irq, NULL);
-        evt->irq = -1;
-}
 
 void xen_setup_cpu_clockevents(void)
 {
         BUG_ON(preemptible());
 
-        clockevents_register_device(&__get_cpu_var(xen_clock_events));
+        clockevents_register_device(&__get_cpu_var(xen_clock_events).evt);
 }
 
 void xen_timer_resume(void)
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index d7546c94da52..8f017eb309bd 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -393,14 +393,6 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 extern  void update_mmu_cache(struct vm_area_struct * vma,
                               unsigned long address, pte_t *ptep);
 
-/*
- * remap a physical page `pfn' of size `size' with page protection `prot'
- * into virtual address `from'
- */
-
-#define io_remap_pfn_range(vma,from,pfn,size,prot) \
-        remap_pfn_range(vma, from, pfn, size, prot)
-
 typedef pte_t *pte_addr_t;
 
 #endif /* !defined (__ASSEMBLY__) */
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index bba125b4bb06..479d7537a32a 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -173,39 +173,16 @@ void __init zones_init(void)
 
 void __init mem_init(void)
 {
-        unsigned long codesize, reservedpages, datasize, initsize;
-        unsigned long highmemsize, tmp, ram;
-
-        max_mapnr = num_physpages = max_low_pfn - ARCH_PFN_OFFSET;
+        max_mapnr = max_low_pfn - ARCH_PFN_OFFSET;
         high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
-        highmemsize = 0;
 
 #ifdef CONFIG_HIGHMEM
 #error HIGHGMEM not implemented in init.c
 #endif
 
-        totalram_pages += free_all_bootmem();
-
-        reservedpages = ram = 0;
-        for (tmp = 0; tmp < max_mapnr; tmp++) {
-                ram++;
-                if (PageReserved(mem_map+tmp))
-                        reservedpages++;
-        }
+        free_all_bootmem();
 
-        codesize =  (unsigned long) _etext - (unsigned long) _stext;
-        datasize =  (unsigned long) _edata - (unsigned long) _sdata;
-        initsize =  (unsigned long) __init_end - (unsigned long) __init_begin;
-
-        printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, "
-               "%ldk data, %ldk init %ldk highmem)\n",
-               nr_free_pages() << (PAGE_SHIFT-10),
-               ram << (PAGE_SHIFT-10),
-               codesize >> 10,
-               reservedpages << (PAGE_SHIFT-10),
-               datasize >> 10,
-               initsize >> 10,
-               highmemsize >> 10);
+        mem_init_print_info(NULL);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
@@ -214,11 +191,11 @@ extern int initrd_is_mapped;
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
         if (initrd_is_mapped)
-                free_reserved_area(start, end, 0, "initrd");
+                free_reserved_area((void *)start, (void *)end, -1, "initrd");
 }
 #endif
 
 void free_initmem(void)
 {
-        free_initmem_default(0);
+        free_initmem_default(-1);
 }