diff options
Diffstat (limited to 'arch')
611 files changed, 15452 insertions, 6280 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 57eb6ef7f48d..5dbb9562742c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -260,6 +260,7 @@ config ARCH_INTEGRATOR | |||
260 | select ICST | 260 | select ICST |
261 | select GENERIC_CLOCKEVENTS | 261 | select GENERIC_CLOCKEVENTS |
262 | select PLAT_VERSATILE | 262 | select PLAT_VERSATILE |
263 | select PLAT_VERSATILE_CLOCK | ||
263 | select PLAT_VERSATILE_FPGA_IRQ | 264 | select PLAT_VERSATILE_FPGA_IRQ |
264 | select NEED_MACH_IO_H | 265 | select NEED_MACH_IO_H |
265 | select NEED_MACH_MEMORY_H | 266 | select NEED_MACH_MEMORY_H |
@@ -277,6 +278,7 @@ config ARCH_REALVIEW | |||
277 | select GENERIC_CLOCKEVENTS | 278 | select GENERIC_CLOCKEVENTS |
278 | select ARCH_WANT_OPTIONAL_GPIOLIB | 279 | select ARCH_WANT_OPTIONAL_GPIOLIB |
279 | select PLAT_VERSATILE | 280 | select PLAT_VERSATILE |
281 | select PLAT_VERSATILE_CLOCK | ||
280 | select PLAT_VERSATILE_CLCD | 282 | select PLAT_VERSATILE_CLCD |
281 | select ARM_TIMER_SP804 | 283 | select ARM_TIMER_SP804 |
282 | select GPIO_PL061 if GPIOLIB | 284 | select GPIO_PL061 if GPIOLIB |
@@ -295,6 +297,7 @@ config ARCH_VERSATILE | |||
295 | select ARCH_WANT_OPTIONAL_GPIOLIB | 297 | select ARCH_WANT_OPTIONAL_GPIOLIB |
296 | select NEED_MACH_IO_H if PCI | 298 | select NEED_MACH_IO_H if PCI |
297 | select PLAT_VERSATILE | 299 | select PLAT_VERSATILE |
300 | select PLAT_VERSATILE_CLOCK | ||
298 | select PLAT_VERSATILE_CLCD | 301 | select PLAT_VERSATILE_CLCD |
299 | select PLAT_VERSATILE_FPGA_IRQ | 302 | select PLAT_VERSATILE_FPGA_IRQ |
300 | select ARM_TIMER_SP804 | 303 | select ARM_TIMER_SP804 |
@@ -307,7 +310,7 @@ config ARCH_VEXPRESS | |||
307 | select ARM_AMBA | 310 | select ARM_AMBA |
308 | select ARM_TIMER_SP804 | 311 | select ARM_TIMER_SP804 |
309 | select CLKDEV_LOOKUP | 312 | select CLKDEV_LOOKUP |
310 | select HAVE_MACH_CLKDEV | 313 | select COMMON_CLK |
311 | select GENERIC_CLOCKEVENTS | 314 | select GENERIC_CLOCKEVENTS |
312 | select HAVE_CLK | 315 | select HAVE_CLK |
313 | select HAVE_PATA_PLATFORM | 316 | select HAVE_PATA_PLATFORM |
@@ -315,6 +318,7 @@ config ARCH_VEXPRESS | |||
315 | select NO_IOPORT | 318 | select NO_IOPORT |
316 | select PLAT_VERSATILE | 319 | select PLAT_VERSATILE |
317 | select PLAT_VERSATILE_CLCD | 320 | select PLAT_VERSATILE_CLCD |
321 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
318 | help | 322 | help |
319 | This enables support for the ARM Ltd Versatile Express boards. | 323 | This enables support for the ARM Ltd Versatile Express boards. |
320 | 324 | ||
@@ -567,6 +571,7 @@ config ARCH_LPC32XX | |||
567 | select CLKDEV_LOOKUP | 571 | select CLKDEV_LOOKUP |
568 | select GENERIC_CLOCKEVENTS | 572 | select GENERIC_CLOCKEVENTS |
569 | select USE_OF | 573 | select USE_OF |
574 | select HAVE_PWM | ||
570 | help | 575 | help |
571 | Support for the NXP LPC32XX family of processors | 576 | Support for the NXP LPC32XX family of processors |
572 | 577 | ||
@@ -914,7 +919,7 @@ config ARCH_NOMADIK | |||
914 | select ARM_AMBA | 919 | select ARM_AMBA |
915 | select ARM_VIC | 920 | select ARM_VIC |
916 | select CPU_ARM926T | 921 | select CPU_ARM926T |
917 | select CLKDEV_LOOKUP | 922 | select COMMON_CLK |
918 | select GENERIC_CLOCKEVENTS | 923 | select GENERIC_CLOCKEVENTS |
919 | select PINCTRL | 924 | select PINCTRL |
920 | select MIGHT_HAVE_CACHE_L2X0 | 925 | select MIGHT_HAVE_CACHE_L2X0 |
@@ -937,6 +942,7 @@ config ARCH_DAVINCI | |||
937 | 942 | ||
938 | config ARCH_OMAP | 943 | config ARCH_OMAP |
939 | bool "TI OMAP" | 944 | bool "TI OMAP" |
945 | depends on MMU | ||
940 | select HAVE_CLK | 946 | select HAVE_CLK |
941 | select ARCH_REQUIRE_GPIOLIB | 947 | select ARCH_REQUIRE_GPIOLIB |
942 | select ARCH_HAS_CPUFREQ | 948 | select ARCH_HAS_CPUFREQ |
@@ -1022,8 +1028,6 @@ source "arch/arm/mach-kirkwood/Kconfig" | |||
1022 | 1028 | ||
1023 | source "arch/arm/mach-ks8695/Kconfig" | 1029 | source "arch/arm/mach-ks8695/Kconfig" |
1024 | 1030 | ||
1025 | source "arch/arm/mach-lpc32xx/Kconfig" | ||
1026 | |||
1027 | source "arch/arm/mach-msm/Kconfig" | 1031 | source "arch/arm/mach-msm/Kconfig" |
1028 | 1032 | ||
1029 | source "arch/arm/mach-mv78xx0/Kconfig" | 1033 | source "arch/arm/mach-mv78xx0/Kconfig" |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 01a134141216..a03b5a7059e2 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -310,6 +310,32 @@ choice | |||
310 | The uncompressor code port configuration is now handled | 310 | The uncompressor code port configuration is now handled |
311 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | 311 | by CONFIG_S3C_LOWLEVEL_UART_PORT. |
312 | 312 | ||
313 | config DEBUG_VEXPRESS_UART0_DETECT | ||
314 | bool "Autodetect UART0 on Versatile Express Cortex-A core tiles" | ||
315 | depends on ARCH_VEXPRESS && CPU_CP15_MMU | ||
316 | help | ||
317 | This option enables a simple heuristic which tries to determine | ||
318 | the motherboard's memory map variant (original or RS1) and then | ||
319 | choose the relevant UART0 base address. | ||
320 | |||
321 | Note that this will only work with standard A-class core tiles, | ||
322 | and may fail with non-standard SMM or custom software models. | ||
323 | |||
324 | config DEBUG_VEXPRESS_UART0_CA9 | ||
325 | bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)" | ||
326 | depends on ARCH_VEXPRESS | ||
327 | help | ||
328 | This option selects UART0 at 0x10009000. Except for custom models, | ||
329 | this applies only to the V2P-CA9 tile. | ||
330 | |||
331 | config DEBUG_VEXPRESS_UART0_RS1 | ||
332 | bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)" | ||
333 | depends on ARCH_VEXPRESS | ||
334 | help | ||
335 | This option selects UART0 at 0x1c090000. This applies to most | ||
336 | of the tiles using the RS1 memory map, including all new A-class | ||
337 | core tiles, FPGA-based SMMs and software models. | ||
338 | |||
313 | config DEBUG_LL_UART_NONE | 339 | config DEBUG_LL_UART_NONE |
314 | bool "No low-level debugging UART" | 340 | bool "No low-level debugging UART" |
315 | help | 341 | help |
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts new file mode 100644 index 000000000000..29b9f15e7599 --- /dev/null +++ b/arch/arm/boot/dts/aks-cdu.dts | |||
@@ -0,0 +1,113 @@ | |||
1 | /* | ||
2 | * aks-cdu.dts - Device Tree file for AK signal CDU | ||
3 | * | ||
4 | * Copyright (C) 2012 AK signal Brno a.s. | ||
5 | * 2012 Jiri Prchal <jiri.prchal@aksignal.cz> | ||
6 | * | ||
7 | * Licensed under GPLv2 or later. | ||
8 | */ | ||
9 | |||
10 | /dts-v1/; | ||
11 | |||
12 | /include/ "ge863-pro3.dtsi" | ||
13 | |||
14 | / { | ||
15 | chosen { | ||
16 | bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; | ||
17 | }; | ||
18 | |||
19 | ahb { | ||
20 | apb { | ||
21 | usart0: serial@fffb0000 { | ||
22 | status = "okay"; | ||
23 | }; | ||
24 | |||
25 | usart1: serial@fffb4000 { | ||
26 | status = "okay"; | ||
27 | linux,rs485-enabled-at-boot-time; | ||
28 | rs485-rts-delay = <0 0>; | ||
29 | }; | ||
30 | |||
31 | usart2: serial@fffb8000 { | ||
32 | status = "okay"; | ||
33 | linux,rs485-enabled-at-boot-time; | ||
34 | rs485-rts-delay = <0 0>; | ||
35 | }; | ||
36 | |||
37 | usart3: serial@fffd0000 { | ||
38 | status = "okay"; | ||
39 | linux,rs485-enabled-at-boot-time; | ||
40 | rs485-rts-delay = <0 0>; | ||
41 | }; | ||
42 | |||
43 | macb0: ethernet@fffc4000 { | ||
44 | phy-mode = "rmii"; | ||
45 | status = "okay"; | ||
46 | }; | ||
47 | |||
48 | usb1: gadget@fffa4000 { | ||
49 | atmel,vbus-gpio = <&pioC 15 0>; | ||
50 | status = "okay"; | ||
51 | }; | ||
52 | }; | ||
53 | |||
54 | usb0: ohci@00500000 { | ||
55 | num-ports = <2>; | ||
56 | status = "okay"; | ||
57 | }; | ||
58 | |||
59 | nand0: nand@40000000 { | ||
60 | nand-bus-width = <8>; | ||
61 | nand-ecc-mode = "soft"; | ||
62 | nand-on-flash-bbt; | ||
63 | status = "okay"; | ||
64 | |||
65 | bootstrap@0 { | ||
66 | label = "bootstrap"; | ||
67 | reg = <0x0 0x40000>; | ||
68 | }; | ||
69 | |||
70 | uboot@40000 { | ||
71 | label = "uboot"; | ||
72 | reg = <0x40000 0x80000>; | ||
73 | }; | ||
74 | ubootenv@c0000 { | ||
75 | label = "ubootenv"; | ||
76 | reg = <0xc0000 0x40000>; | ||
77 | }; | ||
78 | kernel@100000 { | ||
79 | label = "kernel"; | ||
80 | reg = <0x100000 0x400000>; | ||
81 | }; | ||
82 | rootfs@500000 { | ||
83 | label = "rootfs"; | ||
84 | reg = <0x500000 0x7b00000>; | ||
85 | }; | ||
86 | }; | ||
87 | }; | ||
88 | |||
89 | leds { | ||
90 | compatible = "gpio-leds"; | ||
91 | |||
92 | red { | ||
93 | gpios = <&pioC 10 0>; | ||
94 | linux,default-trigger = "none"; | ||
95 | }; | ||
96 | |||
97 | green { | ||
98 | gpios = <&pioA 5 1>; | ||
99 | linux,default-trigger = "none"; | ||
100 | default-state = "on"; | ||
101 | }; | ||
102 | |||
103 | yellow { | ||
104 | gpios = <&pioB 20 1>; | ||
105 | linux,default-trigger = "none"; | ||
106 | }; | ||
107 | |||
108 | blue { | ||
109 | gpios = <&pioB 21 1>; | ||
110 | linux,default-trigger = "none"; | ||
111 | }; | ||
112 | }; | ||
113 | }; | ||
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts new file mode 100644 index 000000000000..a9af4db7234c --- /dev/null +++ b/arch/arm/boot/dts/am335x-bone.dts | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "am33xx.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "TI AM335x BeagleBone"; | ||
14 | compatible = "ti,am335x-bone", "ti,am33xx"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
19 | }; | ||
20 | }; | ||
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts new file mode 100644 index 000000000000..d6a97d9eff72 --- /dev/null +++ b/arch/arm/boot/dts/am335x-evm.dts | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "am33xx.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "TI AM335x EVM"; | ||
14 | compatible = "ti,am335x-evm", "ti,am33xx"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
19 | }; | ||
20 | }; | ||
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi new file mode 100644 index 000000000000..59509c48d7e5 --- /dev/null +++ b/arch/arm/boot/dts/am33xx.dtsi | |||
@@ -0,0 +1,158 @@ | |||
1 | /* | ||
2 | * Device Tree Source for AM33XX SoC | ||
3 | * | ||
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public License | ||
7 | * version 2. This program is licensed "as is" without any warranty of any | ||
8 | * kind, whether express or implied. | ||
9 | */ | ||
10 | |||
11 | /include/ "skeleton.dtsi" | ||
12 | |||
13 | / { | ||
14 | compatible = "ti,am33xx"; | ||
15 | |||
16 | aliases { | ||
17 | serial0 = &uart1; | ||
18 | serial1 = &uart2; | ||
19 | serial2 = &uart3; | ||
20 | serial3 = &uart4; | ||
21 | serial4 = &uart5; | ||
22 | serial5 = &uart6; | ||
23 | }; | ||
24 | |||
25 | cpus { | ||
26 | cpu@0 { | ||
27 | compatible = "arm,cortex-a8"; | ||
28 | }; | ||
29 | }; | ||
30 | |||
31 | /* | ||
32 | * The soc node represents the soc top level view. It is uses for IPs | ||
33 | * that are not memory mapped in the MPU view or for the MPU itself. | ||
34 | */ | ||
35 | soc { | ||
36 | compatible = "ti,omap-infra"; | ||
37 | mpu { | ||
38 | compatible = "ti,omap3-mpu"; | ||
39 | ti,hwmods = "mpu"; | ||
40 | }; | ||
41 | }; | ||
42 | |||
43 | /* | ||
44 | * XXX: Use a flat representation of the AM33XX interconnect. | ||
45 | * The real AM33XX interconnect network is quite complex.Since | ||
46 | * that will not bring real advantage to represent that in DT | ||
47 | * for the moment, just use a fake OCP bus entry to represent | ||
48 | * the whole bus hierarchy. | ||
49 | */ | ||
50 | ocp { | ||
51 | compatible = "simple-bus"; | ||
52 | #address-cells = <1>; | ||
53 | #size-cells = <1>; | ||
54 | ranges; | ||
55 | ti,hwmods = "l3_main"; | ||
56 | |||
57 | intc: interrupt-controller@48200000 { | ||
58 | compatible = "ti,omap2-intc"; | ||
59 | interrupt-controller; | ||
60 | #interrupt-cells = <1>; | ||
61 | ti,intc-size = <128>; | ||
62 | reg = <0x48200000 0x1000>; | ||
63 | }; | ||
64 | |||
65 | gpio1: gpio@44e07000 { | ||
66 | compatible = "ti,omap4-gpio"; | ||
67 | ti,hwmods = "gpio1"; | ||
68 | gpio-controller; | ||
69 | #gpio-cells = <2>; | ||
70 | interrupt-controller; | ||
71 | #interrupt-cells = <1>; | ||
72 | }; | ||
73 | |||
74 | gpio2: gpio@4804C000 { | ||
75 | compatible = "ti,omap4-gpio"; | ||
76 | ti,hwmods = "gpio2"; | ||
77 | gpio-controller; | ||
78 | #gpio-cells = <2>; | ||
79 | interrupt-controller; | ||
80 | #interrupt-cells = <1>; | ||
81 | }; | ||
82 | |||
83 | gpio3: gpio@481AC000 { | ||
84 | compatible = "ti,omap4-gpio"; | ||
85 | ti,hwmods = "gpio3"; | ||
86 | gpio-controller; | ||
87 | #gpio-cells = <2>; | ||
88 | interrupt-controller; | ||
89 | #interrupt-cells = <1>; | ||
90 | }; | ||
91 | |||
92 | gpio4: gpio@481AE000 { | ||
93 | compatible = "ti,omap4-gpio"; | ||
94 | ti,hwmods = "gpio4"; | ||
95 | gpio-controller; | ||
96 | #gpio-cells = <2>; | ||
97 | interrupt-controller; | ||
98 | #interrupt-cells = <1>; | ||
99 | }; | ||
100 | |||
101 | uart1: serial@44E09000 { | ||
102 | compatible = "ti,omap3-uart"; | ||
103 | ti,hwmods = "uart1"; | ||
104 | clock-frequency = <48000000>; | ||
105 | }; | ||
106 | |||
107 | uart2: serial@48022000 { | ||
108 | compatible = "ti,omap3-uart"; | ||
109 | ti,hwmods = "uart2"; | ||
110 | clock-frequency = <48000000>; | ||
111 | }; | ||
112 | |||
113 | uart3: serial@48024000 { | ||
114 | compatible = "ti,omap3-uart"; | ||
115 | ti,hwmods = "uart3"; | ||
116 | clock-frequency = <48000000>; | ||
117 | }; | ||
118 | |||
119 | uart4: serial@481A6000 { | ||
120 | compatible = "ti,omap3-uart"; | ||
121 | ti,hwmods = "uart4"; | ||
122 | clock-frequency = <48000000>; | ||
123 | }; | ||
124 | |||
125 | uart5: serial@481A8000 { | ||
126 | compatible = "ti,omap3-uart"; | ||
127 | ti,hwmods = "uart5"; | ||
128 | clock-frequency = <48000000>; | ||
129 | }; | ||
130 | |||
131 | uart6: serial@481AA000 { | ||
132 | compatible = "ti,omap3-uart"; | ||
133 | ti,hwmods = "uart6"; | ||
134 | clock-frequency = <48000000>; | ||
135 | }; | ||
136 | |||
137 | i2c1: i2c@44E0B000 { | ||
138 | compatible = "ti,omap4-i2c"; | ||
139 | #address-cells = <1>; | ||
140 | #size-cells = <0>; | ||
141 | ti,hwmods = "i2c1"; | ||
142 | }; | ||
143 | |||
144 | i2c2: i2c@4802A000 { | ||
145 | compatible = "ti,omap4-i2c"; | ||
146 | #address-cells = <1>; | ||
147 | #size-cells = <0>; | ||
148 | ti,hwmods = "i2c2"; | ||
149 | }; | ||
150 | |||
151 | i2c3: i2c@4819C000 { | ||
152 | compatible = "ti,omap4-i2c"; | ||
153 | #address-cells = <1>; | ||
154 | #size-cells = <0>; | ||
155 | ti,hwmods = "i2c3"; | ||
156 | }; | ||
157 | }; | ||
158 | }; | ||
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts new file mode 100644 index 000000000000..474f760ecadf --- /dev/null +++ b/arch/arm/boot/dts/am3517-evm.dts | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "omap3.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "TI AM3517 EVM (AM3517/05)"; | ||
14 | compatible = "ti,am3517-evm", "ti,omap3"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | ||
19 | }; | ||
20 | }; | ||
21 | |||
22 | &i2c1 { | ||
23 | clock-frequency = <400000>; | ||
24 | }; | ||
25 | |||
26 | &i2c2 { | ||
27 | clock-frequency = <400000>; | ||
28 | }; | ||
29 | |||
30 | &i2c3 { | ||
31 | clock-frequency = <400000>; | ||
32 | }; | ||
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index f449efc9825f..66389c1c6f62 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi | |||
@@ -52,10 +52,11 @@ | |||
52 | ranges; | 52 | ranges; |
53 | 53 | ||
54 | aic: interrupt-controller@fffff000 { | 54 | aic: interrupt-controller@fffff000 { |
55 | #interrupt-cells = <2>; | 55 | #interrupt-cells = <3>; |
56 | compatible = "atmel,at91rm9200-aic"; | 56 | compatible = "atmel,at91rm9200-aic"; |
57 | interrupt-controller; | 57 | interrupt-controller; |
58 | reg = <0xfffff000 0x200>; | 58 | reg = <0xfffff000 0x200>; |
59 | atmel,external-irqs = <29 30 31>; | ||
59 | }; | 60 | }; |
60 | 61 | ||
61 | ramc0: ramc@ffffea00 { | 62 | ramc0: ramc@ffffea00 { |
@@ -81,25 +82,25 @@ | |||
81 | pit: timer@fffffd30 { | 82 | pit: timer@fffffd30 { |
82 | compatible = "atmel,at91sam9260-pit"; | 83 | compatible = "atmel,at91sam9260-pit"; |
83 | reg = <0xfffffd30 0xf>; | 84 | reg = <0xfffffd30 0xf>; |
84 | interrupts = <1 4>; | 85 | interrupts = <1 4 7>; |
85 | }; | 86 | }; |
86 | 87 | ||
87 | tcb0: timer@fffa0000 { | 88 | tcb0: timer@fffa0000 { |
88 | compatible = "atmel,at91rm9200-tcb"; | 89 | compatible = "atmel,at91rm9200-tcb"; |
89 | reg = <0xfffa0000 0x100>; | 90 | reg = <0xfffa0000 0x100>; |
90 | interrupts = <17 4 18 4 19 4>; | 91 | interrupts = <17 4 0 18 4 0 19 4 0>; |
91 | }; | 92 | }; |
92 | 93 | ||
93 | tcb1: timer@fffdc000 { | 94 | tcb1: timer@fffdc000 { |
94 | compatible = "atmel,at91rm9200-tcb"; | 95 | compatible = "atmel,at91rm9200-tcb"; |
95 | reg = <0xfffdc000 0x100>; | 96 | reg = <0xfffdc000 0x100>; |
96 | interrupts = <26 4 27 4 28 4>; | 97 | interrupts = <26 4 0 27 4 0 28 4 0>; |
97 | }; | 98 | }; |
98 | 99 | ||
99 | pioA: gpio@fffff400 { | 100 | pioA: gpio@fffff400 { |
100 | compatible = "atmel,at91rm9200-gpio"; | 101 | compatible = "atmel,at91rm9200-gpio"; |
101 | reg = <0xfffff400 0x100>; | 102 | reg = <0xfffff400 0x100>; |
102 | interrupts = <2 4>; | 103 | interrupts = <2 4 1>; |
103 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
104 | gpio-controller; | 105 | gpio-controller; |
105 | interrupt-controller; | 106 | interrupt-controller; |
@@ -108,7 +109,7 @@ | |||
108 | pioB: gpio@fffff600 { | 109 | pioB: gpio@fffff600 { |
109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
110 | reg = <0xfffff600 0x100>; | 111 | reg = <0xfffff600 0x100>; |
111 | interrupts = <3 4>; | 112 | interrupts = <3 4 1>; |
112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
113 | gpio-controller; | 114 | gpio-controller; |
114 | interrupt-controller; | 115 | interrupt-controller; |
@@ -117,7 +118,7 @@ | |||
117 | pioC: gpio@fffff800 { | 118 | pioC: gpio@fffff800 { |
118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
119 | reg = <0xfffff800 0x100>; | 120 | reg = <0xfffff800 0x100>; |
120 | interrupts = <4 4>; | 121 | interrupts = <4 4 1>; |
121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
122 | gpio-controller; | 123 | gpio-controller; |
123 | interrupt-controller; | 124 | interrupt-controller; |
@@ -126,14 +127,14 @@ | |||
126 | dbgu: serial@fffff200 { | 127 | dbgu: serial@fffff200 { |
127 | compatible = "atmel,at91sam9260-usart"; | 128 | compatible = "atmel,at91sam9260-usart"; |
128 | reg = <0xfffff200 0x200>; | 129 | reg = <0xfffff200 0x200>; |
129 | interrupts = <1 4>; | 130 | interrupts = <1 4 7>; |
130 | status = "disabled"; | 131 | status = "disabled"; |
131 | }; | 132 | }; |
132 | 133 | ||
133 | usart0: serial@fffb0000 { | 134 | usart0: serial@fffb0000 { |
134 | compatible = "atmel,at91sam9260-usart"; | 135 | compatible = "atmel,at91sam9260-usart"; |
135 | reg = <0xfffb0000 0x200>; | 136 | reg = <0xfffb0000 0x200>; |
136 | interrupts = <6 4>; | 137 | interrupts = <6 4 5>; |
137 | atmel,use-dma-rx; | 138 | atmel,use-dma-rx; |
138 | atmel,use-dma-tx; | 139 | atmel,use-dma-tx; |
139 | status = "disabled"; | 140 | status = "disabled"; |
@@ -142,7 +143,7 @@ | |||
142 | usart1: serial@fffb4000 { | 143 | usart1: serial@fffb4000 { |
143 | compatible = "atmel,at91sam9260-usart"; | 144 | compatible = "atmel,at91sam9260-usart"; |
144 | reg = <0xfffb4000 0x200>; | 145 | reg = <0xfffb4000 0x200>; |
145 | interrupts = <7 4>; | 146 | interrupts = <7 4 5>; |
146 | atmel,use-dma-rx; | 147 | atmel,use-dma-rx; |
147 | atmel,use-dma-tx; | 148 | atmel,use-dma-tx; |
148 | status = "disabled"; | 149 | status = "disabled"; |
@@ -151,7 +152,7 @@ | |||
151 | usart2: serial@fffb8000 { | 152 | usart2: serial@fffb8000 { |
152 | compatible = "atmel,at91sam9260-usart"; | 153 | compatible = "atmel,at91sam9260-usart"; |
153 | reg = <0xfffb8000 0x200>; | 154 | reg = <0xfffb8000 0x200>; |
154 | interrupts = <8 4>; | 155 | interrupts = <8 4 5>; |
155 | atmel,use-dma-rx; | 156 | atmel,use-dma-rx; |
156 | atmel,use-dma-tx; | 157 | atmel,use-dma-tx; |
157 | status = "disabled"; | 158 | status = "disabled"; |
@@ -160,7 +161,7 @@ | |||
160 | usart3: serial@fffd0000 { | 161 | usart3: serial@fffd0000 { |
161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
162 | reg = <0xfffd0000 0x200>; | 163 | reg = <0xfffd0000 0x200>; |
163 | interrupts = <23 4>; | 164 | interrupts = <23 4 5>; |
164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
166 | status = "disabled"; | 167 | status = "disabled"; |
@@ -169,7 +170,7 @@ | |||
169 | usart4: serial@fffd4000 { | 170 | usart4: serial@fffd4000 { |
170 | compatible = "atmel,at91sam9260-usart"; | 171 | compatible = "atmel,at91sam9260-usart"; |
171 | reg = <0xfffd4000 0x200>; | 172 | reg = <0xfffd4000 0x200>; |
172 | interrupts = <24 4>; | 173 | interrupts = <24 4 5>; |
173 | atmel,use-dma-rx; | 174 | atmel,use-dma-rx; |
174 | atmel,use-dma-tx; | 175 | atmel,use-dma-tx; |
175 | status = "disabled"; | 176 | status = "disabled"; |
@@ -178,7 +179,7 @@ | |||
178 | usart5: serial@fffd8000 { | 179 | usart5: serial@fffd8000 { |
179 | compatible = "atmel,at91sam9260-usart"; | 180 | compatible = "atmel,at91sam9260-usart"; |
180 | reg = <0xfffd8000 0x200>; | 181 | reg = <0xfffd8000 0x200>; |
181 | interrupts = <25 4>; | 182 | interrupts = <25 4 5>; |
182 | atmel,use-dma-rx; | 183 | atmel,use-dma-rx; |
183 | atmel,use-dma-tx; | 184 | atmel,use-dma-tx; |
184 | status = "disabled"; | 185 | status = "disabled"; |
@@ -187,21 +188,21 @@ | |||
187 | macb0: ethernet@fffc4000 { | 188 | macb0: ethernet@fffc4000 { |
188 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 189 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
189 | reg = <0xfffc4000 0x100>; | 190 | reg = <0xfffc4000 0x100>; |
190 | interrupts = <21 4>; | 191 | interrupts = <21 4 3>; |
191 | status = "disabled"; | 192 | status = "disabled"; |
192 | }; | 193 | }; |
193 | 194 | ||
194 | usb1: gadget@fffa4000 { | 195 | usb1: gadget@fffa4000 { |
195 | compatible = "atmel,at91rm9200-udc"; | 196 | compatible = "atmel,at91rm9200-udc"; |
196 | reg = <0xfffa4000 0x4000>; | 197 | reg = <0xfffa4000 0x4000>; |
197 | interrupts = <10 4>; | 198 | interrupts = <10 4 2>; |
198 | status = "disabled"; | 199 | status = "disabled"; |
199 | }; | 200 | }; |
200 | 201 | ||
201 | adc0: adc@fffe0000 { | 202 | adc0: adc@fffe0000 { |
202 | compatible = "atmel,at91sam9260-adc"; | 203 | compatible = "atmel,at91sam9260-adc"; |
203 | reg = <0xfffe0000 0x100>; | 204 | reg = <0xfffe0000 0x100>; |
204 | interrupts = <5 4>; | 205 | interrupts = <5 4 0>; |
205 | atmel,adc-use-external-triggers; | 206 | atmel,adc-use-external-triggers; |
206 | atmel,adc-channels-used = <0xf>; | 207 | atmel,adc-channels-used = <0xf>; |
207 | atmel,adc-vref = <3300>; | 208 | atmel,adc-vref = <3300>; |
@@ -253,7 +254,7 @@ | |||
253 | usb0: ohci@00500000 { | 254 | usb0: ohci@00500000 { |
254 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 255 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
255 | reg = <0x00500000 0x100000>; | 256 | reg = <0x00500000 0x100000>; |
256 | interrupts = <20 4>; | 257 | interrupts = <20 4 2>; |
257 | status = "disabled"; | 258 | status = "disabled"; |
258 | }; | 259 | }; |
259 | }; | 260 | }; |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index 0209913a65a2..b460d6ce9eb5 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
@@ -48,10 +48,11 @@ | |||
48 | ranges; | 48 | ranges; |
49 | 49 | ||
50 | aic: interrupt-controller@fffff000 { | 50 | aic: interrupt-controller@fffff000 { |
51 | #interrupt-cells = <2>; | 51 | #interrupt-cells = <3>; |
52 | compatible = "atmel,at91rm9200-aic"; | 52 | compatible = "atmel,at91rm9200-aic"; |
53 | interrupt-controller; | 53 | interrupt-controller; |
54 | reg = <0xfffff000 0x200>; | 54 | reg = <0xfffff000 0x200>; |
55 | atmel,external-irqs = <30 31>; | ||
55 | }; | 56 | }; |
56 | 57 | ||
57 | pmc: pmc@fffffc00 { | 58 | pmc: pmc@fffffc00 { |
@@ -68,13 +69,13 @@ | |||
68 | pit: timer@fffffd30 { | 69 | pit: timer@fffffd30 { |
69 | compatible = "atmel,at91sam9260-pit"; | 70 | compatible = "atmel,at91sam9260-pit"; |
70 | reg = <0xfffffd30 0xf>; | 71 | reg = <0xfffffd30 0xf>; |
71 | interrupts = <1 4>; | 72 | interrupts = <1 4 7>; |
72 | }; | 73 | }; |
73 | 74 | ||
74 | tcb0: timer@fff7c000 { | 75 | tcb0: timer@fff7c000 { |
75 | compatible = "atmel,at91rm9200-tcb"; | 76 | compatible = "atmel,at91rm9200-tcb"; |
76 | reg = <0xfff7c000 0x100>; | 77 | reg = <0xfff7c000 0x100>; |
77 | interrupts = <19 4>; | 78 | interrupts = <19 4 0>; |
78 | }; | 79 | }; |
79 | 80 | ||
80 | rstc@fffffd00 { | 81 | rstc@fffffd00 { |
@@ -90,7 +91,7 @@ | |||
90 | pioA: gpio@fffff200 { | 91 | pioA: gpio@fffff200 { |
91 | compatible = "atmel,at91rm9200-gpio"; | 92 | compatible = "atmel,at91rm9200-gpio"; |
92 | reg = <0xfffff200 0x100>; | 93 | reg = <0xfffff200 0x100>; |
93 | interrupts = <2 4>; | 94 | interrupts = <2 4 1>; |
94 | #gpio-cells = <2>; | 95 | #gpio-cells = <2>; |
95 | gpio-controller; | 96 | gpio-controller; |
96 | interrupt-controller; | 97 | interrupt-controller; |
@@ -99,7 +100,7 @@ | |||
99 | pioB: gpio@fffff400 { | 100 | pioB: gpio@fffff400 { |
100 | compatible = "atmel,at91rm9200-gpio"; | 101 | compatible = "atmel,at91rm9200-gpio"; |
101 | reg = <0xfffff400 0x100>; | 102 | reg = <0xfffff400 0x100>; |
102 | interrupts = <3 4>; | 103 | interrupts = <3 4 1>; |
103 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
104 | gpio-controller; | 105 | gpio-controller; |
105 | interrupt-controller; | 106 | interrupt-controller; |
@@ -108,7 +109,7 @@ | |||
108 | pioC: gpio@fffff600 { | 109 | pioC: gpio@fffff600 { |
109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
110 | reg = <0xfffff600 0x100>; | 111 | reg = <0xfffff600 0x100>; |
111 | interrupts = <4 4>; | 112 | interrupts = <4 4 1>; |
112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
113 | gpio-controller; | 114 | gpio-controller; |
114 | interrupt-controller; | 115 | interrupt-controller; |
@@ -117,7 +118,7 @@ | |||
117 | pioD: gpio@fffff800 { | 118 | pioD: gpio@fffff800 { |
118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
119 | reg = <0xfffff800 0x100>; | 120 | reg = <0xfffff800 0x100>; |
120 | interrupts = <4 4>; | 121 | interrupts = <4 4 1>; |
121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
122 | gpio-controller; | 123 | gpio-controller; |
123 | interrupt-controller; | 124 | interrupt-controller; |
@@ -126,7 +127,7 @@ | |||
126 | pioE: gpio@fffffa00 { | 127 | pioE: gpio@fffffa00 { |
127 | compatible = "atmel,at91rm9200-gpio"; | 128 | compatible = "atmel,at91rm9200-gpio"; |
128 | reg = <0xfffffa00 0x100>; | 129 | reg = <0xfffffa00 0x100>; |
129 | interrupts = <4 4>; | 130 | interrupts = <4 4 1>; |
130 | #gpio-cells = <2>; | 131 | #gpio-cells = <2>; |
131 | gpio-controller; | 132 | gpio-controller; |
132 | interrupt-controller; | 133 | interrupt-controller; |
@@ -135,14 +136,14 @@ | |||
135 | dbgu: serial@ffffee00 { | 136 | dbgu: serial@ffffee00 { |
136 | compatible = "atmel,at91sam9260-usart"; | 137 | compatible = "atmel,at91sam9260-usart"; |
137 | reg = <0xffffee00 0x200>; | 138 | reg = <0xffffee00 0x200>; |
138 | interrupts = <1 4>; | 139 | interrupts = <1 4 7>; |
139 | status = "disabled"; | 140 | status = "disabled"; |
140 | }; | 141 | }; |
141 | 142 | ||
142 | usart0: serial@fff8c000 { | 143 | usart0: serial@fff8c000 { |
143 | compatible = "atmel,at91sam9260-usart"; | 144 | compatible = "atmel,at91sam9260-usart"; |
144 | reg = <0xfff8c000 0x200>; | 145 | reg = <0xfff8c000 0x200>; |
145 | interrupts = <7 4>; | 146 | interrupts = <7 4 5>; |
146 | atmel,use-dma-rx; | 147 | atmel,use-dma-rx; |
147 | atmel,use-dma-tx; | 148 | atmel,use-dma-tx; |
148 | status = "disabled"; | 149 | status = "disabled"; |
@@ -151,7 +152,7 @@ | |||
151 | usart1: serial@fff90000 { | 152 | usart1: serial@fff90000 { |
152 | compatible = "atmel,at91sam9260-usart"; | 153 | compatible = "atmel,at91sam9260-usart"; |
153 | reg = <0xfff90000 0x200>; | 154 | reg = <0xfff90000 0x200>; |
154 | interrupts = <8 4>; | 155 | interrupts = <8 4 5>; |
155 | atmel,use-dma-rx; | 156 | atmel,use-dma-rx; |
156 | atmel,use-dma-tx; | 157 | atmel,use-dma-tx; |
157 | status = "disabled"; | 158 | status = "disabled"; |
@@ -160,7 +161,7 @@ | |||
160 | usart2: serial@fff94000 { | 161 | usart2: serial@fff94000 { |
161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
162 | reg = <0xfff94000 0x200>; | 163 | reg = <0xfff94000 0x200>; |
163 | interrupts = <9 4>; | 164 | interrupts = <9 4 5>; |
164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
166 | status = "disabled"; | 167 | status = "disabled"; |
@@ -169,14 +170,14 @@ | |||
169 | macb0: ethernet@fffbc000 { | 170 | macb0: ethernet@fffbc000 { |
170 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 171 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
171 | reg = <0xfffbc000 0x100>; | 172 | reg = <0xfffbc000 0x100>; |
172 | interrupts = <21 4>; | 173 | interrupts = <21 4 3>; |
173 | status = "disabled"; | 174 | status = "disabled"; |
174 | }; | 175 | }; |
175 | 176 | ||
176 | usb1: gadget@fff78000 { | 177 | usb1: gadget@fff78000 { |
177 | compatible = "atmel,at91rm9200-udc"; | 178 | compatible = "atmel,at91rm9200-udc"; |
178 | reg = <0xfff78000 0x4000>; | 179 | reg = <0xfff78000 0x4000>; |
179 | interrupts = <24 4>; | 180 | interrupts = <24 4 2>; |
180 | status = "disabled"; | 181 | status = "disabled"; |
181 | }; | 182 | }; |
182 | }; | 183 | }; |
@@ -200,7 +201,7 @@ | |||
200 | usb0: ohci@00a00000 { | 201 | usb0: ohci@00a00000 { |
201 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
202 | reg = <0x00a00000 0x100000>; | 203 | reg = <0x00a00000 0x100000>; |
203 | interrupts = <29 4>; | 204 | interrupts = <29 4 2>; |
204 | status = "disabled"; | 205 | status = "disabled"; |
205 | }; | 206 | }; |
206 | }; | 207 | }; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 7dbccaf199f7..bafa8806fc17 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
@@ -53,10 +53,11 @@ | |||
53 | ranges; | 53 | ranges; |
54 | 54 | ||
55 | aic: interrupt-controller@fffff000 { | 55 | aic: interrupt-controller@fffff000 { |
56 | #interrupt-cells = <2>; | 56 | #interrupt-cells = <3>; |
57 | compatible = "atmel,at91rm9200-aic"; | 57 | compatible = "atmel,at91rm9200-aic"; |
58 | interrupt-controller; | 58 | interrupt-controller; |
59 | reg = <0xfffff000 0x200>; | 59 | reg = <0xfffff000 0x200>; |
60 | atmel,external-irqs = <31>; | ||
60 | }; | 61 | }; |
61 | 62 | ||
62 | ramc0: ramc@ffffe400 { | 63 | ramc0: ramc@ffffe400 { |
@@ -78,7 +79,7 @@ | |||
78 | pit: timer@fffffd30 { | 79 | pit: timer@fffffd30 { |
79 | compatible = "atmel,at91sam9260-pit"; | 80 | compatible = "atmel,at91sam9260-pit"; |
80 | reg = <0xfffffd30 0xf>; | 81 | reg = <0xfffffd30 0xf>; |
81 | interrupts = <1 4>; | 82 | interrupts = <1 4 7>; |
82 | }; | 83 | }; |
83 | 84 | ||
84 | 85 | ||
@@ -90,25 +91,25 @@ | |||
90 | tcb0: timer@fff7c000 { | 91 | tcb0: timer@fff7c000 { |
91 | compatible = "atmel,at91rm9200-tcb"; | 92 | compatible = "atmel,at91rm9200-tcb"; |
92 | reg = <0xfff7c000 0x100>; | 93 | reg = <0xfff7c000 0x100>; |
93 | interrupts = <18 4>; | 94 | interrupts = <18 4 0>; |
94 | }; | 95 | }; |
95 | 96 | ||
96 | tcb1: timer@fffd4000 { | 97 | tcb1: timer@fffd4000 { |
97 | compatible = "atmel,at91rm9200-tcb"; | 98 | compatible = "atmel,at91rm9200-tcb"; |
98 | reg = <0xfffd4000 0x100>; | 99 | reg = <0xfffd4000 0x100>; |
99 | interrupts = <18 4>; | 100 | interrupts = <18 4 0>; |
100 | }; | 101 | }; |
101 | 102 | ||
102 | dma: dma-controller@ffffec00 { | 103 | dma: dma-controller@ffffec00 { |
103 | compatible = "atmel,at91sam9g45-dma"; | 104 | compatible = "atmel,at91sam9g45-dma"; |
104 | reg = <0xffffec00 0x200>; | 105 | reg = <0xffffec00 0x200>; |
105 | interrupts = <21 4>; | 106 | interrupts = <21 4 0>; |
106 | }; | 107 | }; |
107 | 108 | ||
108 | pioA: gpio@fffff200 { | 109 | pioA: gpio@fffff200 { |
109 | compatible = "atmel,at91rm9200-gpio"; | 110 | compatible = "atmel,at91rm9200-gpio"; |
110 | reg = <0xfffff200 0x100>; | 111 | reg = <0xfffff200 0x100>; |
111 | interrupts = <2 4>; | 112 | interrupts = <2 4 1>; |
112 | #gpio-cells = <2>; | 113 | #gpio-cells = <2>; |
113 | gpio-controller; | 114 | gpio-controller; |
114 | interrupt-controller; | 115 | interrupt-controller; |
@@ -117,7 +118,7 @@ | |||
117 | pioB: gpio@fffff400 { | 118 | pioB: gpio@fffff400 { |
118 | compatible = "atmel,at91rm9200-gpio"; | 119 | compatible = "atmel,at91rm9200-gpio"; |
119 | reg = <0xfffff400 0x100>; | 120 | reg = <0xfffff400 0x100>; |
120 | interrupts = <3 4>; | 121 | interrupts = <3 4 1>; |
121 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
122 | gpio-controller; | 123 | gpio-controller; |
123 | interrupt-controller; | 124 | interrupt-controller; |
@@ -126,7 +127,7 @@ | |||
126 | pioC: gpio@fffff600 { | 127 | pioC: gpio@fffff600 { |
127 | compatible = "atmel,at91rm9200-gpio"; | 128 | compatible = "atmel,at91rm9200-gpio"; |
128 | reg = <0xfffff600 0x100>; | 129 | reg = <0xfffff600 0x100>; |
129 | interrupts = <4 4>; | 130 | interrupts = <4 4 1>; |
130 | #gpio-cells = <2>; | 131 | #gpio-cells = <2>; |
131 | gpio-controller; | 132 | gpio-controller; |
132 | interrupt-controller; | 133 | interrupt-controller; |
@@ -135,7 +136,7 @@ | |||
135 | pioD: gpio@fffff800 { | 136 | pioD: gpio@fffff800 { |
136 | compatible = "atmel,at91rm9200-gpio"; | 137 | compatible = "atmel,at91rm9200-gpio"; |
137 | reg = <0xfffff800 0x100>; | 138 | reg = <0xfffff800 0x100>; |
138 | interrupts = <5 4>; | 139 | interrupts = <5 4 1>; |
139 | #gpio-cells = <2>; | 140 | #gpio-cells = <2>; |
140 | gpio-controller; | 141 | gpio-controller; |
141 | interrupt-controller; | 142 | interrupt-controller; |
@@ -144,7 +145,7 @@ | |||
144 | pioE: gpio@fffffa00 { | 145 | pioE: gpio@fffffa00 { |
145 | compatible = "atmel,at91rm9200-gpio"; | 146 | compatible = "atmel,at91rm9200-gpio"; |
146 | reg = <0xfffffa00 0x100>; | 147 | reg = <0xfffffa00 0x100>; |
147 | interrupts = <5 4>; | 148 | interrupts = <5 4 1>; |
148 | #gpio-cells = <2>; | 149 | #gpio-cells = <2>; |
149 | gpio-controller; | 150 | gpio-controller; |
150 | interrupt-controller; | 151 | interrupt-controller; |
@@ -153,14 +154,14 @@ | |||
153 | dbgu: serial@ffffee00 { | 154 | dbgu: serial@ffffee00 { |
154 | compatible = "atmel,at91sam9260-usart"; | 155 | compatible = "atmel,at91sam9260-usart"; |
155 | reg = <0xffffee00 0x200>; | 156 | reg = <0xffffee00 0x200>; |
156 | interrupts = <1 4>; | 157 | interrupts = <1 4 7>; |
157 | status = "disabled"; | 158 | status = "disabled"; |
158 | }; | 159 | }; |
159 | 160 | ||
160 | usart0: serial@fff8c000 { | 161 | usart0: serial@fff8c000 { |
161 | compatible = "atmel,at91sam9260-usart"; | 162 | compatible = "atmel,at91sam9260-usart"; |
162 | reg = <0xfff8c000 0x200>; | 163 | reg = <0xfff8c000 0x200>; |
163 | interrupts = <7 4>; | 164 | interrupts = <7 4 5>; |
164 | atmel,use-dma-rx; | 165 | atmel,use-dma-rx; |
165 | atmel,use-dma-tx; | 166 | atmel,use-dma-tx; |
166 | status = "disabled"; | 167 | status = "disabled"; |
@@ -169,7 +170,7 @@ | |||
169 | usart1: serial@fff90000 { | 170 | usart1: serial@fff90000 { |
170 | compatible = "atmel,at91sam9260-usart"; | 171 | compatible = "atmel,at91sam9260-usart"; |
171 | reg = <0xfff90000 0x200>; | 172 | reg = <0xfff90000 0x200>; |
172 | interrupts = <8 4>; | 173 | interrupts = <8 4 5>; |
173 | atmel,use-dma-rx; | 174 | atmel,use-dma-rx; |
174 | atmel,use-dma-tx; | 175 | atmel,use-dma-tx; |
175 | status = "disabled"; | 176 | status = "disabled"; |
@@ -178,7 +179,7 @@ | |||
178 | usart2: serial@fff94000 { | 179 | usart2: serial@fff94000 { |
179 | compatible = "atmel,at91sam9260-usart"; | 180 | compatible = "atmel,at91sam9260-usart"; |
180 | reg = <0xfff94000 0x200>; | 181 | reg = <0xfff94000 0x200>; |
181 | interrupts = <9 4>; | 182 | interrupts = <9 4 5>; |
182 | atmel,use-dma-rx; | 183 | atmel,use-dma-rx; |
183 | atmel,use-dma-tx; | 184 | atmel,use-dma-tx; |
184 | status = "disabled"; | 185 | status = "disabled"; |
@@ -187,7 +188,7 @@ | |||
187 | usart3: serial@fff98000 { | 188 | usart3: serial@fff98000 { |
188 | compatible = "atmel,at91sam9260-usart"; | 189 | compatible = "atmel,at91sam9260-usart"; |
189 | reg = <0xfff98000 0x200>; | 190 | reg = <0xfff98000 0x200>; |
190 | interrupts = <10 4>; | 191 | interrupts = <10 4 5>; |
191 | atmel,use-dma-rx; | 192 | atmel,use-dma-rx; |
192 | atmel,use-dma-tx; | 193 | atmel,use-dma-tx; |
193 | status = "disabled"; | 194 | status = "disabled"; |
@@ -196,14 +197,14 @@ | |||
196 | macb0: ethernet@fffbc000 { | 197 | macb0: ethernet@fffbc000 { |
197 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 198 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
198 | reg = <0xfffbc000 0x100>; | 199 | reg = <0xfffbc000 0x100>; |
199 | interrupts = <25 4>; | 200 | interrupts = <25 4 3>; |
200 | status = "disabled"; | 201 | status = "disabled"; |
201 | }; | 202 | }; |
202 | 203 | ||
203 | adc0: adc@fffb0000 { | 204 | adc0: adc@fffb0000 { |
204 | compatible = "atmel,at91sam9260-adc"; | 205 | compatible = "atmel,at91sam9260-adc"; |
205 | reg = <0xfffb0000 0x100>; | 206 | reg = <0xfffb0000 0x100>; |
206 | interrupts = <20 4>; | 207 | interrupts = <20 4 0>; |
207 | atmel,adc-use-external-triggers; | 208 | atmel,adc-use-external-triggers; |
208 | atmel,adc-channels-used = <0xff>; | 209 | atmel,adc-channels-used = <0xff>; |
209 | atmel,adc-vref = <3300>; | 210 | atmel,adc-vref = <3300>; |
@@ -257,14 +258,14 @@ | |||
257 | usb0: ohci@00700000 { | 258 | usb0: ohci@00700000 { |
258 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 259 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
259 | reg = <0x00700000 0x100000>; | 260 | reg = <0x00700000 0x100000>; |
260 | interrupts = <22 4>; | 261 | interrupts = <22 4 2>; |
261 | status = "disabled"; | 262 | status = "disabled"; |
262 | }; | 263 | }; |
263 | 264 | ||
264 | usb1: ehci@00800000 { | 265 | usb1: ehci@00800000 { |
265 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 266 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
266 | reg = <0x00800000 0x100000>; | 267 | reg = <0x00800000 0x100000>; |
267 | interrupts = <22 4>; | 268 | interrupts = <22 4 2>; |
268 | status = "disabled"; | 269 | status = "disabled"; |
269 | }; | 270 | }; |
270 | }; | 271 | }; |
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index cb84de791b5a..bfac0dfc332c 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi | |||
@@ -50,7 +50,7 @@ | |||
50 | ranges; | 50 | ranges; |
51 | 51 | ||
52 | aic: interrupt-controller@fffff000 { | 52 | aic: interrupt-controller@fffff000 { |
53 | #interrupt-cells = <2>; | 53 | #interrupt-cells = <3>; |
54 | compatible = "atmel,at91rm9200-aic"; | 54 | compatible = "atmel,at91rm9200-aic"; |
55 | interrupt-controller; | 55 | interrupt-controller; |
56 | reg = <0xfffff000 0x200>; | 56 | reg = <0xfffff000 0x200>; |
@@ -74,7 +74,7 @@ | |||
74 | pit: timer@fffffe30 { | 74 | pit: timer@fffffe30 { |
75 | compatible = "atmel,at91sam9260-pit"; | 75 | compatible = "atmel,at91sam9260-pit"; |
76 | reg = <0xfffffe30 0xf>; | 76 | reg = <0xfffffe30 0xf>; |
77 | interrupts = <1 4>; | 77 | interrupts = <1 4 7>; |
78 | }; | 78 | }; |
79 | 79 | ||
80 | shdwc@fffffe10 { | 80 | shdwc@fffffe10 { |
@@ -85,25 +85,25 @@ | |||
85 | tcb0: timer@f8008000 { | 85 | tcb0: timer@f8008000 { |
86 | compatible = "atmel,at91sam9x5-tcb"; | 86 | compatible = "atmel,at91sam9x5-tcb"; |
87 | reg = <0xf8008000 0x100>; | 87 | reg = <0xf8008000 0x100>; |
88 | interrupts = <17 4>; | 88 | interrupts = <17 4 0>; |
89 | }; | 89 | }; |
90 | 90 | ||
91 | tcb1: timer@f800c000 { | 91 | tcb1: timer@f800c000 { |
92 | compatible = "atmel,at91sam9x5-tcb"; | 92 | compatible = "atmel,at91sam9x5-tcb"; |
93 | reg = <0xf800c000 0x100>; | 93 | reg = <0xf800c000 0x100>; |
94 | interrupts = <17 4>; | 94 | interrupts = <17 4 0>; |
95 | }; | 95 | }; |
96 | 96 | ||
97 | dma: dma-controller@ffffec00 { | 97 | dma: dma-controller@ffffec00 { |
98 | compatible = "atmel,at91sam9g45-dma"; | 98 | compatible = "atmel,at91sam9g45-dma"; |
99 | reg = <0xffffec00 0x200>; | 99 | reg = <0xffffec00 0x200>; |
100 | interrupts = <20 4>; | 100 | interrupts = <20 4 0>; |
101 | }; | 101 | }; |
102 | 102 | ||
103 | pioA: gpio@fffff400 { | 103 | pioA: gpio@fffff400 { |
104 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 104 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
105 | reg = <0xfffff400 0x100>; | 105 | reg = <0xfffff400 0x100>; |
106 | interrupts = <2 4>; | 106 | interrupts = <2 4 1>; |
107 | #gpio-cells = <2>; | 107 | #gpio-cells = <2>; |
108 | gpio-controller; | 108 | gpio-controller; |
109 | interrupt-controller; | 109 | interrupt-controller; |
@@ -112,7 +112,7 @@ | |||
112 | pioB: gpio@fffff600 { | 112 | pioB: gpio@fffff600 { |
113 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 113 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
114 | reg = <0xfffff600 0x100>; | 114 | reg = <0xfffff600 0x100>; |
115 | interrupts = <2 4>; | 115 | interrupts = <2 4 1>; |
116 | #gpio-cells = <2>; | 116 | #gpio-cells = <2>; |
117 | gpio-controller; | 117 | gpio-controller; |
118 | interrupt-controller; | 118 | interrupt-controller; |
@@ -121,7 +121,7 @@ | |||
121 | pioC: gpio@fffff800 { | 121 | pioC: gpio@fffff800 { |
122 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 122 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
123 | reg = <0xfffff800 0x100>; | 123 | reg = <0xfffff800 0x100>; |
124 | interrupts = <3 4>; | 124 | interrupts = <3 4 1>; |
125 | #gpio-cells = <2>; | 125 | #gpio-cells = <2>; |
126 | gpio-controller; | 126 | gpio-controller; |
127 | interrupt-controller; | 127 | interrupt-controller; |
@@ -130,7 +130,7 @@ | |||
130 | pioD: gpio@fffffa00 { | 130 | pioD: gpio@fffffa00 { |
131 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 131 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
132 | reg = <0xfffffa00 0x100>; | 132 | reg = <0xfffffa00 0x100>; |
133 | interrupts = <3 4>; | 133 | interrupts = <3 4 1>; |
134 | #gpio-cells = <2>; | 134 | #gpio-cells = <2>; |
135 | gpio-controller; | 135 | gpio-controller; |
136 | interrupt-controller; | 136 | interrupt-controller; |
@@ -139,14 +139,14 @@ | |||
139 | dbgu: serial@fffff200 { | 139 | dbgu: serial@fffff200 { |
140 | compatible = "atmel,at91sam9260-usart"; | 140 | compatible = "atmel,at91sam9260-usart"; |
141 | reg = <0xfffff200 0x200>; | 141 | reg = <0xfffff200 0x200>; |
142 | interrupts = <1 4>; | 142 | interrupts = <1 4 7>; |
143 | status = "disabled"; | 143 | status = "disabled"; |
144 | }; | 144 | }; |
145 | 145 | ||
146 | usart0: serial@f801c000 { | 146 | usart0: serial@f801c000 { |
147 | compatible = "atmel,at91sam9260-usart"; | 147 | compatible = "atmel,at91sam9260-usart"; |
148 | reg = <0xf801c000 0x4000>; | 148 | reg = <0xf801c000 0x4000>; |
149 | interrupts = <5 4>; | 149 | interrupts = <5 4 5>; |
150 | atmel,use-dma-rx; | 150 | atmel,use-dma-rx; |
151 | atmel,use-dma-tx; | 151 | atmel,use-dma-tx; |
152 | status = "disabled"; | 152 | status = "disabled"; |
@@ -155,7 +155,7 @@ | |||
155 | usart1: serial@f8020000 { | 155 | usart1: serial@f8020000 { |
156 | compatible = "atmel,at91sam9260-usart"; | 156 | compatible = "atmel,at91sam9260-usart"; |
157 | reg = <0xf8020000 0x4000>; | 157 | reg = <0xf8020000 0x4000>; |
158 | interrupts = <6 4>; | 158 | interrupts = <6 4 5>; |
159 | atmel,use-dma-rx; | 159 | atmel,use-dma-rx; |
160 | atmel,use-dma-tx; | 160 | atmel,use-dma-tx; |
161 | status = "disabled"; | 161 | status = "disabled"; |
@@ -164,7 +164,7 @@ | |||
164 | usart2: serial@f8024000 { | 164 | usart2: serial@f8024000 { |
165 | compatible = "atmel,at91sam9260-usart"; | 165 | compatible = "atmel,at91sam9260-usart"; |
166 | reg = <0xf8024000 0x4000>; | 166 | reg = <0xf8024000 0x4000>; |
167 | interrupts = <7 4>; | 167 | interrupts = <7 4 5>; |
168 | atmel,use-dma-rx; | 168 | atmel,use-dma-rx; |
169 | atmel,use-dma-tx; | 169 | atmel,use-dma-tx; |
170 | status = "disabled"; | 170 | status = "disabled"; |
@@ -173,7 +173,7 @@ | |||
173 | usart3: serial@f8028000 { | 173 | usart3: serial@f8028000 { |
174 | compatible = "atmel,at91sam9260-usart"; | 174 | compatible = "atmel,at91sam9260-usart"; |
175 | reg = <0xf8028000 0x4000>; | 175 | reg = <0xf8028000 0x4000>; |
176 | interrupts = <8 4>; | 176 | interrupts = <8 4 5>; |
177 | atmel,use-dma-rx; | 177 | atmel,use-dma-rx; |
178 | atmel,use-dma-tx; | 178 | atmel,use-dma-tx; |
179 | status = "disabled"; | 179 | status = "disabled"; |
@@ -201,7 +201,7 @@ | |||
201 | usb0: ohci@00500000 { | 201 | usb0: ohci@00500000 { |
202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 202 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
203 | reg = <0x00500000 0x00100000>; | 203 | reg = <0x00500000 0x00100000>; |
204 | interrupts = <22 4>; | 204 | interrupts = <22 4 2>; |
205 | status = "disabled"; | 205 | status = "disabled"; |
206 | }; | 206 | }; |
207 | }; | 207 | }; |
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index 6b3ef4339ae7..4a18c393b136 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi | |||
@@ -51,10 +51,11 @@ | |||
51 | ranges; | 51 | ranges; |
52 | 52 | ||
53 | aic: interrupt-controller@fffff000 { | 53 | aic: interrupt-controller@fffff000 { |
54 | #interrupt-cells = <2>; | 54 | #interrupt-cells = <3>; |
55 | compatible = "atmel,at91rm9200-aic"; | 55 | compatible = "atmel,at91rm9200-aic"; |
56 | interrupt-controller; | 56 | interrupt-controller; |
57 | reg = <0xfffff000 0x200>; | 57 | reg = <0xfffff000 0x200>; |
58 | atmel,external-irqs = <31>; | ||
58 | }; | 59 | }; |
59 | 60 | ||
60 | ramc0: ramc@ffffe800 { | 61 | ramc0: ramc@ffffe800 { |
@@ -80,37 +81,37 @@ | |||
80 | pit: timer@fffffe30 { | 81 | pit: timer@fffffe30 { |
81 | compatible = "atmel,at91sam9260-pit"; | 82 | compatible = "atmel,at91sam9260-pit"; |
82 | reg = <0xfffffe30 0xf>; | 83 | reg = <0xfffffe30 0xf>; |
83 | interrupts = <1 4>; | 84 | interrupts = <1 4 7>; |
84 | }; | 85 | }; |
85 | 86 | ||
86 | tcb0: timer@f8008000 { | 87 | tcb0: timer@f8008000 { |
87 | compatible = "atmel,at91sam9x5-tcb"; | 88 | compatible = "atmel,at91sam9x5-tcb"; |
88 | reg = <0xf8008000 0x100>; | 89 | reg = <0xf8008000 0x100>; |
89 | interrupts = <17 4>; | 90 | interrupts = <17 4 0>; |
90 | }; | 91 | }; |
91 | 92 | ||
92 | tcb1: timer@f800c000 { | 93 | tcb1: timer@f800c000 { |
93 | compatible = "atmel,at91sam9x5-tcb"; | 94 | compatible = "atmel,at91sam9x5-tcb"; |
94 | reg = <0xf800c000 0x100>; | 95 | reg = <0xf800c000 0x100>; |
95 | interrupts = <17 4>; | 96 | interrupts = <17 4 0>; |
96 | }; | 97 | }; |
97 | 98 | ||
98 | dma0: dma-controller@ffffec00 { | 99 | dma0: dma-controller@ffffec00 { |
99 | compatible = "atmel,at91sam9g45-dma"; | 100 | compatible = "atmel,at91sam9g45-dma"; |
100 | reg = <0xffffec00 0x200>; | 101 | reg = <0xffffec00 0x200>; |
101 | interrupts = <20 4>; | 102 | interrupts = <20 4 0>; |
102 | }; | 103 | }; |
103 | 104 | ||
104 | dma1: dma-controller@ffffee00 { | 105 | dma1: dma-controller@ffffee00 { |
105 | compatible = "atmel,at91sam9g45-dma"; | 106 | compatible = "atmel,at91sam9g45-dma"; |
106 | reg = <0xffffee00 0x200>; | 107 | reg = <0xffffee00 0x200>; |
107 | interrupts = <21 4>; | 108 | interrupts = <21 4 0>; |
108 | }; | 109 | }; |
109 | 110 | ||
110 | pioA: gpio@fffff400 { | 111 | pioA: gpio@fffff400 { |
111 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 112 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
112 | reg = <0xfffff400 0x100>; | 113 | reg = <0xfffff400 0x100>; |
113 | interrupts = <2 4>; | 114 | interrupts = <2 4 1>; |
114 | #gpio-cells = <2>; | 115 | #gpio-cells = <2>; |
115 | gpio-controller; | 116 | gpio-controller; |
116 | interrupt-controller; | 117 | interrupt-controller; |
@@ -119,7 +120,7 @@ | |||
119 | pioB: gpio@fffff600 { | 120 | pioB: gpio@fffff600 { |
120 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 121 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
121 | reg = <0xfffff600 0x100>; | 122 | reg = <0xfffff600 0x100>; |
122 | interrupts = <2 4>; | 123 | interrupts = <2 4 1>; |
123 | #gpio-cells = <2>; | 124 | #gpio-cells = <2>; |
124 | gpio-controller; | 125 | gpio-controller; |
125 | interrupt-controller; | 126 | interrupt-controller; |
@@ -128,7 +129,7 @@ | |||
128 | pioC: gpio@fffff800 { | 129 | pioC: gpio@fffff800 { |
129 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 130 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
130 | reg = <0xfffff800 0x100>; | 131 | reg = <0xfffff800 0x100>; |
131 | interrupts = <3 4>; | 132 | interrupts = <3 4 1>; |
132 | #gpio-cells = <2>; | 133 | #gpio-cells = <2>; |
133 | gpio-controller; | 134 | gpio-controller; |
134 | interrupt-controller; | 135 | interrupt-controller; |
@@ -137,7 +138,7 @@ | |||
137 | pioD: gpio@fffffa00 { | 138 | pioD: gpio@fffffa00 { |
138 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | 139 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; |
139 | reg = <0xfffffa00 0x100>; | 140 | reg = <0xfffffa00 0x100>; |
140 | interrupts = <3 4>; | 141 | interrupts = <3 4 1>; |
141 | #gpio-cells = <2>; | 142 | #gpio-cells = <2>; |
142 | gpio-controller; | 143 | gpio-controller; |
143 | interrupt-controller; | 144 | interrupt-controller; |
@@ -146,14 +147,14 @@ | |||
146 | dbgu: serial@fffff200 { | 147 | dbgu: serial@fffff200 { |
147 | compatible = "atmel,at91sam9260-usart"; | 148 | compatible = "atmel,at91sam9260-usart"; |
148 | reg = <0xfffff200 0x200>; | 149 | reg = <0xfffff200 0x200>; |
149 | interrupts = <1 4>; | 150 | interrupts = <1 4 7>; |
150 | status = "disabled"; | 151 | status = "disabled"; |
151 | }; | 152 | }; |
152 | 153 | ||
153 | usart0: serial@f801c000 { | 154 | usart0: serial@f801c000 { |
154 | compatible = "atmel,at91sam9260-usart"; | 155 | compatible = "atmel,at91sam9260-usart"; |
155 | reg = <0xf801c000 0x200>; | 156 | reg = <0xf801c000 0x200>; |
156 | interrupts = <5 4>; | 157 | interrupts = <5 4 5>; |
157 | atmel,use-dma-rx; | 158 | atmel,use-dma-rx; |
158 | atmel,use-dma-tx; | 159 | atmel,use-dma-tx; |
159 | status = "disabled"; | 160 | status = "disabled"; |
@@ -162,7 +163,7 @@ | |||
162 | usart1: serial@f8020000 { | 163 | usart1: serial@f8020000 { |
163 | compatible = "atmel,at91sam9260-usart"; | 164 | compatible = "atmel,at91sam9260-usart"; |
164 | reg = <0xf8020000 0x200>; | 165 | reg = <0xf8020000 0x200>; |
165 | interrupts = <6 4>; | 166 | interrupts = <6 4 5>; |
166 | atmel,use-dma-rx; | 167 | atmel,use-dma-rx; |
167 | atmel,use-dma-tx; | 168 | atmel,use-dma-tx; |
168 | status = "disabled"; | 169 | status = "disabled"; |
@@ -171,7 +172,7 @@ | |||
171 | usart2: serial@f8024000 { | 172 | usart2: serial@f8024000 { |
172 | compatible = "atmel,at91sam9260-usart"; | 173 | compatible = "atmel,at91sam9260-usart"; |
173 | reg = <0xf8024000 0x200>; | 174 | reg = <0xf8024000 0x200>; |
174 | interrupts = <7 4>; | 175 | interrupts = <7 4 5>; |
175 | atmel,use-dma-rx; | 176 | atmel,use-dma-rx; |
176 | atmel,use-dma-tx; | 177 | atmel,use-dma-tx; |
177 | status = "disabled"; | 178 | status = "disabled"; |
@@ -180,21 +181,21 @@ | |||
180 | macb0: ethernet@f802c000 { | 181 | macb0: ethernet@f802c000 { |
181 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 182 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
182 | reg = <0xf802c000 0x100>; | 183 | reg = <0xf802c000 0x100>; |
183 | interrupts = <24 4>; | 184 | interrupts = <24 4 3>; |
184 | status = "disabled"; | 185 | status = "disabled"; |
185 | }; | 186 | }; |
186 | 187 | ||
187 | macb1: ethernet@f8030000 { | 188 | macb1: ethernet@f8030000 { |
188 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 189 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
189 | reg = <0xf8030000 0x100>; | 190 | reg = <0xf8030000 0x100>; |
190 | interrupts = <27 4>; | 191 | interrupts = <27 4 3>; |
191 | status = "disabled"; | 192 | status = "disabled"; |
192 | }; | 193 | }; |
193 | 194 | ||
194 | adc0: adc@f804c000 { | 195 | adc0: adc@f804c000 { |
195 | compatible = "atmel,at91sam9260-adc"; | 196 | compatible = "atmel,at91sam9260-adc"; |
196 | reg = <0xf804c000 0x100>; | 197 | reg = <0xf804c000 0x100>; |
197 | interrupts = <19 4>; | 198 | interrupts = <19 4 0>; |
198 | atmel,adc-use-external; | 199 | atmel,adc-use-external; |
199 | atmel,adc-channels-used = <0xffff>; | 200 | atmel,adc-channels-used = <0xffff>; |
200 | atmel,adc-vref = <3300>; | 201 | atmel,adc-vref = <3300>; |
@@ -248,14 +249,14 @@ | |||
248 | usb0: ohci@00600000 { | 249 | usb0: ohci@00600000 { |
249 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 250 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
250 | reg = <0x00600000 0x100000>; | 251 | reg = <0x00600000 0x100000>; |
251 | interrupts = <22 4>; | 252 | interrupts = <22 4 2>; |
252 | status = "disabled"; | 253 | status = "disabled"; |
253 | }; | 254 | }; |
254 | 255 | ||
255 | usb1: ehci@00700000 { | 256 | usb1: ehci@00700000 { |
256 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 257 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
257 | reg = <0x00700000 0x100000>; | 258 | reg = <0x00700000 0x100000>; |
258 | interrupts = <22 4>; | 259 | interrupts = <22 4 2>; |
259 | status = "disabled"; | 260 | status = "disabled"; |
260 | }; | 261 | }; |
261 | }; | 262 | }; |
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi index 4ad5160018cb..3180a9c588b9 100644 --- a/arch/arm/boot/dts/db8500.dtsi +++ b/arch/arm/boot/dts/db8500.dtsi | |||
@@ -48,7 +48,7 @@ | |||
48 | }; | 48 | }; |
49 | 49 | ||
50 | rtc@80154000 { | 50 | rtc@80154000 { |
51 | compatible = "stericsson,db8500-rtc"; | 51 | compatible = "arm,rtc-pl031", "arm,primecell"; |
52 | reg = <0x80154000 0x1000>; | 52 | reg = <0x80154000 0x1000>; |
53 | interrupts = <0 18 0x4>; | 53 | interrupts = <0 18 0x4>; |
54 | }; | 54 | }; |
@@ -60,7 +60,7 @@ | |||
60 | interrupts = <0 119 0x4>; | 60 | interrupts = <0 119 0x4>; |
61 | interrupt-controller; | 61 | interrupt-controller; |
62 | #interrupt-cells = <2>; | 62 | #interrupt-cells = <2>; |
63 | supports-sleepmode; | 63 | st,supports-sleepmode; |
64 | gpio-controller; | 64 | gpio-controller; |
65 | #gpio-cells = <2>; | 65 | #gpio-cells = <2>; |
66 | gpio-bank = <0>; | 66 | gpio-bank = <0>; |
@@ -73,7 +73,7 @@ | |||
73 | interrupts = <0 120 0x4>; | 73 | interrupts = <0 120 0x4>; |
74 | interrupt-controller; | 74 | interrupt-controller; |
75 | #interrupt-cells = <2>; | 75 | #interrupt-cells = <2>; |
76 | supports-sleepmode; | 76 | st,supports-sleepmode; |
77 | gpio-controller; | 77 | gpio-controller; |
78 | #gpio-cells = <2>; | 78 | #gpio-cells = <2>; |
79 | gpio-bank = <1>; | 79 | gpio-bank = <1>; |
@@ -86,7 +86,7 @@ | |||
86 | interrupts = <0 121 0x4>; | 86 | interrupts = <0 121 0x4>; |
87 | interrupt-controller; | 87 | interrupt-controller; |
88 | #interrupt-cells = <2>; | 88 | #interrupt-cells = <2>; |
89 | supports-sleepmode; | 89 | st,supports-sleepmode; |
90 | gpio-controller; | 90 | gpio-controller; |
91 | #gpio-cells = <2>; | 91 | #gpio-cells = <2>; |
92 | gpio-bank = <2>; | 92 | gpio-bank = <2>; |
@@ -99,7 +99,7 @@ | |||
99 | interrupts = <0 122 0x4>; | 99 | interrupts = <0 122 0x4>; |
100 | interrupt-controller; | 100 | interrupt-controller; |
101 | #interrupt-cells = <2>; | 101 | #interrupt-cells = <2>; |
102 | supports-sleepmode; | 102 | st,supports-sleepmode; |
103 | gpio-controller; | 103 | gpio-controller; |
104 | #gpio-cells = <2>; | 104 | #gpio-cells = <2>; |
105 | gpio-bank = <3>; | 105 | gpio-bank = <3>; |
@@ -112,7 +112,7 @@ | |||
112 | interrupts = <0 123 0x4>; | 112 | interrupts = <0 123 0x4>; |
113 | interrupt-controller; | 113 | interrupt-controller; |
114 | #interrupt-cells = <2>; | 114 | #interrupt-cells = <2>; |
115 | supports-sleepmode; | 115 | st,supports-sleepmode; |
116 | gpio-controller; | 116 | gpio-controller; |
117 | #gpio-cells = <2>; | 117 | #gpio-cells = <2>; |
118 | gpio-bank = <4>; | 118 | gpio-bank = <4>; |
@@ -125,7 +125,7 @@ | |||
125 | interrupts = <0 124 0x4>; | 125 | interrupts = <0 124 0x4>; |
126 | interrupt-controller; | 126 | interrupt-controller; |
127 | #interrupt-cells = <2>; | 127 | #interrupt-cells = <2>; |
128 | supports-sleepmode; | 128 | st,supports-sleepmode; |
129 | gpio-controller; | 129 | gpio-controller; |
130 | #gpio-cells = <2>; | 130 | #gpio-cells = <2>; |
131 | gpio-bank = <5>; | 131 | gpio-bank = <5>; |
@@ -138,7 +138,7 @@ | |||
138 | interrupts = <0 125 0x4>; | 138 | interrupts = <0 125 0x4>; |
139 | interrupt-controller; | 139 | interrupt-controller; |
140 | #interrupt-cells = <2>; | 140 | #interrupt-cells = <2>; |
141 | supports-sleepmode; | 141 | st,supports-sleepmode; |
142 | gpio-controller; | 142 | gpio-controller; |
143 | #gpio-cells = <2>; | 143 | #gpio-cells = <2>; |
144 | gpio-bank = <6>; | 144 | gpio-bank = <6>; |
@@ -151,7 +151,7 @@ | |||
151 | interrupts = <0 126 0x4>; | 151 | interrupts = <0 126 0x4>; |
152 | interrupt-controller; | 152 | interrupt-controller; |
153 | #interrupt-cells = <2>; | 153 | #interrupt-cells = <2>; |
154 | supports-sleepmode; | 154 | st,supports-sleepmode; |
155 | gpio-controller; | 155 | gpio-controller; |
156 | #gpio-cells = <2>; | 156 | #gpio-cells = <2>; |
157 | gpio-bank = <7>; | 157 | gpio-bank = <7>; |
@@ -164,7 +164,7 @@ | |||
164 | interrupts = <0 127 0x4>; | 164 | interrupts = <0 127 0x4>; |
165 | interrupt-controller; | 165 | interrupt-controller; |
166 | #interrupt-cells = <2>; | 166 | #interrupt-cells = <2>; |
167 | supports-sleepmode; | 167 | st,supports-sleepmode; |
168 | gpio-controller; | 168 | gpio-controller; |
169 | #gpio-cells = <2>; | 169 | #gpio-cells = <2>; |
170 | gpio-bank = <8>; | 170 | gpio-bank = <8>; |
@@ -206,62 +206,74 @@ | |||
206 | 206 | ||
207 | // DB8500_REGULATOR_VAPE | 207 | // DB8500_REGULATOR_VAPE |
208 | db8500_vape_reg: db8500_vape { | 208 | db8500_vape_reg: db8500_vape { |
209 | regulator-compatible = "db8500_vape"; | ||
209 | regulator-name = "db8500-vape"; | 210 | regulator-name = "db8500-vape"; |
210 | regulator-always-on; | 211 | regulator-always-on; |
211 | }; | 212 | }; |
212 | 213 | ||
213 | // DB8500_REGULATOR_VARM | 214 | // DB8500_REGULATOR_VARM |
214 | db8500_varm_reg: db8500_varm { | 215 | db8500_varm_reg: db8500_varm { |
216 | regulator-compatible = "db8500_varm"; | ||
215 | regulator-name = "db8500-varm"; | 217 | regulator-name = "db8500-varm"; |
216 | }; | 218 | }; |
217 | 219 | ||
218 | // DB8500_REGULATOR_VMODEM | 220 | // DB8500_REGULATOR_VMODEM |
219 | db8500_vmodem_reg: db8500_vmodem { | 221 | db8500_vmodem_reg: db8500_vmodem { |
222 | regulator-compatible = "db8500_vmodem"; | ||
220 | regulator-name = "db8500-vmodem"; | 223 | regulator-name = "db8500-vmodem"; |
221 | }; | 224 | }; |
222 | 225 | ||
223 | // DB8500_REGULATOR_VPLL | 226 | // DB8500_REGULATOR_VPLL |
224 | db8500_vpll_reg: db8500_vpll { | 227 | db8500_vpll_reg: db8500_vpll { |
228 | regulator-compatible = "db8500_vpll"; | ||
225 | regulator-name = "db8500-vpll"; | 229 | regulator-name = "db8500-vpll"; |
226 | }; | 230 | }; |
227 | 231 | ||
228 | // DB8500_REGULATOR_VSMPS1 | 232 | // DB8500_REGULATOR_VSMPS1 |
229 | db8500_vsmps1_reg: db8500_vsmps1 { | 233 | db8500_vsmps1_reg: db8500_vsmps1 { |
234 | regulator-compatible = "db8500_vsmps1"; | ||
230 | regulator-name = "db8500-vsmps1"; | 235 | regulator-name = "db8500-vsmps1"; |
231 | }; | 236 | }; |
232 | 237 | ||
233 | // DB8500_REGULATOR_VSMPS2 | 238 | // DB8500_REGULATOR_VSMPS2 |
234 | db8500_vsmps2_reg: db8500_vsmps2 { | 239 | db8500_vsmps2_reg: db8500_vsmps2 { |
240 | regulator-compatible = "db8500_vsmps2"; | ||
235 | regulator-name = "db8500-vsmps2"; | 241 | regulator-name = "db8500-vsmps2"; |
236 | }; | 242 | }; |
237 | 243 | ||
238 | // DB8500_REGULATOR_VSMPS3 | 244 | // DB8500_REGULATOR_VSMPS3 |
239 | db8500_vsmps3_reg: db8500_vsmps3 { | 245 | db8500_vsmps3_reg: db8500_vsmps3 { |
246 | regulator-compatible = "db8500_vsmps3"; | ||
240 | regulator-name = "db8500-vsmps3"; | 247 | regulator-name = "db8500-vsmps3"; |
241 | }; | 248 | }; |
242 | 249 | ||
243 | // DB8500_REGULATOR_VRF1 | 250 | // DB8500_REGULATOR_VRF1 |
244 | db8500_vrf1_reg: db8500_vrf1 { | 251 | db8500_vrf1_reg: db8500_vrf1 { |
252 | regulator-compatible = "db8500_vrf1"; | ||
245 | regulator-name = "db8500-vrf1"; | 253 | regulator-name = "db8500-vrf1"; |
246 | }; | 254 | }; |
247 | 255 | ||
248 | // DB8500_REGULATOR_SWITCH_SVAMMDSP | 256 | // DB8500_REGULATOR_SWITCH_SVAMMDSP |
249 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { | 257 | db8500_sva_mmdsp_reg: db8500_sva_mmdsp { |
258 | regulator-compatible = "db8500_sva_mmdsp"; | ||
250 | regulator-name = "db8500-sva-mmdsp"; | 259 | regulator-name = "db8500-sva-mmdsp"; |
251 | }; | 260 | }; |
252 | 261 | ||
253 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET | 262 | // DB8500_REGULATOR_SWITCH_SVAMMDSPRET |
254 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { | 263 | db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret { |
264 | regulator-compatible = "db8500_sva_mmdsp_ret"; | ||
255 | regulator-name = "db8500-sva-mmdsp-ret"; | 265 | regulator-name = "db8500-sva-mmdsp-ret"; |
256 | }; | 266 | }; |
257 | 267 | ||
258 | // DB8500_REGULATOR_SWITCH_SVAPIPE | 268 | // DB8500_REGULATOR_SWITCH_SVAPIPE |
259 | db8500_sva_pipe_reg: db8500_sva_pipe { | 269 | db8500_sva_pipe_reg: db8500_sva_pipe { |
270 | regulator-compatible = "db8500_sva_pipe"; | ||
260 | regulator-name = "db8500_sva_pipe"; | 271 | regulator-name = "db8500_sva_pipe"; |
261 | }; | 272 | }; |
262 | 273 | ||
263 | // DB8500_REGULATOR_SWITCH_SIAMMDSP | 274 | // DB8500_REGULATOR_SWITCH_SIAMMDSP |
264 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { | 275 | db8500_sia_mmdsp_reg: db8500_sia_mmdsp { |
276 | regulator-compatible = "db8500_sia_mmdsp"; | ||
265 | regulator-name = "db8500_sia_mmdsp"; | 277 | regulator-name = "db8500_sia_mmdsp"; |
266 | }; | 278 | }; |
267 | 279 | ||
@@ -272,38 +284,45 @@ | |||
272 | 284 | ||
273 | // DB8500_REGULATOR_SWITCH_SIAPIPE | 285 | // DB8500_REGULATOR_SWITCH_SIAPIPE |
274 | db8500_sia_pipe_reg: db8500_sia_pipe { | 286 | db8500_sia_pipe_reg: db8500_sia_pipe { |
287 | regulator-compatible = "db8500_sia_pipe"; | ||
275 | regulator-name = "db8500-sia-pipe"; | 288 | regulator-name = "db8500-sia-pipe"; |
276 | }; | 289 | }; |
277 | 290 | ||
278 | // DB8500_REGULATOR_SWITCH_SGA | 291 | // DB8500_REGULATOR_SWITCH_SGA |
279 | db8500_sga_reg: db8500_sga { | 292 | db8500_sga_reg: db8500_sga { |
293 | regulator-compatible = "db8500_sga"; | ||
280 | regulator-name = "db8500-sga"; | 294 | regulator-name = "db8500-sga"; |
281 | vin-supply = <&db8500_vape_reg>; | 295 | vin-supply = <&db8500_vape_reg>; |
282 | }; | 296 | }; |
283 | 297 | ||
284 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE | 298 | // DB8500_REGULATOR_SWITCH_B2R2_MCDE |
285 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { | 299 | db8500_b2r2_mcde_reg: db8500_b2r2_mcde { |
300 | regulator-compatible = "db8500_b2r2_mcde"; | ||
286 | regulator-name = "db8500-b2r2-mcde"; | 301 | regulator-name = "db8500-b2r2-mcde"; |
287 | vin-supply = <&db8500_vape_reg>; | 302 | vin-supply = <&db8500_vape_reg>; |
288 | }; | 303 | }; |
289 | 304 | ||
290 | // DB8500_REGULATOR_SWITCH_ESRAM12 | 305 | // DB8500_REGULATOR_SWITCH_ESRAM12 |
291 | db8500_esram12_reg: db8500_esram12 { | 306 | db8500_esram12_reg: db8500_esram12 { |
307 | regulator-compatible = "db8500_esram12"; | ||
292 | regulator-name = "db8500-esram12"; | 308 | regulator-name = "db8500-esram12"; |
293 | }; | 309 | }; |
294 | 310 | ||
295 | // DB8500_REGULATOR_SWITCH_ESRAM12RET | 311 | // DB8500_REGULATOR_SWITCH_ESRAM12RET |
296 | db8500_esram12_ret_reg: db8500_esram12_ret { | 312 | db8500_esram12_ret_reg: db8500_esram12_ret { |
313 | regulator-compatible = "db8500_esram12_ret"; | ||
297 | regulator-name = "db8500-esram12-ret"; | 314 | regulator-name = "db8500-esram12-ret"; |
298 | }; | 315 | }; |
299 | 316 | ||
300 | // DB8500_REGULATOR_SWITCH_ESRAM34 | 317 | // DB8500_REGULATOR_SWITCH_ESRAM34 |
301 | db8500_esram34_reg: db8500_esram34 { | 318 | db8500_esram34_reg: db8500_esram34 { |
319 | regulator-compatible = "db8500_esram34"; | ||
302 | regulator-name = "db8500-esram34"; | 320 | regulator-name = "db8500-esram34"; |
303 | }; | 321 | }; |
304 | 322 | ||
305 | // DB8500_REGULATOR_SWITCH_ESRAM34RET | 323 | // DB8500_REGULATOR_SWITCH_ESRAM34RET |
306 | db8500_esram34_ret_reg: db8500_esram34_ret { | 324 | db8500_esram34_ret_reg: db8500_esram34_ret { |
325 | regulator-compatible = "db8500_esram34_ret"; | ||
307 | regulator-name = "db8500-esram34-ret"; | 326 | regulator-name = "db8500-esram34-ret"; |
308 | }; | 327 | }; |
309 | }; | 328 | }; |
@@ -312,12 +331,70 @@ | |||
312 | compatible = "stericsson,ab8500"; | 331 | compatible = "stericsson,ab8500"; |
313 | reg = <5>; /* mailbox 5 is i2c */ | 332 | reg = <5>; /* mailbox 5 is i2c */ |
314 | interrupts = <0 40 0x4>; | 333 | interrupts = <0 40 0x4>; |
334 | interrupt-controller; | ||
335 | #interrupt-cells = <2>; | ||
336 | |||
337 | ab8500-rtc { | ||
338 | compatible = "stericsson,ab8500-rtc"; | ||
339 | interrupts = <17 0x4 | ||
340 | 18 0x4>; | ||
341 | interrupt-names = "60S", "ALARM"; | ||
342 | }; | ||
343 | |||
344 | ab8500-gpadc { | ||
345 | compatible = "stericsson,ab8500-gpadc"; | ||
346 | interrupts = <32 0x4 | ||
347 | 39 0x4>; | ||
348 | interrupt-names = "HW_CONV_END", "SW_CONV_END"; | ||
349 | vddadc-supply = <&ab8500_ldo_tvout_reg>; | ||
350 | }; | ||
351 | |||
352 | ab8500-usb { | ||
353 | compatible = "stericsson,ab8500-usb"; | ||
354 | interrupts = < 90 0x4 | ||
355 | 96 0x4 | ||
356 | 14 0x4 | ||
357 | 15 0x4 | ||
358 | 79 0x4 | ||
359 | 74 0x4 | ||
360 | 75 0x4>; | ||
361 | interrupt-names = "ID_WAKEUP_R", | ||
362 | "ID_WAKEUP_F", | ||
363 | "VBUS_DET_F", | ||
364 | "VBUS_DET_R", | ||
365 | "USB_LINK_STATUS", | ||
366 | "USB_ADP_PROBE_PLUG", | ||
367 | "USB_ADP_PROBE_UNPLUG"; | ||
368 | vddulpivio18-supply = <&ab8500_ldo_initcore_reg>; | ||
369 | v-ape-supply = <&db8500_vape_reg>; | ||
370 | musb_1v8-supply = <&db8500_vsmps2_reg>; | ||
371 | }; | ||
372 | |||
373 | ab8500-ponkey { | ||
374 | compatible = "stericsson,ab8500-ponkey"; | ||
375 | interrupts = <6 0x4 | ||
376 | 7 0x4>; | ||
377 | interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; | ||
378 | }; | ||
379 | |||
380 | ab8500-sysctrl { | ||
381 | compatible = "stericsson,ab8500-sysctrl"; | ||
382 | }; | ||
383 | |||
384 | ab8500-pwm { | ||
385 | compatible = "stericsson,ab8500-pwm"; | ||
386 | }; | ||
387 | |||
388 | ab8500-debugfs { | ||
389 | compatible = "stericsson,ab8500-debug"; | ||
390 | }; | ||
315 | 391 | ||
316 | ab8500-regulators { | 392 | ab8500-regulators { |
317 | compatible = "stericsson,ab8500-regulator"; | 393 | compatible = "stericsson,ab8500-regulator"; |
318 | 394 | ||
319 | // supplies to the display/camera | 395 | // supplies to the display/camera |
320 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { | 396 | ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { |
397 | regulator-compatible = "ab8500_ldo_aux1"; | ||
321 | regulator-name = "V-DISPLAY"; | 398 | regulator-name = "V-DISPLAY"; |
322 | regulator-min-microvolt = <2500000>; | 399 | regulator-min-microvolt = <2500000>; |
323 | regulator-max-microvolt = <2900000>; | 400 | regulator-max-microvolt = <2900000>; |
@@ -328,6 +405,7 @@ | |||
328 | 405 | ||
329 | // supplies to the on-board eMMC | 406 | // supplies to the on-board eMMC |
330 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { | 407 | ab8500_ldo_aux2_reg: ab8500_ldo_aux2 { |
408 | regulator-compatible = "ab8500_ldo_aux2"; | ||
331 | regulator-name = "V-eMMC1"; | 409 | regulator-name = "V-eMMC1"; |
332 | regulator-min-microvolt = <1100000>; | 410 | regulator-min-microvolt = <1100000>; |
333 | regulator-max-microvolt = <3300000>; | 411 | regulator-max-microvolt = <3300000>; |
@@ -335,6 +413,7 @@ | |||
335 | 413 | ||
336 | // supply for VAUX3; SDcard slots | 414 | // supply for VAUX3; SDcard slots |
337 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { | 415 | ab8500_ldo_aux3_reg: ab8500_ldo_aux3 { |
416 | regulator-compatible = "ab8500_ldo_aux3"; | ||
338 | regulator-name = "V-MMC-SD"; | 417 | regulator-name = "V-MMC-SD"; |
339 | regulator-min-microvolt = <1100000>; | 418 | regulator-min-microvolt = <1100000>; |
340 | regulator-max-microvolt = <3300000>; | 419 | regulator-max-microvolt = <3300000>; |
@@ -342,41 +421,49 @@ | |||
342 | 421 | ||
343 | // supply for v-intcore12; VINTCORE12 LDO | 422 | // supply for v-intcore12; VINTCORE12 LDO |
344 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { | 423 | ab8500_ldo_initcore_reg: ab8500_ldo_initcore { |
424 | regulator-compatible = "ab8500_ldo_initcore"; | ||
345 | regulator-name = "V-INTCORE"; | 425 | regulator-name = "V-INTCORE"; |
346 | }; | 426 | }; |
347 | 427 | ||
348 | // supply for tvout; gpadc; TVOUT LDO | 428 | // supply for tvout; gpadc; TVOUT LDO |
349 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { | 429 | ab8500_ldo_tvout_reg: ab8500_ldo_tvout { |
430 | regulator-compatible = "ab8500_ldo_tvout"; | ||
350 | regulator-name = "V-TVOUT"; | 431 | regulator-name = "V-TVOUT"; |
351 | }; | 432 | }; |
352 | 433 | ||
353 | // supply for ab8500-usb; USB LDO | 434 | // supply for ab8500-usb; USB LDO |
354 | ab8500_ldo_usb_reg: ab8500_ldo_usb { | 435 | ab8500_ldo_usb_reg: ab8500_ldo_usb { |
436 | regulator-compatible = "ab8500_ldo_usb"; | ||
355 | regulator-name = "dummy"; | 437 | regulator-name = "dummy"; |
356 | }; | 438 | }; |
357 | 439 | ||
358 | // supply for ab8500-vaudio; VAUDIO LDO | 440 | // supply for ab8500-vaudio; VAUDIO LDO |
359 | ab8500_ldo_audio_reg: ab8500_ldo_audio { | 441 | ab8500_ldo_audio_reg: ab8500_ldo_audio { |
442 | regulator-compatible = "ab8500_ldo_audio"; | ||
360 | regulator-name = "V-AUD"; | 443 | regulator-name = "V-AUD"; |
361 | }; | 444 | }; |
362 | 445 | ||
363 | // supply for v-anamic1 VAMic1-LDO | 446 | // supply for v-anamic1 VAMic1-LDO |
364 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { | 447 | ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 { |
448 | regulator-compatible = "ab8500_ldo_anamic1"; | ||
365 | regulator-name = "V-AMIC1"; | 449 | regulator-name = "V-AMIC1"; |
366 | }; | 450 | }; |
367 | 451 | ||
368 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 | 452 | // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1 |
369 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { | 453 | ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 { |
454 | regulator-compatible = "ab8500_ldo_amamic2"; | ||
370 | regulator-name = "V-AMIC2"; | 455 | regulator-name = "V-AMIC2"; |
371 | }; | 456 | }; |
372 | 457 | ||
373 | // supply for v-dmic; VDMIC LDO | 458 | // supply for v-dmic; VDMIC LDO |
374 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { | 459 | ab8500_ldo_dmic_reg: ab8500_ldo_dmic { |
460 | regulator-compatible = "ab8500_ldo_dmic"; | ||
375 | regulator-name = "V-DMIC"; | 461 | regulator-name = "V-DMIC"; |
376 | }; | 462 | }; |
377 | 463 | ||
378 | // supply for U8500 CSI/DSI; VANA LDO | 464 | // supply for U8500 CSI/DSI; VANA LDO |
379 | ab8500_ldo_ana_reg: ab8500_ldo_ana { | 465 | ab8500_ldo_ana_reg: ab8500_ldo_ana { |
466 | regulator-compatible = "ab8500_ldo_ana"; | ||
380 | regulator-name = "V-CSI/DSI"; | 467 | regulator-name = "V-CSI/DSI"; |
381 | }; | 468 | }; |
382 | }; | 469 | }; |
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts new file mode 100644 index 000000000000..d79b28d9c963 --- /dev/null +++ b/arch/arm/boot/dts/ea3250.dts | |||
@@ -0,0 +1,174 @@ | |||
1 | /* | ||
2 | * Embedded Artists LPC3250 board | ||
3 | * | ||
4 | * Copyright 2012 Roland Stigge <stigge@antcom.de> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /dts-v1/; | ||
15 | /include/ "lpc32xx.dtsi" | ||
16 | |||
17 | / { | ||
18 | model = "Embedded Artists LPC3250 board based on NXP LPC3250"; | ||
19 | compatible = "ea,ea3250", "nxp,lpc3250"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | |||
23 | memory { | ||
24 | device_type = "memory"; | ||
25 | reg = <0 0x4000000>; | ||
26 | }; | ||
27 | |||
28 | ahb { | ||
29 | mac: ethernet@31060000 { | ||
30 | phy-mode = "rmii"; | ||
31 | use-iram; | ||
32 | }; | ||
33 | |||
34 | /* Here, choose exactly one from: ohci, usbd */ | ||
35 | ohci@31020000 { | ||
36 | transceiver = <&isp1301>; | ||
37 | status = "okay"; | ||
38 | }; | ||
39 | |||
40 | /* | ||
41 | usbd@31020000 { | ||
42 | transceiver = <&isp1301>; | ||
43 | status = "okay"; | ||
44 | }; | ||
45 | */ | ||
46 | |||
47 | /* 128MB Flash via SLC NAND controller */ | ||
48 | slc: flash@20020000 { | ||
49 | status = "okay"; | ||
50 | #address-cells = <1>; | ||
51 | #size-cells = <1>; | ||
52 | |||
53 | nxp,wdr-clks = <14>; | ||
54 | nxp,wwidth = <260000000>; | ||
55 | nxp,whold = <104000000>; | ||
56 | nxp,wsetup = <200000000>; | ||
57 | nxp,rdr-clks = <14>; | ||
58 | nxp,rwidth = <34666666>; | ||
59 | nxp,rhold = <104000000>; | ||
60 | nxp,rsetup = <200000000>; | ||
61 | nand-on-flash-bbt; | ||
62 | gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | ||
63 | |||
64 | mtd0@00000000 { | ||
65 | label = "ea3250-boot"; | ||
66 | reg = <0x00000000 0x00080000>; | ||
67 | read-only; | ||
68 | }; | ||
69 | |||
70 | mtd1@00080000 { | ||
71 | label = "ea3250-uboot"; | ||
72 | reg = <0x00080000 0x000c0000>; | ||
73 | read-only; | ||
74 | }; | ||
75 | |||
76 | mtd2@00140000 { | ||
77 | label = "ea3250-kernel"; | ||
78 | reg = <0x00140000 0x00400000>; | ||
79 | }; | ||
80 | |||
81 | mtd3@00540000 { | ||
82 | label = "ea3250-rootfs"; | ||
83 | reg = <0x00540000 0x07ac0000>; | ||
84 | }; | ||
85 | }; | ||
86 | |||
87 | apb { | ||
88 | uart5: serial@40090000 { | ||
89 | status = "okay"; | ||
90 | }; | ||
91 | |||
92 | uart3: serial@40080000 { | ||
93 | status = "okay"; | ||
94 | }; | ||
95 | |||
96 | uart6: serial@40098000 { | ||
97 | status = "okay"; | ||
98 | }; | ||
99 | |||
100 | i2c1: i2c@400A0000 { | ||
101 | clock-frequency = <100000>; | ||
102 | |||
103 | eeprom@50 { | ||
104 | compatible = "at,24c256"; | ||
105 | reg = <0x50>; | ||
106 | }; | ||
107 | |||
108 | eeprom@57 { | ||
109 | compatible = "at,24c64"; | ||
110 | reg = <0x57>; | ||
111 | }; | ||
112 | |||
113 | uda1380: uda1380@18 { | ||
114 | compatible = "nxp,uda1380"; | ||
115 | reg = <0x18>; | ||
116 | power-gpio = <&gpio 0x59 0>; | ||
117 | reset-gpio = <&gpio 0x51 0>; | ||
118 | dac-clk = "wspll"; | ||
119 | }; | ||
120 | |||
121 | pca9532: pca9532@60 { | ||
122 | compatible = "nxp,pca9532"; | ||
123 | gpio-controller; | ||
124 | #gpio-cells = <2>; | ||
125 | reg = <0x60>; | ||
126 | }; | ||
127 | }; | ||
128 | |||
129 | i2c2: i2c@400A8000 { | ||
130 | clock-frequency = <100000>; | ||
131 | }; | ||
132 | |||
133 | i2cusb: i2c@31020300 { | ||
134 | clock-frequency = <100000>; | ||
135 | |||
136 | isp1301: usb-transceiver@2d { | ||
137 | compatible = "nxp,isp1301"; | ||
138 | reg = <0x2d>; | ||
139 | }; | ||
140 | }; | ||
141 | |||
142 | sd@20098000 { | ||
143 | wp-gpios = <&pca9532 5 0>; | ||
144 | cd-gpios = <&pca9532 4 0>; | ||
145 | cd-inverted; | ||
146 | bus-width = <4>; | ||
147 | status = "okay"; | ||
148 | }; | ||
149 | }; | ||
150 | |||
151 | fab { | ||
152 | uart1: serial@40014000 { | ||
153 | status = "okay"; | ||
154 | }; | ||
155 | |||
156 | /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ | ||
157 | adc@40048000 { | ||
158 | status = "okay"; | ||
159 | }; | ||
160 | }; | ||
161 | }; | ||
162 | |||
163 | gpio_keys { | ||
164 | compatible = "gpio-keys"; | ||
165 | #address-cells = <1>; | ||
166 | #size-cells = <0>; | ||
167 | autorepeat; | ||
168 | button@21 { | ||
169 | label = "GPIO Key UP"; | ||
170 | linux,code = <103>; | ||
171 | gpios = <&gpio 4 1 0>; /* GPI_P3 1 */ | ||
172 | }; | ||
173 | }; | ||
174 | }; | ||
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts new file mode 100644 index 000000000000..b7354e6506de --- /dev/null +++ b/arch/arm/boot/dts/evk-pro3.dts | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3 | ||
3 | * | ||
4 | * Copyright (C) 2012 Telit, | ||
5 | * 2012 Fabio Porcedda <fabio.porcedda@gmail.com> | ||
6 | * | ||
7 | * Licensed under GPLv2 or later. | ||
8 | */ | ||
9 | |||
10 | /dts-v1/; | ||
11 | |||
12 | /include/ "ge863-pro3.dtsi" | ||
13 | |||
14 | / { | ||
15 | model = "Telit EVK-PRO3 for Telit GE863-PRO3"; | ||
16 | compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; | ||
17 | |||
18 | ahb { | ||
19 | apb { | ||
20 | macb0: ethernet@fffc4000 { | ||
21 | phy-mode = "rmii"; | ||
22 | status = "okay"; | ||
23 | }; | ||
24 | |||
25 | usb1: gadget@fffa4000 { | ||
26 | atmel,vbus-gpio = <&pioC 5 0>; | ||
27 | status = "okay"; | ||
28 | }; | ||
29 | }; | ||
30 | |||
31 | usb0: ohci@00500000 { | ||
32 | num-ports = <2>; | ||
33 | status = "okay"; | ||
34 | }; | ||
35 | }; | ||
36 | |||
37 | i2c@0 { | ||
38 | status = "okay"; | ||
39 | }; | ||
40 | |||
41 | }; \ No newline at end of file | ||
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index b8c476384eef..0c49caa09978 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts | |||
@@ -134,4 +134,16 @@ | |||
134 | i2c@138D0000 { | 134 | i2c@138D0000 { |
135 | status = "disabled"; | 135 | status = "disabled"; |
136 | }; | 136 | }; |
137 | |||
138 | spi_0: spi@13920000 { | ||
139 | status = "disabled"; | ||
140 | }; | ||
141 | |||
142 | spi_1: spi@13930000 { | ||
143 | status = "disabled"; | ||
144 | }; | ||
145 | |||
146 | spi_2: spi@13940000 { | ||
147 | status = "disabled"; | ||
148 | }; | ||
137 | }; | 149 | }; |
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 27afc8e535ca..1beccc8f14ff 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts | |||
@@ -179,4 +179,42 @@ | |||
179 | i2c@138D0000 { | 179 | i2c@138D0000 { |
180 | status = "disabled"; | 180 | status = "disabled"; |
181 | }; | 181 | }; |
182 | |||
183 | spi_0: spi@13920000 { | ||
184 | status = "disabled"; | ||
185 | }; | ||
186 | |||
187 | spi_1: spi@13930000 { | ||
188 | status = "disabled"; | ||
189 | }; | ||
190 | |||
191 | spi_2: spi@13940000 { | ||
192 | gpios = <&gpc1 1 5 3 0>, | ||
193 | <&gpc1 3 5 3 0>, | ||
194 | <&gpc1 4 5 3 0>; | ||
195 | |||
196 | w25x80@0 { | ||
197 | #address-cells = <1>; | ||
198 | #size-cells = <1>; | ||
199 | compatible = "w25x80"; | ||
200 | reg = <0>; | ||
201 | spi-max-frequency = <1000000>; | ||
202 | |||
203 | controller-data { | ||
204 | cs-gpio = <&gpc1 2 1 0 3>; | ||
205 | samsung,spi-feedback-delay = <0>; | ||
206 | }; | ||
207 | |||
208 | partition@0 { | ||
209 | label = "U-Boot"; | ||
210 | reg = <0x0 0x40000>; | ||
211 | read-only; | ||
212 | }; | ||
213 | |||
214 | partition@40000 { | ||
215 | label = "Kernel"; | ||
216 | reg = <0x40000 0xc0000>; | ||
217 | }; | ||
218 | }; | ||
219 | }; | ||
182 | }; | 220 | }; |
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index a1dd2ee83753..02891fe876e4 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi | |||
@@ -25,6 +25,12 @@ | |||
25 | compatible = "samsung,exynos4210"; | 25 | compatible = "samsung,exynos4210"; |
26 | interrupt-parent = <&gic>; | 26 | interrupt-parent = <&gic>; |
27 | 27 | ||
28 | aliases { | ||
29 | spi0 = &spi_0; | ||
30 | spi1 = &spi_1; | ||
31 | spi2 = &spi_2; | ||
32 | }; | ||
33 | |||
28 | gic:interrupt-controller@10490000 { | 34 | gic:interrupt-controller@10490000 { |
29 | compatible = "arm,cortex-a9-gic"; | 35 | compatible = "arm,cortex-a9-gic"; |
30 | #interrupt-cells = <3>; | 36 | #interrupt-cells = <3>; |
@@ -33,6 +39,17 @@ | |||
33 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; | 39 | reg = <0x10490000 0x1000>, <0x10480000 0x100>; |
34 | }; | 40 | }; |
35 | 41 | ||
42 | combiner:interrupt-controller@10440000 { | ||
43 | compatible = "samsung,exynos4210-combiner"; | ||
44 | #interrupt-cells = <2>; | ||
45 | interrupt-controller; | ||
46 | reg = <0x10440000 0x1000>; | ||
47 | interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, | ||
48 | <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, | ||
49 | <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, | ||
50 | <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; | ||
51 | }; | ||
52 | |||
36 | watchdog@10060000 { | 53 | watchdog@10060000 { |
37 | compatible = "samsung,s3c2410-wdt"; | 54 | compatible = "samsung,s3c2410-wdt"; |
38 | reg = <0x10060000 0x100>; | 55 | reg = <0x10060000 0x100>; |
@@ -147,6 +164,36 @@ | |||
147 | interrupts = <0 65 0>; | 164 | interrupts = <0 65 0>; |
148 | }; | 165 | }; |
149 | 166 | ||
167 | spi_0: spi@13920000 { | ||
168 | compatible = "samsung,exynos4210-spi"; | ||
169 | reg = <0x13920000 0x100>; | ||
170 | interrupts = <0 66 0>; | ||
171 | tx-dma-channel = <&pdma0 7>; /* preliminary */ | ||
172 | rx-dma-channel = <&pdma0 6>; /* preliminary */ | ||
173 | #address-cells = <1>; | ||
174 | #size-cells = <0>; | ||
175 | }; | ||
176 | |||
177 | spi_1: spi@13930000 { | ||
178 | compatible = "samsung,exynos4210-spi"; | ||
179 | reg = <0x13930000 0x100>; | ||
180 | interrupts = <0 67 0>; | ||
181 | tx-dma-channel = <&pdma1 7>; /* preliminary */ | ||
182 | rx-dma-channel = <&pdma1 6>; /* preliminary */ | ||
183 | #address-cells = <1>; | ||
184 | #size-cells = <0>; | ||
185 | }; | ||
186 | |||
187 | spi_2: spi@13940000 { | ||
188 | compatible = "samsung,exynos4210-spi"; | ||
189 | reg = <0x13940000 0x100>; | ||
190 | interrupts = <0 68 0>; | ||
191 | tx-dma-channel = <&pdma0 9>; /* preliminary */ | ||
192 | rx-dma-channel = <&pdma0 8>; /* preliminary */ | ||
193 | #address-cells = <1>; | ||
194 | #size-cells = <0>; | ||
195 | }; | ||
196 | |||
150 | amba { | 197 | amba { |
151 | #address-cells = <1>; | 198 | #address-cells = <1>; |
152 | #size-cells = <1>; | 199 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 49945cc1bc7d..8a5e348793c7 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts | |||
@@ -71,4 +71,42 @@ | |||
71 | i2c@12CD0000 { | 71 | i2c@12CD0000 { |
72 | status = "disabled"; | 72 | status = "disabled"; |
73 | }; | 73 | }; |
74 | |||
75 | spi_0: spi@12d20000 { | ||
76 | status = "disabled"; | ||
77 | }; | ||
78 | |||
79 | spi_1: spi@12d30000 { | ||
80 | gpios = <&gpa2 4 2 3 0>, | ||
81 | <&gpa2 6 2 3 0>, | ||
82 | <&gpa2 7 2 3 0>; | ||
83 | |||
84 | w25q80bw@0 { | ||
85 | #address-cells = <1>; | ||
86 | #size-cells = <1>; | ||
87 | compatible = "w25x80"; | ||
88 | reg = <0>; | ||
89 | spi-max-frequency = <1000000>; | ||
90 | |||
91 | controller-data { | ||
92 | cs-gpio = <&gpa2 5 1 0 3>; | ||
93 | samsung,spi-feedback-delay = <0>; | ||
94 | }; | ||
95 | |||
96 | partition@0 { | ||
97 | label = "U-Boot"; | ||
98 | reg = <0x0 0x40000>; | ||
99 | read-only; | ||
100 | }; | ||
101 | |||
102 | partition@40000 { | ||
103 | label = "Kernel"; | ||
104 | reg = <0x40000 0xc0000>; | ||
105 | }; | ||
106 | }; | ||
107 | }; | ||
108 | |||
109 | spi_2: spi@12d40000 { | ||
110 | status = "disabled"; | ||
111 | }; | ||
74 | }; | 112 | }; |
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4272b2949228..004aaa8d123c 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi | |||
@@ -23,6 +23,12 @@ | |||
23 | compatible = "samsung,exynos5250"; | 23 | compatible = "samsung,exynos5250"; |
24 | interrupt-parent = <&gic>; | 24 | interrupt-parent = <&gic>; |
25 | 25 | ||
26 | aliases { | ||
27 | spi0 = &spi_0; | ||
28 | spi1 = &spi_1; | ||
29 | spi2 = &spi_2; | ||
30 | }; | ||
31 | |||
26 | gic:interrupt-controller@10481000 { | 32 | gic:interrupt-controller@10481000 { |
27 | compatible = "arm,cortex-a9-gic"; | 33 | compatible = "arm,cortex-a9-gic"; |
28 | #interrupt-cells = <3>; | 34 | #interrupt-cells = <3>; |
@@ -146,6 +152,36 @@ | |||
146 | #size-cells = <0>; | 152 | #size-cells = <0>; |
147 | }; | 153 | }; |
148 | 154 | ||
155 | spi_0: spi@12d20000 { | ||
156 | compatible = "samsung,exynos4210-spi"; | ||
157 | reg = <0x12d20000 0x100>; | ||
158 | interrupts = <0 66 0>; | ||
159 | tx-dma-channel = <&pdma0 5>; /* preliminary */ | ||
160 | rx-dma-channel = <&pdma0 4>; /* preliminary */ | ||
161 | #address-cells = <1>; | ||
162 | #size-cells = <0>; | ||
163 | }; | ||
164 | |||
165 | spi_1: spi@12d30000 { | ||
166 | compatible = "samsung,exynos4210-spi"; | ||
167 | reg = <0x12d30000 0x100>; | ||
168 | interrupts = <0 67 0>; | ||
169 | tx-dma-channel = <&pdma1 5>; /* preliminary */ | ||
170 | rx-dma-channel = <&pdma1 4>; /* preliminary */ | ||
171 | #address-cells = <1>; | ||
172 | #size-cells = <0>; | ||
173 | }; | ||
174 | |||
175 | spi_2: spi@12d40000 { | ||
176 | compatible = "samsung,exynos4210-spi"; | ||
177 | reg = <0x12d40000 0x100>; | ||
178 | interrupts = <0 68 0>; | ||
179 | tx-dma-channel = <&pdma0 7>; /* preliminary */ | ||
180 | rx-dma-channel = <&pdma0 6>; /* preliminary */ | ||
181 | #address-cells = <1>; | ||
182 | #size-cells = <0>; | ||
183 | }; | ||
184 | |||
149 | amba { | 185 | amba { |
150 | #address-cells = <1>; | 186 | #address-cells = <1>; |
151 | #size-cells = <1>; | 187 | #size-cells = <1>; |
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi new file mode 100644 index 000000000000..17136fc7a516 --- /dev/null +++ b/arch/arm/boot/dts/ge863-pro3.dtsi | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3 | ||
3 | * | ||
4 | * Copyright (C) 2012 Telit, | ||
5 | * 2012 Fabio Porcedda <fabio.porcedda@gmail.com> | ||
6 | * | ||
7 | * Licensed under GPLv2 or later. | ||
8 | */ | ||
9 | |||
10 | /include/ "at91sam9260.dtsi" | ||
11 | |||
12 | / { | ||
13 | clocks { | ||
14 | #address-cells = <1>; | ||
15 | #size-cells = <1>; | ||
16 | ranges; | ||
17 | |||
18 | main_clock: clock@0 { | ||
19 | compatible = "atmel,osc", "fixed-clock"; | ||
20 | clock-frequency = <6000000>; | ||
21 | }; | ||
22 | }; | ||
23 | |||
24 | ahb { | ||
25 | apb { | ||
26 | dbgu: serial@fffff200 { | ||
27 | status = "okay"; | ||
28 | }; | ||
29 | }; | ||
30 | |||
31 | nand0: nand@40000000 { | ||
32 | nand-bus-width = <8>; | ||
33 | nand-ecc-mode = "soft"; | ||
34 | nand-on-flash-bbt; | ||
35 | status = "okay"; | ||
36 | |||
37 | boot@0 { | ||
38 | label = "boot"; | ||
39 | reg = <0x0 0x7c0000>; | ||
40 | }; | ||
41 | |||
42 | root@07c0000 { | ||
43 | label = "root"; | ||
44 | reg = <0x7c0000 0x7840000>; | ||
45 | }; | ||
46 | }; | ||
47 | }; | ||
48 | |||
49 | chosen { | ||
50 | bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs"; | ||
51 | }; | ||
52 | }; | ||
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index 70bffa929b65..e3486f486b40 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts | |||
@@ -22,17 +22,60 @@ | |||
22 | 22 | ||
23 | apb@80000000 { | 23 | apb@80000000 { |
24 | apbh@80000000 { | 24 | apbh@80000000 { |
25 | gpmi-nand@8000c000 { | ||
26 | pinctrl-names = "default"; | ||
27 | pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>; | ||
28 | status = "okay"; | ||
29 | }; | ||
30 | |||
25 | ssp0: ssp@80010000 { | 31 | ssp0: ssp@80010000 { |
26 | compatible = "fsl,imx23-mmc"; | 32 | compatible = "fsl,imx23-mmc"; |
27 | pinctrl-names = "default"; | 33 | pinctrl-names = "default"; |
28 | pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>; | 34 | pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; |
29 | bus-width = <8>; | 35 | bus-width = <4>; |
30 | wp-gpios = <&gpio1 30 0>; | 36 | wp-gpios = <&gpio1 30 0>; |
37 | vmmc-supply = <®_vddio_sd0>; | ||
38 | status = "okay"; | ||
39 | }; | ||
40 | |||
41 | pinctrl@80018000 { | ||
42 | pinctrl-names = "default"; | ||
43 | pinctrl-0 = <&hog_pins_a>; | ||
44 | |||
45 | hog_pins_a: hog-gpios@0 { | ||
46 | reg = <0>; | ||
47 | fsl,pinmux-ids = < | ||
48 | 0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */ | ||
49 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | ||
50 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ | ||
51 | >; | ||
52 | fsl,drive-strength = <0>; | ||
53 | fsl,voltage = <1>; | ||
54 | fsl,pull-up = <0>; | ||
55 | }; | ||
56 | }; | ||
57 | |||
58 | lcdif@80030000 { | ||
59 | pinctrl-names = "default"; | ||
60 | pinctrl-0 = <&lcdif_24bit_pins_a>; | ||
61 | panel-enable-gpios = <&gpio1 18 0>; | ||
31 | status = "okay"; | 62 | status = "okay"; |
32 | }; | 63 | }; |
33 | }; | 64 | }; |
34 | 65 | ||
35 | apbx@80040000 { | 66 | apbx@80040000 { |
67 | pwm: pwm@80064000 { | ||
68 | pinctrl-names = "default"; | ||
69 | pinctrl-0 = <&pwm2_pins_a>; | ||
70 | status = "okay"; | ||
71 | }; | ||
72 | |||
73 | auart0: serial@8006c000 { | ||
74 | pinctrl-names = "default"; | ||
75 | pinctrl-0 = <&auart0_pins_a>; | ||
76 | status = "okay"; | ||
77 | }; | ||
78 | |||
36 | duart: serial@80070000 { | 79 | duart: serial@80070000 { |
37 | pinctrl-names = "default"; | 80 | pinctrl-names = "default"; |
38 | pinctrl-0 = <&duart_pins_a>; | 81 | pinctrl-0 = <&duart_pins_a>; |
@@ -40,4 +83,23 @@ | |||
40 | }; | 83 | }; |
41 | }; | 84 | }; |
42 | }; | 85 | }; |
86 | |||
87 | regulators { | ||
88 | compatible = "simple-bus"; | ||
89 | |||
90 | reg_vddio_sd0: vddio-sd0 { | ||
91 | compatible = "regulator-fixed"; | ||
92 | regulator-name = "vddio-sd0"; | ||
93 | regulator-min-microvolt = <3300000>; | ||
94 | regulator-max-microvolt = <3300000>; | ||
95 | gpio = <&gpio1 29 0>; | ||
96 | }; | ||
97 | }; | ||
98 | |||
99 | backlight { | ||
100 | compatible = "pwm-backlight"; | ||
101 | pwms = <&pwm 2 5000000>; | ||
102 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
103 | default-brightness-level = <6>; | ||
104 | }; | ||
43 | }; | 105 | }; |
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts new file mode 100644 index 000000000000..20912b1d8893 --- /dev/null +++ b/arch/arm/boot/dts/imx23-olinuxino.dts | |||
@@ -0,0 +1,44 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | ||
5 | * | ||
6 | * The code contained herein is licensed under the GNU General Public | ||
7 | * License. You may obtain a copy of the GNU General Public License | ||
8 | * Version 2 or later at the following locations: | ||
9 | * | ||
10 | * http://www.opensource.org/licenses/gpl-license.html | ||
11 | * http://www.gnu.org/copyleft/gpl.html | ||
12 | */ | ||
13 | |||
14 | /dts-v1/; | ||
15 | /include/ "imx23.dtsi" | ||
16 | |||
17 | / { | ||
18 | model = "i.MX23 Olinuxino Low Cost Board"; | ||
19 | compatible = "olimex,imx23-olinuxino", "fsl,imx23"; | ||
20 | |||
21 | memory { | ||
22 | reg = <0x40000000 0x04000000>; | ||
23 | }; | ||
24 | |||
25 | apb@80000000 { | ||
26 | apbh@80000000 { | ||
27 | ssp0: ssp@80010000 { | ||
28 | compatible = "fsl,imx23-mmc"; | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; | ||
31 | bus-width = <4>; | ||
32 | status = "okay"; | ||
33 | }; | ||
34 | }; | ||
35 | |||
36 | apbx@80040000 { | ||
37 | duart: serial@80070000 { | ||
38 | pinctrl-names = "default"; | ||
39 | pinctrl-0 = <&duart_pins_a>; | ||
40 | status = "okay"; | ||
41 | }; | ||
42 | }; | ||
43 | }; | ||
44 | }; | ||
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts new file mode 100644 index 000000000000..757a327ff3e8 --- /dev/null +++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Freescale Semiconductor, Inc. | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | /include/ "imx23.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "Freescale STMP378x Development Board"; | ||
17 | compatible = "fsl,stmp378x-devb", "fsl,imx23"; | ||
18 | |||
19 | memory { | ||
20 | reg = <0x40000000 0x04000000>; | ||
21 | }; | ||
22 | |||
23 | apb@80000000 { | ||
24 | apbh@80000000 { | ||
25 | ssp0: ssp@80010000 { | ||
26 | compatible = "fsl,imx23-mmc"; | ||
27 | pinctrl-names = "default"; | ||
28 | pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>; | ||
29 | bus-width = <4>; | ||
30 | wp-gpios = <&gpio1 30 0>; | ||
31 | vmmc-supply = <®_vddio_sd0>; | ||
32 | status = "okay"; | ||
33 | }; | ||
34 | |||
35 | pinctrl@80018000 { | ||
36 | pinctrl-names = "default"; | ||
37 | pinctrl-0 = <&hog_pins_a>; | ||
38 | |||
39 | hog_pins_a: hog-gpios@0 { | ||
40 | reg = <0>; | ||
41 | fsl,pinmux-ids = < | ||
42 | 0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */ | ||
43 | 0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */ | ||
44 | >; | ||
45 | fsl,drive-strength = <0>; | ||
46 | fsl,voltage = <1>; | ||
47 | fsl,pull-up = <0>; | ||
48 | }; | ||
49 | }; | ||
50 | }; | ||
51 | |||
52 | apbx@80040000 { | ||
53 | auart0: serial@8006c000 { | ||
54 | pinctrl-names = "default"; | ||
55 | pinctrl-0 = <&auart0_pins_a>; | ||
56 | status = "okay"; | ||
57 | }; | ||
58 | |||
59 | duart: serial@80070000 { | ||
60 | pinctrl-names = "default"; | ||
61 | pinctrl-0 = <&duart_pins_a>; | ||
62 | status = "okay"; | ||
63 | }; | ||
64 | }; | ||
65 | }; | ||
66 | |||
67 | regulators { | ||
68 | compatible = "simple-bus"; | ||
69 | |||
70 | reg_vddio_sd0: vddio-sd0 { | ||
71 | compatible = "regulator-fixed"; | ||
72 | regulator-name = "vddio-sd0"; | ||
73 | regulator-min-microvolt = <3300000>; | ||
74 | regulator-max-microvolt = <3300000>; | ||
75 | gpio = <&gpio1 29 0>; | ||
76 | }; | ||
77 | }; | ||
78 | }; | ||
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 8c5f9994f3fc..a874dbfb5ae6 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi | |||
@@ -18,6 +18,8 @@ | |||
18 | gpio0 = &gpio0; | 18 | gpio0 = &gpio0; |
19 | gpio1 = &gpio1; | 19 | gpio1 = &gpio1; |
20 | gpio2 = &gpio2; | 20 | gpio2 = &gpio2; |
21 | serial0 = &auart0; | ||
22 | serial1 = &auart1; | ||
21 | }; | 23 | }; |
22 | 24 | ||
23 | cpus { | 25 | cpus { |
@@ -57,13 +59,15 @@ | |||
57 | status = "disabled"; | 59 | status = "disabled"; |
58 | }; | 60 | }; |
59 | 61 | ||
60 | bch@8000a000 { | 62 | gpmi-nand@8000c000 { |
61 | reg = <0x8000a000 2000>; | 63 | compatible = "fsl,imx23-gpmi-nand"; |
62 | status = "disabled"; | 64 | #address-cells = <1>; |
63 | }; | 65 | #size-cells = <1>; |
64 | 66 | reg = <0x8000c000 2000>, <0x8000a000 2000>; | |
65 | gpmi@8000c000 { | 67 | reg-names = "gpmi-nand", "bch"; |
66 | reg = <0x8000c000 2000>; | 68 | interrupts = <13>, <56>; |
69 | interrupt-names = "gpmi-dma", "bch"; | ||
70 | fsl,gpmi-dma-channel = <4>; | ||
67 | status = "disabled"; | 71 | status = "disabled"; |
68 | }; | 72 | }; |
69 | 73 | ||
@@ -114,24 +118,151 @@ | |||
114 | 118 | ||
115 | duart_pins_a: duart@0 { | 119 | duart_pins_a: duart@0 { |
116 | reg = <0>; | 120 | reg = <0>; |
117 | fsl,pinmux-ids = <0x11a2 0x11b2>; | 121 | fsl,pinmux-ids = < |
122 | 0x11a2 /* MX23_PAD_PWM0__DUART_RX */ | ||
123 | 0x11b2 /* MX23_PAD_PWM1__DUART_TX */ | ||
124 | >; | ||
125 | fsl,drive-strength = <0>; | ||
126 | fsl,voltage = <1>; | ||
127 | fsl,pull-up = <0>; | ||
128 | }; | ||
129 | |||
130 | auart0_pins_a: auart0@0 { | ||
131 | reg = <0>; | ||
132 | fsl,pinmux-ids = < | ||
133 | 0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */ | ||
134 | 0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */ | ||
135 | 0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */ | ||
136 | 0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */ | ||
137 | >; | ||
118 | fsl,drive-strength = <0>; | 138 | fsl,drive-strength = <0>; |
119 | fsl,voltage = <1>; | 139 | fsl,voltage = <1>; |
120 | fsl,pull-up = <0>; | 140 | fsl,pull-up = <0>; |
121 | }; | 141 | }; |
122 | 142 | ||
143 | gpmi_pins_a: gpmi-nand@0 { | ||
144 | reg = <0>; | ||
145 | fsl,pinmux-ids = < | ||
146 | 0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */ | ||
147 | 0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */ | ||
148 | 0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */ | ||
149 | 0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */ | ||
150 | 0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */ | ||
151 | 0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */ | ||
152 | 0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */ | ||
153 | 0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */ | ||
154 | 0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */ | ||
155 | 0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */ | ||
156 | 0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */ | ||
157 | 0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */ | ||
158 | 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ | ||
159 | 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ | ||
160 | 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ | ||
161 | 0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */ | ||
162 | 0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */ | ||
163 | >; | ||
164 | fsl,drive-strength = <0>; | ||
165 | fsl,voltage = <1>; | ||
166 | fsl,pull-up = <0>; | ||
167 | }; | ||
168 | |||
169 | gpmi_pins_fixup: gpmi-pins-fixup { | ||
170 | fsl,pinmux-ids = < | ||
171 | 0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */ | ||
172 | 0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */ | ||
173 | 0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */ | ||
174 | >; | ||
175 | fsl,drive-strength = <2>; | ||
176 | }; | ||
177 | |||
178 | mmc0_4bit_pins_a: mmc0-4bit@0 { | ||
179 | reg = <0>; | ||
180 | fsl,pinmux-ids = < | ||
181 | 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ | ||
182 | 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ | ||
183 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ | ||
184 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ | ||
185 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ | ||
186 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
187 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ | ||
188 | >; | ||
189 | fsl,drive-strength = <1>; | ||
190 | fsl,voltage = <1>; | ||
191 | fsl,pull-up = <1>; | ||
192 | }; | ||
193 | |||
123 | mmc0_8bit_pins_a: mmc0-8bit@0 { | 194 | mmc0_8bit_pins_a: mmc0-8bit@0 { |
124 | reg = <0>; | 195 | reg = <0>; |
125 | fsl,pinmux-ids = <0x2020 0x2030 0x2040 | 196 | fsl,pinmux-ids = < |
126 | 0x2050 0x0082 0x0092 0x00a2 | 197 | 0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */ |
127 | 0x00b2 0x2000 0x2010 0x2060>; | 198 | 0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */ |
199 | 0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */ | ||
200 | 0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */ | ||
201 | 0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */ | ||
202 | 0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */ | ||
203 | 0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */ | ||
204 | 0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */ | ||
205 | 0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */ | ||
206 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
207 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ | ||
208 | >; | ||
128 | fsl,drive-strength = <1>; | 209 | fsl,drive-strength = <1>; |
129 | fsl,voltage = <1>; | 210 | fsl,voltage = <1>; |
130 | fsl,pull-up = <1>; | 211 | fsl,pull-up = <1>; |
131 | }; | 212 | }; |
132 | 213 | ||
133 | mmc0_pins_fixup: mmc0-pins-fixup { | 214 | mmc0_pins_fixup: mmc0-pins-fixup { |
134 | fsl,pinmux-ids = <0x2010 0x2060>; | 215 | fsl,pinmux-ids = < |
216 | 0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */ | ||
217 | 0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */ | ||
218 | >; | ||
219 | fsl,pull-up = <0>; | ||
220 | }; | ||
221 | |||
222 | pwm2_pins_a: pwm2@0 { | ||
223 | reg = <0>; | ||
224 | fsl,pinmux-ids = < | ||
225 | 0x11c0 /* MX23_PAD_PWM2__PWM2 */ | ||
226 | >; | ||
227 | fsl,drive-strength = <0>; | ||
228 | fsl,voltage = <1>; | ||
229 | fsl,pull-up = <0>; | ||
230 | }; | ||
231 | |||
232 | lcdif_24bit_pins_a: lcdif-24bit@0 { | ||
233 | reg = <0>; | ||
234 | fsl,pinmux-ids = < | ||
235 | 0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */ | ||
236 | 0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */ | ||
237 | 0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */ | ||
238 | 0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */ | ||
239 | 0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */ | ||
240 | 0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */ | ||
241 | 0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */ | ||
242 | 0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */ | ||
243 | 0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */ | ||
244 | 0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */ | ||
245 | 0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */ | ||
246 | 0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */ | ||
247 | 0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */ | ||
248 | 0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */ | ||
249 | 0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */ | ||
250 | 0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */ | ||
251 | 0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */ | ||
252 | 0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */ | ||
253 | 0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */ | ||
254 | 0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */ | ||
255 | 0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */ | ||
256 | 0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */ | ||
257 | 0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */ | ||
258 | 0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */ | ||
259 | 0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */ | ||
260 | 0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */ | ||
261 | 0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */ | ||
262 | 0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */ | ||
263 | >; | ||
264 | fsl,drive-strength = <0>; | ||
265 | fsl,voltage = <1>; | ||
135 | fsl,pull-up = <0>; | 266 | fsl,pull-up = <0>; |
136 | }; | 267 | }; |
137 | }; | 268 | }; |
@@ -172,7 +303,9 @@ | |||
172 | }; | 303 | }; |
173 | 304 | ||
174 | lcdif@80030000 { | 305 | lcdif@80030000 { |
306 | compatible = "fsl,imx23-lcdif"; | ||
175 | reg = <0x80030000 2000>; | 307 | reg = <0x80030000 2000>; |
308 | interrupts = <46 45>; | ||
176 | status = "disabled"; | 309 | status = "disabled"; |
177 | }; | 310 | }; |
178 | 311 | ||
@@ -242,12 +375,16 @@ | |||
242 | }; | 375 | }; |
243 | 376 | ||
244 | rtc@8005c000 { | 377 | rtc@8005c000 { |
378 | compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; | ||
245 | reg = <0x8005c000 2000>; | 379 | reg = <0x8005c000 2000>; |
246 | status = "disabled"; | 380 | interrupts = <22>; |
247 | }; | 381 | }; |
248 | 382 | ||
249 | pwm@80064000 { | 383 | pwm: pwm@80064000 { |
384 | compatible = "fsl,imx23-pwm"; | ||
250 | reg = <0x80064000 2000>; | 385 | reg = <0x80064000 2000>; |
386 | #pwm-cells = <2>; | ||
387 | fsl,pwm-number = <5>; | ||
251 | status = "disabled"; | 388 | status = "disabled"; |
252 | }; | 389 | }; |
253 | 390 | ||
@@ -257,12 +394,16 @@ | |||
257 | }; | 394 | }; |
258 | 395 | ||
259 | auart0: serial@8006c000 { | 396 | auart0: serial@8006c000 { |
397 | compatible = "fsl,imx23-auart"; | ||
260 | reg = <0x8006c000 0x2000>; | 398 | reg = <0x8006c000 0x2000>; |
399 | interrupts = <24 25 23>; | ||
261 | status = "disabled"; | 400 | status = "disabled"; |
262 | }; | 401 | }; |
263 | 402 | ||
264 | auart1: serial@8006e000 { | 403 | auart1: serial@8006e000 { |
404 | compatible = "fsl,imx23-auart"; | ||
265 | reg = <0x8006e000 0x2000>; | 405 | reg = <0x8006e000 0x2000>; |
406 | interrupts = <59 60 58>; | ||
266 | status = "disabled"; | 407 | status = "disabled"; |
267 | }; | 408 | }; |
268 | 409 | ||
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts new file mode 100644 index 000000000000..d3f8296e19e0 --- /dev/null +++ b/arch/arm/boot/dts/imx27-3ds.dts | |||
@@ -0,0 +1,41 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Sascha Hauer, Pengutronix | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | /include/ "imx27.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "mx27_3ds"; | ||
17 | compatible = "freescale,imx27-3ds", "fsl,imx27"; | ||
18 | |||
19 | memory { | ||
20 | reg = <0x0 0x0>; | ||
21 | }; | ||
22 | |||
23 | soc { | ||
24 | aipi@10000000 { /* aipi */ | ||
25 | |||
26 | wdog@10002000 { | ||
27 | status = "okay"; | ||
28 | }; | ||
29 | |||
30 | uart@1000a000 { | ||
31 | fsl,uart-has-rtscts; | ||
32 | status = "okay"; | ||
33 | }; | ||
34 | |||
35 | fec@1002b000 { | ||
36 | status = "okay"; | ||
37 | }; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | }; | ||
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi index 386c769c38d1..00bae3aad5ab 100644 --- a/arch/arm/boot/dts/imx27.dtsi +++ b/arch/arm/boot/dts/imx27.dtsi | |||
@@ -121,7 +121,7 @@ | |||
121 | gpio-controller; | 121 | gpio-controller; |
122 | #gpio-cells = <2>; | 122 | #gpio-cells = <2>; |
123 | interrupt-controller; | 123 | interrupt-controller; |
124 | #interrupt-cells = <1>; | 124 | #interrupt-cells = <2>; |
125 | }; | 125 | }; |
126 | 126 | ||
127 | gpio2: gpio@10015100 { | 127 | gpio2: gpio@10015100 { |
@@ -131,7 +131,7 @@ | |||
131 | gpio-controller; | 131 | gpio-controller; |
132 | #gpio-cells = <2>; | 132 | #gpio-cells = <2>; |
133 | interrupt-controller; | 133 | interrupt-controller; |
134 | #interrupt-cells = <1>; | 134 | #interrupt-cells = <2>; |
135 | }; | 135 | }; |
136 | 136 | ||
137 | gpio3: gpio@10015200 { | 137 | gpio3: gpio@10015200 { |
@@ -141,7 +141,7 @@ | |||
141 | gpio-controller; | 141 | gpio-controller; |
142 | #gpio-cells = <2>; | 142 | #gpio-cells = <2>; |
143 | interrupt-controller; | 143 | interrupt-controller; |
144 | #interrupt-cells = <1>; | 144 | #interrupt-cells = <2>; |
145 | }; | 145 | }; |
146 | 146 | ||
147 | gpio4: gpio@10015300 { | 147 | gpio4: gpio@10015300 { |
@@ -151,7 +151,7 @@ | |||
151 | gpio-controller; | 151 | gpio-controller; |
152 | #gpio-cells = <2>; | 152 | #gpio-cells = <2>; |
153 | interrupt-controller; | 153 | interrupt-controller; |
154 | #interrupt-cells = <1>; | 154 | #interrupt-cells = <2>; |
155 | }; | 155 | }; |
156 | 156 | ||
157 | gpio5: gpio@10015400 { | 157 | gpio5: gpio@10015400 { |
@@ -161,7 +161,7 @@ | |||
161 | gpio-controller; | 161 | gpio-controller; |
162 | #gpio-cells = <2>; | 162 | #gpio-cells = <2>; |
163 | interrupt-controller; | 163 | interrupt-controller; |
164 | #interrupt-cells = <1>; | 164 | #interrupt-cells = <2>; |
165 | }; | 165 | }; |
166 | 166 | ||
167 | gpio6: gpio@10015500 { | 167 | gpio6: gpio@10015500 { |
@@ -171,7 +171,7 @@ | |||
171 | gpio-controller; | 171 | gpio-controller; |
172 | #gpio-cells = <2>; | 172 | #gpio-cells = <2>; |
173 | interrupt-controller; | 173 | interrupt-controller; |
174 | #interrupt-cells = <1>; | 174 | #interrupt-cells = <2>; |
175 | }; | 175 | }; |
176 | 176 | ||
177 | cspi3: cspi@10017000 { | 177 | cspi3: cspi@10017000 { |
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts new file mode 100644 index 000000000000..b383417a558f --- /dev/null +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts | |||
@@ -0,0 +1,198 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "imx28.dtsi" | ||
3 | |||
4 | / { | ||
5 | model = "Bluegiga APX4 Development Kit"; | ||
6 | compatible = "bluegiga,apx4devkit", "fsl,imx28"; | ||
7 | |||
8 | memory { | ||
9 | reg = <0x40000000 0x04000000>; | ||
10 | }; | ||
11 | |||
12 | apb@80000000 { | ||
13 | apbh@80000000 { | ||
14 | gpmi-nand@8000c000 { | ||
15 | pinctrl-names = "default"; | ||
16 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | ||
17 | status = "okay"; | ||
18 | }; | ||
19 | |||
20 | ssp0: ssp@80010000 { | ||
21 | compatible = "fsl,imx28-mmc"; | ||
22 | pinctrl-names = "default"; | ||
23 | pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>; | ||
24 | bus-width = <4>; | ||
25 | status = "okay"; | ||
26 | }; | ||
27 | |||
28 | ssp2: ssp@80014000 { | ||
29 | compatible = "fsl,imx28-mmc"; | ||
30 | pinctrl-names = "default"; | ||
31 | pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>; | ||
32 | bus-width = <4>; | ||
33 | status = "okay"; | ||
34 | }; | ||
35 | |||
36 | pinctrl@80018000 { | ||
37 | pinctrl-names = "default"; | ||
38 | pinctrl-0 = <&hog_pins_a>; | ||
39 | |||
40 | hog_pins_a: hog-gpios@0 { | ||
41 | reg = <0>; | ||
42 | fsl,pinmux-ids = < | ||
43 | 0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */ | ||
44 | 0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */ | ||
45 | 0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */ | ||
46 | 0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */ | ||
47 | 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ | ||
48 | 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ | ||
49 | 0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */ | ||
50 | >; | ||
51 | fsl,drive-strength = <0>; | ||
52 | fsl,voltage = <1>; | ||
53 | fsl,pull-up = <0>; | ||
54 | }; | ||
55 | |||
56 | lcdif_pins_apx4: lcdif-apx4@0 { | ||
57 | reg = <0>; | ||
58 | fsl,pinmux-ids = < | ||
59 | 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ | ||
60 | 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ | ||
61 | 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ | ||
62 | 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ | ||
63 | >; | ||
64 | fsl,drive-strength = <0>; | ||
65 | fsl,voltage = <1>; | ||
66 | fsl,pull-up = <0>; | ||
67 | }; | ||
68 | |||
69 | mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 { | ||
70 | reg = <0>; | ||
71 | fsl,pinmux-ids = < | ||
72 | 0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */ | ||
73 | 0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */ | ||
74 | 0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */ | ||
75 | 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ | ||
76 | 0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */ | ||
77 | 0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */ | ||
78 | >; | ||
79 | fsl,drive-strength = <1>; | ||
80 | fsl,voltage = <1>; | ||
81 | fsl,pull-up = <1>; | ||
82 | }; | ||
83 | |||
84 | mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 { | ||
85 | fsl,pinmux-ids = < | ||
86 | 0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */ | ||
87 | >; | ||
88 | fsl,drive-strength = <2>; | ||
89 | fsl,pull-up = <0>; | ||
90 | }; | ||
91 | }; | ||
92 | |||
93 | lcdif@80030000 { | ||
94 | pinctrl-names = "default"; | ||
95 | pinctrl-0 = <&lcdif_24bit_pins_a | ||
96 | &lcdif_pins_apx4>; | ||
97 | status = "okay"; | ||
98 | }; | ||
99 | }; | ||
100 | |||
101 | apbx@80040000 { | ||
102 | saif0: saif@80042000 { | ||
103 | pinctrl-names = "default"; | ||
104 | pinctrl-0 = <&saif0_pins_a>; | ||
105 | status = "okay"; | ||
106 | }; | ||
107 | |||
108 | saif1: saif@80046000 { | ||
109 | pinctrl-names = "default"; | ||
110 | pinctrl-0 = <&saif1_pins_a>; | ||
111 | fsl,saif-master = <&saif0>; | ||
112 | status = "okay"; | ||
113 | }; | ||
114 | |||
115 | i2c0: i2c@80058000 { | ||
116 | pinctrl-names = "default"; | ||
117 | pinctrl-0 = <&i2c0_pins_a>; | ||
118 | status = "okay"; | ||
119 | |||
120 | sgtl5000: codec@0a { | ||
121 | compatible = "fsl,sgtl5000"; | ||
122 | reg = <0x0a>; | ||
123 | VDDA-supply = <®_3p3v>; | ||
124 | VDDIO-supply = <®_3p3v>; | ||
125 | |||
126 | }; | ||
127 | |||
128 | pcf8563: rtc@51 { | ||
129 | compatible = "phg,pcf8563"; | ||
130 | reg = <0x51>; | ||
131 | }; | ||
132 | }; | ||
133 | |||
134 | duart: serial@80074000 { | ||
135 | pinctrl-names = "default"; | ||
136 | pinctrl-0 = <&duart_pins_a>; | ||
137 | status = "okay"; | ||
138 | }; | ||
139 | |||
140 | auart0: serial@8006a000 { | ||
141 | pinctrl-names = "default"; | ||
142 | pinctrl-0 = <&auart0_pins_a>; | ||
143 | status = "okay"; | ||
144 | }; | ||
145 | |||
146 | auart1: serial@8006c000 { | ||
147 | pinctrl-names = "default"; | ||
148 | pinctrl-0 = <&auart1_2pins_a>; | ||
149 | status = "okay"; | ||
150 | }; | ||
151 | |||
152 | auart2: serial@8006e000 { | ||
153 | pinctrl-names = "default"; | ||
154 | pinctrl-0 = <&auart2_2pins_a>; | ||
155 | status = "okay"; | ||
156 | }; | ||
157 | }; | ||
158 | }; | ||
159 | |||
160 | ahb@80080000 { | ||
161 | mac0: ethernet@800f0000 { | ||
162 | phy-mode = "rmii"; | ||
163 | pinctrl-names = "default"; | ||
164 | pinctrl-0 = <&mac0_pins_a>; | ||
165 | status = "okay"; | ||
166 | }; | ||
167 | }; | ||
168 | |||
169 | regulators { | ||
170 | compatible = "simple-bus"; | ||
171 | |||
172 | reg_3p3v: 3p3v { | ||
173 | compatible = "regulator-fixed"; | ||
174 | regulator-name = "3P3V"; | ||
175 | regulator-min-microvolt = <3300000>; | ||
176 | regulator-max-microvolt = <3300000>; | ||
177 | regulator-always-on; | ||
178 | }; | ||
179 | }; | ||
180 | |||
181 | sound { | ||
182 | compatible = "bluegiga,apx4devkit-sgtl5000", | ||
183 | "fsl,mxs-audio-sgtl5000"; | ||
184 | model = "apx4devkit-sgtl5000"; | ||
185 | saif-controllers = <&saif0 &saif1>; | ||
186 | audio-codec = <&sgtl5000>; | ||
187 | }; | ||
188 | |||
189 | leds { | ||
190 | compatible = "gpio-leds"; | ||
191 | |||
192 | user { | ||
193 | label = "Heartbeat"; | ||
194 | gpios = <&gpio3 28 0>; | ||
195 | linux,default-trigger = "heartbeat"; | ||
196 | }; | ||
197 | }; | ||
198 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts new file mode 100644 index 000000000000..c03a577beca3 --- /dev/null +++ b/arch/arm/boot/dts/imx28-cfa10036.dts | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Free Electrons | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | /include/ "imx28.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "Crystalfontz CFA-10036 Board"; | ||
17 | compatible = "crystalfontz,cfa10036", "fsl,imx28"; | ||
18 | |||
19 | memory { | ||
20 | reg = <0x40000000 0x08000000>; | ||
21 | }; | ||
22 | |||
23 | apb@80000000 { | ||
24 | apbh@80000000 { | ||
25 | ssp0: ssp@80010000 { | ||
26 | compatible = "fsl,imx28-mmc"; | ||
27 | pinctrl-names = "default"; | ||
28 | pinctrl-0 = <&mmc0_4bit_pins_a | ||
29 | &mmc0_cd_cfg &mmc0_sck_cfg>; | ||
30 | bus-width = <4>; | ||
31 | status = "okay"; | ||
32 | }; | ||
33 | }; | ||
34 | |||
35 | apbx@80040000 { | ||
36 | duart: serial@80074000 { | ||
37 | pinctrl-names = "default"; | ||
38 | pinctrl-0 = <&duart_pins_b>; | ||
39 | status = "okay"; | ||
40 | }; | ||
41 | }; | ||
42 | }; | ||
43 | |||
44 | leds { | ||
45 | compatible = "gpio-leds"; | ||
46 | |||
47 | power { | ||
48 | gpios = <&gpio3 4 1>; | ||
49 | default-state = "on"; | ||
50 | }; | ||
51 | }; | ||
52 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index ee520a529cb4..773c0e84d1fb 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts | |||
@@ -22,6 +22,13 @@ | |||
22 | 22 | ||
23 | apb@80000000 { | 23 | apb@80000000 { |
24 | apbh@80000000 { | 24 | apbh@80000000 { |
25 | gpmi-nand@8000c000 { | ||
26 | pinctrl-names = "default"; | ||
27 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg | ||
28 | &gpmi_pins_evk>; | ||
29 | status = "okay"; | ||
30 | }; | ||
31 | |||
25 | ssp0: ssp@80010000 { | 32 | ssp0: ssp@80010000 { |
26 | compatible = "fsl,imx28-mmc"; | 33 | compatible = "fsl,imx28-mmc"; |
27 | pinctrl-names = "default"; | 34 | pinctrl-names = "default"; |
@@ -29,6 +36,7 @@ | |||
29 | &mmc0_cd_cfg &mmc0_sck_cfg>; | 36 | &mmc0_cd_cfg &mmc0_sck_cfg>; |
30 | bus-width = <8>; | 37 | bus-width = <8>; |
31 | wp-gpios = <&gpio2 12 0>; | 38 | wp-gpios = <&gpio2 12 0>; |
39 | vmmc-supply = <®_vddio_sd0>; | ||
32 | status = "okay"; | 40 | status = "okay"; |
33 | }; | 41 | }; |
34 | 42 | ||
@@ -36,6 +44,72 @@ | |||
36 | compatible = "fsl,imx28-mmc"; | 44 | compatible = "fsl,imx28-mmc"; |
37 | bus-width = <8>; | 45 | bus-width = <8>; |
38 | wp-gpios = <&gpio0 28 0>; | 46 | wp-gpios = <&gpio0 28 0>; |
47 | }; | ||
48 | |||
49 | pinctrl@80018000 { | ||
50 | pinctrl-names = "default"; | ||
51 | pinctrl-0 = <&hog_pins_a>; | ||
52 | |||
53 | hog_pins_a: hog-gpios@0 { | ||
54 | reg = <0>; | ||
55 | fsl,pinmux-ids = < | ||
56 | 0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */ | ||
57 | 0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */ | ||
58 | 0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */ | ||
59 | 0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */ | ||
60 | 0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */ | ||
61 | 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */ | ||
62 | 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */ | ||
63 | 0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */ | ||
64 | 0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */ | ||
65 | >; | ||
66 | fsl,drive-strength = <0>; | ||
67 | fsl,voltage = <1>; | ||
68 | fsl,pull-up = <0>; | ||
69 | }; | ||
70 | |||
71 | gpmi_pins_evk: gpmi-nand-evk@0 { | ||
72 | reg = <0>; | ||
73 | fsl,pinmux-ids = < | ||
74 | 0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */ | ||
75 | 0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */ | ||
76 | >; | ||
77 | fsl,drive-strength = <0>; | ||
78 | fsl,voltage = <1>; | ||
79 | fsl,pull-up = <0>; | ||
80 | }; | ||
81 | |||
82 | lcdif_pins_evk: lcdif-evk@0 { | ||
83 | reg = <0>; | ||
84 | fsl,pinmux-ids = < | ||
85 | 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ | ||
86 | 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ | ||
87 | 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ | ||
88 | 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ | ||
89 | >; | ||
90 | fsl,drive-strength = <0>; | ||
91 | fsl,voltage = <1>; | ||
92 | fsl,pull-up = <0>; | ||
93 | }; | ||
94 | }; | ||
95 | |||
96 | lcdif@80030000 { | ||
97 | pinctrl-names = "default"; | ||
98 | pinctrl-0 = <&lcdif_24bit_pins_a | ||
99 | &lcdif_pins_evk>; | ||
100 | panel-enable-gpios = <&gpio3 30 0>; | ||
101 | status = "okay"; | ||
102 | }; | ||
103 | |||
104 | can0: can@80032000 { | ||
105 | pinctrl-names = "default"; | ||
106 | pinctrl-0 = <&can0_pins_a>; | ||
107 | status = "okay"; | ||
108 | }; | ||
109 | |||
110 | can1: can@80034000 { | ||
111 | pinctrl-names = "default"; | ||
112 | pinctrl-0 = <&can1_pins_a>; | ||
39 | status = "okay"; | 113 | status = "okay"; |
40 | }; | 114 | }; |
41 | }; | 115 | }; |
@@ -68,19 +142,58 @@ | |||
68 | }; | 142 | }; |
69 | }; | 143 | }; |
70 | 144 | ||
145 | pwm: pwm@80064000 { | ||
146 | pinctrl-names = "default"; | ||
147 | pinctrl-0 = <&pwm2_pins_a>; | ||
148 | status = "okay"; | ||
149 | }; | ||
150 | |||
71 | duart: serial@80074000 { | 151 | duart: serial@80074000 { |
72 | pinctrl-names = "default"; | 152 | pinctrl-names = "default"; |
73 | pinctrl-0 = <&duart_pins_a>; | 153 | pinctrl-0 = <&duart_pins_a>; |
74 | status = "okay"; | 154 | status = "okay"; |
75 | }; | 155 | }; |
156 | |||
157 | auart0: serial@8006a000 { | ||
158 | pinctrl-names = "default"; | ||
159 | pinctrl-0 = <&auart0_pins_a>; | ||
160 | status = "okay"; | ||
161 | }; | ||
162 | |||
163 | auart3: serial@80070000 { | ||
164 | pinctrl-names = "default"; | ||
165 | pinctrl-0 = <&auart3_pins_a>; | ||
166 | status = "okay"; | ||
167 | }; | ||
168 | |||
169 | usbphy0: usbphy@8007c000 { | ||
170 | status = "okay"; | ||
171 | }; | ||
172 | |||
173 | usbphy1: usbphy@8007e000 { | ||
174 | status = "okay"; | ||
175 | }; | ||
76 | }; | 176 | }; |
77 | }; | 177 | }; |
78 | 178 | ||
79 | ahb@80080000 { | 179 | ahb@80080000 { |
180 | usb0: usb@80080000 { | ||
181 | vbus-supply = <®_usb0_vbus>; | ||
182 | status = "okay"; | ||
183 | }; | ||
184 | |||
185 | usb1: usb@80090000 { | ||
186 | vbus-supply = <®_usb1_vbus>; | ||
187 | status = "okay"; | ||
188 | }; | ||
189 | |||
80 | mac0: ethernet@800f0000 { | 190 | mac0: ethernet@800f0000 { |
81 | phy-mode = "rmii"; | 191 | phy-mode = "rmii"; |
82 | pinctrl-names = "default"; | 192 | pinctrl-names = "default"; |
83 | pinctrl-0 = <&mac0_pins_a>; | 193 | pinctrl-0 = <&mac0_pins_a>; |
194 | phy-supply = <®_fec_3v3>; | ||
195 | phy-reset-gpios = <&gpio4 13 0>; | ||
196 | phy-reset-duration = <100>; | ||
84 | status = "okay"; | 197 | status = "okay"; |
85 | }; | 198 | }; |
86 | 199 | ||
@@ -102,6 +215,40 @@ | |||
102 | regulator-max-microvolt = <3300000>; | 215 | regulator-max-microvolt = <3300000>; |
103 | regulator-always-on; | 216 | regulator-always-on; |
104 | }; | 217 | }; |
218 | |||
219 | reg_vddio_sd0: vddio-sd0 { | ||
220 | compatible = "regulator-fixed"; | ||
221 | regulator-name = "vddio-sd0"; | ||
222 | regulator-min-microvolt = <3300000>; | ||
223 | regulator-max-microvolt = <3300000>; | ||
224 | gpio = <&gpio3 28 0>; | ||
225 | }; | ||
226 | |||
227 | reg_fec_3v3: fec-3v3 { | ||
228 | compatible = "regulator-fixed"; | ||
229 | regulator-name = "fec-3v3"; | ||
230 | regulator-min-microvolt = <3300000>; | ||
231 | regulator-max-microvolt = <3300000>; | ||
232 | gpio = <&gpio2 15 0>; | ||
233 | }; | ||
234 | |||
235 | reg_usb0_vbus: usb0_vbus { | ||
236 | compatible = "regulator-fixed"; | ||
237 | regulator-name = "usb0_vbus"; | ||
238 | regulator-min-microvolt = <5000000>; | ||
239 | regulator-max-microvolt = <5000000>; | ||
240 | gpio = <&gpio3 9 0>; | ||
241 | enable-active-high; | ||
242 | }; | ||
243 | |||
244 | reg_usb1_vbus: usb1_vbus { | ||
245 | compatible = "regulator-fixed"; | ||
246 | regulator-name = "usb1_vbus"; | ||
247 | regulator-min-microvolt = <5000000>; | ||
248 | regulator-max-microvolt = <5000000>; | ||
249 | gpio = <&gpio3 8 0>; | ||
250 | enable-active-high; | ||
251 | }; | ||
105 | }; | 252 | }; |
106 | 253 | ||
107 | sound { | 254 | sound { |
@@ -111,4 +258,21 @@ | |||
111 | saif-controllers = <&saif0 &saif1>; | 258 | saif-controllers = <&saif0 &saif1>; |
112 | audio-codec = <&sgtl5000>; | 259 | audio-codec = <&sgtl5000>; |
113 | }; | 260 | }; |
261 | |||
262 | leds { | ||
263 | compatible = "gpio-leds"; | ||
264 | |||
265 | user { | ||
266 | label = "Heartbeat"; | ||
267 | gpios = <&gpio3 5 0>; | ||
268 | linux,default-trigger = "heartbeat"; | ||
269 | }; | ||
270 | }; | ||
271 | |||
272 | backlight { | ||
273 | compatible = "pwm-backlight"; | ||
274 | pwms = <&pwm 2 5000000>; | ||
275 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
276 | default-brightness-level = <6>; | ||
277 | }; | ||
114 | }; | 278 | }; |
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts new file mode 100644 index 000000000000..183a3fd2d859 --- /dev/null +++ b/arch/arm/boot/dts/imx28-m28evk.dts | |||
@@ -0,0 +1,210 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Marek Vasut <marex@denx.de> | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | /include/ "imx28.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "DENX M28EVK"; | ||
17 | compatible = "denx,m28evk", "fsl,imx28"; | ||
18 | |||
19 | memory { | ||
20 | reg = <0x40000000 0x08000000>; | ||
21 | }; | ||
22 | |||
23 | apb@80000000 { | ||
24 | apbh@80000000 { | ||
25 | gpmi-nand@8000c000 { | ||
26 | pinctrl-names = "default"; | ||
27 | pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; | ||
28 | status = "okay"; | ||
29 | |||
30 | partition@0 { | ||
31 | label = "bootloader"; | ||
32 | reg = <0x00000000 0x00300000>; | ||
33 | read-only; | ||
34 | }; | ||
35 | |||
36 | partition@1 { | ||
37 | label = "environment"; | ||
38 | reg = <0x00300000 0x00080000>; | ||
39 | }; | ||
40 | |||
41 | partition@2 { | ||
42 | label = "redundant-environment"; | ||
43 | reg = <0x00380000 0x00080000>; | ||
44 | }; | ||
45 | |||
46 | partition@3 { | ||
47 | label = "kernel"; | ||
48 | reg = <0x00400000 0x00400000>; | ||
49 | }; | ||
50 | |||
51 | partition@4 { | ||
52 | label = "filesystem"; | ||
53 | reg = <0x00800000 0x0f800000>; | ||
54 | }; | ||
55 | }; | ||
56 | |||
57 | ssp0: ssp@80010000 { | ||
58 | compatible = "fsl,imx28-mmc"; | ||
59 | pinctrl-names = "default"; | ||
60 | pinctrl-0 = <&mmc0_8bit_pins_a | ||
61 | &mmc0_cd_cfg | ||
62 | &mmc0_sck_cfg>; | ||
63 | bus-width = <8>; | ||
64 | wp-gpios = <&gpio3 10 1>; | ||
65 | status = "okay"; | ||
66 | }; | ||
67 | |||
68 | pinctrl@80018000 { | ||
69 | pinctrl-names = "default"; | ||
70 | pinctrl-0 = <&hog_pins_a>; | ||
71 | |||
72 | hog_pins_a: hog-gpios@0 { | ||
73 | reg = <0>; | ||
74 | fsl,pinmux-ids = < | ||
75 | 0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */ | ||
76 | 0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */ | ||
77 | >; | ||
78 | fsl,drive-strength = <0>; | ||
79 | fsl,voltage = <1>; | ||
80 | fsl,pull-up = <0>; | ||
81 | }; | ||
82 | |||
83 | lcdif_pins_m28: lcdif-m28@0 { | ||
84 | reg = <0>; | ||
85 | fsl,pinmux-ids = < | ||
86 | 0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */ | ||
87 | 0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */ | ||
88 | >; | ||
89 | fsl,drive-strength = <0>; | ||
90 | fsl,voltage = <1>; | ||
91 | fsl,pull-up = <0>; | ||
92 | }; | ||
93 | }; | ||
94 | |||
95 | lcdif@80030000 { | ||
96 | pinctrl-names = "default"; | ||
97 | pinctrl-0 = <&lcdif_24bit_pins_a | ||
98 | &lcdif_pins_m28>; | ||
99 | status = "okay"; | ||
100 | }; | ||
101 | |||
102 | can0: can@80032000 { | ||
103 | pinctrl-names = "default"; | ||
104 | pinctrl-0 = <&can0_pins_a>; | ||
105 | status = "okay"; | ||
106 | }; | ||
107 | |||
108 | can1: can@80034000 { | ||
109 | pinctrl-names = "default"; | ||
110 | pinctrl-0 = <&can1_pins_a>; | ||
111 | status = "okay"; | ||
112 | }; | ||
113 | }; | ||
114 | |||
115 | apbx@80040000 { | ||
116 | saif0: saif@80042000 { | ||
117 | pinctrl-names = "default"; | ||
118 | pinctrl-0 = <&saif0_pins_a>; | ||
119 | status = "okay"; | ||
120 | }; | ||
121 | |||
122 | saif1: saif@80046000 { | ||
123 | pinctrl-names = "default"; | ||
124 | pinctrl-0 = <&saif1_pins_a>; | ||
125 | fsl,saif-master = <&saif0>; | ||
126 | status = "okay"; | ||
127 | }; | ||
128 | |||
129 | i2c0: i2c@80058000 { | ||
130 | pinctrl-names = "default"; | ||
131 | pinctrl-0 = <&i2c0_pins_a>; | ||
132 | status = "okay"; | ||
133 | |||
134 | sgtl5000: codec@0a { | ||
135 | compatible = "fsl,sgtl5000"; | ||
136 | reg = <0x0a>; | ||
137 | VDDA-supply = <®_3p3v>; | ||
138 | VDDIO-supply = <®_3p3v>; | ||
139 | |||
140 | }; | ||
141 | |||
142 | eeprom: eeprom@51 { | ||
143 | compatible = "atmel,24c128"; | ||
144 | reg = <0x51>; | ||
145 | pagesize = <32>; | ||
146 | }; | ||
147 | |||
148 | rtc: rtc@68 { | ||
149 | compatible = "stm,mt41t62"; | ||
150 | reg = <0x68>; | ||
151 | }; | ||
152 | }; | ||
153 | |||
154 | duart: serial@80074000 { | ||
155 | pinctrl-names = "default"; | ||
156 | pinctrl-0 = <&duart_pins_a>; | ||
157 | status = "okay"; | ||
158 | }; | ||
159 | |||
160 | auart0: serial@8006a000 { | ||
161 | pinctrl-names = "default"; | ||
162 | pinctrl-0 = <&auart0_2pins_a>; | ||
163 | status = "okay"; | ||
164 | }; | ||
165 | |||
166 | auart3: serial@80070000 { | ||
167 | pinctrl-names = "default"; | ||
168 | pinctrl-0 = <&auart3_pins_a>; | ||
169 | status = "okay"; | ||
170 | }; | ||
171 | }; | ||
172 | }; | ||
173 | |||
174 | ahb@80080000 { | ||
175 | mac0: ethernet@800f0000 { | ||
176 | phy-mode = "rmii"; | ||
177 | pinctrl-names = "default"; | ||
178 | pinctrl-0 = <&mac0_pins_a>; | ||
179 | phy-reset-gpios = <&gpio3 11 0>; | ||
180 | status = "okay"; | ||
181 | }; | ||
182 | |||
183 | mac1: ethernet@800f4000 { | ||
184 | phy-mode = "rmii"; | ||
185 | pinctrl-names = "default"; | ||
186 | pinctrl-0 = <&mac1_pins_a>; | ||
187 | status = "okay"; | ||
188 | }; | ||
189 | }; | ||
190 | |||
191 | regulators { | ||
192 | compatible = "simple-bus"; | ||
193 | |||
194 | reg_3p3v: 3p3v { | ||
195 | compatible = "regulator-fixed"; | ||
196 | regulator-name = "3P3V"; | ||
197 | regulator-min-microvolt = <3300000>; | ||
198 | regulator-max-microvolt = <3300000>; | ||
199 | regulator-always-on; | ||
200 | }; | ||
201 | }; | ||
202 | |||
203 | sound { | ||
204 | compatible = "denx,m28evk-sgtl5000", | ||
205 | "fsl,mxs-audio-sgtl5000"; | ||
206 | model = "m28evk-sgtl5000"; | ||
207 | saif-controllers = <&saif0 &saif1>; | ||
208 | audio-codec = <&sgtl5000>; | ||
209 | }; | ||
210 | }; | ||
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts new file mode 100644 index 000000000000..62bf767409a6 --- /dev/null +++ b/arch/arm/boot/dts/imx28-tx28.dts | |||
@@ -0,0 +1,97 @@ | |||
1 | /dts-v1/; | ||
2 | /include/ "imx28.dtsi" | ||
3 | |||
4 | / { | ||
5 | model = "Ka-Ro electronics TX28 module"; | ||
6 | compatible = "karo,tx28", "fsl,imx28"; | ||
7 | |||
8 | memory { | ||
9 | reg = <0x40000000 0x08000000>; | ||
10 | }; | ||
11 | |||
12 | apb@80000000 { | ||
13 | apbh@80000000 { | ||
14 | ssp0: ssp@80010000 { | ||
15 | compatible = "fsl,imx28-mmc"; | ||
16 | pinctrl-names = "default"; | ||
17 | pinctrl-0 = <&mmc0_4bit_pins_a | ||
18 | &mmc0_cd_cfg | ||
19 | &mmc0_sck_cfg>; | ||
20 | bus-width = <4>; | ||
21 | status = "okay"; | ||
22 | }; | ||
23 | |||
24 | pinctrl@80018000 { | ||
25 | pinctrl-names = "default"; | ||
26 | pinctrl-0 = <&hog_pins_a>; | ||
27 | |||
28 | hog_pins_a: hog-gpios@0 { | ||
29 | reg = <0>; | ||
30 | fsl,pinmux-ids = < | ||
31 | 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ | ||
32 | >; | ||
33 | fsl,drive-strength = <0>; | ||
34 | fsl,voltage = <1>; | ||
35 | fsl,pull-up = <0>; | ||
36 | }; | ||
37 | }; | ||
38 | }; | ||
39 | |||
40 | apbx@80040000 { | ||
41 | i2c0: i2c@80058000 { | ||
42 | pinctrl-names = "default"; | ||
43 | pinctrl-0 = <&i2c0_pins_a>; | ||
44 | status = "okay"; | ||
45 | |||
46 | ds1339: rtc@68 { | ||
47 | compatible = "mxim,ds1339"; | ||
48 | reg = <0x68>; | ||
49 | }; | ||
50 | }; | ||
51 | |||
52 | pwm: pwm@80064000 { | ||
53 | pinctrl-names = "default"; | ||
54 | pinctrl-0 = <&pwm0_pins_a>; | ||
55 | status = "okay"; | ||
56 | }; | ||
57 | |||
58 | duart: serial@80074000 { | ||
59 | pinctrl-names = "default"; | ||
60 | pinctrl-0 = <&duart_4pins_a>; | ||
61 | status = "okay"; | ||
62 | }; | ||
63 | |||
64 | auart1: serial@8006c000 { | ||
65 | pinctrl-names = "default"; | ||
66 | pinctrl-0 = <&auart1_pins_a>; | ||
67 | status = "okay"; | ||
68 | }; | ||
69 | }; | ||
70 | }; | ||
71 | |||
72 | ahb@80080000 { | ||
73 | mac0: ethernet@800f0000 { | ||
74 | phy-mode = "rmii"; | ||
75 | pinctrl-names = "default"; | ||
76 | pinctrl-0 = <&mac0_pins_a>; | ||
77 | status = "okay"; | ||
78 | }; | ||
79 | }; | ||
80 | |||
81 | leds { | ||
82 | compatible = "gpio-leds"; | ||
83 | |||
84 | user { | ||
85 | label = "Heartbeat"; | ||
86 | gpios = <&gpio4 10 0>; | ||
87 | linux,default-trigger = "heartbeat"; | ||
88 | }; | ||
89 | }; | ||
90 | |||
91 | backlight { | ||
92 | compatible = "pwm-backlight"; | ||
93 | pwms = <&pwm 0 5000000>; | ||
94 | brightness-levels = <0 4 8 16 32 64 128 255>; | ||
95 | default-brightness-level = <6>; | ||
96 | }; | ||
97 | }; | ||
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 4634cb861a59..915db89e3644 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi | |||
@@ -22,6 +22,11 @@ | |||
22 | gpio4 = &gpio4; | 22 | gpio4 = &gpio4; |
23 | saif0 = &saif0; | 23 | saif0 = &saif0; |
24 | saif1 = &saif1; | 24 | saif1 = &saif1; |
25 | serial0 = &auart0; | ||
26 | serial1 = &auart1; | ||
27 | serial2 = &auart2; | ||
28 | serial3 = &auart3; | ||
29 | serial4 = &auart4; | ||
25 | }; | 30 | }; |
26 | 31 | ||
27 | cpus { | 32 | cpus { |
@@ -68,15 +73,15 @@ | |||
68 | status = "disabled"; | 73 | status = "disabled"; |
69 | }; | 74 | }; |
70 | 75 | ||
71 | bch@8000a000 { | 76 | gpmi-nand@8000c000 { |
72 | reg = <0x8000a000 2000>; | 77 | compatible = "fsl,imx28-gpmi-nand"; |
73 | interrupts = <41>; | 78 | #address-cells = <1>; |
74 | status = "disabled"; | 79 | #size-cells = <1>; |
75 | }; | 80 | reg = <0x8000c000 2000>, <0x8000a000 2000>; |
76 | 81 | reg-names = "gpmi-nand", "bch"; | |
77 | gpmi@8000c000 { | 82 | interrupts = <88>, <41>; |
78 | reg = <0x8000c000 2000>; | 83 | interrupt-names = "gpmi-dma", "bch"; |
79 | interrupts = <42 88>; | 84 | fsl,gpmi-dma-channel = <4>; |
80 | status = "disabled"; | 85 | status = "disabled"; |
81 | }; | 86 | }; |
82 | 87 | ||
@@ -161,7 +166,150 @@ | |||
161 | 166 | ||
162 | duart_pins_a: duart@0 { | 167 | duart_pins_a: duart@0 { |
163 | reg = <0>; | 168 | reg = <0>; |
164 | fsl,pinmux-ids = <0x3102 0x3112>; | 169 | fsl,pinmux-ids = < |
170 | 0x3102 /* MX28_PAD_PWM0__DUART_RX */ | ||
171 | 0x3112 /* MX28_PAD_PWM1__DUART_TX */ | ||
172 | >; | ||
173 | fsl,drive-strength = <0>; | ||
174 | fsl,voltage = <1>; | ||
175 | fsl,pull-up = <0>; | ||
176 | }; | ||
177 | |||
178 | duart_pins_b: duart@1 { | ||
179 | reg = <1>; | ||
180 | fsl,pinmux-ids = < | ||
181 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ | ||
182 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ | ||
183 | >; | ||
184 | fsl,drive-strength = <0>; | ||
185 | fsl,voltage = <1>; | ||
186 | fsl,pull-up = <0>; | ||
187 | }; | ||
188 | |||
189 | duart_4pins_a: duart-4pins@0 { | ||
190 | reg = <0>; | ||
191 | fsl,pinmux-ids = < | ||
192 | 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ | ||
193 | 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ | ||
194 | 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ | ||
195 | 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ | ||
196 | >; | ||
197 | fsl,drive-strength = <0>; | ||
198 | fsl,voltage = <1>; | ||
199 | fsl,pull-up = <0>; | ||
200 | }; | ||
201 | |||
202 | gpmi_pins_a: gpmi-nand@0 { | ||
203 | reg = <0>; | ||
204 | fsl,pinmux-ids = < | ||
205 | 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ | ||
206 | 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ | ||
207 | 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ | ||
208 | 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ | ||
209 | 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ | ||
210 | 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ | ||
211 | 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ | ||
212 | 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ | ||
213 | 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ | ||
214 | 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ | ||
215 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ | ||
216 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ | ||
217 | 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ | ||
218 | 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ | ||
219 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ | ||
220 | >; | ||
221 | fsl,drive-strength = <0>; | ||
222 | fsl,voltage = <1>; | ||
223 | fsl,pull-up = <0>; | ||
224 | }; | ||
225 | |||
226 | gpmi_status_cfg: gpmi-status-cfg { | ||
227 | fsl,pinmux-ids = < | ||
228 | 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ | ||
229 | 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ | ||
230 | 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ | ||
231 | >; | ||
232 | fsl,drive-strength = <2>; | ||
233 | }; | ||
234 | |||
235 | auart0_pins_a: auart0@0 { | ||
236 | reg = <0>; | ||
237 | fsl,pinmux-ids = < | ||
238 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ | ||
239 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ | ||
240 | 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ | ||
241 | 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ | ||
242 | >; | ||
243 | fsl,drive-strength = <0>; | ||
244 | fsl,voltage = <1>; | ||
245 | fsl,pull-up = <0>; | ||
246 | }; | ||
247 | |||
248 | auart0_2pins_a: auart0-2pins@0 { | ||
249 | reg = <0>; | ||
250 | fsl,pinmux-ids = < | ||
251 | 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ | ||
252 | 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ | ||
253 | >; | ||
254 | fsl,drive-strength = <0>; | ||
255 | fsl,voltage = <1>; | ||
256 | fsl,pull-up = <0>; | ||
257 | }; | ||
258 | |||
259 | auart1_pins_a: auart1@0 { | ||
260 | reg = <0>; | ||
261 | fsl,pinmux-ids = < | ||
262 | 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ | ||
263 | 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ | ||
264 | 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ | ||
265 | 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ | ||
266 | >; | ||
267 | fsl,drive-strength = <0>; | ||
268 | fsl,voltage = <1>; | ||
269 | fsl,pull-up = <0>; | ||
270 | }; | ||
271 | |||
272 | auart1_2pins_a: auart1-2pins@0 { | ||
273 | reg = <0>; | ||
274 | fsl,pinmux-ids = < | ||
275 | 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ | ||
276 | 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ | ||
277 | >; | ||
278 | fsl,drive-strength = <0>; | ||
279 | fsl,voltage = <1>; | ||
280 | fsl,pull-up = <0>; | ||
281 | }; | ||
282 | |||
283 | auart2_2pins_a: auart2-2pins@0 { | ||
284 | reg = <0>; | ||
285 | fsl,pinmux-ids = < | ||
286 | 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ | ||
287 | 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ | ||
288 | >; | ||
289 | fsl,drive-strength = <0>; | ||
290 | fsl,voltage = <1>; | ||
291 | fsl,pull-up = <0>; | ||
292 | }; | ||
293 | |||
294 | auart3_pins_a: auart3@0 { | ||
295 | reg = <0>; | ||
296 | fsl,pinmux-ids = < | ||
297 | 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ | ||
298 | 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ | ||
299 | 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ | ||
300 | 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ | ||
301 | >; | ||
302 | fsl,drive-strength = <0>; | ||
303 | fsl,voltage = <1>; | ||
304 | fsl,pull-up = <0>; | ||
305 | }; | ||
306 | |||
307 | auart3_2pins_a: auart3-2pins@0 { | ||
308 | reg = <0>; | ||
309 | fsl,pinmux-ids = < | ||
310 | 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ | ||
311 | 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ | ||
312 | >; | ||
165 | fsl,drive-strength = <0>; | 313 | fsl,drive-strength = <0>; |
166 | fsl,voltage = <1>; | 314 | fsl,voltage = <1>; |
167 | fsl,pull-up = <0>; | 315 | fsl,pull-up = <0>; |
@@ -169,9 +317,17 @@ | |||
169 | 317 | ||
170 | mac0_pins_a: mac0@0 { | 318 | mac0_pins_a: mac0@0 { |
171 | reg = <0>; | 319 | reg = <0>; |
172 | fsl,pinmux-ids = <0x4000 0x4010 0x4020 | 320 | fsl,pinmux-ids = < |
173 | 0x4030 0x4040 0x4060 0x4070 | 321 | 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ |
174 | 0x4080 0x4100>; | 322 | 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ |
323 | 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ | ||
324 | 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ | ||
325 | 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ | ||
326 | 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ | ||
327 | 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ | ||
328 | 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ | ||
329 | 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ | ||
330 | >; | ||
175 | fsl,drive-strength = <1>; | 331 | fsl,drive-strength = <1>; |
176 | fsl,voltage = <1>; | 332 | fsl,voltage = <1>; |
177 | fsl,pull-up = <1>; | 333 | fsl,pull-up = <1>; |
@@ -179,8 +335,14 @@ | |||
179 | 335 | ||
180 | mac1_pins_a: mac1@0 { | 336 | mac1_pins_a: mac1@0 { |
181 | reg = <0>; | 337 | reg = <0>; |
182 | fsl,pinmux-ids = <0x40f1 0x4091 0x40a1 | 338 | fsl,pinmux-ids = < |
183 | 0x40e1 0x40b1 0x40c1>; | 339 | 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ |
340 | 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ | ||
341 | 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ | ||
342 | 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ | ||
343 | 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ | ||
344 | 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ | ||
345 | >; | ||
184 | fsl,drive-strength = <1>; | 346 | fsl,drive-strength = <1>; |
185 | fsl,voltage = <1>; | 347 | fsl,voltage = <1>; |
186 | fsl,pull-up = <1>; | 348 | fsl,pull-up = <1>; |
@@ -188,28 +350,61 @@ | |||
188 | 350 | ||
189 | mmc0_8bit_pins_a: mmc0-8bit@0 { | 351 | mmc0_8bit_pins_a: mmc0-8bit@0 { |
190 | reg = <0>; | 352 | reg = <0>; |
191 | fsl,pinmux-ids = <0x2000 0x2010 0x2020 | 353 | fsl,pinmux-ids = < |
192 | 0x2030 0x2040 0x2050 0x2060 | 354 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ |
193 | 0x2070 0x2080 0x2090 0x20a0>; | 355 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ |
356 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ | ||
357 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ | ||
358 | 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ | ||
359 | 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ | ||
360 | 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ | ||
361 | 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ | ||
362 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ | ||
363 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | ||
364 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | ||
365 | >; | ||
366 | fsl,drive-strength = <1>; | ||
367 | fsl,voltage = <1>; | ||
368 | fsl,pull-up = <1>; | ||
369 | }; | ||
370 | |||
371 | mmc0_4bit_pins_a: mmc0-4bit@0 { | ||
372 | reg = <0>; | ||
373 | fsl,pinmux-ids = < | ||
374 | 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ | ||
375 | 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ | ||
376 | 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ | ||
377 | 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ | ||
378 | 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ | ||
379 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | ||
380 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | ||
381 | >; | ||
194 | fsl,drive-strength = <1>; | 382 | fsl,drive-strength = <1>; |
195 | fsl,voltage = <1>; | 383 | fsl,voltage = <1>; |
196 | fsl,pull-up = <1>; | 384 | fsl,pull-up = <1>; |
197 | }; | 385 | }; |
198 | 386 | ||
199 | mmc0_cd_cfg: mmc0-cd-cfg { | 387 | mmc0_cd_cfg: mmc0-cd-cfg { |
200 | fsl,pinmux-ids = <0x2090>; | 388 | fsl,pinmux-ids = < |
389 | 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ | ||
390 | >; | ||
201 | fsl,pull-up = <0>; | 391 | fsl,pull-up = <0>; |
202 | }; | 392 | }; |
203 | 393 | ||
204 | mmc0_sck_cfg: mmc0-sck-cfg { | 394 | mmc0_sck_cfg: mmc0-sck-cfg { |
205 | fsl,pinmux-ids = <0x20a0>; | 395 | fsl,pinmux-ids = < |
396 | 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ | ||
397 | >; | ||
206 | fsl,drive-strength = <2>; | 398 | fsl,drive-strength = <2>; |
207 | fsl,pull-up = <0>; | 399 | fsl,pull-up = <0>; |
208 | }; | 400 | }; |
209 | 401 | ||
210 | i2c0_pins_a: i2c0@0 { | 402 | i2c0_pins_a: i2c0@0 { |
211 | reg = <0>; | 403 | reg = <0>; |
212 | fsl,pinmux-ids = <0x3180 0x3190>; | 404 | fsl,pinmux-ids = < |
405 | 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ | ||
406 | 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ | ||
407 | >; | ||
213 | fsl,drive-strength = <1>; | 408 | fsl,drive-strength = <1>; |
214 | fsl,voltage = <1>; | 409 | fsl,voltage = <1>; |
215 | fsl,pull-up = <1>; | 410 | fsl,pull-up = <1>; |
@@ -217,8 +412,12 @@ | |||
217 | 412 | ||
218 | saif0_pins_a: saif0@0 { | 413 | saif0_pins_a: saif0@0 { |
219 | reg = <0>; | 414 | reg = <0>; |
220 | fsl,pinmux-ids = | 415 | fsl,pinmux-ids = < |
221 | <0x3140 0x3150 0x3160 0x3170>; | 416 | 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ |
417 | 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ | ||
418 | 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ | ||
419 | 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ | ||
420 | >; | ||
222 | fsl,drive-strength = <2>; | 421 | fsl,drive-strength = <2>; |
223 | fsl,voltage = <1>; | 422 | fsl,voltage = <1>; |
224 | fsl,pull-up = <1>; | 423 | fsl,pull-up = <1>; |
@@ -226,11 +425,88 @@ | |||
226 | 425 | ||
227 | saif1_pins_a: saif1@0 { | 426 | saif1_pins_a: saif1@0 { |
228 | reg = <0>; | 427 | reg = <0>; |
229 | fsl,pinmux-ids = <0x31a0>; | 428 | fsl,pinmux-ids = < |
429 | 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ | ||
430 | >; | ||
230 | fsl,drive-strength = <2>; | 431 | fsl,drive-strength = <2>; |
231 | fsl,voltage = <1>; | 432 | fsl,voltage = <1>; |
232 | fsl,pull-up = <1>; | 433 | fsl,pull-up = <1>; |
233 | }; | 434 | }; |
435 | |||
436 | pwm0_pins_a: pwm0@0 { | ||
437 | reg = <0>; | ||
438 | fsl,pinmux-ids = < | ||
439 | 0x3100 /* MX28_PAD_PWM0__PWM_0 */ | ||
440 | >; | ||
441 | fsl,drive-strength = <0>; | ||
442 | fsl,voltage = <1>; | ||
443 | fsl,pull-up = <0>; | ||
444 | }; | ||
445 | |||
446 | pwm2_pins_a: pwm2@0 { | ||
447 | reg = <0>; | ||
448 | fsl,pinmux-ids = < | ||
449 | 0x3120 /* MX28_PAD_PWM2__PWM_2 */ | ||
450 | >; | ||
451 | fsl,drive-strength = <0>; | ||
452 | fsl,voltage = <1>; | ||
453 | fsl,pull-up = <0>; | ||
454 | }; | ||
455 | |||
456 | lcdif_24bit_pins_a: lcdif-24bit@0 { | ||
457 | reg = <0>; | ||
458 | fsl,pinmux-ids = < | ||
459 | 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ | ||
460 | 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ | ||
461 | 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ | ||
462 | 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ | ||
463 | 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ | ||
464 | 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ | ||
465 | 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ | ||
466 | 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ | ||
467 | 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ | ||
468 | 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ | ||
469 | 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ | ||
470 | 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ | ||
471 | 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ | ||
472 | 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ | ||
473 | 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ | ||
474 | 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ | ||
475 | 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ | ||
476 | 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ | ||
477 | 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ | ||
478 | 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ | ||
479 | 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ | ||
480 | 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ | ||
481 | 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ | ||
482 | 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ | ||
483 | >; | ||
484 | fsl,drive-strength = <0>; | ||
485 | fsl,voltage = <1>; | ||
486 | fsl,pull-up = <0>; | ||
487 | }; | ||
488 | |||
489 | can0_pins_a: can0@0 { | ||
490 | reg = <0>; | ||
491 | fsl,pinmux-ids = < | ||
492 | 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ | ||
493 | 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ | ||
494 | >; | ||
495 | fsl,drive-strength = <0>; | ||
496 | fsl,voltage = <1>; | ||
497 | fsl,pull-up = <0>; | ||
498 | }; | ||
499 | |||
500 | can1_pins_a: can1@0 { | ||
501 | reg = <0>; | ||
502 | fsl,pinmux-ids = < | ||
503 | 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ | ||
504 | 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ | ||
505 | >; | ||
506 | fsl,drive-strength = <0>; | ||
507 | fsl,voltage = <1>; | ||
508 | fsl,pull-up = <0>; | ||
509 | }; | ||
234 | }; | 510 | }; |
235 | 511 | ||
236 | digctl@8001c000 { | 512 | digctl@8001c000 { |
@@ -272,18 +548,21 @@ | |||
272 | }; | 548 | }; |
273 | 549 | ||
274 | lcdif@80030000 { | 550 | lcdif@80030000 { |
551 | compatible = "fsl,imx28-lcdif"; | ||
275 | reg = <0x80030000 2000>; | 552 | reg = <0x80030000 2000>; |
276 | interrupts = <38 86>; | 553 | interrupts = <38 86>; |
277 | status = "disabled"; | 554 | status = "disabled"; |
278 | }; | 555 | }; |
279 | 556 | ||
280 | can0: can@80032000 { | 557 | can0: can@80032000 { |
558 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | ||
281 | reg = <0x80032000 2000>; | 559 | reg = <0x80032000 2000>; |
282 | interrupts = <8>; | 560 | interrupts = <8>; |
283 | status = "disabled"; | 561 | status = "disabled"; |
284 | }; | 562 | }; |
285 | 563 | ||
286 | can1: can@80034000 { | 564 | can1: can@80034000 { |
565 | compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; | ||
287 | reg = <0x80034000 2000>; | 566 | reg = <0x80034000 2000>; |
288 | interrupts = <9>; | 567 | interrupts = <9>; |
289 | status = "disabled"; | 568 | status = "disabled"; |
@@ -370,9 +649,9 @@ | |||
370 | }; | 649 | }; |
371 | 650 | ||
372 | rtc@80056000 { | 651 | rtc@80056000 { |
652 | compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; | ||
373 | reg = <0x80056000 2000>; | 653 | reg = <0x80056000 2000>; |
374 | interrupts = <28 29>; | 654 | interrupts = <29>; |
375 | status = "disabled"; | ||
376 | }; | 655 | }; |
377 | 656 | ||
378 | i2c0: i2c@80058000 { | 657 | i2c0: i2c@80058000 { |
@@ -393,8 +672,11 @@ | |||
393 | status = "disabled"; | 672 | status = "disabled"; |
394 | }; | 673 | }; |
395 | 674 | ||
396 | pwm@80064000 { | 675 | pwm: pwm@80064000 { |
676 | compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; | ||
397 | reg = <0x80064000 2000>; | 677 | reg = <0x80064000 2000>; |
678 | #pwm-cells = <2>; | ||
679 | fsl,pwm-number = <8>; | ||
398 | status = "disabled"; | 680 | status = "disabled"; |
399 | }; | 681 | }; |
400 | 682 | ||
@@ -404,30 +686,35 @@ | |||
404 | }; | 686 | }; |
405 | 687 | ||
406 | auart0: serial@8006a000 { | 688 | auart0: serial@8006a000 { |
689 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
407 | reg = <0x8006a000 0x2000>; | 690 | reg = <0x8006a000 0x2000>; |
408 | interrupts = <112 70 71>; | 691 | interrupts = <112 70 71>; |
409 | status = "disabled"; | 692 | status = "disabled"; |
410 | }; | 693 | }; |
411 | 694 | ||
412 | auart1: serial@8006c000 { | 695 | auart1: serial@8006c000 { |
696 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
413 | reg = <0x8006c000 0x2000>; | 697 | reg = <0x8006c000 0x2000>; |
414 | interrupts = <113 72 73>; | 698 | interrupts = <113 72 73>; |
415 | status = "disabled"; | 699 | status = "disabled"; |
416 | }; | 700 | }; |
417 | 701 | ||
418 | auart2: serial@8006e000 { | 702 | auart2: serial@8006e000 { |
703 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
419 | reg = <0x8006e000 0x2000>; | 704 | reg = <0x8006e000 0x2000>; |
420 | interrupts = <114 74 75>; | 705 | interrupts = <114 74 75>; |
421 | status = "disabled"; | 706 | status = "disabled"; |
422 | }; | 707 | }; |
423 | 708 | ||
424 | auart3: serial@80070000 { | 709 | auart3: serial@80070000 { |
710 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
425 | reg = <0x80070000 0x2000>; | 711 | reg = <0x80070000 0x2000>; |
426 | interrupts = <115 76 77>; | 712 | interrupts = <115 76 77>; |
427 | status = "disabled"; | 713 | status = "disabled"; |
428 | }; | 714 | }; |
429 | 715 | ||
430 | auart4: serial@80072000 { | 716 | auart4: serial@80072000 { |
717 | compatible = "fsl,imx28-auart", "fsl,imx23-auart"; | ||
431 | reg = <0x80072000 0x2000>; | 718 | reg = <0x80072000 0x2000>; |
432 | interrupts = <116 78 79>; | 719 | interrupts = <116 78 79>; |
433 | status = "disabled"; | 720 | status = "disabled"; |
@@ -441,11 +728,13 @@ | |||
441 | }; | 728 | }; |
442 | 729 | ||
443 | usbphy0: usbphy@8007c000 { | 730 | usbphy0: usbphy@8007c000 { |
731 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | ||
444 | reg = <0x8007c000 0x2000>; | 732 | reg = <0x8007c000 0x2000>; |
445 | status = "disabled"; | 733 | status = "disabled"; |
446 | }; | 734 | }; |
447 | 735 | ||
448 | usbphy1: usbphy@8007e000 { | 736 | usbphy1: usbphy@8007e000 { |
737 | compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; | ||
449 | reg = <0x8007e000 0x2000>; | 738 | reg = <0x8007e000 0x2000>; |
450 | status = "disabled"; | 739 | status = "disabled"; |
451 | }; | 740 | }; |
@@ -459,13 +748,19 @@ | |||
459 | reg = <0x80080000 0x80000>; | 748 | reg = <0x80080000 0x80000>; |
460 | ranges; | 749 | ranges; |
461 | 750 | ||
462 | usbctrl0: usbctrl@80080000 { | 751 | usb0: usb@80080000 { |
752 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | ||
463 | reg = <0x80080000 0x10000>; | 753 | reg = <0x80080000 0x10000>; |
754 | interrupts = <93>; | ||
755 | fsl,usbphy = <&usbphy0>; | ||
464 | status = "disabled"; | 756 | status = "disabled"; |
465 | }; | 757 | }; |
466 | 758 | ||
467 | usbctrl1: usbctrl@80090000 { | 759 | usb1: usb@80090000 { |
760 | compatible = "fsl,imx28-usb", "fsl,imx27-usb"; | ||
468 | reg = <0x80090000 0x10000>; | 761 | reg = <0x80090000 0x10000>; |
762 | interrupts = <92>; | ||
763 | fsl,usbphy = <&usbphy1>; | ||
469 | status = "disabled"; | 764 | status = "disabled"; |
470 | }; | 765 | }; |
471 | 766 | ||
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts new file mode 100644 index 000000000000..24731cb78e8e --- /dev/null +++ b/arch/arm/boot/dts/imx31-bug.dts | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /dts-v1/; | ||
13 | /include/ "imx31.dtsi" | ||
14 | |||
15 | / { | ||
16 | model = "Buglabs i.MX31 Bug 1.x"; | ||
17 | compatible = "fsl,imx31-bug", "fsl,imx31"; | ||
18 | |||
19 | memory { | ||
20 | reg = <0x80000000 0x8000000>; /* 128M */ | ||
21 | }; | ||
22 | |||
23 | soc { | ||
24 | aips@43f00000 { /* AIPS1 */ | ||
25 | uart5: serial@43fb4000 { | ||
26 | fsl,uart-has-rtscts; | ||
27 | status = "okay"; | ||
28 | }; | ||
29 | }; | ||
30 | }; | ||
31 | }; | ||
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi new file mode 100644 index 000000000000..eef7099f3e3c --- /dev/null +++ b/arch/arm/boot/dts/imx31.dtsi | |||
@@ -0,0 +1,88 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | /include/ "skeleton.dtsi" | ||
13 | |||
14 | / { | ||
15 | aliases { | ||
16 | serial0 = &uart1; | ||
17 | serial1 = &uart2; | ||
18 | serial2 = &uart3; | ||
19 | serial3 = &uart4; | ||
20 | serial4 = &uart5; | ||
21 | }; | ||
22 | |||
23 | avic: avic-interrupt-controller@60000000 { | ||
24 | compatible = "fsl,imx31-avic", "fsl,avic"; | ||
25 | interrupt-controller; | ||
26 | #interrupt-cells = <1>; | ||
27 | reg = <0x60000000 0x100000>; | ||
28 | }; | ||
29 | |||
30 | soc { | ||
31 | #address-cells = <1>; | ||
32 | #size-cells = <1>; | ||
33 | compatible = "simple-bus"; | ||
34 | interrupt-parent = <&avic>; | ||
35 | ranges; | ||
36 | |||
37 | aips@43f00000 { /* AIPS1 */ | ||
38 | compatible = "fsl,aips-bus", "simple-bus"; | ||
39 | #address-cells = <1>; | ||
40 | #size-cells = <1>; | ||
41 | reg = <0x43f00000 0x100000>; | ||
42 | ranges; | ||
43 | |||
44 | uart1: serial@43f90000 { | ||
45 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | ||
46 | reg = <0x43f90000 0x4000>; | ||
47 | interrupts = <45>; | ||
48 | status = "disabled"; | ||
49 | }; | ||
50 | |||
51 | uart2: serial@43f94000 { | ||
52 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | ||
53 | reg = <0x43f94000 0x4000>; | ||
54 | interrupts = <32>; | ||
55 | status = "disabled"; | ||
56 | }; | ||
57 | |||
58 | uart4: serial@43fb0000 { | ||
59 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | ||
60 | reg = <0x43fb0000 0x4000>; | ||
61 | interrupts = <46>; | ||
62 | status = "disabled"; | ||
63 | }; | ||
64 | |||
65 | uart5: serial@43fb4000 { | ||
66 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | ||
67 | reg = <0x43fb4000 0x4000>; | ||
68 | interrupts = <47>; | ||
69 | status = "disabled"; | ||
70 | }; | ||
71 | }; | ||
72 | |||
73 | spba@50000000 { | ||
74 | compatible = "fsl,spba-bus", "simple-bus"; | ||
75 | #address-cells = <1>; | ||
76 | #size-cells = <1>; | ||
77 | reg = <0x50000000 0x100000>; | ||
78 | ranges; | ||
79 | |||
80 | uart3: serial@5000c000 { | ||
81 | compatible = "fsl,imx31-uart", "fsl,imx21-uart"; | ||
82 | reg = <0x5000c000 0x4000>; | ||
83 | interrupts = <18>; | ||
84 | status = "disabled"; | ||
85 | }; | ||
86 | }; | ||
87 | }; | ||
88 | }; | ||
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index bfa65abe8ef2..922adefdd291 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi | |||
@@ -133,7 +133,7 @@ | |||
133 | gpio-controller; | 133 | gpio-controller; |
134 | #gpio-cells = <2>; | 134 | #gpio-cells = <2>; |
135 | interrupt-controller; | 135 | interrupt-controller; |
136 | #interrupt-cells = <1>; | 136 | #interrupt-cells = <2>; |
137 | }; | 137 | }; |
138 | 138 | ||
139 | gpio2: gpio@73f88000 { | 139 | gpio2: gpio@73f88000 { |
@@ -143,7 +143,7 @@ | |||
143 | gpio-controller; | 143 | gpio-controller; |
144 | #gpio-cells = <2>; | 144 | #gpio-cells = <2>; |
145 | interrupt-controller; | 145 | interrupt-controller; |
146 | #interrupt-cells = <1>; | 146 | #interrupt-cells = <2>; |
147 | }; | 147 | }; |
148 | 148 | ||
149 | gpio3: gpio@73f8c000 { | 149 | gpio3: gpio@73f8c000 { |
@@ -153,7 +153,7 @@ | |||
153 | gpio-controller; | 153 | gpio-controller; |
154 | #gpio-cells = <2>; | 154 | #gpio-cells = <2>; |
155 | interrupt-controller; | 155 | interrupt-controller; |
156 | #interrupt-cells = <1>; | 156 | #interrupt-cells = <2>; |
157 | }; | 157 | }; |
158 | 158 | ||
159 | gpio4: gpio@73f90000 { | 159 | gpio4: gpio@73f90000 { |
@@ -163,7 +163,7 @@ | |||
163 | gpio-controller; | 163 | gpio-controller; |
164 | #gpio-cells = <2>; | 164 | #gpio-cells = <2>; |
165 | interrupt-controller; | 165 | interrupt-controller; |
166 | #interrupt-cells = <1>; | 166 | #interrupt-cells = <2>; |
167 | }; | 167 | }; |
168 | 168 | ||
169 | wdog@73f98000 { /* WDOG1 */ | 169 | wdog@73f98000 { /* WDOG1 */ |
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index e3e869470cd3..4e735edc78ed 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
@@ -135,7 +135,7 @@ | |||
135 | gpio-controller; | 135 | gpio-controller; |
136 | #gpio-cells = <2>; | 136 | #gpio-cells = <2>; |
137 | interrupt-controller; | 137 | interrupt-controller; |
138 | #interrupt-cells = <1>; | 138 | #interrupt-cells = <2>; |
139 | }; | 139 | }; |
140 | 140 | ||
141 | gpio2: gpio@53f88000 { | 141 | gpio2: gpio@53f88000 { |
@@ -145,7 +145,7 @@ | |||
145 | gpio-controller; | 145 | gpio-controller; |
146 | #gpio-cells = <2>; | 146 | #gpio-cells = <2>; |
147 | interrupt-controller; | 147 | interrupt-controller; |
148 | #interrupt-cells = <1>; | 148 | #interrupt-cells = <2>; |
149 | }; | 149 | }; |
150 | 150 | ||
151 | gpio3: gpio@53f8c000 { | 151 | gpio3: gpio@53f8c000 { |
@@ -155,7 +155,7 @@ | |||
155 | gpio-controller; | 155 | gpio-controller; |
156 | #gpio-cells = <2>; | 156 | #gpio-cells = <2>; |
157 | interrupt-controller; | 157 | interrupt-controller; |
158 | #interrupt-cells = <1>; | 158 | #interrupt-cells = <2>; |
159 | }; | 159 | }; |
160 | 160 | ||
161 | gpio4: gpio@53f90000 { | 161 | gpio4: gpio@53f90000 { |
@@ -165,7 +165,7 @@ | |||
165 | gpio-controller; | 165 | gpio-controller; |
166 | #gpio-cells = <2>; | 166 | #gpio-cells = <2>; |
167 | interrupt-controller; | 167 | interrupt-controller; |
168 | #interrupt-cells = <1>; | 168 | #interrupt-cells = <2>; |
169 | }; | 169 | }; |
170 | 170 | ||
171 | wdog@53f98000 { /* WDOG1 */ | 171 | wdog@53f98000 { /* WDOG1 */ |
@@ -203,7 +203,7 @@ | |||
203 | gpio-controller; | 203 | gpio-controller; |
204 | #gpio-cells = <2>; | 204 | #gpio-cells = <2>; |
205 | interrupt-controller; | 205 | interrupt-controller; |
206 | #interrupt-cells = <1>; | 206 | #interrupt-cells = <2>; |
207 | }; | 207 | }; |
208 | 208 | ||
209 | gpio6: gpio@53fe0000 { | 209 | gpio6: gpio@53fe0000 { |
@@ -213,7 +213,7 @@ | |||
213 | gpio-controller; | 213 | gpio-controller; |
214 | #gpio-cells = <2>; | 214 | #gpio-cells = <2>; |
215 | interrupt-controller; | 215 | interrupt-controller; |
216 | #interrupt-cells = <1>; | 216 | #interrupt-cells = <2>; |
217 | }; | 217 | }; |
218 | 218 | ||
219 | gpio7: gpio@53fe4000 { | 219 | gpio7: gpio@53fe4000 { |
@@ -223,7 +223,7 @@ | |||
223 | gpio-controller; | 223 | gpio-controller; |
224 | #gpio-cells = <2>; | 224 | #gpio-cells = <2>; |
225 | interrupt-controller; | 225 | interrupt-controller; |
226 | #interrupt-cells = <1>; | 226 | #interrupt-cells = <2>; |
227 | }; | 227 | }; |
228 | 228 | ||
229 | i2c@53fec000 { /* I2C3 */ | 229 | i2c@53fec000 { /* I2C3 */ |
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index db4c6096c562..d792581672cc 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts | |||
@@ -22,6 +22,12 @@ | |||
22 | }; | 22 | }; |
23 | 23 | ||
24 | soc { | 24 | soc { |
25 | gpmi-nand@00112000 { | ||
26 | pinctrl-names = "default"; | ||
27 | pinctrl-0 = <&pinctrl_gpmi_nand_1>; | ||
28 | status = "disabled"; /* gpmi nand conflicts with SD */ | ||
29 | }; | ||
30 | |||
25 | aips-bus@02100000 { /* AIPS2 */ | 31 | aips-bus@02100000 { /* AIPS2 */ |
26 | ethernet@02188000 { | 32 | ethernet@02188000 { |
27 | phy-mode = "rgmii"; | 33 | phy-mode = "rgmii"; |
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts index e0ec92973e7e..d42e851ceb97 100644 --- a/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/arch/arm/boot/dts/imx6q-sabrelite.dts | |||
@@ -27,6 +27,8 @@ | |||
27 | ecspi@02008000 { /* eCSPI1 */ | 27 | ecspi@02008000 { /* eCSPI1 */ |
28 | fsl,spi-num-chipselects = <1>; | 28 | fsl,spi-num-chipselects = <1>; |
29 | cs-gpios = <&gpio3 19 0>; | 29 | cs-gpios = <&gpio3 19 0>; |
30 | pinctrl-names = "default"; | ||
31 | pinctrl-0 = <&pinctrl_ecspi1_1>; | ||
30 | status = "okay"; | 32 | status = "okay"; |
31 | 33 | ||
32 | flash: m25p80@0 { | 34 | flash: m25p80@0 { |
@@ -42,9 +44,31 @@ | |||
42 | }; | 44 | }; |
43 | }; | 45 | }; |
44 | 46 | ||
47 | iomuxc@020e0000 { | ||
48 | pinctrl-names = "default"; | ||
49 | pinctrl-0 = <&pinctrl_gpio_hog>; | ||
50 | |||
51 | gpios { | ||
52 | pinctrl_gpio_hog: gpiohog { | ||
53 | fsl,pins = < | ||
54 | 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ | ||
55 | 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ | ||
56 | >; | ||
57 | }; | ||
58 | }; | ||
59 | }; | ||
45 | }; | 60 | }; |
46 | 61 | ||
47 | aips-bus@02100000 { /* AIPS2 */ | 62 | aips-bus@02100000 { /* AIPS2 */ |
63 | usb@02184000 { /* USB OTG */ | ||
64 | vbus-supply = <®_usb_otg_vbus>; | ||
65 | status = "okay"; | ||
66 | }; | ||
67 | |||
68 | usb@02184200 { /* USB1 */ | ||
69 | status = "okay"; | ||
70 | }; | ||
71 | |||
48 | ethernet@02188000 { | 72 | ethernet@02188000 { |
49 | phy-mode = "rgmii"; | 73 | phy-mode = "rgmii"; |
50 | phy-reset-gpios = <&gpio3 23 0>; | 74 | phy-reset-gpios = <&gpio3 23 0>; |
@@ -111,6 +135,15 @@ | |||
111 | regulator-max-microvolt = <3300000>; | 135 | regulator-max-microvolt = <3300000>; |
112 | regulator-always-on; | 136 | regulator-always-on; |
113 | }; | 137 | }; |
138 | |||
139 | reg_usb_otg_vbus: usb_otg_vbus { | ||
140 | compatible = "regulator-fixed"; | ||
141 | regulator-name = "usb_otg_vbus"; | ||
142 | regulator-min-microvolt = <5000000>; | ||
143 | regulator-max-microvolt = <5000000>; | ||
144 | gpio = <&gpio3 22 0>; | ||
145 | enable-active-high; | ||
146 | }; | ||
114 | }; | 147 | }; |
115 | 148 | ||
116 | sound { | 149 | sound { |
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 8c90cbac945f..c25d49584814 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi | |||
@@ -87,6 +87,23 @@ | |||
87 | interrupt-parent = <&intc>; | 87 | interrupt-parent = <&intc>; |
88 | ranges; | 88 | ranges; |
89 | 89 | ||
90 | dma-apbh@00110000 { | ||
91 | compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | ||
92 | reg = <0x00110000 0x2000>; | ||
93 | }; | ||
94 | |||
95 | gpmi-nand@00112000 { | ||
96 | compatible = "fsl,imx6q-gpmi-nand"; | ||
97 | #address-cells = <1>; | ||
98 | #size-cells = <1>; | ||
99 | reg = <0x00112000 0x2000>, <0x00114000 0x2000>; | ||
100 | reg-names = "gpmi-nand", "bch"; | ||
101 | interrupts = <0 13 0x04>, <0 15 0x04>; | ||
102 | interrupt-names = "gpmi-dma", "bch"; | ||
103 | fsl,gpmi-dma-channel = <0>; | ||
104 | status = "disabled"; | ||
105 | }; | ||
106 | |||
90 | timer@00a00600 { | 107 | timer@00a00600 { |
91 | compatible = "arm,cortex-a9-twd-timer"; | 108 | compatible = "arm,cortex-a9-twd-timer"; |
92 | reg = <0x00a00600 0x20>; | 109 | reg = <0x00a00600 0x20>; |
@@ -266,7 +283,7 @@ | |||
266 | gpio-controller; | 283 | gpio-controller; |
267 | #gpio-cells = <2>; | 284 | #gpio-cells = <2>; |
268 | interrupt-controller; | 285 | interrupt-controller; |
269 | #interrupt-cells = <1>; | 286 | #interrupt-cells = <2>; |
270 | }; | 287 | }; |
271 | 288 | ||
272 | gpio2: gpio@020a0000 { | 289 | gpio2: gpio@020a0000 { |
@@ -276,7 +293,7 @@ | |||
276 | gpio-controller; | 293 | gpio-controller; |
277 | #gpio-cells = <2>; | 294 | #gpio-cells = <2>; |
278 | interrupt-controller; | 295 | interrupt-controller; |
279 | #interrupt-cells = <1>; | 296 | #interrupt-cells = <2>; |
280 | }; | 297 | }; |
281 | 298 | ||
282 | gpio3: gpio@020a4000 { | 299 | gpio3: gpio@020a4000 { |
@@ -286,7 +303,7 @@ | |||
286 | gpio-controller; | 303 | gpio-controller; |
287 | #gpio-cells = <2>; | 304 | #gpio-cells = <2>; |
288 | interrupt-controller; | 305 | interrupt-controller; |
289 | #interrupt-cells = <1>; | 306 | #interrupt-cells = <2>; |
290 | }; | 307 | }; |
291 | 308 | ||
292 | gpio4: gpio@020a8000 { | 309 | gpio4: gpio@020a8000 { |
@@ -296,7 +313,7 @@ | |||
296 | gpio-controller; | 313 | gpio-controller; |
297 | #gpio-cells = <2>; | 314 | #gpio-cells = <2>; |
298 | interrupt-controller; | 315 | interrupt-controller; |
299 | #interrupt-cells = <1>; | 316 | #interrupt-cells = <2>; |
300 | }; | 317 | }; |
301 | 318 | ||
302 | gpio5: gpio@020ac000 { | 319 | gpio5: gpio@020ac000 { |
@@ -306,7 +323,7 @@ | |||
306 | gpio-controller; | 323 | gpio-controller; |
307 | #gpio-cells = <2>; | 324 | #gpio-cells = <2>; |
308 | interrupt-controller; | 325 | interrupt-controller; |
309 | #interrupt-cells = <1>; | 326 | #interrupt-cells = <2>; |
310 | }; | 327 | }; |
311 | 328 | ||
312 | gpio6: gpio@020b0000 { | 329 | gpio6: gpio@020b0000 { |
@@ -316,7 +333,7 @@ | |||
316 | gpio-controller; | 333 | gpio-controller; |
317 | #gpio-cells = <2>; | 334 | #gpio-cells = <2>; |
318 | interrupt-controller; | 335 | interrupt-controller; |
319 | #interrupt-cells = <1>; | 336 | #interrupt-cells = <2>; |
320 | }; | 337 | }; |
321 | 338 | ||
322 | gpio7: gpio@020b4000 { | 339 | gpio7: gpio@020b4000 { |
@@ -326,7 +343,7 @@ | |||
326 | gpio-controller; | 343 | gpio-controller; |
327 | #gpio-cells = <2>; | 344 | #gpio-cells = <2>; |
328 | interrupt-controller; | 345 | interrupt-controller; |
329 | #interrupt-cells = <1>; | 346 | #interrupt-cells = <2>; |
330 | }; | 347 | }; |
331 | 348 | ||
332 | kpp@020b8000 { | 349 | kpp@020b8000 { |
@@ -444,12 +461,14 @@ | |||
444 | }; | 461 | }; |
445 | }; | 462 | }; |
446 | 463 | ||
447 | usbphy@020c9000 { /* USBPHY1 */ | 464 | usbphy1: usbphy@020c9000 { |
465 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | ||
448 | reg = <0x020c9000 0x1000>; | 466 | reg = <0x020c9000 0x1000>; |
449 | interrupts = <0 44 0x04>; | 467 | interrupts = <0 44 0x04>; |
450 | }; | 468 | }; |
451 | 469 | ||
452 | usbphy@020ca000 { /* USBPHY2 */ | 470 | usbphy2: usbphy@020ca000 { |
471 | compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; | ||
453 | reg = <0x020ca000 0x1000>; | 472 | reg = <0x020ca000 0x1000>; |
454 | interrupts = <0 45 0x04>; | 473 | interrupts = <0 45 0x04>; |
455 | }; | 474 | }; |
@@ -495,6 +514,30 @@ | |||
495 | }; | 514 | }; |
496 | }; | 515 | }; |
497 | 516 | ||
517 | gpmi-nand { | ||
518 | pinctrl_gpmi_nand_1: gpmi-nand-1 { | ||
519 | fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ | ||
520 | 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ | ||
521 | 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ | ||
522 | 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ | ||
523 | 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ | ||
524 | 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ | ||
525 | 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ | ||
526 | 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ | ||
527 | 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ | ||
528 | 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ | ||
529 | 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ | ||
530 | 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ | ||
531 | 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ | ||
532 | 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ | ||
533 | 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ | ||
534 | 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ | ||
535 | 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ | ||
536 | 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ | ||
537 | 1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ | ||
538 | }; | ||
539 | }; | ||
540 | |||
498 | i2c1 { | 541 | i2c1 { |
499 | pinctrl_i2c1_1: i2c1grp-1 { | 542 | pinctrl_i2c1_1: i2c1grp-1 { |
500 | fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ | 543 | fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ |
@@ -538,6 +581,14 @@ | |||
538 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ | 581 | 1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ |
539 | }; | 582 | }; |
540 | }; | 583 | }; |
584 | |||
585 | ecspi1 { | ||
586 | pinctrl_ecspi1_1: ecspi1grp-1 { | ||
587 | fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ | ||
588 | 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ | ||
589 | 94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ | ||
590 | }; | ||
591 | }; | ||
541 | }; | 592 | }; |
542 | 593 | ||
543 | dcic@020e4000 { /* DCIC1 */ | 594 | dcic@020e4000 { /* DCIC1 */ |
@@ -573,6 +624,36 @@ | |||
573 | reg = <0x0217c000 0x4000>; | 624 | reg = <0x0217c000 0x4000>; |
574 | }; | 625 | }; |
575 | 626 | ||
627 | usb@02184000 { /* USB OTG */ | ||
628 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | ||
629 | reg = <0x02184000 0x200>; | ||
630 | interrupts = <0 43 0x04>; | ||
631 | fsl,usbphy = <&usbphy1>; | ||
632 | status = "disabled"; | ||
633 | }; | ||
634 | |||
635 | usb@02184200 { /* USB1 */ | ||
636 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | ||
637 | reg = <0x02184200 0x200>; | ||
638 | interrupts = <0 40 0x04>; | ||
639 | fsl,usbphy = <&usbphy2>; | ||
640 | status = "disabled"; | ||
641 | }; | ||
642 | |||
643 | usb@02184400 { /* USB2 */ | ||
644 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | ||
645 | reg = <0x02184400 0x200>; | ||
646 | interrupts = <0 41 0x04>; | ||
647 | status = "disabled"; | ||
648 | }; | ||
649 | |||
650 | usb@02184600 { /* USB3 */ | ||
651 | compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; | ||
652 | reg = <0x02184600 0x200>; | ||
653 | interrupts = <0 42 0x04>; | ||
654 | status = "disabled"; | ||
655 | }; | ||
656 | |||
576 | ethernet@02188000 { | 657 | ethernet@02188000 { |
577 | compatible = "fsl,imx6q-fec"; | 658 | compatible = "fsl,imx6q-fec"; |
578 | reg = <0x02188000 0x4000>; | 659 | reg = <0x02188000 0x4000>; |
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index 3f5dad801a98..e5ffe960dbf3 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi | |||
@@ -35,13 +35,14 @@ | |||
35 | slc: flash@20020000 { | 35 | slc: flash@20020000 { |
36 | compatible = "nxp,lpc3220-slc"; | 36 | compatible = "nxp,lpc3220-slc"; |
37 | reg = <0x20020000 0x1000>; | 37 | reg = <0x20020000 0x1000>; |
38 | status = "disable"; | 38 | status = "disabled"; |
39 | }; | 39 | }; |
40 | 40 | ||
41 | mlc: flash@200B0000 { | 41 | mlc: flash@200a8000 { |
42 | compatible = "nxp,lpc3220-mlc"; | 42 | compatible = "nxp,lpc3220-mlc"; |
43 | reg = <0x200B0000 0x1000>; | 43 | reg = <0x200a8000 0x11000>; |
44 | status = "disable"; | 44 | interrupts = <11 0>; |
45 | status = "disabled"; | ||
45 | }; | 46 | }; |
46 | 47 | ||
47 | dma@31000000 { | 48 | dma@31000000 { |
@@ -57,21 +58,21 @@ | |||
57 | compatible = "nxp,ohci-nxp", "usb-ohci"; | 58 | compatible = "nxp,ohci-nxp", "usb-ohci"; |
58 | reg = <0x31020000 0x300>; | 59 | reg = <0x31020000 0x300>; |
59 | interrupts = <0x3b 0>; | 60 | interrupts = <0x3b 0>; |
60 | status = "disable"; | 61 | status = "disabled"; |
61 | }; | 62 | }; |
62 | 63 | ||
63 | usbd@31020000 { | 64 | usbd@31020000 { |
64 | compatible = "nxp,lpc3220-udc"; | 65 | compatible = "nxp,lpc3220-udc"; |
65 | reg = <0x31020000 0x300>; | 66 | reg = <0x31020000 0x300>; |
66 | interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; | 67 | interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; |
67 | status = "disable"; | 68 | status = "disabled"; |
68 | }; | 69 | }; |
69 | 70 | ||
70 | clcd@31040000 { | 71 | clcd@31040000 { |
71 | compatible = "arm,pl110", "arm,primecell"; | 72 | compatible = "arm,pl110", "arm,primecell"; |
72 | reg = <0x31040000 0x1000>; | 73 | reg = <0x31040000 0x1000>; |
73 | interrupts = <0x0e 0>; | 74 | interrupts = <0x0e 0>; |
74 | status = "disable"; | 75 | status = "disabled"; |
75 | }; | 76 | }; |
76 | 77 | ||
77 | mac: ethernet@31060000 { | 78 | mac: ethernet@31060000 { |
@@ -114,9 +115,10 @@ | |||
114 | }; | 115 | }; |
115 | 116 | ||
116 | sd@20098000 { | 117 | sd@20098000 { |
117 | compatible = "arm,pl180", "arm,primecell"; | 118 | compatible = "arm,pl18x", "arm,primecell"; |
118 | reg = <0x20098000 0x1000>; | 119 | reg = <0x20098000 0x1000>; |
119 | interrupts = <0x0f 0>, <0x0d 0>; | 120 | interrupts = <0x0f 0>, <0x0d 0>; |
121 | status = "disabled"; | ||
120 | }; | 122 | }; |
121 | 123 | ||
122 | i2s1: i2s@2009C000 { | 124 | i2s1: i2s@2009C000 { |
@@ -124,24 +126,42 @@ | |||
124 | reg = <0x2009C000 0x1000>; | 126 | reg = <0x2009C000 0x1000>; |
125 | }; | 127 | }; |
126 | 128 | ||
129 | /* UART5 first since it is the default console, ttyS0 */ | ||
130 | uart5: serial@40090000 { | ||
131 | /* actually, ns16550a w/ 64 byte fifos! */ | ||
132 | compatible = "nxp,lpc3220-uart"; | ||
133 | reg = <0x40090000 0x1000>; | ||
134 | interrupts = <9 0>; | ||
135 | clock-frequency = <13000000>; | ||
136 | reg-shift = <2>; | ||
137 | status = "disabled"; | ||
138 | }; | ||
139 | |||
127 | uart3: serial@40080000 { | 140 | uart3: serial@40080000 { |
128 | compatible = "nxp,serial"; | 141 | compatible = "nxp,lpc3220-uart"; |
129 | reg = <0x40080000 0x1000>; | 142 | reg = <0x40080000 0x1000>; |
143 | interrupts = <7 0>; | ||
144 | clock-frequency = <13000000>; | ||
145 | reg-shift = <2>; | ||
146 | status = "disabled"; | ||
130 | }; | 147 | }; |
131 | 148 | ||
132 | uart4: serial@40088000 { | 149 | uart4: serial@40088000 { |
133 | compatible = "nxp,serial"; | 150 | compatible = "nxp,lpc3220-uart"; |
134 | reg = <0x40088000 0x1000>; | 151 | reg = <0x40088000 0x1000>; |
135 | }; | 152 | interrupts = <8 0>; |
136 | 153 | clock-frequency = <13000000>; | |
137 | uart5: serial@40090000 { | 154 | reg-shift = <2>; |
138 | compatible = "nxp,serial"; | 155 | status = "disabled"; |
139 | reg = <0x40090000 0x1000>; | ||
140 | }; | 156 | }; |
141 | 157 | ||
142 | uart6: serial@40098000 { | 158 | uart6: serial@40098000 { |
143 | compatible = "nxp,serial"; | 159 | compatible = "nxp,lpc3220-uart"; |
144 | reg = <0x40098000 0x1000>; | 160 | reg = <0x40098000 0x1000>; |
161 | interrupts = <10 0>; | ||
162 | clock-frequency = <13000000>; | ||
163 | reg-shift = <2>; | ||
164 | status = "disabled"; | ||
145 | }; | 165 | }; |
146 | 166 | ||
147 | i2c1: i2c@400A0000 { | 167 | i2c1: i2c@400A0000 { |
@@ -192,18 +212,24 @@ | |||
192 | }; | 212 | }; |
193 | 213 | ||
194 | uart1: serial@40014000 { | 214 | uart1: serial@40014000 { |
195 | compatible = "nxp,serial"; | 215 | compatible = "nxp,lpc3220-hsuart"; |
196 | reg = <0x40014000 0x1000>; | 216 | reg = <0x40014000 0x1000>; |
217 | interrupts = <26 0>; | ||
218 | status = "disabled"; | ||
197 | }; | 219 | }; |
198 | 220 | ||
199 | uart2: serial@40018000 { | 221 | uart2: serial@40018000 { |
200 | compatible = "nxp,serial"; | 222 | compatible = "nxp,lpc3220-hsuart"; |
201 | reg = <0x40018000 0x1000>; | 223 | reg = <0x40018000 0x1000>; |
224 | interrupts = <25 0>; | ||
225 | status = "disabled"; | ||
202 | }; | 226 | }; |
203 | 227 | ||
204 | uart7: serial@4001C000 { | 228 | uart7: serial@4001c000 { |
205 | compatible = "nxp,serial"; | 229 | compatible = "nxp,lpc3220-hsuart"; |
206 | reg = <0x4001C000 0x1000>; | 230 | reg = <0x4001c000 0x1000>; |
231 | interrupts = <24 0>; | ||
232 | status = "disabled"; | ||
207 | }; | 233 | }; |
208 | 234 | ||
209 | rtc@40024000 { | 235 | rtc@40024000 { |
@@ -235,21 +261,28 @@ | |||
235 | compatible = "nxp,lpc3220-adc"; | 261 | compatible = "nxp,lpc3220-adc"; |
236 | reg = <0x40048000 0x1000>; | 262 | reg = <0x40048000 0x1000>; |
237 | interrupts = <0x27 0>; | 263 | interrupts = <0x27 0>; |
238 | status = "disable"; | 264 | status = "disabled"; |
239 | }; | 265 | }; |
240 | 266 | ||
241 | tsc@40048000 { | 267 | tsc@40048000 { |
242 | compatible = "nxp,lpc3220-tsc"; | 268 | compatible = "nxp,lpc3220-tsc"; |
243 | reg = <0x40048000 0x1000>; | 269 | reg = <0x40048000 0x1000>; |
244 | interrupts = <0x27 0>; | 270 | interrupts = <0x27 0>; |
245 | status = "disable"; | 271 | status = "disabled"; |
246 | }; | 272 | }; |
247 | 273 | ||
248 | key@40050000 { | 274 | key@40050000 { |
249 | compatible = "nxp,lpc3220-key"; | 275 | compatible = "nxp,lpc3220-key"; |
250 | reg = <0x40050000 0x1000>; | 276 | reg = <0x40050000 0x1000>; |
277 | interrupts = <54 0>; | ||
278 | status = "disabled"; | ||
251 | }; | 279 | }; |
252 | 280 | ||
281 | pwm: pwm@4005C000 { | ||
282 | compatible = "nxp,lpc3220-pwm"; | ||
283 | reg = <0x4005C000 0x8>; | ||
284 | status = "disabled"; | ||
285 | }; | ||
253 | }; | 286 | }; |
254 | }; | 287 | }; |
255 | }; | 288 | }; |
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts new file mode 100644 index 000000000000..25b50b759dec --- /dev/null +++ b/arch/arm/boot/dts/omap2420-h4.dts | |||
@@ -0,0 +1,20 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "omap2.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "TI OMAP2420 H4 board"; | ||
14 | compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x84000000>; /* 64 MB */ | ||
19 | }; | ||
20 | }; | ||
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 5b4506c0a8c4..cdcb98c7e075 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts | |||
@@ -61,9 +61,9 @@ | |||
61 | }; | 61 | }; |
62 | 62 | ||
63 | &mmc2 { | 63 | &mmc2 { |
64 | status = "disable"; | 64 | status = "disabled"; |
65 | }; | 65 | }; |
66 | 66 | ||
67 | &mmc3 { | 67 | &mmc3 { |
68 | status = "disable"; | 68 | status = "disabled"; |
69 | }; | 69 | }; |
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index 2eee16ec59b4..f349ee9182ce 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts | |||
@@ -18,3 +18,31 @@ | |||
18 | reg = <0x80000000 0x10000000>; /* 256 MB */ | 18 | reg = <0x80000000 0x10000000>; /* 256 MB */ |
19 | }; | 19 | }; |
20 | }; | 20 | }; |
21 | |||
22 | &i2c1 { | ||
23 | clock-frequency = <2600000>; | ||
24 | |||
25 | twl: twl@48 { | ||
26 | reg = <0x48>; | ||
27 | interrupts = <7>; /* SYS_NIRQ cascaded to intc */ | ||
28 | interrupt-parent = <&intc>; | ||
29 | }; | ||
30 | }; | ||
31 | |||
32 | /include/ "twl4030.dtsi" | ||
33 | |||
34 | &i2c2 { | ||
35 | clock-frequency = <400000>; | ||
36 | }; | ||
37 | |||
38 | &i2c3 { | ||
39 | clock-frequency = <400000>; | ||
40 | |||
41 | /* | ||
42 | * TVP5146 Video decoder-in for analog input support. | ||
43 | */ | ||
44 | tvp5146@5c { | ||
45 | compatible = "ti,tvp5146m2"; | ||
46 | reg = <0x5c>; | ||
47 | }; | ||
48 | }; | ||
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 99474fa5fac4..810947198208 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi | |||
@@ -215,5 +215,10 @@ | |||
215 | compatible = "ti,omap3-hsmmc"; | 215 | compatible = "ti,omap3-hsmmc"; |
216 | ti,hwmods = "mmc3"; | 216 | ti,hwmods = "mmc3"; |
217 | }; | 217 | }; |
218 | |||
219 | wdt2: wdt@48314000 { | ||
220 | compatible = "ti,omap3-wdt"; | ||
221 | ti,hwmods = "wd_timer2"; | ||
222 | }; | ||
218 | }; | 223 | }; |
219 | }; | 224 | }; |
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 1efe0c587985..9880c12877b3 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts | |||
@@ -32,6 +32,30 @@ | |||
32 | linux,default-trigger = "mmc0"; | 32 | linux,default-trigger = "mmc0"; |
33 | }; | 33 | }; |
34 | }; | 34 | }; |
35 | |||
36 | sound: sound { | ||
37 | compatible = "ti,abe-twl6040"; | ||
38 | ti,model = "PandaBoard"; | ||
39 | |||
40 | ti,mclk-freq = <38400000>; | ||
41 | |||
42 | ti,mcpdm = <&mcpdm>; | ||
43 | |||
44 | ti,twl6040 = <&twl6040>; | ||
45 | |||
46 | /* Audio routing */ | ||
47 | ti,audio-routing = | ||
48 | "Headset Stereophone", "HSOL", | ||
49 | "Headset Stereophone", "HSOR", | ||
50 | "Ext Spk", "HFL", | ||
51 | "Ext Spk", "HFR", | ||
52 | "Line Out", "AUXL", | ||
53 | "Line Out", "AUXR", | ||
54 | "HSMIC", "Headset Mic", | ||
55 | "Headset Mic", "Headset Mic Bias", | ||
56 | "AFML", "Line In", | ||
57 | "AFMR", "Line In"; | ||
58 | }; | ||
35 | }; | 59 | }; |
36 | 60 | ||
37 | &i2c1 { | 61 | &i2c1 { |
@@ -43,6 +67,19 @@ | |||
43 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | 67 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ |
44 | interrupt-parent = <&gic>; | 68 | interrupt-parent = <&gic>; |
45 | }; | 69 | }; |
70 | |||
71 | twl6040: twl@4b { | ||
72 | compatible = "ti,twl6040"; | ||
73 | reg = <0x4b>; | ||
74 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | ||
75 | interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ | ||
76 | interrupt-parent = <&gic>; | ||
77 | ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ | ||
78 | |||
79 | vio-supply = <&v1v8>; | ||
80 | v2v1-supply = <&v2v1>; | ||
81 | enable-active-high; | ||
82 | }; | ||
46 | }; | 83 | }; |
47 | 84 | ||
48 | /include/ "twl6030.dtsi" | 85 | /include/ "twl6030.dtsi" |
@@ -74,15 +111,15 @@ | |||
74 | }; | 111 | }; |
75 | 112 | ||
76 | &mmc2 { | 113 | &mmc2 { |
77 | status = "disable"; | 114 | status = "disabled"; |
78 | }; | 115 | }; |
79 | 116 | ||
80 | &mmc3 { | 117 | &mmc3 { |
81 | status = "disable"; | 118 | status = "disabled"; |
82 | }; | 119 | }; |
83 | 120 | ||
84 | &mmc4 { | 121 | &mmc4 { |
85 | status = "disable"; | 122 | status = "disabled"; |
86 | }; | 123 | }; |
87 | 124 | ||
88 | &mmc5 { | 125 | &mmc5 { |
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts new file mode 100644 index 000000000000..d4ba43a48d9b --- /dev/null +++ b/arch/arm/boot/dts/omap4-pandaES.dts | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /include/ "omap4-panda.dts" | ||
9 | |||
10 | /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ | ||
11 | &sound { | ||
12 | ti,model = "PandaBoardES"; | ||
13 | |||
14 | /* Audio routing */ | ||
15 | ti,audio-routing = | ||
16 | "Headset Stereophone", "HSOL", | ||
17 | "Headset Stereophone", "HSOR", | ||
18 | "Ext Spk", "HFL", | ||
19 | "Ext Spk", "HFR", | ||
20 | "Line Out", "AUXL", | ||
21 | "Line Out", "AUXR", | ||
22 | "AFML", "Line In", | ||
23 | "AFMR", "Line In"; | ||
24 | }; | ||
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index d08c4d137280..72216e932fc0 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts | |||
@@ -28,6 +28,14 @@ | |||
28 | regulator-boot-on; | 28 | regulator-boot-on; |
29 | }; | 29 | }; |
30 | 30 | ||
31 | vbat: fixedregulator@2 { | ||
32 | compatible = "regulator-fixed"; | ||
33 | regulator-name = "VBAT"; | ||
34 | regulator-min-microvolt = <3750000>; | ||
35 | regulator-max-microvolt = <3750000>; | ||
36 | regulator-boot-on; | ||
37 | }; | ||
38 | |||
31 | leds { | 39 | leds { |
32 | compatible = "gpio-leds"; | 40 | compatible = "gpio-leds"; |
33 | debug0 { | 41 | debug0 { |
@@ -70,6 +78,41 @@ | |||
70 | gpios = <&gpio5 11 0>; /* 139 */ | 78 | gpios = <&gpio5 11 0>; /* 139 */ |
71 | }; | 79 | }; |
72 | }; | 80 | }; |
81 | |||
82 | sound { | ||
83 | compatible = "ti,abe-twl6040"; | ||
84 | ti,model = "SDP4430"; | ||
85 | |||
86 | ti,jack-detection = <1>; | ||
87 | ti,mclk-freq = <38400000>; | ||
88 | |||
89 | ti,mcpdm = <&mcpdm>; | ||
90 | ti,dmic = <&dmic>; | ||
91 | |||
92 | ti,twl6040 = <&twl6040>; | ||
93 | |||
94 | /* Audio routing */ | ||
95 | ti,audio-routing = | ||
96 | "Headset Stereophone", "HSOL", | ||
97 | "Headset Stereophone", "HSOR", | ||
98 | "Earphone Spk", "EP", | ||
99 | "Ext Spk", "HFL", | ||
100 | "Ext Spk", "HFR", | ||
101 | "Line Out", "AUXL", | ||
102 | "Line Out", "AUXR", | ||
103 | "Vibrator", "VIBRAL", | ||
104 | "Vibrator", "VIBRAR", | ||
105 | "HSMIC", "Headset Mic", | ||
106 | "Headset Mic", "Headset Mic Bias", | ||
107 | "MAINMIC", "Main Handset Mic", | ||
108 | "Main Handset Mic", "Main Mic Bias", | ||
109 | "SUBMIC", "Sub Handset Mic", | ||
110 | "Sub Handset Mic", "Main Mic Bias", | ||
111 | "AFML", "Line In", | ||
112 | "AFMR", "Line In", | ||
113 | "DMic", "Digital Mic", | ||
114 | "Digital Mic", "Digital Mic1 Bias"; | ||
115 | }; | ||
73 | }; | 116 | }; |
74 | 117 | ||
75 | &i2c1 { | 118 | &i2c1 { |
@@ -81,6 +124,31 @@ | |||
81 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | 124 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ |
82 | interrupt-parent = <&gic>; | 125 | interrupt-parent = <&gic>; |
83 | }; | 126 | }; |
127 | |||
128 | twl6040: twl@4b { | ||
129 | compatible = "ti,twl6040"; | ||
130 | reg = <0x4b>; | ||
131 | /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */ | ||
132 | interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */ | ||
133 | interrupt-parent = <&gic>; | ||
134 | ti,audpwron-gpio = <&gpio4 31 0>; /* gpio line 127 */ | ||
135 | |||
136 | vio-supply = <&v1v8>; | ||
137 | v2v1-supply = <&v2v1>; | ||
138 | enable-active-high; | ||
139 | |||
140 | /* regulators for vibra motor */ | ||
141 | vddvibl-supply = <&vbat>; | ||
142 | vddvibr-supply = <&vbat>; | ||
143 | |||
144 | vibra { | ||
145 | /* Vibra driver, motor resistance parameters */ | ||
146 | ti,vibldrv-res = <8>; | ||
147 | ti,vibrdrv-res = <3>; | ||
148 | ti,viblmotor-res = <10>; | ||
149 | ti,vibrmotor-res = <10>; | ||
150 | }; | ||
151 | }; | ||
84 | }; | 152 | }; |
85 | 153 | ||
86 | /include/ "twl6030.dtsi" | 154 | /include/ "twl6030.dtsi" |
@@ -147,11 +215,11 @@ | |||
147 | }; | 215 | }; |
148 | 216 | ||
149 | &mmc3 { | 217 | &mmc3 { |
150 | status = "disable"; | 218 | status = "disabled"; |
151 | }; | 219 | }; |
152 | 220 | ||
153 | &mmc4 { | 221 | &mmc4 { |
154 | status = "disable"; | 222 | status = "disabled"; |
155 | }; | 223 | }; |
156 | 224 | ||
157 | &mmc5 { | 225 | &mmc5 { |
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts new file mode 100644 index 000000000000..6601e6af6092 --- /dev/null +++ b/arch/arm/boot/dts/omap4-var_som.dts | |||
@@ -0,0 +1,96 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License version 2 as | ||
6 | * published by the Free Software Foundation. | ||
7 | */ | ||
8 | /dts-v1/; | ||
9 | |||
10 | /include/ "omap4.dtsi" | ||
11 | |||
12 | / { | ||
13 | model = "Variscite OMAP4 SOM"; | ||
14 | compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4"; | ||
15 | |||
16 | memory { | ||
17 | device_type = "memory"; | ||
18 | reg = <0x80000000 0x40000000>; /* 1 GB */ | ||
19 | }; | ||
20 | |||
21 | vdd_eth: fixedregulator@0 { | ||
22 | compatible = "regulator-fixed"; | ||
23 | regulator-name = "VDD_ETH"; | ||
24 | regulator-min-microvolt = <3300000>; | ||
25 | regulator-max-microvolt = <3300000>; | ||
26 | enable-active-high; | ||
27 | regulator-boot-on; | ||
28 | }; | ||
29 | }; | ||
30 | |||
31 | &i2c1 { | ||
32 | clock-frequency = <400000>; | ||
33 | |||
34 | twl: twl@48 { | ||
35 | reg = <0x48>; | ||
36 | /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */ | ||
37 | interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */ | ||
38 | interrupt-parent = <&gic>; | ||
39 | }; | ||
40 | }; | ||
41 | |||
42 | /include/ "twl6030.dtsi" | ||
43 | |||
44 | &i2c2 { | ||
45 | clock-frequency = <400000>; | ||
46 | }; | ||
47 | |||
48 | &i2c3 { | ||
49 | clock-frequency = <400000>; | ||
50 | |||
51 | /* | ||
52 | * Temperature Sensor | ||
53 | * http://www.ti.com/lit/ds/symlink/tmp105.pdf | ||
54 | */ | ||
55 | tmp105@49 { | ||
56 | compatible = "ti,tmp105"; | ||
57 | reg = <0x49>; | ||
58 | }; | ||
59 | }; | ||
60 | |||
61 | &i2c4 { | ||
62 | clock-frequency = <400000>; | ||
63 | }; | ||
64 | |||
65 | &mcspi1 { | ||
66 | eth@0 { | ||
67 | compatible = "ks8851"; | ||
68 | spi-max-frequency = <24000000>; | ||
69 | reg = <0>; | ||
70 | interrupt-parent = <&gpio6>; | ||
71 | interrupts = <11>; /* gpio line 171 */ | ||
72 | vdd-supply = <&vdd_eth>; | ||
73 | }; | ||
74 | }; | ||
75 | |||
76 | &mmc1 { | ||
77 | vmmc-supply = <&vmmc>; | ||
78 | ti,bus-width = <8>; | ||
79 | ti,non-removable; | ||
80 | }; | ||
81 | |||
82 | &mmc2 { | ||
83 | status = "disabled"; | ||
84 | }; | ||
85 | |||
86 | &mmc3 { | ||
87 | status = "disabled"; | ||
88 | }; | ||
89 | |||
90 | &mmc4 { | ||
91 | status = "disabled"; | ||
92 | }; | ||
93 | |||
94 | &mmc5 { | ||
95 | ti,bus-width = <4>; | ||
96 | }; | ||
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 359c4979c8aa..04cbbcb6ff91 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi | |||
@@ -272,5 +272,28 @@ | |||
272 | ti,hwmods = "mmc5"; | 272 | ti,hwmods = "mmc5"; |
273 | ti,needs-special-reset; | 273 | ti,needs-special-reset; |
274 | }; | 274 | }; |
275 | |||
276 | wdt2: wdt@4a314000 { | ||
277 | compatible = "ti,omap4-wdt", "ti,omap3-wdt"; | ||
278 | ti,hwmods = "wd_timer2"; | ||
279 | }; | ||
280 | |||
281 | mcpdm: mcpdm@40132000 { | ||
282 | compatible = "ti,omap4-mcpdm"; | ||
283 | reg = <0x40132000 0x7f>, /* MPU private access */ | ||
284 | <0x49032000 0x7f>; /* L3 Interconnect */ | ||
285 | interrupts = <0 112 0x4>; | ||
286 | interrupt-parent = <&gic>; | ||
287 | ti,hwmods = "mcpdm"; | ||
288 | }; | ||
289 | |||
290 | dmic: dmic@4012e000 { | ||
291 | compatible = "ti,omap4-dmic"; | ||
292 | reg = <0x4012e000 0x7f>, /* MPU private access */ | ||
293 | <0x4902e000 0x7f>; /* L3 Interconnect */ | ||
294 | interrupts = <0 114 0x4>; | ||
295 | interrupt-parent = <&gic>; | ||
296 | ti,hwmods = "dmic"; | ||
297 | }; | ||
275 | }; | 298 | }; |
276 | }; | 299 | }; |
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index c4ff6d1a018b..802ec5b2fd00 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts | |||
@@ -54,6 +54,17 @@ | |||
54 | #address-cells = <1>; | 54 | #address-cells = <1>; |
55 | #size-cells = <1>; | 55 | #size-cells = <1>; |
56 | 56 | ||
57 | nxp,wdr-clks = <14>; | ||
58 | nxp,wwidth = <40000000>; | ||
59 | nxp,whold = <100000000>; | ||
60 | nxp,wsetup = <100000000>; | ||
61 | nxp,rdr-clks = <14>; | ||
62 | nxp,rwidth = <40000000>; | ||
63 | nxp,rhold = <66666666>; | ||
64 | nxp,rsetup = <100000000>; | ||
65 | nand-on-flash-bbt; | ||
66 | gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ | ||
67 | |||
57 | mtd0@00000000 { | 68 | mtd0@00000000 { |
58 | label = "phy3250-boot"; | 69 | label = "phy3250-boot"; |
59 | reg = <0x00000000 0x00064000>; | 70 | reg = <0x00000000 0x00064000>; |
@@ -83,6 +94,14 @@ | |||
83 | }; | 94 | }; |
84 | 95 | ||
85 | apb { | 96 | apb { |
97 | uart5: serial@40090000 { | ||
98 | status = "okay"; | ||
99 | }; | ||
100 | |||
101 | uart3: serial@40080000 { | ||
102 | status = "okay"; | ||
103 | }; | ||
104 | |||
86 | i2c1: i2c@400A0000 { | 105 | i2c1: i2c@400A0000 { |
87 | clock-frequency = <100000>; | 106 | clock-frequency = <100000>; |
88 | 107 | ||
@@ -114,16 +133,58 @@ | |||
114 | }; | 133 | }; |
115 | 134 | ||
116 | ssp0: ssp@20084000 { | 135 | ssp0: ssp@20084000 { |
136 | #address-cells = <1>; | ||
137 | #size-cells = <0>; | ||
138 | pl022,num-chipselects = <1>; | ||
139 | cs-gpios = <&gpio 3 5 0>; | ||
140 | |||
117 | eeprom: at25@0 { | 141 | eeprom: at25@0 { |
142 | pl022,hierarchy = <0>; | ||
143 | pl022,interface = <0>; | ||
144 | pl022,slave-tx-disable = <0>; | ||
145 | pl022,com-mode = <0>; | ||
146 | pl022,rx-level-trig = <1>; | ||
147 | pl022,tx-level-trig = <1>; | ||
148 | pl022,ctrl-len = <11>; | ||
149 | pl022,wait-state = <0>; | ||
150 | pl022,duplex = <0>; | ||
151 | |||
152 | at25,byte-len = <0x8000>; | ||
153 | at25,addr-mode = <2>; | ||
154 | at25,page-size = <64>; | ||
155 | |||
118 | compatible = "atmel,at25"; | 156 | compatible = "atmel,at25"; |
157 | reg = <0>; | ||
158 | spi-max-frequency = <5000000>; | ||
119 | }; | 159 | }; |
120 | }; | 160 | }; |
161 | |||
162 | sd@20098000 { | ||
163 | wp-gpios = <&gpio 3 0 0>; | ||
164 | cd-gpios = <&gpio 3 1 0>; | ||
165 | cd-inverted; | ||
166 | bus-width = <4>; | ||
167 | status = "okay"; | ||
168 | }; | ||
121 | }; | 169 | }; |
122 | 170 | ||
123 | fab { | 171 | fab { |
172 | uart2: serial@40018000 { | ||
173 | status = "okay"; | ||
174 | }; | ||
175 | |||
124 | tsc@40048000 { | 176 | tsc@40048000 { |
125 | status = "okay"; | 177 | status = "okay"; |
126 | }; | 178 | }; |
179 | |||
180 | key@40050000 { | ||
181 | status = "okay"; | ||
182 | keypad,num-rows = <1>; | ||
183 | keypad,num-columns = <1>; | ||
184 | nxp,debounce-delay-ms = <3>; | ||
185 | nxp,scan-delay-ms = <34>; | ||
186 | linux,keymap = <0x00000002>; | ||
187 | }; | ||
127 | }; | 188 | }; |
128 | }; | 189 | }; |
129 | 190 | ||
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts index ec3c33975110..7e334d4cae21 100644 --- a/arch/arm/boot/dts/snowball.dts +++ b/arch/arm/boot/dts/snowball.dts | |||
@@ -77,6 +77,8 @@ | |||
77 | used-led { | 77 | used-led { |
78 | label = "user_led"; | 78 | label = "user_led"; |
79 | gpios = <&gpio4 14 0x4>; | 79 | gpios = <&gpio4 14 0x4>; |
80 | default-state = "on"; | ||
81 | linux,default-trigger = "heartbeat"; | ||
80 | }; | 82 | }; |
81 | }; | 83 | }; |
82 | 84 | ||
@@ -101,15 +103,30 @@ | |||
101 | }; | 103 | }; |
102 | }; | 104 | }; |
103 | 105 | ||
106 | // External Micro SD slot | ||
104 | sdi@80126000 { | 107 | sdi@80126000 { |
105 | status = "enabled"; | 108 | arm,primecell-periphid = <0x10480180>; |
109 | max-frequency = <50000000>; | ||
110 | bus-width = <8>; | ||
111 | mmc-cap-mmc-highspeed; | ||
106 | vmmc-supply = <&ab8500_ldo_aux3_reg>; | 112 | vmmc-supply = <&ab8500_ldo_aux3_reg>; |
113 | |||
114 | #gpio-cells = <1>; | ||
107 | cd-gpios = <&gpio6 26 0x4>; // 218 | 115 | cd-gpios = <&gpio6 26 0x4>; // 218 |
116 | cd-inverted; | ||
117 | |||
118 | status = "okay"; | ||
108 | }; | 119 | }; |
109 | 120 | ||
121 | // On-board eMMC | ||
110 | sdi@80114000 { | 122 | sdi@80114000 { |
111 | status = "enabled"; | 123 | arm,primecell-periphid = <0x10480180>; |
124 | max-frequency = <50000000>; | ||
125 | bus-width = <8>; | ||
126 | mmc-cap-mmc-highspeed; | ||
112 | vmmc-supply = <&ab8500_ldo_aux2_reg>; | 127 | vmmc-supply = <&ab8500_ldo_aux2_reg>; |
128 | |||
129 | status = "okay"; | ||
113 | }; | 130 | }; |
114 | 131 | ||
115 | uart@80120000 { | 132 | uart@80120000 { |
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 10dcec7e7321..f7b84aced654 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi | |||
@@ -43,8 +43,8 @@ | |||
43 | 43 | ||
44 | pmu { | 44 | pmu { |
45 | compatible = "arm,cortex-a9-pmu"; | 45 | compatible = "arm,cortex-a9-pmu"; |
46 | interrupts = <0 8 0x04 | 46 | interrupts = <0 6 0x04 |
47 | 0 9 0x04>; | 47 | 0 7 0x04>; |
48 | }; | 48 | }; |
49 | 49 | ||
50 | L2: l2-cache { | 50 | L2: l2-cache { |
@@ -119,8 +119,8 @@ | |||
119 | gmac0: eth@e2000000 { | 119 | gmac0: eth@e2000000 { |
120 | compatible = "st,spear600-gmac"; | 120 | compatible = "st,spear600-gmac"; |
121 | reg = <0xe2000000 0x8000>; | 121 | reg = <0xe2000000 0x8000>; |
122 | interrupts = <0 23 0x4 | 122 | interrupts = <0 33 0x4 |
123 | 0 24 0x4>; | 123 | 0 34 0x4>; |
124 | interrupt-names = "macirq", "eth_wake_irq"; | 124 | interrupt-names = "macirq", "eth_wake_irq"; |
125 | status = "disabled"; | 125 | status = "disabled"; |
126 | }; | 126 | }; |
@@ -202,6 +202,7 @@ | |||
202 | kbd@e0300000 { | 202 | kbd@e0300000 { |
203 | compatible = "st,spear300-kbd"; | 203 | compatible = "st,spear300-kbd"; |
204 | reg = <0xe0300000 0x1000>; | 204 | reg = <0xe0300000 0x1000>; |
205 | interrupts = <0 52 0x4>; | ||
205 | status = "disabled"; | 206 | status = "disabled"; |
206 | }; | 207 | }; |
207 | 208 | ||
@@ -224,7 +225,7 @@ | |||
224 | serial@e0000000 { | 225 | serial@e0000000 { |
225 | compatible = "arm,pl011", "arm,primecell"; | 226 | compatible = "arm,pl011", "arm,primecell"; |
226 | reg = <0xe0000000 0x1000>; | 227 | reg = <0xe0000000 0x1000>; |
227 | interrupts = <0 36 0x4>; | 228 | interrupts = <0 35 0x4>; |
228 | status = "disabled"; | 229 | status = "disabled"; |
229 | }; | 230 | }; |
230 | 231 | ||
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts index c13fd1f3b09f..e4e912f95024 100644 --- a/arch/arm/boot/dts/spear320-evb.dts +++ b/arch/arm/boot/dts/spear320-evb.dts | |||
@@ -15,8 +15,8 @@ | |||
15 | /include/ "spear320.dtsi" | 15 | /include/ "spear320.dtsi" |
16 | 16 | ||
17 | / { | 17 | / { |
18 | model = "ST SPEAr300 Evaluation Board"; | 18 | model = "ST SPEAr320 Evaluation Board"; |
19 | compatible = "st,spear300-evb", "st,spear300"; | 19 | compatible = "st,spear320-evb", "st,spear320"; |
20 | #address-cells = <1>; | 20 | #address-cells = <1>; |
21 | #size-cells = <1>; | 21 | #size-cells = <1>; |
22 | 22 | ||
@@ -26,7 +26,7 @@ | |||
26 | 26 | ||
27 | ahb { | 27 | ahb { |
28 | pinmux@b3000000 { | 28 | pinmux@b3000000 { |
29 | st,pinmux-mode = <3>; | 29 | st,pinmux-mode = <4>; |
30 | pinctrl-names = "default"; | 30 | pinctrl-names = "default"; |
31 | pinctrl-0 = <&state_default>; | 31 | pinctrl-0 = <&state_default>; |
32 | 32 | ||
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi index 089f0a42c50e..a3c36e47d7ef 100644 --- a/arch/arm/boot/dts/spear600.dtsi +++ b/arch/arm/boot/dts/spear600.dtsi | |||
@@ -181,6 +181,7 @@ | |||
181 | timer@f0000000 { | 181 | timer@f0000000 { |
182 | compatible = "st,spear-timer"; | 182 | compatible = "st,spear-timer"; |
183 | reg = <0xf0000000 0x400>; | 183 | reg = <0xf0000000 0x400>; |
184 | interrupt-parent = <&vic0>; | ||
184 | interrupts = <16>; | 185 | interrupts = <16>; |
185 | }; | 186 | }; |
186 | }; | 187 | }; |
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index 7de701365fce..f146dbf6f7f8 100644 --- a/arch/arm/boot/dts/tegra-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts | |||
@@ -307,7 +307,6 @@ | |||
307 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ | 307 | cd-gpios = <&gpio 58 0>; /* gpio PH2 */ |
308 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ | 308 | wp-gpios = <&gpio 59 0>; /* gpio PH3 */ |
309 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ | 309 | power-gpios = <&gpio 70 0>; /* gpio PI6 */ |
310 | support-8bit; | ||
311 | bus-width = <8>; | 310 | bus-width = <8>; |
312 | }; | 311 | }; |
313 | 312 | ||
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index bfeb117d5aea..684a9e1ff7e9 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts | |||
@@ -301,7 +301,6 @@ | |||
301 | 301 | ||
302 | sdhci@c8000600 { | 302 | sdhci@c8000600 { |
303 | status = "okay"; | 303 | status = "okay"; |
304 | support-8bit; | ||
305 | bus-width = <8>; | 304 | bus-width = <8>; |
306 | }; | 305 | }; |
307 | 306 | ||
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index 89cb7f2acd92..85e621ab2968 100644 --- a/arch/arm/boot/dts/tegra-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts | |||
@@ -64,11 +64,6 @@ | |||
64 | nvidia,pins = "dap4"; | 64 | nvidia,pins = "dap4"; |
65 | nvidia,function = "dap4"; | 65 | nvidia,function = "dap4"; |
66 | }; | 66 | }; |
67 | ddc { | ||
68 | nvidia,pins = "ddc", "owc", "spdi", "spdo", | ||
69 | "uac"; | ||
70 | nvidia,function = "rsvd2"; | ||
71 | }; | ||
72 | dta { | 67 | dta { |
73 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | 68 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
74 | nvidia,function = "vi"; | 69 | nvidia,function = "vi"; |
@@ -129,14 +124,14 @@ | |||
129 | "lspi", "lvp1", "lvs"; | 124 | "lspi", "lvp1", "lvs"; |
130 | nvidia,function = "displaya"; | 125 | nvidia,function = "displaya"; |
131 | }; | 126 | }; |
127 | owc { | ||
128 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | ||
129 | nvidia,function = "rsvd2"; | ||
130 | }; | ||
132 | pmc { | 131 | pmc { |
133 | nvidia,pins = "pmc"; | 132 | nvidia,pins = "pmc"; |
134 | nvidia,function = "pwr_on"; | 133 | nvidia,function = "pwr_on"; |
135 | }; | 134 | }; |
136 | pta { | ||
137 | nvidia,pins = "pta"; | ||
138 | nvidia,function = "i2c2"; | ||
139 | }; | ||
140 | rm { | 135 | rm { |
141 | nvidia,pins = "rm"; | 136 | nvidia,pins = "rm"; |
142 | nvidia,function = "i2c1"; | 137 | nvidia,function = "i2c1"; |
@@ -176,7 +171,7 @@ | |||
176 | conf_ata { | 171 | conf_ata { |
177 | nvidia,pins = "ata", "atb", "atc", "atd", | 172 | nvidia,pins = "ata", "atb", "atc", "atd", |
178 | "cdev1", "cdev2", "dap1", "dap2", | 173 | "cdev1", "cdev2", "dap1", "dap2", |
179 | "dap4", "dtf", "gma", "gmc", "gmd", | 174 | "dap4", "ddc", "dtf", "gma", "gmc", "gmd", |
180 | "gme", "gpu", "gpu7", "i2cp", "irrx", | 175 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
181 | "irtx", "pta", "rm", "sdc", "sdd", | 176 | "irtx", "pta", "rm", "sdc", "sdd", |
182 | "slxd", "slxk", "spdi", "spdo", "uac", | 177 | "slxd", "slxk", "spdi", "spdo", "uac", |
@@ -185,7 +180,7 @@ | |||
185 | nvidia,tristate = <0>; | 180 | nvidia,tristate = <0>; |
186 | }; | 181 | }; |
187 | conf_ate { | 182 | conf_ate { |
188 | nvidia,pins = "ate", "csus", "dap3", "ddc", | 183 | nvidia,pins = "ate", "csus", "dap3", |
189 | "gpv", "owc", "slxc", "spib", "spid", | 184 | "gpv", "owc", "slxc", "spib", "spid", |
190 | "spie"; | 185 | "spie"; |
191 | nvidia,pull = <0>; | 186 | nvidia,pull = <0>; |
@@ -255,6 +250,39 @@ | |||
255 | nvidia,slew-rate-falling = <3>; | 250 | nvidia,slew-rate-falling = <3>; |
256 | }; | 251 | }; |
257 | }; | 252 | }; |
253 | |||
254 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | ||
255 | ddc { | ||
256 | nvidia,pins = "ddc"; | ||
257 | nvidia,function = "i2c2"; | ||
258 | }; | ||
259 | pta { | ||
260 | nvidia,pins = "pta"; | ||
261 | nvidia,function = "rsvd4"; | ||
262 | }; | ||
263 | }; | ||
264 | |||
265 | state_i2cmux_pta: pinmux_i2cmux_pta { | ||
266 | ddc { | ||
267 | nvidia,pins = "ddc"; | ||
268 | nvidia,function = "rsvd4"; | ||
269 | }; | ||
270 | pta { | ||
271 | nvidia,pins = "pta"; | ||
272 | nvidia,function = "i2c2"; | ||
273 | }; | ||
274 | }; | ||
275 | |||
276 | state_i2cmux_idle: pinmux_i2cmux_idle { | ||
277 | ddc { | ||
278 | nvidia,pins = "ddc"; | ||
279 | nvidia,function = "rsvd4"; | ||
280 | }; | ||
281 | pta { | ||
282 | nvidia,pins = "pta"; | ||
283 | nvidia,function = "rsvd4"; | ||
284 | }; | ||
285 | }; | ||
258 | }; | 286 | }; |
259 | 287 | ||
260 | i2s@70002800 { | 288 | i2s@70002800 { |
@@ -303,12 +331,37 @@ | |||
303 | i2c@7000c400 { | 331 | i2c@7000c400 { |
304 | status = "okay"; | 332 | status = "okay"; |
305 | clock-frequency = <100000>; | 333 | clock-frequency = <100000>; |
334 | }; | ||
335 | |||
336 | i2cmux { | ||
337 | compatible = "i2c-mux-pinctrl"; | ||
338 | #address-cells = <1>; | ||
339 | #size-cells = <0>; | ||
340 | |||
341 | i2c-parent = <&{/i2c@7000c400}>; | ||
306 | 342 | ||
307 | smart-battery@b { | 343 | pinctrl-names = "ddc", "pta", "idle"; |
308 | compatible = "ti,bq20z75", "smart-battery-1.1"; | 344 | pinctrl-0 = <&state_i2cmux_ddc>; |
309 | reg = <0xb>; | 345 | pinctrl-1 = <&state_i2cmux_pta>; |
310 | ti,i2c-retry-count = <2>; | 346 | pinctrl-2 = <&state_i2cmux_idle>; |
311 | ti,poll-retry-count = <10>; | 347 | |
348 | i2c@0 { | ||
349 | reg = <0>; | ||
350 | #address-cells = <1>; | ||
351 | #size-cells = <0>; | ||
352 | }; | ||
353 | |||
354 | i2c@1 { | ||
355 | reg = <1>; | ||
356 | #address-cells = <1>; | ||
357 | #size-cells = <0>; | ||
358 | |||
359 | smart-battery@b { | ||
360 | compatible = "ti,bq20z75", "smart-battery-1.1"; | ||
361 | reg = <0xb>; | ||
362 | ti,i2c-retry-count = <2>; | ||
363 | ti,poll-retry-count = <10>; | ||
364 | }; | ||
312 | }; | 365 | }; |
313 | }; | 366 | }; |
314 | 367 | ||
@@ -334,7 +387,7 @@ | |||
334 | }; | 387 | }; |
335 | }; | 388 | }; |
336 | 389 | ||
337 | emc { | 390 | memory-controller@0x7000f400 { |
338 | emc-table@190000 { | 391 | emc-table@190000 { |
339 | reg = <190000>; | 392 | reg = <190000>; |
340 | compatible = "nvidia,tegra20-emc-table"; | 393 | compatible = "nvidia,tegra20-emc-table"; |
@@ -397,7 +450,6 @@ | |||
397 | 450 | ||
398 | sdhci@c8000600 { | 451 | sdhci@c8000600 { |
399 | status = "okay"; | 452 | status = "okay"; |
400 | support-8bit; | ||
401 | bus-width = <8>; | 453 | bus-width = <8>; |
402 | }; | 454 | }; |
403 | 455 | ||
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 9de5636023f6..9de5636023f6 100644 --- a/arch/arm/boot/dts/tegra-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts | |||
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 445343b0fbdd..be90544e6b59 100644 --- a/arch/arm/boot/dts/tegra-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts | |||
@@ -314,7 +314,6 @@ | |||
314 | 314 | ||
315 | sdhci@c8000600 { | 315 | sdhci@c8000600 { |
316 | status = "okay"; | 316 | status = "okay"; |
317 | support-8bit; | ||
318 | bus-width = <8>; | 317 | bus-width = <8>; |
319 | }; | 318 | }; |
320 | 319 | ||
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts new file mode 100644 index 000000000000..6916310bf58f --- /dev/null +++ b/arch/arm/boot/dts/tegra20-whistler.dts | |||
@@ -0,0 +1,301 @@ | |||
1 | /dts-v1/; | ||
2 | |||
3 | /include/ "tegra20.dtsi" | ||
4 | |||
5 | / { | ||
6 | model = "NVIDIA Tegra2 Whistler evaluation board"; | ||
7 | compatible = "nvidia,whistler", "nvidia,tegra20"; | ||
8 | |||
9 | memory { | ||
10 | reg = <0x00000000 0x20000000>; | ||
11 | }; | ||
12 | |||
13 | pinmux { | ||
14 | pinctrl-names = "default"; | ||
15 | pinctrl-0 = <&state_default>; | ||
16 | |||
17 | state_default: pinmux { | ||
18 | ata { | ||
19 | nvidia,pins = "ata", "atb", "ate", "gma", "gmb", | ||
20 | "gmc", "gmd", "gpu"; | ||
21 | nvidia,function = "gmi"; | ||
22 | }; | ||
23 | atc { | ||
24 | nvidia,pins = "atc", "atd"; | ||
25 | nvidia,function = "sdio4"; | ||
26 | }; | ||
27 | cdev1 { | ||
28 | nvidia,pins = "cdev1"; | ||
29 | nvidia,function = "plla_out"; | ||
30 | }; | ||
31 | cdev2 { | ||
32 | nvidia,pins = "cdev2"; | ||
33 | nvidia,function = "osc"; | ||
34 | }; | ||
35 | crtp { | ||
36 | nvidia,pins = "crtp"; | ||
37 | nvidia,function = "crt"; | ||
38 | }; | ||
39 | csus { | ||
40 | nvidia,pins = "csus"; | ||
41 | nvidia,function = "vi_sensor_clk"; | ||
42 | }; | ||
43 | dap1 { | ||
44 | nvidia,pins = "dap1"; | ||
45 | nvidia,function = "dap1"; | ||
46 | }; | ||
47 | dap2 { | ||
48 | nvidia,pins = "dap2"; | ||
49 | nvidia,function = "dap2"; | ||
50 | }; | ||
51 | dap3 { | ||
52 | nvidia,pins = "dap3"; | ||
53 | nvidia,function = "dap3"; | ||
54 | }; | ||
55 | dap4 { | ||
56 | nvidia,pins = "dap4"; | ||
57 | nvidia,function = "dap4"; | ||
58 | }; | ||
59 | ddc { | ||
60 | nvidia,pins = "ddc"; | ||
61 | nvidia,function = "i2c2"; | ||
62 | }; | ||
63 | dta { | ||
64 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | ||
65 | nvidia,function = "vi"; | ||
66 | }; | ||
67 | dte { | ||
68 | nvidia,pins = "dte"; | ||
69 | nvidia,function = "rsvd1"; | ||
70 | }; | ||
71 | dtf { | ||
72 | nvidia,pins = "dtf"; | ||
73 | nvidia,function = "i2c3"; | ||
74 | }; | ||
75 | gme { | ||
76 | nvidia,pins = "gme"; | ||
77 | nvidia,function = "dap5"; | ||
78 | }; | ||
79 | gpu7 { | ||
80 | nvidia,pins = "gpu7"; | ||
81 | nvidia,function = "rtck"; | ||
82 | }; | ||
83 | gpv { | ||
84 | nvidia,pins = "gpv"; | ||
85 | nvidia,function = "pcie"; | ||
86 | }; | ||
87 | hdint { | ||
88 | nvidia,pins = "hdint", "pta"; | ||
89 | nvidia,function = "hdmi"; | ||
90 | }; | ||
91 | i2cp { | ||
92 | nvidia,pins = "i2cp"; | ||
93 | nvidia,function = "i2cp"; | ||
94 | }; | ||
95 | irrx { | ||
96 | nvidia,pins = "irrx", "irtx"; | ||
97 | nvidia,function = "uartb"; | ||
98 | }; | ||
99 | kbca { | ||
100 | nvidia,pins = "kbca", "kbcc", "kbce", "kbcf"; | ||
101 | nvidia,function = "kbc"; | ||
102 | }; | ||
103 | kbcb { | ||
104 | nvidia,pins = "kbcb", "kbcd"; | ||
105 | nvidia,function = "sdio2"; | ||
106 | }; | ||
107 | lcsn { | ||
108 | nvidia,pins = "lcsn", "lsck", "lsda", "lsdi", | ||
109 | "spia", "spib", "spic"; | ||
110 | nvidia,function = "spi3"; | ||
111 | }; | ||
112 | ld0 { | ||
113 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | ||
114 | "ld5", "ld6", "ld7", "ld8", "ld9", | ||
115 | "ld10", "ld11", "ld12", "ld13", "ld14", | ||
116 | "ld15", "ld16", "ld17", "ldc", "ldi", | ||
117 | "lhp0", "lhp1", "lhp2", "lhs", "lm0", | ||
118 | "lm1", "lpp", "lpw0", "lpw1", "lpw2", | ||
119 | "lsc0", "lsc1", "lspi", "lvp0", "lvp1", | ||
120 | "lvs"; | ||
121 | nvidia,function = "displaya"; | ||
122 | }; | ||
123 | owc { | ||
124 | nvidia,pins = "owc", "uac"; | ||
125 | nvidia,function = "owr"; | ||
126 | }; | ||
127 | pmc { | ||
128 | nvidia,pins = "pmc"; | ||
129 | nvidia,function = "pwr_on"; | ||
130 | }; | ||
131 | rm { | ||
132 | nvidia,pins = "rm"; | ||
133 | nvidia,function = "i2c1"; | ||
134 | }; | ||
135 | sdb { | ||
136 | nvidia,pins = "sdb", "sdc", "sdd", "slxa", | ||
137 | "slxc", "slxd", "slxk"; | ||
138 | nvidia,function = "sdio3"; | ||
139 | }; | ||
140 | sdio1 { | ||
141 | nvidia,pins = "sdio1"; | ||
142 | nvidia,function = "sdio1"; | ||
143 | }; | ||
144 | spdi { | ||
145 | nvidia,pins = "spdi", "spdo"; | ||
146 | nvidia,function = "rsvd2"; | ||
147 | }; | ||
148 | spid { | ||
149 | nvidia,pins = "spid", "spie", "spig", "spih"; | ||
150 | nvidia,function = "spi2_alt"; | ||
151 | }; | ||
152 | spif { | ||
153 | nvidia,pins = "spif"; | ||
154 | nvidia,function = "spi2"; | ||
155 | }; | ||
156 | uaa { | ||
157 | nvidia,pins = "uaa", "uab"; | ||
158 | nvidia,function = "uarta"; | ||
159 | }; | ||
160 | uad { | ||
161 | nvidia,pins = "uad"; | ||
162 | nvidia,function = "irda"; | ||
163 | }; | ||
164 | uca { | ||
165 | nvidia,pins = "uca", "ucb"; | ||
166 | nvidia,function = "uartc"; | ||
167 | }; | ||
168 | uda { | ||
169 | nvidia,pins = "uda"; | ||
170 | nvidia,function = "spi1"; | ||
171 | }; | ||
172 | conf_ata { | ||
173 | nvidia,pins = "ata", "atb", "atc", "ddc", "gma", | ||
174 | "gmb", "gmc", "gmd", "irrx", "irtx", | ||
175 | "kbca", "kbcb", "kbcc", "kbcd", "kbce", | ||
176 | "kbcf", "sdc", "sdd", "spie", "spig", | ||
177 | "spih", "uaa", "uab", "uad", "uca", | ||
178 | "ucb"; | ||
179 | nvidia,pull = <2>; | ||
180 | nvidia,tristate = <0>; | ||
181 | }; | ||
182 | conf_atd { | ||
183 | nvidia,pins = "atd", "ate", "cdev1", "csus", | ||
184 | "dap1", "dap2", "dap3", "dap4", "dte", | ||
185 | "dtf", "gpu", "gpu7", "gpv", "i2cp", | ||
186 | "rm", "sdio1", "slxa", "slxc", "slxd", | ||
187 | "slxk", "spdi", "spdo", "uac", "uda"; | ||
188 | nvidia,pull = <0>; | ||
189 | nvidia,tristate = <0>; | ||
190 | }; | ||
191 | conf_cdev2 { | ||
192 | nvidia,pins = "cdev2", "spia", "spib"; | ||
193 | nvidia,pull = <1>; | ||
194 | nvidia,tristate = <1>; | ||
195 | }; | ||
196 | conf_ck32 { | ||
197 | nvidia,pins = "ck32", "ddrc", "lc", "pmca", | ||
198 | "pmcb", "pmcc", "pmcd", "xm2c", | ||
199 | "xm2d"; | ||
200 | nvidia,pull = <0>; | ||
201 | }; | ||
202 | conf_crtp { | ||
203 | nvidia,pins = "crtp"; | ||
204 | nvidia,pull = <0>; | ||
205 | nvidia,tristate = <1>; | ||
206 | }; | ||
207 | conf_dta { | ||
208 | nvidia,pins = "dta", "dtb", "dtc", "dtd", | ||
209 | "spid", "spif"; | ||
210 | nvidia,pull = <1>; | ||
211 | nvidia,tristate = <0>; | ||
212 | }; | ||
213 | conf_gme { | ||
214 | nvidia,pins = "gme", "owc", "pta", "spic"; | ||
215 | nvidia,pull = <2>; | ||
216 | nvidia,tristate = <1>; | ||
217 | }; | ||
218 | conf_ld17_0 { | ||
219 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | ||
220 | "ld23_22"; | ||
221 | nvidia,pull = <1>; | ||
222 | }; | ||
223 | conf_ls { | ||
224 | nvidia,pins = "ls", "pmce"; | ||
225 | nvidia,pull = <2>; | ||
226 | }; | ||
227 | drive_dap1 { | ||
228 | nvidia,pins = "drive_dap1"; | ||
229 | nvidia,high-speed-mode = <0>; | ||
230 | nvidia,schmitt = <1>; | ||
231 | nvidia,low-power-mode = <0>; | ||
232 | nvidia,pull-down-strength = <0>; | ||
233 | nvidia,pull-up-strength = <0>; | ||
234 | nvidia,slew-rate-rising = <0>; | ||
235 | nvidia,slew-rate-falling = <0>; | ||
236 | }; | ||
237 | }; | ||
238 | }; | ||
239 | |||
240 | i2s@70002800 { | ||
241 | status = "okay"; | ||
242 | }; | ||
243 | |||
244 | serial@70006000 { | ||
245 | status = "okay"; | ||
246 | clock-frequency = <216000000>; | ||
247 | }; | ||
248 | |||
249 | i2c@7000d000 { | ||
250 | status = "okay"; | ||
251 | clock-frequency = <100000>; | ||
252 | |||
253 | codec: codec@1a { | ||
254 | compatible = "wlf,wm8753"; | ||
255 | reg = <0x1a>; | ||
256 | }; | ||
257 | |||
258 | tca6416: gpio@20 { | ||
259 | compatible = "ti,tca6416"; | ||
260 | reg = <0x20>; | ||
261 | gpio-controller; | ||
262 | #gpio-cells = <2>; | ||
263 | }; | ||
264 | }; | ||
265 | |||
266 | usb@c5000000 { | ||
267 | status = "okay"; | ||
268 | nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */ | ||
269 | }; | ||
270 | |||
271 | usb@c5008000 { | ||
272 | status = "okay"; | ||
273 | nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */ | ||
274 | }; | ||
275 | |||
276 | sdhci@c8000400 { | ||
277 | status = "okay"; | ||
278 | wp-gpios = <&gpio 173 0>; /* gpio PV5 */ | ||
279 | bus-width = <8>; | ||
280 | }; | ||
281 | |||
282 | sdhci@c8000600 { | ||
283 | status = "okay"; | ||
284 | bus-width = <8>; | ||
285 | }; | ||
286 | |||
287 | sound { | ||
288 | compatible = "nvidia,tegra-audio-wm8753-whistler", | ||
289 | "nvidia,tegra-audio-wm8753"; | ||
290 | nvidia,model = "NVIDIA Tegra Whistler"; | ||
291 | |||
292 | nvidia,audio-routing = | ||
293 | "Headphone Jack", "LOUT1", | ||
294 | "Headphone Jack", "ROUT1", | ||
295 | "MIC2", "Mic Jack", | ||
296 | "MIC2N", "Mic Jack"; | ||
297 | |||
298 | nvidia,i2s-controller = <&tegra_i2s1>; | ||
299 | nvidia,audio-codec = <&codec>; | ||
300 | }; | ||
301 | }; | ||
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index c417d67e9027..9f1921634eb7 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -72,7 +72,7 @@ | |||
72 | reg = <0x70002800 0x200>; | 72 | reg = <0x70002800 0x200>; |
73 | interrupts = <0 13 0x04>; | 73 | interrupts = <0 13 0x04>; |
74 | nvidia,dma-request-selector = <&apbdma 2>; | 74 | nvidia,dma-request-selector = <&apbdma 2>; |
75 | status = "disable"; | 75 | status = "disabled"; |
76 | }; | 76 | }; |
77 | 77 | ||
78 | tegra_i2s2: i2s@70002a00 { | 78 | tegra_i2s2: i2s@70002a00 { |
@@ -80,7 +80,7 @@ | |||
80 | reg = <0x70002a00 0x200>; | 80 | reg = <0x70002a00 0x200>; |
81 | interrupts = <0 3 0x04>; | 81 | interrupts = <0 3 0x04>; |
82 | nvidia,dma-request-selector = <&apbdma 1>; | 82 | nvidia,dma-request-selector = <&apbdma 1>; |
83 | status = "disable"; | 83 | status = "disabled"; |
84 | }; | 84 | }; |
85 | 85 | ||
86 | serial@70006000 { | 86 | serial@70006000 { |
@@ -88,7 +88,7 @@ | |||
88 | reg = <0x70006000 0x40>; | 88 | reg = <0x70006000 0x40>; |
89 | reg-shift = <2>; | 89 | reg-shift = <2>; |
90 | interrupts = <0 36 0x04>; | 90 | interrupts = <0 36 0x04>; |
91 | status = "disable"; | 91 | status = "disabled"; |
92 | }; | 92 | }; |
93 | 93 | ||
94 | serial@70006040 { | 94 | serial@70006040 { |
@@ -96,7 +96,7 @@ | |||
96 | reg = <0x70006040 0x40>; | 96 | reg = <0x70006040 0x40>; |
97 | reg-shift = <2>; | 97 | reg-shift = <2>; |
98 | interrupts = <0 37 0x04>; | 98 | interrupts = <0 37 0x04>; |
99 | status = "disable"; | 99 | status = "disabled"; |
100 | }; | 100 | }; |
101 | 101 | ||
102 | serial@70006200 { | 102 | serial@70006200 { |
@@ -104,7 +104,7 @@ | |||
104 | reg = <0x70006200 0x100>; | 104 | reg = <0x70006200 0x100>; |
105 | reg-shift = <2>; | 105 | reg-shift = <2>; |
106 | interrupts = <0 46 0x04>; | 106 | interrupts = <0 46 0x04>; |
107 | status = "disable"; | 107 | status = "disabled"; |
108 | }; | 108 | }; |
109 | 109 | ||
110 | serial@70006300 { | 110 | serial@70006300 { |
@@ -112,7 +112,7 @@ | |||
112 | reg = <0x70006300 0x100>; | 112 | reg = <0x70006300 0x100>; |
113 | reg-shift = <2>; | 113 | reg-shift = <2>; |
114 | interrupts = <0 90 0x04>; | 114 | interrupts = <0 90 0x04>; |
115 | status = "disable"; | 115 | status = "disabled"; |
116 | }; | 116 | }; |
117 | 117 | ||
118 | serial@70006400 { | 118 | serial@70006400 { |
@@ -120,7 +120,7 @@ | |||
120 | reg = <0x70006400 0x100>; | 120 | reg = <0x70006400 0x100>; |
121 | reg-shift = <2>; | 121 | reg-shift = <2>; |
122 | interrupts = <0 91 0x04>; | 122 | interrupts = <0 91 0x04>; |
123 | status = "disable"; | 123 | status = "disabled"; |
124 | }; | 124 | }; |
125 | 125 | ||
126 | i2c@7000c000 { | 126 | i2c@7000c000 { |
@@ -129,7 +129,7 @@ | |||
129 | interrupts = <0 38 0x04>; | 129 | interrupts = <0 38 0x04>; |
130 | #address-cells = <1>; | 130 | #address-cells = <1>; |
131 | #size-cells = <0>; | 131 | #size-cells = <0>; |
132 | status = "disable"; | 132 | status = "disabled"; |
133 | }; | 133 | }; |
134 | 134 | ||
135 | i2c@7000c400 { | 135 | i2c@7000c400 { |
@@ -138,7 +138,7 @@ | |||
138 | interrupts = <0 84 0x04>; | 138 | interrupts = <0 84 0x04>; |
139 | #address-cells = <1>; | 139 | #address-cells = <1>; |
140 | #size-cells = <0>; | 140 | #size-cells = <0>; |
141 | status = "disable"; | 141 | status = "disabled"; |
142 | }; | 142 | }; |
143 | 143 | ||
144 | i2c@7000c500 { | 144 | i2c@7000c500 { |
@@ -147,7 +147,7 @@ | |||
147 | interrupts = <0 92 0x04>; | 147 | interrupts = <0 92 0x04>; |
148 | #address-cells = <1>; | 148 | #address-cells = <1>; |
149 | #size-cells = <0>; | 149 | #size-cells = <0>; |
150 | status = "disable"; | 150 | status = "disabled"; |
151 | }; | 151 | }; |
152 | 152 | ||
153 | i2c@7000d000 { | 153 | i2c@7000d000 { |
@@ -156,7 +156,7 @@ | |||
156 | interrupts = <0 53 0x04>; | 156 | interrupts = <0 53 0x04>; |
157 | #address-cells = <1>; | 157 | #address-cells = <1>; |
158 | #size-cells = <0>; | 158 | #size-cells = <0>; |
159 | status = "disable"; | 159 | status = "disabled"; |
160 | }; | 160 | }; |
161 | 161 | ||
162 | pmc { | 162 | pmc { |
@@ -164,7 +164,7 @@ | |||
164 | reg = <0x7000e400 0x400>; | 164 | reg = <0x7000e400 0x400>; |
165 | }; | 165 | }; |
166 | 166 | ||
167 | mc { | 167 | memory-controller@0x7000f000 { |
168 | compatible = "nvidia,tegra20-mc"; | 168 | compatible = "nvidia,tegra20-mc"; |
169 | reg = <0x7000f000 0x024 | 169 | reg = <0x7000f000 0x024 |
170 | 0x7000f03c 0x3c4>; | 170 | 0x7000f03c 0x3c4>; |
@@ -177,7 +177,7 @@ | |||
177 | 0x58000000 0x02000000>; /* GART aperture */ | 177 | 0x58000000 0x02000000>; /* GART aperture */ |
178 | }; | 178 | }; |
179 | 179 | ||
180 | emc { | 180 | memory-controller@0x7000f400 { |
181 | compatible = "nvidia,tegra20-emc"; | 181 | compatible = "nvidia,tegra20-emc"; |
182 | reg = <0x7000f400 0x200>; | 182 | reg = <0x7000f400 0x200>; |
183 | #address-cells = <1>; | 183 | #address-cells = <1>; |
@@ -190,7 +190,7 @@ | |||
190 | interrupts = <0 20 0x04>; | 190 | interrupts = <0 20 0x04>; |
191 | phy_type = "utmi"; | 191 | phy_type = "utmi"; |
192 | nvidia,has-legacy-mode; | 192 | nvidia,has-legacy-mode; |
193 | status = "disable"; | 193 | status = "disabled"; |
194 | }; | 194 | }; |
195 | 195 | ||
196 | usb@c5004000 { | 196 | usb@c5004000 { |
@@ -198,7 +198,7 @@ | |||
198 | reg = <0xc5004000 0x4000>; | 198 | reg = <0xc5004000 0x4000>; |
199 | interrupts = <0 21 0x04>; | 199 | interrupts = <0 21 0x04>; |
200 | phy_type = "ulpi"; | 200 | phy_type = "ulpi"; |
201 | status = "disable"; | 201 | status = "disabled"; |
202 | }; | 202 | }; |
203 | 203 | ||
204 | usb@c5008000 { | 204 | usb@c5008000 { |
@@ -206,35 +206,35 @@ | |||
206 | reg = <0xc5008000 0x4000>; | 206 | reg = <0xc5008000 0x4000>; |
207 | interrupts = <0 97 0x04>; | 207 | interrupts = <0 97 0x04>; |
208 | phy_type = "utmi"; | 208 | phy_type = "utmi"; |
209 | status = "disable"; | 209 | status = "disabled"; |
210 | }; | 210 | }; |
211 | 211 | ||
212 | sdhci@c8000000 { | 212 | sdhci@c8000000 { |
213 | compatible = "nvidia,tegra20-sdhci"; | 213 | compatible = "nvidia,tegra20-sdhci"; |
214 | reg = <0xc8000000 0x200>; | 214 | reg = <0xc8000000 0x200>; |
215 | interrupts = <0 14 0x04>; | 215 | interrupts = <0 14 0x04>; |
216 | status = "disable"; | 216 | status = "disabled"; |
217 | }; | 217 | }; |
218 | 218 | ||
219 | sdhci@c8000200 { | 219 | sdhci@c8000200 { |
220 | compatible = "nvidia,tegra20-sdhci"; | 220 | compatible = "nvidia,tegra20-sdhci"; |
221 | reg = <0xc8000200 0x200>; | 221 | reg = <0xc8000200 0x200>; |
222 | interrupts = <0 15 0x04>; | 222 | interrupts = <0 15 0x04>; |
223 | status = "disable"; | 223 | status = "disabled"; |
224 | }; | 224 | }; |
225 | 225 | ||
226 | sdhci@c8000400 { | 226 | sdhci@c8000400 { |
227 | compatible = "nvidia,tegra20-sdhci"; | 227 | compatible = "nvidia,tegra20-sdhci"; |
228 | reg = <0xc8000400 0x200>; | 228 | reg = <0xc8000400 0x200>; |
229 | interrupts = <0 19 0x04>; | 229 | interrupts = <0 19 0x04>; |
230 | status = "disable"; | 230 | status = "disabled"; |
231 | }; | 231 | }; |
232 | 232 | ||
233 | sdhci@c8000600 { | 233 | sdhci@c8000600 { |
234 | compatible = "nvidia,tegra20-sdhci"; | 234 | compatible = "nvidia,tegra20-sdhci"; |
235 | reg = <0xc8000600 0x200>; | 235 | reg = <0xc8000600 0x200>; |
236 | interrupts = <0 31 0x04>; | 236 | interrupts = <0 31 0x04>; |
237 | status = "disable"; | 237 | status = "disabled"; |
238 | }; | 238 | }; |
239 | 239 | ||
240 | pmu { | 240 | pmu { |
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts index 36321bceec46..c169bced131e 100644 --- a/arch/arm/boot/dts/tegra-cardhu.dts +++ b/arch/arm/boot/dts/tegra30-cardhu.dts | |||
@@ -144,7 +144,6 @@ | |||
144 | 144 | ||
145 | sdhci@78000600 { | 145 | sdhci@78000600 { |
146 | status = "okay"; | 146 | status = "okay"; |
147 | support-8bit; | ||
148 | bus-width = <8>; | 147 | bus-width = <8>; |
149 | }; | 148 | }; |
150 | 149 | ||
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2dcc09e784b5..da740191771f 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
@@ -82,7 +82,7 @@ | |||
82 | reg = <0x70006000 0x40>; | 82 | reg = <0x70006000 0x40>; |
83 | reg-shift = <2>; | 83 | reg-shift = <2>; |
84 | interrupts = <0 36 0x04>; | 84 | interrupts = <0 36 0x04>; |
85 | status = "disable"; | 85 | status = "disabled"; |
86 | }; | 86 | }; |
87 | 87 | ||
88 | serial@70006040 { | 88 | serial@70006040 { |
@@ -90,7 +90,7 @@ | |||
90 | reg = <0x70006040 0x40>; | 90 | reg = <0x70006040 0x40>; |
91 | reg-shift = <2>; | 91 | reg-shift = <2>; |
92 | interrupts = <0 37 0x04>; | 92 | interrupts = <0 37 0x04>; |
93 | status = "disable"; | 93 | status = "disabled"; |
94 | }; | 94 | }; |
95 | 95 | ||
96 | serial@70006200 { | 96 | serial@70006200 { |
@@ -98,7 +98,7 @@ | |||
98 | reg = <0x70006200 0x100>; | 98 | reg = <0x70006200 0x100>; |
99 | reg-shift = <2>; | 99 | reg-shift = <2>; |
100 | interrupts = <0 46 0x04>; | 100 | interrupts = <0 46 0x04>; |
101 | status = "disable"; | 101 | status = "disabled"; |
102 | }; | 102 | }; |
103 | 103 | ||
104 | serial@70006300 { | 104 | serial@70006300 { |
@@ -106,7 +106,7 @@ | |||
106 | reg = <0x70006300 0x100>; | 106 | reg = <0x70006300 0x100>; |
107 | reg-shift = <2>; | 107 | reg-shift = <2>; |
108 | interrupts = <0 90 0x04>; | 108 | interrupts = <0 90 0x04>; |
109 | status = "disable"; | 109 | status = "disabled"; |
110 | }; | 110 | }; |
111 | 111 | ||
112 | serial@70006400 { | 112 | serial@70006400 { |
@@ -114,7 +114,7 @@ | |||
114 | reg = <0x70006400 0x100>; | 114 | reg = <0x70006400 0x100>; |
115 | reg-shift = <2>; | 115 | reg-shift = <2>; |
116 | interrupts = <0 91 0x04>; | 116 | interrupts = <0 91 0x04>; |
117 | status = "disable"; | 117 | status = "disabled"; |
118 | }; | 118 | }; |
119 | 119 | ||
120 | i2c@7000c000 { | 120 | i2c@7000c000 { |
@@ -123,7 +123,7 @@ | |||
123 | interrupts = <0 38 0x04>; | 123 | interrupts = <0 38 0x04>; |
124 | #address-cells = <1>; | 124 | #address-cells = <1>; |
125 | #size-cells = <0>; | 125 | #size-cells = <0>; |
126 | status = "disable"; | 126 | status = "disabled"; |
127 | }; | 127 | }; |
128 | 128 | ||
129 | i2c@7000c400 { | 129 | i2c@7000c400 { |
@@ -132,7 +132,7 @@ | |||
132 | interrupts = <0 84 0x04>; | 132 | interrupts = <0 84 0x04>; |
133 | #address-cells = <1>; | 133 | #address-cells = <1>; |
134 | #size-cells = <0>; | 134 | #size-cells = <0>; |
135 | status = "disable"; | 135 | status = "disabled"; |
136 | }; | 136 | }; |
137 | 137 | ||
138 | i2c@7000c500 { | 138 | i2c@7000c500 { |
@@ -141,7 +141,7 @@ | |||
141 | interrupts = <0 92 0x04>; | 141 | interrupts = <0 92 0x04>; |
142 | #address-cells = <1>; | 142 | #address-cells = <1>; |
143 | #size-cells = <0>; | 143 | #size-cells = <0>; |
144 | status = "disable"; | 144 | status = "disabled"; |
145 | }; | 145 | }; |
146 | 146 | ||
147 | i2c@7000c700 { | 147 | i2c@7000c700 { |
@@ -150,7 +150,7 @@ | |||
150 | interrupts = <0 120 0x04>; | 150 | interrupts = <0 120 0x04>; |
151 | #address-cells = <1>; | 151 | #address-cells = <1>; |
152 | #size-cells = <0>; | 152 | #size-cells = <0>; |
153 | status = "disable"; | 153 | status = "disabled"; |
154 | }; | 154 | }; |
155 | 155 | ||
156 | i2c@7000d000 { | 156 | i2c@7000d000 { |
@@ -159,7 +159,7 @@ | |||
159 | interrupts = <0 53 0x04>; | 159 | interrupts = <0 53 0x04>; |
160 | #address-cells = <1>; | 160 | #address-cells = <1>; |
161 | #size-cells = <0>; | 161 | #size-cells = <0>; |
162 | status = "disable"; | 162 | status = "disabled"; |
163 | }; | 163 | }; |
164 | 164 | ||
165 | pmc { | 165 | pmc { |
@@ -167,7 +167,7 @@ | |||
167 | reg = <0x7000e400 0x400>; | 167 | reg = <0x7000e400 0x400>; |
168 | }; | 168 | }; |
169 | 169 | ||
170 | mc { | 170 | memory-controller { |
171 | compatible = "nvidia,tegra30-mc"; | 171 | compatible = "nvidia,tegra30-mc"; |
172 | reg = <0x7000f000 0x010 | 172 | reg = <0x7000f000 0x010 |
173 | 0x7000f03c 0x1b4 | 173 | 0x7000f03c 0x1b4 |
@@ -201,35 +201,35 @@ | |||
201 | compatible = "nvidia,tegra30-i2s"; | 201 | compatible = "nvidia,tegra30-i2s"; |
202 | reg = <0x70080300 0x100>; | 202 | reg = <0x70080300 0x100>; |
203 | nvidia,ahub-cif-ids = <4 4>; | 203 | nvidia,ahub-cif-ids = <4 4>; |
204 | status = "disable"; | 204 | status = "disabled"; |
205 | }; | 205 | }; |
206 | 206 | ||
207 | tegra_i2s1: i2s@70080400 { | 207 | tegra_i2s1: i2s@70080400 { |
208 | compatible = "nvidia,tegra30-i2s"; | 208 | compatible = "nvidia,tegra30-i2s"; |
209 | reg = <0x70080400 0x100>; | 209 | reg = <0x70080400 0x100>; |
210 | nvidia,ahub-cif-ids = <5 5>; | 210 | nvidia,ahub-cif-ids = <5 5>; |
211 | status = "disable"; | 211 | status = "disabled"; |
212 | }; | 212 | }; |
213 | 213 | ||
214 | tegra_i2s2: i2s@70080500 { | 214 | tegra_i2s2: i2s@70080500 { |
215 | compatible = "nvidia,tegra30-i2s"; | 215 | compatible = "nvidia,tegra30-i2s"; |
216 | reg = <0x70080500 0x100>; | 216 | reg = <0x70080500 0x100>; |
217 | nvidia,ahub-cif-ids = <6 6>; | 217 | nvidia,ahub-cif-ids = <6 6>; |
218 | status = "disable"; | 218 | status = "disabled"; |
219 | }; | 219 | }; |
220 | 220 | ||
221 | tegra_i2s3: i2s@70080600 { | 221 | tegra_i2s3: i2s@70080600 { |
222 | compatible = "nvidia,tegra30-i2s"; | 222 | compatible = "nvidia,tegra30-i2s"; |
223 | reg = <0x70080600 0x100>; | 223 | reg = <0x70080600 0x100>; |
224 | nvidia,ahub-cif-ids = <7 7>; | 224 | nvidia,ahub-cif-ids = <7 7>; |
225 | status = "disable"; | 225 | status = "disabled"; |
226 | }; | 226 | }; |
227 | 227 | ||
228 | tegra_i2s4: i2s@70080700 { | 228 | tegra_i2s4: i2s@70080700 { |
229 | compatible = "nvidia,tegra30-i2s"; | 229 | compatible = "nvidia,tegra30-i2s"; |
230 | reg = <0x70080700 0x100>; | 230 | reg = <0x70080700 0x100>; |
231 | nvidia,ahub-cif-ids = <8 8>; | 231 | nvidia,ahub-cif-ids = <8 8>; |
232 | status = "disable"; | 232 | status = "disabled"; |
233 | }; | 233 | }; |
234 | }; | 234 | }; |
235 | 235 | ||
@@ -237,28 +237,28 @@ | |||
237 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 237 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
238 | reg = <0x78000000 0x200>; | 238 | reg = <0x78000000 0x200>; |
239 | interrupts = <0 14 0x04>; | 239 | interrupts = <0 14 0x04>; |
240 | status = "disable"; | 240 | status = "disabled"; |
241 | }; | 241 | }; |
242 | 242 | ||
243 | sdhci@78000200 { | 243 | sdhci@78000200 { |
244 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 244 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
245 | reg = <0x78000200 0x200>; | 245 | reg = <0x78000200 0x200>; |
246 | interrupts = <0 15 0x04>; | 246 | interrupts = <0 15 0x04>; |
247 | status = "disable"; | 247 | status = "disabled"; |
248 | }; | 248 | }; |
249 | 249 | ||
250 | sdhci@78000400 { | 250 | sdhci@78000400 { |
251 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 251 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
252 | reg = <0x78000400 0x200>; | 252 | reg = <0x78000400 0x200>; |
253 | interrupts = <0 19 0x04>; | 253 | interrupts = <0 19 0x04>; |
254 | status = "disable"; | 254 | status = "disabled"; |
255 | }; | 255 | }; |
256 | 256 | ||
257 | sdhci@78000600 { | 257 | sdhci@78000600 { |
258 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | 258 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; |
259 | reg = <0x78000600 0x200>; | 259 | reg = <0x78000600 0x200>; |
260 | interrupts = <0 31 0x04>; | 260 | interrupts = <0 31 0x04>; |
261 | status = "disable"; | 261 | status = "disabled"; |
262 | }; | 262 | }; |
263 | 263 | ||
264 | pmu { | 264 | pmu { |
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 16076e2d0934..d8a827bd2bf3 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | |||
@@ -55,6 +55,8 @@ | |||
55 | reg-io-width = <4>; | 55 | reg-io-width = <4>; |
56 | smsc,irq-active-high; | 56 | smsc,irq-active-high; |
57 | smsc,irq-push-pull; | 57 | smsc,irq-push-pull; |
58 | vdd33a-supply = <&v2m_fixed_3v3>; | ||
59 | vddvario-supply = <&v2m_fixed_3v3>; | ||
58 | }; | 60 | }; |
59 | 61 | ||
60 | usb@2,03000000 { | 62 | usb@2,03000000 { |
@@ -157,6 +159,7 @@ | |||
157 | v2m_timer23: timer@120000 { | 159 | v2m_timer23: timer@120000 { |
158 | compatible = "arm,sp804", "arm,primecell"; | 160 | compatible = "arm,sp804", "arm,primecell"; |
159 | reg = <0x120000 0x1000>; | 161 | reg = <0x120000 0x1000>; |
162 | interrupts = <3>; | ||
160 | }; | 163 | }; |
161 | 164 | ||
162 | /* DVI I2C bus */ | 165 | /* DVI I2C bus */ |
@@ -197,5 +200,13 @@ | |||
197 | interrupts = <14>; | 200 | interrupts = <14>; |
198 | }; | 201 | }; |
199 | }; | 202 | }; |
203 | |||
204 | v2m_fixed_3v3: fixedregulator@0 { | ||
205 | compatible = "regulator-fixed"; | ||
206 | regulator-name = "3V3"; | ||
207 | regulator-min-microvolt = <3300000>; | ||
208 | regulator-max-microvolt = <3300000>; | ||
209 | regulator-always-on; | ||
210 | }; | ||
200 | }; | 211 | }; |
201 | }; | 212 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index a6c9c7c82d53..dba53fd026bb 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi | |||
@@ -54,6 +54,8 @@ | |||
54 | reg-io-width = <4>; | 54 | reg-io-width = <4>; |
55 | smsc,irq-active-high; | 55 | smsc,irq-active-high; |
56 | smsc,irq-push-pull; | 56 | smsc,irq-push-pull; |
57 | vdd33a-supply = <&v2m_fixed_3v3>; | ||
58 | vddvario-supply = <&v2m_fixed_3v3>; | ||
57 | }; | 59 | }; |
58 | 60 | ||
59 | usb@3,03000000 { | 61 | usb@3,03000000 { |
@@ -156,6 +158,7 @@ | |||
156 | v2m_timer23: timer@12000 { | 158 | v2m_timer23: timer@12000 { |
157 | compatible = "arm,sp804", "arm,primecell"; | 159 | compatible = "arm,sp804", "arm,primecell"; |
158 | reg = <0x12000 0x1000>; | 160 | reg = <0x12000 0x1000>; |
161 | interrupts = <3>; | ||
159 | }; | 162 | }; |
160 | 163 | ||
161 | /* DVI I2C bus */ | 164 | /* DVI I2C bus */ |
@@ -196,5 +199,13 @@ | |||
196 | interrupts = <14>; | 199 | interrupts = <14>; |
197 | }; | 200 | }; |
198 | }; | 201 | }; |
202 | |||
203 | v2m_fixed_3v3: fixedregulator@0 { | ||
204 | compatible = "regulator-fixed"; | ||
205 | regulator-name = "3V3"; | ||
206 | regulator-min-microvolt = <3300000>; | ||
207 | regulator-max-microvolt = <3300000>; | ||
208 | regulator-always-on; | ||
209 | }; | ||
199 | }; | 210 | }; |
200 | }; | 211 | }; |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 7e1091d91af8..d12b34ca0568 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | |||
@@ -14,8 +14,8 @@ | |||
14 | arm,hbi = <0x237>; | 14 | arm,hbi = <0x237>; |
15 | compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; | 15 | compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; |
16 | interrupt-parent = <&gic>; | 16 | interrupt-parent = <&gic>; |
17 | #address-cells = <1>; | 17 | #address-cells = <2>; |
18 | #size-cells = <1>; | 18 | #size-cells = <2>; |
19 | 19 | ||
20 | chosen { }; | 20 | chosen { }; |
21 | 21 | ||
@@ -47,23 +47,23 @@ | |||
47 | 47 | ||
48 | memory@80000000 { | 48 | memory@80000000 { |
49 | device_type = "memory"; | 49 | device_type = "memory"; |
50 | reg = <0x80000000 0x40000000>; | 50 | reg = <0 0x80000000 0 0x40000000>; |
51 | }; | 51 | }; |
52 | 52 | ||
53 | hdlcd@2b000000 { | 53 | hdlcd@2b000000 { |
54 | compatible = "arm,hdlcd"; | 54 | compatible = "arm,hdlcd"; |
55 | reg = <0x2b000000 0x1000>; | 55 | reg = <0 0x2b000000 0 0x1000>; |
56 | interrupts = <0 85 4>; | 56 | interrupts = <0 85 4>; |
57 | }; | 57 | }; |
58 | 58 | ||
59 | memory-controller@2b0a0000 { | 59 | memory-controller@2b0a0000 { |
60 | compatible = "arm,pl341", "arm,primecell"; | 60 | compatible = "arm,pl341", "arm,primecell"; |
61 | reg = <0x2b0a0000 0x1000>; | 61 | reg = <0 0x2b0a0000 0 0x1000>; |
62 | }; | 62 | }; |
63 | 63 | ||
64 | wdt@2b060000 { | 64 | wdt@2b060000 { |
65 | compatible = "arm,sp805", "arm,primecell"; | 65 | compatible = "arm,sp805", "arm,primecell"; |
66 | reg = <0x2b060000 0x1000>; | 66 | reg = <0 0x2b060000 0 0x1000>; |
67 | interrupts = <98>; | 67 | interrupts = <98>; |
68 | }; | 68 | }; |
69 | 69 | ||
@@ -72,23 +72,23 @@ | |||
72 | #interrupt-cells = <3>; | 72 | #interrupt-cells = <3>; |
73 | #address-cells = <0>; | 73 | #address-cells = <0>; |
74 | interrupt-controller; | 74 | interrupt-controller; |
75 | reg = <0x2c001000 0x1000>, | 75 | reg = <0 0x2c001000 0 0x1000>, |
76 | <0x2c002000 0x1000>, | 76 | <0 0x2c002000 0 0x1000>, |
77 | <0x2c004000 0x2000>, | 77 | <0 0x2c004000 0 0x2000>, |
78 | <0x2c006000 0x2000>; | 78 | <0 0x2c006000 0 0x2000>; |
79 | interrupts = <1 9 0xf04>; | 79 | interrupts = <1 9 0xf04>; |
80 | }; | 80 | }; |
81 | 81 | ||
82 | memory-controller@7ffd0000 { | 82 | memory-controller@7ffd0000 { |
83 | compatible = "arm,pl354", "arm,primecell"; | 83 | compatible = "arm,pl354", "arm,primecell"; |
84 | reg = <0x7ffd0000 0x1000>; | 84 | reg = <0 0x7ffd0000 0 0x1000>; |
85 | interrupts = <0 86 4>, | 85 | interrupts = <0 86 4>, |
86 | <0 87 4>; | 86 | <0 87 4>; |
87 | }; | 87 | }; |
88 | 88 | ||
89 | dma@7ffb0000 { | 89 | dma@7ffb0000 { |
90 | compatible = "arm,pl330", "arm,primecell"; | 90 | compatible = "arm,pl330", "arm,primecell"; |
91 | reg = <0x7ffb0000 0x1000>; | 91 | reg = <0 0x7ffb0000 0 0x1000>; |
92 | interrupts = <0 92 4>, | 92 | interrupts = <0 92 4>, |
93 | <0 88 4>, | 93 | <0 88 4>, |
94 | <0 89 4>, | 94 | <0 89 4>, |
@@ -111,12 +111,12 @@ | |||
111 | }; | 111 | }; |
112 | 112 | ||
113 | motherboard { | 113 | motherboard { |
114 | ranges = <0 0 0x08000000 0x04000000>, | 114 | ranges = <0 0 0 0x08000000 0x04000000>, |
115 | <1 0 0x14000000 0x04000000>, | 115 | <1 0 0 0x14000000 0x04000000>, |
116 | <2 0 0x18000000 0x04000000>, | 116 | <2 0 0 0x18000000 0x04000000>, |
117 | <3 0 0x1c000000 0x04000000>, | 117 | <3 0 0 0x1c000000 0x04000000>, |
118 | <4 0 0x0c000000 0x04000000>, | 118 | <4 0 0 0x0c000000 0x04000000>, |
119 | <5 0 0x10000000 0x04000000>; | 119 | <5 0 0 0x10000000 0x04000000>; |
120 | 120 | ||
121 | interrupt-map-mask = <0 0 63>; | 121 | interrupt-map-mask = <0 0 63>; |
122 | interrupt-map = <0 0 0 &gic 0 0 4>, | 122 | interrupt-map = <0 0 0 &gic 0 0 4>, |
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts new file mode 100644 index 000000000000..4890a81c5467 --- /dev/null +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | |||
@@ -0,0 +1,188 @@ | |||
1 | /* | ||
2 | * ARM Ltd. Versatile Express | ||
3 | * | ||
4 | * CoreTile Express A15x2 A7x3 | ||
5 | * Cortex-A15_A7 MPCore (V2P-CA15_A7) | ||
6 | * | ||
7 | * HBI-0249A | ||
8 | */ | ||
9 | |||
10 | /dts-v1/; | ||
11 | |||
12 | / { | ||
13 | model = "V2P-CA15_CA7"; | ||
14 | arm,hbi = <0x249>; | ||
15 | compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; | ||
16 | interrupt-parent = <&gic>; | ||
17 | #address-cells = <2>; | ||
18 | #size-cells = <2>; | ||
19 | |||
20 | chosen { }; | ||
21 | |||
22 | aliases { | ||
23 | serial0 = &v2m_serial0; | ||
24 | serial1 = &v2m_serial1; | ||
25 | serial2 = &v2m_serial2; | ||
26 | serial3 = &v2m_serial3; | ||
27 | i2c0 = &v2m_i2c_dvi; | ||
28 | i2c1 = &v2m_i2c_pcie; | ||
29 | }; | ||
30 | |||
31 | cpus { | ||
32 | #address-cells = <1>; | ||
33 | #size-cells = <0>; | ||
34 | |||
35 | cpu0: cpu@0 { | ||
36 | device_type = "cpu"; | ||
37 | compatible = "arm,cortex-a15"; | ||
38 | reg = <0>; | ||
39 | }; | ||
40 | |||
41 | cpu1: cpu@1 { | ||
42 | device_type = "cpu"; | ||
43 | compatible = "arm,cortex-a15"; | ||
44 | reg = <1>; | ||
45 | }; | ||
46 | |||
47 | /* A7s disabled till big.LITTLE patches are available... | ||
48 | cpu2: cpu@2 { | ||
49 | device_type = "cpu"; | ||
50 | compatible = "arm,cortex-a7"; | ||
51 | reg = <0x100>; | ||
52 | }; | ||
53 | |||
54 | cpu3: cpu@3 { | ||
55 | device_type = "cpu"; | ||
56 | compatible = "arm,cortex-a7"; | ||
57 | reg = <0x101>; | ||
58 | }; | ||
59 | |||
60 | cpu4: cpu@4 { | ||
61 | device_type = "cpu"; | ||
62 | compatible = "arm,cortex-a7"; | ||
63 | reg = <0x102>; | ||
64 | }; | ||
65 | */ | ||
66 | }; | ||
67 | |||
68 | memory@80000000 { | ||
69 | device_type = "memory"; | ||
70 | reg = <0 0x80000000 0 0x40000000>; | ||
71 | }; | ||
72 | |||
73 | wdt@2a490000 { | ||
74 | compatible = "arm,sp805", "arm,primecell"; | ||
75 | reg = <0 0x2a490000 0 0x1000>; | ||
76 | interrupts = <98>; | ||
77 | }; | ||
78 | |||
79 | hdlcd@2b000000 { | ||
80 | compatible = "arm,hdlcd"; | ||
81 | reg = <0 0x2b000000 0 0x1000>; | ||
82 | interrupts = <0 85 4>; | ||
83 | }; | ||
84 | |||
85 | memory-controller@2b0a0000 { | ||
86 | compatible = "arm,pl341", "arm,primecell"; | ||
87 | reg = <0 0x2b0a0000 0 0x1000>; | ||
88 | }; | ||
89 | |||
90 | gic: interrupt-controller@2c001000 { | ||
91 | compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; | ||
92 | #interrupt-cells = <3>; | ||
93 | #address-cells = <0>; | ||
94 | interrupt-controller; | ||
95 | reg = <0 0x2c001000 0 0x1000>, | ||
96 | <0 0x2c002000 0 0x1000>, | ||
97 | <0 0x2c004000 0 0x2000>, | ||
98 | <0 0x2c006000 0 0x2000>; | ||
99 | interrupts = <1 9 0xf04>; | ||
100 | }; | ||
101 | |||
102 | memory-controller@7ffd0000 { | ||
103 | compatible = "arm,pl354", "arm,primecell"; | ||
104 | reg = <0 0x7ffd0000 0 0x1000>; | ||
105 | interrupts = <0 86 4>, | ||
106 | <0 87 4>; | ||
107 | }; | ||
108 | |||
109 | dma@7ff00000 { | ||
110 | compatible = "arm,pl330", "arm,primecell"; | ||
111 | reg = <0 0x7ff00000 0 0x1000>; | ||
112 | interrupts = <0 92 4>, | ||
113 | <0 88 4>, | ||
114 | <0 89 4>, | ||
115 | <0 90 4>, | ||
116 | <0 91 4>; | ||
117 | }; | ||
118 | |||
119 | timer { | ||
120 | compatible = "arm,armv7-timer"; | ||
121 | interrupts = <1 13 0xf08>, | ||
122 | <1 14 0xf08>, | ||
123 | <1 11 0xf08>, | ||
124 | <1 10 0xf08>; | ||
125 | }; | ||
126 | |||
127 | pmu { | ||
128 | compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; | ||
129 | interrupts = <0 68 4>, | ||
130 | <0 69 4>; | ||
131 | }; | ||
132 | |||
133 | motherboard { | ||
134 | ranges = <0 0 0 0x08000000 0x04000000>, | ||
135 | <1 0 0 0x14000000 0x04000000>, | ||
136 | <2 0 0 0x18000000 0x04000000>, | ||
137 | <3 0 0 0x1c000000 0x04000000>, | ||
138 | <4 0 0 0x0c000000 0x04000000>, | ||
139 | <5 0 0 0x10000000 0x04000000>; | ||
140 | |||
141 | interrupt-map-mask = <0 0 63>; | ||
142 | interrupt-map = <0 0 0 &gic 0 0 4>, | ||
143 | <0 0 1 &gic 0 1 4>, | ||
144 | <0 0 2 &gic 0 2 4>, | ||
145 | <0 0 3 &gic 0 3 4>, | ||
146 | <0 0 4 &gic 0 4 4>, | ||
147 | <0 0 5 &gic 0 5 4>, | ||
148 | <0 0 6 &gic 0 6 4>, | ||
149 | <0 0 7 &gic 0 7 4>, | ||
150 | <0 0 8 &gic 0 8 4>, | ||
151 | <0 0 9 &gic 0 9 4>, | ||
152 | <0 0 10 &gic 0 10 4>, | ||
153 | <0 0 11 &gic 0 11 4>, | ||
154 | <0 0 12 &gic 0 12 4>, | ||
155 | <0 0 13 &gic 0 13 4>, | ||
156 | <0 0 14 &gic 0 14 4>, | ||
157 | <0 0 15 &gic 0 15 4>, | ||
158 | <0 0 16 &gic 0 16 4>, | ||
159 | <0 0 17 &gic 0 17 4>, | ||
160 | <0 0 18 &gic 0 18 4>, | ||
161 | <0 0 19 &gic 0 19 4>, | ||
162 | <0 0 20 &gic 0 20 4>, | ||
163 | <0 0 21 &gic 0 21 4>, | ||
164 | <0 0 22 &gic 0 22 4>, | ||
165 | <0 0 23 &gic 0 23 4>, | ||
166 | <0 0 24 &gic 0 24 4>, | ||
167 | <0 0 25 &gic 0 25 4>, | ||
168 | <0 0 26 &gic 0 26 4>, | ||
169 | <0 0 27 &gic 0 27 4>, | ||
170 | <0 0 28 &gic 0 28 4>, | ||
171 | <0 0 29 &gic 0 29 4>, | ||
172 | <0 0 30 &gic 0 30 4>, | ||
173 | <0 0 31 &gic 0 31 4>, | ||
174 | <0 0 32 &gic 0 32 4>, | ||
175 | <0 0 33 &gic 0 33 4>, | ||
176 | <0 0 34 &gic 0 34 4>, | ||
177 | <0 0 35 &gic 0 35 4>, | ||
178 | <0 0 36 &gic 0 36 4>, | ||
179 | <0 0 37 &gic 0 37 4>, | ||
180 | <0 0 38 &gic 0 38 4>, | ||
181 | <0 0 39 &gic 0 39 4>, | ||
182 | <0 0 40 &gic 0 40 4>, | ||
183 | <0 0 41 &gic 0 41 4>, | ||
184 | <0 0 42 &gic 0 42 4>; | ||
185 | }; | ||
186 | }; | ||
187 | |||
188 | /include/ "vexpress-v2m-rs1.dtsi" | ||
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 4fa60547494a..eceed186a3c1 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig | |||
@@ -1,5 +1,7 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | 1 | CONFIG_EXPERIMENTAL=y |
2 | CONFIG_SYSVIPC=y | 2 | CONFIG_SYSVIPC=y |
3 | CONFIG_NO_HZ=y | ||
4 | CONFIG_HIGH_RES_TIMERS=y | ||
3 | CONFIG_IKCONFIG=y | 5 | CONFIG_IKCONFIG=y |
4 | CONFIG_IKCONFIG_PROC=y | 6 | CONFIG_IKCONFIG_PROC=y |
5 | CONFIG_LOG_BUF_SHIFT=16 | 7 | CONFIG_LOG_BUF_SHIFT=16 |
@@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y | |||
16 | # CONFIG_BLK_DEV_BSG is not set | 18 | # CONFIG_BLK_DEV_BSG is not set |
17 | CONFIG_PARTITION_ADVANCED=y | 19 | CONFIG_PARTITION_ADVANCED=y |
18 | CONFIG_ARCH_LPC32XX=y | 20 | CONFIG_ARCH_LPC32XX=y |
19 | CONFIG_NO_HZ=y | ||
20 | CONFIG_HIGH_RES_TIMERS=y | ||
21 | CONFIG_PREEMPT=y | 21 | CONFIG_PREEMPT=y |
22 | CONFIG_AEABI=y | 22 | CONFIG_AEABI=y |
23 | CONFIG_ZBOOT_ROM_TEXT=0x0 | 23 | CONFIG_ZBOOT_ROM_TEXT=0x0 |
@@ -52,13 +52,17 @@ CONFIG_MTD=y | |||
52 | CONFIG_MTD_CMDLINE_PARTS=y | 52 | CONFIG_MTD_CMDLINE_PARTS=y |
53 | CONFIG_MTD_CHAR=y | 53 | CONFIG_MTD_CHAR=y |
54 | CONFIG_MTD_BLOCK=y | 54 | CONFIG_MTD_BLOCK=y |
55 | CONFIG_MTD_M25P80=y | ||
55 | CONFIG_MTD_NAND=y | 56 | CONFIG_MTD_NAND=y |
56 | CONFIG_MTD_NAND_MUSEUM_IDS=y | 57 | CONFIG_MTD_NAND_MUSEUM_IDS=y |
58 | CONFIG_MTD_NAND_SLC_LPC32XX=y | ||
59 | CONFIG_MTD_NAND_MLC_LPC32XX=y | ||
57 | CONFIG_BLK_DEV_LOOP=y | 60 | CONFIG_BLK_DEV_LOOP=y |
58 | CONFIG_BLK_DEV_CRYPTOLOOP=y | 61 | CONFIG_BLK_DEV_CRYPTOLOOP=y |
59 | CONFIG_BLK_DEV_RAM=y | 62 | CONFIG_BLK_DEV_RAM=y |
60 | CONFIG_BLK_DEV_RAM_COUNT=1 | 63 | CONFIG_BLK_DEV_RAM_COUNT=1 |
61 | CONFIG_BLK_DEV_RAM_SIZE=16384 | 64 | CONFIG_BLK_DEV_RAM_SIZE=16384 |
65 | CONFIG_EEPROM_AT24=y | ||
62 | CONFIG_EEPROM_AT25=y | 66 | CONFIG_EEPROM_AT25=y |
63 | CONFIG_SCSI=y | 67 | CONFIG_SCSI=y |
64 | CONFIG_BLK_DEV_SD=y | 68 | CONFIG_BLK_DEV_SD=y |
@@ -79,16 +83,22 @@ CONFIG_LPC_ENET=y | |||
79 | # CONFIG_NET_VENDOR_STMICRO is not set | 83 | # CONFIG_NET_VENDOR_STMICRO is not set |
80 | CONFIG_SMSC_PHY=y | 84 | CONFIG_SMSC_PHY=y |
81 | # CONFIG_WLAN is not set | 85 | # CONFIG_WLAN is not set |
86 | CONFIG_INPUT_MATRIXKMAP=y | ||
82 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | 87 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set |
83 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 | 88 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 |
84 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 | 89 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 |
85 | CONFIG_INPUT_EVDEV=y | 90 | CONFIG_INPUT_EVDEV=y |
91 | # CONFIG_KEYBOARD_ATKBD is not set | ||
92 | CONFIG_KEYBOARD_LPC32XX=y | ||
86 | # CONFIG_INPUT_MOUSE is not set | 93 | # CONFIG_INPUT_MOUSE is not set |
87 | CONFIG_INPUT_TOUCHSCREEN=y | 94 | CONFIG_INPUT_TOUCHSCREEN=y |
88 | CONFIG_TOUCHSCREEN_LPC32XX=y | 95 | CONFIG_TOUCHSCREEN_LPC32XX=y |
96 | CONFIG_SERIO_LIBPS2=y | ||
89 | # CONFIG_LEGACY_PTYS is not set | 97 | # CONFIG_LEGACY_PTYS is not set |
90 | CONFIG_SERIAL_8250=y | 98 | CONFIG_SERIAL_8250=y |
91 | CONFIG_SERIAL_8250_CONSOLE=y | 99 | CONFIG_SERIAL_8250_CONSOLE=y |
100 | CONFIG_SERIAL_HS_LPC32XX=y | ||
101 | CONFIG_SERIAL_OF_PLATFORM=y | ||
92 | # CONFIG_HW_RANDOM is not set | 102 | # CONFIG_HW_RANDOM is not set |
93 | CONFIG_I2C=y | 103 | CONFIG_I2C=y |
94 | CONFIG_I2C_CHARDEV=y | 104 | CONFIG_I2C_CHARDEV=y |
@@ -96,7 +106,8 @@ CONFIG_I2C_PNX=y | |||
96 | CONFIG_SPI=y | 106 | CONFIG_SPI=y |
97 | CONFIG_SPI_PL022=y | 107 | CONFIG_SPI_PL022=y |
98 | CONFIG_GPIO_SYSFS=y | 108 | CONFIG_GPIO_SYSFS=y |
99 | # CONFIG_HWMON is not set | 109 | CONFIG_SENSORS_DS620=y |
110 | CONFIG_SENSORS_MAX6639=y | ||
100 | CONFIG_WATCHDOG=y | 111 | CONFIG_WATCHDOG=y |
101 | CONFIG_PNX4008_WATCHDOG=y | 112 | CONFIG_PNX4008_WATCHDOG=y |
102 | CONFIG_FB=y | 113 | CONFIG_FB=y |
@@ -133,6 +144,8 @@ CONFIG_MMC=y | |||
133 | CONFIG_MMC_ARMMMCI=y | 144 | CONFIG_MMC_ARMMMCI=y |
134 | CONFIG_NEW_LEDS=y | 145 | CONFIG_NEW_LEDS=y |
135 | CONFIG_LEDS_CLASS=y | 146 | CONFIG_LEDS_CLASS=y |
147 | CONFIG_LEDS_PCA9532=y | ||
148 | CONFIG_LEDS_PCA9532_GPIO=y | ||
136 | CONFIG_LEDS_GPIO=y | 149 | CONFIG_LEDS_GPIO=y |
137 | CONFIG_LEDS_TRIGGERS=y | 150 | CONFIG_LEDS_TRIGGERS=y |
138 | CONFIG_LEDS_TRIGGER_TIMER=y | 151 | CONFIG_LEDS_TRIGGER_TIMER=y |
@@ -146,10 +159,10 @@ CONFIG_RTC_DRV_DS1374=y | |||
146 | CONFIG_RTC_DRV_PCF8563=y | 159 | CONFIG_RTC_DRV_PCF8563=y |
147 | CONFIG_RTC_DRV_LPC32XX=y | 160 | CONFIG_RTC_DRV_LPC32XX=y |
148 | CONFIG_DMADEVICES=y | 161 | CONFIG_DMADEVICES=y |
149 | CONFIG_AMBA_PL08X=y | ||
150 | CONFIG_STAGING=y | 162 | CONFIG_STAGING=y |
151 | CONFIG_IIO=y | ||
152 | CONFIG_LPC32XX_ADC=y | 163 | CONFIG_LPC32XX_ADC=y |
164 | CONFIG_MAX517=y | ||
165 | CONFIG_IIO=y | ||
153 | CONFIG_EXT2_FS=y | 166 | CONFIG_EXT2_FS=y |
154 | CONFIG_AUTOFS4_FS=y | 167 | CONFIG_AUTOFS4_FS=y |
155 | CONFIG_MSDOS_FS=y | 168 | CONFIG_MSDOS_FS=y |
@@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y | |||
159 | CONFIG_JFFS2_FS_WBUF_VERIFY=y | 172 | CONFIG_JFFS2_FS_WBUF_VERIFY=y |
160 | CONFIG_CRAMFS=y | 173 | CONFIG_CRAMFS=y |
161 | CONFIG_NFS_FS=y | 174 | CONFIG_NFS_FS=y |
162 | CONFIG_NFS_V3=y | ||
163 | CONFIG_ROOT_NFS=y | 175 | CONFIG_ROOT_NFS=y |
164 | CONFIG_NLS_CODEPAGE_437=y | 176 | CONFIG_NLS_CODEPAGE_437=y |
165 | CONFIG_NLS_ASCII=y | 177 | CONFIG_NLS_ASCII=y |
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 9854ff4279e0..d3c29b377af9 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig | |||
@@ -176,7 +176,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | |||
176 | CONFIG_USB_DEVICEFS=y | 176 | CONFIG_USB_DEVICEFS=y |
177 | CONFIG_USB_SUSPEND=y | 177 | CONFIG_USB_SUSPEND=y |
178 | CONFIG_USB_MON=y | 178 | CONFIG_USB_MON=y |
179 | CONFIG_USB_EHCI_HCD=y | ||
180 | CONFIG_USB_WDM=y | 179 | CONFIG_USB_WDM=y |
181 | CONFIG_USB_STORAGE=y | 180 | CONFIG_USB_STORAGE=y |
182 | CONFIG_USB_LIBUSUAL=y | 181 | CONFIG_USB_LIBUSUAL=y |
@@ -197,6 +196,7 @@ CONFIG_RTC_DRV_TWL4030=y | |||
197 | CONFIG_EXT2_FS=y | 196 | CONFIG_EXT2_FS=y |
198 | CONFIG_EXT3_FS=y | 197 | CONFIG_EXT3_FS=y |
199 | # CONFIG_EXT3_FS_XATTR is not set | 198 | # CONFIG_EXT3_FS_XATTR is not set |
199 | CONFIG_EXT4_FS=y | ||
200 | CONFIG_QUOTA=y | 200 | CONFIG_QUOTA=y |
201 | CONFIG_QFMT_V2=y | 201 | CONFIG_QFMT_V2=y |
202 | CONFIG_MSDOS_FS=y | 202 | CONFIG_MSDOS_FS=y |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index 8349d4e97e2b..16cedb42c0c3 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -40,13 +40,6 @@ | |||
40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
42 | 42 | ||
43 | /* | ||
44 | * No architecture-specific irq_finish function defined in arm/arch/irqs.h. | ||
45 | */ | ||
46 | #ifndef irq_finish | ||
47 | #define irq_finish(irq) do { } while (0) | ||
48 | #endif | ||
49 | |||
50 | unsigned long irq_err_count; | 43 | unsigned long irq_err_count; |
51 | 44 | ||
52 | int arch_show_interrupts(struct seq_file *p, int prec) | 45 | int arch_show_interrupts(struct seq_file *p, int prec) |
@@ -85,9 +78,6 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs) | |||
85 | generic_handle_irq(irq); | 78 | generic_handle_irq(irq); |
86 | } | 79 | } |
87 | 80 | ||
88 | /* AT91 specific workaround */ | ||
89 | irq_finish(irq); | ||
90 | |||
91 | irq_exit(); | 81 | irq_exit(); |
92 | set_irq_regs(old_regs); | 82 | set_irq_regs(old_regs); |
93 | } | 83 | } |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 19505c0a3f01..c8050b14e615 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
@@ -29,12 +29,16 @@ comment "Atmel AT91 Processor" | |||
29 | config SOC_AT91SAM9 | 29 | config SOC_AT91SAM9 |
30 | bool | 30 | bool |
31 | select CPU_ARM926T | 31 | select CPU_ARM926T |
32 | select MULTI_IRQ_HANDLER | ||
33 | select SPARSE_IRQ | ||
32 | select AT91_SAM9_TIME | 34 | select AT91_SAM9_TIME |
33 | select AT91_SAM9_SMC | 35 | select AT91_SAM9_SMC |
34 | 36 | ||
35 | config SOC_AT91RM9200 | 37 | config SOC_AT91RM9200 |
36 | bool "AT91RM9200" | 38 | bool "AT91RM9200" |
37 | select CPU_ARM920T | 39 | select CPU_ARM920T |
40 | select MULTI_IRQ_HANDLER | ||
41 | select SPARSE_IRQ | ||
38 | select GENERIC_CLOCKEVENTS | 42 | select GENERIC_CLOCKEVENTS |
39 | select HAVE_AT91_DBGU0 | 43 | select HAVE_AT91_DBGU0 |
40 | 44 | ||
@@ -140,6 +144,8 @@ config ARCH_AT91SAM9G45 | |||
140 | config ARCH_AT91X40 | 144 | config ARCH_AT91X40 |
141 | bool "AT91x40" | 145 | bool "AT91x40" |
142 | depends on !MMU | 146 | depends on !MMU |
147 | select MULTI_IRQ_HANDLER | ||
148 | select SPARSE_IRQ | ||
143 | select ARCH_USES_GETTIMEOFFSET | 149 | select ARCH_USES_GETTIMEOFFSET |
144 | 150 | ||
145 | endchoice | 151 | endchoice |
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 9e84fe4f2aaa..30bb7332e30b 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot | |||
@@ -15,7 +15,9 @@ endif | |||
15 | 15 | ||
16 | # Keep dtb files sorted alphabetically for each SoC | 16 | # Keep dtb files sorted alphabetically for each SoC |
17 | # sam9260 | 17 | # sam9260 |
18 | dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb | ||
18 | dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb | 19 | dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb |
20 | dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb | ||
19 | dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb | 21 | dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb |
20 | dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb | 22 | dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb |
21 | # sam9263 | 23 | # sam9263 |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 26917687fc30..6f50c6722276 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
18 | #include <asm/system_misc.h> | 18 | #include <asm/system_misc.h> |
19 | #include <mach/at91rm9200.h> | 19 | #include <mach/at91rm9200.h> |
20 | #include <mach/at91_aic.h> | ||
20 | #include <mach/at91_pmc.h> | 21 | #include <mach/at91_pmc.h> |
21 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
22 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c index e6b7d0533dd7..01fb7325fecc 100644 --- a/arch/arm/mach-at91/at91rm9200_devices.c +++ b/arch/arm/mach-at91/at91rm9200_devices.c | |||
@@ -41,8 +41,8 @@ static struct resource usbh_resources[] = { | |||
41 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
42 | }, | 42 | }, |
43 | [1] = { | 43 | [1] = { |
44 | .start = AT91RM9200_ID_UHP, | 44 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, |
45 | .end = AT91RM9200_ID_UHP, | 45 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_UHP, |
46 | .flags = IORESOURCE_IRQ, | 46 | .flags = IORESOURCE_IRQ, |
47 | }, | 47 | }, |
48 | }; | 48 | }; |
@@ -94,8 +94,8 @@ static struct resource udc_resources[] = { | |||
94 | .flags = IORESOURCE_MEM, | 94 | .flags = IORESOURCE_MEM, |
95 | }, | 95 | }, |
96 | [1] = { | 96 | [1] = { |
97 | .start = AT91RM9200_ID_UDP, | 97 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, |
98 | .end = AT91RM9200_ID_UDP, | 98 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_UDP, |
99 | .flags = IORESOURCE_IRQ, | 99 | .flags = IORESOURCE_IRQ, |
100 | }, | 100 | }, |
101 | }; | 101 | }; |
@@ -145,8 +145,8 @@ static struct resource eth_resources[] = { | |||
145 | .flags = IORESOURCE_MEM, | 145 | .flags = IORESOURCE_MEM, |
146 | }, | 146 | }, |
147 | [1] = { | 147 | [1] = { |
148 | .start = AT91RM9200_ID_EMAC, | 148 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, |
149 | .end = AT91RM9200_ID_EMAC, | 149 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC, |
150 | .flags = IORESOURCE_IRQ, | 150 | .flags = IORESOURCE_IRQ, |
151 | }, | 151 | }, |
152 | }; | 152 | }; |
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = { | |||
305 | .flags = IORESOURCE_MEM, | 305 | .flags = IORESOURCE_MEM, |
306 | }, | 306 | }, |
307 | [1] = { | 307 | [1] = { |
308 | .start = AT91RM9200_ID_MCI, | 308 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, |
309 | .end = AT91RM9200_ID_MCI, | 309 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_MCI, |
310 | .flags = IORESOURCE_IRQ, | 310 | .flags = IORESOURCE_IRQ, |
311 | }, | 311 | }, |
312 | }; | 312 | }; |
@@ -488,8 +488,8 @@ static struct resource twi_resources[] = { | |||
488 | .flags = IORESOURCE_MEM, | 488 | .flags = IORESOURCE_MEM, |
489 | }, | 489 | }, |
490 | [1] = { | 490 | [1] = { |
491 | .start = AT91RM9200_ID_TWI, | 491 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, |
492 | .end = AT91RM9200_ID_TWI, | 492 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TWI, |
493 | .flags = IORESOURCE_IRQ, | 493 | .flags = IORESOURCE_IRQ, |
494 | }, | 494 | }, |
495 | }; | 495 | }; |
@@ -532,8 +532,8 @@ static struct resource spi_resources[] = { | |||
532 | .flags = IORESOURCE_MEM, | 532 | .flags = IORESOURCE_MEM, |
533 | }, | 533 | }, |
534 | [1] = { | 534 | [1] = { |
535 | .start = AT91RM9200_ID_SPI, | 535 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, |
536 | .end = AT91RM9200_ID_SPI, | 536 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SPI, |
537 | .flags = IORESOURCE_IRQ, | 537 | .flags = IORESOURCE_IRQ, |
538 | }, | 538 | }, |
539 | }; | 539 | }; |
@@ -598,18 +598,18 @@ static struct resource tcb0_resources[] = { | |||
598 | .flags = IORESOURCE_MEM, | 598 | .flags = IORESOURCE_MEM, |
599 | }, | 599 | }, |
600 | [1] = { | 600 | [1] = { |
601 | .start = AT91RM9200_ID_TC0, | 601 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, |
602 | .end = AT91RM9200_ID_TC0, | 602 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC0, |
603 | .flags = IORESOURCE_IRQ, | 603 | .flags = IORESOURCE_IRQ, |
604 | }, | 604 | }, |
605 | [2] = { | 605 | [2] = { |
606 | .start = AT91RM9200_ID_TC1, | 606 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, |
607 | .end = AT91RM9200_ID_TC1, | 607 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC1, |
608 | .flags = IORESOURCE_IRQ, | 608 | .flags = IORESOURCE_IRQ, |
609 | }, | 609 | }, |
610 | [3] = { | 610 | [3] = { |
611 | .start = AT91RM9200_ID_TC2, | 611 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, |
612 | .end = AT91RM9200_ID_TC2, | 612 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC2, |
613 | .flags = IORESOURCE_IRQ, | 613 | .flags = IORESOURCE_IRQ, |
614 | }, | 614 | }, |
615 | }; | 615 | }; |
@@ -628,18 +628,18 @@ static struct resource tcb1_resources[] = { | |||
628 | .flags = IORESOURCE_MEM, | 628 | .flags = IORESOURCE_MEM, |
629 | }, | 629 | }, |
630 | [1] = { | 630 | [1] = { |
631 | .start = AT91RM9200_ID_TC3, | 631 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, |
632 | .end = AT91RM9200_ID_TC3, | 632 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC3, |
633 | .flags = IORESOURCE_IRQ, | 633 | .flags = IORESOURCE_IRQ, |
634 | }, | 634 | }, |
635 | [2] = { | 635 | [2] = { |
636 | .start = AT91RM9200_ID_TC4, | 636 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, |
637 | .end = AT91RM9200_ID_TC4, | 637 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC4, |
638 | .flags = IORESOURCE_IRQ, | 638 | .flags = IORESOURCE_IRQ, |
639 | }, | 639 | }, |
640 | [3] = { | 640 | [3] = { |
641 | .start = AT91RM9200_ID_TC5, | 641 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, |
642 | .end = AT91RM9200_ID_TC5, | 642 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_TC5, |
643 | .flags = IORESOURCE_IRQ, | 643 | .flags = IORESOURCE_IRQ, |
644 | }, | 644 | }, |
645 | }; | 645 | }; |
@@ -673,8 +673,8 @@ static struct resource rtc_resources[] = { | |||
673 | .flags = IORESOURCE_MEM, | 673 | .flags = IORESOURCE_MEM, |
674 | }, | 674 | }, |
675 | [1] = { | 675 | [1] = { |
676 | .start = AT91_ID_SYS, | 676 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
677 | .end = AT91_ID_SYS, | 677 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
678 | .flags = IORESOURCE_IRQ, | 678 | .flags = IORESOURCE_IRQ, |
679 | }, | 679 | }, |
680 | }; | 680 | }; |
@@ -729,8 +729,8 @@ static struct resource ssc0_resources[] = { | |||
729 | .flags = IORESOURCE_MEM, | 729 | .flags = IORESOURCE_MEM, |
730 | }, | 730 | }, |
731 | [1] = { | 731 | [1] = { |
732 | .start = AT91RM9200_ID_SSC0, | 732 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, |
733 | .end = AT91RM9200_ID_SSC0, | 733 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0, |
734 | .flags = IORESOURCE_IRQ, | 734 | .flags = IORESOURCE_IRQ, |
735 | }, | 735 | }, |
736 | }; | 736 | }; |
@@ -771,8 +771,8 @@ static struct resource ssc1_resources[] = { | |||
771 | .flags = IORESOURCE_MEM, | 771 | .flags = IORESOURCE_MEM, |
772 | }, | 772 | }, |
773 | [1] = { | 773 | [1] = { |
774 | .start = AT91RM9200_ID_SSC1, | 774 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, |
775 | .end = AT91RM9200_ID_SSC1, | 775 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1, |
776 | .flags = IORESOURCE_IRQ, | 776 | .flags = IORESOURCE_IRQ, |
777 | }, | 777 | }, |
778 | }; | 778 | }; |
@@ -813,8 +813,8 @@ static struct resource ssc2_resources[] = { | |||
813 | .flags = IORESOURCE_MEM, | 813 | .flags = IORESOURCE_MEM, |
814 | }, | 814 | }, |
815 | [1] = { | 815 | [1] = { |
816 | .start = AT91RM9200_ID_SSC2, | 816 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, |
817 | .end = AT91RM9200_ID_SSC2, | 817 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2, |
818 | .flags = IORESOURCE_IRQ, | 818 | .flags = IORESOURCE_IRQ, |
819 | }, | 819 | }, |
820 | }; | 820 | }; |
@@ -897,8 +897,8 @@ static struct resource dbgu_resources[] = { | |||
897 | .flags = IORESOURCE_MEM, | 897 | .flags = IORESOURCE_MEM, |
898 | }, | 898 | }, |
899 | [1] = { | 899 | [1] = { |
900 | .start = AT91_ID_SYS, | 900 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
901 | .end = AT91_ID_SYS, | 901 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
902 | .flags = IORESOURCE_IRQ, | 902 | .flags = IORESOURCE_IRQ, |
903 | }, | 903 | }, |
904 | }; | 904 | }; |
@@ -935,8 +935,8 @@ static struct resource uart0_resources[] = { | |||
935 | .flags = IORESOURCE_MEM, | 935 | .flags = IORESOURCE_MEM, |
936 | }, | 936 | }, |
937 | [1] = { | 937 | [1] = { |
938 | .start = AT91RM9200_ID_US0, | 938 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US0, |
939 | .end = AT91RM9200_ID_US0, | 939 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US0, |
940 | .flags = IORESOURCE_IRQ, | 940 | .flags = IORESOURCE_IRQ, |
941 | }, | 941 | }, |
942 | }; | 942 | }; |
@@ -984,8 +984,8 @@ static struct resource uart1_resources[] = { | |||
984 | .flags = IORESOURCE_MEM, | 984 | .flags = IORESOURCE_MEM, |
985 | }, | 985 | }, |
986 | [1] = { | 986 | [1] = { |
987 | .start = AT91RM9200_ID_US1, | 987 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US1, |
988 | .end = AT91RM9200_ID_US1, | 988 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US1, |
989 | .flags = IORESOURCE_IRQ, | 989 | .flags = IORESOURCE_IRQ, |
990 | }, | 990 | }, |
991 | }; | 991 | }; |
@@ -1035,8 +1035,8 @@ static struct resource uart2_resources[] = { | |||
1035 | .flags = IORESOURCE_MEM, | 1035 | .flags = IORESOURCE_MEM, |
1036 | }, | 1036 | }, |
1037 | [1] = { | 1037 | [1] = { |
1038 | .start = AT91RM9200_ID_US2, | 1038 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US2, |
1039 | .end = AT91RM9200_ID_US2, | 1039 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US2, |
1040 | .flags = IORESOURCE_IRQ, | 1040 | .flags = IORESOURCE_IRQ, |
1041 | }, | 1041 | }, |
1042 | }; | 1042 | }; |
@@ -1078,8 +1078,8 @@ static struct resource uart3_resources[] = { | |||
1078 | .flags = IORESOURCE_MEM, | 1078 | .flags = IORESOURCE_MEM, |
1079 | }, | 1079 | }, |
1080 | [1] = { | 1080 | [1] = { |
1081 | .start = AT91RM9200_ID_US3, | 1081 | .start = NR_IRQS_LEGACY + AT91RM9200_ID_US3, |
1082 | .end = AT91RM9200_ID_US3, | 1082 | .end = NR_IRQS_LEGACY + AT91RM9200_ID_US3, |
1083 | .flags = IORESOURCE_IRQ, | 1083 | .flags = IORESOURCE_IRQ, |
1084 | }, | 1084 | }, |
1085 | }; | 1085 | }; |
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index 2b1e438ed878..30c7f26a4668 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
21 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
22 | #include <mach/at91sam9260.h> | 22 | #include <mach/at91sam9260.h> |
23 | #include <mach/at91_aic.h> | ||
23 | #include <mach/at91_pmc.h> | 24 | #include <mach/at91_pmc.h> |
24 | #include <mach/at91_rstc.h> | 25 | #include <mach/at91_rstc.h> |
25 | 26 | ||
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index 0ded951f785a..7b9c2ba396ed 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = { | |||
45 | .flags = IORESOURCE_MEM, | 45 | .flags = IORESOURCE_MEM, |
46 | }, | 46 | }, |
47 | [1] = { | 47 | [1] = { |
48 | .start = AT91SAM9260_ID_UHP, | 48 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, |
49 | .end = AT91SAM9260_ID_UHP, | 49 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP, |
50 | .flags = IORESOURCE_IRQ, | 50 | .flags = IORESOURCE_IRQ, |
51 | }, | 51 | }, |
52 | }; | 52 | }; |
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = { | |||
98 | .flags = IORESOURCE_MEM, | 98 | .flags = IORESOURCE_MEM, |
99 | }, | 99 | }, |
100 | [1] = { | 100 | [1] = { |
101 | .start = AT91SAM9260_ID_UDP, | 101 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, |
102 | .end = AT91SAM9260_ID_UDP, | 102 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP, |
103 | .flags = IORESOURCE_IRQ, | 103 | .flags = IORESOURCE_IRQ, |
104 | }, | 104 | }, |
105 | }; | 105 | }; |
@@ -149,8 +149,8 @@ static struct resource eth_resources[] = { | |||
149 | .flags = IORESOURCE_MEM, | 149 | .flags = IORESOURCE_MEM, |
150 | }, | 150 | }, |
151 | [1] = { | 151 | [1] = { |
152 | .start = AT91SAM9260_ID_EMAC, | 152 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, |
153 | .end = AT91SAM9260_ID_EMAC, | 153 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC, |
154 | .flags = IORESOURCE_IRQ, | 154 | .flags = IORESOURCE_IRQ, |
155 | }, | 155 | }, |
156 | }; | 156 | }; |
@@ -223,8 +223,8 @@ static struct resource mmc_resources[] = { | |||
223 | .flags = IORESOURCE_MEM, | 223 | .flags = IORESOURCE_MEM, |
224 | }, | 224 | }, |
225 | [1] = { | 225 | [1] = { |
226 | .start = AT91SAM9260_ID_MCI, | 226 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
227 | .end = AT91SAM9260_ID_MCI, | 227 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
228 | .flags = IORESOURCE_IRQ, | 228 | .flags = IORESOURCE_IRQ, |
229 | }, | 229 | }, |
230 | }; | 230 | }; |
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = { | |||
305 | .flags = IORESOURCE_MEM, | 305 | .flags = IORESOURCE_MEM, |
306 | }, | 306 | }, |
307 | [1] = { | 307 | [1] = { |
308 | .start = AT91SAM9260_ID_MCI, | 308 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
309 | .end = AT91SAM9260_ID_MCI, | 309 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI, |
310 | .flags = IORESOURCE_IRQ, | 310 | .flags = IORESOURCE_IRQ, |
311 | }, | 311 | }, |
312 | }; | 312 | }; |
@@ -496,8 +496,8 @@ static struct resource twi_resources[] = { | |||
496 | .flags = IORESOURCE_MEM, | 496 | .flags = IORESOURCE_MEM, |
497 | }, | 497 | }, |
498 | [1] = { | 498 | [1] = { |
499 | .start = AT91SAM9260_ID_TWI, | 499 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, |
500 | .end = AT91SAM9260_ID_TWI, | 500 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI, |
501 | .flags = IORESOURCE_IRQ, | 501 | .flags = IORESOURCE_IRQ, |
502 | }, | 502 | }, |
503 | }; | 503 | }; |
@@ -540,8 +540,8 @@ static struct resource spi0_resources[] = { | |||
540 | .flags = IORESOURCE_MEM, | 540 | .flags = IORESOURCE_MEM, |
541 | }, | 541 | }, |
542 | [1] = { | 542 | [1] = { |
543 | .start = AT91SAM9260_ID_SPI0, | 543 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, |
544 | .end = AT91SAM9260_ID_SPI0, | 544 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0, |
545 | .flags = IORESOURCE_IRQ, | 545 | .flags = IORESOURCE_IRQ, |
546 | }, | 546 | }, |
547 | }; | 547 | }; |
@@ -566,8 +566,8 @@ static struct resource spi1_resources[] = { | |||
566 | .flags = IORESOURCE_MEM, | 566 | .flags = IORESOURCE_MEM, |
567 | }, | 567 | }, |
568 | [1] = { | 568 | [1] = { |
569 | .start = AT91SAM9260_ID_SPI1, | 569 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, |
570 | .end = AT91SAM9260_ID_SPI1, | 570 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1, |
571 | .flags = IORESOURCE_IRQ, | 571 | .flags = IORESOURCE_IRQ, |
572 | }, | 572 | }, |
573 | }; | 573 | }; |
@@ -652,18 +652,18 @@ static struct resource tcb0_resources[] = { | |||
652 | .flags = IORESOURCE_MEM, | 652 | .flags = IORESOURCE_MEM, |
653 | }, | 653 | }, |
654 | [1] = { | 654 | [1] = { |
655 | .start = AT91SAM9260_ID_TC0, | 655 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, |
656 | .end = AT91SAM9260_ID_TC0, | 656 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0, |
657 | .flags = IORESOURCE_IRQ, | 657 | .flags = IORESOURCE_IRQ, |
658 | }, | 658 | }, |
659 | [2] = { | 659 | [2] = { |
660 | .start = AT91SAM9260_ID_TC1, | 660 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, |
661 | .end = AT91SAM9260_ID_TC1, | 661 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1, |
662 | .flags = IORESOURCE_IRQ, | 662 | .flags = IORESOURCE_IRQ, |
663 | }, | 663 | }, |
664 | [3] = { | 664 | [3] = { |
665 | .start = AT91SAM9260_ID_TC2, | 665 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, |
666 | .end = AT91SAM9260_ID_TC2, | 666 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2, |
667 | .flags = IORESOURCE_IRQ, | 667 | .flags = IORESOURCE_IRQ, |
668 | }, | 668 | }, |
669 | }; | 669 | }; |
@@ -682,18 +682,18 @@ static struct resource tcb1_resources[] = { | |||
682 | .flags = IORESOURCE_MEM, | 682 | .flags = IORESOURCE_MEM, |
683 | }, | 683 | }, |
684 | [1] = { | 684 | [1] = { |
685 | .start = AT91SAM9260_ID_TC3, | 685 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, |
686 | .end = AT91SAM9260_ID_TC3, | 686 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3, |
687 | .flags = IORESOURCE_IRQ, | 687 | .flags = IORESOURCE_IRQ, |
688 | }, | 688 | }, |
689 | [2] = { | 689 | [2] = { |
690 | .start = AT91SAM9260_ID_TC4, | 690 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, |
691 | .end = AT91SAM9260_ID_TC4, | 691 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4, |
692 | .flags = IORESOURCE_IRQ, | 692 | .flags = IORESOURCE_IRQ, |
693 | }, | 693 | }, |
694 | [3] = { | 694 | [3] = { |
695 | .start = AT91SAM9260_ID_TC5, | 695 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, |
696 | .end = AT91SAM9260_ID_TC5, | 696 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5, |
697 | .flags = IORESOURCE_IRQ, | 697 | .flags = IORESOURCE_IRQ, |
698 | }, | 698 | }, |
699 | }; | 699 | }; |
@@ -807,8 +807,8 @@ static struct resource ssc_resources[] = { | |||
807 | .flags = IORESOURCE_MEM, | 807 | .flags = IORESOURCE_MEM, |
808 | }, | 808 | }, |
809 | [1] = { | 809 | [1] = { |
810 | .start = AT91SAM9260_ID_SSC, | 810 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, |
811 | .end = AT91SAM9260_ID_SSC, | 811 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC, |
812 | .flags = IORESOURCE_IRQ, | 812 | .flags = IORESOURCE_IRQ, |
813 | }, | 813 | }, |
814 | }; | 814 | }; |
@@ -882,8 +882,8 @@ static struct resource dbgu_resources[] = { | |||
882 | .flags = IORESOURCE_MEM, | 882 | .flags = IORESOURCE_MEM, |
883 | }, | 883 | }, |
884 | [1] = { | 884 | [1] = { |
885 | .start = AT91_ID_SYS, | 885 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
886 | .end = AT91_ID_SYS, | 886 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
887 | .flags = IORESOURCE_IRQ, | 887 | .flags = IORESOURCE_IRQ, |
888 | }, | 888 | }, |
889 | }; | 889 | }; |
@@ -920,8 +920,8 @@ static struct resource uart0_resources[] = { | |||
920 | .flags = IORESOURCE_MEM, | 920 | .flags = IORESOURCE_MEM, |
921 | }, | 921 | }, |
922 | [1] = { | 922 | [1] = { |
923 | .start = AT91SAM9260_ID_US0, | 923 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, |
924 | .end = AT91SAM9260_ID_US0, | 924 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0, |
925 | .flags = IORESOURCE_IRQ, | 925 | .flags = IORESOURCE_IRQ, |
926 | }, | 926 | }, |
927 | }; | 927 | }; |
@@ -971,8 +971,8 @@ static struct resource uart1_resources[] = { | |||
971 | .flags = IORESOURCE_MEM, | 971 | .flags = IORESOURCE_MEM, |
972 | }, | 972 | }, |
973 | [1] = { | 973 | [1] = { |
974 | .start = AT91SAM9260_ID_US1, | 974 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, |
975 | .end = AT91SAM9260_ID_US1, | 975 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1, |
976 | .flags = IORESOURCE_IRQ, | 976 | .flags = IORESOURCE_IRQ, |
977 | }, | 977 | }, |
978 | }; | 978 | }; |
@@ -1014,8 +1014,8 @@ static struct resource uart2_resources[] = { | |||
1014 | .flags = IORESOURCE_MEM, | 1014 | .flags = IORESOURCE_MEM, |
1015 | }, | 1015 | }, |
1016 | [1] = { | 1016 | [1] = { |
1017 | .start = AT91SAM9260_ID_US2, | 1017 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, |
1018 | .end = AT91SAM9260_ID_US2, | 1018 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2, |
1019 | .flags = IORESOURCE_IRQ, | 1019 | .flags = IORESOURCE_IRQ, |
1020 | }, | 1020 | }, |
1021 | }; | 1021 | }; |
@@ -1057,8 +1057,8 @@ static struct resource uart3_resources[] = { | |||
1057 | .flags = IORESOURCE_MEM, | 1057 | .flags = IORESOURCE_MEM, |
1058 | }, | 1058 | }, |
1059 | [1] = { | 1059 | [1] = { |
1060 | .start = AT91SAM9260_ID_US3, | 1060 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, |
1061 | .end = AT91SAM9260_ID_US3, | 1061 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3, |
1062 | .flags = IORESOURCE_IRQ, | 1062 | .flags = IORESOURCE_IRQ, |
1063 | }, | 1063 | }, |
1064 | }; | 1064 | }; |
@@ -1100,8 +1100,8 @@ static struct resource uart4_resources[] = { | |||
1100 | .flags = IORESOURCE_MEM, | 1100 | .flags = IORESOURCE_MEM, |
1101 | }, | 1101 | }, |
1102 | [1] = { | 1102 | [1] = { |
1103 | .start = AT91SAM9260_ID_US4, | 1103 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, |
1104 | .end = AT91SAM9260_ID_US4, | 1104 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4, |
1105 | .flags = IORESOURCE_IRQ, | 1105 | .flags = IORESOURCE_IRQ, |
1106 | }, | 1106 | }, |
1107 | }; | 1107 | }; |
@@ -1138,8 +1138,8 @@ static struct resource uart5_resources[] = { | |||
1138 | .flags = IORESOURCE_MEM, | 1138 | .flags = IORESOURCE_MEM, |
1139 | }, | 1139 | }, |
1140 | [1] = { | 1140 | [1] = { |
1141 | .start = AT91SAM9260_ID_US5, | 1141 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, |
1142 | .end = AT91SAM9260_ID_US5, | 1142 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5, |
1143 | .flags = IORESOURCE_IRQ, | 1143 | .flags = IORESOURCE_IRQ, |
1144 | }, | 1144 | }, |
1145 | }; | 1145 | }; |
@@ -1357,8 +1357,8 @@ static struct resource adc_resources[] = { | |||
1357 | .flags = IORESOURCE_MEM, | 1357 | .flags = IORESOURCE_MEM, |
1358 | }, | 1358 | }, |
1359 | [1] = { | 1359 | [1] = { |
1360 | .start = AT91SAM9260_ID_ADC, | 1360 | .start = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC, |
1361 | .end = AT91SAM9260_ID_ADC, | 1361 | .end = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC, |
1362 | .flags = IORESOURCE_IRQ, | 1362 | .flags = IORESOURCE_IRQ, |
1363 | }, | 1363 | }, |
1364 | }; | 1364 | }; |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index c77d503d09d1..f40762c5fede 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
20 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
21 | #include <mach/at91sam9261.h> | 21 | #include <mach/at91sam9261.h> |
22 | #include <mach/at91_aic.h> | ||
22 | #include <mach/at91_pmc.h> | 23 | #include <mach/at91_pmc.h> |
23 | #include <mach/at91_rstc.h> | 24 | #include <mach/at91_rstc.h> |
24 | 25 | ||
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c index 9295e90b08ff..8df5c1bdff92 100644 --- a/arch/arm/mach-at91/at91sam9261_devices.c +++ b/arch/arm/mach-at91/at91sam9261_devices.c | |||
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = { | |||
45 | .flags = IORESOURCE_MEM, | 45 | .flags = IORESOURCE_MEM, |
46 | }, | 46 | }, |
47 | [1] = { | 47 | [1] = { |
48 | .start = AT91SAM9261_ID_UHP, | 48 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, |
49 | .end = AT91SAM9261_ID_UHP, | 49 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP, |
50 | .flags = IORESOURCE_IRQ, | 50 | .flags = IORESOURCE_IRQ, |
51 | }, | 51 | }, |
52 | }; | 52 | }; |
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = { | |||
98 | .flags = IORESOURCE_MEM, | 98 | .flags = IORESOURCE_MEM, |
99 | }, | 99 | }, |
100 | [1] = { | 100 | [1] = { |
101 | .start = AT91SAM9261_ID_UDP, | 101 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, |
102 | .end = AT91SAM9261_ID_UDP, | 102 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP, |
103 | .flags = IORESOURCE_IRQ, | 103 | .flags = IORESOURCE_IRQ, |
104 | }, | 104 | }, |
105 | }; | 105 | }; |
@@ -148,8 +148,8 @@ static struct resource mmc_resources[] = { | |||
148 | .flags = IORESOURCE_MEM, | 148 | .flags = IORESOURCE_MEM, |
149 | }, | 149 | }, |
150 | [1] = { | 150 | [1] = { |
151 | .start = AT91SAM9261_ID_MCI, | 151 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, |
152 | .end = AT91SAM9261_ID_MCI, | 152 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI, |
153 | .flags = IORESOURCE_IRQ, | 153 | .flags = IORESOURCE_IRQ, |
154 | }, | 154 | }, |
155 | }; | 155 | }; |
@@ -310,8 +310,8 @@ static struct resource twi_resources[] = { | |||
310 | .flags = IORESOURCE_MEM, | 310 | .flags = IORESOURCE_MEM, |
311 | }, | 311 | }, |
312 | [1] = { | 312 | [1] = { |
313 | .start = AT91SAM9261_ID_TWI, | 313 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, |
314 | .end = AT91SAM9261_ID_TWI, | 314 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI, |
315 | .flags = IORESOURCE_IRQ, | 315 | .flags = IORESOURCE_IRQ, |
316 | }, | 316 | }, |
317 | }; | 317 | }; |
@@ -354,8 +354,8 @@ static struct resource spi0_resources[] = { | |||
354 | .flags = IORESOURCE_MEM, | 354 | .flags = IORESOURCE_MEM, |
355 | }, | 355 | }, |
356 | [1] = { | 356 | [1] = { |
357 | .start = AT91SAM9261_ID_SPI0, | 357 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, |
358 | .end = AT91SAM9261_ID_SPI0, | 358 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0, |
359 | .flags = IORESOURCE_IRQ, | 359 | .flags = IORESOURCE_IRQ, |
360 | }, | 360 | }, |
361 | }; | 361 | }; |
@@ -380,8 +380,8 @@ static struct resource spi1_resources[] = { | |||
380 | .flags = IORESOURCE_MEM, | 380 | .flags = IORESOURCE_MEM, |
381 | }, | 381 | }, |
382 | [1] = { | 382 | [1] = { |
383 | .start = AT91SAM9261_ID_SPI1, | 383 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, |
384 | .end = AT91SAM9261_ID_SPI1, | 384 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1, |
385 | .flags = IORESOURCE_IRQ, | 385 | .flags = IORESOURCE_IRQ, |
386 | }, | 386 | }, |
387 | }; | 387 | }; |
@@ -468,8 +468,8 @@ static struct resource lcdc_resources[] = { | |||
468 | .flags = IORESOURCE_MEM, | 468 | .flags = IORESOURCE_MEM, |
469 | }, | 469 | }, |
470 | [1] = { | 470 | [1] = { |
471 | .start = AT91SAM9261_ID_LCDC, | 471 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, |
472 | .end = AT91SAM9261_ID_LCDC, | 472 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC, |
473 | .flags = IORESOURCE_IRQ, | 473 | .flags = IORESOURCE_IRQ, |
474 | }, | 474 | }, |
475 | #if defined(CONFIG_FB_INTSRAM) | 475 | #if defined(CONFIG_FB_INTSRAM) |
@@ -566,18 +566,18 @@ static struct resource tcb_resources[] = { | |||
566 | .flags = IORESOURCE_MEM, | 566 | .flags = IORESOURCE_MEM, |
567 | }, | 567 | }, |
568 | [1] = { | 568 | [1] = { |
569 | .start = AT91SAM9261_ID_TC0, | 569 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, |
570 | .end = AT91SAM9261_ID_TC0, | 570 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0, |
571 | .flags = IORESOURCE_IRQ, | 571 | .flags = IORESOURCE_IRQ, |
572 | }, | 572 | }, |
573 | [2] = { | 573 | [2] = { |
574 | .start = AT91SAM9261_ID_TC1, | 574 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, |
575 | .end = AT91SAM9261_ID_TC1, | 575 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1, |
576 | .flags = IORESOURCE_IRQ, | 576 | .flags = IORESOURCE_IRQ, |
577 | }, | 577 | }, |
578 | [3] = { | 578 | [3] = { |
579 | .start = AT91SAM9261_ID_TC2, | 579 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, |
580 | .end = AT91SAM9261_ID_TC2, | 580 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2, |
581 | .flags = IORESOURCE_IRQ, | 581 | .flags = IORESOURCE_IRQ, |
582 | }, | 582 | }, |
583 | }; | 583 | }; |
@@ -689,8 +689,8 @@ static struct resource ssc0_resources[] = { | |||
689 | .flags = IORESOURCE_MEM, | 689 | .flags = IORESOURCE_MEM, |
690 | }, | 690 | }, |
691 | [1] = { | 691 | [1] = { |
692 | .start = AT91SAM9261_ID_SSC0, | 692 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, |
693 | .end = AT91SAM9261_ID_SSC0, | 693 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0, |
694 | .flags = IORESOURCE_IRQ, | 694 | .flags = IORESOURCE_IRQ, |
695 | }, | 695 | }, |
696 | }; | 696 | }; |
@@ -731,8 +731,8 @@ static struct resource ssc1_resources[] = { | |||
731 | .flags = IORESOURCE_MEM, | 731 | .flags = IORESOURCE_MEM, |
732 | }, | 732 | }, |
733 | [1] = { | 733 | [1] = { |
734 | .start = AT91SAM9261_ID_SSC1, | 734 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, |
735 | .end = AT91SAM9261_ID_SSC1, | 735 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1, |
736 | .flags = IORESOURCE_IRQ, | 736 | .flags = IORESOURCE_IRQ, |
737 | }, | 737 | }, |
738 | }; | 738 | }; |
@@ -773,8 +773,8 @@ static struct resource ssc2_resources[] = { | |||
773 | .flags = IORESOURCE_MEM, | 773 | .flags = IORESOURCE_MEM, |
774 | }, | 774 | }, |
775 | [1] = { | 775 | [1] = { |
776 | .start = AT91SAM9261_ID_SSC2, | 776 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, |
777 | .end = AT91SAM9261_ID_SSC2, | 777 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2, |
778 | .flags = IORESOURCE_IRQ, | 778 | .flags = IORESOURCE_IRQ, |
779 | }, | 779 | }, |
780 | }; | 780 | }; |
@@ -857,8 +857,8 @@ static struct resource dbgu_resources[] = { | |||
857 | .flags = IORESOURCE_MEM, | 857 | .flags = IORESOURCE_MEM, |
858 | }, | 858 | }, |
859 | [1] = { | 859 | [1] = { |
860 | .start = AT91_ID_SYS, | 860 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
861 | .end = AT91_ID_SYS, | 861 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
862 | .flags = IORESOURCE_IRQ, | 862 | .flags = IORESOURCE_IRQ, |
863 | }, | 863 | }, |
864 | }; | 864 | }; |
@@ -895,8 +895,8 @@ static struct resource uart0_resources[] = { | |||
895 | .flags = IORESOURCE_MEM, | 895 | .flags = IORESOURCE_MEM, |
896 | }, | 896 | }, |
897 | [1] = { | 897 | [1] = { |
898 | .start = AT91SAM9261_ID_US0, | 898 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, |
899 | .end = AT91SAM9261_ID_US0, | 899 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0, |
900 | .flags = IORESOURCE_IRQ, | 900 | .flags = IORESOURCE_IRQ, |
901 | }, | 901 | }, |
902 | }; | 902 | }; |
@@ -938,8 +938,8 @@ static struct resource uart1_resources[] = { | |||
938 | .flags = IORESOURCE_MEM, | 938 | .flags = IORESOURCE_MEM, |
939 | }, | 939 | }, |
940 | [1] = { | 940 | [1] = { |
941 | .start = AT91SAM9261_ID_US1, | 941 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, |
942 | .end = AT91SAM9261_ID_US1, | 942 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1, |
943 | .flags = IORESOURCE_IRQ, | 943 | .flags = IORESOURCE_IRQ, |
944 | }, | 944 | }, |
945 | }; | 945 | }; |
@@ -981,8 +981,8 @@ static struct resource uart2_resources[] = { | |||
981 | .flags = IORESOURCE_MEM, | 981 | .flags = IORESOURCE_MEM, |
982 | }, | 982 | }, |
983 | [1] = { | 983 | [1] = { |
984 | .start = AT91SAM9261_ID_US2, | 984 | .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, |
985 | .end = AT91SAM9261_ID_US2, | 985 | .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2, |
986 | .flags = IORESOURCE_IRQ, | 986 | .flags = IORESOURCE_IRQ, |
987 | }, | 987 | }, |
988 | }; | 988 | }; |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index ed91c7e9f7c2..84b38105231e 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
20 | #include <mach/at91sam9263.h> | 20 | #include <mach/at91sam9263.h> |
21 | #include <mach/at91_aic.h> | ||
21 | #include <mach/at91_pmc.h> | 22 | #include <mach/at91_pmc.h> |
22 | #include <mach/at91_rstc.h> | 23 | #include <mach/at91_rstc.h> |
23 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 175e0009eaa9..eb6bbf86fb9f 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
@@ -44,8 +44,8 @@ static struct resource usbh_resources[] = { | |||
44 | .flags = IORESOURCE_MEM, | 44 | .flags = IORESOURCE_MEM, |
45 | }, | 45 | }, |
46 | [1] = { | 46 | [1] = { |
47 | .start = AT91SAM9263_ID_UHP, | 47 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, |
48 | .end = AT91SAM9263_ID_UHP, | 48 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP, |
49 | .flags = IORESOURCE_IRQ, | 49 | .flags = IORESOURCE_IRQ, |
50 | }, | 50 | }, |
51 | }; | 51 | }; |
@@ -104,8 +104,8 @@ static struct resource udc_resources[] = { | |||
104 | .flags = IORESOURCE_MEM, | 104 | .flags = IORESOURCE_MEM, |
105 | }, | 105 | }, |
106 | [1] = { | 106 | [1] = { |
107 | .start = AT91SAM9263_ID_UDP, | 107 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, |
108 | .end = AT91SAM9263_ID_UDP, | 108 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP, |
109 | .flags = IORESOURCE_IRQ, | 109 | .flags = IORESOURCE_IRQ, |
110 | }, | 110 | }, |
111 | }; | 111 | }; |
@@ -155,8 +155,8 @@ static struct resource eth_resources[] = { | |||
155 | .flags = IORESOURCE_MEM, | 155 | .flags = IORESOURCE_MEM, |
156 | }, | 156 | }, |
157 | [1] = { | 157 | [1] = { |
158 | .start = AT91SAM9263_ID_EMAC, | 158 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, |
159 | .end = AT91SAM9263_ID_EMAC, | 159 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC, |
160 | .flags = IORESOURCE_IRQ, | 160 | .flags = IORESOURCE_IRQ, |
161 | }, | 161 | }, |
162 | }; | 162 | }; |
@@ -229,8 +229,8 @@ static struct resource mmc0_resources[] = { | |||
229 | .flags = IORESOURCE_MEM, | 229 | .flags = IORESOURCE_MEM, |
230 | }, | 230 | }, |
231 | [1] = { | 231 | [1] = { |
232 | .start = AT91SAM9263_ID_MCI0, | 232 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, |
233 | .end = AT91SAM9263_ID_MCI0, | 233 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0, |
234 | .flags = IORESOURCE_IRQ, | 234 | .flags = IORESOURCE_IRQ, |
235 | }, | 235 | }, |
236 | }; | 236 | }; |
@@ -254,8 +254,8 @@ static struct resource mmc1_resources[] = { | |||
254 | .flags = IORESOURCE_MEM, | 254 | .flags = IORESOURCE_MEM, |
255 | }, | 255 | }, |
256 | [1] = { | 256 | [1] = { |
257 | .start = AT91SAM9263_ID_MCI1, | 257 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, |
258 | .end = AT91SAM9263_ID_MCI1, | 258 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1, |
259 | .flags = IORESOURCE_IRQ, | 259 | .flags = IORESOURCE_IRQ, |
260 | }, | 260 | }, |
261 | }; | 261 | }; |
@@ -567,8 +567,8 @@ static struct resource twi_resources[] = { | |||
567 | .flags = IORESOURCE_MEM, | 567 | .flags = IORESOURCE_MEM, |
568 | }, | 568 | }, |
569 | [1] = { | 569 | [1] = { |
570 | .start = AT91SAM9263_ID_TWI, | 570 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, |
571 | .end = AT91SAM9263_ID_TWI, | 571 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI, |
572 | .flags = IORESOURCE_IRQ, | 572 | .flags = IORESOURCE_IRQ, |
573 | }, | 573 | }, |
574 | }; | 574 | }; |
@@ -611,8 +611,8 @@ static struct resource spi0_resources[] = { | |||
611 | .flags = IORESOURCE_MEM, | 611 | .flags = IORESOURCE_MEM, |
612 | }, | 612 | }, |
613 | [1] = { | 613 | [1] = { |
614 | .start = AT91SAM9263_ID_SPI0, | 614 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, |
615 | .end = AT91SAM9263_ID_SPI0, | 615 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0, |
616 | .flags = IORESOURCE_IRQ, | 616 | .flags = IORESOURCE_IRQ, |
617 | }, | 617 | }, |
618 | }; | 618 | }; |
@@ -637,8 +637,8 @@ static struct resource spi1_resources[] = { | |||
637 | .flags = IORESOURCE_MEM, | 637 | .flags = IORESOURCE_MEM, |
638 | }, | 638 | }, |
639 | [1] = { | 639 | [1] = { |
640 | .start = AT91SAM9263_ID_SPI1, | 640 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, |
641 | .end = AT91SAM9263_ID_SPI1, | 641 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1, |
642 | .flags = IORESOURCE_IRQ, | 642 | .flags = IORESOURCE_IRQ, |
643 | }, | 643 | }, |
644 | }; | 644 | }; |
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = { | |||
725 | .flags = IORESOURCE_MEM, | 725 | .flags = IORESOURCE_MEM, |
726 | }, | 726 | }, |
727 | [1] = { | 727 | [1] = { |
728 | .start = AT91SAM9263_ID_AC97C, | 728 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, |
729 | .end = AT91SAM9263_ID_AC97C, | 729 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C, |
730 | .flags = IORESOURCE_IRQ, | 730 | .flags = IORESOURCE_IRQ, |
731 | }, | 731 | }, |
732 | }; | 732 | }; |
@@ -776,8 +776,8 @@ static struct resource can_resources[] = { | |||
776 | .flags = IORESOURCE_MEM, | 776 | .flags = IORESOURCE_MEM, |
777 | }, | 777 | }, |
778 | [1] = { | 778 | [1] = { |
779 | .start = AT91SAM9263_ID_CAN, | 779 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, |
780 | .end = AT91SAM9263_ID_CAN, | 780 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN, |
781 | .flags = IORESOURCE_IRQ, | 781 | .flags = IORESOURCE_IRQ, |
782 | }, | 782 | }, |
783 | }; | 783 | }; |
@@ -816,8 +816,8 @@ static struct resource lcdc_resources[] = { | |||
816 | .flags = IORESOURCE_MEM, | 816 | .flags = IORESOURCE_MEM, |
817 | }, | 817 | }, |
818 | [1] = { | 818 | [1] = { |
819 | .start = AT91SAM9263_ID_LCDC, | 819 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, |
820 | .end = AT91SAM9263_ID_LCDC, | 820 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC, |
821 | .flags = IORESOURCE_IRQ, | 821 | .flags = IORESOURCE_IRQ, |
822 | }, | 822 | }, |
823 | }; | 823 | }; |
@@ -883,8 +883,8 @@ struct resource isi_resources[] = { | |||
883 | .flags = IORESOURCE_MEM, | 883 | .flags = IORESOURCE_MEM, |
884 | }, | 884 | }, |
885 | [1] = { | 885 | [1] = { |
886 | .start = AT91SAM9263_ID_ISI, | 886 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, |
887 | .end = AT91SAM9263_ID_ISI, | 887 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI, |
888 | .flags = IORESOURCE_IRQ, | 888 | .flags = IORESOURCE_IRQ, |
889 | }, | 889 | }, |
890 | }; | 890 | }; |
@@ -940,8 +940,8 @@ static struct resource tcb_resources[] = { | |||
940 | .flags = IORESOURCE_MEM, | 940 | .flags = IORESOURCE_MEM, |
941 | }, | 941 | }, |
942 | [1] = { | 942 | [1] = { |
943 | .start = AT91SAM9263_ID_TCB, | 943 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, |
944 | .end = AT91SAM9263_ID_TCB, | 944 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB, |
945 | .flags = IORESOURCE_IRQ, | 945 | .flags = IORESOURCE_IRQ, |
946 | }, | 946 | }, |
947 | }; | 947 | }; |
@@ -1108,8 +1108,8 @@ static struct resource pwm_resources[] = { | |||
1108 | .flags = IORESOURCE_MEM, | 1108 | .flags = IORESOURCE_MEM, |
1109 | }, | 1109 | }, |
1110 | [1] = { | 1110 | [1] = { |
1111 | .start = AT91SAM9263_ID_PWMC, | 1111 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, |
1112 | .end = AT91SAM9263_ID_PWMC, | 1112 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC, |
1113 | .flags = IORESOURCE_IRQ, | 1113 | .flags = IORESOURCE_IRQ, |
1114 | }, | 1114 | }, |
1115 | }; | 1115 | }; |
@@ -1161,8 +1161,8 @@ static struct resource ssc0_resources[] = { | |||
1161 | .flags = IORESOURCE_MEM, | 1161 | .flags = IORESOURCE_MEM, |
1162 | }, | 1162 | }, |
1163 | [1] = { | 1163 | [1] = { |
1164 | .start = AT91SAM9263_ID_SSC0, | 1164 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, |
1165 | .end = AT91SAM9263_ID_SSC0, | 1165 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0, |
1166 | .flags = IORESOURCE_IRQ, | 1166 | .flags = IORESOURCE_IRQ, |
1167 | }, | 1167 | }, |
1168 | }; | 1168 | }; |
@@ -1203,8 +1203,8 @@ static struct resource ssc1_resources[] = { | |||
1203 | .flags = IORESOURCE_MEM, | 1203 | .flags = IORESOURCE_MEM, |
1204 | }, | 1204 | }, |
1205 | [1] = { | 1205 | [1] = { |
1206 | .start = AT91SAM9263_ID_SSC1, | 1206 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, |
1207 | .end = AT91SAM9263_ID_SSC1, | 1207 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1, |
1208 | .flags = IORESOURCE_IRQ, | 1208 | .flags = IORESOURCE_IRQ, |
1209 | }, | 1209 | }, |
1210 | }; | 1210 | }; |
@@ -1284,8 +1284,8 @@ static struct resource dbgu_resources[] = { | |||
1284 | .flags = IORESOURCE_MEM, | 1284 | .flags = IORESOURCE_MEM, |
1285 | }, | 1285 | }, |
1286 | [1] = { | 1286 | [1] = { |
1287 | .start = AT91_ID_SYS, | 1287 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
1288 | .end = AT91_ID_SYS, | 1288 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
1289 | .flags = IORESOURCE_IRQ, | 1289 | .flags = IORESOURCE_IRQ, |
1290 | }, | 1290 | }, |
1291 | }; | 1291 | }; |
@@ -1322,8 +1322,8 @@ static struct resource uart0_resources[] = { | |||
1322 | .flags = IORESOURCE_MEM, | 1322 | .flags = IORESOURCE_MEM, |
1323 | }, | 1323 | }, |
1324 | [1] = { | 1324 | [1] = { |
1325 | .start = AT91SAM9263_ID_US0, | 1325 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, |
1326 | .end = AT91SAM9263_ID_US0, | 1326 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US0, |
1327 | .flags = IORESOURCE_IRQ, | 1327 | .flags = IORESOURCE_IRQ, |
1328 | }, | 1328 | }, |
1329 | }; | 1329 | }; |
@@ -1365,8 +1365,8 @@ static struct resource uart1_resources[] = { | |||
1365 | .flags = IORESOURCE_MEM, | 1365 | .flags = IORESOURCE_MEM, |
1366 | }, | 1366 | }, |
1367 | [1] = { | 1367 | [1] = { |
1368 | .start = AT91SAM9263_ID_US1, | 1368 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, |
1369 | .end = AT91SAM9263_ID_US1, | 1369 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US1, |
1370 | .flags = IORESOURCE_IRQ, | 1370 | .flags = IORESOURCE_IRQ, |
1371 | }, | 1371 | }, |
1372 | }; | 1372 | }; |
@@ -1408,8 +1408,8 @@ static struct resource uart2_resources[] = { | |||
1408 | .flags = IORESOURCE_MEM, | 1408 | .flags = IORESOURCE_MEM, |
1409 | }, | 1409 | }, |
1410 | [1] = { | 1410 | [1] = { |
1411 | .start = AT91SAM9263_ID_US2, | 1411 | .start = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, |
1412 | .end = AT91SAM9263_ID_US2, | 1412 | .end = NR_IRQS_LEGACY + AT91SAM9263_ID_US2, |
1413 | .flags = IORESOURCE_IRQ, | 1413 | .flags = IORESOURCE_IRQ, |
1414 | }, | 1414 | }, |
1415 | }; | 1415 | }; |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index a94758b42737..ffc0957d7623 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
@@ -137,7 +137,7 @@ static struct irqaction at91sam926x_pit_irq = { | |||
137 | .name = "at91_tick", | 137 | .name = "at91_tick", |
138 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 138 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
139 | .handler = at91sam926x_pit_interrupt, | 139 | .handler = at91sam926x_pit_interrupt, |
140 | .irq = AT91_ID_SYS, | 140 | .irq = NR_IRQS_LEGACY + AT91_ID_SYS, |
141 | }; | 141 | }; |
142 | 142 | ||
143 | static void at91sam926x_pit_reset(void) | 143 | static void at91sam926x_pit_reset(void) |
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 4792682d52b9..977127368a7d 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
19 | #include <asm/system_misc.h> | 19 | #include <asm/system_misc.h> |
20 | #include <mach/at91sam9g45.h> | 20 | #include <mach/at91sam9g45.h> |
21 | #include <mach/at91_aic.h> | ||
21 | #include <mach/at91_pmc.h> | 22 | #include <mach/at91_pmc.h> |
22 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
23 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c index 933fc9afe7d0..40fb79df2de0 100644 --- a/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
@@ -53,8 +53,8 @@ static struct resource hdmac_resources[] = { | |||
53 | .flags = IORESOURCE_MEM, | 53 | .flags = IORESOURCE_MEM, |
54 | }, | 54 | }, |
55 | [1] = { | 55 | [1] = { |
56 | .start = AT91SAM9G45_ID_DMA, | 56 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, |
57 | .end = AT91SAM9G45_ID_DMA, | 57 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA, |
58 | .flags = IORESOURCE_IRQ, | 58 | .flags = IORESOURCE_IRQ, |
59 | }, | 59 | }, |
60 | }; | 60 | }; |
@@ -94,8 +94,8 @@ static struct resource usbh_ohci_resources[] = { | |||
94 | .flags = IORESOURCE_MEM, | 94 | .flags = IORESOURCE_MEM, |
95 | }, | 95 | }, |
96 | [1] = { | 96 | [1] = { |
97 | .start = AT91SAM9G45_ID_UHPHS, | 97 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
98 | .end = AT91SAM9G45_ID_UHPHS, | 98 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
99 | .flags = IORESOURCE_IRQ, | 99 | .flags = IORESOURCE_IRQ, |
100 | }, | 100 | }, |
101 | }; | 101 | }; |
@@ -156,8 +156,8 @@ static struct resource usbh_ehci_resources[] = { | |||
156 | .flags = IORESOURCE_MEM, | 156 | .flags = IORESOURCE_MEM, |
157 | }, | 157 | }, |
158 | [1] = { | 158 | [1] = { |
159 | .start = AT91SAM9G45_ID_UHPHS, | 159 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
160 | .end = AT91SAM9G45_ID_UHPHS, | 160 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS, |
161 | .flags = IORESOURCE_IRQ, | 161 | .flags = IORESOURCE_IRQ, |
162 | }, | 162 | }, |
163 | }; | 163 | }; |
@@ -213,8 +213,8 @@ static struct resource usba_udc_resources[] = { | |||
213 | .flags = IORESOURCE_MEM, | 213 | .flags = IORESOURCE_MEM, |
214 | }, | 214 | }, |
215 | [2] = { | 215 | [2] = { |
216 | .start = AT91SAM9G45_ID_UDPHS, | 216 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, |
217 | .end = AT91SAM9G45_ID_UDPHS, | 217 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS, |
218 | .flags = IORESOURCE_IRQ, | 218 | .flags = IORESOURCE_IRQ, |
219 | }, | 219 | }, |
220 | }; | 220 | }; |
@@ -296,8 +296,8 @@ static struct resource eth_resources[] = { | |||
296 | .flags = IORESOURCE_MEM, | 296 | .flags = IORESOURCE_MEM, |
297 | }, | 297 | }, |
298 | [1] = { | 298 | [1] = { |
299 | .start = AT91SAM9G45_ID_EMAC, | 299 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, |
300 | .end = AT91SAM9G45_ID_EMAC, | 300 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC, |
301 | .flags = IORESOURCE_IRQ, | 301 | .flags = IORESOURCE_IRQ, |
302 | }, | 302 | }, |
303 | }; | 303 | }; |
@@ -370,8 +370,8 @@ static struct resource mmc0_resources[] = { | |||
370 | .flags = IORESOURCE_MEM, | 370 | .flags = IORESOURCE_MEM, |
371 | }, | 371 | }, |
372 | [1] = { | 372 | [1] = { |
373 | .start = AT91SAM9G45_ID_MCI0, | 373 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, |
374 | .end = AT91SAM9G45_ID_MCI0, | 374 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0, |
375 | .flags = IORESOURCE_IRQ, | 375 | .flags = IORESOURCE_IRQ, |
376 | }, | 376 | }, |
377 | }; | 377 | }; |
@@ -395,8 +395,8 @@ static struct resource mmc1_resources[] = { | |||
395 | .flags = IORESOURCE_MEM, | 395 | .flags = IORESOURCE_MEM, |
396 | }, | 396 | }, |
397 | [1] = { | 397 | [1] = { |
398 | .start = AT91SAM9G45_ID_MCI1, | 398 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, |
399 | .end = AT91SAM9G45_ID_MCI1, | 399 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1, |
400 | .flags = IORESOURCE_IRQ, | 400 | .flags = IORESOURCE_IRQ, |
401 | }, | 401 | }, |
402 | }; | 402 | }; |
@@ -645,8 +645,8 @@ static struct resource twi0_resources[] = { | |||
645 | .flags = IORESOURCE_MEM, | 645 | .flags = IORESOURCE_MEM, |
646 | }, | 646 | }, |
647 | [1] = { | 647 | [1] = { |
648 | .start = AT91SAM9G45_ID_TWI0, | 648 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, |
649 | .end = AT91SAM9G45_ID_TWI0, | 649 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0, |
650 | .flags = IORESOURCE_IRQ, | 650 | .flags = IORESOURCE_IRQ, |
651 | }, | 651 | }, |
652 | }; | 652 | }; |
@@ -665,8 +665,8 @@ static struct resource twi1_resources[] = { | |||
665 | .flags = IORESOURCE_MEM, | 665 | .flags = IORESOURCE_MEM, |
666 | }, | 666 | }, |
667 | [1] = { | 667 | [1] = { |
668 | .start = AT91SAM9G45_ID_TWI1, | 668 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, |
669 | .end = AT91SAM9G45_ID_TWI1, | 669 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1, |
670 | .flags = IORESOURCE_IRQ, | 670 | .flags = IORESOURCE_IRQ, |
671 | }, | 671 | }, |
672 | }; | 672 | }; |
@@ -720,8 +720,8 @@ static struct resource spi0_resources[] = { | |||
720 | .flags = IORESOURCE_MEM, | 720 | .flags = IORESOURCE_MEM, |
721 | }, | 721 | }, |
722 | [1] = { | 722 | [1] = { |
723 | .start = AT91SAM9G45_ID_SPI0, | 723 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, |
724 | .end = AT91SAM9G45_ID_SPI0, | 724 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0, |
725 | .flags = IORESOURCE_IRQ, | 725 | .flags = IORESOURCE_IRQ, |
726 | }, | 726 | }, |
727 | }; | 727 | }; |
@@ -746,8 +746,8 @@ static struct resource spi1_resources[] = { | |||
746 | .flags = IORESOURCE_MEM, | 746 | .flags = IORESOURCE_MEM, |
747 | }, | 747 | }, |
748 | [1] = { | 748 | [1] = { |
749 | .start = AT91SAM9G45_ID_SPI1, | 749 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, |
750 | .end = AT91SAM9G45_ID_SPI1, | 750 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1, |
751 | .flags = IORESOURCE_IRQ, | 751 | .flags = IORESOURCE_IRQ, |
752 | }, | 752 | }, |
753 | }; | 753 | }; |
@@ -834,8 +834,8 @@ static struct resource ac97_resources[] = { | |||
834 | .flags = IORESOURCE_MEM, | 834 | .flags = IORESOURCE_MEM, |
835 | }, | 835 | }, |
836 | [1] = { | 836 | [1] = { |
837 | .start = AT91SAM9G45_ID_AC97C, | 837 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, |
838 | .end = AT91SAM9G45_ID_AC97C, | 838 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C, |
839 | .flags = IORESOURCE_IRQ, | 839 | .flags = IORESOURCE_IRQ, |
840 | }, | 840 | }, |
841 | }; | 841 | }; |
@@ -887,8 +887,8 @@ struct resource isi_resources[] = { | |||
887 | .flags = IORESOURCE_MEM, | 887 | .flags = IORESOURCE_MEM, |
888 | }, | 888 | }, |
889 | [1] = { | 889 | [1] = { |
890 | .start = AT91SAM9G45_ID_ISI, | 890 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, |
891 | .end = AT91SAM9G45_ID_ISI, | 891 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI, |
892 | .flags = IORESOURCE_IRQ, | 892 | .flags = IORESOURCE_IRQ, |
893 | }, | 893 | }, |
894 | }; | 894 | }; |
@@ -979,8 +979,8 @@ static struct resource lcdc_resources[] = { | |||
979 | .flags = IORESOURCE_MEM, | 979 | .flags = IORESOURCE_MEM, |
980 | }, | 980 | }, |
981 | [1] = { | 981 | [1] = { |
982 | .start = AT91SAM9G45_ID_LCDC, | 982 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, |
983 | .end = AT91SAM9G45_ID_LCDC, | 983 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC, |
984 | .flags = IORESOURCE_IRQ, | 984 | .flags = IORESOURCE_IRQ, |
985 | }, | 985 | }, |
986 | }; | 986 | }; |
@@ -1054,8 +1054,8 @@ static struct resource tcb0_resources[] = { | |||
1054 | .flags = IORESOURCE_MEM, | 1054 | .flags = IORESOURCE_MEM, |
1055 | }, | 1055 | }, |
1056 | [1] = { | 1056 | [1] = { |
1057 | .start = AT91SAM9G45_ID_TCB, | 1057 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
1058 | .end = AT91SAM9G45_ID_TCB, | 1058 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
1059 | .flags = IORESOURCE_IRQ, | 1059 | .flags = IORESOURCE_IRQ, |
1060 | }, | 1060 | }, |
1061 | }; | 1061 | }; |
@@ -1075,8 +1075,8 @@ static struct resource tcb1_resources[] = { | |||
1075 | .flags = IORESOURCE_MEM, | 1075 | .flags = IORESOURCE_MEM, |
1076 | }, | 1076 | }, |
1077 | [1] = { | 1077 | [1] = { |
1078 | .start = AT91SAM9G45_ID_TCB, | 1078 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
1079 | .end = AT91SAM9G45_ID_TCB, | 1079 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB, |
1080 | .flags = IORESOURCE_IRQ, | 1080 | .flags = IORESOURCE_IRQ, |
1081 | }, | 1081 | }, |
1082 | }; | 1082 | }; |
@@ -1110,8 +1110,8 @@ static struct resource rtc_resources[] = { | |||
1110 | .flags = IORESOURCE_MEM, | 1110 | .flags = IORESOURCE_MEM, |
1111 | }, | 1111 | }, |
1112 | [1] = { | 1112 | [1] = { |
1113 | .start = AT91_ID_SYS, | 1113 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
1114 | .end = AT91_ID_SYS, | 1114 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
1115 | .flags = IORESOURCE_IRQ, | 1115 | .flags = IORESOURCE_IRQ, |
1116 | }, | 1116 | }, |
1117 | }; | 1117 | }; |
@@ -1147,8 +1147,8 @@ static struct resource tsadcc_resources[] = { | |||
1147 | .flags = IORESOURCE_MEM, | 1147 | .flags = IORESOURCE_MEM, |
1148 | }, | 1148 | }, |
1149 | [1] = { | 1149 | [1] = { |
1150 | .start = AT91SAM9G45_ID_TSC, | 1150 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
1151 | .end = AT91SAM9G45_ID_TSC, | 1151 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
1152 | .flags = IORESOURCE_IRQ, | 1152 | .flags = IORESOURCE_IRQ, |
1153 | } | 1153 | } |
1154 | }; | 1154 | }; |
@@ -1197,8 +1197,8 @@ static struct resource adc_resources[] = { | |||
1197 | .flags = IORESOURCE_MEM, | 1197 | .flags = IORESOURCE_MEM, |
1198 | }, | 1198 | }, |
1199 | [1] = { | 1199 | [1] = { |
1200 | .start = AT91SAM9G45_ID_TSC, | 1200 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
1201 | .end = AT91SAM9G45_ID_TSC, | 1201 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC, |
1202 | .flags = IORESOURCE_IRQ, | 1202 | .flags = IORESOURCE_IRQ, |
1203 | } | 1203 | } |
1204 | }; | 1204 | }; |
@@ -1400,8 +1400,8 @@ static struct resource pwm_resources[] = { | |||
1400 | .flags = IORESOURCE_MEM, | 1400 | .flags = IORESOURCE_MEM, |
1401 | }, | 1401 | }, |
1402 | [1] = { | 1402 | [1] = { |
1403 | .start = AT91SAM9G45_ID_PWMC, | 1403 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, |
1404 | .end = AT91SAM9G45_ID_PWMC, | 1404 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC, |
1405 | .flags = IORESOURCE_IRQ, | 1405 | .flags = IORESOURCE_IRQ, |
1406 | }, | 1406 | }, |
1407 | }; | 1407 | }; |
@@ -1453,8 +1453,8 @@ static struct resource ssc0_resources[] = { | |||
1453 | .flags = IORESOURCE_MEM, | 1453 | .flags = IORESOURCE_MEM, |
1454 | }, | 1454 | }, |
1455 | [1] = { | 1455 | [1] = { |
1456 | .start = AT91SAM9G45_ID_SSC0, | 1456 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, |
1457 | .end = AT91SAM9G45_ID_SSC0, | 1457 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0, |
1458 | .flags = IORESOURCE_IRQ, | 1458 | .flags = IORESOURCE_IRQ, |
1459 | }, | 1459 | }, |
1460 | }; | 1460 | }; |
@@ -1495,8 +1495,8 @@ static struct resource ssc1_resources[] = { | |||
1495 | .flags = IORESOURCE_MEM, | 1495 | .flags = IORESOURCE_MEM, |
1496 | }, | 1496 | }, |
1497 | [1] = { | 1497 | [1] = { |
1498 | .start = AT91SAM9G45_ID_SSC1, | 1498 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, |
1499 | .end = AT91SAM9G45_ID_SSC1, | 1499 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1, |
1500 | .flags = IORESOURCE_IRQ, | 1500 | .flags = IORESOURCE_IRQ, |
1501 | }, | 1501 | }, |
1502 | }; | 1502 | }; |
@@ -1575,8 +1575,8 @@ static struct resource dbgu_resources[] = { | |||
1575 | .flags = IORESOURCE_MEM, | 1575 | .flags = IORESOURCE_MEM, |
1576 | }, | 1576 | }, |
1577 | [1] = { | 1577 | [1] = { |
1578 | .start = AT91_ID_SYS, | 1578 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
1579 | .end = AT91_ID_SYS, | 1579 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
1580 | .flags = IORESOURCE_IRQ, | 1580 | .flags = IORESOURCE_IRQ, |
1581 | }, | 1581 | }, |
1582 | }; | 1582 | }; |
@@ -1613,8 +1613,8 @@ static struct resource uart0_resources[] = { | |||
1613 | .flags = IORESOURCE_MEM, | 1613 | .flags = IORESOURCE_MEM, |
1614 | }, | 1614 | }, |
1615 | [1] = { | 1615 | [1] = { |
1616 | .start = AT91SAM9G45_ID_US0, | 1616 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, |
1617 | .end = AT91SAM9G45_ID_US0, | 1617 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0, |
1618 | .flags = IORESOURCE_IRQ, | 1618 | .flags = IORESOURCE_IRQ, |
1619 | }, | 1619 | }, |
1620 | }; | 1620 | }; |
@@ -1656,8 +1656,8 @@ static struct resource uart1_resources[] = { | |||
1656 | .flags = IORESOURCE_MEM, | 1656 | .flags = IORESOURCE_MEM, |
1657 | }, | 1657 | }, |
1658 | [1] = { | 1658 | [1] = { |
1659 | .start = AT91SAM9G45_ID_US1, | 1659 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, |
1660 | .end = AT91SAM9G45_ID_US1, | 1660 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1, |
1661 | .flags = IORESOURCE_IRQ, | 1661 | .flags = IORESOURCE_IRQ, |
1662 | }, | 1662 | }, |
1663 | }; | 1663 | }; |
@@ -1699,8 +1699,8 @@ static struct resource uart2_resources[] = { | |||
1699 | .flags = IORESOURCE_MEM, | 1699 | .flags = IORESOURCE_MEM, |
1700 | }, | 1700 | }, |
1701 | [1] = { | 1701 | [1] = { |
1702 | .start = AT91SAM9G45_ID_US2, | 1702 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, |
1703 | .end = AT91SAM9G45_ID_US2, | 1703 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2, |
1704 | .flags = IORESOURCE_IRQ, | 1704 | .flags = IORESOURCE_IRQ, |
1705 | }, | 1705 | }, |
1706 | }; | 1706 | }; |
@@ -1742,8 +1742,8 @@ static struct resource uart3_resources[] = { | |||
1742 | .flags = IORESOURCE_MEM, | 1742 | .flags = IORESOURCE_MEM, |
1743 | }, | 1743 | }, |
1744 | [1] = { | 1744 | [1] = { |
1745 | .start = AT91SAM9G45_ID_US3, | 1745 | .start = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, |
1746 | .end = AT91SAM9G45_ID_US3, | 1746 | .end = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3, |
1747 | .flags = IORESOURCE_IRQ, | 1747 | .flags = IORESOURCE_IRQ, |
1748 | }, | 1748 | }, |
1749 | }; | 1749 | }; |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index e420085a57ef..72ce50a50de5 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <mach/cpu.h> | 19 | #include <mach/cpu.h> |
20 | #include <mach/at91_dbgu.h> | 20 | #include <mach/at91_dbgu.h> |
21 | #include <mach/at91sam9rl.h> | 21 | #include <mach/at91sam9rl.h> |
22 | #include <mach/at91_aic.h> | ||
22 | #include <mach/at91_pmc.h> | 23 | #include <mach/at91_pmc.h> |
23 | #include <mach/at91_rstc.h> | 24 | #include <mach/at91_rstc.h> |
24 | 25 | ||
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c index 9c0b1481a9a7..f09fff932172 100644 --- a/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/arch/arm/mach-at91/at91sam9rl_devices.c | |||
@@ -41,8 +41,8 @@ static struct resource hdmac_resources[] = { | |||
41 | .flags = IORESOURCE_MEM, | 41 | .flags = IORESOURCE_MEM, |
42 | }, | 42 | }, |
43 | [2] = { | 43 | [2] = { |
44 | .start = AT91SAM9RL_ID_DMA, | 44 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, |
45 | .end = AT91SAM9RL_ID_DMA, | 45 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA, |
46 | .flags = IORESOURCE_IRQ, | 46 | .flags = IORESOURCE_IRQ, |
47 | }, | 47 | }, |
48 | }; | 48 | }; |
@@ -84,8 +84,8 @@ static struct resource usba_udc_resources[] = { | |||
84 | .flags = IORESOURCE_MEM, | 84 | .flags = IORESOURCE_MEM, |
85 | }, | 85 | }, |
86 | [2] = { | 86 | [2] = { |
87 | .start = AT91SAM9RL_ID_UDPHS, | 87 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, |
88 | .end = AT91SAM9RL_ID_UDPHS, | 88 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS, |
89 | .flags = IORESOURCE_IRQ, | 89 | .flags = IORESOURCE_IRQ, |
90 | }, | 90 | }, |
91 | }; | 91 | }; |
@@ -172,8 +172,8 @@ static struct resource mmc_resources[] = { | |||
172 | .flags = IORESOURCE_MEM, | 172 | .flags = IORESOURCE_MEM, |
173 | }, | 173 | }, |
174 | [1] = { | 174 | [1] = { |
175 | .start = AT91SAM9RL_ID_MCI, | 175 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, |
176 | .end = AT91SAM9RL_ID_MCI, | 176 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI, |
177 | .flags = IORESOURCE_IRQ, | 177 | .flags = IORESOURCE_IRQ, |
178 | }, | 178 | }, |
179 | }; | 179 | }; |
@@ -339,8 +339,8 @@ static struct resource twi_resources[] = { | |||
339 | .flags = IORESOURCE_MEM, | 339 | .flags = IORESOURCE_MEM, |
340 | }, | 340 | }, |
341 | [1] = { | 341 | [1] = { |
342 | .start = AT91SAM9RL_ID_TWI0, | 342 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, |
343 | .end = AT91SAM9RL_ID_TWI0, | 343 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0, |
344 | .flags = IORESOURCE_IRQ, | 344 | .flags = IORESOURCE_IRQ, |
345 | }, | 345 | }, |
346 | }; | 346 | }; |
@@ -383,8 +383,8 @@ static struct resource spi_resources[] = { | |||
383 | .flags = IORESOURCE_MEM, | 383 | .flags = IORESOURCE_MEM, |
384 | }, | 384 | }, |
385 | [1] = { | 385 | [1] = { |
386 | .start = AT91SAM9RL_ID_SPI, | 386 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, |
387 | .end = AT91SAM9RL_ID_SPI, | 387 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI, |
388 | .flags = IORESOURCE_IRQ, | 388 | .flags = IORESOURCE_IRQ, |
389 | }, | 389 | }, |
390 | }; | 390 | }; |
@@ -452,8 +452,8 @@ static struct resource ac97_resources[] = { | |||
452 | .flags = IORESOURCE_MEM, | 452 | .flags = IORESOURCE_MEM, |
453 | }, | 453 | }, |
454 | [1] = { | 454 | [1] = { |
455 | .start = AT91SAM9RL_ID_AC97C, | 455 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, |
456 | .end = AT91SAM9RL_ID_AC97C, | 456 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C, |
457 | .flags = IORESOURCE_IRQ, | 457 | .flags = IORESOURCE_IRQ, |
458 | }, | 458 | }, |
459 | }; | 459 | }; |
@@ -507,8 +507,8 @@ static struct resource lcdc_resources[] = { | |||
507 | .flags = IORESOURCE_MEM, | 507 | .flags = IORESOURCE_MEM, |
508 | }, | 508 | }, |
509 | [1] = { | 509 | [1] = { |
510 | .start = AT91SAM9RL_ID_LCDC, | 510 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, |
511 | .end = AT91SAM9RL_ID_LCDC, | 511 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC, |
512 | .flags = IORESOURCE_IRQ, | 512 | .flags = IORESOURCE_IRQ, |
513 | }, | 513 | }, |
514 | }; | 514 | }; |
@@ -574,18 +574,18 @@ static struct resource tcb_resources[] = { | |||
574 | .flags = IORESOURCE_MEM, | 574 | .flags = IORESOURCE_MEM, |
575 | }, | 575 | }, |
576 | [1] = { | 576 | [1] = { |
577 | .start = AT91SAM9RL_ID_TC0, | 577 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, |
578 | .end = AT91SAM9RL_ID_TC0, | 578 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0, |
579 | .flags = IORESOURCE_IRQ, | 579 | .flags = IORESOURCE_IRQ, |
580 | }, | 580 | }, |
581 | [2] = { | 581 | [2] = { |
582 | .start = AT91SAM9RL_ID_TC1, | 582 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, |
583 | .end = AT91SAM9RL_ID_TC1, | 583 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1, |
584 | .flags = IORESOURCE_IRQ, | 584 | .flags = IORESOURCE_IRQ, |
585 | }, | 585 | }, |
586 | [3] = { | 586 | [3] = { |
587 | .start = AT91SAM9RL_ID_TC2, | 587 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, |
588 | .end = AT91SAM9RL_ID_TC2, | 588 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2, |
589 | .flags = IORESOURCE_IRQ, | 589 | .flags = IORESOURCE_IRQ, |
590 | }, | 590 | }, |
591 | }; | 591 | }; |
@@ -621,8 +621,8 @@ static struct resource tsadcc_resources[] = { | |||
621 | .flags = IORESOURCE_MEM, | 621 | .flags = IORESOURCE_MEM, |
622 | }, | 622 | }, |
623 | [1] = { | 623 | [1] = { |
624 | .start = AT91SAM9RL_ID_TSC, | 624 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, |
625 | .end = AT91SAM9RL_ID_TSC, | 625 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC, |
626 | .flags = IORESOURCE_IRQ, | 626 | .flags = IORESOURCE_IRQ, |
627 | } | 627 | } |
628 | }; | 628 | }; |
@@ -768,8 +768,8 @@ static struct resource pwm_resources[] = { | |||
768 | .flags = IORESOURCE_MEM, | 768 | .flags = IORESOURCE_MEM, |
769 | }, | 769 | }, |
770 | [1] = { | 770 | [1] = { |
771 | .start = AT91SAM9RL_ID_PWMC, | 771 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, |
772 | .end = AT91SAM9RL_ID_PWMC, | 772 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC, |
773 | .flags = IORESOURCE_IRQ, | 773 | .flags = IORESOURCE_IRQ, |
774 | }, | 774 | }, |
775 | }; | 775 | }; |
@@ -821,8 +821,8 @@ static struct resource ssc0_resources[] = { | |||
821 | .flags = IORESOURCE_MEM, | 821 | .flags = IORESOURCE_MEM, |
822 | }, | 822 | }, |
823 | [1] = { | 823 | [1] = { |
824 | .start = AT91SAM9RL_ID_SSC0, | 824 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, |
825 | .end = AT91SAM9RL_ID_SSC0, | 825 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0, |
826 | .flags = IORESOURCE_IRQ, | 826 | .flags = IORESOURCE_IRQ, |
827 | }, | 827 | }, |
828 | }; | 828 | }; |
@@ -863,8 +863,8 @@ static struct resource ssc1_resources[] = { | |||
863 | .flags = IORESOURCE_MEM, | 863 | .flags = IORESOURCE_MEM, |
864 | }, | 864 | }, |
865 | [1] = { | 865 | [1] = { |
866 | .start = AT91SAM9RL_ID_SSC1, | 866 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, |
867 | .end = AT91SAM9RL_ID_SSC1, | 867 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1, |
868 | .flags = IORESOURCE_IRQ, | 868 | .flags = IORESOURCE_IRQ, |
869 | }, | 869 | }, |
870 | }; | 870 | }; |
@@ -943,8 +943,8 @@ static struct resource dbgu_resources[] = { | |||
943 | .flags = IORESOURCE_MEM, | 943 | .flags = IORESOURCE_MEM, |
944 | }, | 944 | }, |
945 | [1] = { | 945 | [1] = { |
946 | .start = AT91_ID_SYS, | 946 | .start = NR_IRQS_LEGACY + AT91_ID_SYS, |
947 | .end = AT91_ID_SYS, | 947 | .end = NR_IRQS_LEGACY + AT91_ID_SYS, |
948 | .flags = IORESOURCE_IRQ, | 948 | .flags = IORESOURCE_IRQ, |
949 | }, | 949 | }, |
950 | }; | 950 | }; |
@@ -981,8 +981,8 @@ static struct resource uart0_resources[] = { | |||
981 | .flags = IORESOURCE_MEM, | 981 | .flags = IORESOURCE_MEM, |
982 | }, | 982 | }, |
983 | [1] = { | 983 | [1] = { |
984 | .start = AT91SAM9RL_ID_US0, | 984 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, |
985 | .end = AT91SAM9RL_ID_US0, | 985 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0, |
986 | .flags = IORESOURCE_IRQ, | 986 | .flags = IORESOURCE_IRQ, |
987 | }, | 987 | }, |
988 | }; | 988 | }; |
@@ -1032,8 +1032,8 @@ static struct resource uart1_resources[] = { | |||
1032 | .flags = IORESOURCE_MEM, | 1032 | .flags = IORESOURCE_MEM, |
1033 | }, | 1033 | }, |
1034 | [1] = { | 1034 | [1] = { |
1035 | .start = AT91SAM9RL_ID_US1, | 1035 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, |
1036 | .end = AT91SAM9RL_ID_US1, | 1036 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1, |
1037 | .flags = IORESOURCE_IRQ, | 1037 | .flags = IORESOURCE_IRQ, |
1038 | }, | 1038 | }, |
1039 | }; | 1039 | }; |
@@ -1075,8 +1075,8 @@ static struct resource uart2_resources[] = { | |||
1075 | .flags = IORESOURCE_MEM, | 1075 | .flags = IORESOURCE_MEM, |
1076 | }, | 1076 | }, |
1077 | [1] = { | 1077 | [1] = { |
1078 | .start = AT91SAM9RL_ID_US2, | 1078 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, |
1079 | .end = AT91SAM9RL_ID_US2, | 1079 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2, |
1080 | .flags = IORESOURCE_IRQ, | 1080 | .flags = IORESOURCE_IRQ, |
1081 | }, | 1081 | }, |
1082 | }; | 1082 | }; |
@@ -1118,8 +1118,8 @@ static struct resource uart3_resources[] = { | |||
1118 | .flags = IORESOURCE_MEM, | 1118 | .flags = IORESOURCE_MEM, |
1119 | }, | 1119 | }, |
1120 | [1] = { | 1120 | [1] = { |
1121 | .start = AT91SAM9RL_ID_US3, | 1121 | .start = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, |
1122 | .end = AT91SAM9RL_ID_US3, | 1122 | .end = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3, |
1123 | .flags = IORESOURCE_IRQ, | 1123 | .flags = IORESOURCE_IRQ, |
1124 | }, | 1124 | }, |
1125 | }; | 1125 | }; |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index 1b144b4d3ce1..477cf9d06672 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
@@ -312,8 +312,6 @@ static void __init at91sam9x5_map_io(void) | |||
312 | 312 | ||
313 | void __init at91sam9x5_initialize(void) | 313 | void __init at91sam9x5_initialize(void) |
314 | { | 314 | { |
315 | at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0); | ||
316 | |||
317 | /* Register GPIO subsystem (using DT) */ | 315 | /* Register GPIO subsystem (using DT) */ |
318 | at91_gpio_init(NULL, 0); | 316 | at91_gpio_init(NULL, 0); |
319 | } | 317 | } |
@@ -321,47 +319,9 @@ void __init at91sam9x5_initialize(void) | |||
321 | /* -------------------------------------------------------------------- | 319 | /* -------------------------------------------------------------------- |
322 | * Interrupt initialization | 320 | * Interrupt initialization |
323 | * -------------------------------------------------------------------- */ | 321 | * -------------------------------------------------------------------- */ |
324 | /* | ||
325 | * The default interrupt priority levels (0 = lowest, 7 = highest). | ||
326 | */ | ||
327 | static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = { | ||
328 | 7, /* Advanced Interrupt Controller (FIQ) */ | ||
329 | 7, /* System Peripherals */ | ||
330 | 1, /* Parallel IO Controller A and B */ | ||
331 | 1, /* Parallel IO Controller C and D */ | ||
332 | 4, /* Soft Modem */ | ||
333 | 5, /* USART 0 */ | ||
334 | 5, /* USART 1 */ | ||
335 | 5, /* USART 2 */ | ||
336 | 5, /* USART 3 */ | ||
337 | 6, /* Two-Wire Interface 0 */ | ||
338 | 6, /* Two-Wire Interface 1 */ | ||
339 | 6, /* Two-Wire Interface 2 */ | ||
340 | 0, /* Multimedia Card Interface 0 */ | ||
341 | 5, /* Serial Peripheral Interface 0 */ | ||
342 | 5, /* Serial Peripheral Interface 1 */ | ||
343 | 5, /* UART 0 */ | ||
344 | 5, /* UART 1 */ | ||
345 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | ||
346 | 0, /* Pulse Width Modulation Controller */ | ||
347 | 0, /* ADC Controller */ | ||
348 | 0, /* DMA Controller 0 */ | ||
349 | 0, /* DMA Controller 1 */ | ||
350 | 2, /* USB Host High Speed port */ | ||
351 | 2, /* USB Device High speed port */ | ||
352 | 3, /* Ethernet MAC 0 */ | ||
353 | 3, /* LDC Controller or Image Sensor Interface */ | ||
354 | 0, /* Multimedia Card Interface 1 */ | ||
355 | 3, /* Ethernet MAC 1 */ | ||
356 | 4, /* Synchronous Serial Interface */ | ||
357 | 4, /* CAN Controller 0 */ | ||
358 | 4, /* CAN Controller 1 */ | ||
359 | 0, /* Advanced Interrupt Controller (IRQ0) */ | ||
360 | }; | ||
361 | 322 | ||
362 | struct at91_init_soc __initdata at91sam9x5_soc = { | 323 | struct at91_init_soc __initdata at91sam9x5_soc = { |
363 | .map_io = at91sam9x5_map_io, | 324 | .map_io = at91sam9x5_map_io, |
364 | .default_irq_priority = at91sam9x5_default_irq_priority, | ||
365 | .register_clocks = at91sam9x5_register_clocks, | 325 | .register_clocks = at91sam9x5_register_clocks, |
366 | .init = at91sam9x5_initialize, | 326 | .init = at91sam9x5_initialize, |
367 | }; | 327 | }; |
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c index d62fe090d814..46090e642d8e 100644 --- a/arch/arm/mach-at91/at91x40.c +++ b/arch/arm/mach-at91/at91x40.c | |||
@@ -13,10 +13,12 @@ | |||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/irq.h> | 15 | #include <linux/irq.h> |
16 | #include <linux/io.h> | ||
16 | #include <asm/proc-fns.h> | 17 | #include <asm/proc-fns.h> |
17 | #include <asm/system_misc.h> | 18 | #include <asm/system_misc.h> |
18 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
19 | #include <mach/at91x40.h> | 20 | #include <mach/at91x40.h> |
21 | #include <mach/at91_aic.h> | ||
20 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
21 | #include <mach/timex.h> | 23 | #include <mach/timex.h> |
22 | #include "generic.h" | 24 | #include "generic.h" |
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c index 271f994314a4..22d8856094f1 100644 --- a/arch/arm/mach-at91/board-1arm.c +++ b/arch/arm/mach-at91/board-1arm.c | |||
@@ -36,6 +36,7 @@ | |||
36 | 36 | ||
37 | #include <mach/board.h> | 37 | #include <mach/board.h> |
38 | #include <mach/cpu.h> | 38 | #include <mach/cpu.h> |
39 | #include <mach/at91_aic.h> | ||
39 | 40 | ||
40 | #include "generic.h" | 41 | #include "generic.h" |
41 | 42 | ||
@@ -91,6 +92,7 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") | |||
91 | /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ | 92 | /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ |
92 | .timer = &at91rm9200_timer, | 93 | .timer = &at91rm9200_timer, |
93 | .map_io = at91_map_io, | 94 | .map_io = at91_map_io, |
95 | .handle_irq = at91_aic_handle_irq, | ||
94 | .init_early = onearm_init_early, | 96 | .init_early = onearm_init_early, |
95 | .init_irq = at91_init_irq_default, | 97 | .init_irq = at91_init_irq_default, |
96 | .init_machine = onearm_board_init, | 98 | .init_machine = onearm_board_init, |
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index b7d8aa7b81e6..de7be1931817 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
45 | 45 | ||
46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
47 | #include <mach/at91_aic.h> | ||
47 | 48 | ||
48 | #include "generic.h" | 49 | #include "generic.h" |
49 | 50 | ||
@@ -212,6 +213,7 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board") | |||
212 | /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ | 213 | /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ |
213 | .timer = &at91sam926x_timer, | 214 | .timer = &at91sam926x_timer, |
214 | .map_io = at91_map_io, | 215 | .map_io = at91_map_io, |
216 | .handle_irq = at91_aic_handle_irq, | ||
215 | .init_early = afeb9260_init_early, | 217 | .init_early = afeb9260_init_early, |
216 | .init_irq = at91_init_irq_default, | 218 | .init_irq = at91_init_irq_default, |
217 | .init_machine = afeb9260_board_init, | 219 | .init_machine = afeb9260_board_init, |
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c index 29d3ef0a50fb..477e708497bc 100644 --- a/arch/arm/mach-at91/board-cam60.c +++ b/arch/arm/mach-at91/board-cam60.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
40 | 40 | ||
41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
42 | #include <mach/at91_aic.h> | ||
42 | #include <mach/at91sam9_smc.h> | 43 | #include <mach/at91sam9_smc.h> |
43 | 44 | ||
44 | #include "sam9_smc.h" | 45 | #include "sam9_smc.h" |
@@ -188,6 +189,7 @@ MACHINE_START(CAM60, "KwikByte CAM60") | |||
188 | /* Maintainer: KwikByte */ | 189 | /* Maintainer: KwikByte */ |
189 | .timer = &at91sam926x_timer, | 190 | .timer = &at91sam926x_timer, |
190 | .map_io = at91_map_io, | 191 | .map_io = at91_map_io, |
192 | .handle_irq = at91_aic_handle_irq, | ||
191 | .init_early = cam60_init_early, | 193 | .init_early = cam60_init_early, |
192 | .init_irq = at91_init_irq_default, | 194 | .init_irq = at91_init_irq_default, |
193 | .init_machine = cam60_board_init, | 195 | .init_machine = cam60_board_init, |
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c index 44328a6d4609..a5b002f32a61 100644 --- a/arch/arm/mach-at91/board-carmeva.c +++ b/arch/arm/mach-at91/board-carmeva.c | |||
@@ -36,6 +36,7 @@ | |||
36 | 36 | ||
37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
39 | #include <mach/at91_aic.h> | ||
39 | 40 | ||
40 | #include "generic.h" | 41 | #include "generic.h" |
41 | 42 | ||
@@ -158,6 +159,7 @@ MACHINE_START(CARMEVA, "Carmeva") | |||
158 | /* Maintainer: Conitec Datasystems */ | 159 | /* Maintainer: Conitec Datasystems */ |
159 | .timer = &at91rm9200_timer, | 160 | .timer = &at91rm9200_timer, |
160 | .map_io = at91_map_io, | 161 | .map_io = at91_map_io, |
162 | .handle_irq = at91_aic_handle_irq, | ||
161 | .init_early = carmeva_init_early, | 163 | .init_early = carmeva_init_early, |
162 | .init_irq = at91_init_irq_default, | 164 | .init_irq = at91_init_irq_default, |
163 | .init_machine = carmeva_board_init, | 165 | .init_machine = carmeva_board_init, |
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c index 69951ec7dbf3..ecbc13b594de 100644 --- a/arch/arm/mach-at91/board-cpu9krea.c +++ b/arch/arm/mach-at91/board-cpu9krea.c | |||
@@ -41,6 +41,7 @@ | |||
41 | 41 | ||
42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
43 | #include <mach/board.h> | 43 | #include <mach/board.h> |
44 | #include <mach/at91_aic.h> | ||
44 | #include <mach/at91sam9_smc.h> | 45 | #include <mach/at91sam9_smc.h> |
45 | #include <mach/at91sam9260_matrix.h> | 46 | #include <mach/at91sam9260_matrix.h> |
46 | #include <mach/at91_matrix.h> | 47 | #include <mach/at91_matrix.h> |
@@ -376,6 +377,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") | |||
376 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | 377 | /* Maintainer: Eric Benard - EUKREA Electromatique */ |
377 | .timer = &at91sam926x_timer, | 378 | .timer = &at91sam926x_timer, |
378 | .map_io = at91_map_io, | 379 | .map_io = at91_map_io, |
380 | .handle_irq = at91_aic_handle_irq, | ||
379 | .init_early = cpu9krea_init_early, | 381 | .init_early = cpu9krea_init_early, |
380 | .init_irq = at91_init_irq_default, | 382 | .init_irq = at91_init_irq_default, |
381 | .init_machine = cpu9krea_board_init, | 383 | .init_machine = cpu9krea_board_init, |
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c index 895cf2dba612..2e6d043c82f2 100644 --- a/arch/arm/mach-at91/board-cpuat91.c +++ b/arch/arm/mach-at91/board-cpuat91.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <asm/mach/irq.h> | 37 | #include <asm/mach/irq.h> |
38 | 38 | ||
39 | #include <mach/board.h> | 39 | #include <mach/board.h> |
40 | #include <mach/at91_aic.h> | ||
40 | #include <mach/at91rm9200_mc.h> | 41 | #include <mach/at91rm9200_mc.h> |
41 | #include <mach/at91_ramc.h> | 42 | #include <mach/at91_ramc.h> |
42 | #include <mach/cpu.h> | 43 | #include <mach/cpu.h> |
@@ -178,6 +179,7 @@ MACHINE_START(CPUAT91, "Eukrea") | |||
178 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | 179 | /* Maintainer: Eric Benard - EUKREA Electromatique */ |
179 | .timer = &at91rm9200_timer, | 180 | .timer = &at91rm9200_timer, |
180 | .map_io = at91_map_io, | 181 | .map_io = at91_map_io, |
182 | .handle_irq = at91_aic_handle_irq, | ||
181 | .init_early = cpuat91_init_early, | 183 | .init_early = cpuat91_init_early, |
182 | .init_irq = at91_init_irq_default, | 184 | .init_irq = at91_init_irq_default, |
183 | .init_machine = cpuat91_board_init, | 185 | .init_machine = cpuat91_board_init, |
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c index cd813361cd26..462bc319cbc5 100644 --- a/arch/arm/mach-at91/board-csb337.c +++ b/arch/arm/mach-at91/board-csb337.c | |||
@@ -39,6 +39,7 @@ | |||
39 | 39 | ||
40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
42 | #include <mach/at91_aic.h> | ||
42 | 43 | ||
43 | #include "generic.h" | 44 | #include "generic.h" |
44 | 45 | ||
@@ -252,6 +253,7 @@ MACHINE_START(CSB337, "Cogent CSB337") | |||
252 | /* Maintainer: Bill Gatliff */ | 253 | /* Maintainer: Bill Gatliff */ |
253 | .timer = &at91rm9200_timer, | 254 | .timer = &at91rm9200_timer, |
254 | .map_io = at91_map_io, | 255 | .map_io = at91_map_io, |
256 | .handle_irq = at91_aic_handle_irq, | ||
255 | .init_early = csb337_init_early, | 257 | .init_early = csb337_init_early, |
256 | .init_irq = at91_init_irq_default, | 258 | .init_irq = at91_init_irq_default, |
257 | .init_machine = csb337_board_init, | 259 | .init_machine = csb337_board_init, |
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c index 7c8b05a57d7f..872871ab1160 100644 --- a/arch/arm/mach-at91/board-csb637.c +++ b/arch/arm/mach-at91/board-csb637.c | |||
@@ -36,6 +36,7 @@ | |||
36 | 36 | ||
37 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
39 | #include <mach/at91_aic.h> | ||
39 | 40 | ||
40 | #include "generic.h" | 41 | #include "generic.h" |
41 | 42 | ||
@@ -133,6 +134,7 @@ MACHINE_START(CSB637, "Cogent CSB637") | |||
133 | /* Maintainer: Bill Gatliff */ | 134 | /* Maintainer: Bill Gatliff */ |
134 | .timer = &at91rm9200_timer, | 135 | .timer = &at91rm9200_timer, |
135 | .map_io = at91_map_io, | 136 | .map_io = at91_map_io, |
137 | .handle_irq = at91_aic_handle_irq, | ||
136 | .init_early = csb637_init_early, | 138 | .init_early = csb637_init_early, |
137 | .init_irq = at91_init_irq_default, | 139 | .init_irq = at91_init_irq_default, |
138 | .init_machine = csb637_board_init, | 140 | .init_machine = csb637_board_init, |
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c index a1fce05aa7a5..e8f45c4e0ea8 100644 --- a/arch/arm/mach-at91/board-dt.c +++ b/arch/arm/mach-at91/board-dt.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/of_platform.h> | 16 | #include <linux/of_platform.h> |
17 | 17 | ||
18 | #include <mach/board.h> | 18 | #include <mach/board.h> |
19 | #include <mach/at91_aic.h> | ||
19 | 20 | ||
20 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
21 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
@@ -53,6 +54,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") | |||
53 | /* Maintainer: Atmel */ | 54 | /* Maintainer: Atmel */ |
54 | .timer = &at91sam926x_timer, | 55 | .timer = &at91sam926x_timer, |
55 | .map_io = at91_map_io, | 56 | .map_io = at91_map_io, |
57 | .handle_irq = at91_aic_handle_irq, | ||
56 | .init_early = at91_dt_initialize, | 58 | .init_early = at91_dt_initialize, |
57 | .init_irq = at91_dt_init_irq, | 59 | .init_irq = at91_dt_init_irq, |
58 | .init_machine = at91_dt_device_init, | 60 | .init_machine = at91_dt_device_init, |
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c index d2023f27c652..01f66e99ece7 100644 --- a/arch/arm/mach-at91/board-eb01.c +++ b/arch/arm/mach-at91/board-eb01.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
29 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
30 | #include <mach/board.h> | 30 | #include <mach/board.h> |
31 | #include <mach/at91_aic.h> | ||
31 | #include "generic.h" | 32 | #include "generic.h" |
32 | 33 | ||
33 | static void __init at91eb01_init_irq(void) | 34 | static void __init at91eb01_init_irq(void) |
@@ -43,6 +44,7 @@ static void __init at91eb01_init_early(void) | |||
43 | MACHINE_START(AT91EB01, "Atmel AT91 EB01") | 44 | MACHINE_START(AT91EB01, "Atmel AT91 EB01") |
44 | /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ | 45 | /* Maintainer: Greg Ungerer <gerg@snapgear.com> */ |
45 | .timer = &at91x40_timer, | 46 | .timer = &at91x40_timer, |
47 | .handle_irq = at91_aic_handle_irq, | ||
46 | .init_early = at91eb01_init_early, | 48 | .init_early = at91eb01_init_early, |
47 | .init_irq = at91eb01_init_irq, | 49 | .init_irq = at91eb01_init_irq, |
48 | MACHINE_END | 50 | MACHINE_END |
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c index bd1017297989..d1e1f3fc0a47 100644 --- a/arch/arm/mach-at91/board-eb9200.c +++ b/arch/arm/mach-at91/board-eb9200.c | |||
@@ -36,6 +36,7 @@ | |||
36 | #include <asm/mach/irq.h> | 36 | #include <asm/mach/irq.h> |
37 | 37 | ||
38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
39 | #include <mach/at91_aic.h> | ||
39 | 40 | ||
40 | #include "generic.h" | 41 | #include "generic.h" |
41 | 42 | ||
@@ -118,6 +119,7 @@ static void __init eb9200_board_init(void) | |||
118 | MACHINE_START(ATEB9200, "Embest ATEB9200") | 119 | MACHINE_START(ATEB9200, "Embest ATEB9200") |
119 | .timer = &at91rm9200_timer, | 120 | .timer = &at91rm9200_timer, |
120 | .map_io = at91_map_io, | 121 | .map_io = at91_map_io, |
122 | .handle_irq = at91_aic_handle_irq, | ||
121 | .init_early = eb9200_init_early, | 123 | .init_early = eb9200_init_early, |
122 | .init_irq = at91_init_irq_default, | 124 | .init_irq = at91_init_irq_default, |
123 | .init_machine = eb9200_board_init, | 125 | .init_machine = eb9200_board_init, |
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c index 89cc3726a9ce..9c24cb25707c 100644 --- a/arch/arm/mach-at91/board-ecbat91.c +++ b/arch/arm/mach-at91/board-ecbat91.c | |||
@@ -39,6 +39,7 @@ | |||
39 | 39 | ||
40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
41 | #include <mach/cpu.h> | 41 | #include <mach/cpu.h> |
42 | #include <mach/at91_aic.h> | ||
42 | 43 | ||
43 | #include "generic.h" | 44 | #include "generic.h" |
44 | 45 | ||
@@ -170,6 +171,7 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91") | |||
170 | /* Maintainer: emQbit.com */ | 171 | /* Maintainer: emQbit.com */ |
171 | .timer = &at91rm9200_timer, | 172 | .timer = &at91rm9200_timer, |
172 | .map_io = at91_map_io, | 173 | .map_io = at91_map_io, |
174 | .handle_irq = at91_aic_handle_irq, | ||
173 | .init_early = ecb_at91init_early, | 175 | .init_early = ecb_at91init_early, |
174 | .init_irq = at91_init_irq_default, | 176 | .init_irq = at91_init_irq_default, |
175 | .init_machine = ecb_at91board_init, | 177 | .init_machine = ecb_at91board_init, |
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c index 558546cf63f4..82bdfde3405f 100644 --- a/arch/arm/mach-at91/board-eco920.c +++ b/arch/arm/mach-at91/board-eco920.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <asm/mach/map.h> | 25 | #include <asm/mach/map.h> |
26 | 26 | ||
27 | #include <mach/board.h> | 27 | #include <mach/board.h> |
28 | #include <mach/at91_aic.h> | ||
28 | #include <mach/at91rm9200_mc.h> | 29 | #include <mach/at91rm9200_mc.h> |
29 | #include <mach/at91_ramc.h> | 30 | #include <mach/at91_ramc.h> |
30 | #include <mach/cpu.h> | 31 | #include <mach/cpu.h> |
@@ -132,6 +133,7 @@ MACHINE_START(ECO920, "eco920") | |||
132 | /* Maintainer: Sascha Hauer */ | 133 | /* Maintainer: Sascha Hauer */ |
133 | .timer = &at91rm9200_timer, | 134 | .timer = &at91rm9200_timer, |
134 | .map_io = at91_map_io, | 135 | .map_io = at91_map_io, |
136 | .handle_irq = at91_aic_handle_irq, | ||
135 | .init_early = eco920_init_early, | 137 | .init_early = eco920_init_early, |
136 | .init_irq = at91_init_irq_default, | 138 | .init_irq = at91_init_irq_default, |
137 | .init_machine = eco920_board_init, | 139 | .init_machine = eco920_board_init, |
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c index 47658f78105d..6cc83a87d77c 100644 --- a/arch/arm/mach-at91/board-flexibity.c +++ b/arch/arm/mach-at91/board-flexibity.c | |||
@@ -34,6 +34,7 @@ | |||
34 | 34 | ||
35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
36 | #include <mach/board.h> | 36 | #include <mach/board.h> |
37 | #include <mach/at91_aic.h> | ||
37 | 38 | ||
38 | #include "generic.h" | 39 | #include "generic.h" |
39 | 40 | ||
@@ -160,6 +161,7 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect") | |||
160 | /* Maintainer: Maxim Osipov */ | 161 | /* Maintainer: Maxim Osipov */ |
161 | .timer = &at91sam926x_timer, | 162 | .timer = &at91sam926x_timer, |
162 | .map_io = at91_map_io, | 163 | .map_io = at91_map_io, |
164 | .handle_irq = at91_aic_handle_irq, | ||
163 | .init_early = flexibity_init_early, | 165 | .init_early = flexibity_init_early, |
164 | .init_irq = at91_init_irq_default, | 166 | .init_irq = at91_init_irq_default, |
165 | .init_machine = flexibity_board_init, | 167 | .init_machine = flexibity_board_init, |
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c index 33411e6ecb1f..69ab1247ef81 100644 --- a/arch/arm/mach-at91/board-foxg20.c +++ b/arch/arm/mach-at91/board-foxg20.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
43 | 43 | ||
44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
45 | #include <mach/at91_aic.h> | ||
45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
46 | 47 | ||
47 | #include "sam9_smc.h" | 48 | #include "sam9_smc.h" |
@@ -262,6 +263,7 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20") | |||
262 | /* Maintainer: Sergio Tanzilli */ | 263 | /* Maintainer: Sergio Tanzilli */ |
263 | .timer = &at91sam926x_timer, | 264 | .timer = &at91sam926x_timer, |
264 | .map_io = at91_map_io, | 265 | .map_io = at91_map_io, |
266 | .handle_irq = at91_aic_handle_irq, | ||
265 | .init_early = foxg20_init_early, | 267 | .init_early = foxg20_init_early, |
266 | .init_irq = at91_init_irq_default, | 268 | .init_irq = at91_init_irq_default, |
267 | .init_machine = foxg20_board_init, | 269 | .init_machine = foxg20_board_init, |
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c index 3e0dfa643a86..a9d5e78118c5 100644 --- a/arch/arm/mach-at91/board-gsia18s.c +++ b/arch/arm/mach-at91/board-gsia18s.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
32 | 32 | ||
33 | #include <mach/board.h> | 33 | #include <mach/board.h> |
34 | #include <mach/at91_aic.h> | ||
34 | #include <mach/at91sam9_smc.h> | 35 | #include <mach/at91sam9_smc.h> |
35 | #include <mach/gsia18s.h> | 36 | #include <mach/gsia18s.h> |
36 | #include <mach/stamp9g20.h> | 37 | #include <mach/stamp9g20.h> |
@@ -575,6 +576,7 @@ static void __init gsia18s_board_init(void) | |||
575 | MACHINE_START(GSIA18S, "GS_IA18_S") | 576 | MACHINE_START(GSIA18S, "GS_IA18_S") |
576 | .timer = &at91sam926x_timer, | 577 | .timer = &at91sam926x_timer, |
577 | .map_io = at91_map_io, | 578 | .map_io = at91_map_io, |
579 | .handle_irq = at91_aic_handle_irq, | ||
578 | .init_early = gsia18s_init_early, | 580 | .init_early = gsia18s_init_early, |
579 | .init_irq = at91_init_irq_default, | 581 | .init_irq = at91_init_irq_default, |
580 | .init_machine = gsia18s_board_init, | 582 | .init_machine = gsia18s_board_init, |
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c index f260657f32bc..64c1dbf88a07 100644 --- a/arch/arm/mach-at91/board-kafa.c +++ b/arch/arm/mach-at91/board-kafa.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <asm/mach/irq.h> | 35 | #include <asm/mach/irq.h> |
36 | 36 | ||
37 | #include <mach/board.h> | 37 | #include <mach/board.h> |
38 | #include <mach/at91_aic.h> | ||
38 | #include <mach/cpu.h> | 39 | #include <mach/cpu.h> |
39 | 40 | ||
40 | #include "generic.h" | 41 | #include "generic.h" |
@@ -93,6 +94,7 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA") | |||
93 | /* Maintainer: Sergei Sharonov */ | 94 | /* Maintainer: Sergei Sharonov */ |
94 | .timer = &at91rm9200_timer, | 95 | .timer = &at91rm9200_timer, |
95 | .map_io = at91_map_io, | 96 | .map_io = at91_map_io, |
97 | .handle_irq = at91_aic_handle_irq, | ||
96 | .init_early = kafa_init_early, | 98 | .init_early = kafa_init_early, |
97 | .init_irq = at91_init_irq_default, | 99 | .init_irq = at91_init_irq_default, |
98 | .init_machine = kafa_board_init, | 100 | .init_machine = kafa_board_init, |
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c index ba39db5482b9..5d96cb85175f 100644 --- a/arch/arm/mach-at91/board-kb9202.c +++ b/arch/arm/mach-at91/board-kb9202.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #include <mach/board.h> | 38 | #include <mach/board.h> |
39 | #include <mach/cpu.h> | 39 | #include <mach/cpu.h> |
40 | #include <mach/at91_aic.h> | ||
40 | #include <mach/at91rm9200_mc.h> | 41 | #include <mach/at91rm9200_mc.h> |
41 | #include <mach/at91_ramc.h> | 42 | #include <mach/at91_ramc.h> |
42 | 43 | ||
@@ -133,6 +134,7 @@ MACHINE_START(KB9200, "KB920x") | |||
133 | /* Maintainer: KwikByte, Inc. */ | 134 | /* Maintainer: KwikByte, Inc. */ |
134 | .timer = &at91rm9200_timer, | 135 | .timer = &at91rm9200_timer, |
135 | .map_io = at91_map_io, | 136 | .map_io = at91_map_io, |
137 | .handle_irq = at91_aic_handle_irq, | ||
136 | .init_early = kb9202_init_early, | 138 | .init_early = kb9202_init_early, |
137 | .init_irq = at91_init_irq_default, | 139 | .init_irq = at91_init_irq_default, |
138 | .init_machine = kb9202_board_init, | 140 | .init_machine = kb9202_board_init, |
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c index d2f4cc161766..18103c5d993c 100644 --- a/arch/arm/mach-at91/board-neocore926.c +++ b/arch/arm/mach-at91/board-neocore926.c | |||
@@ -45,6 +45,7 @@ | |||
45 | 45 | ||
46 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
47 | #include <mach/board.h> | 47 | #include <mach/board.h> |
48 | #include <mach/at91_aic.h> | ||
48 | #include <mach/at91sam9_smc.h> | 49 | #include <mach/at91sam9_smc.h> |
49 | 50 | ||
50 | #include "sam9_smc.h" | 51 | #include "sam9_smc.h" |
@@ -378,6 +379,7 @@ MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") | |||
378 | /* Maintainer: ADENEO */ | 379 | /* Maintainer: ADENEO */ |
379 | .timer = &at91sam926x_timer, | 380 | .timer = &at91sam926x_timer, |
380 | .map_io = at91_map_io, | 381 | .map_io = at91_map_io, |
382 | .handle_irq = at91_aic_handle_irq, | ||
381 | .init_early = neocore926_init_early, | 383 | .init_early = neocore926_init_early, |
382 | .init_irq = at91_init_irq_default, | 384 | .init_irq = at91_init_irq_default, |
383 | .init_machine = neocore926_board_init, | 385 | .init_machine = neocore926_board_init, |
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c index 7fe638342421..9ca3e32c54cb 100644 --- a/arch/arm/mach-at91/board-pcontrol-g20.c +++ b/arch/arm/mach-at91/board-pcontrol-g20.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
31 | 31 | ||
32 | #include <mach/board.h> | 32 | #include <mach/board.h> |
33 | #include <mach/at91_aic.h> | ||
33 | #include <mach/at91sam9_smc.h> | 34 | #include <mach/at91sam9_smc.h> |
34 | #include <mach/stamp9g20.h> | 35 | #include <mach/stamp9g20.h> |
35 | 36 | ||
@@ -218,6 +219,7 @@ MACHINE_START(PCONTROL_G20, "PControl G20") | |||
218 | /* Maintainer: pgsellmann@portner-elektronik.at */ | 219 | /* Maintainer: pgsellmann@portner-elektronik.at */ |
219 | .timer = &at91sam926x_timer, | 220 | .timer = &at91sam926x_timer, |
220 | .map_io = at91_map_io, | 221 | .map_io = at91_map_io, |
222 | .handle_irq = at91_aic_handle_irq, | ||
221 | .init_early = pcontrol_g20_init_early, | 223 | .init_early = pcontrol_g20_init_early, |
222 | .init_irq = at91_init_irq_default, | 224 | .init_irq = at91_init_irq_default, |
223 | .init_machine = pcontrol_g20_board_init, | 225 | .init_machine = pcontrol_g20_board_init, |
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c index b45c0a5d5ca7..127065504508 100644 --- a/arch/arm/mach-at91/board-picotux200.c +++ b/arch/arm/mach-at91/board-picotux200.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
39 | 39 | ||
40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
41 | #include <mach/at91_aic.h> | ||
41 | #include <mach/at91rm9200_mc.h> | 42 | #include <mach/at91rm9200_mc.h> |
42 | #include <mach/at91_ramc.h> | 43 | #include <mach/at91_ramc.h> |
43 | 44 | ||
@@ -120,6 +121,7 @@ MACHINE_START(PICOTUX2XX, "picotux 200") | |||
120 | /* Maintainer: Kleinhenz Elektronik GmbH */ | 121 | /* Maintainer: Kleinhenz Elektronik GmbH */ |
121 | .timer = &at91rm9200_timer, | 122 | .timer = &at91rm9200_timer, |
122 | .map_io = at91_map_io, | 123 | .map_io = at91_map_io, |
124 | .handle_irq = at91_aic_handle_irq, | ||
123 | .init_early = picotux200_init_early, | 125 | .init_early = picotux200_init_early, |
124 | .init_irq = at91_init_irq_default, | 126 | .init_irq = at91_init_irq_default, |
125 | .init_machine = picotux200_board_init, | 127 | .init_machine = picotux200_board_init, |
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c index 0c61bf0d272c..bf351e285422 100644 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ b/arch/arm/mach-at91/board-qil-a9260.c | |||
@@ -41,6 +41,7 @@ | |||
41 | 41 | ||
42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
43 | #include <mach/board.h> | 43 | #include <mach/board.h> |
44 | #include <mach/at91_aic.h> | ||
44 | #include <mach/at91sam9_smc.h> | 45 | #include <mach/at91sam9_smc.h> |
45 | #include <mach/at91_shdwc.h> | 46 | #include <mach/at91_shdwc.h> |
46 | 47 | ||
@@ -258,6 +259,7 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260") | |||
258 | /* Maintainer: calao-systems */ | 259 | /* Maintainer: calao-systems */ |
259 | .timer = &at91sam926x_timer, | 260 | .timer = &at91sam926x_timer, |
260 | .map_io = at91_map_io, | 261 | .map_io = at91_map_io, |
262 | .handle_irq = at91_aic_handle_irq, | ||
261 | .init_early = ek_init_early, | 263 | .init_early = ek_init_early, |
262 | .init_irq = at91_init_irq_default, | 264 | .init_irq = at91_init_irq_default, |
263 | .init_machine = ek_board_init, | 265 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c index afd7a4713766..cc2bf9796073 100644 --- a/arch/arm/mach-at91/board-rm9200dk.c +++ b/arch/arm/mach-at91/board-rm9200dk.c | |||
@@ -40,6 +40,7 @@ | |||
40 | 40 | ||
41 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
42 | #include <mach/board.h> | 42 | #include <mach/board.h> |
43 | #include <mach/at91_aic.h> | ||
43 | #include <mach/at91rm9200_mc.h> | 44 | #include <mach/at91rm9200_mc.h> |
44 | #include <mach/at91_ramc.h> | 45 | #include <mach/at91_ramc.h> |
45 | 46 | ||
@@ -223,6 +224,7 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") | |||
223 | /* Maintainer: SAN People/Atmel */ | 224 | /* Maintainer: SAN People/Atmel */ |
224 | .timer = &at91rm9200_timer, | 225 | .timer = &at91rm9200_timer, |
225 | .map_io = at91_map_io, | 226 | .map_io = at91_map_io, |
227 | .handle_irq = at91_aic_handle_irq, | ||
226 | .init_early = dk_init_early, | 228 | .init_early = dk_init_early, |
227 | .init_irq = at91_init_irq_default, | 229 | .init_irq = at91_init_irq_default, |
228 | .init_machine = dk_board_init, | 230 | .init_machine = dk_board_init, |
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c index 2b15b8adec4c..62e19e64c9d3 100644 --- a/arch/arm/mach-at91/board-rm9200ek.c +++ b/arch/arm/mach-at91/board-rm9200ek.c | |||
@@ -40,6 +40,7 @@ | |||
40 | 40 | ||
41 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
42 | #include <mach/board.h> | 42 | #include <mach/board.h> |
43 | #include <mach/at91_aic.h> | ||
43 | #include <mach/at91rm9200_mc.h> | 44 | #include <mach/at91rm9200_mc.h> |
44 | #include <mach/at91_ramc.h> | 45 | #include <mach/at91_ramc.h> |
45 | 46 | ||
@@ -190,6 +191,7 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") | |||
190 | /* Maintainer: SAN People/Atmel */ | 191 | /* Maintainer: SAN People/Atmel */ |
191 | .timer = &at91rm9200_timer, | 192 | .timer = &at91rm9200_timer, |
192 | .map_io = at91_map_io, | 193 | .map_io = at91_map_io, |
194 | .handle_irq = at91_aic_handle_irq, | ||
193 | .init_early = ek_init_early, | 195 | .init_early = ek_init_early, |
194 | .init_irq = at91_init_irq_default, | 196 | .init_irq = at91_init_irq_default, |
195 | .init_machine = ek_board_init, | 197 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c index 24ab9be7510f..c3b43aefdb75 100644 --- a/arch/arm/mach-at91/board-rsi-ews.c +++ b/arch/arm/mach-at91/board-rsi-ews.c | |||
@@ -26,6 +26,7 @@ | |||
26 | 26 | ||
27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
29 | #include <mach/at91_aic.h> | ||
29 | 30 | ||
30 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
31 | 32 | ||
@@ -225,6 +226,7 @@ MACHINE_START(RSI_EWS, "RSI EWS") | |||
225 | /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */ | 226 | /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */ |
226 | .timer = &at91rm9200_timer, | 227 | .timer = &at91rm9200_timer, |
227 | .map_io = at91_map_io, | 228 | .map_io = at91_map_io, |
229 | .handle_irq = at91_aic_handle_irq, | ||
228 | .init_early = rsi_ews_init_early, | 230 | .init_early = rsi_ews_init_early, |
229 | .init_irq = at91_init_irq_default, | 231 | .init_irq = at91_init_irq_default, |
230 | .init_machine = rsi_ews_board_init, | 232 | .init_machine = rsi_ews_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c index cdd21f2595d2..7bf6da70d7d5 100644 --- a/arch/arm/mach-at91/board-sam9-l9260.c +++ b/arch/arm/mach-at91/board-sam9-l9260.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
39 | 39 | ||
40 | #include <mach/board.h> | 40 | #include <mach/board.h> |
41 | #include <mach/at91_aic.h> | ||
41 | #include <mach/at91sam9_smc.h> | 42 | #include <mach/at91sam9_smc.h> |
42 | 43 | ||
43 | #include "sam9_smc.h" | 44 | #include "sam9_smc.h" |
@@ -202,6 +203,7 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") | |||
202 | /* Maintainer: Olimex */ | 203 | /* Maintainer: Olimex */ |
203 | .timer = &at91sam926x_timer, | 204 | .timer = &at91sam926x_timer, |
204 | .map_io = at91_map_io, | 205 | .map_io = at91_map_io, |
206 | .handle_irq = at91_aic_handle_irq, | ||
205 | .init_early = ek_init_early, | 207 | .init_early = ek_init_early, |
206 | .init_irq = at91_init_irq_default, | 208 | .init_irq = at91_init_irq_default, |
207 | .init_machine = ek_board_init, | 209 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c index 7b3c3913551a..889c1bf71eb5 100644 --- a/arch/arm/mach-at91/board-sam9260ek.c +++ b/arch/arm/mach-at91/board-sam9260ek.c | |||
@@ -42,6 +42,7 @@ | |||
42 | 42 | ||
43 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
45 | #include <mach/at91_aic.h> | ||
45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
46 | #include <mach/at91_shdwc.h> | 47 | #include <mach/at91_shdwc.h> |
47 | #include <mach/system_rev.h> | 48 | #include <mach/system_rev.h> |
@@ -344,6 +345,7 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") | |||
344 | /* Maintainer: Atmel */ | 345 | /* Maintainer: Atmel */ |
345 | .timer = &at91sam926x_timer, | 346 | .timer = &at91sam926x_timer, |
346 | .map_io = at91_map_io, | 347 | .map_io = at91_map_io, |
348 | .handle_irq = at91_aic_handle_irq, | ||
347 | .init_early = ek_init_early, | 349 | .init_early = ek_init_early, |
348 | .init_irq = at91_init_irq_default, | 350 | .init_irq = at91_init_irq_default, |
349 | .init_machine = ek_board_init, | 351 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index 2736453821b0..2269be5fa384 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
@@ -46,6 +46,7 @@ | |||
46 | 46 | ||
47 | #include <mach/hardware.h> | 47 | #include <mach/hardware.h> |
48 | #include <mach/board.h> | 48 | #include <mach/board.h> |
49 | #include <mach/at91_aic.h> | ||
49 | #include <mach/at91sam9_smc.h> | 50 | #include <mach/at91sam9_smc.h> |
50 | #include <mach/at91_shdwc.h> | 51 | #include <mach/at91_shdwc.h> |
51 | #include <mach/system_rev.h> | 52 | #include <mach/system_rev.h> |
@@ -615,6 +616,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") | |||
615 | /* Maintainer: Atmel */ | 616 | /* Maintainer: Atmel */ |
616 | .timer = &at91sam926x_timer, | 617 | .timer = &at91sam926x_timer, |
617 | .map_io = at91_map_io, | 618 | .map_io = at91_map_io, |
619 | .handle_irq = at91_aic_handle_irq, | ||
618 | .init_early = ek_init_early, | 620 | .init_early = ek_init_early, |
619 | .init_irq = at91_init_irq_default, | 621 | .init_irq = at91_init_irq_default, |
620 | .init_machine = ek_board_init, | 622 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 983cb98d2465..82adf581afc2 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
@@ -45,6 +45,7 @@ | |||
45 | 45 | ||
46 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
47 | #include <mach/board.h> | 47 | #include <mach/board.h> |
48 | #include <mach/at91_aic.h> | ||
48 | #include <mach/at91sam9_smc.h> | 49 | #include <mach/at91sam9_smc.h> |
49 | #include <mach/at91_shdwc.h> | 50 | #include <mach/at91_shdwc.h> |
50 | #include <mach/system_rev.h> | 51 | #include <mach/system_rev.h> |
@@ -443,6 +444,7 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") | |||
443 | /* Maintainer: Atmel */ | 444 | /* Maintainer: Atmel */ |
444 | .timer = &at91sam926x_timer, | 445 | .timer = &at91sam926x_timer, |
445 | .map_io = at91_map_io, | 446 | .map_io = at91_map_io, |
447 | .handle_irq = at91_aic_handle_irq, | ||
446 | .init_early = ek_init_early, | 448 | .init_early = ek_init_early, |
447 | .init_irq = at91_init_irq_default, | 449 | .init_irq = at91_init_irq_default, |
448 | .init_machine = ek_board_init, | 450 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 6860d3451100..4ea4ee00364b 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include <asm/mach/irq.h> | 44 | #include <asm/mach/irq.h> |
45 | 45 | ||
46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
47 | #include <mach/at91_aic.h> | ||
47 | #include <mach/at91sam9_smc.h> | 48 | #include <mach/at91sam9_smc.h> |
48 | #include <mach/system_rev.h> | 49 | #include <mach/system_rev.h> |
49 | 50 | ||
@@ -413,6 +414,7 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") | |||
413 | /* Maintainer: Atmel */ | 414 | /* Maintainer: Atmel */ |
414 | .timer = &at91sam926x_timer, | 415 | .timer = &at91sam926x_timer, |
415 | .map_io = at91_map_io, | 416 | .map_io = at91_map_io, |
417 | .handle_irq = at91_aic_handle_irq, | ||
416 | .init_early = ek_init_early, | 418 | .init_early = ek_init_early, |
417 | .init_irq = at91_init_irq_default, | 419 | .init_irq = at91_init_irq_default, |
418 | .init_machine = ek_board_init, | 420 | .init_machine = ek_board_init, |
@@ -422,6 +424,7 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod") | |||
422 | /* Maintainer: Atmel */ | 424 | /* Maintainer: Atmel */ |
423 | .timer = &at91sam926x_timer, | 425 | .timer = &at91sam926x_timer, |
424 | .map_io = at91_map_io, | 426 | .map_io = at91_map_io, |
427 | .handle_irq = at91_aic_handle_irq, | ||
425 | .init_early = ek_init_early, | 428 | .init_early = ek_init_early, |
426 | .init_irq = at91_init_irq_default, | 429 | .init_irq = at91_init_irq_default, |
427 | .init_machine = ek_board_init, | 430 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 63163dc7df46..3d48ec154685 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c | |||
@@ -43,6 +43,7 @@ | |||
43 | #include <asm/mach/irq.h> | 43 | #include <asm/mach/irq.h> |
44 | 44 | ||
45 | #include <mach/board.h> | 45 | #include <mach/board.h> |
46 | #include <mach/at91_aic.h> | ||
46 | #include <mach/at91sam9_smc.h> | 47 | #include <mach/at91sam9_smc.h> |
47 | #include <mach/at91_shdwc.h> | 48 | #include <mach/at91_shdwc.h> |
48 | #include <mach/system_rev.h> | 49 | #include <mach/system_rev.h> |
@@ -503,6 +504,7 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK") | |||
503 | /* Maintainer: Atmel */ | 504 | /* Maintainer: Atmel */ |
504 | .timer = &at91sam926x_timer, | 505 | .timer = &at91sam926x_timer, |
505 | .map_io = at91_map_io, | 506 | .map_io = at91_map_io, |
507 | .handle_irq = at91_aic_handle_irq, | ||
506 | .init_early = ek_init_early, | 508 | .init_early = ek_init_early, |
507 | .init_irq = at91_init_irq_default, | 509 | .init_irq = at91_init_irq_default, |
508 | .init_machine = ek_board_init, | 510 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index be3239f13daa..e7dc3ead7045 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
@@ -31,6 +31,7 @@ | |||
31 | 31 | ||
32 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
33 | #include <mach/board.h> | 33 | #include <mach/board.h> |
34 | #include <mach/at91_aic.h> | ||
34 | #include <mach/at91sam9_smc.h> | 35 | #include <mach/at91sam9_smc.h> |
35 | #include <mach/at91_shdwc.h> | 36 | #include <mach/at91_shdwc.h> |
36 | 37 | ||
@@ -319,6 +320,7 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") | |||
319 | /* Maintainer: Atmel */ | 320 | /* Maintainer: Atmel */ |
320 | .timer = &at91sam926x_timer, | 321 | .timer = &at91sam926x_timer, |
321 | .map_io = at91_map_io, | 322 | .map_io = at91_map_io, |
323 | .handle_irq = at91_aic_handle_irq, | ||
322 | .init_early = ek_init_early, | 324 | .init_early = ek_init_early, |
323 | .init_irq = at91_init_irq_default, | 325 | .init_irq = at91_init_irq_default, |
324 | .init_machine = ek_board_init, | 326 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c index 9d446f1bb45f..a4e031a039fd 100644 --- a/arch/arm/mach-at91/board-snapper9260.c +++ b/arch/arm/mach-at91/board-snapper9260.c | |||
@@ -33,6 +33,7 @@ | |||
33 | 33 | ||
34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
35 | #include <mach/board.h> | 35 | #include <mach/board.h> |
36 | #include <mach/at91_aic.h> | ||
36 | #include <mach/at91sam9_smc.h> | 37 | #include <mach/at91sam9_smc.h> |
37 | 38 | ||
38 | #include "sam9_smc.h" | 39 | #include "sam9_smc.h" |
@@ -178,6 +179,7 @@ static void __init snapper9260_board_init(void) | |||
178 | MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") | 179 | MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") |
179 | .timer = &at91sam926x_timer, | 180 | .timer = &at91sam926x_timer, |
180 | .map_io = at91_map_io, | 181 | .map_io = at91_map_io, |
182 | .handle_irq = at91_aic_handle_irq, | ||
181 | .init_early = snapper9260_init_early, | 183 | .init_early = snapper9260_init_early, |
182 | .init_irq = at91_init_irq_default, | 184 | .init_irq = at91_init_irq_default, |
183 | .init_machine = snapper9260_board_init, | 185 | .init_machine = snapper9260_board_init, |
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c index ee86f9d7ee72..29eae1626bf7 100644 --- a/arch/arm/mach-at91/board-stamp9g20.c +++ b/arch/arm/mach-at91/board-stamp9g20.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | 27 | ||
28 | #include <mach/board.h> | 28 | #include <mach/board.h> |
29 | #include <mach/at91_aic.h> | ||
29 | #include <mach/at91sam9_smc.h> | 30 | #include <mach/at91sam9_smc.h> |
30 | 31 | ||
31 | #include "sam9_smc.h" | 32 | #include "sam9_smc.h" |
@@ -287,6 +288,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20") | |||
287 | /* Maintainer: taskit GmbH */ | 288 | /* Maintainer: taskit GmbH */ |
288 | .timer = &at91sam926x_timer, | 289 | .timer = &at91sam926x_timer, |
289 | .map_io = at91_map_io, | 290 | .map_io = at91_map_io, |
291 | .handle_irq = at91_aic_handle_irq, | ||
290 | .init_early = stamp9g20_init_early, | 292 | .init_early = stamp9g20_init_early, |
291 | .init_irq = at91_init_irq_default, | 293 | .init_irq = at91_init_irq_default, |
292 | .init_machine = portuxg20_board_init, | 294 | .init_machine = portuxg20_board_init, |
@@ -296,6 +298,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20") | |||
296 | /* Maintainer: taskit GmbH */ | 298 | /* Maintainer: taskit GmbH */ |
297 | .timer = &at91sam926x_timer, | 299 | .timer = &at91sam926x_timer, |
298 | .map_io = at91_map_io, | 300 | .map_io = at91_map_io, |
301 | .handle_irq = at91_aic_handle_irq, | ||
299 | .init_early = stamp9g20_init_early, | 302 | .init_early = stamp9g20_init_early, |
300 | .init_irq = at91_init_irq_default, | 303 | .init_irq = at91_init_irq_default, |
301 | .init_machine = stamp9g20evb_board_init, | 304 | .init_machine = stamp9g20evb_board_init, |
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c index 95393fcaf199..c1476b9fe7b9 100644 --- a/arch/arm/mach-at91/board-usb-a926x.c +++ b/arch/arm/mach-at91/board-usb-a926x.c | |||
@@ -42,6 +42,7 @@ | |||
42 | 42 | ||
43 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
44 | #include <mach/board.h> | 44 | #include <mach/board.h> |
45 | #include <mach/at91_aic.h> | ||
45 | #include <mach/at91sam9_smc.h> | 46 | #include <mach/at91sam9_smc.h> |
46 | #include <mach/at91_shdwc.h> | 47 | #include <mach/at91_shdwc.h> |
47 | 48 | ||
@@ -358,6 +359,7 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263") | |||
358 | /* Maintainer: calao-systems */ | 359 | /* Maintainer: calao-systems */ |
359 | .timer = &at91sam926x_timer, | 360 | .timer = &at91sam926x_timer, |
360 | .map_io = at91_map_io, | 361 | .map_io = at91_map_io, |
362 | .handle_irq = at91_aic_handle_irq, | ||
361 | .init_early = ek_init_early, | 363 | .init_early = ek_init_early, |
362 | .init_irq = at91_init_irq_default, | 364 | .init_irq = at91_init_irq_default, |
363 | .init_machine = ek_board_init, | 365 | .init_machine = ek_board_init, |
@@ -367,6 +369,7 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260") | |||
367 | /* Maintainer: calao-systems */ | 369 | /* Maintainer: calao-systems */ |
368 | .timer = &at91sam926x_timer, | 370 | .timer = &at91sam926x_timer, |
369 | .map_io = at91_map_io, | 371 | .map_io = at91_map_io, |
372 | .handle_irq = at91_aic_handle_irq, | ||
370 | .init_early = ek_init_early, | 373 | .init_early = ek_init_early, |
371 | .init_irq = at91_init_irq_default, | 374 | .init_irq = at91_init_irq_default, |
372 | .init_machine = ek_board_init, | 375 | .init_machine = ek_board_init, |
@@ -376,6 +379,7 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0") | |||
376 | /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ | 379 | /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */ |
377 | .timer = &at91sam926x_timer, | 380 | .timer = &at91sam926x_timer, |
378 | .map_io = at91_map_io, | 381 | .map_io = at91_map_io, |
382 | .handle_irq = at91_aic_handle_irq, | ||
379 | .init_early = ek_init_early, | 383 | .init_early = ek_init_early, |
380 | .init_irq = at91_init_irq_default, | 384 | .init_irq = at91_init_irq_default, |
381 | .init_machine = ek_board_init, | 385 | .init_machine = ek_board_init, |
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c index d56665ea4b55..516d340549d8 100644 --- a/arch/arm/mach-at91/board-yl-9200.c +++ b/arch/arm/mach-at91/board-yl-9200.c | |||
@@ -44,6 +44,7 @@ | |||
44 | 44 | ||
45 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
46 | #include <mach/board.h> | 46 | #include <mach/board.h> |
47 | #include <mach/at91_aic.h> | ||
47 | #include <mach/at91rm9200_mc.h> | 48 | #include <mach/at91rm9200_mc.h> |
48 | #include <mach/at91_ramc.h> | 49 | #include <mach/at91_ramc.h> |
49 | #include <mach/cpu.h> | 50 | #include <mach/cpu.h> |
@@ -590,6 +591,7 @@ MACHINE_START(YL9200, "uCdragon YL-9200") | |||
590 | /* Maintainer: S.Birtles */ | 591 | /* Maintainer: S.Birtles */ |
591 | .timer = &at91rm9200_timer, | 592 | .timer = &at91rm9200_timer, |
592 | .map_io = at91_map_io, | 593 | .map_io = at91_map_io, |
594 | .handle_irq = at91_aic_handle_irq, | ||
593 | .init_early = yl9200_init_early, | 595 | .init_early = yl9200_init_early, |
594 | .init_irq = at91_init_irq_default, | 596 | .init_irq = at91_init_irq_default, |
595 | .init_machine = yl9200_board_init, | 597 | .init_machine = yl9200_board_init, |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 0a60bf837037..f49650677653 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
@@ -29,6 +29,8 @@ extern void __init at91x40_init_interrupts(unsigned int priority[]); | |||
29 | extern void __init at91_aic_init(unsigned int priority[]); | 29 | extern void __init at91_aic_init(unsigned int priority[]); |
30 | extern int __init at91_aic_of_init(struct device_node *node, | 30 | extern int __init at91_aic_of_init(struct device_node *node, |
31 | struct device_node *parent); | 31 | struct device_node *parent); |
32 | extern int __init at91_aic5_of_init(struct device_node *node, | ||
33 | struct device_node *parent); | ||
32 | 34 | ||
33 | 35 | ||
34 | /* Timer */ | 36 | /* Timer */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 325837a264c9..be42cf0e74bd 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
@@ -26,6 +26,8 @@ | |||
26 | #include <linux/of_irq.h> | 26 | #include <linux/of_irq.h> |
27 | #include <linux/of_gpio.h> | 27 | #include <linux/of_gpio.h> |
28 | 28 | ||
29 | #include <asm/mach/irq.h> | ||
30 | |||
29 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
30 | #include <mach/at91_pio.h> | 32 | #include <mach/at91_pio.h> |
31 | 33 | ||
@@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = { | |||
585 | 587 | ||
586 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | 588 | static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) |
587 | { | 589 | { |
590 | struct irq_chip *chip = irq_desc_get_chip(desc); | ||
588 | struct irq_data *idata = irq_desc_get_irq_data(desc); | 591 | struct irq_data *idata = irq_desc_get_irq_data(desc); |
589 | struct irq_chip *chip = irq_data_get_irq_chip(idata); | ||
590 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); | 592 | struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); |
591 | void __iomem *pio = at91_gpio->regbase; | 593 | void __iomem *pio = at91_gpio->regbase; |
592 | unsigned long isr; | 594 | unsigned long isr; |
593 | int n; | 595 | int n; |
594 | 596 | ||
595 | /* temporarily mask (level sensitive) parent IRQ */ | 597 | chained_irq_enter(chip, desc); |
596 | chip->irq_ack(idata); | ||
597 | for (;;) { | 598 | for (;;) { |
598 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. | 599 | /* Reading ISR acks pending (edge triggered) GPIO interrupts. |
599 | * When there none are pending, we're finished unless we need | 600 | * When there none are pending, we're finished unless we need |
@@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
614 | n = find_next_bit(&isr, BITS_PER_LONG, n + 1); | 615 | n = find_next_bit(&isr, BITS_PER_LONG, n + 1); |
615 | } | 616 | } |
616 | } | 617 | } |
617 | chip->irq_unmask(idata); | 618 | chained_irq_exit(chip, desc); |
618 | /* now it may re-trigger */ | 619 | /* now it may re-trigger */ |
619 | } | 620 | } |
620 | 621 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h index 3045781c473f..eaea66197fa1 100644 --- a/arch/arm/mach-at91/include/mach/at91_aic.h +++ b/arch/arm/mach-at91/include/mach/at91_aic.h | |||
@@ -23,12 +23,23 @@ extern void __iomem *at91_aic_base; | |||
23 | __raw_readl(at91_aic_base + field) | 23 | __raw_readl(at91_aic_base + field) |
24 | 24 | ||
25 | #define at91_aic_write(field, value) \ | 25 | #define at91_aic_write(field, value) \ |
26 | __raw_writel(value, at91_aic_base + field); | 26 | __raw_writel(value, at91_aic_base + field) |
27 | #else | 27 | #else |
28 | .extern at91_aic_base | 28 | .extern at91_aic_base |
29 | #endif | 29 | #endif |
30 | 30 | ||
31 | /* Number of irq lines managed by AIC */ | ||
32 | #define NR_AIC_IRQS 32 | ||
33 | #define NR_AIC5_IRQS 128 | ||
34 | |||
35 | #define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */ | ||
36 | #define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */ | ||
37 | |||
38 | #define AT91_AIC_IRQ_MIN_PRIORITY 0 | ||
39 | #define AT91_AIC_IRQ_MAX_PRIORITY 7 | ||
40 | |||
31 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ | 41 | #define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */ |
42 | #define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */ | ||
32 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ | 43 | #define AT91_AIC_PRIOR (7 << 0) /* Priority Level */ |
33 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ | 44 | #define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */ |
34 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) | 45 | #define AT91_AIC_SRCTYPE_LOW (0 << 5) |
@@ -37,29 +48,52 @@ extern void __iomem *at91_aic_base; | |||
37 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) | 48 | #define AT91_AIC_SRCTYPE_RISING (3 << 5) |
38 | 49 | ||
39 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ | 50 | #define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */ |
51 | #define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */ | ||
40 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ | 52 | #define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */ |
53 | #define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */ | ||
41 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ | 54 | #define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */ |
55 | #define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */ | ||
42 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ | 56 | #define AT91_AIC_ISR 0x108 /* Interrupt Status Register */ |
57 | #define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */ | ||
43 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ | 58 | #define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */ |
44 | 59 | ||
45 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ | 60 | #define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */ |
61 | #define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */ | ||
62 | #define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */ | ||
63 | #define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */ | ||
64 | #define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */ | ||
46 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ | 65 | #define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */ |
66 | #define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */ | ||
47 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ | 67 | #define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */ |
68 | #define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */ | ||
48 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ | 69 | #define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */ |
49 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ | 70 | #define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */ |
50 | 71 | ||
51 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ | 72 | #define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */ |
73 | #define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */ | ||
52 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ | 74 | #define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */ |
75 | #define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */ | ||
53 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ | 76 | #define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */ |
77 | #define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */ | ||
54 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ | 78 | #define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */ |
79 | #define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */ | ||
55 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ | 80 | #define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */ |
81 | #define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */ | ||
56 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ | 82 | #define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */ |
83 | #define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */ | ||
57 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ | 84 | #define AT91_AIC_DCR 0x138 /* Debug Control Register */ |
85 | #define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */ | ||
58 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ | 86 | #define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */ |
59 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ | 87 | #define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */ |
60 | 88 | ||
61 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ | 89 | #define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */ |
90 | #define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */ | ||
62 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ | 91 | #define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */ |
92 | #define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */ | ||
63 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ | 93 | #define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */ |
94 | #define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */ | ||
95 | |||
96 | void at91_aic_handle_irq(struct pt_regs *regs); | ||
97 | void at91_aic5_handle_irq(struct pt_regs *regs); | ||
64 | 98 | ||
65 | #endif | 99 | #endif |
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h deleted file mode 100644 index 2f6ba0c5636e..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_spi.h +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91_spi.h | ||
3 | * | ||
4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
5 | * Copyright (C) SAN People | ||
6 | * | ||
7 | * Serial Peripheral Interface (SPI) registers. | ||
8 | * Based on AT91RM9200 datasheet revision E. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifndef AT91_SPI_H | ||
17 | #define AT91_SPI_H | ||
18 | |||
19 | #define AT91_SPI_CR 0x00 /* Control Register */ | ||
20 | #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ | ||
21 | #define AT91_SPI_SPIDIS (1 << 1) /* SPI Disable */ | ||
22 | #define AT91_SPI_SWRST (1 << 7) /* SPI Software Reset */ | ||
23 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
24 | |||
25 | #define AT91_SPI_MR 0x04 /* Mode Register */ | ||
26 | #define AT91_SPI_MSTR (1 << 0) /* Master/Slave Mode */ | ||
27 | #define AT91_SPI_PS (1 << 1) /* Peripheral Select */ | ||
28 | #define AT91_SPI_PS_FIXED (0 << 1) | ||
29 | #define AT91_SPI_PS_VARIABLE (1 << 1) | ||
30 | #define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */ | ||
31 | #define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */ | ||
32 | #define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */ | ||
33 | #define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */ | ||
34 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
35 | #define AT91_SPI_DLYBCS (0xff << 24) /* Delay Between Chip Selects */ | ||
36 | |||
37 | #define AT91_SPI_RDR 0x08 /* Receive Data Register */ | ||
38 | #define AT91_SPI_RD (0xffff << 0) /* Receive Data */ | ||
39 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
40 | |||
41 | #define AT91_SPI_TDR 0x0c /* Transmit Data Register */ | ||
42 | #define AT91_SPI_TD (0xffff << 0) /* Transmit Data */ | ||
43 | #define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */ | ||
44 | #define AT91_SPI_LASTXFER (1 << 24) /* Last Transfer [SAM9261 only] */ | ||
45 | |||
46 | #define AT91_SPI_SR 0x10 /* Status Register */ | ||
47 | #define AT91_SPI_RDRF (1 << 0) /* Receive Data Register Full */ | ||
48 | #define AT91_SPI_TDRE (1 << 1) /* Transmit Data Register Full */ | ||
49 | #define AT91_SPI_MODF (1 << 2) /* Mode Fault Error */ | ||
50 | #define AT91_SPI_OVRES (1 << 3) /* Overrun Error Status */ | ||
51 | #define AT91_SPI_ENDRX (1 << 4) /* End of RX buffer */ | ||
52 | #define AT91_SPI_ENDTX (1 << 5) /* End of TX buffer */ | ||
53 | #define AT91_SPI_RXBUFF (1 << 6) /* RX Buffer Full */ | ||
54 | #define AT91_SPI_TXBUFE (1 << 7) /* TX Buffer Empty */ | ||
55 | #define AT91_SPI_NSSR (1 << 8) /* NSS Rising [SAM9261 only] */ | ||
56 | #define AT91_SPI_TXEMPTY (1 << 9) /* Transmission Register Empty [SAM9261 only] */ | ||
57 | #define AT91_SPI_SPIENS (1 << 16) /* SPI Enable Status */ | ||
58 | |||
59 | #define AT91_SPI_IER 0x14 /* Interrupt Enable Register */ | ||
60 | #define AT91_SPI_IDR 0x18 /* Interrupt Disable Register */ | ||
61 | #define AT91_SPI_IMR 0x1c /* Interrupt Mask Register */ | ||
62 | |||
63 | #define AT91_SPI_CSR(n) (0x30 + ((n) * 4)) /* Chip Select Registers 0-3 */ | ||
64 | #define AT91_SPI_CPOL (1 << 0) /* Clock Polarity */ | ||
65 | #define AT91_SPI_NCPHA (1 << 1) /* Clock Phase */ | ||
66 | #define AT91_SPI_CSAAT (1 << 3) /* Chip Select Active After Transfer [SAM9261 only] */ | ||
67 | #define AT91_SPI_BITS (0xf << 4) /* Bits Per Transfer */ | ||
68 | #define AT91_SPI_BITS_8 (0 << 4) | ||
69 | #define AT91_SPI_BITS_9 (1 << 4) | ||
70 | #define AT91_SPI_BITS_10 (2 << 4) | ||
71 | #define AT91_SPI_BITS_11 (3 << 4) | ||
72 | #define AT91_SPI_BITS_12 (4 << 4) | ||
73 | #define AT91_SPI_BITS_13 (5 << 4) | ||
74 | #define AT91_SPI_BITS_14 (6 << 4) | ||
75 | #define AT91_SPI_BITS_15 (7 << 4) | ||
76 | #define AT91_SPI_BITS_16 (8 << 4) | ||
77 | #define AT91_SPI_SCBR (0xff << 8) /* Serial Clock Baud Rate */ | ||
78 | #define AT91_SPI_DLYBS (0xff << 16) /* Delay before SPCK */ | ||
79 | #define AT91_SPI_DLYBCT (0xff << 24) /* Delay between Consecutive Transfers */ | ||
80 | |||
81 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h deleted file mode 100644 index a81114c11c74..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_ssc.h +++ /dev/null | |||
@@ -1,106 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91_ssc.h | ||
3 | * | ||
4 | * Copyright (C) SAN People | ||
5 | * | ||
6 | * Serial Synchronous Controller (SSC) registers. | ||
7 | * Based on AT91RM9200 datasheet revision E. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | */ | ||
14 | |||
15 | #ifndef AT91_SSC_H | ||
16 | #define AT91_SSC_H | ||
17 | |||
18 | #define AT91_SSC_CR 0x00 /* Control Register */ | ||
19 | #define AT91_SSC_RXEN (1 << 0) /* Receive Enable */ | ||
20 | #define AT91_SSC_RXDIS (1 << 1) /* Receive Disable */ | ||
21 | #define AT91_SSC_TXEN (1 << 8) /* Transmit Enable */ | ||
22 | #define AT91_SSC_TXDIS (1 << 9) /* Transmit Disable */ | ||
23 | #define AT91_SSC_SWRST (1 << 15) /* Software Reset */ | ||
24 | |||
25 | #define AT91_SSC_CMR 0x04 /* Clock Mode Register */ | ||
26 | #define AT91_SSC_CMR_DIV (0xfff << 0) /* Clock Divider */ | ||
27 | |||
28 | #define AT91_SSC_RCMR 0x10 /* Receive Clock Mode Register */ | ||
29 | #define AT91_SSC_CKS (3 << 0) /* Clock Selection */ | ||
30 | #define AT91_SSC_CKS_DIV (0 << 0) | ||
31 | #define AT91_SSC_CKS_CLOCK (1 << 0) | ||
32 | #define AT91_SSC_CKS_PIN (2 << 0) | ||
33 | #define AT91_SSC_CKO (7 << 2) /* Clock Output Mode Selection */ | ||
34 | #define AT91_SSC_CKO_NONE (0 << 2) | ||
35 | #define AT91_SSC_CKO_CONTINUOUS (1 << 2) | ||
36 | #define AT91_SSC_CKI (1 << 5) /* Clock Inversion */ | ||
37 | #define AT91_SSC_CKI_FALLING (0 << 5) | ||
38 | #define AT91_SSC_CK_RISING (1 << 5) | ||
39 | #define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */ | ||
40 | #define AT91_SSC_CKG_NONE (0 << 6) | ||
41 | #define AT91_SSC_CKG_RFLOW (1 << 6) | ||
42 | #define AT91_SSC_CKG_RFHIGH (2 << 6) | ||
43 | #define AT91_SSC_START (0xf << 8) /* Start Selection */ | ||
44 | #define AT91_SSC_START_CONTINUOUS (0 << 8) | ||
45 | #define AT91_SSC_START_TX_RX (1 << 8) | ||
46 | #define AT91_SSC_START_LOW_RF (2 << 8) | ||
47 | #define AT91_SSC_START_HIGH_RF (3 << 8) | ||
48 | #define AT91_SSC_START_FALLING_RF (4 << 8) | ||
49 | #define AT91_SSC_START_RISING_RF (5 << 8) | ||
50 | #define AT91_SSC_START_LEVEL_RF (6 << 8) | ||
51 | #define AT91_SSC_START_EDGE_RF (7 << 8) | ||
52 | #define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */ | ||
53 | #define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */ | ||
54 | #define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */ | ||
55 | |||
56 | #define AT91_SSC_RFMR 0x14 /* Receive Frame Mode Register */ | ||
57 | #define AT91_SSC_DATALEN (0x1f << 0) /* Data Length */ | ||
58 | #define AT91_SSC_LOOP (1 << 5) /* Loop Mode */ | ||
59 | #define AT91_SSC_MSBF (1 << 7) /* Most Significant Bit First */ | ||
60 | #define AT91_SSC_DATNB (0xf << 8) /* Data Number per Frame */ | ||
61 | #define AT91_SSC_FSLEN (0xf << 16) /* Frame Sync Length */ | ||
62 | #define AT91_SSC_FSOS (7 << 20) /* Frame Sync Output Selection */ | ||
63 | #define AT91_SSC_FSOS_NONE (0 << 20) | ||
64 | #define AT91_SSC_FSOS_NEGATIVE (1 << 20) | ||
65 | #define AT91_SSC_FSOS_POSITIVE (2 << 20) | ||
66 | #define AT91_SSC_FSOS_LOW (3 << 20) | ||
67 | #define AT91_SSC_FSOS_HIGH (4 << 20) | ||
68 | #define AT91_SSC_FSOS_TOGGLE (5 << 20) | ||
69 | #define AT91_SSC_FSEDGE (1 << 24) /* Frame Sync Edge Detection */ | ||
70 | #define AT91_SSC_FSEDGE_POSITIVE (0 << 24) | ||
71 | #define AT91_SSC_FSEDGE_NEGATIVE (1 << 24) | ||
72 | |||
73 | #define AT91_SSC_TCMR 0x18 /* Transmit Clock Mode Register */ | ||
74 | #define AT91_SSC_TFMR 0x1c /* Transmit Fram Mode Register */ | ||
75 | #define AT91_SSC_DATDEF (1 << 5) /* Data Default Value */ | ||
76 | #define AT91_SSC_FSDEN (1 << 23) /* Frame Sync Data Enable */ | ||
77 | |||
78 | #define AT91_SSC_RHR 0x20 /* Receive Holding Register */ | ||
79 | #define AT91_SSC_THR 0x24 /* Transmit Holding Register */ | ||
80 | #define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */ | ||
81 | #define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */ | ||
82 | |||
83 | #define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */ | ||
84 | #define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */ | ||
85 | |||
86 | #define AT91_SSC_SR 0x40 /* Status Register */ | ||
87 | #define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */ | ||
88 | #define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */ | ||
89 | #define AT91_SSC_ENDTX (1 << 2) /* End of Transmission */ | ||
90 | #define AT91_SSC_TXBUFE (1 << 3) /* Transmit Buffer Empty */ | ||
91 | #define AT91_SSC_RXRDY (1 << 4) /* Receive Ready */ | ||
92 | #define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */ | ||
93 | #define AT91_SSC_ENDRX (1 << 6) /* End of Reception */ | ||
94 | #define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */ | ||
95 | #define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */ | ||
96 | #define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */ | ||
97 | #define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */ | ||
98 | #define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */ | ||
99 | #define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */ | ||
100 | #define AT91_SSC_RXENA (1 << 17) /* Receive Enable */ | ||
101 | |||
102 | #define AT91_SSC_IER 0x44 /* Interrupt Enable Register */ | ||
103 | #define AT91_SSC_IDR 0x48 /* Interrupt Disable Register */ | ||
104 | #define AT91_SSC_IMR 0x4c /* Interrupt Mask Register */ | ||
105 | |||
106 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S deleted file mode 100644 index 903bf205a333..000000000000 --- a/arch/arm/mach-at91/include/mach/entry-macro.S +++ /dev/null | |||
@@ -1,27 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Copyright (C) 2003-2005 SAN People | ||
5 | * | ||
6 | * Low-level IRQ helper macros for AT91RM9200 platforms | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #include <mach/hardware.h> | ||
14 | #include <mach/at91_aic.h> | ||
15 | |||
16 | .macro get_irqnr_preamble, base, tmp | ||
17 | ldr \base, =at91_aic_base @ base virtual address of AIC peripheral | ||
18 | ldr \base, [\base] | ||
19 | .endm | ||
20 | |||
21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
22 | ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) | ||
23 | ldr \irqstat, [\base, #AT91_AIC_ISR] @ read interrupt source number | ||
24 | teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt | ||
25 | streq \tmp, [\base, #AT91_AIC_EOICR] @ not going to be handled further, then ACK it now. | ||
26 | .endm | ||
27 | |||
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h deleted file mode 100644 index ac8b7dfc85ef..000000000000 --- a/arch/arm/mach-at91/include/mach/irqs.h +++ /dev/null | |||
@@ -1,48 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 2004 SAN People | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __ASM_ARCH_IRQS_H | ||
22 | #define __ASM_ARCH_IRQS_H | ||
23 | |||
24 | #include <linux/io.h> | ||
25 | #include <mach/at91_aic.h> | ||
26 | |||
27 | #define NR_AIC_IRQS 32 | ||
28 | |||
29 | |||
30 | /* | ||
31 | * Acknowledge interrupt with AIC after interrupt has been handled. | ||
32 | * (by kernel/irq.c) | ||
33 | */ | ||
34 | #define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0) | ||
35 | |||
36 | |||
37 | /* | ||
38 | * IRQ interrupt symbols are the AT91xxx_ID_* symbols | ||
39 | * for IRQs handled directly through the AIC, or else the AT91_PIN_* | ||
40 | * symbols in gpio.h for ones handled indirectly as GPIOs. | ||
41 | * We make provision for 5 banks of GPIO. | ||
42 | */ | ||
43 | #define NR_IRQS (NR_AIC_IRQS + (5 * 32)) | ||
44 | |||
45 | /* FIQ is AIC source 0. */ | ||
46 | #define FIQ_START AT91_ID_FIQ | ||
47 | |||
48 | #endif | ||
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c index cfcfcbe36269..1e02c0e49dcc 100644 --- a/arch/arm/mach-at91/irq.c +++ b/arch/arm/mach-at91/irq.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
25 | #include <linux/mm.h> | 25 | #include <linux/mm.h> |
26 | #include <linux/bitmap.h> | ||
26 | #include <linux/types.h> | 27 | #include <linux/types.h> |
27 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
28 | #include <linux/of.h> | 29 | #include <linux/of.h> |
@@ -30,38 +31,218 @@ | |||
30 | #include <linux/of_irq.h> | 31 | #include <linux/of_irq.h> |
31 | #include <linux/irqdomain.h> | 32 | #include <linux/irqdomain.h> |
32 | #include <linux/err.h> | 33 | #include <linux/err.h> |
34 | #include <linux/slab.h> | ||
33 | 35 | ||
34 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
35 | #include <asm/irq.h> | 37 | #include <asm/irq.h> |
36 | #include <asm/setup.h> | 38 | #include <asm/setup.h> |
37 | 39 | ||
40 | #include <asm/exception.h> | ||
38 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
39 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
40 | #include <asm/mach/map.h> | 43 | #include <asm/mach/map.h> |
41 | 44 | ||
45 | #include <mach/at91_aic.h> | ||
46 | |||
42 | void __iomem *at91_aic_base; | 47 | void __iomem *at91_aic_base; |
43 | static struct irq_domain *at91_aic_domain; | 48 | static struct irq_domain *at91_aic_domain; |
44 | static struct device_node *at91_aic_np; | 49 | static struct device_node *at91_aic_np; |
50 | static unsigned int n_irqs = NR_AIC_IRQS; | ||
51 | static unsigned long at91_aic_caps = 0; | ||
52 | |||
53 | /* AIC5 introduces a Source Select Register */ | ||
54 | #define AT91_AIC_CAP_AIC5 (1 << 0) | ||
55 | #define has_aic5() (at91_aic_caps & AT91_AIC_CAP_AIC5) | ||
56 | |||
57 | #ifdef CONFIG_PM | ||
58 | |||
59 | static unsigned long *wakeups; | ||
60 | static unsigned long *backups; | ||
61 | |||
62 | #define set_backup(bit) set_bit(bit, backups) | ||
63 | #define clear_backup(bit) clear_bit(bit, backups) | ||
64 | |||
65 | static int at91_aic_pm_init(void) | ||
66 | { | ||
67 | backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); | ||
68 | if (!backups) | ||
69 | return -ENOMEM; | ||
70 | |||
71 | wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL); | ||
72 | if (!wakeups) { | ||
73 | kfree(backups); | ||
74 | return -ENOMEM; | ||
75 | } | ||
76 | |||
77 | return 0; | ||
78 | } | ||
79 | |||
80 | static int at91_aic_set_wake(struct irq_data *d, unsigned value) | ||
81 | { | ||
82 | if (unlikely(d->hwirq >= n_irqs)) | ||
83 | return -EINVAL; | ||
84 | |||
85 | if (value) | ||
86 | set_bit(d->hwirq, wakeups); | ||
87 | else | ||
88 | clear_bit(d->hwirq, wakeups); | ||
89 | |||
90 | return 0; | ||
91 | } | ||
92 | |||
93 | void at91_irq_suspend(void) | ||
94 | { | ||
95 | int i = 0, bit; | ||
96 | |||
97 | if (has_aic5()) { | ||
98 | /* disable enabled irqs */ | ||
99 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | ||
100 | at91_aic_write(AT91_AIC5_SSR, | ||
101 | bit & AT91_AIC5_INTSEL_MSK); | ||
102 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
103 | i = bit; | ||
104 | } | ||
105 | /* enable wakeup irqs */ | ||
106 | i = 0; | ||
107 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | ||
108 | at91_aic_write(AT91_AIC5_SSR, | ||
109 | bit & AT91_AIC5_INTSEL_MSK); | ||
110 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
111 | i = bit; | ||
112 | } | ||
113 | } else { | ||
114 | at91_aic_write(AT91_AIC_IDCR, *backups); | ||
115 | at91_aic_write(AT91_AIC_IECR, *wakeups); | ||
116 | } | ||
117 | } | ||
118 | |||
119 | void at91_irq_resume(void) | ||
120 | { | ||
121 | int i = 0, bit; | ||
122 | |||
123 | if (has_aic5()) { | ||
124 | /* disable wakeup irqs */ | ||
125 | while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) { | ||
126 | at91_aic_write(AT91_AIC5_SSR, | ||
127 | bit & AT91_AIC5_INTSEL_MSK); | ||
128 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
129 | i = bit; | ||
130 | } | ||
131 | /* enable irqs disabled for suspend */ | ||
132 | i = 0; | ||
133 | while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) { | ||
134 | at91_aic_write(AT91_AIC5_SSR, | ||
135 | bit & AT91_AIC5_INTSEL_MSK); | ||
136 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
137 | i = bit; | ||
138 | } | ||
139 | } else { | ||
140 | at91_aic_write(AT91_AIC_IDCR, *wakeups); | ||
141 | at91_aic_write(AT91_AIC_IECR, *backups); | ||
142 | } | ||
143 | } | ||
144 | |||
145 | #else | ||
146 | static inline int at91_aic_pm_init(void) | ||
147 | { | ||
148 | return 0; | ||
149 | } | ||
150 | |||
151 | #define set_backup(bit) | ||
152 | #define clear_backup(bit) | ||
153 | #define at91_aic_set_wake NULL | ||
154 | |||
155 | #endif /* CONFIG_PM */ | ||
156 | |||
157 | asmlinkage void __exception_irq_entry | ||
158 | at91_aic_handle_irq(struct pt_regs *regs) | ||
159 | { | ||
160 | u32 irqnr; | ||
161 | u32 irqstat; | ||
162 | |||
163 | irqnr = at91_aic_read(AT91_AIC_IVR); | ||
164 | irqstat = at91_aic_read(AT91_AIC_ISR); | ||
165 | |||
166 | /* | ||
167 | * ISR value is 0 when there is no current interrupt or when there is | ||
168 | * a spurious interrupt | ||
169 | */ | ||
170 | if (!irqstat) | ||
171 | at91_aic_write(AT91_AIC_EOICR, 0); | ||
172 | else | ||
173 | handle_IRQ(irqnr, regs); | ||
174 | } | ||
175 | |||
176 | asmlinkage void __exception_irq_entry | ||
177 | at91_aic5_handle_irq(struct pt_regs *regs) | ||
178 | { | ||
179 | u32 irqnr; | ||
180 | u32 irqstat; | ||
181 | |||
182 | irqnr = at91_aic_read(AT91_AIC5_IVR); | ||
183 | irqstat = at91_aic_read(AT91_AIC5_ISR); | ||
184 | |||
185 | if (!irqstat) | ||
186 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
187 | else | ||
188 | handle_IRQ(irqnr, regs); | ||
189 | } | ||
45 | 190 | ||
46 | static void at91_aic_mask_irq(struct irq_data *d) | 191 | static void at91_aic_mask_irq(struct irq_data *d) |
47 | { | 192 | { |
48 | /* Disable interrupt on AIC */ | 193 | /* Disable interrupt on AIC */ |
49 | at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq); | 194 | at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq); |
195 | /* Update ISR cache */ | ||
196 | clear_backup(d->hwirq); | ||
197 | } | ||
198 | |||
199 | static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d) | ||
200 | { | ||
201 | /* Disable interrupt on AIC5 */ | ||
202 | at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
203 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
204 | /* Update ISR cache */ | ||
205 | clear_backup(d->hwirq); | ||
50 | } | 206 | } |
51 | 207 | ||
52 | static void at91_aic_unmask_irq(struct irq_data *d) | 208 | static void at91_aic_unmask_irq(struct irq_data *d) |
53 | { | 209 | { |
54 | /* Enable interrupt on AIC */ | 210 | /* Enable interrupt on AIC */ |
55 | at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); | 211 | at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq); |
212 | /* Update ISR cache */ | ||
213 | set_backup(d->hwirq); | ||
214 | } | ||
215 | |||
216 | static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d) | ||
217 | { | ||
218 | /* Enable interrupt on AIC5 */ | ||
219 | at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
220 | at91_aic_write(AT91_AIC5_IECR, 1); | ||
221 | /* Update ISR cache */ | ||
222 | set_backup(d->hwirq); | ||
56 | } | 223 | } |
57 | 224 | ||
58 | unsigned int at91_extern_irq; | 225 | static void at91_aic_eoi(struct irq_data *d) |
226 | { | ||
227 | /* | ||
228 | * Mark end-of-interrupt on AIC, the controller doesn't care about | ||
229 | * the value written. Moreover it's a write-only register. | ||
230 | */ | ||
231 | at91_aic_write(AT91_AIC_EOICR, 0); | ||
232 | } | ||
233 | |||
234 | static void __maybe_unused at91_aic5_eoi(struct irq_data *d) | ||
235 | { | ||
236 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
237 | } | ||
59 | 238 | ||
60 | #define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq) | 239 | unsigned long *at91_extern_irq; |
61 | 240 | ||
62 | static int at91_aic_set_type(struct irq_data *d, unsigned type) | 241 | #define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq) |
242 | |||
243 | static int at91_aic_compute_srctype(struct irq_data *d, unsigned type) | ||
63 | { | 244 | { |
64 | unsigned int smr, srctype; | 245 | int srctype; |
65 | 246 | ||
66 | switch (type) { | 247 | switch (type) { |
67 | case IRQ_TYPE_LEVEL_HIGH: | 248 | case IRQ_TYPE_LEVEL_HIGH: |
@@ -74,65 +255,51 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type) | |||
74 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ | 255 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ |
75 | srctype = AT91_AIC_SRCTYPE_LOW; | 256 | srctype = AT91_AIC_SRCTYPE_LOW; |
76 | else | 257 | else |
77 | return -EINVAL; | 258 | srctype = -EINVAL; |
78 | break; | 259 | break; |
79 | case IRQ_TYPE_EDGE_FALLING: | 260 | case IRQ_TYPE_EDGE_FALLING: |
80 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ | 261 | if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */ |
81 | srctype = AT91_AIC_SRCTYPE_FALLING; | 262 | srctype = AT91_AIC_SRCTYPE_FALLING; |
82 | else | 263 | else |
83 | return -EINVAL; | 264 | srctype = -EINVAL; |
84 | break; | 265 | break; |
85 | default: | 266 | default: |
86 | return -EINVAL; | 267 | srctype = -EINVAL; |
87 | } | 268 | } |
88 | 269 | ||
89 | smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE; | 270 | return srctype; |
90 | at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); | ||
91 | return 0; | ||
92 | } | 271 | } |
93 | 272 | ||
94 | #ifdef CONFIG_PM | 273 | static int at91_aic_set_type(struct irq_data *d, unsigned type) |
95 | |||
96 | static u32 wakeups; | ||
97 | static u32 backups; | ||
98 | |||
99 | static int at91_aic_set_wake(struct irq_data *d, unsigned value) | ||
100 | { | 274 | { |
101 | if (unlikely(d->hwirq >= NR_AIC_IRQS)) | 275 | unsigned int smr; |
102 | return -EINVAL; | 276 | int srctype; |
103 | 277 | ||
104 | if (value) | 278 | srctype = at91_aic_compute_srctype(d, type); |
105 | wakeups |= (1 << d->hwirq); | 279 | if (srctype < 0) |
106 | else | 280 | return srctype; |
107 | wakeups &= ~(1 << d->hwirq); | 281 | |
282 | if (has_aic5()) { | ||
283 | at91_aic_write(AT91_AIC5_SSR, | ||
284 | d->hwirq & AT91_AIC5_INTSEL_MSK); | ||
285 | smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE; | ||
286 | at91_aic_write(AT91_AIC5_SMR, smr | srctype); | ||
287 | } else { | ||
288 | smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) | ||
289 | & ~AT91_AIC_SRCTYPE; | ||
290 | at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype); | ||
291 | } | ||
108 | 292 | ||
109 | return 0; | 293 | return 0; |
110 | } | 294 | } |
111 | 295 | ||
112 | void at91_irq_suspend(void) | ||
113 | { | ||
114 | backups = at91_aic_read(AT91_AIC_IMR); | ||
115 | at91_aic_write(AT91_AIC_IDCR, backups); | ||
116 | at91_aic_write(AT91_AIC_IECR, wakeups); | ||
117 | } | ||
118 | |||
119 | void at91_irq_resume(void) | ||
120 | { | ||
121 | at91_aic_write(AT91_AIC_IDCR, wakeups); | ||
122 | at91_aic_write(AT91_AIC_IECR, backups); | ||
123 | } | ||
124 | |||
125 | #else | ||
126 | #define at91_aic_set_wake NULL | ||
127 | #endif | ||
128 | |||
129 | static struct irq_chip at91_aic_chip = { | 296 | static struct irq_chip at91_aic_chip = { |
130 | .name = "AIC", | 297 | .name = "AIC", |
131 | .irq_ack = at91_aic_mask_irq, | ||
132 | .irq_mask = at91_aic_mask_irq, | 298 | .irq_mask = at91_aic_mask_irq, |
133 | .irq_unmask = at91_aic_unmask_irq, | 299 | .irq_unmask = at91_aic_unmask_irq, |
134 | .irq_set_type = at91_aic_set_type, | 300 | .irq_set_type = at91_aic_set_type, |
135 | .irq_set_wake = at91_aic_set_wake, | 301 | .irq_set_wake = at91_aic_set_wake, |
302 | .irq_eoi = at91_aic_eoi, | ||
136 | }; | 303 | }; |
137 | 304 | ||
138 | static void __init at91_aic_hw_init(unsigned int spu_vector) | 305 | static void __init at91_aic_hw_init(unsigned int spu_vector) |
@@ -161,41 +328,172 @@ static void __init at91_aic_hw_init(unsigned int spu_vector) | |||
161 | at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); | 328 | at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF); |
162 | } | 329 | } |
163 | 330 | ||
331 | static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector) | ||
332 | { | ||
333 | int i; | ||
334 | |||
335 | /* | ||
336 | * Perform 8 End Of Interrupt Command to make sure AIC | ||
337 | * will not Lock out nIRQ | ||
338 | */ | ||
339 | for (i = 0; i < 8; i++) | ||
340 | at91_aic_write(AT91_AIC5_EOICR, 0); | ||
341 | |||
342 | /* | ||
343 | * Spurious Interrupt ID in Spurious Vector Register. | ||
344 | * When there is no current interrupt, the IRQ Vector Register | ||
345 | * reads the value stored in AIC_SPU | ||
346 | */ | ||
347 | at91_aic_write(AT91_AIC5_SPU, spu_vector); | ||
348 | |||
349 | /* No debugging in AIC: Debug (Protect) Control Register */ | ||
350 | at91_aic_write(AT91_AIC5_DCR, 0); | ||
351 | |||
352 | /* Disable and clear all interrupts initially */ | ||
353 | for (i = 0; i < n_irqs; i++) { | ||
354 | at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK); | ||
355 | at91_aic_write(AT91_AIC5_IDCR, 1); | ||
356 | at91_aic_write(AT91_AIC5_ICCR, 1); | ||
357 | } | ||
358 | } | ||
359 | |||
164 | #if defined(CONFIG_OF) | 360 | #if defined(CONFIG_OF) |
361 | static unsigned int *at91_aic_irq_priorities; | ||
362 | |||
165 | static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, | 363 | static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq, |
166 | irq_hw_number_t hw) | 364 | irq_hw_number_t hw) |
167 | { | 365 | { |
168 | /* Put virq number in Source Vector Register */ | 366 | /* Put virq number in Source Vector Register */ |
169 | at91_aic_write(AT91_AIC_SVR(hw), virq); | 367 | at91_aic_write(AT91_AIC_SVR(hw), virq); |
170 | 368 | ||
171 | /* Active Low interrupt, without priority */ | 369 | /* Active Low interrupt, with priority */ |
172 | at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW); | 370 | at91_aic_write(AT91_AIC_SMR(hw), |
371 | AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); | ||
173 | 372 | ||
174 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq); | 373 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); |
175 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | 374 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); |
176 | 375 | ||
177 | return 0; | 376 | return 0; |
178 | } | 377 | } |
179 | 378 | ||
379 | static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq, | ||
380 | irq_hw_number_t hw) | ||
381 | { | ||
382 | at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK); | ||
383 | |||
384 | /* Put virq number in Source Vector Register */ | ||
385 | at91_aic_write(AT91_AIC5_SVR, virq); | ||
386 | |||
387 | /* Active Low interrupt, with priority */ | ||
388 | at91_aic_write(AT91_AIC5_SMR, | ||
389 | AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]); | ||
390 | |||
391 | irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq); | ||
392 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
393 | |||
394 | return 0; | ||
395 | } | ||
396 | |||
397 | static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, | ||
398 | const u32 *intspec, unsigned int intsize, | ||
399 | irq_hw_number_t *out_hwirq, unsigned int *out_type) | ||
400 | { | ||
401 | if (WARN_ON(intsize < 3)) | ||
402 | return -EINVAL; | ||
403 | if (WARN_ON(intspec[0] >= n_irqs)) | ||
404 | return -EINVAL; | ||
405 | if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY) | ||
406 | || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY))) | ||
407 | return -EINVAL; | ||
408 | |||
409 | *out_hwirq = intspec[0]; | ||
410 | *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; | ||
411 | at91_aic_irq_priorities[*out_hwirq] = intspec[2]; | ||
412 | |||
413 | return 0; | ||
414 | } | ||
415 | |||
180 | static struct irq_domain_ops at91_aic_irq_ops = { | 416 | static struct irq_domain_ops at91_aic_irq_ops = { |
181 | .map = at91_aic_irq_map, | 417 | .map = at91_aic_irq_map, |
182 | .xlate = irq_domain_xlate_twocell, | 418 | .xlate = at91_aic_irq_domain_xlate, |
183 | }; | 419 | }; |
184 | 420 | ||
185 | int __init at91_aic_of_init(struct device_node *node, | 421 | int __init at91_aic_of_common_init(struct device_node *node, |
186 | struct device_node *parent) | 422 | struct device_node *parent) |
187 | { | 423 | { |
424 | struct property *prop; | ||
425 | const __be32 *p; | ||
426 | u32 val; | ||
427 | |||
428 | at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs) | ||
429 | * sizeof(*at91_extern_irq), GFP_KERNEL); | ||
430 | if (!at91_extern_irq) | ||
431 | return -ENOMEM; | ||
432 | |||
433 | if (at91_aic_pm_init()) { | ||
434 | kfree(at91_extern_irq); | ||
435 | return -ENOMEM; | ||
436 | } | ||
437 | |||
438 | at91_aic_irq_priorities = kzalloc(n_irqs | ||
439 | * sizeof(*at91_aic_irq_priorities), | ||
440 | GFP_KERNEL); | ||
441 | if (!at91_aic_irq_priorities) | ||
442 | return -ENOMEM; | ||
443 | |||
188 | at91_aic_base = of_iomap(node, 0); | 444 | at91_aic_base = of_iomap(node, 0); |
189 | at91_aic_np = node; | 445 | at91_aic_np = node; |
190 | 446 | ||
191 | at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS, | 447 | at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs, |
192 | &at91_aic_irq_ops, NULL); | 448 | &at91_aic_irq_ops, NULL); |
193 | if (!at91_aic_domain) | 449 | if (!at91_aic_domain) |
194 | panic("Unable to add AIC irq domain (DT)\n"); | 450 | panic("Unable to add AIC irq domain (DT)\n"); |
195 | 451 | ||
452 | of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) { | ||
453 | if (val >= n_irqs) | ||
454 | pr_warn("AIC: external irq %d >= %d skip it\n", | ||
455 | val, n_irqs); | ||
456 | else | ||
457 | set_bit(val, at91_extern_irq); | ||
458 | } | ||
459 | |||
196 | irq_set_default_host(at91_aic_domain); | 460 | irq_set_default_host(at91_aic_domain); |
197 | 461 | ||
198 | at91_aic_hw_init(NR_AIC_IRQS); | 462 | return 0; |
463 | } | ||
464 | |||
465 | int __init at91_aic_of_init(struct device_node *node, | ||
466 | struct device_node *parent) | ||
467 | { | ||
468 | int err; | ||
469 | |||
470 | err = at91_aic_of_common_init(node, parent); | ||
471 | if (err) | ||
472 | return err; | ||
473 | |||
474 | at91_aic_hw_init(n_irqs); | ||
475 | |||
476 | return 0; | ||
477 | } | ||
478 | |||
479 | int __init at91_aic5_of_init(struct device_node *node, | ||
480 | struct device_node *parent) | ||
481 | { | ||
482 | int err; | ||
483 | |||
484 | at91_aic_caps |= AT91_AIC_CAP_AIC5; | ||
485 | n_irqs = NR_AIC5_IRQS; | ||
486 | at91_aic_chip.irq_ack = at91_aic5_mask_irq; | ||
487 | at91_aic_chip.irq_mask = at91_aic5_mask_irq; | ||
488 | at91_aic_chip.irq_unmask = at91_aic5_unmask_irq; | ||
489 | at91_aic_chip.irq_eoi = at91_aic5_eoi; | ||
490 | at91_aic_irq_ops.map = at91_aic5_irq_map; | ||
491 | |||
492 | err = at91_aic_of_common_init(node, parent); | ||
493 | if (err) | ||
494 | return err; | ||
495 | |||
496 | at91_aic5_hw_init(n_irqs); | ||
199 | 497 | ||
200 | return 0; | 498 | return 0; |
201 | } | 499 | } |
@@ -204,22 +502,25 @@ int __init at91_aic_of_init(struct device_node *node, | |||
204 | /* | 502 | /* |
205 | * Initialize the AIC interrupt controller. | 503 | * Initialize the AIC interrupt controller. |
206 | */ | 504 | */ |
207 | void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | 505 | void __init at91_aic_init(unsigned int *priority) |
208 | { | 506 | { |
209 | unsigned int i; | 507 | unsigned int i; |
210 | int irq_base; | 508 | int irq_base; |
211 | 509 | ||
510 | if (at91_aic_pm_init()) | ||
511 | panic("Unable to allocate bit maps\n"); | ||
512 | |||
212 | at91_aic_base = ioremap(AT91_AIC, 512); | 513 | at91_aic_base = ioremap(AT91_AIC, 512); |
213 | if (!at91_aic_base) | 514 | if (!at91_aic_base) |
214 | panic("Unable to ioremap AIC registers\n"); | 515 | panic("Unable to ioremap AIC registers\n"); |
215 | 516 | ||
216 | /* Add irq domain for AIC */ | 517 | /* Add irq domain for AIC */ |
217 | irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0); | 518 | irq_base = irq_alloc_descs(-1, 0, n_irqs, 0); |
218 | if (irq_base < 0) { | 519 | if (irq_base < 0) { |
219 | WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); | 520 | WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n"); |
220 | irq_base = 0; | 521 | irq_base = 0; |
221 | } | 522 | } |
222 | at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS, | 523 | at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs, |
223 | irq_base, 0, | 524 | irq_base, 0, |
224 | &irq_domain_simple_ops, NULL); | 525 | &irq_domain_simple_ops, NULL); |
225 | 526 | ||
@@ -232,15 +533,14 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) | |||
232 | * The IVR is used by macro get_irqnr_and_base to read and verify. | 533 | * The IVR is used by macro get_irqnr_and_base to read and verify. |
233 | * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. | 534 | * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. |
234 | */ | 535 | */ |
235 | for (i = 0; i < NR_AIC_IRQS; i++) { | 536 | for (i = 0; i < n_irqs; i++) { |
236 | /* Put hardware irq number in Source Vector Register: */ | 537 | /* Put hardware irq number in Source Vector Register: */ |
237 | at91_aic_write(AT91_AIC_SVR(i), i); | 538 | at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i); |
238 | /* Active Low interrupt, with the specified priority */ | 539 | /* Active Low interrupt, with the specified priority */ |
239 | at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); | 540 | at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); |
240 | 541 | irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq); | |
241 | irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq); | ||
242 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 542 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); |
243 | } | 543 | } |
244 | 544 | ||
245 | at91_aic_hw_init(NR_AIC_IRQS); | 545 | at91_aic_hw_init(n_irqs); |
246 | } | 546 | } |
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 1bfaad628731..2c2d86505a54 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
26 | #include <asm/mach/irq.h> | 26 | #include <asm/mach/irq.h> |
27 | 27 | ||
28 | #include <mach/at91_aic.h> | ||
28 | #include <mach/at91_pmc.h> | 29 | #include <mach/at91_pmc.h> |
29 | #include <mach/cpu.h> | 30 | #include <mach/cpu.h> |
30 | 31 | ||
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index c965fd8eb31a..f15293bd7974 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
28 | #include <linux/sched.h> | 28 | #include <linux/sched.h> |
29 | #include <linux/timex.h> | ||
30 | 29 | ||
31 | #include <asm/sizes.h> | 30 | #include <asm/sizes.h> |
32 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
@@ -188,7 +187,6 @@ static struct irqaction clps711x_timer_irq = { | |||
188 | 187 | ||
189 | static void __init clps711x_timer_init(void) | 188 | static void __init clps711x_timer_init(void) |
190 | { | 189 | { |
191 | struct timespec tv; | ||
192 | unsigned int syscon; | 190 | unsigned int syscon; |
193 | 191 | ||
194 | syscon = clps_readl(SYSCON1); | 192 | syscon = clps_readl(SYSCON1); |
@@ -198,10 +196,6 @@ static void __init clps711x_timer_init(void) | |||
198 | clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ | 196 | clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */ |
199 | 197 | ||
200 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); | 198 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); |
201 | |||
202 | tv.tv_nsec = 0; | ||
203 | tv.tv_sec = clps_readl(RTCDR); | ||
204 | do_settimeofday(&tv); | ||
205 | } | 199 | } |
206 | 200 | ||
207 | struct sys_timer clps711x_timer = { | 201 | struct sys_timer clps711x_timer = { |
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h index 3a032a67725c..fc0e028d9405 100644 --- a/arch/arm/mach-clps711x/include/mach/memory.h +++ b/arch/arm/mach-clps711x/include/mach/memory.h | |||
@@ -25,26 +25,6 @@ | |||
25 | */ | 25 | */ |
26 | #define PLAT_PHYS_OFFSET UL(0xc0000000) | 26 | #define PLAT_PHYS_OFFSET UL(0xc0000000) |
27 | 27 | ||
28 | #if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12) | ||
29 | |||
30 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
31 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
32 | #define __pfn_to_bus(x) (__pfn_to_phys(x) - PHYS_OFFSET) | ||
33 | #define __bus_to_pfn(x) __phys_to_pfn((x) + PHYS_OFFSET) | ||
34 | |||
35 | #endif | ||
36 | |||
37 | |||
38 | /* | ||
39 | * Like the SA1100, the EDB7211 has a large gap between physical RAM | ||
40 | * banks. In 2.2, the Psion (CL-PS7110) port added custom support for | ||
41 | * discontiguous physical memory. In 2.4, we can use the standard | ||
42 | * Linux NUMA support. | ||
43 | * | ||
44 | * This is not necessary for EP7211 implementations with only one used | ||
45 | * memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM. | ||
46 | */ | ||
47 | |||
48 | /* | 28 | /* |
49 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 | 29 | * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211 |
50 | * uses only one of the two banks (bank #1). However, even within | 30 | * uses only one of the two banks (bank #1). However, even within |
@@ -54,23 +34,6 @@ | |||
54 | * them, so we use 24 for the node max shift to get 16MB node sizes. | 34 | * them, so we use 24 for the node max shift to get 16MB node sizes. |
55 | */ | 35 | */ |
56 | 36 | ||
57 | /* | ||
58 | * Because of the wide memory address space between physical RAM banks on the | ||
59 | * SA1100, it's much more convenient to use Linux's NUMA support to implement | ||
60 | * our memory map representation. Assuming all memory nodes have equal access | ||
61 | * characteristics, we then have generic discontiguous memory support. | ||
62 | * | ||
63 | * Of course, all this isn't mandatory for SA1100 implementations with only | ||
64 | * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. | ||
65 | * | ||
66 | * The nodes are matched with the physical memory bank addresses which are | ||
67 | * incidentally the same as virtual addresses. | ||
68 | * | ||
69 | * node 0: 0xc0000000 - 0xc7ffffff | ||
70 | * node 1: 0xc8000000 - 0xcfffffff | ||
71 | * node 2: 0xd0000000 - 0xd7ffffff | ||
72 | * node 3: 0xd8000000 - 0xdfffffff | ||
73 | */ | ||
74 | #define SECTION_SIZE_BITS 24 | 37 | #define SECTION_SIZE_BITS 24 |
75 | #define MAX_PHYSMEM_BITS 32 | 38 | #define MAX_PHYSMEM_BITS 32 |
76 | 39 | ||
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c index 42ee8f33eafb..f266d90b9efc 100644 --- a/arch/arm/mach-clps711x/p720t.c +++ b/arch/arm/mach-clps711x/p720t.c | |||
@@ -86,17 +86,7 @@ static void __init p720t_map_io(void) | |||
86 | iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); | 86 | iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc)); |
87 | } | 87 | } |
88 | 88 | ||
89 | MACHINE_START(P720T, "ARM-Prospector720T") | 89 | static void __init p720t_init_early(void) |
90 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
91 | .atag_offset = 0x100, | ||
92 | .fixup = fixup_p720t, | ||
93 | .map_io = p720t_map_io, | ||
94 | .init_irq = clps711x_init_irq, | ||
95 | .timer = &clps711x_timer, | ||
96 | .restart = clps711x_restart, | ||
97 | MACHINE_END | ||
98 | |||
99 | static int p720t_hw_init(void) | ||
100 | { | 90 | { |
101 | /* | 91 | /* |
102 | * Power down as much as possible in case we don't | 92 | * Power down as much as possible in case we don't |
@@ -111,13 +101,19 @@ static int p720t_hw_init(void) | |||
111 | PLD_CODEC = 0; | 101 | PLD_CODEC = 0; |
112 | PLD_TCH = 0; | 102 | PLD_TCH = 0; |
113 | PLD_SPI = 0; | 103 | PLD_SPI = 0; |
114 | #ifndef CONFIG_DEBUG_LL | 104 | if (!IS_ENABLED(CONFIG_DEBUG_LL)) { |
115 | PLD_COM2 = 0; | 105 | PLD_COM2 = 0; |
116 | PLD_COM1 = 0; | 106 | PLD_COM1 = 0; |
117 | #endif | 107 | } |
118 | |||
119 | return 0; | ||
120 | } | 108 | } |
121 | 109 | ||
122 | __initcall(p720t_hw_init); | 110 | MACHINE_START(P720T, "ARM-Prospector720T") |
123 | 111 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | |
112 | .atag_offset = 0x100, | ||
113 | .fixup = fixup_p720t, | ||
114 | .init_early = p720t_init_early, | ||
115 | .map_io = p720t_map_io, | ||
116 | .init_irq = clps711x_init_irq, | ||
117 | .timer = &clps711x_timer, | ||
118 | .restart = clps711x_restart, | ||
119 | MACHINE_END | ||
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 32d837d8eab9..2ce1ef07c13d 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig | |||
@@ -4,6 +4,7 @@ config AINTC | |||
4 | bool | 4 | bool |
5 | 5 | ||
6 | config CP_INTC | 6 | config CP_INTC |
7 | select IRQ_DOMAIN | ||
7 | bool | 8 | bool |
8 | 9 | ||
9 | config ARCH_DAVINCI_DMx | 10 | config ARCH_DAVINCI_DMx |
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 2db78bd5c835..2227effcb0e9 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile | |||
@@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o | |||
39 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o | 39 | obj-$(CONFIG_CPU_FREQ) += cpufreq.o |
40 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 40 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
41 | obj-$(CONFIG_SUSPEND) += pm.o sleep.o | 41 | obj-$(CONFIG_SUSPEND) += pm.o sleep.o |
42 | obj-$(CONFIG_HAVE_CLK) += pm_domain.o | ||
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c index f83152d643c5..006dae8dfe44 100644 --- a/arch/arm/mach-davinci/cp_intc.c +++ b/arch/arm/mach-davinci/cp_intc.c | |||
@@ -9,9 +9,14 @@ | |||
9 | * kind, whether express or implied. | 9 | * kind, whether express or implied. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/export.h> | ||
12 | #include <linux/init.h> | 13 | #include <linux/init.h> |
13 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | ||
14 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | #include <linux/of.h> | ||
18 | #include <linux/of_address.h> | ||
19 | #include <linux/of_irq.h> | ||
15 | 20 | ||
16 | #include <mach/common.h> | 21 | #include <mach/common.h> |
17 | #include <mach/cp_intc.h> | 22 | #include <mach/cp_intc.h> |
@@ -28,7 +33,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset) | |||
28 | 33 | ||
29 | static void cp_intc_ack_irq(struct irq_data *d) | 34 | static void cp_intc_ack_irq(struct irq_data *d) |
30 | { | 35 | { |
31 | cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR); | 36 | cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR); |
32 | } | 37 | } |
33 | 38 | ||
34 | /* Disable interrupt */ | 39 | /* Disable interrupt */ |
@@ -36,20 +41,20 @@ static void cp_intc_mask_irq(struct irq_data *d) | |||
36 | { | 41 | { |
37 | /* XXX don't know why we need to disable nIRQ here... */ | 42 | /* XXX don't know why we need to disable nIRQ here... */ |
38 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); | 43 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); |
39 | cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR); | 44 | cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR); |
40 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); | 45 | cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); |
41 | } | 46 | } |
42 | 47 | ||
43 | /* Enable interrupt */ | 48 | /* Enable interrupt */ |
44 | static void cp_intc_unmask_irq(struct irq_data *d) | 49 | static void cp_intc_unmask_irq(struct irq_data *d) |
45 | { | 50 | { |
46 | cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET); | 51 | cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET); |
47 | } | 52 | } |
48 | 53 | ||
49 | static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) | 54 | static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) |
50 | { | 55 | { |
51 | unsigned reg = BIT_WORD(d->irq); | 56 | unsigned reg = BIT_WORD(d->hwirq); |
52 | unsigned mask = BIT_MASK(d->irq); | 57 | unsigned mask = BIT_MASK(d->hwirq); |
53 | unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); | 58 | unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); |
54 | unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); | 59 | unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); |
55 | 60 | ||
@@ -99,18 +104,43 @@ static struct irq_chip cp_intc_irq_chip = { | |||
99 | .irq_set_wake = cp_intc_set_wake, | 104 | .irq_set_wake = cp_intc_set_wake, |
100 | }; | 105 | }; |
101 | 106 | ||
102 | void __init cp_intc_init(void) | 107 | static struct irq_domain *cp_intc_domain; |
108 | |||
109 | static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, | ||
110 | irq_hw_number_t hw) | ||
103 | { | 111 | { |
104 | unsigned long num_irq = davinci_soc_info.intc_irq_num; | 112 | pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); |
113 | |||
114 | irq_set_chip(virq, &cp_intc_irq_chip); | ||
115 | set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); | ||
116 | irq_set_handler(virq, handle_edge_irq); | ||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | static const struct irq_domain_ops cp_intc_host_ops = { | ||
121 | .map = cp_intc_host_map, | ||
122 | .xlate = irq_domain_xlate_onetwocell, | ||
123 | }; | ||
124 | |||
125 | int __init cp_intc_of_init(struct device_node *node, struct device_node *parent) | ||
126 | { | ||
127 | u32 num_irq = davinci_soc_info.intc_irq_num; | ||
105 | u8 *irq_prio = davinci_soc_info.intc_irq_prios; | 128 | u8 *irq_prio = davinci_soc_info.intc_irq_prios; |
106 | u32 *host_map = davinci_soc_info.intc_host_map; | 129 | u32 *host_map = davinci_soc_info.intc_host_map; |
107 | unsigned num_reg = BITS_TO_LONGS(num_irq); | 130 | unsigned num_reg = BITS_TO_LONGS(num_irq); |
108 | int i; | 131 | int i, irq_base; |
109 | 132 | ||
110 | davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; | 133 | davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; |
111 | davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); | 134 | if (node) { |
135 | davinci_intc_base = of_iomap(node, 0); | ||
136 | if (of_property_read_u32(node, "ti,intc-size", &num_irq)) | ||
137 | pr_warn("unable to get intc-size, default to %d\n", | ||
138 | num_irq); | ||
139 | } else { | ||
140 | davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); | ||
141 | } | ||
112 | if (WARN_ON(!davinci_intc_base)) | 142 | if (WARN_ON(!davinci_intc_base)) |
113 | return; | 143 | return -EINVAL; |
114 | 144 | ||
115 | cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); | 145 | cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); |
116 | 146 | ||
@@ -165,13 +195,28 @@ void __init cp_intc_init(void) | |||
165 | for (i = 0; host_map[i] != -1; i++) | 195 | for (i = 0; host_map[i] != -1; i++) |
166 | cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); | 196 | cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); |
167 | 197 | ||
168 | /* Set up genirq dispatching for cp_intc */ | 198 | irq_base = irq_alloc_descs(-1, 0, num_irq, 0); |
169 | for (i = 0; i < num_irq; i++) { | 199 | if (irq_base < 0) { |
170 | irq_set_chip(i, &cp_intc_irq_chip); | 200 | pr_warn("Couldn't allocate IRQ numbers\n"); |
171 | set_irq_flags(i, IRQF_VALID | IRQF_PROBE); | 201 | irq_base = 0; |
172 | irq_set_handler(i, handle_edge_irq); | 202 | } |
203 | |||
204 | /* create a legacy host */ | ||
205 | cp_intc_domain = irq_domain_add_legacy(node, num_irq, | ||
206 | irq_base, 0, &cp_intc_host_ops, NULL); | ||
207 | |||
208 | if (!cp_intc_domain) { | ||
209 | pr_err("cp_intc: failed to allocate irq host!\n"); | ||
210 | return -EINVAL; | ||
173 | } | 211 | } |
174 | 212 | ||
175 | /* Enable global interrupt */ | 213 | /* Enable global interrupt */ |
176 | cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); | 214 | cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); |
215 | |||
216 | return 0; | ||
217 | } | ||
218 | |||
219 | void __init cp_intc_init(void) | ||
220 | { | ||
221 | cp_intc_of_init(NULL, NULL); | ||
177 | } | 222 | } |
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h index 4e8190eed673..d13d8dfa2b0d 100644 --- a/arch/arm/mach-davinci/include/mach/cp_intc.h +++ b/arch/arm/mach-davinci/include/mach/cp_intc.h | |||
@@ -52,5 +52,6 @@ | |||
52 | #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) | 52 | #define CP_INTC_VECTOR_ADDR(n) (0x2000 + (n << 2)) |
53 | 53 | ||
54 | void __init cp_intc_init(void); | 54 | void __init cp_intc_init(void); |
55 | int __init cp_intc_of_init(struct device_node *, struct device_node *); | ||
55 | 56 | ||
56 | #endif /* __ASM_HARDWARE_CP_INTC_H */ | 57 | #endif /* __ASM_HARDWARE_CP_INTC_H */ |
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h deleted file mode 100644 index b9bf3d6a4423..000000000000 --- a/arch/arm/mach-davinci/include/mach/dm365.h +++ /dev/null | |||
@@ -1 +0,0 @@ | |||
1 | /* empty, remove once unused */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h deleted file mode 100644 index b9bf3d6a4423..000000000000 --- a/arch/arm/mach-davinci/include/mach/dm646x.h +++ /dev/null | |||
@@ -1 +0,0 @@ | |||
1 | /* empty, remove once unused */ | ||
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S index 768b3c060214..cf5f573eb5fd 100644 --- a/arch/arm/mach-davinci/include/mach/entry-macro.S +++ b/arch/arm/mach-davinci/include/mach/entry-macro.S | |||
@@ -30,12 +30,10 @@ | |||
30 | #endif | 30 | #endif |
31 | #if defined(CONFIG_CP_INTC) | 31 | #if defined(CONFIG_CP_INTC) |
32 | 1001: ldr \irqnr, [\base, #0x80] /* get irq number */ | 32 | 1001: ldr \irqnr, [\base, #0x80] /* get irq number */ |
33 | mov \tmp, \irqnr, lsr #31 | ||
33 | and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ | 34 | and \irqnr, \irqnr, #0xff /* irq is in bits 0-9 */ |
34 | mov \tmp, \irqnr, lsr #3 | 35 | and \tmp, \tmp, #0x1 |
35 | and \tmp, \tmp, #0xfc | 36 | cmp \tmp, #0x1 |
36 | add \tmp, \tmp, #0x280 /* get the register offset */ | ||
37 | ldr \irqstat, [\base, \tmp] /* get the intc status */ | ||
38 | cmp \irqstat, #0x0 | ||
39 | #endif | 37 | #endif |
40 | 1002: | 38 | 1002: |
41 | .endm | 39 | .endm |
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c new file mode 100644 index 000000000000..00946e23c1ee --- /dev/null +++ b/arch/arm/mach-davinci/pm_domain.c | |||
@@ -0,0 +1,64 @@ | |||
1 | /* | ||
2 | * Runtime PM support code for DaVinci | ||
3 | * | ||
4 | * Author: Kevin Hilman | ||
5 | * | ||
6 | * Copyright (C) 2012 Texas Instruments, Inc. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | #include <linux/init.h> | ||
13 | #include <linux/pm_runtime.h> | ||
14 | #include <linux/pm_clock.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | |||
17 | #ifdef CONFIG_PM_RUNTIME | ||
18 | static int davinci_pm_runtime_suspend(struct device *dev) | ||
19 | { | ||
20 | int ret; | ||
21 | |||
22 | dev_dbg(dev, "%s\n", __func__); | ||
23 | |||
24 | ret = pm_generic_runtime_suspend(dev); | ||
25 | if (ret) | ||
26 | return ret; | ||
27 | |||
28 | ret = pm_clk_suspend(dev); | ||
29 | if (ret) { | ||
30 | pm_generic_runtime_resume(dev); | ||
31 | return ret; | ||
32 | } | ||
33 | |||
34 | return 0; | ||
35 | } | ||
36 | |||
37 | static int davinci_pm_runtime_resume(struct device *dev) | ||
38 | { | ||
39 | dev_dbg(dev, "%s\n", __func__); | ||
40 | |||
41 | pm_clk_resume(dev); | ||
42 | return pm_generic_runtime_resume(dev); | ||
43 | } | ||
44 | #endif | ||
45 | |||
46 | static struct dev_pm_domain davinci_pm_domain = { | ||
47 | .ops = { | ||
48 | SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend, | ||
49 | davinci_pm_runtime_resume, NULL) | ||
50 | USE_PLATFORM_PM_SLEEP_OPS | ||
51 | }, | ||
52 | }; | ||
53 | |||
54 | static struct pm_clk_notifier_block platform_bus_notifier = { | ||
55 | .pm_domain = &davinci_pm_domain, | ||
56 | }; | ||
57 | |||
58 | static int __init davinci_pm_runtime_init(void) | ||
59 | { | ||
60 | pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); | ||
61 | |||
62 | return 0; | ||
63 | } | ||
64 | core_initcall(davinci_pm_runtime_init); | ||
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 4dd07a0e3604..4afe52aaaff3 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
@@ -797,6 +797,102 @@ static struct platform_device ep93xx_wdt_device = { | |||
797 | .resource = ep93xx_wdt_resources, | 797 | .resource = ep93xx_wdt_resources, |
798 | }; | 798 | }; |
799 | 799 | ||
800 | /************************************************************************* | ||
801 | * EP93xx IDE | ||
802 | *************************************************************************/ | ||
803 | static struct resource ep93xx_ide_resources[] = { | ||
804 | DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38), | ||
805 | DEFINE_RES_IRQ(IRQ_EP93XX_EXT3), | ||
806 | }; | ||
807 | |||
808 | static struct platform_device ep93xx_ide_device = { | ||
809 | .name = "ep93xx-ide", | ||
810 | .id = -1, | ||
811 | .dev = { | ||
812 | .dma_mask = &ep93xx_ide_device.dev.coherent_dma_mask, | ||
813 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
814 | }, | ||
815 | .num_resources = ARRAY_SIZE(ep93xx_ide_resources), | ||
816 | .resource = ep93xx_ide_resources, | ||
817 | }; | ||
818 | |||
819 | void __init ep93xx_register_ide(void) | ||
820 | { | ||
821 | platform_device_register(&ep93xx_ide_device); | ||
822 | } | ||
823 | |||
824 | int ep93xx_ide_acquire_gpio(struct platform_device *pdev) | ||
825 | { | ||
826 | int err; | ||
827 | int i; | ||
828 | |||
829 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev)); | ||
830 | if (err) | ||
831 | return err; | ||
832 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev)); | ||
833 | if (err) | ||
834 | goto fail_egpio15; | ||
835 | for (i = 2; i < 8; i++) { | ||
836 | err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev)); | ||
837 | if (err) | ||
838 | goto fail_gpio_e; | ||
839 | } | ||
840 | for (i = 4; i < 8; i++) { | ||
841 | err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev)); | ||
842 | if (err) | ||
843 | goto fail_gpio_g; | ||
844 | } | ||
845 | for (i = 0; i < 8; i++) { | ||
846 | err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev)); | ||
847 | if (err) | ||
848 | goto fail_gpio_h; | ||
849 | } | ||
850 | |||
851 | /* GPIO ports E[7:2], G[7:4] and H used by IDE */ | ||
852 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE | | ||
853 | EP93XX_SYSCON_DEVCFG_GONIDE | | ||
854 | EP93XX_SYSCON_DEVCFG_HONIDE); | ||
855 | return 0; | ||
856 | |||
857 | fail_gpio_h: | ||
858 | for (--i; i >= 0; --i) | ||
859 | gpio_free(EP93XX_GPIO_LINE_H(i)); | ||
860 | i = 8; | ||
861 | fail_gpio_g: | ||
862 | for (--i; i >= 4; --i) | ||
863 | gpio_free(EP93XX_GPIO_LINE_G(i)); | ||
864 | i = 8; | ||
865 | fail_gpio_e: | ||
866 | for (--i; i >= 2; --i) | ||
867 | gpio_free(EP93XX_GPIO_LINE_E(i)); | ||
868 | gpio_free(EP93XX_GPIO_LINE_EGPIO15); | ||
869 | fail_egpio15: | ||
870 | gpio_free(EP93XX_GPIO_LINE_EGPIO2); | ||
871 | return err; | ||
872 | } | ||
873 | EXPORT_SYMBOL(ep93xx_ide_acquire_gpio); | ||
874 | |||
875 | void ep93xx_ide_release_gpio(struct platform_device *pdev) | ||
876 | { | ||
877 | int i; | ||
878 | |||
879 | for (i = 2; i < 8; i++) | ||
880 | gpio_free(EP93XX_GPIO_LINE_E(i)); | ||
881 | for (i = 4; i < 8; i++) | ||
882 | gpio_free(EP93XX_GPIO_LINE_G(i)); | ||
883 | for (i = 0; i < 8; i++) | ||
884 | gpio_free(EP93XX_GPIO_LINE_H(i)); | ||
885 | gpio_free(EP93XX_GPIO_LINE_EGPIO15); | ||
886 | gpio_free(EP93XX_GPIO_LINE_EGPIO2); | ||
887 | |||
888 | |||
889 | /* GPIO ports E[7:2], G[7:4] and H used by GPIO */ | ||
890 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE | | ||
891 | EP93XX_SYSCON_DEVCFG_GONIDE | | ||
892 | EP93XX_SYSCON_DEVCFG_HONIDE); | ||
893 | } | ||
894 | EXPORT_SYMBOL(ep93xx_ide_release_gpio); | ||
895 | |||
800 | void __init ep93xx_init_devices(void) | 896 | void __init ep93xx_init_devices(void) |
801 | { | 897 | { |
802 | /* Disallow access to MaverickCrunch initially */ | 898 | /* Disallow access to MaverickCrunch initially */ |
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index d74c5cddb98b..337ab7cf4c16 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c | |||
@@ -91,8 +91,8 @@ static void __init edb93xx_register_i2c(void) | |||
91 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, | 91 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, |
92 | edb93xxa_i2c_board_info, | 92 | edb93xxa_i2c_board_info, |
93 | ARRAY_SIZE(edb93xxa_i2c_board_info)); | 93 | ARRAY_SIZE(edb93xxa_i2c_board_info)); |
94 | } else if (machine_is_edb9307() || machine_is_edb9312() || | 94 | } else if (machine_is_edb9302() || machine_is_edb9307() |
95 | machine_is_edb9315()) { | 95 | || machine_is_edb9312() || machine_is_edb9315()) { |
96 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, | 96 | ep93xx_register_i2c(&edb93xx_i2c_gpio_data, |
97 | edb93xx_i2c_board_info, | 97 | edb93xx_i2c_board_info, |
98 | ARRAY_SIZE(edb93xx_i2c_board_info)); | 98 | ARRAY_SIZE(edb93xx_i2c_board_info)); |
@@ -233,6 +233,29 @@ static void __init edb93xx_register_fb(void) | |||
233 | } | 233 | } |
234 | 234 | ||
235 | 235 | ||
236 | /************************************************************************* | ||
237 | * EDB93xx IDE | ||
238 | *************************************************************************/ | ||
239 | static int __init edb93xx_has_ide(void) | ||
240 | { | ||
241 | /* | ||
242 | * Although EDB9312 and EDB9315 do have IDE capability, they have | ||
243 | * INTRQ line wired as pull-up, which makes using IDE interface | ||
244 | * problematic. | ||
245 | */ | ||
246 | return machine_is_edb9312() || machine_is_edb9315() || | ||
247 | machine_is_edb9315a(); | ||
248 | } | ||
249 | |||
250 | static void __init edb93xx_register_ide(void) | ||
251 | { | ||
252 | if (!edb93xx_has_ide()) | ||
253 | return; | ||
254 | |||
255 | ep93xx_register_ide(); | ||
256 | } | ||
257 | |||
258 | |||
236 | static void __init edb93xx_init_machine(void) | 259 | static void __init edb93xx_init_machine(void) |
237 | { | 260 | { |
238 | ep93xx_init_devices(); | 261 | ep93xx_init_devices(); |
@@ -243,6 +266,7 @@ static void __init edb93xx_init_machine(void) | |||
243 | edb93xx_register_i2s(); | 266 | edb93xx_register_i2s(); |
244 | edb93xx_register_pwm(); | 267 | edb93xx_register_pwm(); |
245 | edb93xx_register_fb(); | 268 | edb93xx_register_fb(); |
269 | edb93xx_register_ide(); | ||
246 | } | 270 | } |
247 | 271 | ||
248 | 272 | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 1ecb040d98bf..33a5122c6dc8 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h | |||
@@ -48,6 +48,9 @@ void ep93xx_register_i2s(void); | |||
48 | int ep93xx_i2s_acquire(void); | 48 | int ep93xx_i2s_acquire(void); |
49 | void ep93xx_i2s_release(void); | 49 | void ep93xx_i2s_release(void); |
50 | void ep93xx_register_ac97(void); | 50 | void ep93xx_register_ac97(void); |
51 | void ep93xx_register_ide(void); | ||
52 | int ep93xx_ide_acquire_gpio(struct platform_device *pdev); | ||
53 | void ep93xx_ide_release_gpio(struct platform_device *pdev); | ||
51 | 54 | ||
52 | void ep93xx_init_devices(void); | 55 | void ep93xx_init_devices(void); |
53 | extern struct sys_timer ep93xx_timer; | 56 | extern struct sys_timer ep93xx_timer; |
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h index 979fba722926..7bf7ff8beae7 100644 --- a/arch/arm/mach-ep93xx/soc.h +++ b/arch/arm/mach-ep93xx/soc.h | |||
@@ -69,6 +69,7 @@ | |||
69 | 69 | ||
70 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) | 70 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) |
71 | 71 | ||
72 | #define EP93XX_IDE_PHYS_BASE EP93XX_AHB_PHYS(0x000a0000) | ||
72 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) | 73 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) |
73 | 74 | ||
74 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) | 75 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) |
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index bcb7db453145..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c | |||
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = { | |||
586 | .ctrlbit = (1 << 13), | 586 | .ctrlbit = (1 << 13), |
587 | }, { | 587 | }, { |
588 | .name = "spi", | 588 | .name = "spi", |
589 | .devname = "s3c64xx-spi.0", | 589 | .devname = "exynos4210-spi.0", |
590 | .enable = exynos4_clk_ip_peril_ctrl, | 590 | .enable = exynos4_clk_ip_peril_ctrl, |
591 | .ctrlbit = (1 << 16), | 591 | .ctrlbit = (1 << 16), |
592 | }, { | 592 | }, { |
593 | .name = "spi", | 593 | .name = "spi", |
594 | .devname = "s3c64xx-spi.1", | 594 | .devname = "exynos4210-spi.1", |
595 | .enable = exynos4_clk_ip_peril_ctrl, | 595 | .enable = exynos4_clk_ip_peril_ctrl, |
596 | .ctrlbit = (1 << 17), | 596 | .ctrlbit = (1 << 17), |
597 | }, { | 597 | }, { |
598 | .name = "spi", | 598 | .name = "spi", |
599 | .devname = "s3c64xx-spi.2", | 599 | .devname = "exynos4210-spi.2", |
600 | .enable = exynos4_clk_ip_peril_ctrl, | 600 | .enable = exynos4_clk_ip_peril_ctrl, |
601 | .ctrlbit = (1 << 18), | 601 | .ctrlbit = (1 << 18), |
602 | }, { | 602 | }, { |
@@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { | |||
1242 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | 1242 | .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
1243 | }; | 1243 | }; |
1244 | 1244 | ||
1245 | static struct clksrc_clk exynos4_clk_mdout_spi0 = { | ||
1246 | .clk = { | ||
1247 | .name = "mdout_spi", | ||
1248 | .devname = "exynos4210-spi.0", | ||
1249 | }, | ||
1250 | .sources = &exynos4_clkset_group, | ||
1251 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | ||
1252 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | ||
1253 | }; | ||
1254 | |||
1255 | static struct clksrc_clk exynos4_clk_mdout_spi1 = { | ||
1256 | .clk = { | ||
1257 | .name = "mdout_spi", | ||
1258 | .devname = "exynos4210-spi.1", | ||
1259 | }, | ||
1260 | .sources = &exynos4_clkset_group, | ||
1261 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | ||
1262 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | ||
1263 | }; | ||
1264 | |||
1265 | static struct clksrc_clk exynos4_clk_mdout_spi2 = { | ||
1266 | .clk = { | ||
1267 | .name = "mdout_spi", | ||
1268 | .devname = "exynos4210-spi.2", | ||
1269 | }, | ||
1270 | .sources = &exynos4_clkset_group, | ||
1271 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | ||
1272 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | ||
1273 | }; | ||
1274 | |||
1245 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { | 1275 | static struct clksrc_clk exynos4_clk_sclk_spi0 = { |
1246 | .clk = { | 1276 | .clk = { |
1247 | .name = "sclk_spi", | 1277 | .name = "sclk_spi", |
1248 | .devname = "s3c64xx-spi.0", | 1278 | .devname = "exynos4210-spi.0", |
1279 | .parent = &exynos4_clk_mdout_spi0.clk, | ||
1249 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1280 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1250 | .ctrlbit = (1 << 16), | 1281 | .ctrlbit = (1 << 16), |
1251 | }, | 1282 | }, |
1252 | .sources = &exynos4_clkset_group, | 1283 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, |
1253 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, | ||
1254 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, | ||
1255 | }; | 1284 | }; |
1256 | 1285 | ||
1257 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { | 1286 | static struct clksrc_clk exynos4_clk_sclk_spi1 = { |
1258 | .clk = { | 1287 | .clk = { |
1259 | .name = "sclk_spi", | 1288 | .name = "sclk_spi", |
1260 | .devname = "s3c64xx-spi.1", | 1289 | .devname = "exynos4210-spi.1", |
1290 | .parent = &exynos4_clk_mdout_spi1.clk, | ||
1261 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1291 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1262 | .ctrlbit = (1 << 20), | 1292 | .ctrlbit = (1 << 20), |
1263 | }, | 1293 | }, |
1264 | .sources = &exynos4_clkset_group, | 1294 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, |
1265 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, | ||
1266 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, | ||
1267 | }; | 1295 | }; |
1268 | 1296 | ||
1269 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { | 1297 | static struct clksrc_clk exynos4_clk_sclk_spi2 = { |
1270 | .clk = { | 1298 | .clk = { |
1271 | .name = "sclk_spi", | 1299 | .name = "sclk_spi", |
1272 | .devname = "s3c64xx-spi.2", | 1300 | .devname = "exynos4210-spi.2", |
1301 | .parent = &exynos4_clk_mdout_spi2.clk, | ||
1273 | .enable = exynos4_clksrc_mask_peril1_ctrl, | 1302 | .enable = exynos4_clksrc_mask_peril1_ctrl, |
1274 | .ctrlbit = (1 << 24), | 1303 | .ctrlbit = (1 << 24), |
1275 | }, | 1304 | }, |
1276 | .sources = &exynos4_clkset_group, | 1305 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, |
1277 | .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, | ||
1278 | .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, | ||
1279 | }; | 1306 | }; |
1280 | 1307 | ||
1281 | /* Clock initialization code */ | 1308 | /* Clock initialization code */ |
@@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { | |||
1331 | &exynos4_clk_sclk_spi0, | 1358 | &exynos4_clk_sclk_spi0, |
1332 | &exynos4_clk_sclk_spi1, | 1359 | &exynos4_clk_sclk_spi1, |
1333 | &exynos4_clk_sclk_spi2, | 1360 | &exynos4_clk_sclk_spi2, |
1334 | 1361 | &exynos4_clk_mdout_spi0, | |
1362 | &exynos4_clk_mdout_spi1, | ||
1363 | &exynos4_clk_mdout_spi2, | ||
1335 | }; | 1364 | }; |
1336 | 1365 | ||
1337 | static struct clk_lookup exynos4_clk_lookup[] = { | 1366 | static struct clk_lookup exynos4_clk_lookup[] = { |
@@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = { | |||
1347 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), | 1376 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), |
1348 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), | 1377 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), |
1349 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), | 1378 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), |
1350 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), | 1379 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), |
1351 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), | 1380 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), |
1352 | CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), | 1381 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), |
1353 | }; | 1382 | }; |
1354 | 1383 | ||
1355 | static int xtal_rate; | 1384 | static int xtal_rate; |
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index fefa336be2b4..774533c67066 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c | |||
@@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable) | |||
131 | return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); | 131 | return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable); |
132 | } | 132 | } |
133 | 133 | ||
134 | static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable) | ||
135 | { | ||
136 | return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable); | ||
137 | } | ||
138 | |||
134 | static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) | 139 | static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable) |
135 | { | 140 | { |
136 | return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); | 141 | return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable); |
@@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = { | |||
741 | .enable = exynos5_clk_ip_peric_ctrl, | 746 | .enable = exynos5_clk_ip_peric_ctrl, |
742 | .ctrlbit = (1 << 14), | 747 | .ctrlbit = (1 << 14), |
743 | }, { | 748 | }, { |
749 | .name = "spi", | ||
750 | .devname = "exynos4210-spi.0", | ||
751 | .parent = &exynos5_clk_aclk_66.clk, | ||
752 | .enable = exynos5_clk_ip_peric_ctrl, | ||
753 | .ctrlbit = (1 << 16), | ||
754 | }, { | ||
755 | .name = "spi", | ||
756 | .devname = "exynos4210-spi.1", | ||
757 | .parent = &exynos5_clk_aclk_66.clk, | ||
758 | .enable = exynos5_clk_ip_peric_ctrl, | ||
759 | .ctrlbit = (1 << 17), | ||
760 | }, { | ||
761 | .name = "spi", | ||
762 | .devname = "exynos4210-spi.2", | ||
763 | .parent = &exynos5_clk_aclk_66.clk, | ||
764 | .enable = exynos5_clk_ip_peric_ctrl, | ||
765 | .ctrlbit = (1 << 18), | ||
766 | }, { | ||
744 | .name = SYSMMU_CLOCK_NAME, | 767 | .name = SYSMMU_CLOCK_NAME, |
745 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), | 768 | .devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0), |
746 | .enable = &exynos5_clk_ip_mfc_ctrl, | 769 | .enable = &exynos5_clk_ip_mfc_ctrl, |
@@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = { | |||
1034 | .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, | 1057 | .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 }, |
1035 | }; | 1058 | }; |
1036 | 1059 | ||
1060 | static struct clksrc_clk exynos5_clk_mdout_spi0 = { | ||
1061 | .clk = { | ||
1062 | .name = "mdout_spi", | ||
1063 | .devname = "exynos4210-spi.0", | ||
1064 | }, | ||
1065 | .sources = &exynos5_clkset_group, | ||
1066 | .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 }, | ||
1067 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 }, | ||
1068 | }; | ||
1069 | |||
1070 | static struct clksrc_clk exynos5_clk_mdout_spi1 = { | ||
1071 | .clk = { | ||
1072 | .name = "mdout_spi", | ||
1073 | .devname = "exynos4210-spi.1", | ||
1074 | }, | ||
1075 | .sources = &exynos5_clkset_group, | ||
1076 | .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 }, | ||
1077 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 }, | ||
1078 | }; | ||
1079 | |||
1080 | static struct clksrc_clk exynos5_clk_mdout_spi2 = { | ||
1081 | .clk = { | ||
1082 | .name = "mdout_spi", | ||
1083 | .devname = "exynos4210-spi.2", | ||
1084 | }, | ||
1085 | .sources = &exynos5_clkset_group, | ||
1086 | .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 }, | ||
1087 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 }, | ||
1088 | }; | ||
1089 | |||
1090 | static struct clksrc_clk exynos5_clk_sclk_spi0 = { | ||
1091 | .clk = { | ||
1092 | .name = "sclk_spi", | ||
1093 | .devname = "exynos4210-spi.0", | ||
1094 | .parent = &exynos5_clk_mdout_spi0.clk, | ||
1095 | .enable = exynos5_clksrc_mask_peric1_ctrl, | ||
1096 | .ctrlbit = (1 << 16), | ||
1097 | }, | ||
1098 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 }, | ||
1099 | }; | ||
1100 | |||
1101 | static struct clksrc_clk exynos5_clk_sclk_spi1 = { | ||
1102 | .clk = { | ||
1103 | .name = "sclk_spi", | ||
1104 | .devname = "exynos4210-spi.1", | ||
1105 | .parent = &exynos5_clk_mdout_spi1.clk, | ||
1106 | .enable = exynos5_clksrc_mask_peric1_ctrl, | ||
1107 | .ctrlbit = (1 << 20), | ||
1108 | }, | ||
1109 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 }, | ||
1110 | }; | ||
1111 | |||
1112 | static struct clksrc_clk exynos5_clk_sclk_spi2 = { | ||
1113 | .clk = { | ||
1114 | .name = "sclk_spi", | ||
1115 | .devname = "exynos4210-spi.2", | ||
1116 | .parent = &exynos5_clk_mdout_spi2.clk, | ||
1117 | .enable = exynos5_clksrc_mask_peric1_ctrl, | ||
1118 | .ctrlbit = (1 << 24), | ||
1119 | }, | ||
1120 | .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 }, | ||
1121 | }; | ||
1122 | |||
1037 | static struct clksrc_clk exynos5_clksrcs[] = { | 1123 | static struct clksrc_clk exynos5_clksrcs[] = { |
1038 | { | 1124 | { |
1039 | .clk = { | 1125 | .clk = { |
@@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = { | |||
1148 | &exynos5_clk_dout_mmc4, | 1234 | &exynos5_clk_dout_mmc4, |
1149 | &exynos5_clk_aclk_acp, | 1235 | &exynos5_clk_aclk_acp, |
1150 | &exynos5_clk_pclk_acp, | 1236 | &exynos5_clk_pclk_acp, |
1237 | &exynos5_clk_sclk_spi0, | ||
1238 | &exynos5_clk_sclk_spi1, | ||
1239 | &exynos5_clk_sclk_spi2, | ||
1240 | &exynos5_clk_mdout_spi0, | ||
1241 | &exynos5_clk_mdout_spi1, | ||
1242 | &exynos5_clk_mdout_spi2, | ||
1151 | }; | 1243 | }; |
1152 | 1244 | ||
1153 | static struct clk *exynos5_clk_cdev[] = { | 1245 | static struct clk *exynos5_clk_cdev[] = { |
@@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = { | |||
1176 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), | 1268 | CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), |
1177 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), | 1269 | CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), |
1178 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), | 1270 | CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), |
1271 | CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk), | ||
1272 | CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk), | ||
1273 | CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk), | ||
1179 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), | 1274 | CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), |
1180 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), | 1275 | CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), |
1181 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), | 1276 | CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), |
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 742edd3bbec3..4eb39cdf75ea 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = { | |||
540 | .map = combiner_irq_domain_map, | 540 | .map = combiner_irq_domain_map, |
541 | }; | 541 | }; |
542 | 542 | ||
543 | void __init combiner_init(void __iomem *combiner_base, struct device_node *np) | 543 | static void __init combiner_init(void __iomem *combiner_base, |
544 | struct device_node *np) | ||
544 | { | 545 | { |
545 | int i, irq, irq_base; | 546 | int i, irq, irq_base; |
546 | unsigned int max_nr, nr_irq; | 547 | unsigned int max_nr, nr_irq; |
@@ -712,31 +713,6 @@ static int __init exynos4_l2x0_cache_init(void) | |||
712 | early_initcall(exynos4_l2x0_cache_init); | 713 | early_initcall(exynos4_l2x0_cache_init); |
713 | #endif | 714 | #endif |
714 | 715 | ||
715 | static int __init exynos5_l2_cache_init(void) | ||
716 | { | ||
717 | unsigned int val; | ||
718 | |||
719 | if (!soc_is_exynos5250()) | ||
720 | return 0; | ||
721 | |||
722 | asm volatile("mrc p15, 0, %0, c1, c0, 0\n" | ||
723 | "bic %0, %0, #(1 << 2)\n" /* cache disable */ | ||
724 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
725 | "mrc p15, 1, %0, c9, c0, 2\n" | ||
726 | : "=r"(val)); | ||
727 | |||
728 | val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0); | ||
729 | |||
730 | asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); | ||
731 | asm volatile("mrc p15, 0, %0, c1, c0, 0\n" | ||
732 | "orr %0, %0, #(1 << 2)\n" /* cache enable */ | ||
733 | "mcr p15, 0, %0, c1, c0, 0\n" | ||
734 | : : "r"(val)); | ||
735 | |||
736 | return 0; | ||
737 | } | ||
738 | early_initcall(exynos5_l2_cache_init); | ||
739 | |||
740 | static int __init exynos_init(void) | 716 | static int __init exynos_init(void) |
741 | { | 717 | { |
742 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); | 718 | printk(KERN_INFO "EXYNOS: Initializing architecture\n"); |
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h index 7a4b4789eb72..35bced6f9092 100644 --- a/arch/arm/mach-exynos/include/mach/irqs.h +++ b/arch/arm/mach-exynos/include/mach/irqs.h | |||
@@ -195,6 +195,10 @@ | |||
195 | #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 | 195 | #define IRQ_IIC6 EXYNOS4_IRQ_IIC6 |
196 | #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 | 196 | #define IRQ_IIC7 EXYNOS4_IRQ_IIC7 |
197 | 197 | ||
198 | #define IRQ_SPI0 EXYNOS4_IRQ_SPI0 | ||
199 | #define IRQ_SPI1 EXYNOS4_IRQ_SPI1 | ||
200 | #define IRQ_SPI2 EXYNOS4_IRQ_SPI2 | ||
201 | |||
198 | #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST | 202 | #define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST |
199 | #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG | 203 | #define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG |
200 | 204 | ||
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index ca4aa89aa46b..c72b675b3e4b 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h | |||
@@ -154,6 +154,9 @@ | |||
154 | #define EXYNOS4_PA_SPI0 0x13920000 | 154 | #define EXYNOS4_PA_SPI0 0x13920000 |
155 | #define EXYNOS4_PA_SPI1 0x13930000 | 155 | #define EXYNOS4_PA_SPI1 0x13930000 |
156 | #define EXYNOS4_PA_SPI2 0x13940000 | 156 | #define EXYNOS4_PA_SPI2 0x13940000 |
157 | #define EXYNOS5_PA_SPI0 0x12D20000 | ||
158 | #define EXYNOS5_PA_SPI1 0x12D30000 | ||
159 | #define EXYNOS5_PA_SPI2 0x12D40000 | ||
157 | 160 | ||
158 | #define EXYNOS4_PA_GPIO1 0x11400000 | 161 | #define EXYNOS4_PA_GPIO1 0x11400000 |
159 | #define EXYNOS4_PA_GPIO2 0x11000000 | 162 | #define EXYNOS4_PA_GPIO2 0x11000000 |
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 43a99e6f56ab..d4e392b811a3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h | |||
@@ -232,6 +232,11 @@ | |||
232 | 232 | ||
233 | #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) | 233 | #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) |
234 | 234 | ||
235 | #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) | ||
236 | #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) | ||
237 | |||
238 | #define EXYNOS5_SYS_WDTRESET (1 << 20) | ||
239 | |||
235 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) | 240 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) |
236 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) | 241 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) |
237 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) | 242 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) |
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h | |||
@@ -35,11 +35,21 @@ | |||
35 | #define PHY1_COMMON_ON_N (1 << 7) | 35 | #define PHY1_COMMON_ON_N (1 << 7) |
36 | #define PHY0_COMMON_ON_N (1 << 4) | 36 | #define PHY0_COMMON_ON_N (1 << 4) |
37 | #define PHY0_ID_PULLUP (1 << 2) | 37 | #define PHY0_ID_PULLUP (1 << 2) |
38 | #define CLKSEL_MASK (0x3 << 0) | 38 | |
39 | #define CLKSEL_SHIFT (0) | 39 | #define EXYNOS4_CLKSEL_SHIFT (0) |
40 | #define CLKSEL_48M (0x0 << 0) | 40 | |
41 | #define CLKSEL_12M (0x2 << 0) | 41 | #define EXYNOS4210_CLKSEL_MASK (0x3 << 0) |
42 | #define CLKSEL_24M (0x3 << 0) | 42 | #define EXYNOS4210_CLKSEL_48M (0x0 << 0) |
43 | #define EXYNOS4210_CLKSEL_12M (0x2 << 0) | ||
44 | #define EXYNOS4210_CLKSEL_24M (0x3 << 0) | ||
45 | |||
46 | #define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) | ||
47 | #define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) | ||
48 | #define EXYNOS4X12_CLKSEL_10M (0x1 << 0) | ||
49 | #define EXYNOS4X12_CLKSEL_12M (0x2 << 0) | ||
50 | #define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) | ||
51 | #define EXYNOS4X12_CLKSEL_20M (0x4 << 0) | ||
52 | #define EXYNOS4X12_CLKSEL_24M (0x5 << 0) | ||
43 | 53 | ||
44 | #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) | 54 | #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) |
45 | #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) | 55 | #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) |
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h deleted file mode 100644 index c71a5fba6a84..000000000000 --- a/arch/arm/mach-exynos/include/mach/spi-clocks.h +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h | ||
2 | * | ||
3 | * Copyright (C) 2011 Samsung Electronics Co. Ltd. | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | */ | ||
9 | |||
10 | #ifndef __ASM_ARCH_SPI_CLKS_H | ||
11 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ | ||
12 | |||
13 | /* Must source from SCLK_SPI */ | ||
14 | #define EXYNOS_SPI_SRCCLK_SCLK 0 | ||
15 | |||
16 | #endif /* __ASM_ARCH_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c index e7e9743543ac..b2b5d5faa748 100644 --- a/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/arch/arm/mach-exynos/mach-exynos4-dt.c | |||
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { | |||
55 | "exynos4-sdhci.3", NULL), | 55 | "exynos4-sdhci.3", NULL), |
56 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), | 56 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0), |
57 | "s3c2440-i2c.0", NULL), | 57 | "s3c2440-i2c.0", NULL), |
58 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0, | ||
59 | "exynos4210-spi.0", NULL), | ||
60 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1, | ||
61 | "exynos4210-spi.1", NULL), | ||
62 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2, | ||
63 | "exynos4210-spi.2", NULL), | ||
58 | OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), | 64 | OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL), |
59 | OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), | 65 | OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL), |
60 | {}, | 66 | {}, |
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 7b1e11a228cc..ef770bc2318f 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c | |||
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { | |||
47 | "s3c2440-i2c.0", NULL), | 47 | "s3c2440-i2c.0", NULL), |
48 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), | 48 | OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1), |
49 | "s3c2440-i2c.1", NULL), | 49 | "s3c2440-i2c.1", NULL), |
50 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0, | ||
51 | "exynos4210-spi.0", NULL), | ||
52 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1, | ||
53 | "exynos4210-spi.1", NULL), | ||
54 | OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2, | ||
55 | "exynos4210-spi.2", NULL), | ||
50 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), | 56 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL), |
51 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), | 57 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL), |
52 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), | 58 | OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL), |
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c index 656f8fc9addd..f3b328d0aff6 100644 --- a/arch/arm/mach-exynos/mach-nuri.c +++ b/arch/arm/mach-exynos/mach-nuri.c | |||
@@ -50,7 +50,6 @@ | |||
50 | #include <plat/gpio-cfg.h> | 50 | #include <plat/gpio-cfg.h> |
51 | #include <plat/iic.h> | 51 | #include <plat/iic.h> |
52 | #include <plat/mfc.h> | 52 | #include <plat/mfc.h> |
53 | #include <plat/pd.h> | ||
54 | #include <plat/fimc-core.h> | 53 | #include <plat/fimc-core.h> |
55 | #include <plat/camport.h> | 54 | #include <plat/camport.h> |
56 | #include <plat/mipi_csis.h> | 55 | #include <plat/mipi_csis.h> |
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index f5572be9d7bf..873c708fd340 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c | |||
@@ -38,7 +38,6 @@ | |||
38 | #include <plat/clock.h> | 38 | #include <plat/clock.h> |
39 | #include <plat/gpio-cfg.h> | 39 | #include <plat/gpio-cfg.h> |
40 | #include <plat/backlight.h> | 40 | #include <plat/backlight.h> |
41 | #include <plat/pd.h> | ||
42 | #include <plat/fb.h> | 41 | #include <plat/fb.h> |
43 | #include <plat/mfc.h> | 42 | #include <plat/mfc.h> |
44 | 43 | ||
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c index 262e9e446a96..5fb209c4a594 100644 --- a/arch/arm/mach-exynos/mach-smdkv310.c +++ b/arch/arm/mach-exynos/mach-smdkv310.c | |||
@@ -34,7 +34,6 @@ | |||
34 | #include <plat/keypad.h> | 34 | #include <plat/keypad.h> |
35 | #include <plat/sdhci.h> | 35 | #include <plat/sdhci.h> |
36 | #include <plat/iic.h> | 36 | #include <plat/iic.h> |
37 | #include <plat/pd.h> | ||
38 | #include <plat/gpio-cfg.h> | 37 | #include <plat/gpio-cfg.h> |
39 | #include <plat/backlight.h> | 38 | #include <plat/backlight.h> |
40 | #include <plat/mfc.h> | 39 | #include <plat/mfc.h> |
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c index cd92fa86ba41..68719f57dcea 100644 --- a/arch/arm/mach-exynos/mach-universal_c210.c +++ b/arch/arm/mach-exynos/mach-universal_c210.c | |||
@@ -39,7 +39,6 @@ | |||
39 | #include <plat/fb.h> | 39 | #include <plat/fb.h> |
40 | #include <plat/mfc.h> | 40 | #include <plat/mfc.h> |
41 | #include <plat/sdhci.h> | 41 | #include <plat/sdhci.h> |
42 | #include <plat/pd.h> | ||
43 | #include <plat/regs-fb-v4.h> | 42 | #include <plat/regs-fb-v4.h> |
44 | #include <plat/fimc-core.h> | 43 | #include <plat/fimc-core.h> |
45 | #include <plat/s5p-time.h> | 44 | #include <plat/s5p-time.h> |
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index e9fafcf163de..373c3c00d24c 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c | |||
@@ -119,7 +119,9 @@ static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, | |||
119 | struct exynos_pm_domain *pd) | 119 | struct exynos_pm_domain *pd) |
120 | { | 120 | { |
121 | if (pdev->dev.bus) { | 121 | if (pdev->dev.bus) { |
122 | if (pm_genpd_add_device(&pd->pd, &pdev->dev)) | 122 | if (!pm_genpd_add_device(&pd->pd, &pdev->dev)) |
123 | pm_genpd_dev_need_restore(&pdev->dev, true); | ||
124 | else | ||
123 | pr_info("%s: error in adding %s device to %s power" | 125 | pr_info("%s: error in adding %s device to %s power" |
124 | "domain\n", __func__, dev_name(&pdev->dev), | 126 | "domain\n", __func__, dev_name(&pdev->dev), |
125 | pd->name); | 127 | pd->name); |
@@ -151,9 +153,12 @@ static __init int exynos4_pm_init_power_domain(void) | |||
151 | if (of_have_populated_dt()) | 153 | if (of_have_populated_dt()) |
152 | return exynos_pm_dt_parse_domains(); | 154 | return exynos_pm_dt_parse_domains(); |
153 | 155 | ||
154 | for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) | 156 | for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) { |
155 | pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL, | 157 | struct exynos_pm_domain *pd = exynos4_pm_domains[idx]; |
156 | exynos4_pm_domains[idx]->is_off); | 158 | int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; |
159 | |||
160 | pm_genpd_init(&pd->pd, NULL, !on); | ||
161 | } | ||
157 | 162 | ||
158 | #ifdef CONFIG_S5P_DEV_FIMD0 | 163 | #ifdef CONFIG_S5P_DEV_FIMD0 |
159 | exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); | 164 | exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0); |
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 4aacb66f7161..3a48c852be6c 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c | |||
@@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { | |||
315 | { PMU_TABLE_END,}, | 315 | { PMU_TABLE_END,}, |
316 | }; | 316 | }; |
317 | 317 | ||
318 | void __iomem *exynos5_list_both_cnt_feed[] = { | 318 | static void __iomem *exynos5_list_both_cnt_feed[] = { |
319 | EXYNOS5_ARM_CORE0_OPTION, | 319 | EXYNOS5_ARM_CORE0_OPTION, |
320 | EXYNOS5_ARM_CORE1_OPTION, | 320 | EXYNOS5_ARM_CORE1_OPTION, |
321 | EXYNOS5_ARM_COMMON_OPTION, | 321 | EXYNOS5_ARM_COMMON_OPTION, |
@@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = { | |||
329 | EXYNOS5_TOP_PWR_SYSMEM_OPTION, | 329 | EXYNOS5_TOP_PWR_SYSMEM_OPTION, |
330 | }; | 330 | }; |
331 | 331 | ||
332 | void __iomem *exynos5_list_diable_wfi_wfe[] = { | 332 | static void __iomem *exynos5_list_diable_wfi_wfe[] = { |
333 | EXYNOS5_ARM_CORE1_OPTION, | 333 | EXYNOS5_ARM_CORE1_OPTION, |
334 | EXYNOS5_FSYS_ARM_OPTION, | 334 | EXYNOS5_FSYS_ARM_OPTION, |
335 | EXYNOS5_ISP_ARM_OPTION, | 335 | EXYNOS5_ISP_ARM_OPTION, |
@@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) | |||
390 | 390 | ||
391 | static int __init exynos_pmu_init(void) | 391 | static int __init exynos_pmu_init(void) |
392 | { | 392 | { |
393 | unsigned int value; | ||
394 | |||
393 | exynos_pmu_config = exynos4210_pmu_config; | 395 | exynos_pmu_config = exynos4210_pmu_config; |
394 | 396 | ||
395 | if (soc_is_exynos4210()) { | 397 | if (soc_is_exynos4210()) { |
@@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void) | |||
399 | exynos_pmu_config = exynos4x12_pmu_config; | 401 | exynos_pmu_config = exynos4x12_pmu_config; |
400 | pr_info("EXYNOS4x12 PMU Initialize\n"); | 402 | pr_info("EXYNOS4x12 PMU Initialize\n"); |
401 | } else if (soc_is_exynos5250()) { | 403 | } else if (soc_is_exynos5250()) { |
404 | /* | ||
405 | * When SYS_WDTRESET is set, watchdog timer reset request | ||
406 | * is ignored by power management unit. | ||
407 | */ | ||
408 | value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); | ||
409 | value &= ~EXYNOS5_SYS_WDTRESET; | ||
410 | __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); | ||
411 | |||
412 | value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); | ||
413 | value &= ~EXYNOS5_SYS_WDTRESET; | ||
414 | __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); | ||
415 | |||
402 | exynos_pmu_config = exynos5250_pmu_config; | 416 | exynos_pmu_config = exynos5250_pmu_config; |
403 | pr_info("EXYNOS5250 PMU Initialize\n"); | 417 | pr_info("EXYNOS5250 PMU Initialize\n"); |
404 | } else { | 418 | } else { |
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c index 833ff40ee0e8..4999829d1c6e 100644 --- a/arch/arm/mach-exynos/setup-spi.c +++ b/arch/arm/mach-exynos/setup-spi.c | |||
@@ -9,21 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
15 | #include <plat/s3c64xx-spi.h> | ||
16 | 13 | ||
17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
19 | .fifo_lvl_mask = 0x1ff, | ||
20 | .rx_lvl_offset = 15, | ||
21 | .high_speed = 1, | ||
22 | .clk_from_cmu = true, | ||
23 | .tx_st_done = 25, | ||
24 | }; | ||
25 | |||
26 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
27 | { | 16 | { |
28 | s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); | 17 | s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2)); |
29 | s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); | 18 | s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP); |
@@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
34 | #endif | 23 | #endif |
35 | 24 | ||
36 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 25 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
37 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { | 26 | int s3c64xx_spi1_cfg_gpio(void) |
38 | .fifo_lvl_mask = 0x7f, | ||
39 | .rx_lvl_offset = 15, | ||
40 | .high_speed = 1, | ||
41 | .clk_from_cmu = true, | ||
42 | .tx_st_done = 25, | ||
43 | }; | ||
44 | |||
45 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
46 | { | 27 | { |
47 | s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); | 28 | s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2)); |
48 | s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); | 29 | s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP); |
@@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | |||
53 | #endif | 34 | #endif |
54 | 35 | ||
55 | #ifdef CONFIG_S3C64XX_DEV_SPI2 | 36 | #ifdef CONFIG_S3C64XX_DEV_SPI2 |
56 | struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { | 37 | int s3c64xx_spi2_cfg_gpio(void) |
57 | .fifo_lvl_mask = 0x7f, | ||
58 | .rx_lvl_offset = 15, | ||
59 | .high_speed = 1, | ||
60 | .clk_from_cmu = true, | ||
61 | .tx_st_done = 25, | ||
62 | }; | ||
63 | |||
64 | int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) | ||
65 | { | 38 | { |
66 | s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); | 39 | s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5)); |
67 | s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); | 40 | s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f44e00..b81cc569a8dd 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c | |||
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) | |||
31 | struct clk *xusbxti_clk; | 31 | struct clk *xusbxti_clk; |
32 | u32 phyclk; | 32 | u32 phyclk; |
33 | 33 | ||
34 | /* set clock frequency for PLL */ | ||
35 | phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; | ||
36 | |||
37 | xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); | 34 | xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); |
38 | if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { | 35 | if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { |
39 | switch (clk_get_rate(xusbxti_clk)) { | 36 | if (soc_is_exynos4210()) { |
40 | case 12 * MHZ: | 37 | /* set clock frequency for PLL */ |
41 | phyclk |= CLKSEL_12M; | 38 | phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; |
42 | break; | 39 | |
43 | case 24 * MHZ: | 40 | switch (clk_get_rate(xusbxti_clk)) { |
44 | phyclk |= CLKSEL_24M; | 41 | case 12 * MHZ: |
45 | break; | 42 | phyclk |= EXYNOS4210_CLKSEL_12M; |
46 | default: | 43 | break; |
47 | case 48 * MHZ: | 44 | case 48 * MHZ: |
48 | /* default reference clock */ | 45 | phyclk |= EXYNOS4210_CLKSEL_48M; |
49 | break; | 46 | break; |
47 | default: | ||
48 | case 24 * MHZ: | ||
49 | phyclk |= EXYNOS4210_CLKSEL_24M; | ||
50 | break; | ||
51 | } | ||
52 | writel(phyclk, EXYNOS4_PHYCLK); | ||
53 | } else if (soc_is_exynos4212() || soc_is_exynos4412()) { | ||
54 | /* set clock frequency for PLL */ | ||
55 | phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; | ||
56 | |||
57 | switch (clk_get_rate(xusbxti_clk)) { | ||
58 | case 9600 * KHZ: | ||
59 | phyclk |= EXYNOS4X12_CLKSEL_9600K; | ||
60 | break; | ||
61 | case 10 * MHZ: | ||
62 | phyclk |= EXYNOS4X12_CLKSEL_10M; | ||
63 | break; | ||
64 | case 12 * MHZ: | ||
65 | phyclk |= EXYNOS4X12_CLKSEL_12M; | ||
66 | break; | ||
67 | case 19200 * KHZ: | ||
68 | phyclk |= EXYNOS4X12_CLKSEL_19200K; | ||
69 | break; | ||
70 | case 20 * MHZ: | ||
71 | phyclk |= EXYNOS4X12_CLKSEL_20M; | ||
72 | break; | ||
73 | default: | ||
74 | case 24 * MHZ: | ||
75 | /* default reference clock */ | ||
76 | phyclk |= EXYNOS4X12_CLKSEL_24M; | ||
77 | break; | ||
78 | } | ||
79 | writel(phyclk, EXYNOS4_PHYCLK); | ||
50 | } | 80 | } |
51 | clk_put(xusbxti_clk); | 81 | clk_put(xusbxti_clk); |
52 | } | 82 | } |
53 | |||
54 | writel(phyclk, EXYNOS4_PHYCLK); | ||
55 | } | 83 | } |
56 | 84 | ||
57 | static int exynos4210_usb_phy0_init(struct platform_device *pdev) | 85 | static int exynos4210_usb_phy0_init(struct platform_device *pdev) |
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index eff4db5de0dd..7616101a35f0 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig | |||
@@ -52,6 +52,7 @@ config SOC_IMX25 | |||
52 | select ARCH_MX25 | 52 | select ARCH_MX25 |
53 | select COMMON_CLK | 53 | select COMMON_CLK |
54 | select CPU_ARM926T | 54 | select CPU_ARM926T |
55 | select HAVE_CAN_FLEXCAN if CAN | ||
55 | select ARCH_MXC_IOMUX_V3 | 56 | select ARCH_MXC_IOMUX_V3 |
56 | select MXC_AVIC | 57 | select MXC_AVIC |
57 | 58 | ||
@@ -73,12 +74,13 @@ config SOC_IMX31 | |||
73 | 74 | ||
74 | config SOC_IMX35 | 75 | config SOC_IMX35 |
75 | bool | 76 | bool |
76 | select CPU_V6 | 77 | select CPU_V6K |
77 | select ARCH_MXC_IOMUX_V3 | 78 | select ARCH_MXC_IOMUX_V3 |
78 | select COMMON_CLK | 79 | select COMMON_CLK |
79 | select HAVE_EPIT | 80 | select HAVE_EPIT |
80 | select MXC_AVIC | 81 | select MXC_AVIC |
81 | select SMP_ON_UP if SMP | 82 | select SMP_ON_UP if SMP |
83 | select HAVE_CAN_FLEXCAN if CAN | ||
82 | 84 | ||
83 | config SOC_IMX5 | 85 | config SOC_IMX5 |
84 | select CPU_V7 | 86 | select CPU_V7 |
@@ -105,6 +107,7 @@ config SOC_IMX53 | |||
105 | select SOC_IMX5 | 107 | select SOC_IMX5 |
106 | select ARCH_MX5 | 108 | select ARCH_MX5 |
107 | select ARCH_MX53 | 109 | select ARCH_MX53 |
110 | select HAVE_CAN_FLEXCAN if CAN | ||
108 | 111 | ||
109 | if ARCH_IMX_V4_V5 | 112 | if ARCH_IMX_V4_V5 |
110 | 113 | ||
@@ -158,7 +161,6 @@ config MACH_MX25_3DS | |||
158 | select IMX_HAVE_PLATFORM_IMX2_WDT | 161 | select IMX_HAVE_PLATFORM_IMX2_WDT |
159 | select IMX_HAVE_PLATFORM_IMXDI_RTC | 162 | select IMX_HAVE_PLATFORM_IMXDI_RTC |
160 | select IMX_HAVE_PLATFORM_IMX_I2C | 163 | select IMX_HAVE_PLATFORM_IMX_I2C |
161 | select IMX_HAVE_PLATFORM_IMX_SSI | ||
162 | select IMX_HAVE_PLATFORM_IMX_FB | 164 | select IMX_HAVE_PLATFORM_IMX_FB |
163 | select IMX_HAVE_PLATFORM_IMX_KEYPAD | 165 | select IMX_HAVE_PLATFORM_IMX_KEYPAD |
164 | select IMX_HAVE_PLATFORM_IMX_UART | 166 | select IMX_HAVE_PLATFORM_IMX_UART |
@@ -557,6 +559,14 @@ config MACH_BUG | |||
557 | Include support for BUGBase 1.3 platform. This includes specific | 559 | Include support for BUGBase 1.3 platform. This includes specific |
558 | configurations for the board and its peripherals. | 560 | configurations for the board and its peripherals. |
559 | 561 | ||
562 | config MACH_IMX31_DT | ||
563 | bool "Support i.MX31 platforms from device tree" | ||
564 | select SOC_IMX31 | ||
565 | select USE_OF | ||
566 | help | ||
567 | Include support for Freescale i.MX31 based platforms | ||
568 | using the device tree for discovery. | ||
569 | |||
560 | comment "MX35 platforms:" | 570 | comment "MX35 platforms:" |
561 | 571 | ||
562 | config MACH_PCM043 | 572 | config MACH_PCM043 |
@@ -589,6 +599,7 @@ config MACH_MX35_3DS | |||
589 | select IMX_HAVE_PLATFORM_IPU_CORE | 599 | select IMX_HAVE_PLATFORM_IPU_CORE |
590 | select IMX_HAVE_PLATFORM_MXC_EHCI | 600 | select IMX_HAVE_PLATFORM_MXC_EHCI |
591 | select IMX_HAVE_PLATFORM_MXC_NAND | 601 | select IMX_HAVE_PLATFORM_MXC_NAND |
602 | select IMX_HAVE_PLATFORM_MXC_RTC | ||
592 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX | 603 | select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX |
593 | help | 604 | help |
594 | Include support for MX35PDK platform. This includes specific | 605 | Include support for MX35PDK platform. This includes specific |
@@ -826,10 +837,12 @@ config SOC_IMX6Q | |||
826 | select COMMON_CLK | 837 | select COMMON_CLK |
827 | select CPU_V7 | 838 | select CPU_V7 |
828 | select HAVE_ARM_SCU | 839 | select HAVE_ARM_SCU |
840 | select HAVE_CAN_FLEXCAN if CAN | ||
829 | select HAVE_IMX_GPC | 841 | select HAVE_IMX_GPC |
830 | select HAVE_IMX_MMDC | 842 | select HAVE_IMX_MMDC |
831 | select HAVE_IMX_SRC | 843 | select HAVE_IMX_SRC |
832 | select HAVE_SMP | 844 | select HAVE_SMP |
845 | select MFD_ANATOP | ||
833 | select PINCTRL | 846 | select PINCTRL |
834 | select PINCTRL_IMX6Q | 847 | select PINCTRL_IMX6Q |
835 | select USE_OF | 848 | select USE_OF |
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index ff29421414f2..07f7c226e4cf 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile | |||
@@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o | |||
57 | obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o | 57 | obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o |
58 | obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o | 58 | obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o |
59 | obj-$(CONFIG_MACH_BUG) += mach-bug.o | 59 | obj-$(CONFIG_MACH_BUG) += mach-bug.o |
60 | obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o | ||
60 | 61 | ||
61 | # i.MX35 based machines | 62 | # i.MX35 based machines |
62 | obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o | 63 | obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o |
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c index c9a06d800f8e..f87a48fc74e1 100644 --- a/arch/arm/mach-imx/clk-imx31.c +++ b/arch/arm/mach-imx/clk-imx31.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/clkdev.h> | 20 | #include <linux/clkdev.h> |
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/err.h> | 22 | #include <linux/err.h> |
23 | #include <linux/of.h> | ||
23 | 24 | ||
24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
25 | #include <mach/mx31.h> | 26 | #include <mach/mx31.h> |
@@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref) | |||
179 | 180 | ||
180 | return 0; | 181 | return 0; |
181 | } | 182 | } |
183 | |||
184 | #ifdef CONFIG_OF | ||
185 | int __init mx31_clocks_init_dt(void) | ||
186 | { | ||
187 | struct device_node *np; | ||
188 | u32 fref = 26000000; /* default */ | ||
189 | |||
190 | for_each_compatible_node(np, NULL, "fixed-clock") { | ||
191 | if (!of_device_is_compatible(np, "fsl,imx-osc26m")) | ||
192 | continue; | ||
193 | |||
194 | if (!of_property_read_u32(np, "clock-frequency", &fref)) | ||
195 | break; | ||
196 | } | ||
197 | |||
198 | return mx31_clocks_init(fref); | ||
199 | } | ||
200 | #endif | ||
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index e1a17ac7b3b4..ea89520b6e22 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c | |||
@@ -147,12 +147,12 @@ enum mx6q_clks { | |||
147 | esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, | 147 | esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb, |
148 | hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, | 148 | hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2, |
149 | ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, | 149 | ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi, |
150 | mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, | 150 | mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch, |
151 | gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, | 151 | gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1, |
152 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, | 152 | ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, |
153 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, | 153 | usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, |
154 | pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, | 154 | pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, |
155 | ssi2_ipg, ssi3_ipg, rom, | 155 | ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, |
156 | clk_max | 156 | clk_max |
157 | }; | 157 | }; |
158 | 158 | ||
@@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void) | |||
198 | clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); | 198 | clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3); |
199 | clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); | 199 | clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3); |
200 | 200 | ||
201 | clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6); | ||
202 | clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6); | ||
203 | |||
201 | /* name parent_name reg idx */ | 204 | /* name parent_name reg idx */ |
202 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); | 205 | clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); |
203 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); | 206 | clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); |
@@ -318,7 +321,7 @@ int __init mx6q_clocks_init(void) | |||
318 | clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); | 321 | clk[ahb] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); |
319 | 322 | ||
320 | /* name parent_name reg shift */ | 323 | /* name parent_name reg shift */ |
321 | clk[apbh_dma] = imx_clk_gate2("apbh_dma", "ahb", base + 0x68, 4); | 324 | clk[apbh_dma] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); |
322 | clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); | 325 | clk[asrc] = imx_clk_gate2("asrc", "asrc_podf", base + 0x68, 6); |
323 | clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); | 326 | clk[can1_ipg] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); |
324 | clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); | 327 | clk[can1_serial] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); |
@@ -357,6 +360,7 @@ int __init mx6q_clocks_init(void) | |||
357 | clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); | 360 | clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); |
358 | clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); | 361 | clk[openvg_axi] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); |
359 | clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); | 362 | clk[pcie_axi] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); |
363 | clk[per1_bch] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); | ||
360 | clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); | 364 | clk[pwm1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); |
361 | clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); | 365 | clk[pwm2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); |
362 | clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); | 366 | clk[pwm3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); |
@@ -388,12 +392,21 @@ int __init mx6q_clocks_init(void) | |||
388 | pr_err("i.MX6q clk %d: register failed with %ld\n", | 392 | pr_err("i.MX6q clk %d: register failed with %ld\n", |
389 | i, PTR_ERR(clk[i])); | 393 | i, PTR_ERR(clk[i])); |
390 | 394 | ||
391 | clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi"); | ||
392 | clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi"); | ||
393 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); | 395 | clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0"); |
394 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); | 396 | clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); |
395 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); | 397 | clk_register_clkdev(clk[twd], NULL, "smp_twd"); |
396 | clk_register_clkdev(clk[usboh3], NULL, "usboh3"); | 398 | clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh"); |
399 | clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand"); | ||
400 | clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand"); | ||
401 | clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand"); | ||
402 | clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand"); | ||
403 | clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand"); | ||
404 | clk_register_clkdev(clk[usboh3], NULL, "2184000.usb"); | ||
405 | clk_register_clkdev(clk[usboh3], NULL, "2184200.usb"); | ||
406 | clk_register_clkdev(clk[usboh3], NULL, "2184400.usb"); | ||
407 | clk_register_clkdev(clk[usboh3], NULL, "2184600.usb"); | ||
408 | clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy"); | ||
409 | clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy"); | ||
397 | clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); | 410 | clk_register_clkdev(clk[uart_serial], "per", "2020000.serial"); |
398 | clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); | 411 | clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial"); |
399 | clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); | 412 | clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial"); |
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h index 2628e0c474dc..93ece55f75df 100644 --- a/arch/arm/mach-imx/devices-imx21.h +++ b/arch/arm/mach-imx/devices-imx21.h | |||
@@ -14,7 +14,7 @@ extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data; | |||
14 | imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) | 14 | imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata) |
15 | 15 | ||
16 | extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; | 16 | extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data; |
17 | #define imx21_add_imx2_wdt(pdata) \ | 17 | #define imx21_add_imx2_wdt() \ |
18 | imx_add_imx2_wdt(&imx21_imx2_wdt_data) | 18 | imx_add_imx2_wdt(&imx21_imx2_wdt_data) |
19 | 19 | ||
20 | extern const struct imx_imx_fb_data imx21_imx_fb_data; | 20 | extern const struct imx_imx_fb_data imx21_imx_fb_data; |
@@ -50,7 +50,7 @@ extern const struct imx_mxc_nand_data imx21_mxc_nand_data; | |||
50 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) | 50 | imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) |
51 | 51 | ||
52 | extern const struct imx_mxc_w1_data imx21_mxc_w1_data; | 52 | extern const struct imx_mxc_w1_data imx21_mxc_w1_data; |
53 | #define imx21_add_mxc_w1(pdata) \ | 53 | #define imx21_add_mxc_w1() \ |
54 | imx_add_mxc_w1(&imx21_mxc_w1_data) | 54 | imx_add_mxc_w1(&imx21_mxc_w1_data) |
55 | 55 | ||
56 | extern const struct imx_spi_imx_data imx21_cspi_data[]; | 56 | extern const struct imx_spi_imx_data imx21_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h index efa0761c508d..f8e03dd1f116 100644 --- a/arch/arm/mach-imx/devices-imx25.h +++ b/arch/arm/mach-imx/devices-imx25.h | |||
@@ -24,11 +24,11 @@ extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data; | |||
24 | imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) | 24 | imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata) |
25 | 25 | ||
26 | extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; | 26 | extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data; |
27 | #define imx25_add_imxdi_rtc(pdata) \ | 27 | #define imx25_add_imxdi_rtc() \ |
28 | imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) | 28 | imx_add_imxdi_rtc(&imx25_imxdi_rtc_data) |
29 | 29 | ||
30 | extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; | 30 | extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data; |
31 | #define imx25_add_imx2_wdt(pdata) \ | 31 | #define imx25_add_imx2_wdt() \ |
32 | imx_add_imx2_wdt(&imx25_imx2_wdt_data) | 32 | imx_add_imx2_wdt(&imx25_imx2_wdt_data) |
33 | 33 | ||
34 | extern const struct imx_imx_fb_data imx25_imx_fb_data; | 34 | extern const struct imx_imx_fb_data imx25_imx_fb_data; |
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h index 28537a5d9048..436c5720fe6a 100644 --- a/arch/arm/mach-imx/devices-imx27.h +++ b/arch/arm/mach-imx/devices-imx27.h | |||
@@ -18,7 +18,7 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data; | |||
18 | imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) | 18 | imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata) |
19 | 19 | ||
20 | extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; | 20 | extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data; |
21 | #define imx27_add_imx2_wdt(pdata) \ | 21 | #define imx27_add_imx2_wdt() \ |
22 | imx_add_imx2_wdt(&imx27_imx2_wdt_data) | 22 | imx_add_imx2_wdt(&imx27_imx2_wdt_data) |
23 | 23 | ||
24 | extern const struct imx_imx_fb_data imx27_imx_fb_data; | 24 | extern const struct imx_imx_fb_data imx27_imx_fb_data; |
@@ -50,7 +50,7 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[]; | |||
50 | extern const struct imx_mx2_camera_data imx27_mx2_camera_data; | 50 | extern const struct imx_mx2_camera_data imx27_mx2_camera_data; |
51 | #define imx27_add_mx2_camera(pdata) \ | 51 | #define imx27_add_mx2_camera(pdata) \ |
52 | imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) | 52 | imx_add_mx2_camera(&imx27_mx2_camera_data, pdata) |
53 | #define imx27_add_mx2_emmaprp(pdata) \ | 53 | #define imx27_add_mx2_emmaprp() \ |
54 | imx_add_mx2_emmaprp(&imx27_mx2_camera_data) | 54 | imx_add_mx2_emmaprp(&imx27_mx2_camera_data) |
55 | 55 | ||
56 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; | 56 | extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data; |
@@ -69,7 +69,7 @@ extern const struct imx_mxc_nand_data imx27_mxc_nand_data; | |||
69 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) | 69 | imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) |
70 | 70 | ||
71 | extern const struct imx_mxc_w1_data imx27_mxc_w1_data; | 71 | extern const struct imx_mxc_w1_data imx27_mxc_w1_data; |
72 | #define imx27_add_mxc_w1(pdata) \ | 72 | #define imx27_add_mxc_w1() \ |
73 | imx_add_mxc_w1(&imx27_mxc_w1_data) | 73 | imx_add_mxc_w1(&imx27_mxc_w1_data) |
74 | 74 | ||
75 | extern const struct imx_spi_imx_data imx27_cspi_data[]; | 75 | extern const struct imx_spi_imx_data imx27_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h index 488e241a6db6..13f533d0aa5c 100644 --- a/arch/arm/mach-imx/devices-imx31.h +++ b/arch/arm/mach-imx/devices-imx31.h | |||
@@ -14,7 +14,7 @@ extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data; | |||
14 | imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) | 14 | imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata) |
15 | 15 | ||
16 | extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; | 16 | extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data; |
17 | #define imx31_add_imx2_wdt(pdata) \ | 17 | #define imx31_add_imx2_wdt() \ |
18 | imx_add_imx2_wdt(&imx31_imx2_wdt_data) | 18 | imx_add_imx2_wdt(&imx31_imx2_wdt_data) |
19 | 19 | ||
20 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; | 20 | extern const struct imx_imx_i2c_data imx31_imx_i2c_data[]; |
@@ -65,11 +65,11 @@ extern const struct imx_mxc_nand_data imx31_mxc_nand_data; | |||
65 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) | 65 | imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) |
66 | 66 | ||
67 | extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; | 67 | extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data; |
68 | #define imx31_add_mxc_rtc(pdata) \ | 68 | #define imx31_add_mxc_rtc() \ |
69 | imx_add_mxc_rtc(&imx31_mxc_rtc_data) | 69 | imx_add_mxc_rtc(&imx31_mxc_rtc_data) |
70 | 70 | ||
71 | extern const struct imx_mxc_w1_data imx31_mxc_w1_data; | 71 | extern const struct imx_mxc_w1_data imx31_mxc_w1_data; |
72 | #define imx31_add_mxc_w1(pdata) \ | 72 | #define imx31_add_mxc_w1() \ |
73 | imx_add_mxc_w1(&imx31_mxc_w1_data) | 73 | imx_add_mxc_w1(&imx31_mxc_w1_data) |
74 | 74 | ||
75 | extern const struct imx_spi_imx_data imx31_cspi_data[]; | 75 | extern const struct imx_spi_imx_data imx31_cspi_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h index 7b99ef0bb501..4815be1ee675 100644 --- a/arch/arm/mach-imx/devices-imx35.h +++ b/arch/arm/mach-imx/devices-imx35.h | |||
@@ -24,7 +24,7 @@ extern const struct imx_flexcan_data imx35_flexcan_data[]; | |||
24 | #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) | 24 | #define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata) |
25 | 25 | ||
26 | extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; | 26 | extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data; |
27 | #define imx35_add_imx2_wdt(pdata) \ | 27 | #define imx35_add_imx2_wdt() \ |
28 | imx_add_imx2_wdt(&imx35_imx2_wdt_data) | 28 | imx_add_imx2_wdt(&imx35_imx2_wdt_data) |
29 | 29 | ||
30 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; | 30 | extern const struct imx_imx_i2c_data imx35_imx_i2c_data[]; |
@@ -68,8 +68,12 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data; | |||
68 | #define imx35_add_mxc_nand(pdata) \ | 68 | #define imx35_add_mxc_nand(pdata) \ |
69 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) | 69 | imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) |
70 | 70 | ||
71 | extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data; | ||
72 | #define imx35_add_mxc_rtc() \ | ||
73 | imx_add_mxc_rtc(&imx35_mxc_rtc_data) | ||
74 | |||
71 | extern const struct imx_mxc_w1_data imx35_mxc_w1_data; | 75 | extern const struct imx_mxc_w1_data imx35_mxc_w1_data; |
72 | #define imx35_add_mxc_w1(pdata) \ | 76 | #define imx35_add_mxc_w1() \ |
73 | imx_add_mxc_w1(&imx35_mxc_w1_data) | 77 | imx_add_mxc_w1(&imx35_mxc_w1_data) |
74 | 78 | ||
75 | extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; | 79 | extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h index af488bc0e225..9f1718725195 100644 --- a/arch/arm/mach-imx/devices-imx51.h +++ b/arch/arm/mach-imx/devices-imx51.h | |||
@@ -55,7 +55,7 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[]; | |||
55 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) | 55 | imx_add_spi_imx(&imx51_ecspi_data[id], pdata) |
56 | 56 | ||
57 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; | 57 | extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[]; |
58 | #define imx51_add_imx2_wdt(id, pdata) \ | 58 | #define imx51_add_imx2_wdt(id) \ |
59 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) | 59 | imx_add_imx2_wdt(&imx51_imx2_wdt_data[id]) |
60 | 60 | ||
61 | extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; | 61 | extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[]; |
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h index 6e1e5d1f8c3a..77e0db96c448 100644 --- a/arch/arm/mach-imx/devices-imx53.h +++ b/arch/arm/mach-imx/devices-imx53.h | |||
@@ -30,7 +30,7 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[]; | |||
30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) | 30 | imx_add_spi_imx(&imx53_ecspi_data[id], pdata) |
31 | 31 | ||
32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; | 32 | extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[]; |
33 | #define imx53_add_imx2_wdt(id, pdata) \ | 33 | #define imx53_add_imx2_wdt(id) \ |
34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) | 34 | imx_add_imx2_wdt(&imx53_imx2_wdt_data[id]) |
35 | 35 | ||
36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; | 36 | extern const struct imx_imx_ssi_data imx53_imx_ssi_data[]; |
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c index 865daf0b09e9..05bb41d99728 100644 --- a/arch/arm/mach-imx/ehci-imx25.c +++ b/arch/arm/mach-imx/ehci-imx25.c | |||
@@ -24,14 +24,18 @@ | |||
24 | #define MX25_OTG_SIC_SHIFT 29 | 24 | #define MX25_OTG_SIC_SHIFT 29 |
25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) | 25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) |
26 | #define MX25_OTG_PM_BIT (1 << 24) | 26 | #define MX25_OTG_PM_BIT (1 << 24) |
27 | #define MX25_OTG_PP_BIT (1 << 11) | ||
28 | #define MX25_OTG_OCPOL_BIT (1 << 3) | ||
27 | 29 | ||
28 | #define MX25_H1_SIC_SHIFT 21 | 30 | #define MX25_H1_SIC_SHIFT 21 |
29 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) | 31 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) |
32 | #define MX25_H1_PP_BIT (1 << 18) | ||
30 | #define MX25_H1_PM_BIT (1 << 8) | 33 | #define MX25_H1_PM_BIT (1 << 8) |
31 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) |
32 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) |
33 | #define MX25_H1_TLL_BIT (1 << 5) | 36 | #define MX25_H1_TLL_BIT (1 << 5) |
34 | #define MX25_H1_USBTE_BIT (1 << 4) | 37 | #define MX25_H1_USBTE_BIT (1 << 4) |
38 | #define MX25_H1_OCPOL_BIT (1 << 2) | ||
35 | 39 | ||
36 | int mx25_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx25_initialize_usb_hw(int port, unsigned int flags) |
37 | { | 41 | { |
@@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags) | |||
41 | 45 | ||
42 | switch (port) { | 46 | switch (port) { |
43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
44 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); | 48 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | |
49 | MX25_OTG_OCPOL_BIT); | ||
45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; |
46 | 51 | ||
47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
48 | v |= MX25_OTG_PM_BIT; | 53 | v |= MX25_OTG_PM_BIT; |
49 | 54 | ||
55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
56 | v |= MX25_OTG_PP_BIT; | ||
57 | |||
58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
59 | v |= MX25_OTG_OCPOL_BIT; | ||
60 | |||
50 | break; | 61 | break; |
51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
52 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | | 63 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | |
53 | MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | 64 | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | |
65 | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | ||
54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; |
55 | 67 | ||
56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
57 | v |= MX25_H1_PM_BIT; | 69 | v |= MX25_H1_PM_BIT; |
58 | 70 | ||
71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
72 | v |= MX25_H1_PP_BIT; | ||
73 | |||
74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
75 | v |= MX25_H1_OCPOL_BIT; | ||
76 | |||
59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
60 | v |= MX25_H1_TLL_BIT; | 78 | v |= MX25_H1_TLL_BIT; |
61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c index 001ec3971f5d..73574c30cf50 100644 --- a/arch/arm/mach-imx/ehci-imx35.c +++ b/arch/arm/mach-imx/ehci-imx35.c | |||
@@ -24,14 +24,18 @@ | |||
24 | #define MX35_OTG_SIC_SHIFT 29 | 24 | #define MX35_OTG_SIC_SHIFT 29 |
25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) | 25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) |
26 | #define MX35_OTG_PM_BIT (1 << 24) | 26 | #define MX35_OTG_PM_BIT (1 << 24) |
27 | #define MX35_OTG_PP_BIT (1 << 11) | ||
28 | #define MX35_OTG_OCPOL_BIT (1 << 3) | ||
27 | 29 | ||
28 | #define MX35_H1_SIC_SHIFT 21 | 30 | #define MX35_H1_SIC_SHIFT 21 |
29 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) | 31 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) |
32 | #define MX35_H1_PP_BIT (1 << 18) | ||
30 | #define MX35_H1_PM_BIT (1 << 8) | 33 | #define MX35_H1_PM_BIT (1 << 8) |
31 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) |
32 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) |
33 | #define MX35_H1_TLL_BIT (1 << 5) | 36 | #define MX35_H1_TLL_BIT (1 << 5) |
34 | #define MX35_H1_USBTE_BIT (1 << 4) | 37 | #define MX35_H1_USBTE_BIT (1 << 4) |
38 | #define MX35_H1_OCPOL_BIT (1 << 2) | ||
35 | 39 | ||
36 | int mx35_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx35_initialize_usb_hw(int port, unsigned int flags) |
37 | { | 41 | { |
@@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) | |||
41 | 45 | ||
42 | switch (port) { | 46 | switch (port) { |
43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
44 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); | 48 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | |
49 | MX35_OTG_OCPOL_BIT); | ||
45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; |
46 | 51 | ||
47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
48 | v |= MX35_OTG_PM_BIT; | 53 | v |= MX35_OTG_PM_BIT; |
49 | 54 | ||
55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
56 | v |= MX35_OTG_PP_BIT; | ||
57 | |||
58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
59 | v |= MX35_OTG_OCPOL_BIT; | ||
60 | |||
50 | break; | 61 | break; |
51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
52 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | | 63 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | |
53 | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | 64 | MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | |
65 | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | ||
54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; |
55 | 67 | ||
56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
57 | v |= MX35_H1_PM_BIT; | 69 | v |= MX35_H1_PM_BIT; |
58 | 70 | ||
71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
72 | v |= MX35_H1_PP_BIT; | ||
73 | |||
74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
75 | v |= MX35_H1_OCPOL_BIT; | ||
76 | |||
59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
60 | v |= MX35_H1_TLL_BIT; | 78 | v |= MX35_H1_TLL_BIT; |
61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c index c17fa131728b..a6a4afb0ad62 100644 --- a/arch/arm/mach-imx/ehci-imx5.c +++ b/arch/arm/mach-imx/ehci-imx5.c | |||
@@ -28,11 +28,14 @@ | |||
28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ | 28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ |
29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ | 29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ |
30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ | 30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ |
31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ | 31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ |
32 | 32 | ||
33 | /* USB_PHY_CTRL_FUNC */ | 33 | /* USB_PHY_CTRL_FUNC */ |
34 | #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ | ||
34 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | 35 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
36 | #define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ | ||
35 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | 37 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
38 | #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ | ||
36 | 39 | ||
37 | /* USBH2CTRL */ | 40 | /* USBH2CTRL */ |
38 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) | 41 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
@@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
80 | if (flags & MXC_EHCI_INTERNAL_PHY) { | 83 | if (flags & MXC_EHCI_INTERNAL_PHY) { |
81 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 84 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
82 | 85 | ||
86 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
87 | v |= MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
88 | else | ||
89 | v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
83 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { | 90 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { |
84 | /* OC/USBPWR is not used */ | ||
85 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
86 | } else { | ||
87 | /* OC/USBPWR is used */ | 91 | /* OC/USBPWR is used */ |
88 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | 92 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; |
93 | } else { | ||
94 | /* OC/USBPWR is not used */ | ||
95 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | ||
89 | } | 96 | } |
97 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
98 | v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
99 | else | ||
100 | v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
90 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 101 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
91 | 102 | ||
92 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | 103 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); |
@@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
95 | else | 106 | else |
96 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ | 107 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ |
97 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 108 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
98 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
99 | else | ||
100 | v &= ~MXC_OTG_UCTRL_OPM_BIT; | 109 | v &= ~MXC_OTG_UCTRL_OPM_BIT; |
110 | else | ||
111 | v |= MXC_OTG_UCTRL_OPM_BIT; | ||
101 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 112 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
102 | } | 113 | } |
103 | break; | 114 | break; |
@@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
113 | } | 124 | } |
114 | 125 | ||
115 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 126 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
116 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | 127 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ |
117 | else | 128 | else |
118 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | 129 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ |
119 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 130 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
120 | 131 | ||
121 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 132 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
133 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
134 | v |= MXC_H1_OC_POL_BIT; | ||
135 | else | ||
136 | v &= ~MXC_H1_OC_POL_BIT; | ||
122 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 137 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
123 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | 138 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ |
124 | else | 139 | else |
@@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
142 | } | 157 | } |
143 | 158 | ||
144 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 159 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
145 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | 160 | v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ |
146 | else | 161 | else |
147 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ | 162 | v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ |
148 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); | 163 | __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); |
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c index eee0cc8d92a4..52efe4d5149b 100644 --- a/arch/arm/mach-imx/imx27-dt.c +++ b/arch/arm/mach-imx/imx27-dt.c | |||
@@ -75,7 +75,7 @@ static struct sys_timer imx27_timer = { | |||
75 | .init = imx27_timer_init, | 75 | .init = imx27_timer_init, |
76 | }; | 76 | }; |
77 | 77 | ||
78 | static const char *imx27_dt_board_compat[] __initdata = { | 78 | static const char * const imx27_dt_board_compat[] __initconst = { |
79 | "fsl,imx27", | 79 | "fsl,imx27", |
80 | NULL | 80 | NULL |
81 | }; | 81 | }; |
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c new file mode 100644 index 000000000000..a68ba207b2b7 --- /dev/null +++ b/arch/arm/mach-imx/imx31-dt.c | |||
@@ -0,0 +1,63 @@ | |||
1 | /* | ||
2 | * Copyright 2012 Sascha Hauer, Pengutronix | ||
3 | * | ||
4 | * The code contained herein is licensed under the GNU General Public | ||
5 | * License. You may obtain a copy of the GNU General Public License | ||
6 | * Version 2 or later at the following locations: | ||
7 | * | ||
8 | * http://www.opensource.org/licenses/gpl-license.html | ||
9 | * http://www.gnu.org/copyleft/gpl.html | ||
10 | */ | ||
11 | |||
12 | #include <linux/irq.h> | ||
13 | #include <linux/of_irq.h> | ||
14 | #include <linux/of_platform.h> | ||
15 | #include <asm/mach/arch.h> | ||
16 | #include <asm/mach/time.h> | ||
17 | #include <mach/common.h> | ||
18 | #include <mach/mx31.h> | ||
19 | |||
20 | static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = { | ||
21 | OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR, | ||
22 | "imx21-uart.0", NULL), | ||
23 | OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR, | ||
24 | "imx21-uart.1", NULL), | ||
25 | OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR, | ||
26 | "imx21-uart.2", NULL), | ||
27 | OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR, | ||
28 | "imx21-uart.3", NULL), | ||
29 | OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR, | ||
30 | "imx21-uart.4", NULL), | ||
31 | { /* sentinel */ } | ||
32 | }; | ||
33 | |||
34 | static void __init imx31_dt_init(void) | ||
35 | { | ||
36 | of_platform_populate(NULL, of_default_bus_match_table, | ||
37 | imx31_auxdata_lookup, NULL); | ||
38 | } | ||
39 | |||
40 | static void __init imx31_timer_init(void) | ||
41 | { | ||
42 | mx31_clocks_init_dt(); | ||
43 | } | ||
44 | |||
45 | static struct sys_timer imx31_timer = { | ||
46 | .init = imx31_timer_init, | ||
47 | }; | ||
48 | |||
49 | static const char *imx31_dt_board_compat[] __initdata = { | ||
50 | "fsl,imx31", | ||
51 | NULL | ||
52 | }; | ||
53 | |||
54 | DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") | ||
55 | .map_io = mx31_map_io, | ||
56 | .init_early = imx31_init_early, | ||
57 | .init_irq = mx31_init_irq, | ||
58 | .handle_irq = imx31_handle_irq, | ||
59 | .timer = &imx31_timer, | ||
60 | .init_machine = imx31_dt_init, | ||
61 | .dt_compat = imx31_dt_board_compat, | ||
62 | .restart = mxc_restart, | ||
63 | MACHINE_END | ||
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c index d085aea08709..9a3b06e688c5 100644 --- a/arch/arm/mach-imx/mach-cpuimx27.c +++ b/arch/arm/mach-imx/mach-cpuimx27.c | |||
@@ -233,18 +233,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
233 | .phy_mode = FSL_USB2_PHY_ULPI, | 233 | .phy_mode = FSL_USB2_PHY_ULPI, |
234 | }; | 234 | }; |
235 | 235 | ||
236 | static int otg_mode_host; | 236 | static bool otg_mode_host __initdata; |
237 | 237 | ||
238 | static int __init eukrea_cpuimx27_otg_mode(char *options) | 238 | static int __init eukrea_cpuimx27_otg_mode(char *options) |
239 | { | 239 | { |
240 | if (!strcmp(options, "host")) | 240 | if (!strcmp(options, "host")) |
241 | otg_mode_host = 1; | 241 | otg_mode_host = true; |
242 | else if (!strcmp(options, "device")) | 242 | else if (!strcmp(options, "device")) |
243 | otg_mode_host = 0; | 243 | otg_mode_host = false; |
244 | else | 244 | else |
245 | pr_info("otg_mode neither \"host\" nor \"device\". " | 245 | pr_info("otg_mode neither \"host\" nor \"device\". " |
246 | "Defaulting to device\n"); | 246 | "Defaulting to device\n"); |
247 | return 0; | 247 | return 1; |
248 | } | 248 | } |
249 | __setup("otg_mode=", eukrea_cpuimx27_otg_mode); | 249 | __setup("otg_mode=", eukrea_cpuimx27_otg_mode); |
250 | 250 | ||
@@ -266,8 +266,8 @@ static void __init eukrea_cpuimx27_init(void) | |||
266 | 266 | ||
267 | imx27_add_fec(NULL); | 267 | imx27_add_fec(NULL); |
268 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 268 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
269 | imx27_add_imx2_wdt(NULL); | 269 | imx27_add_imx2_wdt(); |
270 | imx27_add_mxc_w1(NULL); | 270 | imx27_add_mxc_w1(); |
271 | 271 | ||
272 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) | 272 | #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) |
273 | /* SDHC2 can be used for Wifi */ | 273 | /* SDHC2 can be used for Wifi */ |
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c index 6450303f1a7a..1634e54ffed5 100644 --- a/arch/arm/mach-imx/mach-cpuimx35.c +++ b/arch/arm/mach-imx/mach-cpuimx35.c | |||
@@ -141,18 +141,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
141 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, | 141 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
142 | }; | 142 | }; |
143 | 143 | ||
144 | static int otg_mode_host; | 144 | static bool otg_mode_host __initdata; |
145 | 145 | ||
146 | static int __init eukrea_cpuimx35_otg_mode(char *options) | 146 | static int __init eukrea_cpuimx35_otg_mode(char *options) |
147 | { | 147 | { |
148 | if (!strcmp(options, "host")) | 148 | if (!strcmp(options, "host")) |
149 | otg_mode_host = 1; | 149 | otg_mode_host = true; |
150 | else if (!strcmp(options, "device")) | 150 | else if (!strcmp(options, "device")) |
151 | otg_mode_host = 0; | 151 | otg_mode_host = false; |
152 | else | 152 | else |
153 | pr_info("otg_mode neither \"host\" nor \"device\". " | 153 | pr_info("otg_mode neither \"host\" nor \"device\". " |
154 | "Defaulting to device\n"); | 154 | "Defaulting to device\n"); |
155 | return 0; | 155 | return 1; |
156 | } | 156 | } |
157 | __setup("otg_mode=", eukrea_cpuimx35_otg_mode); | 157 | __setup("otg_mode=", eukrea_cpuimx35_otg_mode); |
158 | 158 | ||
@@ -167,7 +167,7 @@ static void __init eukrea_cpuimx35_init(void) | |||
167 | ARRAY_SIZE(eukrea_cpuimx35_pads)); | 167 | ARRAY_SIZE(eukrea_cpuimx35_pads)); |
168 | 168 | ||
169 | imx35_add_fec(NULL); | 169 | imx35_add_fec(NULL); |
170 | imx35_add_imx2_wdt(NULL); | 170 | imx35_add_imx2_wdt(); |
171 | 171 | ||
172 | imx35_add_imx_uart0(&uart_pdata); | 172 | imx35_add_imx_uart0(&uart_pdata); |
173 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); | 173 | imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); |
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c index 1e09de50cbcd..e78b40b41462 100644 --- a/arch/arm/mach-imx/mach-cpuimx51sd.c +++ b/arch/arm/mach-imx/mach-cpuimx51sd.c | |||
@@ -217,18 +217,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = { | |||
217 | .portsc = MXC_EHCI_MODE_ULPI, | 217 | .portsc = MXC_EHCI_MODE_ULPI, |
218 | }; | 218 | }; |
219 | 219 | ||
220 | static int otg_mode_host; | 220 | static bool otg_mode_host __initdata; |
221 | 221 | ||
222 | static int __init eukrea_cpuimx51sd_otg_mode(char *options) | 222 | static int __init eukrea_cpuimx51sd_otg_mode(char *options) |
223 | { | 223 | { |
224 | if (!strcmp(options, "host")) | 224 | if (!strcmp(options, "host")) |
225 | otg_mode_host = 1; | 225 | otg_mode_host = true; |
226 | else if (!strcmp(options, "device")) | 226 | else if (!strcmp(options, "device")) |
227 | otg_mode_host = 0; | 227 | otg_mode_host = false; |
228 | else | 228 | else |
229 | pr_info("otg_mode neither \"host\" nor \"device\". " | 229 | pr_info("otg_mode neither \"host\" nor \"device\". " |
230 | "Defaulting to device\n"); | 230 | "Defaulting to device\n"); |
231 | return 0; | 231 | return 1; |
232 | } | 232 | } |
233 | __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); | 233 | __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode); |
234 | 234 | ||
@@ -292,7 +292,7 @@ static void __init eukrea_cpuimx51sd_init(void) | |||
292 | 292 | ||
293 | imx51_add_imx_uart(0, &uart_pdata); | 293 | imx51_add_imx_uart(0, &uart_pdata); |
294 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); | 294 | imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info); |
295 | imx51_add_imx2_wdt(0, NULL); | 295 | imx51_add_imx2_wdt(0); |
296 | 296 | ||
297 | gpio_request(ETH_RST, "eth_rst"); | 297 | gpio_request(ETH_RST, "eth_rst"); |
298 | gpio_set_value(ETH_RST, 1); | 298 | gpio_set_value(ETH_RST, 1); |
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c index d1e04e676e33..017bbb70ea41 100644 --- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c +++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c | |||
@@ -109,18 +109,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
109 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, | 109 | .workaround = FLS_USB2_WORKAROUND_ENGCM09152, |
110 | }; | 110 | }; |
111 | 111 | ||
112 | static int otg_mode_host; | 112 | static bool otg_mode_host __initdata; |
113 | 113 | ||
114 | static int __init eukrea_cpuimx25_otg_mode(char *options) | 114 | static int __init eukrea_cpuimx25_otg_mode(char *options) |
115 | { | 115 | { |
116 | if (!strcmp(options, "host")) | 116 | if (!strcmp(options, "host")) |
117 | otg_mode_host = 1; | 117 | otg_mode_host = true; |
118 | else if (!strcmp(options, "device")) | 118 | else if (!strcmp(options, "device")) |
119 | otg_mode_host = 0; | 119 | otg_mode_host = false; |
120 | else | 120 | else |
121 | pr_info("otg_mode neither \"host\" nor \"device\". " | 121 | pr_info("otg_mode neither \"host\" nor \"device\". " |
122 | "Defaulting to device\n"); | 122 | "Defaulting to device\n"); |
123 | return 0; | 123 | return 1; |
124 | } | 124 | } |
125 | __setup("otg_mode=", eukrea_cpuimx25_otg_mode); | 125 | __setup("otg_mode=", eukrea_cpuimx25_otg_mode); |
126 | 126 | ||
@@ -134,9 +134,9 @@ static void __init eukrea_cpuimx25_init(void) | |||
134 | 134 | ||
135 | imx25_add_imx_uart0(&uart_pdata); | 135 | imx25_add_imx_uart0(&uart_pdata); |
136 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); | 136 | imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); |
137 | imx25_add_imxdi_rtc(NULL); | 137 | imx25_add_imxdi_rtc(); |
138 | imx25_add_fec(&mx25_fec_pdata); | 138 | imx25_add_fec(&mx25_fec_pdata); |
139 | imx25_add_imx2_wdt(NULL); | 139 | imx25_add_imx2_wdt(); |
140 | 140 | ||
141 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, | 141 | i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, |
142 | ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); | 142 | ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); |
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c index c9d350c5dcc8..7381387a8905 100644 --- a/arch/arm/mach-imx/mach-imx27ipcam.c +++ b/arch/arm/mach-imx/mach-imx27ipcam.c | |||
@@ -57,7 +57,7 @@ static void __init mx27ipcam_init(void) | |||
57 | 57 | ||
58 | imx27_add_imx_uart0(NULL); | 58 | imx27_add_imx_uart0(NULL); |
59 | imx27_add_fec(NULL); | 59 | imx27_add_fec(NULL); |
60 | imx27_add_imx2_wdt(NULL); | 60 | imx27_add_imx2_wdt(); |
61 | } | 61 | } |
62 | 62 | ||
63 | static void __init mx27ipcam_timer_init(void) | 63 | static void __init mx27ipcam_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index b47e98b7d539..140f55010630 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/pinctrl/machine.h> | 24 | #include <linux/pinctrl/machine.h> |
25 | #include <linux/phy.h> | 25 | #include <linux/phy.h> |
26 | #include <linux/micrel_phy.h> | 26 | #include <linux/micrel_phy.h> |
27 | #include <linux/mfd/anatop.h> | ||
27 | #include <asm/smp_twd.h> | 28 | #include <asm/smp_twd.h> |
28 | #include <asm/hardware/cache-l2x0.h> | 29 | #include <asm/hardware/cache-l2x0.h> |
29 | #include <asm/hardware/gic.h> | 30 | #include <asm/hardware/gic.h> |
@@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void) | |||
113 | imx6q_sabrelite_cko1_setup(); | 114 | imx6q_sabrelite_cko1_setup(); |
114 | } | 115 | } |
115 | 116 | ||
117 | static void __init imx6q_usb_init(void) | ||
118 | { | ||
119 | struct device_node *np; | ||
120 | struct platform_device *pdev = NULL; | ||
121 | struct anatop *adata = NULL; | ||
122 | |||
123 | np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); | ||
124 | if (np) | ||
125 | pdev = of_find_device_by_node(np); | ||
126 | if (pdev) | ||
127 | adata = platform_get_drvdata(pdev); | ||
128 | if (!adata) { | ||
129 | if (np) | ||
130 | of_node_put(np); | ||
131 | return; | ||
132 | } | ||
133 | |||
134 | #define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0 | ||
135 | #define HW_ANADIG_USB2_CHRG_DETECT 0x00000210 | ||
136 | |||
137 | #define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000 | ||
138 | #define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000 | ||
139 | |||
140 | /* | ||
141 | * The external charger detector needs to be disabled, | ||
142 | * or the signal at DP will be poor | ||
143 | */ | ||
144 | anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT, | ||
145 | BM_ANADIG_USB_CHRG_DETECT_EN_B | ||
146 | | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, | ||
147 | ~0); | ||
148 | anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT, | ||
149 | BM_ANADIG_USB_CHRG_DETECT_EN_B | | ||
150 | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B, | ||
151 | ~0); | ||
152 | |||
153 | of_node_put(np); | ||
154 | } | ||
155 | |||
116 | static void __init imx6q_init_machine(void) | 156 | static void __init imx6q_init_machine(void) |
117 | { | 157 | { |
118 | /* | 158 | /* |
@@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void) | |||
127 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 167 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
128 | 168 | ||
129 | imx6q_pm_init(); | 169 | imx6q_pm_init(); |
170 | imx6q_usb_init(); | ||
130 | } | 171 | } |
131 | 172 | ||
132 | static void __init imx6q_map_io(void) | 173 | static void __init imx6q_map_io(void) |
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c index f26734298aa6..ce247fd1269a 100644 --- a/arch/arm/mach-imx/mach-mx25_3ds.c +++ b/arch/arm/mach-imx/mach-mx25_3ds.c | |||
@@ -237,9 +237,9 @@ static void __init mx25pdk_init(void) | |||
237 | imx25_add_fsl_usb2_udc(&otg_device_pdata); | 237 | imx25_add_fsl_usb2_udc(&otg_device_pdata); |
238 | imx25_add_mxc_ehci_hs(&usbh2_pdata); | 238 | imx25_add_mxc_ehci_hs(&usbh2_pdata); |
239 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); | 239 | imx25_add_mxc_nand(&mx25pdk_nand_board_info); |
240 | imx25_add_imxdi_rtc(NULL); | 240 | imx25_add_imxdi_rtc(); |
241 | imx25_add_imx_fb(&mx25pdk_fb_pdata); | 241 | imx25_add_imx_fb(&mx25pdk_fb_pdata); |
242 | imx25_add_imx2_wdt(NULL); | 242 | imx25_add_imx2_wdt(); |
243 | 243 | ||
244 | mx25pdk_fec_reset(); | 244 | mx25pdk_fec_reset(); |
245 | imx25_add_fec(&mx25_fec_pdata); | 245 | imx25_add_fec(&mx25_fec_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c index c6d385c52257..ce9a5c26290c 100644 --- a/arch/arm/mach-imx/mach-mx27_3ds.c +++ b/arch/arm/mach-imx/mach-mx27_3ds.c | |||
@@ -241,18 +241,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
241 | .phy_mode = FSL_USB2_PHY_ULPI, | 241 | .phy_mode = FSL_USB2_PHY_ULPI, |
242 | }; | 242 | }; |
243 | 243 | ||
244 | static int otg_mode_host; | 244 | static bool otg_mode_host __initdata; |
245 | 245 | ||
246 | static int __init mx27_3ds_otg_mode(char *options) | 246 | static int __init mx27_3ds_otg_mode(char *options) |
247 | { | 247 | { |
248 | if (!strcmp(options, "host")) | 248 | if (!strcmp(options, "host")) |
249 | otg_mode_host = 1; | 249 | otg_mode_host = true; |
250 | else if (!strcmp(options, "device")) | 250 | else if (!strcmp(options, "device")) |
251 | otg_mode_host = 0; | 251 | otg_mode_host = false; |
252 | else | 252 | else |
253 | pr_info("otg_mode neither \"host\" nor \"device\". " | 253 | pr_info("otg_mode neither \"host\" nor \"device\". " |
254 | "Defaulting to device\n"); | 254 | "Defaulting to device\n"); |
255 | return 0; | 255 | return 1; |
256 | } | 256 | } |
257 | __setup("otg_mode=", mx27_3ds_otg_mode); | 257 | __setup("otg_mode=", mx27_3ds_otg_mode); |
258 | 258 | ||
@@ -480,7 +480,7 @@ static void __init mx27pdk_init(void) | |||
480 | imx27_add_fec(NULL); | 480 | imx27_add_fec(NULL); |
481 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); | 481 | imx27_add_imx_keypad(&mx27_3ds_keymap_data); |
482 | imx27_add_mxc_mmc(0, &sdhc1_pdata); | 482 | imx27_add_mxc_mmc(0, &sdhc1_pdata); |
483 | imx27_add_imx2_wdt(NULL); | 483 | imx27_add_imx2_wdt(); |
484 | otg_phy_init(); | 484 | otg_phy_init(); |
485 | 485 | ||
486 | if (otg_mode_host) { | 486 | if (otg_mode_host) { |
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c index 0228d2e07fe0..7936bb32264d 100644 --- a/arch/arm/mach-imx/mach-mx27ads.c +++ b/arch/arm/mach-imx/mach-mx27ads.c | |||
@@ -310,7 +310,7 @@ static void __init mx27ads_board_init(void) | |||
310 | 310 | ||
311 | imx27_add_fec(NULL); | 311 | imx27_add_fec(NULL); |
312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 312 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
313 | imx27_add_mxc_w1(NULL); | 313 | imx27_add_mxc_w1(); |
314 | } | 314 | } |
315 | 315 | ||
316 | static void __init mx27ads_timer_init(void) | 316 | static void __init mx27ads_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c index 4eafdf275ea2..928e1dcbc6a7 100644 --- a/arch/arm/mach-imx/mach-mx31_3ds.c +++ b/arch/arm/mach-imx/mach-mx31_3ds.c | |||
@@ -671,18 +671,18 @@ static const struct fsl_usb2_platform_data usbotg_pdata __initconst = { | |||
671 | .phy_mode = FSL_USB2_PHY_ULPI, | 671 | .phy_mode = FSL_USB2_PHY_ULPI, |
672 | }; | 672 | }; |
673 | 673 | ||
674 | static int otg_mode_host; | 674 | static bool otg_mode_host __initdata; |
675 | 675 | ||
676 | static int __init mx31_3ds_otg_mode(char *options) | 676 | static int __init mx31_3ds_otg_mode(char *options) |
677 | { | 677 | { |
678 | if (!strcmp(options, "host")) | 678 | if (!strcmp(options, "host")) |
679 | otg_mode_host = 1; | 679 | otg_mode_host = true; |
680 | else if (!strcmp(options, "device")) | 680 | else if (!strcmp(options, "device")) |
681 | otg_mode_host = 0; | 681 | otg_mode_host = false; |
682 | else | 682 | else |
683 | pr_info("otg_mode neither \"host\" nor \"device\". " | 683 | pr_info("otg_mode neither \"host\" nor \"device\". " |
684 | "Defaulting to device\n"); | 684 | "Defaulting to device\n"); |
685 | return 0; | 685 | return 1; |
686 | } | 686 | } |
687 | __setup("otg_mode=", mx31_3ds_otg_mode); | 687 | __setup("otg_mode=", mx31_3ds_otg_mode); |
688 | 688 | ||
@@ -739,7 +739,7 @@ static void __init mx31_3ds_init(void) | |||
739 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) | 739 | if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) |
740 | printk(KERN_WARNING "Init of the debug board failed, all " | 740 | printk(KERN_WARNING "Init of the debug board failed, all " |
741 | "devices on the debug board are unusable.\n"); | 741 | "devices on the debug board are unusable.\n"); |
742 | imx31_add_imx2_wdt(NULL); | 742 | imx31_add_imx2_wdt(); |
743 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); | 743 | imx31_add_imx_i2c0(&mx31_3ds_i2c0_data); |
744 | imx31_add_mxc_mmc(0, &sdhc1_pdata); | 744 | imx31_add_mxc_mmc(0, &sdhc1_pdata); |
745 | 745 | ||
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c index 016791f038b0..63e84e67b990 100644 --- a/arch/arm/mach-imx/mach-mx31moboard.c +++ b/arch/arm/mach-imx/mach-mx31moboard.c | |||
@@ -544,7 +544,7 @@ static void __init mx31moboard_init(void) | |||
544 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 544 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
545 | gpio_led_register_device(-1, &mx31moboard_led_pdata); | 545 | gpio_led_register_device(-1, &mx31moboard_led_pdata); |
546 | 546 | ||
547 | imx31_add_imx2_wdt(NULL); | 547 | imx31_add_imx2_wdt(); |
548 | 548 | ||
549 | imx31_add_imx_uart0(&uart0_pdata); | 549 | imx31_add_imx_uart0(&uart0_pdata); |
550 | imx31_add_imx_uart4(&uart4_pdata); | 550 | imx31_add_imx_uart4(&uart4_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c index 28aa19476de7..69018e5c52de 100644 --- a/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/arch/arm/mach-imx/mach-mx35_3ds.c | |||
@@ -540,18 +540,18 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = { | |||
540 | .portsc = MXC_EHCI_MODE_SERIAL, | 540 | .portsc = MXC_EHCI_MODE_SERIAL, |
541 | }; | 541 | }; |
542 | 542 | ||
543 | static int otg_mode_host; | 543 | static bool otg_mode_host __initdata; |
544 | 544 | ||
545 | static int __init mx35_3ds_otg_mode(char *options) | 545 | static int __init mx35_3ds_otg_mode(char *options) |
546 | { | 546 | { |
547 | if (!strcmp(options, "host")) | 547 | if (!strcmp(options, "host")) |
548 | otg_mode_host = 1; | 548 | otg_mode_host = true; |
549 | else if (!strcmp(options, "device")) | 549 | else if (!strcmp(options, "device")) |
550 | otg_mode_host = 0; | 550 | otg_mode_host = false; |
551 | else | 551 | else |
552 | pr_info("otg_mode neither \"host\" nor \"device\". " | 552 | pr_info("otg_mode neither \"host\" nor \"device\". " |
553 | "Defaulting to device\n"); | 553 | "Defaulting to device\n"); |
554 | return 0; | 554 | return 1; |
555 | } | 555 | } |
556 | __setup("otg_mode=", mx35_3ds_otg_mode); | 556 | __setup("otg_mode=", mx35_3ds_otg_mode); |
557 | 557 | ||
@@ -571,7 +571,8 @@ static void __init mx35_3ds_init(void) | |||
571 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); | 571 | mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); |
572 | 572 | ||
573 | imx35_add_fec(NULL); | 573 | imx35_add_fec(NULL); |
574 | imx35_add_imx2_wdt(NULL); | 574 | imx35_add_imx2_wdt(); |
575 | imx35_add_mxc_rtc(); | ||
575 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 576 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
576 | 577 | ||
577 | imx35_add_imx_uart0(&uart_pdata); | 578 | imx35_add_imx_uart0(&uart_pdata); |
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c index 3c5b163923f6..2edb563b968d 100644 --- a/arch/arm/mach-imx/mach-mx51_3ds.c +++ b/arch/arm/mach-imx/mach-mx51_3ds.c | |||
@@ -154,7 +154,7 @@ static void __init mx51_3ds_init(void) | |||
154 | 154 | ||
155 | imx51_add_sdhci_esdhc_imx(0, NULL); | 155 | imx51_add_sdhci_esdhc_imx(0, NULL); |
156 | imx51_add_imx_keypad(&mx51_3ds_map_data); | 156 | imx51_add_imx_keypad(&mx51_3ds_map_data); |
157 | imx51_add_imx2_wdt(0, NULL); | 157 | imx51_add_imx2_wdt(0); |
158 | } | 158 | } |
159 | 159 | ||
160 | static void __init mx51_3ds_timer_init(void) | 160 | static void __init mx51_3ds_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c index dde397014d4b..7b31cbde8775 100644 --- a/arch/arm/mach-imx/mach-mx51_babbage.c +++ b/arch/arm/mach-imx/mach-mx51_babbage.c | |||
@@ -307,18 +307,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = { | |||
307 | .portsc = MXC_EHCI_MODE_ULPI, | 307 | .portsc = MXC_EHCI_MODE_ULPI, |
308 | }; | 308 | }; |
309 | 309 | ||
310 | static int otg_mode_host; | 310 | static bool otg_mode_host __initdata; |
311 | 311 | ||
312 | static int __init babbage_otg_mode(char *options) | 312 | static int __init babbage_otg_mode(char *options) |
313 | { | 313 | { |
314 | if (!strcmp(options, "host")) | 314 | if (!strcmp(options, "host")) |
315 | otg_mode_host = 1; | 315 | otg_mode_host = true; |
316 | else if (!strcmp(options, "device")) | 316 | else if (!strcmp(options, "device")) |
317 | otg_mode_host = 0; | 317 | otg_mode_host = false; |
318 | else | 318 | else |
319 | pr_info("otg_mode neither \"host\" nor \"device\". " | 319 | pr_info("otg_mode neither \"host\" nor \"device\". " |
320 | "Defaulting to device\n"); | 320 | "Defaulting to device\n"); |
321 | return 0; | 321 | return 1; |
322 | } | 322 | } |
323 | __setup("otg_mode=", babbage_otg_mode); | 323 | __setup("otg_mode=", babbage_otg_mode); |
324 | 324 | ||
@@ -411,7 +411,7 @@ static void __init mx51_babbage_init(void) | |||
411 | spi_register_board_info(mx51_babbage_spi_board_info, | 411 | spi_register_board_info(mx51_babbage_spi_board_info, |
412 | ARRAY_SIZE(mx51_babbage_spi_board_info)); | 412 | ARRAY_SIZE(mx51_babbage_spi_board_info)); |
413 | imx51_add_ecspi(0, &mx51_babbage_spi_pdata); | 413 | imx51_add_ecspi(0, &mx51_babbage_spi_pdata); |
414 | imx51_add_imx2_wdt(0, NULL); | 414 | imx51_add_imx2_wdt(0); |
415 | } | 415 | } |
416 | 416 | ||
417 | static void __init mx51_babbage_timer_init(void) | 417 | static void __init mx51_babbage_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c index 05641980dc5e..4a7593a953e2 100644 --- a/arch/arm/mach-imx/mach-mx53_ard.c +++ b/arch/arm/mach-imx/mach-mx53_ard.c | |||
@@ -243,7 +243,7 @@ static void __init mx53_ard_board_init(void) | |||
243 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 243 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
244 | 244 | ||
245 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); | 245 | imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); |
246 | imx53_add_imx2_wdt(0, NULL); | 246 | imx53_add_imx2_wdt(0); |
247 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); | 247 | imx53_add_imx_i2c(1, &mx53_ard_i2c2_data); |
248 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); | 248 | imx53_add_imx_i2c(2, &mx53_ard_i2c3_data); |
249 | imx_add_gpio_keys(&ard_button_data); | 249 | imx_add_gpio_keys(&ard_button_data); |
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c index 5a72188b9cdb..a1060b26fb23 100644 --- a/arch/arm/mach-imx/mach-mx53_evk.c +++ b/arch/arm/mach-imx/mach-mx53_evk.c | |||
@@ -154,7 +154,7 @@ static void __init mx53_evk_board_init(void) | |||
154 | spi_register_board_info(mx53_evk_spi_board_info, | 154 | spi_register_board_info(mx53_evk_spi_board_info, |
155 | ARRAY_SIZE(mx53_evk_spi_board_info)); | 155 | ARRAY_SIZE(mx53_evk_spi_board_info)); |
156 | imx53_add_ecspi(0, &mx53_evk_spi_data); | 156 | imx53_add_ecspi(0, &mx53_evk_spi_data); |
157 | imx53_add_imx2_wdt(0, NULL); | 157 | imx53_add_imx2_wdt(0); |
158 | gpio_led_register_device(-1, &mx53evk_leds_data); | 158 | gpio_led_register_device(-1, &mx53evk_leds_data); |
159 | } | 159 | } |
160 | 160 | ||
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c index 37f67cac15a4..388c415d6b62 100644 --- a/arch/arm/mach-imx/mach-mx53_loco.c +++ b/arch/arm/mach-imx/mach-mx53_loco.c | |||
@@ -283,7 +283,7 @@ static void __init mx53_loco_board_init(void) | |||
283 | imx53_add_imx_uart(0, NULL); | 283 | imx53_add_imx_uart(0, NULL); |
284 | mx53_loco_fec_reset(); | 284 | mx53_loco_fec_reset(); |
285 | imx53_add_fec(&mx53_loco_fec_data); | 285 | imx53_add_fec(&mx53_loco_fec_data); |
286 | imx53_add_imx2_wdt(0, NULL); | 286 | imx53_add_imx2_wdt(0); |
287 | 287 | ||
288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); | 288 | ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en"); |
289 | if (ret) | 289 | if (ret) |
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c index 8e972c5c3e13..f297df7ccb39 100644 --- a/arch/arm/mach-imx/mach-mx53_smd.c +++ b/arch/arm/mach-imx/mach-mx53_smd.c | |||
@@ -138,7 +138,7 @@ static void __init mx53_smd_board_init(void) | |||
138 | mx53_smd_init_uart(); | 138 | mx53_smd_init_uart(); |
139 | mx53_smd_fec_reset(); | 139 | mx53_smd_fec_reset(); |
140 | imx53_add_fec(&mx53_smd_fec_data); | 140 | imx53_add_fec(&mx53_smd_fec_data); |
141 | imx53_add_imx2_wdt(0, NULL); | 141 | imx53_add_imx2_wdt(0); |
142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); | 142 | imx53_add_imx_i2c(0, &mx53_smd_i2c_data); |
143 | imx53_add_sdhci_esdhc_imx(0, NULL); | 143 | imx53_add_sdhci_esdhc_imx(0, NULL); |
144 | imx53_add_sdhci_esdhc_imx(1, NULL); | 144 | imx53_add_sdhci_esdhc_imx(1, NULL); |
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c index 541152e450c4..d37ed25003b2 100644 --- a/arch/arm/mach-imx/mach-pca100.c +++ b/arch/arm/mach-imx/mach-pca100.c | |||
@@ -298,18 +298,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
298 | .phy_mode = FSL_USB2_PHY_ULPI, | 298 | .phy_mode = FSL_USB2_PHY_ULPI, |
299 | }; | 299 | }; |
300 | 300 | ||
301 | static int otg_mode_host; | 301 | static bool otg_mode_host __initdata; |
302 | 302 | ||
303 | static int __init pca100_otg_mode(char *options) | 303 | static int __init pca100_otg_mode(char *options) |
304 | { | 304 | { |
305 | if (!strcmp(options, "host")) | 305 | if (!strcmp(options, "host")) |
306 | otg_mode_host = 1; | 306 | otg_mode_host = true; |
307 | else if (!strcmp(options, "device")) | 307 | else if (!strcmp(options, "device")) |
308 | otg_mode_host = 0; | 308 | otg_mode_host = false; |
309 | else | 309 | else |
310 | pr_info("otg_mode neither \"host\" nor \"device\". " | 310 | pr_info("otg_mode neither \"host\" nor \"device\". " |
311 | "Defaulting to device\n"); | 311 | "Defaulting to device\n"); |
312 | return 0; | 312 | return 1; |
313 | } | 313 | } |
314 | __setup("otg_mode=", pca100_otg_mode); | 314 | __setup("otg_mode=", pca100_otg_mode); |
315 | 315 | ||
@@ -408,8 +408,8 @@ static void __init pca100_init(void) | |||
408 | imx27_add_imx_fb(&pca100_fb_data); | 408 | imx27_add_imx_fb(&pca100_fb_data); |
409 | 409 | ||
410 | imx27_add_fec(NULL); | 410 | imx27_add_fec(NULL); |
411 | imx27_add_imx2_wdt(NULL); | 411 | imx27_add_imx2_wdt(); |
412 | imx27_add_mxc_w1(NULL); | 412 | imx27_add_mxc_w1(); |
413 | } | 413 | } |
414 | 414 | ||
415 | static void __init pca100_timer_init(void) | 415 | static void __init pca100_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c index 0a40004154f2..cd48712a6f50 100644 --- a/arch/arm/mach-imx/mach-pcm037.c +++ b/arch/arm/mach-imx/mach-pcm037.c | |||
@@ -557,18 +557,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
557 | .phy_mode = FSL_USB2_PHY_ULPI, | 557 | .phy_mode = FSL_USB2_PHY_ULPI, |
558 | }; | 558 | }; |
559 | 559 | ||
560 | static int otg_mode_host; | 560 | static bool otg_mode_host __initdata; |
561 | 561 | ||
562 | static int __init pcm037_otg_mode(char *options) | 562 | static int __init pcm037_otg_mode(char *options) |
563 | { | 563 | { |
564 | if (!strcmp(options, "host")) | 564 | if (!strcmp(options, "host")) |
565 | otg_mode_host = 1; | 565 | otg_mode_host = true; |
566 | else if (!strcmp(options, "device")) | 566 | else if (!strcmp(options, "device")) |
567 | otg_mode_host = 0; | 567 | otg_mode_host = false; |
568 | else | 568 | else |
569 | pr_info("otg_mode neither \"host\" nor \"device\". " | 569 | pr_info("otg_mode neither \"host\" nor \"device\". " |
570 | "Defaulting to device\n"); | 570 | "Defaulting to device\n"); |
571 | return 0; | 571 | return 1; |
572 | } | 572 | } |
573 | __setup("otg_mode=", pcm037_otg_mode); | 573 | __setup("otg_mode=", pcm037_otg_mode); |
574 | 574 | ||
@@ -619,13 +619,13 @@ static void __init pcm037_init(void) | |||
619 | 619 | ||
620 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 620 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
621 | 621 | ||
622 | imx31_add_imx2_wdt(NULL); | 622 | imx31_add_imx2_wdt(); |
623 | imx31_add_imx_uart0(&uart_pdata); | 623 | imx31_add_imx_uart0(&uart_pdata); |
624 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ | 624 | /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ |
625 | imx31_add_imx_uart1(&uart_pdata); | 625 | imx31_add_imx_uart1(&uart_pdata); |
626 | imx31_add_imx_uart2(&uart_pdata); | 626 | imx31_add_imx_uart2(&uart_pdata); |
627 | 627 | ||
628 | imx31_add_mxc_w1(NULL); | 628 | imx31_add_mxc_w1(); |
629 | 629 | ||
630 | /* LAN9217 IRQ pin */ | 630 | /* LAN9217 IRQ pin */ |
631 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); | 631 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); |
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index 2f3debe2a113..3fbb89d74fcc 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
@@ -332,8 +332,8 @@ static void __init pcm038_init(void) | |||
332 | 332 | ||
333 | imx27_add_fec(NULL); | 333 | imx27_add_fec(NULL); |
334 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 334 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
335 | imx27_add_imx2_wdt(NULL); | 335 | imx27_add_imx2_wdt(); |
336 | imx27_add_mxc_w1(NULL); | 336 | imx27_add_mxc_w1(); |
337 | 337 | ||
338 | #ifdef CONFIG_MACH_PCM970_BASEBOARD | 338 | #ifdef CONFIG_MACH_PCM970_BASEBOARD |
339 | pcm970_baseboard_init(); | 339 | pcm970_baseboard_init(); |
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c index 73585f55cca0..1f20f222375e 100644 --- a/arch/arm/mach-imx/mach-pcm043.c +++ b/arch/arm/mach-imx/mach-pcm043.c | |||
@@ -330,18 +330,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { | |||
330 | .phy_mode = FSL_USB2_PHY_UTMI, | 330 | .phy_mode = FSL_USB2_PHY_UTMI, |
331 | }; | 331 | }; |
332 | 332 | ||
333 | static int otg_mode_host; | 333 | static bool otg_mode_host __initdata; |
334 | 334 | ||
335 | static int __init pcm043_otg_mode(char *options) | 335 | static int __init pcm043_otg_mode(char *options) |
336 | { | 336 | { |
337 | if (!strcmp(options, "host")) | 337 | if (!strcmp(options, "host")) |
338 | otg_mode_host = 1; | 338 | otg_mode_host = true; |
339 | else if (!strcmp(options, "device")) | 339 | else if (!strcmp(options, "device")) |
340 | otg_mode_host = 0; | 340 | otg_mode_host = false; |
341 | else | 341 | else |
342 | pr_info("otg_mode neither \"host\" nor \"device\". " | 342 | pr_info("otg_mode neither \"host\" nor \"device\". " |
343 | "Defaulting to device\n"); | 343 | "Defaulting to device\n"); |
344 | return 0; | 344 | return 1; |
345 | } | 345 | } |
346 | __setup("otg_mode=", pcm043_otg_mode); | 346 | __setup("otg_mode=", pcm043_otg_mode); |
347 | 347 | ||
@@ -363,7 +363,7 @@ static void __init pcm043_init(void) | |||
363 | 363 | ||
364 | imx35_add_fec(NULL); | 364 | imx35_add_fec(NULL); |
365 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 365 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
366 | imx35_add_imx2_wdt(NULL); | 366 | imx35_add_imx2_wdt(); |
367 | 367 | ||
368 | imx35_add_imx_uart0(&uart_pdata); | 368 | imx35_add_imx_uart0(&uart_pdata); |
369 | imx35_add_mxc_nand(&pcm037_nand_board_info); | 369 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c index 260621055b6b..a13087b11a6e 100644 --- a/arch/arm/mach-imx/mach-qong.c +++ b/arch/arm/mach-imx/mach-qong.c | |||
@@ -252,7 +252,7 @@ static void __init qong_init(void) | |||
252 | mxc_init_imx_uart(); | 252 | mxc_init_imx_uart(); |
253 | qong_init_nor_mtd(); | 253 | qong_init_nor_mtd(); |
254 | qong_init_fpga(); | 254 | qong_init_fpga(); |
255 | imx31_add_imx2_wdt(NULL); | 255 | imx31_add_imx2_wdt(); |
256 | } | 256 | } |
257 | 257 | ||
258 | static void __init qong_timer_init(void) | 258 | static void __init qong_timer_init(void) |
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c index add8c69c6c1a..b26209d4bcef 100644 --- a/arch/arm/mach-imx/mach-vpr200.c +++ b/arch/arm/mach-imx/mach-vpr200.c | |||
@@ -272,7 +272,7 @@ static void __init vpr200_board_init(void) | |||
272 | mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); | 272 | mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads)); |
273 | 273 | ||
274 | imx35_add_fec(NULL); | 274 | imx35_add_fec(NULL); |
275 | imx35_add_imx2_wdt(NULL); | 275 | imx35_add_imx2_wdt(); |
276 | imx_add_gpio_keys(&vpr200_gpio_keys_data); | 276 | imx_add_gpio_keys(&vpr200_gpio_keys_data); |
277 | 277 | ||
278 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 278 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c index bf0fb87946ba..fa60ef6ac7ff 100644 --- a/arch/arm/mach-imx/mx31lite-db.c +++ b/arch/arm/mach-imx/mx31lite-db.c | |||
@@ -191,6 +191,6 @@ void __init mx31lite_db_init(void) | |||
191 | imx31_add_mxc_mmc(0, &mmc_pdata); | 191 | imx31_add_mxc_mmc(0, &mmc_pdata); |
192 | imx31_add_spi_imx0(&spi0_pdata); | 192 | imx31_add_spi_imx0(&spi0_pdata); |
193 | gpio_led_register_device(-1, &litekit_led_platform_data); | 193 | gpio_led_register_device(-1, &litekit_led_platform_data); |
194 | imx31_add_imx2_wdt(NULL); | 194 | imx31_add_imx2_wdt(); |
195 | imx31_add_mxc_rtc(NULL); | 195 | imx31_add_mxc_rtc(); |
196 | } | 196 | } |
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig deleted file mode 100644 index e0b3eee83834..000000000000 --- a/arch/arm/mach-lpc32xx/Kconfig +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | if ARCH_LPC32XX | ||
2 | |||
3 | menu "Individual UART enable selections" | ||
4 | |||
5 | config ARCH_LPC32XX_UART3_SELECT | ||
6 | bool "Add support for standard UART3" | ||
7 | help | ||
8 | Adds support for standard UART 3 when the 8250 serial support | ||
9 | is enabled. | ||
10 | |||
11 | config ARCH_LPC32XX_UART4_SELECT | ||
12 | bool "Add support for standard UART4" | ||
13 | help | ||
14 | Adds support for standard UART 4 when the 8250 serial support | ||
15 | is enabled. | ||
16 | |||
17 | config ARCH_LPC32XX_UART5_SELECT | ||
18 | bool "Add support for standard UART5" | ||
19 | default y | ||
20 | help | ||
21 | Adds support for standard UART 5 when the 8250 serial support | ||
22 | is enabled. | ||
23 | |||
24 | config ARCH_LPC32XX_UART6_SELECT | ||
25 | bool "Add support for standard UART6" | ||
26 | help | ||
27 | Adds support for standard UART 6 when the 8250 serial support | ||
28 | is enabled. | ||
29 | |||
30 | endmenu | ||
31 | |||
32 | endif | ||
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot index 2cfe0ee635c5..697323b5f92d 100644 --- a/arch/arm/mach-lpc32xx/Makefile.boot +++ b/arch/arm/mach-lpc32xx/Makefile.boot | |||
@@ -2,3 +2,4 @@ | |||
2 | params_phys-y := 0x80000100 | 2 | params_phys-y := 0x80000100 |
3 | initrd_phys-y := 0x82000000 | 3 | initrd_phys-y := 0x82000000 |
4 | 4 | ||
5 | dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb | ||
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c index f6a3ffec1f4b..f48c2e961b84 100644 --- a/arch/arm/mach-lpc32xx/clock.c +++ b/arch/arm/mach-lpc32xx/clock.c | |||
@@ -607,6 +607,19 @@ static struct clk clk_dma = { | |||
607 | .get_rate = local_return_parent_rate, | 607 | .get_rate = local_return_parent_rate, |
608 | }; | 608 | }; |
609 | 609 | ||
610 | static struct clk clk_pwm = { | ||
611 | .parent = &clk_pclk, | ||
612 | .enable = local_onoff_enable, | ||
613 | .enable_reg = LPC32XX_CLKPWR_PWM_CLK_CTRL, | ||
614 | .enable_mask = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN | | ||
615 | LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK | | ||
616 | LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) | | ||
617 | LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN | | ||
618 | LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK | | ||
619 | LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1), | ||
620 | .get_rate = local_return_parent_rate, | ||
621 | }; | ||
622 | |||
610 | static struct clk clk_uart3 = { | 623 | static struct clk clk_uart3 = { |
611 | .parent = &clk_pclk, | 624 | .parent = &clk_pclk, |
612 | .enable = local_onoff_enable, | 625 | .enable = local_onoff_enable, |
@@ -691,10 +704,21 @@ static struct clk clk_nand = { | |||
691 | .parent = &clk_hclk, | 704 | .parent = &clk_hclk, |
692 | .enable = local_onoff_enable, | 705 | .enable = local_onoff_enable, |
693 | .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, | 706 | .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, |
694 | .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, | 707 | .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN | |
708 | LPC32XX_CLKPWR_NANDCLK_SEL_SLC, | ||
695 | .get_rate = local_return_parent_rate, | 709 | .get_rate = local_return_parent_rate, |
696 | }; | 710 | }; |
697 | 711 | ||
712 | static struct clk clk_nand_mlc = { | ||
713 | .parent = &clk_hclk, | ||
714 | .enable = local_onoff_enable, | ||
715 | .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, | ||
716 | .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN | | ||
717 | LPC32XX_CLKPWR_NANDCLK_DMA_INT | | ||
718 | LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC, | ||
719 | .get_rate = local_return_parent_rate, | ||
720 | }; | ||
721 | |||
698 | static struct clk clk_i2s0 = { | 722 | static struct clk clk_i2s0 = { |
699 | .parent = &clk_hclk, | 723 | .parent = &clk_hclk, |
700 | .enable = local_onoff_enable, | 724 | .enable = local_onoff_enable, |
@@ -707,7 +731,8 @@ static struct clk clk_i2s1 = { | |||
707 | .parent = &clk_hclk, | 731 | .parent = &clk_hclk, |
708 | .enable = local_onoff_enable, | 732 | .enable = local_onoff_enable, |
709 | .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, | 733 | .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, |
710 | .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, | 734 | .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN | |
735 | LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA, | ||
711 | .get_rate = local_return_parent_rate, | 736 | .get_rate = local_return_parent_rate, |
712 | }; | 737 | }; |
713 | 738 | ||
@@ -727,14 +752,77 @@ static struct clk clk_rtc = { | |||
727 | .get_rate = local_return_parent_rate, | 752 | .get_rate = local_return_parent_rate, |
728 | }; | 753 | }; |
729 | 754 | ||
755 | static int local_usb_enable(struct clk *clk, int enable) | ||
756 | { | ||
757 | u32 tmp; | ||
758 | |||
759 | if (enable) { | ||
760 | /* Set up I2C pull levels */ | ||
761 | tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
762 | tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE; | ||
763 | __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
764 | } | ||
765 | |||
766 | return local_onoff_enable(clk, enable); | ||
767 | } | ||
768 | |||
730 | static struct clk clk_usbd = { | 769 | static struct clk clk_usbd = { |
731 | .parent = &clk_usbpll, | 770 | .parent = &clk_usbpll, |
732 | .enable = local_onoff_enable, | 771 | .enable = local_usb_enable, |
733 | .enable_reg = LPC32XX_CLKPWR_USB_CTRL, | 772 | .enable_reg = LPC32XX_CLKPWR_USB_CTRL, |
734 | .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, | 773 | .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, |
735 | .get_rate = local_return_parent_rate, | 774 | .get_rate = local_return_parent_rate, |
736 | }; | 775 | }; |
737 | 776 | ||
777 | #define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \ | ||
778 | LPC32XX_USB_OTG_I2C_CLOCK_ON) | ||
779 | |||
780 | static int local_usb_otg_enable(struct clk *clk, int enable) | ||
781 | { | ||
782 | int to = 1000; | ||
783 | |||
784 | if (enable) { | ||
785 | __raw_writel(clk->enable_mask, clk->enable_reg); | ||
786 | |||
787 | while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & | ||
788 | clk->enable_mask) != clk->enable_mask) && (to > 0)) | ||
789 | to--; | ||
790 | } else { | ||
791 | __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); | ||
792 | |||
793 | while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & | ||
794 | OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0)) | ||
795 | to--; | ||
796 | } | ||
797 | |||
798 | if (to) | ||
799 | return 0; | ||
800 | else | ||
801 | return -1; | ||
802 | } | ||
803 | |||
804 | static struct clk clk_usb_otg_dev = { | ||
805 | .parent = &clk_usbpll, | ||
806 | .enable = local_usb_otg_enable, | ||
807 | .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, | ||
808 | .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | | ||
809 | LPC32XX_USB_OTG_OTG_CLOCK_ON | | ||
810 | LPC32XX_USB_OTG_DEV_CLOCK_ON | | ||
811 | LPC32XX_USB_OTG_I2C_CLOCK_ON, | ||
812 | .get_rate = local_return_parent_rate, | ||
813 | }; | ||
814 | |||
815 | static struct clk clk_usb_otg_host = { | ||
816 | .parent = &clk_usbpll, | ||
817 | .enable = local_usb_otg_enable, | ||
818 | .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, | ||
819 | .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | | ||
820 | LPC32XX_USB_OTG_OTG_CLOCK_ON | | ||
821 | LPC32XX_USB_OTG_HOST_CLOCK_ON | | ||
822 | LPC32XX_USB_OTG_I2C_CLOCK_ON, | ||
823 | .get_rate = local_return_parent_rate, | ||
824 | }; | ||
825 | |||
738 | static int tsc_onoff_enable(struct clk *clk, int enable) | 826 | static int tsc_onoff_enable(struct clk *clk, int enable) |
739 | { | 827 | { |
740 | u32 tmp; | 828 | u32 tmp; |
@@ -800,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable) | |||
800 | u32 tmp; | 888 | u32 tmp; |
801 | 889 | ||
802 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & | 890 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & |
803 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | 891 | ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | |
892 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN | | ||
893 | LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS | | ||
894 | LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS | | ||
895 | LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS | | ||
896 | LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS); | ||
804 | 897 | ||
805 | /* If rate is 0, disable clock */ | 898 | /* If rate is 0, disable clock */ |
806 | if (enable != 0) | 899 | if (enable != 0) |
807 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | 900 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | |
901 | LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; | ||
808 | 902 | ||
809 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | 903 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); |
810 | 904 | ||
@@ -853,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) | |||
853 | 947 | ||
854 | static int mmc_set_rate(struct clk *clk, unsigned long rate) | 948 | static int mmc_set_rate(struct clk *clk, unsigned long rate) |
855 | { | 949 | { |
856 | u32 oldclk, tmp; | 950 | u32 tmp; |
857 | unsigned long prate, div, crate = mmc_round_rate(clk, rate); | 951 | unsigned long prate, div, crate = mmc_round_rate(clk, rate); |
858 | 952 | ||
859 | prate = clk->parent->get_rate(clk->parent); | 953 | prate = clk->parent->get_rate(clk->parent); |
@@ -861,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate) | |||
861 | div = prate / crate; | 955 | div = prate / crate; |
862 | 956 | ||
863 | /* The MMC clock must be on when accessing an MMC register */ | 957 | /* The MMC clock must be on when accessing an MMC register */ |
864 | oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); | ||
865 | __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, | ||
866 | LPC32XX_CLKPWR_MS_CTRL); | ||
867 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & | 958 | tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & |
868 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); | 959 | ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); |
869 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); | 960 | tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | |
961 | LPC32XX_CLKPWR_MSCARD_SDCARD_EN; | ||
870 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); | 962 | __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); |
871 | 963 | ||
872 | __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); | ||
873 | |||
874 | return 0; | 964 | return 0; |
875 | } | 965 | } |
876 | 966 | ||
@@ -1111,6 +1201,7 @@ static struct clk_lookup lookups[] = { | |||
1111 | CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), | 1201 | CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9), |
1112 | CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), | 1202 | CLKDEV_INIT("pl08xdmac", NULL, &clk_dma), |
1113 | CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), | 1203 | CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt), |
1204 | CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm), | ||
1114 | CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), | 1205 | CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3), |
1115 | CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), | 1206 | CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4), |
1116 | CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), | 1207 | CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5), |
@@ -1120,8 +1211,9 @@ static struct clk_lookup lookups[] = { | |||
1120 | CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), | 1211 | CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), |
1121 | CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), | 1212 | CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), |
1122 | CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), | 1213 | CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), |
1123 | CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), | 1214 | CLKDEV_INIT("40050000.key", NULL, &clk_kscan), |
1124 | CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), | 1215 | CLKDEV_INIT("20020000.flash", NULL, &clk_nand), |
1216 | CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc), | ||
1125 | CLKDEV_INIT("40048000.adc", NULL, &clk_adc), | 1217 | CLKDEV_INIT("40048000.adc", NULL, &clk_adc), |
1126 | CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), | 1218 | CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), |
1127 | CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), | 1219 | CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), |
@@ -1130,6 +1222,9 @@ static struct clk_lookup lookups[] = { | |||
1130 | CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), | 1222 | CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), |
1131 | CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), | 1223 | CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), |
1132 | CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), | 1224 | CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), |
1225 | CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd), | ||
1226 | CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev), | ||
1227 | CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host), | ||
1133 | CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), | 1228 | CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), |
1134 | }; | 1229 | }; |
1135 | 1230 | ||
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c index 5c96057b6d78..a48dc2dec485 100644 --- a/arch/arm/mach-lpc32xx/common.c +++ b/arch/arm/mach-lpc32xx/common.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | 27 | ||
28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
29 | #include <asm/system_info.h> | ||
29 | 30 | ||
30 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
31 | #include <mach/platform.h> | 32 | #include <mach/platform.h> |
@@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd) | |||
224 | ; | 225 | ; |
225 | } | 226 | } |
226 | 227 | ||
227 | static int __init lpc32xx_display_uid(void) | 228 | static int __init lpc32xx_check_uid(void) |
228 | { | 229 | { |
229 | u32 uid[4]; | 230 | u32 uid[4]; |
230 | 231 | ||
@@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void) | |||
233 | printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", | 234 | printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n", |
234 | uid[3], uid[2], uid[1], uid[0]); | 235 | uid[3], uid[2], uid[1], uid[0]); |
235 | 236 | ||
237 | if (!system_serial_low && !system_serial_high) { | ||
238 | system_serial_low = uid[0]; | ||
239 | system_serial_high = uid[1]; | ||
240 | } | ||
241 | |||
236 | return 1; | 242 | return 1; |
237 | } | 243 | } |
238 | arch_initcall(lpc32xx_display_uid); | 244 | arch_initcall(lpc32xx_check_uid); |
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h index 2ba6ca412bef..0052e7a76179 100644 --- a/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h | |||
@@ -3,6 +3,4 @@ | |||
3 | 3 | ||
4 | #include "gpio-lpc32xx.h" | 4 | #include "gpio-lpc32xx.h" |
5 | 5 | ||
6 | #define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX) | ||
7 | |||
8 | #endif /* __MACH_GPIO_H */ | 6 | #endif /* __MACH_GPIO_H */ |
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h index c584f5bb164f..acc4aabf1c7b 100644 --- a/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/arch/arm/mach-lpc32xx/include/mach/platform.h | |||
@@ -694,4 +694,18 @@ | |||
694 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) | 694 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) |
695 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) | 695 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) |
696 | 696 | ||
697 | /* | ||
698 | * USB Otg Registers | ||
699 | */ | ||
700 | #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) | ||
701 | #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) | ||
702 | #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) | ||
703 | |||
704 | /* USB OTG CLK CTRL bit defines */ | ||
705 | #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) | ||
706 | #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) | ||
707 | #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) | ||
708 | #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) | ||
709 | #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) | ||
710 | |||
697 | #endif | 711 | #endif |
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c index 540106cdb9ec..b07dcc90829d 100644 --- a/arch/arm/mach-lpc32xx/phy3250.c +++ b/arch/arm/mach-lpc32xx/phy3250.c | |||
@@ -30,12 +30,13 @@ | |||
30 | #include <linux/amba/bus.h> | 30 | #include <linux/amba/bus.h> |
31 | #include <linux/amba/clcd.h> | 31 | #include <linux/amba/clcd.h> |
32 | #include <linux/amba/pl022.h> | 32 | #include <linux/amba/pl022.h> |
33 | #include <linux/amba/pl08x.h> | ||
34 | #include <linux/amba/mmci.h> | ||
33 | #include <linux/of.h> | 35 | #include <linux/of.h> |
34 | #include <linux/of_address.h> | 36 | #include <linux/of_address.h> |
35 | #include <linux/of_irq.h> | 37 | #include <linux/of_irq.h> |
36 | #include <linux/of_platform.h> | 38 | #include <linux/of_platform.h> |
37 | #include <linux/clk.h> | 39 | #include <linux/clk.h> |
38 | #include <linux/amba/pl08x.h> | ||
39 | 40 | ||
40 | #include <asm/setup.h> | 41 | #include <asm/setup.h> |
41 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
@@ -50,9 +51,9 @@ | |||
50 | /* | 51 | /* |
51 | * Mapped GPIOLIB GPIOs | 52 | * Mapped GPIOLIB GPIOs |
52 | */ | 53 | */ |
53 | #define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) | 54 | #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) |
54 | #define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) | 55 | #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) |
55 | #define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) | 56 | #define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) |
56 | 57 | ||
57 | /* | 58 | /* |
58 | * AMBA LCD controller | 59 | * AMBA LCD controller |
@@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = { | |||
158 | /* | 159 | /* |
159 | * AMBA SSP (SPI) | 160 | * AMBA SSP (SPI) |
160 | */ | 161 | */ |
161 | static void phy3250_spi_cs_set(u32 control) | ||
162 | { | ||
163 | gpio_set_value(SPI0_CS_GPIO, (int) control); | ||
164 | } | ||
165 | |||
166 | static struct pl022_config_chip spi0_chip_info = { | ||
167 | .com_mode = INTERRUPT_TRANSFER, | ||
168 | .iface = SSP_INTERFACE_MOTOROLA_SPI, | ||
169 | .hierarchy = SSP_MASTER, | ||
170 | .slave_tx_disable = 0, | ||
171 | .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, | ||
172 | .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, | ||
173 | .ctrl_len = SSP_BITS_8, | ||
174 | .wait_state = SSP_MWIRE_WAIT_ZERO, | ||
175 | .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, | ||
176 | .cs_control = phy3250_spi_cs_set, | ||
177 | }; | ||
178 | |||
179 | static struct pl022_ssp_controller lpc32xx_ssp0_data = { | 162 | static struct pl022_ssp_controller lpc32xx_ssp0_data = { |
180 | .bus_id = 0, | 163 | .bus_id = 0, |
181 | .num_chipselect = 1, | 164 | .num_chipselect = 1, |
@@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = { | |||
188 | .enable_dma = 0, | 171 | .enable_dma = 0, |
189 | }; | 172 | }; |
190 | 173 | ||
191 | /* AT25 driver registration */ | 174 | static struct pl08x_channel_data pl08x_slave_channels[] = { |
192 | static int __init phy3250_spi_board_register(void) | 175 | { |
176 | .bus_id = "nand-slc", | ||
177 | .min_signal = 1, /* SLC NAND Flash */ | ||
178 | .max_signal = 1, | ||
179 | .periph_buses = PL08X_AHB1, | ||
180 | }, | ||
181 | { | ||
182 | .bus_id = "nand-mlc", | ||
183 | .min_signal = 12, /* MLC NAND Flash */ | ||
184 | .max_signal = 12, | ||
185 | .periph_buses = PL08X_AHB1, | ||
186 | }, | ||
187 | }; | ||
188 | |||
189 | static int pl08x_get_signal(const struct pl08x_channel_data *cd) | ||
190 | { | ||
191 | return cd->min_signal; | ||
192 | } | ||
193 | |||
194 | static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) | ||
193 | { | 195 | { |
194 | #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) | ||
195 | static struct spi_board_info info[] = { | ||
196 | { | ||
197 | .modalias = "spidev", | ||
198 | .max_speed_hz = 5000000, | ||
199 | .bus_num = 0, | ||
200 | .chip_select = 0, | ||
201 | .controller_data = &spi0_chip_info, | ||
202 | }, | ||
203 | }; | ||
204 | |||
205 | #else | ||
206 | static struct spi_eeprom eeprom = { | ||
207 | .name = "at25256a", | ||
208 | .byte_len = 0x8000, | ||
209 | .page_size = 64, | ||
210 | .flags = EE_ADDR2, | ||
211 | }; | ||
212 | |||
213 | static struct spi_board_info info[] = { | ||
214 | { | ||
215 | .modalias = "at25", | ||
216 | .max_speed_hz = 5000000, | ||
217 | .bus_num = 0, | ||
218 | .chip_select = 0, | ||
219 | .mode = SPI_MODE_0, | ||
220 | .platform_data = &eeprom, | ||
221 | .controller_data = &spi0_chip_info, | ||
222 | }, | ||
223 | }; | ||
224 | #endif | ||
225 | return spi_register_board_info(info, ARRAY_SIZE(info)); | ||
226 | } | 196 | } |
227 | arch_initcall(phy3250_spi_board_register); | ||
228 | 197 | ||
229 | static struct pl08x_platform_data pl08x_pd = { | 198 | static struct pl08x_platform_data pl08x_pd = { |
199 | .slave_channels = &pl08x_slave_channels[0], | ||
200 | .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), | ||
201 | .get_signal = pl08x_get_signal, | ||
202 | .put_signal = pl08x_put_signal, | ||
203 | .lli_buses = PL08X_AHB1, | ||
204 | .mem_buses = PL08X_AHB1, | ||
205 | }; | ||
206 | |||
207 | static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios) | ||
208 | { | ||
209 | /* Only on and off are supported */ | ||
210 | if (ios->power_mode == MMC_POWER_OFF) | ||
211 | gpio_set_value(MMC_PWR_ENABLE_GPIO, 0); | ||
212 | else | ||
213 | gpio_set_value(MMC_PWR_ENABLE_GPIO, 1); | ||
214 | return 0; | ||
215 | } | ||
216 | |||
217 | static struct mmci_platform_data lpc32xx_mmci_data = { | ||
218 | .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 | | ||
219 | MMC_VDD_32_33 | MMC_VDD_33_34, | ||
220 | .ios_handler = mmc_handle_ios, | ||
221 | .dma_filter = NULL, | ||
222 | /* No DMA for now since AMBA PL080 dmaengine driver only does scatter | ||
223 | * gather, and the MMCI driver doesn't do it this way */ | ||
230 | }; | 224 | }; |
231 | 225 | ||
232 | static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { | 226 | static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { |
@@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { | |||
234 | OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), | 228 | OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), |
235 | OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), | 229 | OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), |
236 | OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), | 230 | OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), |
231 | OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", | ||
232 | &lpc32xx_mmci_data), | ||
237 | { } | 233 | { } |
238 | }; | 234 | }; |
239 | 235 | ||
@@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void) | |||
241 | { | 237 | { |
242 | u32 tmp; | 238 | u32 tmp; |
243 | 239 | ||
244 | /* Setup SLC NAND controller muxing */ | ||
245 | __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, | ||
246 | LPC32XX_CLKPWR_NAND_CLK_CTRL); | ||
247 | |||
248 | /* Setup LCD muxing to RGB565 */ | 240 | /* Setup LCD muxing to RGB565 */ |
249 | tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & | 241 | tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & |
250 | ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | | 242 | ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | |
@@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void) | |||
252 | tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; | 244 | tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; |
253 | __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); | 245 | __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); |
254 | 246 | ||
255 | /* Set up USB power */ | ||
256 | tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); | ||
257 | tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | | ||
258 | LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; | ||
259 | __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); | ||
260 | |||
261 | /* Set up I2C pull levels */ | ||
262 | tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
263 | tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | | ||
264 | LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; | ||
265 | __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); | ||
266 | |||
267 | /* Disable IrDA pulsing support on UART6 */ | ||
268 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); | ||
269 | tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; | ||
270 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); | ||
271 | |||
272 | /* Enable DMA for I2S1 channel */ | ||
273 | tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); | ||
274 | tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; | ||
275 | __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); | ||
276 | |||
277 | lpc32xx_serial_init(); | 247 | lpc32xx_serial_init(); |
278 | 248 | ||
279 | /* | ||
280 | * AMBA peripheral clocks need to be enabled prior to AMBA device | ||
281 | * detection or a data fault will occur, so enable the clocks | ||
282 | * here. | ||
283 | */ | ||
284 | tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); | ||
285 | __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), | ||
286 | LPC32XX_CLKPWR_LCDCLK_CTRL); | ||
287 | |||
288 | tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); | ||
289 | __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), | ||
290 | LPC32XX_CLKPWR_SSP_CLK_CTRL); | ||
291 | |||
292 | tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); | ||
293 | __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), | ||
294 | LPC32XX_CLKPWR_DMA_CLK_CTRL); | ||
295 | |||
296 | /* Test clock needed for UDA1380 initial init */ | 249 | /* Test clock needed for UDA1380 initial init */ |
297 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | | 250 | __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | |
298 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, | 251 | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, |
@@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void) | |||
302 | lpc32xx_auxdata_lookup, NULL); | 255 | lpc32xx_auxdata_lookup, NULL); |
303 | 256 | ||
304 | /* Register GPIOs used on this board */ | 257 | /* Register GPIOs used on this board */ |
305 | if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) | 258 | if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) |
306 | printk(KERN_ERR "Error requesting gpio %u", | 259 | pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); |
307 | SPI0_CS_GPIO); | 260 | else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) |
308 | else if (gpio_direction_output(SPI0_CS_GPIO, 1)) | 261 | pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); |
309 | printk(KERN_ERR "Error setting gpio %u to output", | ||
310 | SPI0_CS_GPIO); | ||
311 | } | 262 | } |
312 | 263 | ||
313 | static char const *lpc32xx_dt_compat[] __initdata = { | 264 | static char const *lpc32xx_dt_compat[] __initdata = { |
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c index f2735281616a..05621a29fba2 100644 --- a/arch/arm/mach-lpc32xx/serial.c +++ b/arch/arm/mach-lpc32xx/serial.c | |||
@@ -31,59 +31,6 @@ | |||
31 | 31 | ||
32 | #define LPC32XX_SUART_FIFO_SIZE 64 | 32 | #define LPC32XX_SUART_FIFO_SIZE 64 |
33 | 33 | ||
34 | /* Standard 8250/16550 compatible serial ports */ | ||
35 | static struct plat_serial8250_port serial_std_platform_data[] = { | ||
36 | #ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT | ||
37 | { | ||
38 | .membase = io_p2v(LPC32XX_UART5_BASE), | ||
39 | .mapbase = LPC32XX_UART5_BASE, | ||
40 | .irq = IRQ_LPC32XX_UART_IIR5, | ||
41 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
42 | .regshift = 2, | ||
43 | .iotype = UPIO_MEM32, | ||
44 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
45 | UPF_SKIP_TEST, | ||
46 | }, | ||
47 | #endif | ||
48 | #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT | ||
49 | { | ||
50 | .membase = io_p2v(LPC32XX_UART3_BASE), | ||
51 | .mapbase = LPC32XX_UART3_BASE, | ||
52 | .irq = IRQ_LPC32XX_UART_IIR3, | ||
53 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
54 | .regshift = 2, | ||
55 | .iotype = UPIO_MEM32, | ||
56 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
57 | UPF_SKIP_TEST, | ||
58 | }, | ||
59 | #endif | ||
60 | #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT | ||
61 | { | ||
62 | .membase = io_p2v(LPC32XX_UART4_BASE), | ||
63 | .mapbase = LPC32XX_UART4_BASE, | ||
64 | .irq = IRQ_LPC32XX_UART_IIR4, | ||
65 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
66 | .regshift = 2, | ||
67 | .iotype = UPIO_MEM32, | ||
68 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
69 | UPF_SKIP_TEST, | ||
70 | }, | ||
71 | #endif | ||
72 | #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT | ||
73 | { | ||
74 | .membase = io_p2v(LPC32XX_UART6_BASE), | ||
75 | .mapbase = LPC32XX_UART6_BASE, | ||
76 | .irq = IRQ_LPC32XX_UART_IIR6, | ||
77 | .uartclk = LPC32XX_MAIN_OSC_FREQ, | ||
78 | .regshift = 2, | ||
79 | .iotype = UPIO_MEM32, | ||
80 | .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | | ||
81 | UPF_SKIP_TEST, | ||
82 | }, | ||
83 | #endif | ||
84 | { }, | ||
85 | }; | ||
86 | |||
87 | struct uartinit { | 34 | struct uartinit { |
88 | char *uart_ck_name; | 35 | char *uart_ck_name; |
89 | u32 ck_mode_mask; | 36 | u32 ck_mode_mask; |
@@ -92,7 +39,6 @@ struct uartinit { | |||
92 | }; | 39 | }; |
93 | 40 | ||
94 | static struct uartinit uartinit_data[] __initdata = { | 41 | static struct uartinit uartinit_data[] __initdata = { |
95 | #ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT | ||
96 | { | 42 | { |
97 | .uart_ck_name = "uart5_ck", | 43 | .uart_ck_name = "uart5_ck", |
98 | .ck_mode_mask = | 44 | .ck_mode_mask = |
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
100 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, | 46 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, |
101 | .mapbase = LPC32XX_UART5_BASE, | 47 | .mapbase = LPC32XX_UART5_BASE, |
102 | }, | 48 | }, |
103 | #endif | ||
104 | #ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT | ||
105 | { | 49 | { |
106 | .uart_ck_name = "uart3_ck", | 50 | .uart_ck_name = "uart3_ck", |
107 | .ck_mode_mask = | 51 | .ck_mode_mask = |
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
109 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, | 53 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, |
110 | .mapbase = LPC32XX_UART3_BASE, | 54 | .mapbase = LPC32XX_UART3_BASE, |
111 | }, | 55 | }, |
112 | #endif | ||
113 | #ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT | ||
114 | { | 56 | { |
115 | .uart_ck_name = "uart4_ck", | 57 | .uart_ck_name = "uart4_ck", |
116 | .ck_mode_mask = | 58 | .ck_mode_mask = |
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
118 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, | 60 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, |
119 | .mapbase = LPC32XX_UART4_BASE, | 61 | .mapbase = LPC32XX_UART4_BASE, |
120 | }, | 62 | }, |
121 | #endif | ||
122 | #ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT | ||
123 | { | 63 | { |
124 | .uart_ck_name = "uart6_ck", | 64 | .uart_ck_name = "uart6_ck", |
125 | .ck_mode_mask = | 65 | .ck_mode_mask = |
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = { | |||
127 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, | 67 | .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, |
128 | .mapbase = LPC32XX_UART6_BASE, | 68 | .mapbase = LPC32XX_UART6_BASE, |
129 | }, | 69 | }, |
130 | #endif | ||
131 | }; | ||
132 | |||
133 | static struct platform_device serial_std_platform_device = { | ||
134 | .name = "serial8250", | ||
135 | .id = 0, | ||
136 | .dev = { | ||
137 | .platform_data = serial_std_platform_data, | ||
138 | }, | ||
139 | }; | ||
140 | |||
141 | static struct platform_device *lpc32xx_serial_devs[] __initdata = { | ||
142 | &serial_std_platform_device, | ||
143 | }; | 70 | }; |
144 | 71 | ||
145 | void __init lpc32xx_serial_init(void) | 72 | void __init lpc32xx_serial_init(void) |
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void) | |||
156 | clk = clk_get(NULL, uartinit_data[i].uart_ck_name); | 83 | clk = clk_get(NULL, uartinit_data[i].uart_ck_name); |
157 | if (!IS_ERR(clk)) { | 84 | if (!IS_ERR(clk)) { |
158 | clk_enable(clk); | 85 | clk_enable(clk); |
159 | serial_std_platform_data[i].uartclk = | ||
160 | clk_get_rate(clk); | ||
161 | } | 86 | } |
162 | 87 | ||
163 | /* Fall back on main osc rate if clock rate return fails */ | ||
164 | if (serial_std_platform_data[i].uartclk == 0) | ||
165 | serial_std_platform_data[i].uartclk = | ||
166 | LPC32XX_MAIN_OSC_FREQ; | ||
167 | |||
168 | /* Setup UART clock modes for all UARTs, disable autoclock */ | 88 | /* Setup UART clock modes for all UARTs, disable autoclock */ |
169 | clkmodes |= uartinit_data[i].ck_mode_mask; | 89 | clkmodes |= uartinit_data[i].ck_mode_mask; |
170 | 90 | ||
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void) | |||
189 | __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); | 109 | __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); |
190 | for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { | 110 | for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { |
191 | /* Force a flush of the RX FIFOs to work around a HW bug */ | 111 | /* Force a flush of the RX FIFOs to work around a HW bug */ |
192 | puart = serial_std_platform_data[i].mapbase; | 112 | puart = uartinit_data[i].mapbase; |
193 | __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); | 113 | __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); |
194 | __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); | 114 | __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); |
195 | j = LPC32XX_SUART_FIFO_SIZE; | 115 | j = LPC32XX_SUART_FIFO_SIZE; |
@@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void) | |||
198 | __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); | 118 | __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); |
199 | } | 119 | } |
200 | 120 | ||
121 | /* Disable IrDA pulsing support on UART6 */ | ||
122 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); | ||
123 | tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; | ||
124 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); | ||
125 | |||
201 | /* Disable UART5->USB transparent mode or USB won't work */ | 126 | /* Disable UART5->USB transparent mode or USB won't work */ |
202 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); | 127 | tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); |
203 | tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; | 128 | tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; |
204 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); | 129 | __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); |
205 | |||
206 | platform_add_devices(lpc32xx_serial_devs, | ||
207 | ARRAY_SIZE(lpc32xx_serial_devs)); | ||
208 | } | 130 | } |
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig index 91cf0625819c..ccdf83b17cf1 100644 --- a/arch/arm/mach-mxs/Kconfig +++ b/arch/arm/mach-mxs/Kconfig | |||
@@ -16,6 +16,7 @@ config SOC_IMX28 | |||
16 | bool | 16 | bool |
17 | select ARM_AMBA | 17 | select ARM_AMBA |
18 | select CPU_ARM926T | 18 | select CPU_ARM926T |
19 | select HAVE_CAN_FLEXCAN if CAN | ||
19 | select HAVE_PWM | 20 | select HAVE_PWM |
20 | select PINCTRL_IMX28 | 21 | select PINCTRL_IMX28 |
21 | 22 | ||
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot index 07b11fe6453f..4582999cf080 100644 --- a/arch/arm/mach-mxs/Makefile.boot +++ b/arch/arm/mach-mxs/Makefile.boot | |||
@@ -1 +1,10 @@ | |||
1 | zreladdr-y += 0x40008000 | 1 | zreladdr-y += 0x40008000 |
2 | |||
3 | dtb-y += imx23-evk.dtb \ | ||
4 | imx23-olinuxino.dtb \ | ||
5 | imx23-stmp378x_devb.dtb \ | ||
6 | imx28-apx4devkit.dtb \ | ||
7 | imx28-cfa10036.dtb \ | ||
8 | imx28-evk.dtb \ | ||
9 | imx28-m28evk.dtb \ | ||
10 | imx28-tx28.dtb \ | ||
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h index 9acdd6387047..9ee5cede3d42 100644 --- a/arch/arm/mach-mxs/devices-mx23.h +++ b/arch/arm/mach-mxs/devices-mx23.h | |||
@@ -10,7 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | #include <mach/mx23.h> | 11 | #include <mach/mx23.h> |
12 | #include <mach/devices-common.h> | 12 | #include <mach/devices-common.h> |
13 | #include <mach/mxsfb.h> | 13 | #include <linux/mxsfb.h> |
14 | #include <linux/amba/bus.h> | 14 | #include <linux/amba/bus.h> |
15 | 15 | ||
16 | static inline int mx23_add_duart(void) | 16 | static inline int mx23_add_duart(void) |
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h index 84b2960df117..fcab431060f4 100644 --- a/arch/arm/mach-mxs/devices-mx28.h +++ b/arch/arm/mach-mxs/devices-mx28.h | |||
@@ -10,7 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | #include <mach/mx28.h> | 11 | #include <mach/mx28.h> |
12 | #include <mach/devices-common.h> | 12 | #include <mach/devices-common.h> |
13 | #include <mach/mxsfb.h> | 13 | #include <linux/mxsfb.h> |
14 | #include <linux/amba/bus.h> | 14 | #include <linux/amba/bus.h> |
15 | 15 | ||
16 | static inline int mx28_add_duart(void) | 16 | static inline int mx28_add_duart(void) |
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c index 5a75b7180f74..76b53f73418e 100644 --- a/arch/arm/mach-mxs/devices/platform-mxsfb.c +++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c | |||
@@ -10,7 +10,7 @@ | |||
10 | #include <mach/mx23.h> | 10 | #include <mach/mx23.h> |
11 | #include <mach/mx28.h> | 11 | #include <mach/mx28.h> |
12 | #include <mach/devices-common.h> | 12 | #include <mach/devices-common.h> |
13 | #include <mach/mxsfb.h> | 13 | #include <linux/mxsfb.h> |
14 | 14 | ||
15 | #ifdef CONFIG_SOC_IMX23 | 15 | #ifdef CONFIG_SOC_IMX23 |
16 | struct platform_device *__init mx23_add_mxsfb( | 16 | struct platform_device *__init mx23_add_mxsfb( |
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h deleted file mode 100644 index e4d79791515e..000000000000 --- a/arch/arm/mach-mxs/include/mach/mxsfb.h +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | /* | ||
2 | * This program is free software; you can redistribute it and/or | ||
3 | * modify it under the terms of the GNU General Public License | ||
4 | * as published by the Free Software Foundation; either version 2 | ||
5 | * of the License, or (at your option) any later version. | ||
6 | * This program is distributed in the hope that it will be useful, | ||
7 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
8 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
9 | * GNU General Public License for more details. | ||
10 | * | ||
11 | * You should have received a copy of the GNU General Public License | ||
12 | * along with this program; if not, write to the Free Software | ||
13 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
14 | * MA 02110-1301, USA. | ||
15 | */ | ||
16 | |||
17 | #ifndef __MACH_FB_H | ||
18 | #define __MACH_FB_H | ||
19 | |||
20 | #include <linux/fb.h> | ||
21 | |||
22 | #define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ | ||
23 | #define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ | ||
24 | #define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ | ||
25 | #define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ | ||
26 | |||
27 | #define FB_SYNC_DATA_ENABLE_HIGH_ACT (1 << 6) | ||
28 | #define FB_SYNC_DOTCLK_FAILING_ACT (1 << 7) /* failing/negtive edge sampling */ | ||
29 | |||
30 | struct mxsfb_platform_data { | ||
31 | struct fb_videomode *mode_list; | ||
32 | unsigned mode_count; | ||
33 | |||
34 | unsigned default_bpp; | ||
35 | |||
36 | unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ | ||
37 | unsigned ld_intf_width; /* refer STMLCDIF_* macros */ | ||
38 | |||
39 | unsigned fb_size; /* Size of the video memory. If zero a | ||
40 | * default will be used | ||
41 | */ | ||
42 | unsigned long fb_phys; /* physical address for the video memory. If | ||
43 | * zero the framebuffer memory will be dynamically | ||
44 | * allocated. If specified,fb_size must also be specified. | ||
45 | * fb_phys must be unused by Linux. | ||
46 | */ | ||
47 | }; | ||
48 | |||
49 | #endif /* __MACH_FB_H */ | ||
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c index 8cac94b33020..648bdd05d38b 100644 --- a/arch/arm/mach-mxs/mach-mxs.c +++ b/arch/arm/mach-mxs/mach-mxs.c | |||
@@ -16,12 +16,95 @@ | |||
16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/irqdomain.h> | 18 | #include <linux/irqdomain.h> |
19 | #include <linux/micrel_phy.h> | ||
20 | #include <linux/mxsfb.h> | ||
19 | #include <linux/of_irq.h> | 21 | #include <linux/of_irq.h> |
20 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
23 | #include <linux/phy.h> | ||
21 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
22 | #include <asm/mach/time.h> | 25 | #include <asm/mach/time.h> |
23 | #include <mach/common.h> | 26 | #include <mach/common.h> |
24 | 27 | ||
28 | static struct fb_videomode mx23evk_video_modes[] = { | ||
29 | { | ||
30 | .name = "Samsung-LMS430HF02", | ||
31 | .refresh = 60, | ||
32 | .xres = 480, | ||
33 | .yres = 272, | ||
34 | .pixclock = 108096, /* picosecond (9.2 MHz) */ | ||
35 | .left_margin = 15, | ||
36 | .right_margin = 8, | ||
37 | .upper_margin = 12, | ||
38 | .lower_margin = 4, | ||
39 | .hsync_len = 1, | ||
40 | .vsync_len = 1, | ||
41 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
42 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
43 | }, | ||
44 | }; | ||
45 | |||
46 | static struct fb_videomode mx28evk_video_modes[] = { | ||
47 | { | ||
48 | .name = "Seiko-43WVF1G", | ||
49 | .refresh = 60, | ||
50 | .xres = 800, | ||
51 | .yres = 480, | ||
52 | .pixclock = 29851, /* picosecond (33.5 MHz) */ | ||
53 | .left_margin = 89, | ||
54 | .right_margin = 164, | ||
55 | .upper_margin = 23, | ||
56 | .lower_margin = 10, | ||
57 | .hsync_len = 10, | ||
58 | .vsync_len = 10, | ||
59 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
60 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
61 | }, | ||
62 | }; | ||
63 | |||
64 | static struct fb_videomode m28evk_video_modes[] = { | ||
65 | { | ||
66 | .name = "Ampire AM-800480R2TMQW-T01H", | ||
67 | .refresh = 60, | ||
68 | .xres = 800, | ||
69 | .yres = 480, | ||
70 | .pixclock = 30066, /* picosecond (33.26 MHz) */ | ||
71 | .left_margin = 0, | ||
72 | .right_margin = 256, | ||
73 | .upper_margin = 0, | ||
74 | .lower_margin = 45, | ||
75 | .hsync_len = 1, | ||
76 | .vsync_len = 1, | ||
77 | .sync = FB_SYNC_DATA_ENABLE_HIGH_ACT, | ||
78 | }, | ||
79 | }; | ||
80 | |||
81 | static struct fb_videomode apx4devkit_video_modes[] = { | ||
82 | { | ||
83 | .name = "HannStar PJ70112A", | ||
84 | .refresh = 60, | ||
85 | .xres = 800, | ||
86 | .yres = 480, | ||
87 | .pixclock = 33333, /* picosecond (30.00 MHz) */ | ||
88 | .left_margin = 88, | ||
89 | .right_margin = 40, | ||
90 | .upper_margin = 32, | ||
91 | .lower_margin = 13, | ||
92 | .hsync_len = 48, | ||
93 | .vsync_len = 3, | ||
94 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | | ||
95 | FB_SYNC_DATA_ENABLE_HIGH_ACT | | ||
96 | FB_SYNC_DOTCLK_FAILING_ACT, | ||
97 | }, | ||
98 | }; | ||
99 | |||
100 | static struct mxsfb_platform_data mxsfb_pdata __initdata; | ||
101 | |||
102 | static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = { | ||
103 | OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata), | ||
104 | OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata), | ||
105 | { /* sentinel */ } | ||
106 | }; | ||
107 | |||
25 | static int __init mxs_icoll_add_irq_domain(struct device_node *np, | 108 | static int __init mxs_icoll_add_irq_domain(struct device_node *np, |
26 | struct device_node *interrupt_parent) | 109 | struct device_node *interrupt_parent) |
27 | { | 110 | { |
@@ -71,33 +154,155 @@ static struct sys_timer imx28_timer = { | |||
71 | .init = imx28_timer_init, | 154 | .init = imx28_timer_init, |
72 | }; | 155 | }; |
73 | 156 | ||
74 | static void __init imx28_evk_init(void) | 157 | enum mac_oui { |
158 | OUI_FSL, | ||
159 | OUI_DENX, | ||
160 | }; | ||
161 | |||
162 | static void __init update_fec_mac_prop(enum mac_oui oui) | ||
163 | { | ||
164 | struct device_node *np, *from = NULL; | ||
165 | struct property *oldmac, *newmac; | ||
166 | const u32 *ocotp = mxs_get_ocotp(); | ||
167 | u8 *macaddr; | ||
168 | u32 val; | ||
169 | int i; | ||
170 | |||
171 | for (i = 0; i < 2; i++) { | ||
172 | np = of_find_compatible_node(from, NULL, "fsl,imx28-fec"); | ||
173 | if (!np) | ||
174 | return; | ||
175 | from = np; | ||
176 | |||
177 | newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); | ||
178 | if (!newmac) | ||
179 | return; | ||
180 | newmac->value = newmac + 1; | ||
181 | newmac->length = 6; | ||
182 | |||
183 | newmac->name = kstrdup("local-mac-address", GFP_KERNEL); | ||
184 | if (!newmac->name) { | ||
185 | kfree(newmac); | ||
186 | return; | ||
187 | } | ||
188 | |||
189 | /* | ||
190 | * OCOTP only stores the last 4 octets for each mac address, | ||
191 | * so hard-code OUI here. | ||
192 | */ | ||
193 | macaddr = newmac->value; | ||
194 | switch (oui) { | ||
195 | case OUI_FSL: | ||
196 | macaddr[0] = 0x00; | ||
197 | macaddr[1] = 0x04; | ||
198 | macaddr[2] = 0x9f; | ||
199 | break; | ||
200 | case OUI_DENX: | ||
201 | macaddr[0] = 0xc0; | ||
202 | macaddr[1] = 0xe5; | ||
203 | macaddr[2] = 0x4e; | ||
204 | break; | ||
205 | } | ||
206 | val = ocotp[i]; | ||
207 | macaddr[3] = (val >> 16) & 0xff; | ||
208 | macaddr[4] = (val >> 8) & 0xff; | ||
209 | macaddr[5] = (val >> 0) & 0xff; | ||
210 | |||
211 | oldmac = of_find_property(np, newmac->name, NULL); | ||
212 | if (oldmac) | ||
213 | prom_update_property(np, newmac, oldmac); | ||
214 | else | ||
215 | prom_add_property(np, newmac); | ||
216 | } | ||
217 | } | ||
218 | |||
219 | static void __init imx23_evk_init(void) | ||
220 | { | ||
221 | mxsfb_pdata.mode_list = mx23evk_video_modes; | ||
222 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes); | ||
223 | mxsfb_pdata.default_bpp = 32; | ||
224 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | ||
225 | } | ||
226 | |||
227 | static inline void enable_clk_enet_out(void) | ||
75 | { | 228 | { |
76 | struct clk *clk; | 229 | struct clk *clk = clk_get_sys("enet_out", NULL); |
77 | 230 | ||
78 | /* Enable fec phy clock */ | ||
79 | clk = clk_get_sys("enet_out", NULL); | ||
80 | if (!IS_ERR(clk)) | 231 | if (!IS_ERR(clk)) |
81 | clk_prepare_enable(clk); | 232 | clk_prepare_enable(clk); |
82 | } | 233 | } |
83 | 234 | ||
235 | static void __init imx28_evk_init(void) | ||
236 | { | ||
237 | enable_clk_enet_out(); | ||
238 | update_fec_mac_prop(OUI_FSL); | ||
239 | |||
240 | mxsfb_pdata.mode_list = mx28evk_video_modes; | ||
241 | mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes); | ||
242 | mxsfb_pdata.default_bpp = 32; | ||
243 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | ||
244 | } | ||
245 | |||
246 | static void __init m28evk_init(void) | ||
247 | { | ||
248 | enable_clk_enet_out(); | ||
249 | update_fec_mac_prop(OUI_DENX); | ||
250 | |||
251 | mxsfb_pdata.mode_list = m28evk_video_modes; | ||
252 | mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes); | ||
253 | mxsfb_pdata.default_bpp = 16; | ||
254 | mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT; | ||
255 | } | ||
256 | |||
257 | static int apx4devkit_phy_fixup(struct phy_device *phy) | ||
258 | { | ||
259 | phy->dev_flags |= MICREL_PHY_50MHZ_CLK; | ||
260 | return 0; | ||
261 | } | ||
262 | |||
263 | static void __init apx4devkit_init(void) | ||
264 | { | ||
265 | enable_clk_enet_out(); | ||
266 | |||
267 | if (IS_BUILTIN(CONFIG_PHYLIB)) | ||
268 | phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, | ||
269 | apx4devkit_phy_fixup); | ||
270 | |||
271 | mxsfb_pdata.mode_list = apx4devkit_video_modes; | ||
272 | mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes); | ||
273 | mxsfb_pdata.default_bpp = 32; | ||
274 | mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT; | ||
275 | } | ||
276 | |||
84 | static void __init mxs_machine_init(void) | 277 | static void __init mxs_machine_init(void) |
85 | { | 278 | { |
86 | if (of_machine_is_compatible("fsl,imx28-evk")) | 279 | if (of_machine_is_compatible("fsl,imx28-evk")) |
87 | imx28_evk_init(); | 280 | imx28_evk_init(); |
281 | else if (of_machine_is_compatible("fsl,imx23-evk")) | ||
282 | imx23_evk_init(); | ||
283 | else if (of_machine_is_compatible("denx,m28evk")) | ||
284 | m28evk_init(); | ||
285 | else if (of_machine_is_compatible("bluegiga,apx4devkit")) | ||
286 | apx4devkit_init(); | ||
88 | 287 | ||
89 | of_platform_populate(NULL, of_default_bus_match_table, | 288 | of_platform_populate(NULL, of_default_bus_match_table, |
90 | NULL, NULL); | 289 | mxs_auxdata_lookup, NULL); |
91 | } | 290 | } |
92 | 291 | ||
93 | static const char *imx23_dt_compat[] __initdata = { | 292 | static const char *imx23_dt_compat[] __initdata = { |
94 | "fsl,imx23-evk", | 293 | "fsl,imx23-evk", |
294 | "fsl,stmp378x_devb" | ||
295 | "olimex,imx23-olinuxino", | ||
95 | "fsl,imx23", | 296 | "fsl,imx23", |
96 | NULL, | 297 | NULL, |
97 | }; | 298 | }; |
98 | 299 | ||
99 | static const char *imx28_dt_compat[] __initdata = { | 300 | static const char *imx28_dt_compat[] __initdata = { |
301 | "bluegiga,apx4devkit", | ||
302 | "crystalfontz,cfa10036", | ||
303 | "denx,m28evk", | ||
100 | "fsl,imx28-evk", | 304 | "fsl,imx28-evk", |
305 | "karo,tx28", | ||
101 | "fsl,imx28", | 306 | "fsl,imx28", |
102 | NULL, | 307 | NULL, |
103 | }; | 308 | }; |
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c index 9a7b08b2a925..0f71f82101cc 100644 --- a/arch/arm/mach-mxs/module-tx28.c +++ b/arch/arm/mach-mxs/module-tx28.c | |||
@@ -11,7 +11,7 @@ | |||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | 12 | ||
13 | #include <mach/iomux-mx28.h> | 13 | #include <mach/iomux-mx28.h> |
14 | #include "../devices-mx28.h" | 14 | #include "devices-mx28.h" |
15 | 15 | ||
16 | #include "module-tx28.h" | 16 | #include "module-tx28.h" |
17 | 17 | ||
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile index a6bbd1a7b4e7..a42c9a33d3bf 100644 --- a/arch/arm/mach-nomadik/Makefile +++ b/arch/arm/mach-nomadik/Makefile | |||
@@ -7,8 +7,6 @@ | |||
7 | 7 | ||
8 | # Object file lists. | 8 | # Object file lists. |
9 | 9 | ||
10 | obj-y += clock.o | ||
11 | |||
12 | # Cpu revision | 10 | # Cpu revision |
13 | obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o | 11 | obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o |
14 | 12 | ||
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c index 2e8d3e176bc7..f4535a7dadf5 100644 --- a/arch/arm/mach-nomadik/board-nhk8815.c +++ b/arch/arm/mach-nomadik/board-nhk8815.c | |||
@@ -14,12 +14,14 @@ | |||
14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
16 | #include <linux/amba/bus.h> | 16 | #include <linux/amba/bus.h> |
17 | #include <linux/amba/mmci.h> | ||
17 | #include <linux/interrupt.h> | 18 | #include <linux/interrupt.h> |
18 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
19 | #include <linux/mtd/mtd.h> | 20 | #include <linux/mtd/mtd.h> |
20 | #include <linux/mtd/nand.h> | 21 | #include <linux/mtd/nand.h> |
21 | #include <linux/mtd/onenand.h> | 22 | #include <linux/mtd/onenand.h> |
22 | #include <linux/mtd/partitions.h> | 23 | #include <linux/mtd/partitions.h> |
24 | #include <linux/i2c.h> | ||
23 | #include <linux/io.h> | 25 | #include <linux/io.h> |
24 | #include <asm/hardware/vic.h> | 26 | #include <asm/hardware/vic.h> |
25 | #include <asm/sizes.h> | 27 | #include <asm/sizes.h> |
@@ -185,16 +187,28 @@ static void __init nhk8815_onenand_init(void) | |||
185 | #endif | 187 | #endif |
186 | } | 188 | } |
187 | 189 | ||
188 | static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE, | 190 | static struct mmci_platform_data mmcsd_plat_data = { |
189 | { IRQ_UART0 }, NULL); | 191 | .ocr_mask = MMC_VDD_29_30, |
192 | .f_max = 48000000, | ||
193 | .gpio_wp = -1, | ||
194 | .gpio_cd = 111, | ||
195 | .cd_invert = true, | ||
196 | .capabilities = MMC_CAP_MMC_HIGHSPEED | | ||
197 | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA, | ||
198 | }; | ||
190 | 199 | ||
191 | static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE, | 200 | static int __init nhk8815_mmcsd_init(void) |
192 | { IRQ_UART1 }, NULL); | 201 | { |
202 | int ret; | ||
193 | 203 | ||
194 | static struct amba_device *amba_devs[] __initdata = { | 204 | ret = gpio_request(112, "card detect bias"); |
195 | &uart0_device, | 205 | if (ret) |
196 | &uart1_device, | 206 | return ret; |
197 | }; | 207 | gpio_direction_output(112, 0); |
208 | amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180); | ||
209 | return 0; | ||
210 | } | ||
211 | module_init(nhk8815_mmcsd_init); | ||
198 | 212 | ||
199 | static struct resource nhk8815_eth_resources[] = { | 213 | static struct resource nhk8815_eth_resources[] = { |
200 | { | 214 | { |
@@ -253,17 +267,46 @@ static struct sys_timer nomadik_timer = { | |||
253 | .init = nomadik_timer_init, | 267 | .init = nomadik_timer_init, |
254 | }; | 268 | }; |
255 | 269 | ||
270 | static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = { | ||
271 | { | ||
272 | I2C_BOARD_INFO("stw4811", 0x2d), | ||
273 | }, | ||
274 | }; | ||
275 | |||
276 | static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = { | ||
277 | { | ||
278 | I2C_BOARD_INFO("camera", 0x10), | ||
279 | }, | ||
280 | { | ||
281 | I2C_BOARD_INFO("stw5095", 0x1a), | ||
282 | }, | ||
283 | { | ||
284 | I2C_BOARD_INFO("lis3lv02dl", 0x1d), | ||
285 | }, | ||
286 | }; | ||
287 | |||
288 | static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = { | ||
289 | { | ||
290 | I2C_BOARD_INFO("stw4811-usb", 0x2d), | ||
291 | }, | ||
292 | }; | ||
293 | |||
256 | static void __init nhk8815_platform_init(void) | 294 | static void __init nhk8815_platform_init(void) |
257 | { | 295 | { |
258 | int i; | ||
259 | |||
260 | cpu8815_platform_init(); | 296 | cpu8815_platform_init(); |
261 | nhk8815_onenand_init(); | 297 | nhk8815_onenand_init(); |
262 | platform_add_devices(nhk8815_platform_devices, | 298 | platform_add_devices(nhk8815_platform_devices, |
263 | ARRAY_SIZE(nhk8815_platform_devices)); | 299 | ARRAY_SIZE(nhk8815_platform_devices)); |
264 | 300 | ||
265 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) | 301 | amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0); |
266 | amba_device_register(amba_devs[i], &iomem_resource); | 302 | amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0); |
303 | |||
304 | i2c_register_board_info(0, nhk8815_i2c0_devices, | ||
305 | ARRAY_SIZE(nhk8815_i2c0_devices)); | ||
306 | i2c_register_board_info(1, nhk8815_i2c1_devices, | ||
307 | ARRAY_SIZE(nhk8815_i2c1_devices)); | ||
308 | i2c_register_board_info(2, nhk8815_i2c2_devices, | ||
309 | ARRAY_SIZE(nhk8815_i2c2_devices)); | ||
267 | } | 310 | } |
268 | 311 | ||
269 | MACHINE_START(NOMADIK, "NHK8815") | 312 | MACHINE_START(NOMADIK, "NHK8815") |
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c deleted file mode 100644 index 48a59f24e10c..000000000000 --- a/arch/arm/mach-nomadik/clock.c +++ /dev/null | |||
@@ -1,75 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-nomadik/clock.c | ||
3 | * | ||
4 | * Copyright (C) 2009 Alessandro Rubini | ||
5 | */ | ||
6 | #include <linux/kernel.h> | ||
7 | #include <linux/module.h> | ||
8 | #include <linux/errno.h> | ||
9 | #include <linux/clk.h> | ||
10 | #include <linux/clkdev.h> | ||
11 | #include "clock.h" | ||
12 | |||
13 | /* | ||
14 | * The nomadik board uses generic clocks, but the serial pl011 file | ||
15 | * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them | ||
16 | */ | ||
17 | unsigned long clk_get_rate(struct clk *clk) | ||
18 | { | ||
19 | return clk->rate; | ||
20 | } | ||
21 | EXPORT_SYMBOL(clk_get_rate); | ||
22 | |||
23 | /* enable and disable do nothing */ | ||
24 | int clk_enable(struct clk *clk) | ||
25 | { | ||
26 | return 0; | ||
27 | } | ||
28 | EXPORT_SYMBOL(clk_enable); | ||
29 | |||
30 | void clk_disable(struct clk *clk) | ||
31 | { | ||
32 | } | ||
33 | EXPORT_SYMBOL(clk_disable); | ||
34 | |||
35 | static struct clk clk_24 = { | ||
36 | .rate = 2400000, | ||
37 | }; | ||
38 | |||
39 | static struct clk clk_48 = { | ||
40 | .rate = 48 * 1000 * 1000, | ||
41 | }; | ||
42 | |||
43 | /* | ||
44 | * Catch-all default clock to satisfy drivers using the clk API. We don't | ||
45 | * model the actual hardware clocks yet. | ||
46 | */ | ||
47 | static struct clk clk_default; | ||
48 | |||
49 | #define CLK(_clk, dev) \ | ||
50 | { \ | ||
51 | .clk = _clk, \ | ||
52 | .dev_id = dev, \ | ||
53 | } | ||
54 | |||
55 | static struct clk_lookup lookups[] = { | ||
56 | { | ||
57 | .con_id = "apb_pclk", | ||
58 | .clk = &clk_default, | ||
59 | }, | ||
60 | CLK(&clk_24, "mtu0"), | ||
61 | CLK(&clk_24, "mtu1"), | ||
62 | CLK(&clk_48, "uart0"), | ||
63 | CLK(&clk_48, "uart1"), | ||
64 | CLK(&clk_default, "gpio.0"), | ||
65 | CLK(&clk_default, "gpio.1"), | ||
66 | CLK(&clk_default, "gpio.2"), | ||
67 | CLK(&clk_default, "gpio.3"), | ||
68 | CLK(&clk_default, "rng"), | ||
69 | }; | ||
70 | |||
71 | int __init clk_init(void) | ||
72 | { | ||
73 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
74 | return 0; | ||
75 | } | ||
diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h deleted file mode 100644 index 78da2e7c3985..000000000000 --- a/arch/arm/mach-nomadik/clock.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | |||
2 | /* | ||
3 | * linux/arch/arm/mach-nomadik/clock.h | ||
4 | * | ||
5 | * Copyright (C) 2009 Alessandro Rubini | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | struct clk { | ||
12 | unsigned long rate; | ||
13 | }; | ||
14 | |||
15 | int __init clk_init(void); | ||
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c index 27f43a46985e..6fd8e46567a4 100644 --- a/arch/arm/mach-nomadik/cpu-8815.c +++ b/arch/arm/mach-nomadik/cpu-8815.c | |||
@@ -22,6 +22,10 @@ | |||
22 | #include <linux/amba/bus.h> | 22 | #include <linux/amba/bus.h> |
23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/slab.h> | ||
26 | #include <linux/irq.h> | ||
27 | #include <linux/dma-mapping.h> | ||
28 | #include <linux/platform_data/clk-nomadik.h> | ||
25 | 29 | ||
26 | #include <plat/gpio-nomadik.h> | 30 | #include <plat/gpio-nomadik.h> |
27 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
@@ -32,91 +36,63 @@ | |||
32 | #include <asm/cacheflush.h> | 36 | #include <asm/cacheflush.h> |
33 | #include <asm/hardware/cache-l2x0.h> | 37 | #include <asm/hardware/cache-l2x0.h> |
34 | 38 | ||
35 | #include "clock.h" | ||
36 | #include "cpu-8815.h" | 39 | #include "cpu-8815.h" |
37 | 40 | ||
38 | #define __MEM_4K_RESOURCE(x) \ | ||
39 | .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} | ||
40 | |||
41 | /* The 8815 has 4 GPIO blocks, let's register them immediately */ | 41 | /* The 8815 has 4 GPIO blocks, let's register them immediately */ |
42 | 42 | static resource_size_t __initdata cpu8815_gpio_base[] = { | |
43 | #define GPIO_RESOURCE(block) \ | 43 | NOMADIK_GPIO0_BASE, |
44 | { \ | 44 | NOMADIK_GPIO1_BASE, |
45 | .start = NOMADIK_GPIO##block##_BASE, \ | 45 | NOMADIK_GPIO2_BASE, |
46 | .end = NOMADIK_GPIO##block##_BASE + SZ_4K - 1, \ | 46 | NOMADIK_GPIO3_BASE, |
47 | .flags = IORESOURCE_MEM, \ | ||
48 | }, \ | ||
49 | { \ | ||
50 | .start = IRQ_GPIO##block, \ | ||
51 | .end = IRQ_GPIO##block, \ | ||
52 | .flags = IORESOURCE_IRQ, \ | ||
53 | } | ||
54 | |||
55 | #define GPIO_DEVICE(block) \ | ||
56 | { \ | ||
57 | .name = "gpio", \ | ||
58 | .id = block, \ | ||
59 | .num_resources = 2, \ | ||
60 | .resource = &cpu8815_gpio_resources[block * 2], \ | ||
61 | .dev = { \ | ||
62 | .platform_data = &cpu8815_gpio[block], \ | ||
63 | }, \ | ||
64 | } | ||
65 | |||
66 | static struct nmk_gpio_platform_data cpu8815_gpio[] = { | ||
67 | { | ||
68 | .name = "GPIO-0-31", | ||
69 | .first_gpio = 0, | ||
70 | .first_irq = NOMADIK_GPIO_TO_IRQ(0), | ||
71 | }, { | ||
72 | .name = "GPIO-32-63", | ||
73 | .first_gpio = 32, | ||
74 | .first_irq = NOMADIK_GPIO_TO_IRQ(32), | ||
75 | }, { | ||
76 | .name = "GPIO-64-95", | ||
77 | .first_gpio = 64, | ||
78 | .first_irq = NOMADIK_GPIO_TO_IRQ(64), | ||
79 | }, { | ||
80 | .name = "GPIO-96-127", /* 124..127 not routed to pin */ | ||
81 | .first_gpio = 96, | ||
82 | .first_irq = NOMADIK_GPIO_TO_IRQ(96), | ||
83 | } | ||
84 | }; | 47 | }; |
85 | 48 | ||
86 | static struct resource cpu8815_gpio_resources[] = { | 49 | static struct platform_device * |
87 | GPIO_RESOURCE(0), | 50 | cpu8815_add_gpio(int id, resource_size_t addr, int irq, |
88 | GPIO_RESOURCE(1), | 51 | struct nmk_gpio_platform_data *pdata) |
89 | GPIO_RESOURCE(2), | 52 | { |
90 | GPIO_RESOURCE(3), | 53 | struct resource resources[] = { |
91 | }; | 54 | { |
92 | 55 | .start = addr, | |
93 | static struct platform_device cpu8815_platform_gpio[] = { | 56 | .end = addr + 127, |
94 | GPIO_DEVICE(0), | 57 | .flags = IORESOURCE_MEM, |
95 | GPIO_DEVICE(1), | 58 | }, |
96 | GPIO_DEVICE(2), | 59 | { |
97 | GPIO_DEVICE(3), | 60 | .start = irq, |
98 | }; | 61 | .end = irq, |
62 | .flags = IORESOURCE_IRQ, | ||
63 | } | ||
64 | }; | ||
65 | |||
66 | return platform_device_register_resndata(NULL, "gpio", id, | ||
67 | resources, ARRAY_SIZE(resources), | ||
68 | pdata, sizeof(*pdata)); | ||
69 | } | ||
99 | 70 | ||
100 | static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL); | 71 | void cpu8815_add_gpios(resource_size_t *base, int num, int irq, |
72 | struct nmk_gpio_platform_data *pdata) | ||
73 | { | ||
74 | int first = 0; | ||
75 | int i; | ||
101 | 76 | ||
102 | static struct platform_device *platform_devs[] __initdata = { | 77 | for (i = 0; i < num; i++, first += 32, irq++) { |
103 | cpu8815_platform_gpio + 0, | 78 | pdata->first_gpio = first; |
104 | cpu8815_platform_gpio + 1, | 79 | pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); |
105 | cpu8815_platform_gpio + 2, | 80 | pdata->num_gpio = 32; |
106 | cpu8815_platform_gpio + 3, | ||
107 | }; | ||
108 | 81 | ||
109 | static struct amba_device *amba_devs[] __initdata = { | 82 | cpu8815_add_gpio(i, base[i], irq, pdata); |
110 | &cpu8815_amba_rng_device | 83 | } |
111 | }; | 84 | } |
112 | 85 | ||
113 | static int __init cpu8815_init(void) | 86 | static int __init cpu8815_init(void) |
114 | { | 87 | { |
115 | int i; | 88 | struct nmk_gpio_platform_data pdata = { |
116 | 89 | /* No custom data yet */ | |
117 | platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); | 90 | }; |
118 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) | 91 | |
119 | amba_device_register(amba_devs[i], &iomem_resource); | 92 | cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base), |
93 | IRQ_GPIO0, &pdata); | ||
94 | amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0); | ||
95 | amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0); | ||
120 | return 0; | 96 | return 0; |
121 | } | 97 | } |
122 | arch_initcall(cpu8815_init); | 98 | arch_initcall(cpu8815_init); |
@@ -147,7 +123,7 @@ void __init cpu8815_init_irq(void) | |||
147 | * Init clocks here so that they are available for system timer | 123 | * Init clocks here so that they are available for system timer |
148 | * initialization. | 124 | * initialization. |
149 | */ | 125 | */ |
150 | clk_init(); | 126 | nomadik_clk_init(); |
151 | } | 127 | } |
152 | 128 | ||
153 | /* | 129 | /* |
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c index 0fc2f6f1cc97..6d14454d4609 100644 --- a/arch/arm/mach-nomadik/i2c-8815nhk.c +++ b/arch/arm/mach-nomadik/i2c-8815nhk.c | |||
@@ -5,6 +5,7 @@ | |||
5 | #include <linux/i2c-gpio.h> | 5 | #include <linux/i2c-gpio.h> |
6 | #include <linux/platform_device.h> | 6 | #include <linux/platform_device.h> |
7 | #include <plat/gpio-nomadik.h> | 7 | #include <plat/gpio-nomadik.h> |
8 | #include <plat/pincfg.h> | ||
8 | 9 | ||
9 | /* | 10 | /* |
10 | * There are two busses in the 8815NHK. | 11 | * There are two busses in the 8815NHK. |
@@ -12,19 +13,27 @@ | |||
12 | * use bit-bang through GPIO by now, to keep things simple | 13 | * use bit-bang through GPIO by now, to keep things simple |
13 | */ | 14 | */ |
14 | 15 | ||
16 | /* I2C0 connected to the STw4811 power management chip */ | ||
15 | static struct i2c_gpio_platform_data nhk8815_i2c_data0 = { | 17 | static struct i2c_gpio_platform_data nhk8815_i2c_data0 = { |
16 | /* keep defaults for timeouts; pins are push-pull bidirectional */ | 18 | /* keep defaults for timeouts; pins are push-pull bidirectional */ |
17 | .scl_pin = 62, | 19 | .scl_pin = 62, |
18 | .sda_pin = 63, | 20 | .sda_pin = 63, |
19 | }; | 21 | }; |
20 | 22 | ||
23 | /* I2C1 connected to various sensors */ | ||
21 | static struct i2c_gpio_platform_data nhk8815_i2c_data1 = { | 24 | static struct i2c_gpio_platform_data nhk8815_i2c_data1 = { |
22 | /* keep defaults for timeouts; pins are push-pull bidirectional */ | 25 | /* keep defaults for timeouts; pins are push-pull bidirectional */ |
23 | .scl_pin = 53, | 26 | .scl_pin = 53, |
24 | .sda_pin = 54, | 27 | .sda_pin = 54, |
25 | }; | 28 | }; |
26 | 29 | ||
27 | /* first bus: GPIO XX and YY */ | 30 | /* I2C2 connected to the USB portions of the STw4811 only */ |
31 | static struct i2c_gpio_platform_data nhk8815_i2c_data2 = { | ||
32 | /* keep defaults for timeouts; pins are push-pull bidirectional */ | ||
33 | .scl_pin = 73, | ||
34 | .sda_pin = 74, | ||
35 | }; | ||
36 | |||
28 | static struct platform_device nhk8815_i2c_dev0 = { | 37 | static struct platform_device nhk8815_i2c_dev0 = { |
29 | .name = "i2c-gpio", | 38 | .name = "i2c-gpio", |
30 | .id = 0, | 39 | .id = 0, |
@@ -32,7 +41,7 @@ static struct platform_device nhk8815_i2c_dev0 = { | |||
32 | .platform_data = &nhk8815_i2c_data0, | 41 | .platform_data = &nhk8815_i2c_data0, |
33 | }, | 42 | }, |
34 | }; | 43 | }; |
35 | /* second bus: GPIO XX and YY */ | 44 | |
36 | static struct platform_device nhk8815_i2c_dev1 = { | 45 | static struct platform_device nhk8815_i2c_dev1 = { |
37 | .name = "i2c-gpio", | 46 | .name = "i2c-gpio", |
38 | .id = 1, | 47 | .id = 1, |
@@ -41,15 +50,29 @@ static struct platform_device nhk8815_i2c_dev1 = { | |||
41 | }, | 50 | }, |
42 | }; | 51 | }; |
43 | 52 | ||
53 | static struct platform_device nhk8815_i2c_dev2 = { | ||
54 | .name = "i2c-gpio", | ||
55 | .id = 2, | ||
56 | .dev = { | ||
57 | .platform_data = &nhk8815_i2c_data2, | ||
58 | }, | ||
59 | }; | ||
60 | |||
61 | static pin_cfg_t cpu8815_pins_i2c[] = { | ||
62 | PIN_CFG_INPUT(62, GPIO, PULLUP), | ||
63 | PIN_CFG_INPUT(63, GPIO, PULLUP), | ||
64 | PIN_CFG_INPUT(53, GPIO, PULLUP), | ||
65 | PIN_CFG_INPUT(54, GPIO, PULLUP), | ||
66 | PIN_CFG_INPUT(73, GPIO, PULLUP), | ||
67 | PIN_CFG_INPUT(74, GPIO, PULLUP), | ||
68 | }; | ||
69 | |||
44 | static int __init nhk8815_i2c_init(void) | 70 | static int __init nhk8815_i2c_init(void) |
45 | { | 71 | { |
46 | nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO); | 72 | nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c)); |
47 | nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO); | ||
48 | platform_device_register(&nhk8815_i2c_dev0); | 73 | platform_device_register(&nhk8815_i2c_dev0); |
49 | |||
50 | nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO); | ||
51 | nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO); | ||
52 | platform_device_register(&nhk8815_i2c_dev1); | 74 | platform_device_register(&nhk8815_i2c_dev1); |
75 | platform_device_register(&nhk8815_i2c_dev2); | ||
53 | 76 | ||
54 | return 0; | 77 | return 0; |
55 | } | 78 | } |
@@ -58,6 +81,7 @@ static void __exit nhk8815_i2c_exit(void) | |||
58 | { | 81 | { |
59 | platform_device_unregister(&nhk8815_i2c_dev0); | 82 | platform_device_unregister(&nhk8815_i2c_dev0); |
60 | platform_device_unregister(&nhk8815_i2c_dev1); | 83 | platform_device_unregister(&nhk8815_i2c_dev1); |
84 | platform_device_unregister(&nhk8815_i2c_dev2); | ||
61 | return; | 85 | return; |
62 | } | 86 | } |
63 | 87 | ||
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h index 8faabc560398..a118e615f865 100644 --- a/arch/arm/mach-nomadik/include/mach/irqs.h +++ b/arch/arm/mach-nomadik/include/mach/irqs.h | |||
@@ -22,56 +22,56 @@ | |||
22 | 22 | ||
23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
24 | 24 | ||
25 | #define IRQ_VIC_START 0 /* first VIC interrupt is 0 */ | 25 | #define IRQ_VIC_START 1 /* first VIC interrupt is 1 */ |
26 | 26 | ||
27 | /* | 27 | /* |
28 | * Interrupt numbers generic for all Nomadik Chip cuts | 28 | * Interrupt numbers generic for all Nomadik Chip cuts |
29 | */ | 29 | */ |
30 | #define IRQ_WATCHDOG 0 | 30 | #define IRQ_WATCHDOG 1 |
31 | #define IRQ_SOFTINT 1 | 31 | #define IRQ_SOFTINT 2 |
32 | #define IRQ_CRYPTO 2 | 32 | #define IRQ_CRYPTO 3 |
33 | #define IRQ_OWM 3 | 33 | #define IRQ_OWM 4 |
34 | #define IRQ_MTU0 4 | 34 | #define IRQ_MTU0 5 |
35 | #define IRQ_MTU1 5 | 35 | #define IRQ_MTU1 6 |
36 | #define IRQ_GPIO0 6 | 36 | #define IRQ_GPIO0 7 |
37 | #define IRQ_GPIO1 7 | 37 | #define IRQ_GPIO1 8 |
38 | #define IRQ_GPIO2 8 | 38 | #define IRQ_GPIO2 9 |
39 | #define IRQ_GPIO3 9 | 39 | #define IRQ_GPIO3 10 |
40 | #define IRQ_RTC_RTT 10 | 40 | #define IRQ_RTC_RTT 11 |
41 | #define IRQ_SSP 11 | 41 | #define IRQ_SSP 12 |
42 | #define IRQ_UART0 12 | 42 | #define IRQ_UART0 13 |
43 | #define IRQ_DMA1 13 | 43 | #define IRQ_DMA1 14 |
44 | #define IRQ_CLCD_MDIF 14 | 44 | #define IRQ_CLCD_MDIF 15 |
45 | #define IRQ_DMA0 15 | 45 | #define IRQ_DMA0 16 |
46 | #define IRQ_PWRFAIL 16 | 46 | #define IRQ_PWRFAIL 17 |
47 | #define IRQ_UART1 17 | 47 | #define IRQ_UART1 18 |
48 | #define IRQ_FIRDA 18 | 48 | #define IRQ_FIRDA 19 |
49 | #define IRQ_MSP0 19 | 49 | #define IRQ_MSP0 20 |
50 | #define IRQ_I2C0 20 | 50 | #define IRQ_I2C0 21 |
51 | #define IRQ_I2C1 21 | 51 | #define IRQ_I2C1 22 |
52 | #define IRQ_SDMMC 22 | 52 | #define IRQ_SDMMC 23 |
53 | #define IRQ_USBOTG 23 | 53 | #define IRQ_USBOTG 24 |
54 | #define IRQ_SVA_IT0 24 | 54 | #define IRQ_SVA_IT0 25 |
55 | #define IRQ_SVA_IT1 25 | 55 | #define IRQ_SVA_IT1 26 |
56 | #define IRQ_SAA_IT0 26 | 56 | #define IRQ_SAA_IT0 27 |
57 | #define IRQ_SAA_IT1 27 | 57 | #define IRQ_SAA_IT1 28 |
58 | #define IRQ_UART2 28 | 58 | #define IRQ_UART2 29 |
59 | #define IRQ_MSP2 31 | 59 | #define IRQ_MSP2 30 |
60 | #define IRQ_L2CC 48 | 60 | #define IRQ_L2CC 49 |
61 | #define IRQ_HPI 49 | 61 | #define IRQ_HPI 50 |
62 | #define IRQ_SKE 50 | 62 | #define IRQ_SKE 51 |
63 | #define IRQ_KP 51 | 63 | #define IRQ_KP 52 |
64 | #define IRQ_MEMST 54 | 64 | #define IRQ_MEMST 55 |
65 | #define IRQ_SGA_IT 58 | 65 | #define IRQ_SGA_IT 59 |
66 | #define IRQ_USBM 60 | 66 | #define IRQ_USBM 61 |
67 | #define IRQ_MSP1 62 | 67 | #define IRQ_MSP1 63 |
68 | 68 | ||
69 | #define NOMADIK_SOC_NR_IRQS 64 | 69 | #define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) |
70 | 70 | ||
71 | /* After chip-specific IRQ numbers we have the GPIO ones */ | 71 | /* After chip-specific IRQ numbers we have the GPIO ones */ |
72 | #define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */ | 72 | #define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */ |
73 | #define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_SOC_NR_IRQS) | 73 | #define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET) |
74 | #define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_SOC_NR_IRQS) | 74 | #define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET) |
75 | #define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) | 75 | #define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) |
76 | 76 | ||
77 | /* Following two are used by entry_macro.S, to access our dual-vic */ | 77 | /* Following two are used by entry_macro.S, to access our dual-vic */ |
@@ -79,4 +79,3 @@ | |||
79 | #define VIC_REG_IRQSR1 0x20 | 79 | #define VIC_REG_IRQSR1 0x20 |
80 | 80 | ||
81 | #endif /* __ASM_ARCH_IRQS_H */ | 81 | #endif /* __ASM_ARCH_IRQS_H */ |
82 | |||
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index f2f8a5847018..c53469802c03 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
@@ -37,12 +37,12 @@ | |||
37 | #include <plat/board-ams-delta.h> | 37 | #include <plat/board-ams-delta.h> |
38 | #include <plat/keypad.h> | 38 | #include <plat/keypad.h> |
39 | #include <plat/mux.h> | 39 | #include <plat/mux.h> |
40 | #include <plat/usb.h> | ||
41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
42 | 41 | ||
43 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
44 | #include <mach/ams-delta-fiq.h> | 43 | #include <mach/ams-delta-fiq.h> |
45 | #include <mach/camera.h> | 44 | #include <mach/camera.h> |
45 | #include <mach/usb.h> | ||
46 | 46 | ||
47 | #include "iomap.h" | 47 | #include "iomap.h" |
48 | #include "common.h" | 48 | #include "common.h" |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index e75e2d55a2d7..6ec385e2b98e 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
@@ -23,8 +23,10 @@ | |||
23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
24 | 24 | ||
25 | #include <plat/mux.h> | 25 | #include <plat/mux.h> |
26 | #include <plat/usb.h> | ||
27 | #include <plat/board.h> | 26 | #include <plat/board.h> |
27 | |||
28 | #include <mach/usb.h> | ||
29 | |||
28 | #include "common.h" | 30 | #include "common.h" |
29 | 31 | ||
30 | /* assume no Mini-AB port */ | 32 | /* assume no Mini-AB port */ |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index a28e989a63f4..44a4ab195fbc 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
@@ -40,11 +40,11 @@ | |||
40 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
41 | #include <plat/tc.h> | 41 | #include <plat/tc.h> |
42 | #include <plat/irda.h> | 42 | #include <plat/irda.h> |
43 | #include <plat/usb.h> | ||
44 | #include <plat/keypad.h> | 43 | #include <plat/keypad.h> |
45 | #include <plat/flash.h> | 44 | #include <plat/flash.h> |
46 | 45 | ||
47 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
47 | #include <mach/usb.h> | ||
48 | 48 | ||
49 | #include "common.h" | 49 | #include "common.h" |
50 | #include "board-h2.h" | 50 | #include "board-h2.h" |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index 108a8640fc6f..86cb5a04a404 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
@@ -40,13 +40,13 @@ | |||
40 | 40 | ||
41 | #include <plat/mux.h> | 41 | #include <plat/mux.h> |
42 | #include <plat/tc.h> | 42 | #include <plat/tc.h> |
43 | #include <plat/usb.h> | ||
44 | #include <plat/keypad.h> | 43 | #include <plat/keypad.h> |
45 | #include <plat/dma.h> | 44 | #include <plat/dma.h> |
46 | #include <plat/flash.h> | 45 | #include <plat/flash.h> |
47 | 46 | ||
48 | #include <mach/hardware.h> | 47 | #include <mach/hardware.h> |
49 | #include <mach/irqs.h> | 48 | #include <mach/irqs.h> |
49 | #include <mach/usb.h> | ||
50 | 50 | ||
51 | #include "common.h" | 51 | #include "common.h" |
52 | #include "board-h3.h" | 52 | #include "board-h3.h" |
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c index 118a9d4a4c54..b3f6e943e661 100644 --- a/arch/arm/mach-omap1/board-htcherald.c +++ b/arch/arm/mach-omap1/board-htcherald.c | |||
@@ -44,10 +44,10 @@ | |||
44 | #include <plat/omap7xx.h> | 44 | #include <plat/omap7xx.h> |
45 | #include <plat/board.h> | 45 | #include <plat/board.h> |
46 | #include <plat/keypad.h> | 46 | #include <plat/keypad.h> |
47 | #include <plat/usb.h> | ||
48 | #include <plat/mmc.h> | 47 | #include <plat/mmc.h> |
49 | 48 | ||
50 | #include <mach/irqs.h> | 49 | #include <mach/irqs.h> |
50 | #include <mach/usb.h> | ||
51 | 51 | ||
52 | #include "common.h" | 52 | #include "common.h" |
53 | 53 | ||
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 7970223a559d..f21c2966daad 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
@@ -35,11 +35,11 @@ | |||
35 | #include <plat/flash.h> | 35 | #include <plat/flash.h> |
36 | #include <plat/fpga.h> | 36 | #include <plat/fpga.h> |
37 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
38 | #include <plat/usb.h> | ||
39 | #include <plat/keypad.h> | 38 | #include <plat/keypad.h> |
40 | #include <plat/mmc.h> | 39 | #include <plat/mmc.h> |
41 | 40 | ||
42 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
42 | #include <mach/usb.h> | ||
43 | 43 | ||
44 | #include "iomap.h" | 44 | #include "iomap.h" |
45 | #include "common.h" | 45 | #include "common.h" |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index 7212ae97f44a..4007a372481b 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
27 | 27 | ||
28 | #include <plat/mux.h> | 28 | #include <plat/mux.h> |
29 | #include <plat/usb.h> | ||
30 | #include <plat/board.h> | 29 | #include <plat/board.h> |
31 | #include <plat/keypad.h> | 30 | #include <plat/keypad.h> |
32 | #include <plat/lcd_mipid.h> | 31 | #include <plat/lcd_mipid.h> |
@@ -34,6 +33,7 @@ | |||
34 | #include <plat/clock.h> | 33 | #include <plat/clock.h> |
35 | 34 | ||
36 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
36 | #include <mach/usb.h> | ||
37 | 37 | ||
38 | #include "common.h" | 38 | #include "common.h" |
39 | 39 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index da8d872d3d1c..8784705edb60 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
@@ -45,11 +45,11 @@ | |||
45 | #include <asm/mach/map.h> | 45 | #include <asm/mach/map.h> |
46 | 46 | ||
47 | #include <plat/flash.h> | 47 | #include <plat/flash.h> |
48 | #include <plat/usb.h> | ||
49 | #include <plat/mux.h> | 48 | #include <plat/mux.h> |
50 | #include <plat/tc.h> | 49 | #include <plat/tc.h> |
51 | 50 | ||
52 | #include <mach/hardware.h> | 51 | #include <mach/hardware.h> |
52 | #include <mach/usb.h> | ||
53 | 53 | ||
54 | #include "common.h" | 54 | #include "common.h" |
55 | 55 | ||
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 949b62a73693..26bcb9defcdc 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
@@ -35,7 +35,6 @@ | |||
35 | 35 | ||
36 | #include <plat/flash.h> | 36 | #include <plat/flash.h> |
37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <plat/usb.h> | ||
39 | #include <plat/tc.h> | 38 | #include <plat/tc.h> |
40 | #include <plat/dma.h> | 39 | #include <plat/dma.h> |
41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
@@ -43,6 +42,7 @@ | |||
43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
44 | 43 | ||
45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
45 | #include <mach/usb.h> | ||
46 | 46 | ||
47 | #include "common.h" | 47 | #include "common.h" |
48 | 48 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 7f1e1cf2bf46..4d099446dfa8 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
@@ -35,7 +35,6 @@ | |||
35 | #include <plat/led.h> | 35 | #include <plat/led.h> |
36 | #include <plat/flash.h> | 36 | #include <plat/flash.h> |
37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <plat/usb.h> | ||
39 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
40 | #include <plat/tc.h> | 39 | #include <plat/tc.h> |
41 | #include <plat/board.h> | 40 | #include <plat/board.h> |
@@ -43,6 +42,7 @@ | |||
43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
44 | 43 | ||
45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
45 | #include <mach/usb.h> | ||
46 | 46 | ||
47 | #include "common.h" | 47 | #include "common.h" |
48 | 48 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index 3c71c6bace2c..cc71a26723ef 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
@@ -37,7 +37,6 @@ | |||
37 | 37 | ||
38 | #include <plat/flash.h> | 38 | #include <plat/flash.h> |
39 | #include <plat/mux.h> | 39 | #include <plat/mux.h> |
40 | #include <plat/usb.h> | ||
41 | #include <plat/dma.h> | 40 | #include <plat/dma.h> |
42 | #include <plat/tc.h> | 41 | #include <plat/tc.h> |
43 | #include <plat/board.h> | 42 | #include <plat/board.h> |
@@ -45,6 +44,7 @@ | |||
45 | #include <plat/keypad.h> | 44 | #include <plat/keypad.h> |
46 | 45 | ||
47 | #include <mach/hardware.h> | 46 | #include <mach/hardware.h> |
47 | #include <mach/usb.h> | ||
48 | 48 | ||
49 | #include "common.h" | 49 | #include "common.h" |
50 | 50 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 3b7b82b13684..8c665bd16ac2 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
@@ -37,13 +37,13 @@ | |||
37 | #include <plat/mux.h> | 37 | #include <plat/mux.h> |
38 | #include <plat/dma.h> | 38 | #include <plat/dma.h> |
39 | #include <plat/irda.h> | 39 | #include <plat/irda.h> |
40 | #include <plat/usb.h> | ||
41 | #include <plat/tc.h> | 40 | #include <plat/tc.h> |
42 | #include <plat/board.h> | 41 | #include <plat/board.h> |
43 | #include <plat/keypad.h> | 42 | #include <plat/keypad.h> |
44 | #include <plat/board-sx1.h> | 43 | #include <plat/board-sx1.h> |
45 | 44 | ||
46 | #include <mach/hardware.h> | 45 | #include <mach/hardware.h> |
46 | #include <mach/usb.h> | ||
47 | 47 | ||
48 | #include "common.h" | 48 | #include "common.h" |
49 | 49 | ||
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index afd67f0ec495..3497769eb353 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
@@ -35,9 +35,10 @@ | |||
35 | #include <plat/flash.h> | 35 | #include <plat/flash.h> |
36 | #include <plat/mux.h> | 36 | #include <plat/mux.h> |
37 | #include <plat/tc.h> | 37 | #include <plat/tc.h> |
38 | #include <plat/usb.h> | 38 | #include <plat/board.h> |
39 | 39 | ||
40 | #include <mach/hardware.h> | 40 | #include <mach/hardware.h> |
41 | #include <mach/usb.h> | ||
41 | 42 | ||
42 | #include "common.h" | 43 | #include "common.h" |
43 | 44 | ||
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c index c6ce93f71d08..c007d80dfb62 100644 --- a/arch/arm/mach-omap1/clock_data.c +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -25,10 +25,11 @@ | |||
25 | #include <plat/clock.h> | 25 | #include <plat/clock.h> |
26 | #include <plat/cpu.h> | 26 | #include <plat/cpu.h> |
27 | #include <plat/clkdev_omap.h> | 27 | #include <plat/clkdev_omap.h> |
28 | #include <plat/board.h> | ||
28 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ | 29 | #include <plat/sram.h> /* for omap_sram_reprogram_clock() */ |
29 | #include <plat/usb.h> /* for OTG_BASE */ | ||
30 | 30 | ||
31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
32 | #include <mach/usb.h> /* for OTG_BASE */ | ||
32 | 33 | ||
33 | #include "iomap.h" | 34 | #include "iomap.h" |
34 | #include "clock.h" | 35 | #include "clock.h" |
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h new file mode 100644 index 000000000000..753cd5ce6949 --- /dev/null +++ b/arch/arm/mach-omap1/include/mach/usb.h | |||
@@ -0,0 +1,165 @@ | |||
1 | /* | ||
2 | * FIXME correct answer depends on hmc_mode, | ||
3 | * as does (on omap1) any nonzero value for config->otg port number | ||
4 | */ | ||
5 | #ifdef CONFIG_USB_GADGET_OMAP | ||
6 | #define is_usb0_device(config) 1 | ||
7 | #else | ||
8 | #define is_usb0_device(config) 0 | ||
9 | #endif | ||
10 | |||
11 | struct omap_usb_config { | ||
12 | /* Configure drivers according to the connectors on your board: | ||
13 | * - "A" connector (rectagular) | ||
14 | * ... for host/OHCI use, set "register_host". | ||
15 | * - "B" connector (squarish) or "Mini-B" | ||
16 | * ... for device/gadget use, set "register_dev". | ||
17 | * - "Mini-AB" connector (very similar to Mini-B) | ||
18 | * ... for OTG use as device OR host, initialize "otg" | ||
19 | */ | ||
20 | unsigned register_host:1; | ||
21 | unsigned register_dev:1; | ||
22 | u8 otg; /* port number, 1-based: usb1 == 2 */ | ||
23 | |||
24 | u8 hmc_mode; | ||
25 | |||
26 | /* implicitly true if otg: host supports remote wakeup? */ | ||
27 | u8 rwc; | ||
28 | |||
29 | /* signaling pins used to talk to transceiver on usbN: | ||
30 | * 0 == usbN unused | ||
31 | * 2 == usb0-only, using internal transceiver | ||
32 | * 3 == 3 wire bidirectional | ||
33 | * 4 == 4 wire bidirectional | ||
34 | * 6 == 6 wire unidirectional (or TLL) | ||
35 | */ | ||
36 | u8 pins[3]; | ||
37 | |||
38 | struct platform_device *udc_device; | ||
39 | struct platform_device *ohci_device; | ||
40 | struct platform_device *otg_device; | ||
41 | |||
42 | u32 (*usb0_init)(unsigned nwires, unsigned is_device); | ||
43 | u32 (*usb1_init)(unsigned nwires); | ||
44 | u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); | ||
45 | |||
46 | int (*ocpi_enable)(void); | ||
47 | }; | ||
48 | |||
49 | void omap_otg_init(struct omap_usb_config *config); | ||
50 | |||
51 | #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) | ||
52 | void omap1_usb_init(struct omap_usb_config *pdata); | ||
53 | #else | ||
54 | static inline void omap1_usb_init(struct omap_usb_config *pdata) | ||
55 | { | ||
56 | } | ||
57 | #endif | ||
58 | |||
59 | #define OMAP1_OTG_BASE 0xfffb0400 | ||
60 | #define OMAP1_UDC_BASE 0xfffb4000 | ||
61 | #define OMAP1_OHCI_BASE 0xfffba000 | ||
62 | |||
63 | #define OMAP2_OHCI_BASE 0x4805e000 | ||
64 | #define OMAP2_UDC_BASE 0x4805e200 | ||
65 | #define OMAP2_OTG_BASE 0x4805e300 | ||
66 | #define OTG_BASE OMAP1_OTG_BASE | ||
67 | #define UDC_BASE OMAP1_UDC_BASE | ||
68 | #define OMAP_OHCI_BASE OMAP1_OHCI_BASE | ||
69 | |||
70 | /* | ||
71 | * OTG and transceiver registers, for OMAPs starting with ARM926 | ||
72 | */ | ||
73 | #define OTG_REV (OTG_BASE + 0x00) | ||
74 | #define OTG_SYSCON_1 (OTG_BASE + 0x04) | ||
75 | # define USB2_TRX_MODE(w) (((w)>>24)&0x07) | ||
76 | # define USB1_TRX_MODE(w) (((w)>>20)&0x07) | ||
77 | # define USB0_TRX_MODE(w) (((w)>>16)&0x07) | ||
78 | # define OTG_IDLE_EN (1 << 15) | ||
79 | # define HST_IDLE_EN (1 << 14) | ||
80 | # define DEV_IDLE_EN (1 << 13) | ||
81 | # define OTG_RESET_DONE (1 << 2) | ||
82 | # define OTG_SOFT_RESET (1 << 1) | ||
83 | #define OTG_SYSCON_2 (OTG_BASE + 0x08) | ||
84 | # define OTG_EN (1 << 31) | ||
85 | # define USBX_SYNCHRO (1 << 30) | ||
86 | # define OTG_MST16 (1 << 29) | ||
87 | # define SRP_GPDATA (1 << 28) | ||
88 | # define SRP_GPDVBUS (1 << 27) | ||
89 | # define SRP_GPUVBUS(w) (((w)>>24)&0x07) | ||
90 | # define A_WAIT_VRISE(w) (((w)>>20)&0x07) | ||
91 | # define B_ASE_BRST(w) (((w)>>16)&0x07) | ||
92 | # define SRP_DPW (1 << 14) | ||
93 | # define SRP_DATA (1 << 13) | ||
94 | # define SRP_VBUS (1 << 12) | ||
95 | # define OTG_PADEN (1 << 10) | ||
96 | # define HMC_PADEN (1 << 9) | ||
97 | # define UHOST_EN (1 << 8) | ||
98 | # define HMC_TLLSPEED (1 << 7) | ||
99 | # define HMC_TLLATTACH (1 << 6) | ||
100 | # define OTG_HMC(w) (((w)>>0)&0x3f) | ||
101 | #define OTG_CTRL (OTG_BASE + 0x0c) | ||
102 | # define OTG_USB2_EN (1 << 29) | ||
103 | # define OTG_USB2_DP (1 << 28) | ||
104 | # define OTG_USB2_DM (1 << 27) | ||
105 | # define OTG_USB1_EN (1 << 26) | ||
106 | # define OTG_USB1_DP (1 << 25) | ||
107 | # define OTG_USB1_DM (1 << 24) | ||
108 | # define OTG_USB0_EN (1 << 23) | ||
109 | # define OTG_USB0_DP (1 << 22) | ||
110 | # define OTG_USB0_DM (1 << 21) | ||
111 | # define OTG_ASESSVLD (1 << 20) | ||
112 | # define OTG_BSESSEND (1 << 19) | ||
113 | # define OTG_BSESSVLD (1 << 18) | ||
114 | # define OTG_VBUSVLD (1 << 17) | ||
115 | # define OTG_ID (1 << 16) | ||
116 | # define OTG_DRIVER_SEL (1 << 15) | ||
117 | # define OTG_A_SETB_HNPEN (1 << 12) | ||
118 | # define OTG_A_BUSREQ (1 << 11) | ||
119 | # define OTG_B_HNPEN (1 << 9) | ||
120 | # define OTG_B_BUSREQ (1 << 8) | ||
121 | # define OTG_BUSDROP (1 << 7) | ||
122 | # define OTG_PULLDOWN (1 << 5) | ||
123 | # define OTG_PULLUP (1 << 4) | ||
124 | # define OTG_DRV_VBUS (1 << 3) | ||
125 | # define OTG_PD_VBUS (1 << 2) | ||
126 | # define OTG_PU_VBUS (1 << 1) | ||
127 | # define OTG_PU_ID (1 << 0) | ||
128 | #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ | ||
129 | # define DRIVER_SWITCH (1 << 15) | ||
130 | # define A_VBUS_ERR (1 << 13) | ||
131 | # define A_REQ_TMROUT (1 << 12) | ||
132 | # define A_SRP_DETECT (1 << 11) | ||
133 | # define B_HNP_FAIL (1 << 10) | ||
134 | # define B_SRP_TMROUT (1 << 9) | ||
135 | # define B_SRP_DONE (1 << 8) | ||
136 | # define B_SRP_STARTED (1 << 7) | ||
137 | # define OPRT_CHG (1 << 0) | ||
138 | #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ | ||
139 | // same bits as in IRQ_EN | ||
140 | #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ | ||
141 | # define OTGVPD (1 << 14) | ||
142 | # define OTGVPU (1 << 13) | ||
143 | # define OTGPUID (1 << 12) | ||
144 | # define USB2VDR (1 << 10) | ||
145 | # define USB2PDEN (1 << 9) | ||
146 | # define USB2PUEN (1 << 8) | ||
147 | # define USB1VDR (1 << 6) | ||
148 | # define USB1PDEN (1 << 5) | ||
149 | # define USB1PUEN (1 << 4) | ||
150 | # define USB0VDR (1 << 2) | ||
151 | # define USB0PDEN (1 << 1) | ||
152 | # define USB0PUEN (1 << 0) | ||
153 | #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ | ||
154 | #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ | ||
155 | |||
156 | /*-------------------------------------------------------------------------*/ | ||
157 | |||
158 | /* OMAP1 */ | ||
159 | #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) | ||
160 | # define CONF_USB2_UNI_R (1 << 8) | ||
161 | # define CONF_USB1_UNI_R (1 << 7) | ||
162 | # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) | ||
163 | # define CONF_USB0_ISOLATE_R (1 << 3) | ||
164 | # define CONF_USB_PWRDN_DM_R (1 << 2) | ||
165 | # define CONF_USB_PWRDN_DP_R (1 << 1) | ||
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index e61afd922766..65f88176fba8 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c | |||
@@ -27,7 +27,8 @@ | |||
27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
28 | 28 | ||
29 | #include <plat/mux.h> | 29 | #include <plat/mux.h> |
30 | #include <plat/usb.h> | 30 | |
31 | #include <mach/usb.h> | ||
31 | 32 | ||
32 | #include "common.h" | 33 | #include "common.h" |
33 | 34 | ||
@@ -55,6 +56,119 @@ | |||
55 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 | 56 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 |
56 | #define INT_USB_IRQ_OTG IH2_BASE + 8 | 57 | #define INT_USB_IRQ_OTG IH2_BASE + 8 |
57 | 58 | ||
59 | #ifdef CONFIG_ARCH_OMAP_OTG | ||
60 | |||
61 | void __init | ||
62 | omap_otg_init(struct omap_usb_config *config) | ||
63 | { | ||
64 | u32 syscon; | ||
65 | int alt_pingroup = 0; | ||
66 | |||
67 | /* NOTE: no bus or clock setup (yet?) */ | ||
68 | |||
69 | syscon = omap_readl(OTG_SYSCON_1) & 0xffff; | ||
70 | if (!(syscon & OTG_RESET_DONE)) | ||
71 | pr_debug("USB resets not complete?\n"); | ||
72 | |||
73 | //omap_writew(0, OTG_IRQ_EN); | ||
74 | |||
75 | /* pin muxing and transceiver pinouts */ | ||
76 | if (config->pins[0] > 2) /* alt pingroup 2 */ | ||
77 | alt_pingroup = 1; | ||
78 | syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); | ||
79 | syscon |= config->usb1_init(config->pins[1]); | ||
80 | syscon |= config->usb2_init(config->pins[2], alt_pingroup); | ||
81 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
82 | omap_writel(syscon, OTG_SYSCON_1); | ||
83 | |||
84 | syscon = config->hmc_mode; | ||
85 | syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; | ||
86 | #ifdef CONFIG_USB_OTG | ||
87 | if (config->otg) | ||
88 | syscon |= OTG_EN; | ||
89 | #endif | ||
90 | if (cpu_class_is_omap1()) | ||
91 | pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", | ||
92 | omap_readl(USB_TRANSCEIVER_CTRL)); | ||
93 | pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); | ||
94 | omap_writel(syscon, OTG_SYSCON_2); | ||
95 | |||
96 | printk("USB: hmc %d", config->hmc_mode); | ||
97 | if (!alt_pingroup) | ||
98 | printk(", usb2 alt %d wires", config->pins[2]); | ||
99 | else if (config->pins[0]) | ||
100 | printk(", usb0 %d wires%s", config->pins[0], | ||
101 | is_usb0_device(config) ? " (dev)" : ""); | ||
102 | if (config->pins[1]) | ||
103 | printk(", usb1 %d wires", config->pins[1]); | ||
104 | if (!alt_pingroup && config->pins[2]) | ||
105 | printk(", usb2 %d wires", config->pins[2]); | ||
106 | if (config->otg) | ||
107 | printk(", Mini-AB on usb%d", config->otg - 1); | ||
108 | printk("\n"); | ||
109 | |||
110 | if (cpu_class_is_omap1()) { | ||
111 | u16 w; | ||
112 | |||
113 | /* leave USB clocks/controllers off until needed */ | ||
114 | w = omap_readw(ULPD_SOFT_REQ); | ||
115 | w &= ~SOFT_USB_CLK_REQ; | ||
116 | omap_writew(w, ULPD_SOFT_REQ); | ||
117 | |||
118 | w = omap_readw(ULPD_CLOCK_CTRL); | ||
119 | w &= ~USB_MCLK_EN; | ||
120 | w |= DIS_USB_PVCI_CLK; | ||
121 | omap_writew(w, ULPD_CLOCK_CTRL); | ||
122 | } | ||
123 | syscon = omap_readl(OTG_SYSCON_1); | ||
124 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; | ||
125 | |||
126 | #ifdef CONFIG_USB_GADGET_OMAP | ||
127 | if (config->otg || config->register_dev) { | ||
128 | struct platform_device *udc_device = config->udc_device; | ||
129 | int status; | ||
130 | |||
131 | syscon &= ~DEV_IDLE_EN; | ||
132 | udc_device->dev.platform_data = config; | ||
133 | status = platform_device_register(udc_device); | ||
134 | if (status) | ||
135 | pr_debug("can't register UDC device, %d\n", status); | ||
136 | } | ||
137 | #endif | ||
138 | |||
139 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
140 | if (config->otg || config->register_host) { | ||
141 | struct platform_device *ohci_device = config->ohci_device; | ||
142 | int status; | ||
143 | |||
144 | syscon &= ~HST_IDLE_EN; | ||
145 | ohci_device->dev.platform_data = config; | ||
146 | status = platform_device_register(ohci_device); | ||
147 | if (status) | ||
148 | pr_debug("can't register OHCI device, %d\n", status); | ||
149 | } | ||
150 | #endif | ||
151 | |||
152 | #ifdef CONFIG_USB_OTG | ||
153 | if (config->otg) { | ||
154 | struct platform_device *otg_device = config->otg_device; | ||
155 | int status; | ||
156 | |||
157 | syscon &= ~OTG_IDLE_EN; | ||
158 | otg_device->dev.platform_data = config; | ||
159 | status = platform_device_register(otg_device); | ||
160 | if (status) | ||
161 | pr_debug("can't register OTG device, %d\n", status); | ||
162 | } | ||
163 | #endif | ||
164 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
165 | omap_writel(syscon, OTG_SYSCON_1); | ||
166 | } | ||
167 | |||
168 | #else | ||
169 | void omap_otg_init(struct omap_usb_config *config) {} | ||
170 | #endif | ||
171 | |||
58 | #ifdef CONFIG_USB_GADGET_OMAP | 172 | #ifdef CONFIG_USB_GADGET_OMAP |
59 | 173 | ||
60 | static struct resource udc_resources[] = { | 174 | static struct resource udc_resources[] = { |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 4cf5142f22cc..184469517f15 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -35,6 +35,7 @@ config ARCH_OMAP3 | |||
35 | select CPU_V7 | 35 | select CPU_V7 |
36 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 36 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
37 | select ARCH_HAS_OPP | 37 | select ARCH_HAS_OPP |
38 | select PM_RUNTIME if CPU_IDLE | ||
38 | select PM_OPP if PM | 39 | select PM_OPP if PM |
39 | select ARM_CPU_SUSPEND if PM | 40 | select ARM_CPU_SUSPEND if PM |
40 | select MULTI_IRQ_HANDLER | 41 | select MULTI_IRQ_HANDLER |
@@ -52,6 +53,7 @@ config ARCH_OMAP4 | |||
52 | select PL310_ERRATA_727915 | 53 | select PL310_ERRATA_727915 |
53 | select ARM_ERRATA_720789 | 54 | select ARM_ERRATA_720789 |
54 | select ARCH_HAS_OPP | 55 | select ARCH_HAS_OPP |
56 | select PM_RUNTIME if CPU_IDLE | ||
55 | select PM_OPP if PM | 57 | select PM_OPP if PM |
56 | select USB_ARCH_HAS_EHCI if USB_SUPPORT | 58 | select USB_ARCH_HAS_EHCI if USB_SUPPORT |
57 | select ARM_CPU_SUSPEND if PM | 59 | select ARM_CPU_SUSPEND if PM |
@@ -64,19 +66,16 @@ config SOC_OMAP2420 | |||
64 | depends on ARCH_OMAP2 | 66 | depends on ARCH_OMAP2 |
65 | default y | 67 | default y |
66 | select OMAP_DM_TIMER | 68 | select OMAP_DM_TIMER |
67 | select ARCH_OMAP_OTG | ||
68 | 69 | ||
69 | config SOC_OMAP2430 | 70 | config SOC_OMAP2430 |
70 | bool "OMAP2430 support" | 71 | bool "OMAP2430 support" |
71 | depends on ARCH_OMAP2 | 72 | depends on ARCH_OMAP2 |
72 | default y | 73 | default y |
73 | select ARCH_OMAP_OTG | ||
74 | 74 | ||
75 | config SOC_OMAP3430 | 75 | config SOC_OMAP3430 |
76 | bool "OMAP3430 support" | 76 | bool "OMAP3430 support" |
77 | depends on ARCH_OMAP3 | 77 | depends on ARCH_OMAP3 |
78 | default y | 78 | default y |
79 | select ARCH_OMAP_OTG | ||
80 | 79 | ||
81 | config SOC_TI81XX | 80 | config SOC_TI81XX |
82 | bool "TI81XX support" | 81 | bool "TI81XX support" |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index fa742f3c2629..821794fd03d6 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -66,9 +66,7 @@ ifeq ($(CONFIG_PM),y) | |||
66 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o | 66 | obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o |
67 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o | 67 | obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o |
68 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o | 68 | obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o |
69 | obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o | ||
70 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o | 69 | obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o |
71 | obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o | ||
72 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o | 70 | obj-$(CONFIG_PM_DEBUG) += pm-debug.o |
73 | obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o | 71 | obj-$(CONFIG_OMAP_SMARTREFLEX) += sr_device.o smartreflex.o |
74 | obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o | 72 | obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3) += smartreflex-class3.o |
@@ -82,6 +80,11 @@ endif | |||
82 | 80 | ||
83 | endif | 81 | endif |
84 | 82 | ||
83 | ifeq ($(CONFIG_CPU_IDLE),y) | ||
84 | obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o | ||
85 | obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o | ||
86 | endif | ||
87 | |||
85 | # PRCM | 88 | # PRCM |
86 | obj-y += prm_common.o | 89 | obj-y += prm_common.o |
87 | obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o | 90 | obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o |
@@ -90,6 +93,7 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o | |||
90 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o | 93 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o |
91 | obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o | 94 | obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o |
92 | obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o | 95 | obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o |
96 | obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o | ||
93 | 97 | ||
94 | # OMAP voltage domains | 98 | # OMAP voltage domains |
95 | voltagedomain-common := voltage.o vc.o vp.o | 99 | voltagedomain-common := voltage.o vc.o vp.o |
@@ -99,6 +103,7 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) | |||
99 | obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o | 103 | obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o |
100 | obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) | 104 | obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) |
101 | obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o | 105 | obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o |
106 | obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o | ||
102 | 107 | ||
103 | # OMAP powerdomain framework | 108 | # OMAP powerdomain framework |
104 | powerdomain-common += powerdomain.o powerdomain-common.o | 109 | powerdomain-common += powerdomain.o powerdomain-common.o |
@@ -113,10 +118,11 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o | |||
113 | obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) | 118 | obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) |
114 | obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o | 119 | obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o |
115 | obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o | 120 | obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o |
121 | obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o | ||
122 | obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o | ||
116 | 123 | ||
117 | # PRCM clockdomain control | 124 | # PRCM clockdomain control |
118 | clockdomain-common += clockdomain.o | 125 | clockdomain-common += clockdomain.o |
119 | clockdomain-common += clockdomains_common_data.o | ||
120 | obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) | 126 | obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) |
121 | obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o | 127 | obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o |
122 | obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o | 128 | obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o |
@@ -129,6 +135,8 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o | |||
129 | obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) | 135 | obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) |
130 | obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o | 136 | obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o |
131 | obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o | 137 | obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o |
138 | obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o | ||
139 | obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o | ||
132 | 140 | ||
133 | # Clock framework | 141 | # Clock framework |
134 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o | 142 | obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o |
@@ -244,9 +252,6 @@ obj-y += $(omap-flash-y) $(omap-flash-m) | |||
244 | omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o | 252 | omap-hsmmc-$(CONFIG_MMC_OMAP_HS) := hsmmc.o |
245 | obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) | 253 | obj-y += $(omap-hsmmc-m) $(omap-hsmmc-y) |
246 | 254 | ||
247 | |||
248 | usbfs-$(CONFIG_ARCH_OMAP_OTG) := usb-fs.o | ||
249 | obj-y += $(usbfs-m) $(usbfs-y) | ||
250 | obj-y += usb-musb.o | 255 | obj-y += usb-musb.o |
251 | obj-y += omap_phy_internal.o | 256 | obj-y += omap_phy_internal.o |
252 | 257 | ||
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c index 447682c4e11c..2c90ac686686 100644 --- a/arch/arm/mach-omap2/am35xx-emac.c +++ b/arch/arm/mach-omap2/am35xx-emac.c | |||
@@ -15,27 +15,13 @@ | |||
15 | * General Public License for more details. | 15 | * General Public License for more details. |
16 | */ | 16 | */ |
17 | 17 | ||
18 | #include <linux/clk.h> | 18 | #include <linux/err.h> |
19 | #include <linux/davinci_emac.h> | 19 | #include <linux/davinci_emac.h> |
20 | #include <linux/platform_device.h> | 20 | #include <asm/system.h> |
21 | #include <plat/irqs.h> | 21 | #include <plat/omap_device.h> |
22 | #include <mach/am35xx.h> | 22 | #include <mach/am35xx.h> |
23 | |||
24 | #include "control.h" | 23 | #include "control.h" |
25 | 24 | #include "am35xx-emac.h" | |
26 | static struct mdio_platform_data am35xx_emac_mdio_pdata; | ||
27 | |||
28 | static struct resource am35xx_emac_mdio_resources[] = { | ||
29 | DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K), | ||
30 | }; | ||
31 | |||
32 | static struct platform_device am35xx_emac_mdio_device = { | ||
33 | .name = "davinci_mdio", | ||
34 | .id = 0, | ||
35 | .num_resources = ARRAY_SIZE(am35xx_emac_mdio_resources), | ||
36 | .resource = am35xx_emac_mdio_resources, | ||
37 | .dev.platform_data = &am35xx_emac_mdio_pdata, | ||
38 | }; | ||
39 | 25 | ||
40 | static void am35xx_enable_emac_int(void) | 26 | static void am35xx_enable_emac_int(void) |
41 | { | 27 | { |
@@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = { | |||
69 | .interrupt_disable = am35xx_disable_emac_int, | 55 | .interrupt_disable = am35xx_disable_emac_int, |
70 | }; | 56 | }; |
71 | 57 | ||
72 | static struct resource am35xx_emac_resources[] = { | 58 | static struct mdio_platform_data am35xx_mdio_pdata; |
73 | DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000), | ||
74 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ), | ||
75 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ), | ||
76 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ), | ||
77 | DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ), | ||
78 | }; | ||
79 | 59 | ||
80 | static struct platform_device am35xx_emac_device = { | 60 | static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh, |
81 | .name = "davinci_emac", | 61 | void *pdata, int pdata_len) |
82 | .id = -1, | 62 | { |
83 | .num_resources = ARRAY_SIZE(am35xx_emac_resources), | 63 | struct platform_device *pdev; |
84 | .resource = am35xx_emac_resources, | 64 | |
85 | .dev = { | 65 | pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, |
86 | .platform_data = &am35xx_emac_pdata, | 66 | NULL, 0, false); |
87 | }, | 67 | if (IS_ERR(pdev)) { |
88 | }; | 68 | WARN(1, "Can't build omap_device for %s:%s.\n", |
69 | oh->class->name, oh->name); | ||
70 | return PTR_ERR(pdev); | ||
71 | } | ||
72 | |||
73 | return 0; | ||
74 | } | ||
89 | 75 | ||
90 | void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) | 76 | void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en) |
91 | { | 77 | { |
78 | struct omap_hwmod *oh; | ||
92 | u32 v; | 79 | u32 v; |
93 | int err; | 80 | int ret; |
94 | 81 | ||
95 | am35xx_emac_pdata.rmii_en = rmii_en; | 82 | oh = omap_hwmod_lookup("davinci_mdio"); |
96 | am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq; | 83 | if (!oh) { |
97 | err = platform_device_register(&am35xx_emac_device); | 84 | pr_err("Could not find davinci_mdio hwmod\n"); |
98 | if (err) { | 85 | return; |
99 | pr_err("AM35x: failed registering EMAC device: %d\n", err); | 86 | } |
87 | |||
88 | am35xx_mdio_pdata.bus_freq = mdio_bus_freq; | ||
89 | |||
90 | ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata, | ||
91 | sizeof(am35xx_mdio_pdata)); | ||
92 | if (ret) { | ||
93 | pr_err("Could not build davinci_mdio hwmod device\n"); | ||
100 | return; | 94 | return; |
101 | } | 95 | } |
102 | 96 | ||
103 | err = platform_device_register(&am35xx_emac_mdio_device); | 97 | oh = omap_hwmod_lookup("davinci_emac"); |
104 | if (err) { | 98 | if (!oh) { |
105 | pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err); | 99 | pr_err("Could not find davinci_emac hwmod\n"); |
106 | platform_device_unregister(&am35xx_emac_device); | 100 | return; |
101 | } | ||
102 | |||
103 | am35xx_emac_pdata.rmii_en = rmii_en; | ||
104 | |||
105 | ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata, | ||
106 | sizeof(am35xx_emac_pdata)); | ||
107 | if (ret) { | ||
108 | pr_err("Could not build davinci_emac hwmod device\n"); | ||
107 | return; | 109 | return; |
108 | } | 110 | } |
109 | 111 | ||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 99ca6bad5c30..9511584fdc4f 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = { | |||
218 | }; | 218 | }; |
219 | 219 | ||
220 | static struct twl4030_platform_data sdp2430_twldata = { | 220 | static struct twl4030_platform_data sdp2430_twldata = { |
221 | .irq_base = TWL4030_IRQ_BASE, | ||
222 | .irq_end = TWL4030_IRQ_END, | ||
223 | |||
224 | /* platform_data for children goes here */ | 221 | /* platform_data for children goes here */ |
225 | .gpio = &sdp2430_gpio_data, | 222 | .gpio = &sdp2430_gpio_data, |
226 | .vmmc1 = &sdp2430_vmmc1, | 223 | .vmmc1 = &sdp2430_vmmc1, |
@@ -254,16 +251,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = { | |||
254 | {} /* Terminator */ | 251 | {} /* Terminator */ |
255 | }; | 252 | }; |
256 | 253 | ||
257 | static struct omap_usb_config sdp2430_usb_config __initdata = { | ||
258 | .otg = 1, | ||
259 | #ifdef CONFIG_USB_GADGET_OMAP | ||
260 | .hmc_mode = 0x0, | ||
261 | #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
262 | .hmc_mode = 0x1, | ||
263 | #endif | ||
264 | .pins[0] = 3, | ||
265 | }; | ||
266 | |||
267 | #ifdef CONFIG_OMAP_MUX | 254 | #ifdef CONFIG_OMAP_MUX |
268 | static struct omap_board_mux board_mux[] __initdata = { | 255 | static struct omap_board_mux board_mux[] __initdata = { |
269 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 256 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
@@ -280,7 +267,6 @@ static void __init omap_2430sdp_init(void) | |||
280 | omap_serial_init(); | 267 | omap_serial_init(); |
281 | omap_sdrc_init(NULL, NULL); | 268 | omap_sdrc_init(NULL, NULL); |
282 | omap_hsmmc_init(mmc); | 269 | omap_hsmmc_init(mmc); |
283 | omap2_usbfs_init(&sdp2430_usb_config); | ||
284 | 270 | ||
285 | omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); | 271 | omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP); |
286 | usb_musb_init(NULL); | 272 | usb_musb_init(NULL); |
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 502c31e123be..519bcd3079e8 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
@@ -35,7 +35,6 @@ | |||
35 | #include <asm/mach/flash.h> | 35 | #include <asm/mach/flash.h> |
36 | 36 | ||
37 | #include <plat/led.h> | 37 | #include <plat/led.h> |
38 | #include <plat/usb.h> | ||
39 | #include <plat/board.h> | 38 | #include <plat/board.h> |
40 | #include "common.h" | 39 | #include "common.h" |
41 | #include <plat/gpmc.h> | 40 | #include <plat/gpmc.h> |
@@ -253,13 +252,6 @@ out: | |||
253 | clk_put(gpmc_fck); | 252 | clk_put(gpmc_fck); |
254 | } | 253 | } |
255 | 254 | ||
256 | static struct omap_usb_config apollon_usb_config __initdata = { | ||
257 | .register_dev = 1, | ||
258 | .hmc_mode = 0x14, /* 0:dev 1:host1 2:disable */ | ||
259 | |||
260 | .pins[0] = 6, | ||
261 | }; | ||
262 | |||
263 | static struct panel_generic_dpi_data apollon_panel_data = { | 255 | static struct panel_generic_dpi_data apollon_panel_data = { |
264 | .name = "apollon", | 256 | .name = "apollon", |
265 | }; | 257 | }; |
@@ -297,15 +289,6 @@ static void __init apollon_led_init(void) | |||
297 | gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); | 289 | gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds)); |
298 | } | 290 | } |
299 | 291 | ||
300 | static void __init apollon_usb_init(void) | ||
301 | { | ||
302 | /* USB device */ | ||
303 | /* DEVICE_SUSPEND */ | ||
304 | omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0); | ||
305 | gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend"); | ||
306 | omap2_usbfs_init(&apollon_usb_config); | ||
307 | } | ||
308 | |||
309 | #ifdef CONFIG_OMAP_MUX | 292 | #ifdef CONFIG_OMAP_MUX |
310 | static struct omap_board_mux board_mux[] __initdata = { | 293 | static struct omap_board_mux board_mux[] __initdata = { |
311 | { .reg_offset = OMAP_MUX_TERMINATOR }, | 294 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
@@ -321,7 +304,6 @@ static void __init omap_apollon_init(void) | |||
321 | apollon_init_smc91x(); | 304 | apollon_init_smc91x(); |
322 | apollon_led_init(); | 305 | apollon_led_init(); |
323 | apollon_flash_init(); | 306 | apollon_flash_init(); |
324 | apollon_usb_init(); | ||
325 | 307 | ||
326 | /* REVISIT: where's the correct place */ | 308 | /* REVISIT: where's the correct place */ |
327 | omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); | 309 | omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP); |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 202934657867..2f2abfb82d84 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
@@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") | |||
112 | MACHINE_END | 112 | MACHINE_END |
113 | #endif | 113 | #endif |
114 | 114 | ||
115 | #ifdef CONFIG_SOC_AM33XX | ||
116 | static const char *am33xx_boards_compat[] __initdata = { | ||
117 | "ti,am33xx", | ||
118 | NULL, | ||
119 | }; | ||
120 | |||
121 | DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") | ||
122 | .reserve = omap_reserve, | ||
123 | .map_io = am33xx_map_io, | ||
124 | .init_early = am33xx_init_early, | ||
125 | .init_irq = omap_init_irq, | ||
126 | .handle_irq = omap3_intc_handle_irq, | ||
127 | .init_machine = omap_generic_init, | ||
128 | .timer = &omap3_am33xx_timer, | ||
129 | .dt_compat = am33xx_boards_compat, | ||
130 | MACHINE_END | ||
131 | #endif | ||
132 | |||
115 | #ifdef CONFIG_ARCH_OMAP4 | 133 | #ifdef CONFIG_ARCH_OMAP4 |
116 | static const char *omap4_boards_compat[] __initdata = { | 134 | static const char *omap4_boards_compat[] __initdata = { |
117 | "ti,omap4", | 135 | "ti,omap4", |
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 876becf8205a..ace20482e3e1 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
34 | 34 | ||
35 | #include <plat/usb.h> | ||
36 | #include <plat/board.h> | 35 | #include <plat/board.h> |
37 | #include "common.h" | 36 | #include "common.h" |
38 | #include <plat/menelaus.h> | 37 | #include <plat/menelaus.h> |
@@ -329,17 +328,6 @@ static void __init h4_init_flash(void) | |||
329 | h4_flash_resource.end = base + SZ_64M - 1; | 328 | h4_flash_resource.end = base + SZ_64M - 1; |
330 | } | 329 | } |
331 | 330 | ||
332 | static struct omap_usb_config h4_usb_config __initdata = { | ||
333 | /* S1.10 OFF -- usb "download port" | ||
334 | * usb0 switched to Mini-B port and isp1105 transceiver; | ||
335 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging | ||
336 | */ | ||
337 | .register_dev = 1, | ||
338 | .pins[0] = 3, | ||
339 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ | ||
340 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | ||
341 | }; | ||
342 | |||
343 | static struct at24_platform_data m24c01 = { | 331 | static struct at24_platform_data m24c01 = { |
344 | .byte_len = SZ_1K / 8, | 332 | .byte_len = SZ_1K / 8, |
345 | .page_size = 16, | 333 | .page_size = 16, |
@@ -381,7 +369,6 @@ static void __init omap_h4_init(void) | |||
381 | ARRAY_SIZE(h4_i2c_board_info)); | 369 | ARRAY_SIZE(h4_i2c_board_info)); |
382 | 370 | ||
383 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); | 371 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); |
384 | omap2_usbfs_init(&h4_usb_config); | ||
385 | omap_serial_init(); | 372 | omap_serial_init(); |
386 | omap_sdrc_init(NULL, NULL); | 373 | omap_sdrc_init(NULL, NULL); |
387 | h4_init_flash(); | 374 | h4_init_flash(); |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 580fd17208da..6202fc76e490 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
@@ -433,7 +433,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = { | |||
433 | 433 | ||
434 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { | 434 | static const struct usbhs_omap_board_data usbhs_bdata __initconst = { |
435 | 435 | ||
436 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, | 436 | .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, |
437 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | 437 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, |
438 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | 438 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, |
439 | 439 | ||
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index 932e1778aff9..fca93d1afd43 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c | |||
@@ -93,9 +93,6 @@ static struct twl4030_usb_data omap3logic_usb_data = { | |||
93 | 93 | ||
94 | 94 | ||
95 | static struct twl4030_platform_data omap3logic_twldata = { | 95 | static struct twl4030_platform_data omap3logic_twldata = { |
96 | .irq_base = TWL4030_IRQ_BASE, | ||
97 | .irq_end = TWL4030_IRQ_END, | ||
98 | |||
99 | /* platform_data for children goes here */ | 96 | /* platform_data for children goes here */ |
100 | .gpio = &omap3logic_gpio_data, | 97 | .gpio = &omap3logic_gpio_data, |
101 | .vmmc1 = &omap3logic_vmmc1, | 98 | .vmmc1 = &omap3logic_vmmc1, |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index 861767ed1a3a..002745181ad6 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
@@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = { | |||
1774 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), | 1774 | CLK(NULL, "osc_ck", &osc_ck, CK_242X), |
1775 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), | 1775 | CLK(NULL, "sys_ck", &sys_ck, CK_242X), |
1776 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), | 1776 | CLK(NULL, "alt_ck", &alt_ck, CK_242X), |
1777 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_242X), | ||
1778 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_242X), | ||
1779 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), | 1777 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_242X), |
1780 | /* internal analog sources */ | 1778 | /* internal analog sources */ |
1781 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), | 1779 | CLK(NULL, "dpll_ck", &dpll_ck, CK_242X), |
@@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = { | |||
1784 | /* internal prcm root sources */ | 1782 | /* internal prcm root sources */ |
1785 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), | 1783 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_242X), |
1786 | CLK(NULL, "core_ck", &core_ck, CK_242X), | 1784 | CLK(NULL, "core_ck", &core_ck, CK_242X), |
1787 | CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_242X), | ||
1788 | CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_242X), | ||
1789 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), | 1785 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_242X), |
1790 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), | 1786 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_242X), |
1791 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), | 1787 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_242X), |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 5577810dbc26..cacabb070e22 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
@@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = { | |||
1858 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), | 1858 | CLK(NULL, "osc_ck", &osc_ck, CK_243X), |
1859 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), | 1859 | CLK(NULL, "sys_ck", &sys_ck, CK_243X), |
1860 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), | 1860 | CLK(NULL, "alt_ck", &alt_ck, CK_243X), |
1861 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_243X), | ||
1862 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_243X), | ||
1863 | CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_243X), | ||
1864 | CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_243X), | ||
1865 | CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_243X), | ||
1866 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), | 1861 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_243X), |
1867 | /* internal analog sources */ | 1862 | /* internal analog sources */ |
1868 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), | 1863 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X), |
@@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = { | |||
1871 | /* internal prcm root sources */ | 1866 | /* internal prcm root sources */ |
1872 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), | 1867 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X), |
1873 | CLK(NULL, "core_ck", &core_ck, CK_243X), | 1868 | CLK(NULL, "core_ck", &core_ck, CK_243X), |
1874 | CLK("omap-mcbsp.1", "prcm_fck", &func_96m_ck, CK_243X), | ||
1875 | CLK("omap-mcbsp.2", "prcm_fck", &func_96m_ck, CK_243X), | ||
1876 | CLK("omap-mcbsp.3", "prcm_fck", &func_96m_ck, CK_243X), | ||
1877 | CLK("omap-mcbsp.4", "prcm_fck", &func_96m_ck, CK_243X), | ||
1878 | CLK("omap-mcbsp.5", "prcm_fck", &func_96m_ck, CK_243X), | ||
1879 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), | 1869 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X), |
1880 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), | 1870 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X), |
1881 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), | 1871 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X), |
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index 0d814620b69c..51f7430f6d3f 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c | |||
@@ -2490,13 +2490,13 @@ static struct clk uart4_fck = { | |||
2490 | }; | 2490 | }; |
2491 | 2491 | ||
2492 | static struct clk uart4_fck_am35xx = { | 2492 | static struct clk uart4_fck_am35xx = { |
2493 | .name = "uart4_fck", | 2493 | .name = "uart4_fck", |
2494 | .ops = &clkops_omap2_dflt_wait, | 2494 | .ops = &clkops_omap2_dflt_wait, |
2495 | .parent = &per_48m_fck, | 2495 | .parent = &core_48m_fck, |
2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2497 | .enable_bit = OMAP3430_EN_UART4_SHIFT, | 2497 | .enable_bit = AM35XX_EN_UART4_SHIFT, |
2498 | .clkdm_name = "core_l4_clkdm", | 2498 | .clkdm_name = "core_l4_clkdm", |
2499 | .recalc = &followparent_recalc, | 2499 | .recalc = &followparent_recalc, |
2500 | }; | 2500 | }; |
2501 | 2501 | ||
2502 | static struct clk gpt2_fck = { | 2502 | static struct clk gpt2_fck = { |
@@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = { | |||
3201 | }; | 3201 | }; |
3202 | 3202 | ||
3203 | /* | 3203 | /* |
3204 | * The UART1/2 functional clock acts as the functional | 3204 | * The UART1/2 functional clock acts as the functional clock for |
3205 | * clock for UART4. No separate fclk control available. | 3205 | * UART4. No separate fclk control available. XXX Well now we have a |
3206 | * uart4_fck that is apparently used as the UART4 functional clock, | ||
3207 | * but it also seems that uart1_fck or uart2_fck are still needed, at | ||
3208 | * least for UART4 softresets to complete. This really needs | ||
3209 | * clarification. | ||
3206 | */ | 3210 | */ |
3207 | static struct clk uart4_ick_am35xx = { | 3211 | static struct clk uart4_ick_am35xx = { |
3208 | .name = "uart4_ick", | 3212 | .name = "uart4_ick", |
@@ -3236,11 +3240,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3236 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), | 3240 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_3XXX), |
3237 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), | 3241 | CLK(NULL, "sys_ck", &sys_ck, CK_3XXX), |
3238 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), | 3242 | CLK(NULL, "sys_altclk", &sys_altclk, CK_3XXX), |
3239 | CLK("omap-mcbsp.1", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
3240 | CLK("omap-mcbsp.2", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
3241 | CLK("omap-mcbsp.3", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
3242 | CLK("omap-mcbsp.4", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
3243 | CLK("omap-mcbsp.5", "pad_fck", &mcbsp_clks, CK_3XXX), | ||
3244 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), | 3243 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_3XXX), |
3245 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), | 3244 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_3XXX), |
3246 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), | 3245 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_3XXX), |
@@ -3307,8 +3306,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3307 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3306 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
3308 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3307 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
3309 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3308 | CLK("usbhs_omap", "usbtll_fck", &usbtll_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
3310 | CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), | ||
3311 | CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), | ||
3312 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), | 3309 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), |
3313 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), | 3310 | CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), |
3314 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), | 3311 | CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX), |
@@ -3413,9 +3410,6 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3413 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), | 3410 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX), |
3414 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), | 3411 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_3XXX), |
3415 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), | 3412 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_3XXX), |
3416 | CLK("omap-mcbsp.2", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
3417 | CLK("omap-mcbsp.3", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
3418 | CLK("omap-mcbsp.4", "prcm_fck", &per_96m_fck, CK_3XXX), | ||
3419 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), | 3413 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_3XXX), |
3420 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), | 3414 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_3XXX), |
3421 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), | 3415 | CLK(NULL, "uart3_fck", &uart3_fck, CK_3XXX), |
@@ -3474,12 +3468,12 @@ static struct omap_clk omap3xxx_clks[] = { | |||
3474 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), | 3468 | CLK(NULL, "ipss_ick", &ipss_ick, CK_AM35XX), |
3475 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), | 3469 | CLK(NULL, "rmii_ck", &rmii_ck, CK_AM35XX), |
3476 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), | 3470 | CLK(NULL, "pclk_ck", &pclk_ck, CK_AM35XX), |
3477 | CLK("davinci_emac", NULL, &emac_ick, CK_AM35XX), | 3471 | CLK("davinci_emac.0", NULL, &emac_ick, CK_AM35XX), |
3478 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), | 3472 | CLK("davinci_mdio.0", NULL, &emac_fck, CK_AM35XX), |
3479 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), | 3473 | CLK("vpfe-capture", "master", &vpfe_ick, CK_AM35XX), |
3480 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), | 3474 | CLK("vpfe-capture", "slave", &vpfe_fck, CK_AM35XX), |
3481 | CLK("musb-am35x", "ick", &hsotgusb_ick_am35xx, CK_AM35XX), | 3475 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick_am35xx, CK_AM35XX), |
3482 | CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx, CK_AM35XX), | 3476 | CLK(NULL, "hsotgusb_fck", &hsotgusb_fck_am35xx, CK_AM35XX), |
3483 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), | 3477 | CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX), |
3484 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), | 3478 | CLK(NULL, "uart4_ick", &uart4_ick_am35xx, CK_AM35XX), |
3485 | CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), | 3479 | CLK(NULL, "timer_32k_ck", &omap_32k_fck, CK_3XXX), |
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index f7b58609bad8..5601dc13785e 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h | |||
@@ -31,12 +31,16 @@ | |||
31 | * | 31 | * |
32 | * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this | 32 | * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this |
33 | * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) | 33 | * clockdomain. (Currently, this applies to OMAP3 clockdomains only.) |
34 | * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is | ||
35 | * active whenever the MPU is active. True for interconnects and | ||
36 | * the WKUP clockdomains. | ||
34 | */ | 37 | */ |
35 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) | 38 | #define CLKDM_CAN_FORCE_SLEEP (1 << 0) |
36 | #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) | 39 | #define CLKDM_CAN_FORCE_WAKEUP (1 << 1) |
37 | #define CLKDM_CAN_ENABLE_AUTO (1 << 2) | 40 | #define CLKDM_CAN_ENABLE_AUTO (1 << 2) |
38 | #define CLKDM_CAN_DISABLE_AUTO (1 << 3) | 41 | #define CLKDM_CAN_DISABLE_AUTO (1 << 3) |
39 | #define CLKDM_NO_AUTODEPS (1 << 4) | 42 | #define CLKDM_NO_AUTODEPS (1 << 4) |
43 | #define CLKDM_ACTIVE_WITH_MPU (1 << 5) | ||
40 | 44 | ||
41 | #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) | 45 | #define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) |
42 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) | 46 | #define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) |
@@ -195,6 +199,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); | |||
195 | extern void __init omap242x_clockdomains_init(void); | 199 | extern void __init omap242x_clockdomains_init(void); |
196 | extern void __init omap243x_clockdomains_init(void); | 200 | extern void __init omap243x_clockdomains_init(void); |
197 | extern void __init omap3xxx_clockdomains_init(void); | 201 | extern void __init omap3xxx_clockdomains_init(void); |
202 | extern void __init am33xx_clockdomains_init(void); | ||
198 | extern void __init omap44xx_clockdomains_init(void); | 203 | extern void __init omap44xx_clockdomains_init(void); |
199 | extern void _clkdm_add_autodeps(struct clockdomain *clkdm); | 204 | extern void _clkdm_add_autodeps(struct clockdomain *clkdm); |
200 | extern void _clkdm_del_autodeps(struct clockdomain *clkdm); | 205 | extern void _clkdm_del_autodeps(struct clockdomain *clkdm); |
@@ -202,11 +207,10 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm); | |||
202 | extern struct clkdm_ops omap2_clkdm_operations; | 207 | extern struct clkdm_ops omap2_clkdm_operations; |
203 | extern struct clkdm_ops omap3_clkdm_operations; | 208 | extern struct clkdm_ops omap3_clkdm_operations; |
204 | extern struct clkdm_ops omap4_clkdm_operations; | 209 | extern struct clkdm_ops omap4_clkdm_operations; |
210 | extern struct clkdm_ops am33xx_clkdm_operations; | ||
205 | 211 | ||
206 | extern struct clkdm_dep gfx_24xx_wkdeps[]; | 212 | extern struct clkdm_dep gfx_24xx_wkdeps[]; |
207 | extern struct clkdm_dep dsp_24xx_wkdeps[]; | 213 | extern struct clkdm_dep dsp_24xx_wkdeps[]; |
208 | extern struct clockdomain wkup_common_clkdm; | 214 | extern struct clockdomain wkup_common_clkdm; |
209 | extern struct clockdomain prm_common_clkdm; | ||
210 | extern struct clockdomain cm_common_clkdm; | ||
211 | 215 | ||
212 | #endif | 216 | #endif |
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c new file mode 100644 index 000000000000..aca6388fad76 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain33xx.c | |||
@@ -0,0 +1,74 @@ | |||
1 | /* | ||
2 | * AM33XX clockdomain control | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
6 | * | ||
7 | * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License as | ||
11 | * published by the Free Software Foundation version 2. | ||
12 | * | ||
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
14 | * kind, whether express or implied; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | */ | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | |||
21 | #include "clockdomain.h" | ||
22 | #include "cm33xx.h" | ||
23 | |||
24 | |||
25 | static int am33xx_clkdm_sleep(struct clockdomain *clkdm) | ||
26 | { | ||
27 | am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); | ||
28 | return 0; | ||
29 | } | ||
30 | |||
31 | static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) | ||
32 | { | ||
33 | am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
34 | return 0; | ||
35 | } | ||
36 | |||
37 | static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) | ||
38 | { | ||
39 | am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
40 | } | ||
41 | |||
42 | static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) | ||
43 | { | ||
44 | am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
45 | } | ||
46 | |||
47 | static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) | ||
48 | { | ||
49 | if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) | ||
50 | return am33xx_clkdm_wakeup(clkdm); | ||
51 | |||
52 | return 0; | ||
53 | } | ||
54 | |||
55 | static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) | ||
56 | { | ||
57 | bool hwsup = false; | ||
58 | |||
59 | hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); | ||
60 | |||
61 | if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) | ||
62 | am33xx_clkdm_sleep(clkdm); | ||
63 | |||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | struct clkdm_ops am33xx_clkdm_operations = { | ||
68 | .clkdm_sleep = am33xx_clkdm_sleep, | ||
69 | .clkdm_wakeup = am33xx_clkdm_wakeup, | ||
70 | .clkdm_allow_idle = am33xx_clkdm_allow_idle, | ||
71 | .clkdm_deny_idle = am33xx_clkdm_deny_idle, | ||
72 | .clkdm_clk_enable = am33xx_clkdm_clk_enable, | ||
73 | .clkdm_clk_disable = am33xx_clkdm_clk_disable, | ||
74 | }; | ||
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c index 0ab8e46d5b2b..5c741852fac0 100644 --- a/arch/arm/mach-omap2/clockdomains2420_data.c +++ b/arch/arm/mach-omap2/clockdomains2420_data.c | |||
@@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = { | |||
131 | 131 | ||
132 | static struct clockdomain *clockdomains_omap242x[] __initdata = { | 132 | static struct clockdomain *clockdomains_omap242x[] __initdata = { |
133 | &wkup_common_clkdm, | 133 | &wkup_common_clkdm, |
134 | &cm_common_clkdm, | ||
135 | &prm_common_clkdm, | ||
136 | &mpu_2420_clkdm, | 134 | &mpu_2420_clkdm, |
137 | &iva1_2420_clkdm, | 135 | &iva1_2420_clkdm, |
138 | &dsp_2420_clkdm, | 136 | &dsp_2420_clkdm, |
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c index 3645ed044890..f09617555e15 100644 --- a/arch/arm/mach-omap2/clockdomains2430_data.c +++ b/arch/arm/mach-omap2/clockdomains2430_data.c | |||
@@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = { | |||
157 | 157 | ||
158 | static struct clockdomain *clockdomains_omap243x[] __initdata = { | 158 | static struct clockdomain *clockdomains_omap243x[] __initdata = { |
159 | &wkup_common_clkdm, | 159 | &wkup_common_clkdm, |
160 | &cm_common_clkdm, | ||
161 | &prm_common_clkdm, | ||
162 | &mpu_2430_clkdm, | 160 | &mpu_2430_clkdm, |
163 | &mdm_clkdm, | 161 | &mdm_clkdm, |
164 | &dsp_2430_clkdm, | 162 | &dsp_2430_clkdm, |
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 839145e1cfbe..4972219653ce 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | |||
@@ -88,4 +88,5 @@ struct clockdomain wkup_common_clkdm = { | |||
88 | .name = "wkup_clkdm", | 88 | .name = "wkup_clkdm", |
89 | .pwrdm = { .name = "wkup_pwrdm" }, | 89 | .pwrdm = { .name = "wkup_pwrdm" }, |
90 | .dep_bit = OMAP_EN_WKUP_SHIFT, | 90 | .dep_bit = OMAP_EN_WKUP_SHIFT, |
91 | .flags = CLKDM_ACTIVE_WITH_MPU, | ||
91 | }; | 92 | }; |
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c new file mode 100644 index 000000000000..32c90fd9eba2 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains33xx_data.c | |||
@@ -0,0 +1,196 @@ | |||
1 | /* | ||
2 | * AM33XX Clock Domain data. | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include "clockdomain.h" | ||
21 | #include "cm.h" | ||
22 | #include "cm33xx.h" | ||
23 | #include "cm-regbits-33xx.h" | ||
24 | |||
25 | static struct clockdomain l4ls_am33xx_clkdm = { | ||
26 | .name = "l4ls_clkdm", | ||
27 | .pwrdm = { .name = "per_pwrdm" }, | ||
28 | .cm_inst = AM33XX_CM_PER_MOD, | ||
29 | .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, | ||
30 | .flags = CLKDM_CAN_SWSUP, | ||
31 | }; | ||
32 | |||
33 | static struct clockdomain l3s_am33xx_clkdm = { | ||
34 | .name = "l3s_clkdm", | ||
35 | .pwrdm = { .name = "per_pwrdm" }, | ||
36 | .cm_inst = AM33XX_CM_PER_MOD, | ||
37 | .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, | ||
38 | .flags = CLKDM_CAN_SWSUP, | ||
39 | }; | ||
40 | |||
41 | static struct clockdomain l4fw_am33xx_clkdm = { | ||
42 | .name = "l4fw_clkdm", | ||
43 | .pwrdm = { .name = "per_pwrdm" }, | ||
44 | .cm_inst = AM33XX_CM_PER_MOD, | ||
45 | .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, | ||
46 | .flags = CLKDM_CAN_SWSUP, | ||
47 | }; | ||
48 | |||
49 | static struct clockdomain l3_am33xx_clkdm = { | ||
50 | .name = "l3_clkdm", | ||
51 | .pwrdm = { .name = "per_pwrdm" }, | ||
52 | .cm_inst = AM33XX_CM_PER_MOD, | ||
53 | .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, | ||
54 | .flags = CLKDM_CAN_SWSUP, | ||
55 | }; | ||
56 | |||
57 | static struct clockdomain l4hs_am33xx_clkdm = { | ||
58 | .name = "l4hs_clkdm", | ||
59 | .pwrdm = { .name = "per_pwrdm" }, | ||
60 | .cm_inst = AM33XX_CM_PER_MOD, | ||
61 | .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, | ||
62 | .flags = CLKDM_CAN_SWSUP, | ||
63 | }; | ||
64 | |||
65 | static struct clockdomain ocpwp_l3_am33xx_clkdm = { | ||
66 | .name = "ocpwp_l3_clkdm", | ||
67 | .pwrdm = { .name = "per_pwrdm" }, | ||
68 | .cm_inst = AM33XX_CM_PER_MOD, | ||
69 | .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, | ||
70 | .flags = CLKDM_CAN_SWSUP, | ||
71 | }; | ||
72 | |||
73 | static struct clockdomain pruss_ocp_am33xx_clkdm = { | ||
74 | .name = "pruss_ocp_clkdm", | ||
75 | .pwrdm = { .name = "per_pwrdm" }, | ||
76 | .cm_inst = AM33XX_CM_PER_MOD, | ||
77 | .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, | ||
78 | .flags = CLKDM_CAN_SWSUP, | ||
79 | }; | ||
80 | |||
81 | static struct clockdomain cpsw_125mhz_am33xx_clkdm = { | ||
82 | .name = "cpsw_125mhz_clkdm", | ||
83 | .pwrdm = { .name = "per_pwrdm" }, | ||
84 | .cm_inst = AM33XX_CM_PER_MOD, | ||
85 | .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, | ||
86 | .flags = CLKDM_CAN_SWSUP, | ||
87 | }; | ||
88 | |||
89 | static struct clockdomain lcdc_am33xx_clkdm = { | ||
90 | .name = "lcdc_clkdm", | ||
91 | .pwrdm = { .name = "per_pwrdm" }, | ||
92 | .cm_inst = AM33XX_CM_PER_MOD, | ||
93 | .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, | ||
94 | .flags = CLKDM_CAN_SWSUP, | ||
95 | }; | ||
96 | |||
97 | static struct clockdomain clk_24mhz_am33xx_clkdm = { | ||
98 | .name = "clk_24mhz_clkdm", | ||
99 | .pwrdm = { .name = "per_pwrdm" }, | ||
100 | .cm_inst = AM33XX_CM_PER_MOD, | ||
101 | .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, | ||
102 | .flags = CLKDM_CAN_SWSUP, | ||
103 | }; | ||
104 | |||
105 | static struct clockdomain l4_wkup_am33xx_clkdm = { | ||
106 | .name = "l4_wkup_clkdm", | ||
107 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
108 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
109 | .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, | ||
110 | .flags = CLKDM_CAN_SWSUP, | ||
111 | }; | ||
112 | |||
113 | static struct clockdomain l3_aon_am33xx_clkdm = { | ||
114 | .name = "l3_aon_clkdm", | ||
115 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
116 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
117 | .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, | ||
118 | .flags = CLKDM_CAN_SWSUP, | ||
119 | }; | ||
120 | |||
121 | static struct clockdomain l4_wkup_aon_am33xx_clkdm = { | ||
122 | .name = "l4_wkup_aon_clkdm", | ||
123 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
124 | .cm_inst = AM33XX_CM_WKUP_MOD, | ||
125 | .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, | ||
126 | .flags = CLKDM_CAN_SWSUP, | ||
127 | }; | ||
128 | |||
129 | static struct clockdomain mpu_am33xx_clkdm = { | ||
130 | .name = "mpu_clkdm", | ||
131 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
132 | .cm_inst = AM33XX_CM_MPU_MOD, | ||
133 | .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, | ||
134 | .flags = CLKDM_CAN_SWSUP, | ||
135 | }; | ||
136 | |||
137 | static struct clockdomain l4_rtc_am33xx_clkdm = { | ||
138 | .name = "l4_rtc_clkdm", | ||
139 | .pwrdm = { .name = "rtc_pwrdm" }, | ||
140 | .cm_inst = AM33XX_CM_RTC_MOD, | ||
141 | .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, | ||
142 | .flags = CLKDM_CAN_SWSUP, | ||
143 | }; | ||
144 | |||
145 | static struct clockdomain gfx_l3_am33xx_clkdm = { | ||
146 | .name = "gfx_l3_clkdm", | ||
147 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
148 | .cm_inst = AM33XX_CM_GFX_MOD, | ||
149 | .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, | ||
150 | .flags = CLKDM_CAN_SWSUP, | ||
151 | }; | ||
152 | |||
153 | static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { | ||
154 | .name = "gfx_l4ls_gfx_clkdm", | ||
155 | .pwrdm = { .name = "gfx_pwrdm" }, | ||
156 | .cm_inst = AM33XX_CM_GFX_MOD, | ||
157 | .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, | ||
158 | .flags = CLKDM_CAN_SWSUP, | ||
159 | }; | ||
160 | |||
161 | static struct clockdomain l4_cefuse_am33xx_clkdm = { | ||
162 | .name = "l4_cefuse_clkdm", | ||
163 | .pwrdm = { .name = "cefuse_pwrdm" }, | ||
164 | .cm_inst = AM33XX_CM_CEFUSE_MOD, | ||
165 | .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, | ||
166 | .flags = CLKDM_CAN_SWSUP, | ||
167 | }; | ||
168 | |||
169 | static struct clockdomain *clockdomains_am33xx[] __initdata = { | ||
170 | &l4ls_am33xx_clkdm, | ||
171 | &l3s_am33xx_clkdm, | ||
172 | &l4fw_am33xx_clkdm, | ||
173 | &l3_am33xx_clkdm, | ||
174 | &l4hs_am33xx_clkdm, | ||
175 | &ocpwp_l3_am33xx_clkdm, | ||
176 | &pruss_ocp_am33xx_clkdm, | ||
177 | &cpsw_125mhz_am33xx_clkdm, | ||
178 | &lcdc_am33xx_clkdm, | ||
179 | &clk_24mhz_am33xx_clkdm, | ||
180 | &l4_wkup_am33xx_clkdm, | ||
181 | &l3_aon_am33xx_clkdm, | ||
182 | &l4_wkup_aon_am33xx_clkdm, | ||
183 | &mpu_am33xx_clkdm, | ||
184 | &l4_rtc_am33xx_clkdm, | ||
185 | &gfx_l3_am33xx_clkdm, | ||
186 | &gfx_l4ls_gfx_am33xx_clkdm, | ||
187 | &l4_cefuse_am33xx_clkdm, | ||
188 | NULL, | ||
189 | }; | ||
190 | |||
191 | void __init am33xx_clockdomains_init(void) | ||
192 | { | ||
193 | clkdm_register_platform_funcs(&am33xx_clkdm_operations); | ||
194 | clkdm_register_clkdms(clockdomains_am33xx); | ||
195 | clkdm_complete_init(); | ||
196 | } | ||
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c index 6038adb97710..56089c49142a 100644 --- a/arch/arm/mach-omap2/clockdomains3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c | |||
@@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = { | |||
59 | { NULL }, | 59 | { NULL }, |
60 | }; | 60 | }; |
61 | 61 | ||
62 | static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = { | ||
63 | { .clkdm_name = "mpu_clkdm" }, | ||
64 | { .clkdm_name = "wkup_clkdm" }, | ||
65 | { NULL }, | ||
66 | }; | ||
67 | |||
62 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ | 68 | /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */ |
63 | static struct clkdm_dep per_wkdeps[] = { | 69 | static struct clkdm_dep per_wkdeps[] = { |
64 | { .clkdm_name = "core_l3_clkdm" }, | 70 | { .clkdm_name = "core_l3_clkdm" }, |
@@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = { | |||
69 | { NULL }, | 75 | { NULL }, |
70 | }; | 76 | }; |
71 | 77 | ||
78 | static struct clkdm_dep per_am35x_wkdeps[] = { | ||
79 | { .clkdm_name = "core_l3_clkdm" }, | ||
80 | { .clkdm_name = "core_l4_clkdm" }, | ||
81 | { .clkdm_name = "mpu_clkdm" }, | ||
82 | { .clkdm_name = "wkup_clkdm" }, | ||
83 | { NULL }, | ||
84 | }; | ||
85 | |||
72 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ | 86 | /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */ |
73 | static struct clkdm_dep usbhost_wkdeps[] = { | 87 | static struct clkdm_dep usbhost_wkdeps[] = { |
74 | { .clkdm_name = "core_l3_clkdm" }, | 88 | { .clkdm_name = "core_l3_clkdm" }, |
@@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = { | |||
79 | { NULL }, | 93 | { NULL }, |
80 | }; | 94 | }; |
81 | 95 | ||
96 | static struct clkdm_dep usbhost_am35x_wkdeps[] = { | ||
97 | { .clkdm_name = "core_l3_clkdm" }, | ||
98 | { .clkdm_name = "core_l4_clkdm" }, | ||
99 | { .clkdm_name = "mpu_clkdm" }, | ||
100 | { .clkdm_name = "wkup_clkdm" }, | ||
101 | { NULL }, | ||
102 | }; | ||
103 | |||
82 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ | 104 | /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */ |
83 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { | 105 | static struct clkdm_dep mpu_3xxx_wkdeps[] = { |
84 | { .clkdm_name = "core_l3_clkdm" }, | 106 | { .clkdm_name = "core_l3_clkdm" }, |
@@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = { | |||
89 | { NULL }, | 111 | { NULL }, |
90 | }; | 112 | }; |
91 | 113 | ||
114 | static struct clkdm_dep mpu_am35x_wkdeps[] = { | ||
115 | { .clkdm_name = "core_l3_clkdm" }, | ||
116 | { .clkdm_name = "core_l4_clkdm" }, | ||
117 | { .clkdm_name = "dss_clkdm" }, | ||
118 | { .clkdm_name = "per_clkdm" }, | ||
119 | { NULL }, | ||
120 | }; | ||
121 | |||
92 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ | 122 | /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */ |
93 | static struct clkdm_dep iva2_wkdeps[] = { | 123 | static struct clkdm_dep iva2_wkdeps[] = { |
94 | { .clkdm_name = "core_l3_clkdm" }, | 124 | { .clkdm_name = "core_l3_clkdm" }, |
@@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = { | |||
116 | { NULL }, | 146 | { NULL }, |
117 | }; | 147 | }; |
118 | 148 | ||
149 | static struct clkdm_dep dss_am35x_wkdeps[] = { | ||
150 | { .clkdm_name = "mpu_clkdm" }, | ||
151 | { .clkdm_name = "wkup_clkdm" }, | ||
152 | { NULL }, | ||
153 | }; | ||
154 | |||
119 | /* 3430: PM_WKDEP_NEON: MPU */ | 155 | /* 3430: PM_WKDEP_NEON: MPU */ |
120 | static struct clkdm_dep neon_wkdeps[] = { | 156 | static struct clkdm_dep neon_wkdeps[] = { |
121 | { .clkdm_name = "mpu_clkdm" }, | 157 | { .clkdm_name = "mpu_clkdm" }, |
@@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = { | |||
131 | { NULL }, | 167 | { NULL }, |
132 | }; | 168 | }; |
133 | 169 | ||
170 | static struct clkdm_dep dss_am35x_sleepdeps[] = { | ||
171 | { .clkdm_name = "mpu_clkdm" }, | ||
172 | { NULL }, | ||
173 | }; | ||
174 | |||
134 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ | 175 | /* 3430: CM_SLEEPDEP_PER: MPU, IVA */ |
135 | static struct clkdm_dep per_sleepdeps[] = { | 176 | static struct clkdm_dep per_sleepdeps[] = { |
136 | { .clkdm_name = "mpu_clkdm" }, | 177 | { .clkdm_name = "mpu_clkdm" }, |
@@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = { | |||
138 | { NULL }, | 179 | { NULL }, |
139 | }; | 180 | }; |
140 | 181 | ||
182 | static struct clkdm_dep per_am35x_sleepdeps[] = { | ||
183 | { .clkdm_name = "mpu_clkdm" }, | ||
184 | { NULL }, | ||
185 | }; | ||
186 | |||
141 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ | 187 | /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */ |
142 | static struct clkdm_dep usbhost_sleepdeps[] = { | 188 | static struct clkdm_dep usbhost_sleepdeps[] = { |
143 | { .clkdm_name = "mpu_clkdm" }, | 189 | { .clkdm_name = "mpu_clkdm" }, |
@@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = { | |||
145 | { NULL }, | 191 | { NULL }, |
146 | }; | 192 | }; |
147 | 193 | ||
194 | static struct clkdm_dep usbhost_am35x_sleepdeps[] = { | ||
195 | { .clkdm_name = "mpu_clkdm" }, | ||
196 | { NULL }, | ||
197 | }; | ||
198 | |||
148 | /* 3430: CM_SLEEPDEP_CAM: MPU */ | 199 | /* 3430: CM_SLEEPDEP_CAM: MPU */ |
149 | static struct clkdm_dep cam_sleepdeps[] = { | 200 | static struct clkdm_dep cam_sleepdeps[] = { |
150 | { .clkdm_name = "mpu_clkdm" }, | 201 | { .clkdm_name = "mpu_clkdm" }, |
@@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = { | |||
175 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 226 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
176 | }; | 227 | }; |
177 | 228 | ||
229 | static struct clockdomain mpu_am35x_clkdm = { | ||
230 | .name = "mpu_clkdm", | ||
231 | .pwrdm = { .name = "mpu_pwrdm" }, | ||
232 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | ||
233 | .dep_bit = OMAP3430_EN_MPU_SHIFT, | ||
234 | .wkdep_srcs = mpu_am35x_wkdeps, | ||
235 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | ||
236 | }; | ||
237 | |||
178 | static struct clockdomain neon_clkdm = { | 238 | static struct clockdomain neon_clkdm = { |
179 | .name = "neon_clkdm", | 239 | .name = "neon_clkdm", |
180 | .pwrdm = { .name = "neon_pwrdm" }, | 240 | .pwrdm = { .name = "neon_pwrdm" }, |
@@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = { | |||
210 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 270 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
211 | }; | 271 | }; |
212 | 272 | ||
273 | static struct clockdomain sgx_am35x_clkdm = { | ||
274 | .name = "sgx_clkdm", | ||
275 | .pwrdm = { .name = "sgx_pwrdm" }, | ||
276 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
277 | .wkdep_srcs = gfx_sgx_am35x_wkdeps, | ||
278 | .sleepdep_srcs = gfx_sgx_sleepdeps, | ||
279 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | ||
280 | }; | ||
281 | |||
213 | /* | 282 | /* |
214 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but | 283 | * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but |
215 | * then that information was removed from the 34xx ES2+ TRM. It is | 284 | * then that information was removed from the 34xx ES2+ TRM. It is |
@@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = { | |||
261 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 330 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
262 | }; | 331 | }; |
263 | 332 | ||
333 | static struct clockdomain dss_am35x_clkdm = { | ||
334 | .name = "dss_clkdm", | ||
335 | .pwrdm = { .name = "dss_pwrdm" }, | ||
336 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
337 | .dep_bit = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT, | ||
338 | .wkdep_srcs = dss_am35x_wkdeps, | ||
339 | .sleepdep_srcs = dss_am35x_sleepdeps, | ||
340 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | ||
341 | }; | ||
342 | |||
264 | static struct clockdomain cam_clkdm = { | 343 | static struct clockdomain cam_clkdm = { |
265 | .name = "cam_clkdm", | 344 | .name = "cam_clkdm", |
266 | .pwrdm = { .name = "cam_pwrdm" }, | 345 | .pwrdm = { .name = "cam_pwrdm" }, |
@@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = { | |||
279 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 358 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
280 | }; | 359 | }; |
281 | 360 | ||
361 | static struct clockdomain usbhost_am35x_clkdm = { | ||
362 | .name = "usbhost_clkdm", | ||
363 | .pwrdm = { .name = "core_pwrdm" }, | ||
364 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
365 | .wkdep_srcs = usbhost_am35x_wkdeps, | ||
366 | .sleepdep_srcs = usbhost_am35x_sleepdeps, | ||
367 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | ||
368 | }; | ||
369 | |||
282 | static struct clockdomain per_clkdm = { | 370 | static struct clockdomain per_clkdm = { |
283 | .name = "per_clkdm", | 371 | .name = "per_clkdm", |
284 | .pwrdm = { .name = "per_pwrdm" }, | 372 | .pwrdm = { .name = "per_pwrdm" }, |
@@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = { | |||
289 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 377 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
290 | }; | 378 | }; |
291 | 379 | ||
380 | static struct clockdomain per_am35x_clkdm = { | ||
381 | .name = "per_clkdm", | ||
382 | .pwrdm = { .name = "per_pwrdm" }, | ||
383 | .flags = CLKDM_CAN_HWSUP_SWSUP, | ||
384 | .dep_bit = OMAP3430_EN_PER_SHIFT, | ||
385 | .wkdep_srcs = per_am35x_wkdeps, | ||
386 | .sleepdep_srcs = per_am35x_sleepdeps, | ||
387 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | ||
388 | }; | ||
389 | |||
292 | /* | 390 | /* |
293 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | 391 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is |
294 | * switched of even if sdti is in use | 392 | * switched of even if sdti is in use |
@@ -341,31 +439,42 @@ static struct clkdm_autodep clkdm_autodeps[] = { | |||
341 | } | 439 | } |
342 | }; | 440 | }; |
343 | 441 | ||
442 | static struct clkdm_autodep clkdm_am35x_autodeps[] = { | ||
443 | { | ||
444 | .clkdm = { .name = "mpu_clkdm" }, | ||
445 | }, | ||
446 | { | ||
447 | .clkdm = { .name = NULL }, | ||
448 | } | ||
449 | }; | ||
450 | |||
344 | /* | 451 | /* |
345 | * | 452 | * |
346 | */ | 453 | */ |
347 | 454 | ||
348 | static struct clockdomain *clockdomains_omap3430_common[] __initdata = { | 455 | static struct clockdomain *clockdomains_common[] __initdata = { |
349 | &wkup_common_clkdm, | 456 | &wkup_common_clkdm, |
350 | &cm_common_clkdm, | ||
351 | &prm_common_clkdm, | ||
352 | &mpu_3xxx_clkdm, | ||
353 | &neon_clkdm, | 457 | &neon_clkdm, |
354 | &iva2_clkdm, | ||
355 | &d2d_clkdm, | ||
356 | &core_l3_3xxx_clkdm, | 458 | &core_l3_3xxx_clkdm, |
357 | &core_l4_3xxx_clkdm, | 459 | &core_l4_3xxx_clkdm, |
358 | &dss_3xxx_clkdm, | ||
359 | &cam_clkdm, | ||
360 | &per_clkdm, | ||
361 | &emu_clkdm, | 460 | &emu_clkdm, |
362 | &dpll1_clkdm, | 461 | &dpll1_clkdm, |
363 | &dpll2_clkdm, | ||
364 | &dpll3_clkdm, | 462 | &dpll3_clkdm, |
365 | &dpll4_clkdm, | 463 | &dpll4_clkdm, |
366 | NULL | 464 | NULL |
367 | }; | 465 | }; |
368 | 466 | ||
467 | static struct clockdomain *clockdomains_omap3430[] __initdata = { | ||
468 | &mpu_3xxx_clkdm, | ||
469 | &iva2_clkdm, | ||
470 | &d2d_clkdm, | ||
471 | &dss_3xxx_clkdm, | ||
472 | &cam_clkdm, | ||
473 | &per_clkdm, | ||
474 | &dpll2_clkdm, | ||
475 | NULL | ||
476 | }; | ||
477 | |||
369 | static struct clockdomain *clockdomains_omap3430es1[] __initdata = { | 478 | static struct clockdomain *clockdomains_omap3430es1[] __initdata = { |
370 | &gfx_3430es1_clkdm, | 479 | &gfx_3430es1_clkdm, |
371 | NULL, | 480 | NULL, |
@@ -378,21 +487,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = { | |||
378 | NULL, | 487 | NULL, |
379 | }; | 488 | }; |
380 | 489 | ||
490 | static struct clockdomain *clockdomains_am35x[] __initdata = { | ||
491 | &mpu_am35x_clkdm, | ||
492 | &sgx_am35x_clkdm, | ||
493 | &dss_am35x_clkdm, | ||
494 | &per_am35x_clkdm, | ||
495 | &usbhost_am35x_clkdm, | ||
496 | &dpll5_clkdm, | ||
497 | NULL | ||
498 | }; | ||
499 | |||
381 | void __init omap3xxx_clockdomains_init(void) | 500 | void __init omap3xxx_clockdomains_init(void) |
382 | { | 501 | { |
383 | struct clockdomain **sc; | 502 | struct clockdomain **sc; |
503 | unsigned int rev; | ||
384 | 504 | ||
385 | if (!cpu_is_omap34xx()) | 505 | if (!cpu_is_omap34xx()) |
386 | return; | 506 | return; |
387 | 507 | ||
388 | clkdm_register_platform_funcs(&omap3_clkdm_operations); | 508 | clkdm_register_platform_funcs(&omap3_clkdm_operations); |
389 | clkdm_register_clkdms(clockdomains_omap3430_common); | 509 | clkdm_register_clkdms(clockdomains_common); |
390 | 510 | ||
391 | sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 : | 511 | rev = omap_rev(); |
392 | clockdomains_omap3430es2plus; | ||
393 | 512 | ||
394 | clkdm_register_clkdms(sc); | 513 | if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
514 | clkdm_register_clkdms(clockdomains_am35x); | ||
515 | clkdm_register_autodeps(clkdm_am35x_autodeps); | ||
516 | } else { | ||
517 | clkdm_register_clkdms(clockdomains_omap3430); | ||
518 | |||
519 | sc = (rev == OMAP3430_REV_ES1_0) ? | ||
520 | clockdomains_omap3430es1 : clockdomains_omap3430es2plus; | ||
521 | |||
522 | clkdm_register_clkdms(sc); | ||
523 | clkdm_register_autodeps(clkdm_autodeps); | ||
524 | } | ||
395 | 525 | ||
396 | clkdm_register_autodeps(clkdm_autodeps); | ||
397 | clkdm_complete_init(); | 526 | clkdm_complete_init(); |
398 | } | 527 | } |
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index c53425847493..63d60a773d3b 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c | |||
@@ -381,7 +381,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = { | |||
381 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, | 381 | .cm_inst = OMAP4430_PRM_WKUP_CM_INST, |
382 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, | 382 | .clkdm_offs = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS, |
383 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, | 383 | .dep_bit = OMAP4430_L4WKUP_STATDEP_SHIFT, |
384 | .flags = CLKDM_CAN_HWSUP, | 384 | .flags = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU, |
385 | }; | 385 | }; |
386 | 386 | ||
387 | static struct clockdomain emu_sys_44xx_clkdm = { | 387 | static struct clockdomain emu_sys_44xx_clkdm = { |
@@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = { | |||
430 | &l4_wkup_44xx_clkdm, | 430 | &l4_wkup_44xx_clkdm, |
431 | &emu_sys_44xx_clkdm, | 431 | &emu_sys_44xx_clkdm, |
432 | &l3_dma_44xx_clkdm, | 432 | &l3_dma_44xx_clkdm, |
433 | &prm_common_clkdm, | ||
434 | &cm_common_clkdm, | ||
435 | NULL | 433 | NULL |
436 | }; | 434 | }; |
437 | 435 | ||
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c deleted file mode 100644 index 615b1f04967d..000000000000 --- a/arch/arm/mach-omap2/clockdomains_common_data.c +++ /dev/null | |||
@@ -1,24 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP2+-common clockdomain data | ||
3 | * | ||
4 | * Copyright (C) 2008-2012 Texas Instruments, Inc. | ||
5 | * Copyright (C) 2008-2010 Nokia Corporation | ||
6 | * | ||
7 | * Paul Walmsley, Jouni Högander | ||
8 | */ | ||
9 | |||
10 | #include <linux/kernel.h> | ||
11 | #include <linux/io.h> | ||
12 | |||
13 | #include "clockdomain.h" | ||
14 | |||
15 | /* These are implicit clockdomains - they are never defined as such in TRM */ | ||
16 | struct clockdomain prm_common_clkdm = { | ||
17 | .name = "prm_clkdm", | ||
18 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
19 | }; | ||
20 | |||
21 | struct clockdomain cm_common_clkdm = { | ||
22 | .name = "cm_clkdm", | ||
23 | .pwrdm = { .name = "core_pwrdm" }, | ||
24 | }; | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h new file mode 100644 index 000000000000..532027ee3d8d --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h | |||
@@ -0,0 +1,687 @@ | |||
1 | /* | ||
2 | * AM33XX Power Management register bits | ||
3 | * | ||
4 | * This file is automatically generated from the AM33XX hardware databases. | ||
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
6 | * | ||
7 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License as | ||
11 | * published by the Free Software Foundation version 2. | ||
12 | * | ||
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
14 | * kind, whether express or implied; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | */ | ||
18 | |||
19 | |||
20 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | ||
21 | #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H | ||
22 | |||
23 | /* | ||
24 | * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, | ||
25 | * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER | ||
26 | */ | ||
27 | #define AM33XX_AUTO_DPLL_MODE_SHIFT 0 | ||
28 | #define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) | ||
29 | |||
30 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
31 | #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 | ||
32 | #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) | ||
33 | |||
34 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
35 | #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 | ||
36 | #define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) | ||
37 | |||
38 | /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ | ||
39 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 | ||
40 | #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) | ||
41 | |||
42 | /* Used by CM_PER_CPSW_CLKSTCTRL */ | ||
43 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 | ||
44 | #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) | ||
45 | |||
46 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
47 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 | ||
48 | #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) | ||
49 | |||
50 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
51 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 | ||
52 | #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) | ||
53 | |||
54 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
55 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 | ||
56 | #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) | ||
57 | |||
58 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
59 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 | ||
60 | #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) | ||
61 | |||
62 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
63 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 | ||
64 | #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) | ||
65 | |||
66 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
67 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 | ||
68 | #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) | ||
69 | |||
70 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
71 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 | ||
72 | #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) | ||
73 | |||
74 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
75 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 | ||
76 | #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) | ||
77 | |||
78 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
79 | #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 | ||
80 | #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) | ||
81 | |||
82 | /* Used by CM_GFX_L3_CLKSTCTRL */ | ||
83 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 | ||
84 | #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) | ||
85 | |||
86 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
87 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 | ||
88 | #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) | ||
89 | |||
90 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
91 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 | ||
92 | #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) | ||
93 | |||
94 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
95 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 | ||
96 | #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) | ||
97 | |||
98 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
99 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 | ||
100 | #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) | ||
101 | |||
102 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
103 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 | ||
104 | #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) | ||
105 | |||
106 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
107 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 | ||
108 | #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) | ||
109 | |||
110 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
111 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 | ||
112 | #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) | ||
113 | |||
114 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
115 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 | ||
116 | #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) | ||
117 | |||
118 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
119 | #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 | ||
120 | #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) | ||
121 | |||
122 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
123 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 | ||
124 | #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) | ||
125 | |||
126 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
127 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 | ||
128 | #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) | ||
129 | |||
130 | /* Used by CM_PER_PRUSS_CLKSTCTRL */ | ||
131 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 | ||
132 | #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) | ||
133 | |||
134 | /* Used by CM_PER_L3S_CLKSTCTRL */ | ||
135 | #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 | ||
136 | #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) | ||
137 | |||
138 | /* Used by CM_L3_AON_CLKSTCTRL */ | ||
139 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 | ||
140 | #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) | ||
141 | |||
142 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
143 | #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 | ||
144 | #define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) | ||
145 | |||
146 | /* Used by CM_PER_L4FW_CLKSTCTRL */ | ||
147 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 | ||
148 | #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) | ||
149 | |||
150 | /* Used by CM_PER_L4HS_CLKSTCTRL */ | ||
151 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 | ||
152 | #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) | ||
153 | |||
154 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
155 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 | ||
156 | #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) | ||
157 | |||
158 | /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ | ||
159 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 | ||
160 | #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) | ||
161 | |||
162 | /* Used by CM_CEFUSE_CLKSTCTRL */ | ||
163 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 | ||
164 | #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) | ||
165 | |||
166 | /* Used by CM_RTC_CLKSTCTRL */ | ||
167 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 | ||
168 | #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) | ||
169 | |||
170 | /* Used by CM_L4_WKUP_AON_CLKSTCTRL */ | ||
171 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 | ||
172 | #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) | ||
173 | |||
174 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
175 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 | ||
176 | #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) | ||
177 | |||
178 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
179 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 | ||
180 | #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) | ||
181 | |||
182 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
183 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 | ||
184 | #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) | ||
185 | |||
186 | /* Used by CM_PER_LCDC_CLKSTCTRL */ | ||
187 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 | ||
188 | #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) | ||
189 | |||
190 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
191 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 | ||
192 | #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) | ||
193 | |||
194 | /* Used by CM_PER_L3_CLKSTCTRL */ | ||
195 | #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 | ||
196 | #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) | ||
197 | |||
198 | /* Used by CM_MPU_CLKSTCTRL */ | ||
199 | #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 | ||
200 | #define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) | ||
201 | |||
202 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
203 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 | ||
204 | #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) | ||
205 | |||
206 | /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ | ||
207 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 | ||
208 | #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) | ||
209 | |||
210 | /* Used by CM_RTC_CLKSTCTRL */ | ||
211 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 | ||
212 | #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) | ||
213 | |||
214 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
215 | #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 | ||
216 | #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) | ||
217 | |||
218 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
219 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 | ||
220 | #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) | ||
221 | |||
222 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
223 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 | ||
224 | #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) | ||
225 | |||
226 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
227 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 | ||
228 | #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) | ||
229 | |||
230 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
231 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 | ||
232 | #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) | ||
233 | |||
234 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
235 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 | ||
236 | #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) | ||
237 | |||
238 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
239 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 | ||
240 | #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) | ||
241 | |||
242 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
243 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 | ||
244 | #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) | ||
245 | |||
246 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
247 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 | ||
248 | #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) | ||
249 | |||
250 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
251 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 | ||
252 | #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) | ||
253 | |||
254 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
255 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 | ||
256 | #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) | ||
257 | |||
258 | /* Used by CM_PER_L4LS_CLKSTCTRL */ | ||
259 | #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 | ||
260 | #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) | ||
261 | |||
262 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
263 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 | ||
264 | #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) | ||
265 | |||
266 | /* Used by CM_WKUP_CLKSTCTRL */ | ||
267 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 | ||
268 | #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) | ||
269 | |||
270 | /* Used by CLKSEL_GFX_FCLK */ | ||
271 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 | ||
272 | #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) | ||
273 | |||
274 | /* Used by CM_CLKOUT_CTRL */ | ||
275 | #define AM33XX_CLKOUT2DIV_SHIFT 3 | ||
276 | #define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) | ||
277 | |||
278 | /* Used by CM_CLKOUT_CTRL */ | ||
279 | #define AM33XX_CLKOUT2EN_SHIFT 7 | ||
280 | #define AM33XX_CLKOUT2EN_MASK (1 << 7) | ||
281 | |||
282 | /* Used by CM_CLKOUT_CTRL */ | ||
283 | #define AM33XX_CLKOUT2SOURCE_SHIFT 0 | ||
284 | #define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) | ||
285 | |||
286 | /* | ||
287 | * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, | ||
288 | * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, | ||
289 | * CLKSEL_TIMER7_CLK | ||
290 | */ | ||
291 | #define AM33XX_CLKSEL_SHIFT 0 | ||
292 | #define AM33XX_CLKSEL_MASK (0x01 << 0) | ||
293 | |||
294 | /* | ||
295 | * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, | ||
296 | * CM_CPTS_RFT_CLKSEL | ||
297 | */ | ||
298 | #define AM33XX_CLKSEL_0_0_SHIFT 0 | ||
299 | #define AM33XX_CLKSEL_0_0_MASK (1 << 0) | ||
300 | |||
301 | #define AM33XX_CLKSEL_0_1_SHIFT 0 | ||
302 | #define AM33XX_CLKSEL_0_1_MASK (3 << 0) | ||
303 | |||
304 | /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ | ||
305 | #define AM33XX_CLKSEL_0_2_SHIFT 0 | ||
306 | #define AM33XX_CLKSEL_0_2_MASK (7 << 0) | ||
307 | |||
308 | /* Used by CLKSEL_GFX_FCLK */ | ||
309 | #define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 | ||
310 | #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) | ||
311 | |||
312 | /* | ||
313 | * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, | ||
314 | * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, | ||
315 | * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, | ||
316 | * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, | ||
317 | * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, | ||
318 | * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL | ||
319 | */ | ||
320 | #define AM33XX_CLKTRCTRL_SHIFT 0 | ||
321 | #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) | ||
322 | |||
323 | /* | ||
324 | * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, | ||
325 | * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, | ||
326 | * CM_SSC_DELTAMSTEP_DPLL_PER | ||
327 | */ | ||
328 | #define AM33XX_DELTAMSTEP_SHIFT 0 | ||
329 | #define AM33XX_DELTAMSTEP_MASK (0x19 << 0) | ||
330 | |||
331 | /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ | ||
332 | #define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 | ||
333 | #define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) | ||
334 | |||
335 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
336 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 | ||
337 | #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) | ||
338 | |||
339 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
340 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 | ||
341 | #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) | ||
342 | |||
343 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
344 | #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 | ||
345 | #define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) | ||
346 | |||
347 | /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ | ||
348 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 | ||
349 | #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) | ||
350 | |||
351 | /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ | ||
352 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 | ||
353 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) | ||
354 | |||
355 | /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ | ||
356 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 | ||
357 | #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) | ||
358 | |||
359 | /* | ||
360 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
361 | * CM_DIV_M2_DPLL_PER | ||
362 | */ | ||
363 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 | ||
364 | #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | ||
365 | |||
366 | /* | ||
367 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
368 | * CM_CLKSEL_DPLL_MPU | ||
369 | */ | ||
370 | #define AM33XX_DPLL_DIV_SHIFT 0 | ||
371 | #define AM33XX_DPLL_DIV_MASK (0x7f << 0) | ||
372 | |||
373 | #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) | ||
374 | |||
375 | /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ | ||
376 | #define AM33XX_DPLL_DIV_0_7_SHIFT 0 | ||
377 | #define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) | ||
378 | |||
379 | /* | ||
380 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
381 | * CM_CLKMODE_DPLL_MPU | ||
382 | */ | ||
383 | #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 | ||
384 | #define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) | ||
385 | |||
386 | /* | ||
387 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
388 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
389 | */ | ||
390 | #define AM33XX_DPLL_EN_SHIFT 0 | ||
391 | #define AM33XX_DPLL_EN_MASK (0x7 << 0) | ||
392 | |||
393 | /* | ||
394 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
395 | * CM_CLKMODE_DPLL_MPU | ||
396 | */ | ||
397 | #define AM33XX_DPLL_LPMODE_EN_SHIFT 10 | ||
398 | #define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) | ||
399 | |||
400 | /* | ||
401 | * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, | ||
402 | * CM_CLKSEL_DPLL_MPU | ||
403 | */ | ||
404 | #define AM33XX_DPLL_MULT_SHIFT 8 | ||
405 | #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) | ||
406 | |||
407 | /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ | ||
408 | #define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 | ||
409 | #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) | ||
410 | |||
411 | /* | ||
412 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
413 | * CM_CLKMODE_DPLL_MPU | ||
414 | */ | ||
415 | #define AM33XX_DPLL_REGM4XEN_SHIFT 11 | ||
416 | #define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) | ||
417 | |||
418 | /* Used by CM_CLKSEL_DPLL_PERIPH */ | ||
419 | #define AM33XX_DPLL_SD_DIV_SHIFT 24 | ||
420 | #define AM33XX_DPLL_SD_DIV_MASK (24, 31) | ||
421 | |||
422 | /* | ||
423 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
424 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
425 | */ | ||
426 | #define AM33XX_DPLL_SSC_ACK_SHIFT 13 | ||
427 | #define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) | ||
428 | |||
429 | /* | ||
430 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
431 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
432 | */ | ||
433 | #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 | ||
434 | #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) | ||
435 | |||
436 | /* | ||
437 | * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, | ||
438 | * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER | ||
439 | */ | ||
440 | #define AM33XX_DPLL_SSC_EN_SHIFT 12 | ||
441 | #define AM33XX_DPLL_SSC_EN_MASK (1 << 12) | ||
442 | |||
443 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
444 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 | ||
445 | #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) | ||
446 | |||
447 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
448 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 | ||
449 | #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) | ||
450 | |||
451 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
452 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 | ||
453 | #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) | ||
454 | |||
455 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
456 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 | ||
457 | #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) | ||
458 | |||
459 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
460 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 | ||
461 | #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) | ||
462 | |||
463 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
464 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 | ||
465 | #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) | ||
466 | |||
467 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
468 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 | ||
469 | #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) | ||
470 | |||
471 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
472 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 | ||
473 | #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) | ||
474 | |||
475 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
476 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 | ||
477 | #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) | ||
478 | |||
479 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
480 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 | ||
481 | #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) | ||
482 | |||
483 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
484 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 | ||
485 | #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) | ||
486 | |||
487 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
488 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 | ||
489 | #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) | ||
490 | |||
491 | /* | ||
492 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
493 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
494 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
495 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
496 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
497 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
498 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
499 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
500 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
501 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
502 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
503 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
504 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
505 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
506 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
507 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
508 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
509 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
510 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
511 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
512 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
513 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
514 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
515 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
516 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
517 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
518 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
519 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
520 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
521 | * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, | ||
522 | * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL | ||
523 | */ | ||
524 | #define AM33XX_IDLEST_SHIFT 16 | ||
525 | #define AM33XX_IDLEST_MASK (0x3 << 16) | ||
526 | #define AM33XX_IDLEST_VAL 0x3 | ||
527 | |||
528 | /* Used by CM_MAC_CLKSEL */ | ||
529 | #define AM33XX_MII_CLK_SEL_SHIFT 2 | ||
530 | #define AM33XX_MII_CLK_SEL_MASK (1 << 2) | ||
531 | |||
532 | /* | ||
533 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
534 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
535 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
536 | */ | ||
537 | #define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 | ||
538 | #define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) | ||
539 | |||
540 | /* | ||
541 | * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, | ||
542 | * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, | ||
543 | * CM_SSC_MODFREQDIV_DPLL_PER | ||
544 | */ | ||
545 | #define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 | ||
546 | #define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) | ||
547 | |||
548 | /* | ||
549 | * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, | ||
550 | * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, | ||
551 | * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, | ||
552 | * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, | ||
553 | * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, | ||
554 | * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, | ||
555 | * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, | ||
556 | * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, | ||
557 | * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, | ||
558 | * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, | ||
559 | * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, | ||
560 | * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, | ||
561 | * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, | ||
562 | * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, | ||
563 | * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
564 | * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, | ||
565 | * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, | ||
566 | * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, | ||
567 | * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, | ||
568 | * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, | ||
569 | * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, | ||
570 | * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
571 | * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, | ||
572 | * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, | ||
573 | * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, | ||
574 | * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, | ||
575 | * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, | ||
576 | * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, | ||
577 | * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, | ||
578 | * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, | ||
579 | * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, | ||
580 | * CM_CEFUSE_CEFUSE_CLKCTRL | ||
581 | */ | ||
582 | #define AM33XX_MODULEMODE_SHIFT 0 | ||
583 | #define AM33XX_MODULEMODE_MASK (0x3 << 0) | ||
584 | |||
585 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
586 | #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 | ||
587 | #define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) | ||
588 | |||
589 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
590 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 | ||
591 | #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) | ||
592 | |||
593 | /* Used by CM_WKUP_GPIO0_CLKCTRL */ | ||
594 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 | ||
595 | #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) | ||
596 | |||
597 | /* Used by CM_PER_GPIO1_CLKCTRL */ | ||
598 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 | ||
599 | #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) | ||
600 | |||
601 | /* Used by CM_PER_GPIO2_CLKCTRL */ | ||
602 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 | ||
603 | #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) | ||
604 | |||
605 | /* Used by CM_PER_GPIO3_CLKCTRL */ | ||
606 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 | ||
607 | #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) | ||
608 | |||
609 | /* Used by CM_PER_GPIO4_CLKCTRL */ | ||
610 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 | ||
611 | #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) | ||
612 | |||
613 | /* Used by CM_PER_GPIO5_CLKCTRL */ | ||
614 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 | ||
615 | #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) | ||
616 | |||
617 | /* Used by CM_PER_GPIO6_CLKCTRL */ | ||
618 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 | ||
619 | #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) | ||
620 | |||
621 | /* | ||
622 | * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, | ||
623 | * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, | ||
624 | * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, | ||
625 | * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, | ||
626 | * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, | ||
627 | * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL | ||
628 | */ | ||
629 | #define AM33XX_STBYST_SHIFT 18 | ||
630 | #define AM33XX_STBYST_MASK (1 << 18) | ||
631 | |||
632 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
633 | #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 | ||
634 | #define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) | ||
635 | |||
636 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
637 | #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 | ||
638 | #define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) | ||
639 | |||
640 | /* | ||
641 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
642 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
643 | */ | ||
644 | #define AM33XX_ST_DPLL_CLK_SHIFT 0 | ||
645 | #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) | ||
646 | |||
647 | /* Used by CM_CLKDCOLDO_DPLL_PER */ | ||
648 | #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 | ||
649 | #define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) | ||
650 | |||
651 | /* | ||
652 | * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, | ||
653 | * CM_DIV_M2_DPLL_PER | ||
654 | */ | ||
655 | #define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 | ||
656 | #define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) | ||
657 | |||
658 | /* Used by CM_DIV_M4_DPLL_CORE */ | ||
659 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 | ||
660 | #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) | ||
661 | |||
662 | /* Used by CM_DIV_M5_DPLL_CORE */ | ||
663 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 | ||
664 | #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) | ||
665 | |||
666 | /* Used by CM_DIV_M6_DPLL_CORE */ | ||
667 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 | ||
668 | #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) | ||
669 | |||
670 | /* | ||
671 | * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, | ||
672 | * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER | ||
673 | */ | ||
674 | #define AM33XX_ST_MN_BYPASS_SHIFT 8 | ||
675 | #define AM33XX_ST_MN_BYPASS_MASK (1 << 8) | ||
676 | |||
677 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
678 | #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 | ||
679 | #define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) | ||
680 | |||
681 | /* Used by CM_WKUP_DEBUGSS_CLKCTRL */ | ||
682 | #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 | ||
683 | #define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) | ||
684 | |||
685 | /* Used by CONTROL_SEC_CLK_CTRL */ | ||
686 | #define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) | ||
687 | #endif | ||
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 8083a8cdc55f..766338fe4d34 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
@@ -169,8 +169,6 @@ | |||
169 | /* AM35XX specific CM_ICLKEN1_CORE bits */ | 169 | /* AM35XX specific CM_ICLKEN1_CORE bits */ |
170 | #define AM35XX_EN_IPSS_MASK (1 << 4) | 170 | #define AM35XX_EN_IPSS_MASK (1 << 4) |
171 | #define AM35XX_EN_IPSS_SHIFT 4 | 171 | #define AM35XX_EN_IPSS_SHIFT 4 |
172 | #define AM35XX_EN_UART4_MASK (1 << 23) | ||
173 | #define AM35XX_EN_UART4_SHIFT 23 | ||
174 | 172 | ||
175 | /* CM_ICLKEN2_CORE */ | 173 | /* CM_ICLKEN2_CORE */ |
176 | #define OMAP3430_EN_PKA_MASK (1 << 4) | 174 | #define OMAP3430_EN_PKA_MASK (1 << 4) |
@@ -207,6 +205,8 @@ | |||
207 | #define OMAP3430_ST_DES2_MASK (1 << 26) | 205 | #define OMAP3430_ST_DES2_MASK (1 << 26) |
208 | #define OMAP3430_ST_MSPRO_SHIFT 23 | 206 | #define OMAP3430_ST_MSPRO_SHIFT 23 |
209 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) | 207 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) |
208 | #define AM35XX_ST_UART4_SHIFT 23 | ||
209 | #define AM35XX_ST_UART4_MASK (1 << 23) | ||
210 | #define OMAP3430_ST_HDQ_SHIFT 22 | 210 | #define OMAP3430_ST_HDQ_SHIFT 22 |
211 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | 211 | #define OMAP3430_ST_HDQ_MASK (1 << 22) |
212 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | 212 | #define OMAP3430ES1_ST_FAC_SHIFT 8 |
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c new file mode 100644 index 000000000000..13f56eafef03 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.c | |||
@@ -0,0 +1,313 @@ | |||
1 | /* | ||
2 | * AM33XX CM functions | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
6 | * | ||
7 | * Reference taken from from OMAP4 cminst44xx.c | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License as | ||
11 | * published by the Free Software Foundation version 2. | ||
12 | * | ||
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
14 | * kind, whether express or implied; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | */ | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/types.h> | ||
21 | #include <linux/errno.h> | ||
22 | #include <linux/err.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <plat/common.h> | ||
26 | |||
27 | #include "cm.h" | ||
28 | #include "cm33xx.h" | ||
29 | #include "cm-regbits-34xx.h" | ||
30 | #include "cm-regbits-33xx.h" | ||
31 | #include "prm33xx.h" | ||
32 | |||
33 | /* | ||
34 | * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: | ||
35 | * | ||
36 | * 0x0 func: Module is fully functional, including OCP | ||
37 | * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep | ||
38 | * abortion | ||
39 | * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if | ||
40 | * using separate functional clock | ||
41 | * 0x3 disabled: Module is disabled and cannot be accessed | ||
42 | * | ||
43 | */ | ||
44 | #define CLKCTRL_IDLEST_FUNCTIONAL 0x0 | ||
45 | #define CLKCTRL_IDLEST_INTRANSITION 0x1 | ||
46 | #define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 | ||
47 | #define CLKCTRL_IDLEST_DISABLED 0x3 | ||
48 | |||
49 | /* Private functions */ | ||
50 | |||
51 | /* Read a register in a CM instance */ | ||
52 | static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) | ||
53 | { | ||
54 | return __raw_readl(cm_base + inst + idx); | ||
55 | } | ||
56 | |||
57 | /* Write into a register in a CM */ | ||
58 | static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) | ||
59 | { | ||
60 | __raw_writel(val, cm_base + inst + idx); | ||
61 | } | ||
62 | |||
63 | /* Read-modify-write a register in CM */ | ||
64 | static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) | ||
65 | { | ||
66 | u32 v; | ||
67 | |||
68 | v = am33xx_cm_read_reg(inst, idx); | ||
69 | v &= ~mask; | ||
70 | v |= bits; | ||
71 | am33xx_cm_write_reg(v, inst, idx); | ||
72 | |||
73 | return v; | ||
74 | } | ||
75 | |||
76 | static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx) | ||
77 | { | ||
78 | return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx); | ||
79 | } | ||
80 | |||
81 | static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx) | ||
82 | { | ||
83 | return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); | ||
84 | } | ||
85 | |||
86 | static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) | ||
87 | { | ||
88 | u32 v; | ||
89 | |||
90 | v = am33xx_cm_read_reg(inst, idx); | ||
91 | v &= mask; | ||
92 | v >>= __ffs(mask); | ||
93 | |||
94 | return v; | ||
95 | } | ||
96 | |||
97 | /** | ||
98 | * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield | ||
99 | * @inst: CM instance register offset (*_INST macro) | ||
100 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
101 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
102 | * | ||
103 | * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to | ||
104 | * bit 0. | ||
105 | */ | ||
106 | static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
107 | { | ||
108 | u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
109 | v &= AM33XX_IDLEST_MASK; | ||
110 | v >>= AM33XX_IDLEST_SHIFT; | ||
111 | return v; | ||
112 | } | ||
113 | |||
114 | /** | ||
115 | * _is_module_ready - can module registers be accessed without causing an abort? | ||
116 | * @inst: CM instance register offset (*_INST macro) | ||
117 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
118 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
119 | * | ||
120 | * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either | ||
121 | * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. | ||
122 | */ | ||
123 | static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
124 | { | ||
125 | u32 v; | ||
126 | |||
127 | v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); | ||
128 | |||
129 | return (v == CLKCTRL_IDLEST_FUNCTIONAL || | ||
130 | v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; | ||
131 | } | ||
132 | |||
133 | /** | ||
134 | * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield | ||
135 | * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) | ||
136 | * @inst: CM instance register offset (*_INST macro) | ||
137 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
138 | * | ||
139 | * @c must be the unshifted value for CLKTRCTRL - i.e., this function | ||
140 | * will handle the shift itself. | ||
141 | */ | ||
142 | static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) | ||
143 | { | ||
144 | u32 v; | ||
145 | |||
146 | v = am33xx_cm_read_reg(inst, cdoffs); | ||
147 | v &= ~AM33XX_CLKTRCTRL_MASK; | ||
148 | v |= c << AM33XX_CLKTRCTRL_SHIFT; | ||
149 | am33xx_cm_write_reg(v, inst, cdoffs); | ||
150 | } | ||
151 | |||
152 | /* Public functions */ | ||
153 | |||
154 | /** | ||
155 | * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? | ||
156 | * @inst: CM instance register offset (*_INST macro) | ||
157 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
158 | * | ||
159 | * Returns true if the clockdomain referred to by (@inst, @cdoffs) | ||
160 | * is in hardware-supervised idle mode, or 0 otherwise. | ||
161 | */ | ||
162 | bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) | ||
163 | { | ||
164 | u32 v; | ||
165 | |||
166 | v = am33xx_cm_read_reg(inst, cdoffs); | ||
167 | v &= AM33XX_CLKTRCTRL_MASK; | ||
168 | v >>= AM33XX_CLKTRCTRL_SHIFT; | ||
169 | |||
170 | return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; | ||
171 | } | ||
172 | |||
173 | /** | ||
174 | * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode | ||
175 | * @inst: CM instance register offset (*_INST macro) | ||
176 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
177 | * | ||
178 | * Put a clockdomain referred to by (@inst, @cdoffs) into | ||
179 | * hardware-supervised idle mode. No return value. | ||
180 | */ | ||
181 | void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) | ||
182 | { | ||
183 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); | ||
184 | } | ||
185 | |||
186 | /** | ||
187 | * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode | ||
188 | * @inst: CM instance register offset (*_INST macro) | ||
189 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
190 | * | ||
191 | * Put a clockdomain referred to by (@inst, @cdoffs) into | ||
192 | * software-supervised idle mode, i.e., controlled manually by the | ||
193 | * Linux OMAP clockdomain code. No return value. | ||
194 | */ | ||
195 | void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) | ||
196 | { | ||
197 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); | ||
198 | } | ||
199 | |||
200 | /** | ||
201 | * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle | ||
202 | * @inst: CM instance register offset (*_INST macro) | ||
203 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
204 | * | ||
205 | * Put a clockdomain referred to by (@inst, @cdoffs) into idle | ||
206 | * No return value. | ||
207 | */ | ||
208 | void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) | ||
209 | { | ||
210 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); | ||
211 | } | ||
212 | |||
213 | /** | ||
214 | * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle | ||
215 | * @inst: CM instance register offset (*_INST macro) | ||
216 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
217 | * | ||
218 | * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, | ||
219 | * waking it up. No return value. | ||
220 | */ | ||
221 | void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) | ||
222 | { | ||
223 | _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); | ||
224 | } | ||
225 | |||
226 | /* | ||
227 | * | ||
228 | */ | ||
229 | |||
230 | /** | ||
231 | * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state | ||
232 | * @inst: CM instance register offset (*_INST macro) | ||
233 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
234 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
235 | * | ||
236 | * Wait for the module IDLEST to be functional. If the idle state is in any | ||
237 | * the non functional state (trans, idle or disabled), module and thus the | ||
238 | * sysconfig cannot be accessed and will probably lead to an "imprecise | ||
239 | * external abort" | ||
240 | */ | ||
241 | int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
242 | { | ||
243 | int i = 0; | ||
244 | |||
245 | if (!clkctrl_offs) | ||
246 | return 0; | ||
247 | |||
248 | omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), | ||
249 | MAX_MODULE_READY_TIME, i); | ||
250 | |||
251 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
252 | } | ||
253 | |||
254 | /** | ||
255 | * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' | ||
256 | * state | ||
257 | * @inst: CM instance register offset (*_INST macro) | ||
258 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
259 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
260 | * | ||
261 | * Wait for the module IDLEST to be disabled. Some PRCM transition, | ||
262 | * like reset assertion or parent clock de-activation must wait the | ||
263 | * module to be fully disabled. | ||
264 | */ | ||
265 | int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
266 | { | ||
267 | int i = 0; | ||
268 | |||
269 | if (!clkctrl_offs) | ||
270 | return 0; | ||
271 | |||
272 | omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == | ||
273 | CLKCTRL_IDLEST_DISABLED), | ||
274 | MAX_MODULE_READY_TIME, i); | ||
275 | |||
276 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | ||
277 | } | ||
278 | |||
279 | /** | ||
280 | * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL | ||
281 | * @mode: Module mode (SW or HW) | ||
282 | * @inst: CM instance register offset (*_INST macro) | ||
283 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
284 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
285 | * | ||
286 | * No return value. | ||
287 | */ | ||
288 | void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
289 | { | ||
290 | u32 v; | ||
291 | |||
292 | v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
293 | v &= ~AM33XX_MODULEMODE_MASK; | ||
294 | v |= mode << AM33XX_MODULEMODE_SHIFT; | ||
295 | am33xx_cm_write_reg(v, inst, clkctrl_offs); | ||
296 | } | ||
297 | |||
298 | /** | ||
299 | * am33xx_cm_module_disable - Disable the module inside CLKCTRL | ||
300 | * @inst: CM instance register offset (*_INST macro) | ||
301 | * @cdoffs: Clockdomain register offset (*_CDOFFS macro) | ||
302 | * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) | ||
303 | * | ||
304 | * No return value. | ||
305 | */ | ||
306 | void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) | ||
307 | { | ||
308 | u32 v; | ||
309 | |||
310 | v = am33xx_cm_read_reg(inst, clkctrl_offs); | ||
311 | v &= ~AM33XX_MODULEMODE_MASK; | ||
312 | am33xx_cm_write_reg(v, inst, clkctrl_offs); | ||
313 | } | ||
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h new file mode 100644 index 000000000000..5fa0b62e1a79 --- /dev/null +++ b/arch/arm/mach-omap2/cm33xx.h | |||
@@ -0,0 +1,420 @@ | |||
1 | /* | ||
2 | * AM33XX CM offset macros | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * Vaibhav Hiremath <hvaibhav@ti.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or | ||
8 | * modify it under the terms of the GNU General Public License as | ||
9 | * published by the Free Software Foundation version 2. | ||
10 | * | ||
11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
12 | * kind, whether express or implied; without even the implied warranty | ||
13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | */ | ||
16 | |||
17 | #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H | ||
18 | #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H | ||
19 | |||
20 | #include <linux/delay.h> | ||
21 | #include <linux/errno.h> | ||
22 | #include <linux/err.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include "common.h" | ||
26 | |||
27 | #include "cm.h" | ||
28 | #include "cm-regbits-33xx.h" | ||
29 | #include "cm33xx.h" | ||
30 | |||
31 | /* CM base address */ | ||
32 | #define AM33XX_CM_BASE 0x44e00000 | ||
33 | |||
34 | #define AM33XX_CM_REGADDR(inst, reg) \ | ||
35 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) | ||
36 | |||
37 | /* CM instances */ | ||
38 | #define AM33XX_CM_PER_MOD 0x0000 | ||
39 | #define AM33XX_CM_WKUP_MOD 0x0400 | ||
40 | #define AM33XX_CM_DPLL_MOD 0x0500 | ||
41 | #define AM33XX_CM_MPU_MOD 0x0600 | ||
42 | #define AM33XX_CM_DEVICE_MOD 0x0700 | ||
43 | #define AM33XX_CM_RTC_MOD 0x0800 | ||
44 | #define AM33XX_CM_GFX_MOD 0x0900 | ||
45 | #define AM33XX_CM_CEFUSE_MOD 0x0A00 | ||
46 | |||
47 | /* CM */ | ||
48 | |||
49 | /* CM.PER_CM register offsets */ | ||
50 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 | ||
51 | #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) | ||
52 | #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 | ||
53 | #define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) | ||
54 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 | ||
55 | #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) | ||
56 | #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c | ||
57 | #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) | ||
58 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 | ||
59 | #define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) | ||
60 | #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 | ||
61 | #define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) | ||
62 | #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c | ||
63 | #define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) | ||
64 | #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 | ||
65 | #define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) | ||
66 | #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 | ||
67 | #define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) | ||
68 | #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 | ||
69 | #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) | ||
70 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c | ||
71 | #define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) | ||
72 | #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 | ||
73 | #define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) | ||
74 | #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 | ||
75 | #define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) | ||
76 | #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 | ||
77 | #define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) | ||
78 | #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c | ||
79 | #define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) | ||
80 | #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 | ||
81 | #define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) | ||
82 | #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 | ||
83 | #define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) | ||
84 | #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 | ||
85 | #define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) | ||
86 | #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c | ||
87 | #define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) | ||
88 | #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 | ||
89 | #define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) | ||
90 | #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 | ||
91 | #define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) | ||
92 | #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 | ||
93 | #define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) | ||
94 | #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 | ||
95 | #define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) | ||
96 | #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 | ||
97 | #define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) | ||
98 | #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 | ||
99 | #define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) | ||
100 | #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c | ||
101 | #define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) | ||
102 | #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 | ||
103 | #define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) | ||
104 | #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 | ||
105 | #define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) | ||
106 | #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 | ||
107 | #define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) | ||
108 | #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c | ||
109 | #define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) | ||
110 | #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 | ||
111 | #define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) | ||
112 | #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 | ||
113 | #define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) | ||
114 | #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 | ||
115 | #define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) | ||
116 | #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c | ||
117 | #define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) | ||
118 | #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 | ||
119 | #define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) | ||
120 | #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 | ||
121 | #define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) | ||
122 | #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 | ||
123 | #define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) | ||
124 | #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c | ||
125 | #define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) | ||
126 | #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 | ||
127 | #define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) | ||
128 | #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 | ||
129 | #define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) | ||
130 | #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 | ||
131 | #define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) | ||
132 | #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac | ||
133 | #define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) | ||
134 | #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 | ||
135 | #define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) | ||
136 | #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 | ||
137 | #define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) | ||
138 | #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 | ||
139 | #define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) | ||
140 | #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc | ||
141 | #define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) | ||
142 | #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 | ||
143 | #define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) | ||
144 | #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 | ||
145 | #define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) | ||
146 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc | ||
147 | #define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) | ||
148 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 | ||
149 | #define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) | ||
150 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 | ||
151 | #define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) | ||
152 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 | ||
153 | #define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) | ||
154 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc | ||
155 | #define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) | ||
156 | #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 | ||
157 | #define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) | ||
158 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 | ||
159 | #define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) | ||
160 | #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 | ||
161 | #define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) | ||
162 | #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec | ||
163 | #define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) | ||
164 | #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 | ||
165 | #define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) | ||
166 | #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 | ||
167 | #define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) | ||
168 | #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 | ||
169 | #define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) | ||
170 | #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc | ||
171 | #define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) | ||
172 | #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 | ||
173 | #define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) | ||
174 | #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 | ||
175 | #define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) | ||
176 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c | ||
177 | #define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) | ||
178 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 | ||
179 | #define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) | ||
180 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c | ||
181 | #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) | ||
182 | #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 | ||
183 | #define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) | ||
184 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 | ||
185 | #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) | ||
186 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 | ||
187 | #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) | ||
188 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c | ||
189 | #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) | ||
190 | #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 | ||
191 | #define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) | ||
192 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 | ||
193 | #define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) | ||
194 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 | ||
195 | #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) | ||
196 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 | ||
197 | #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) | ||
198 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 | ||
199 | #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) | ||
200 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c | ||
201 | #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) | ||
202 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 | ||
203 | #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) | ||
204 | |||
205 | /* CM.WKUP_CM register offsets */ | ||
206 | #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 | ||
207 | #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) | ||
208 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 | ||
209 | #define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) | ||
210 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 | ||
211 | #define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) | ||
212 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c | ||
213 | #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) | ||
214 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 | ||
215 | #define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) | ||
216 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 | ||
217 | #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) | ||
218 | #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 | ||
219 | #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) | ||
220 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c | ||
221 | #define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) | ||
222 | #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 | ||
223 | #define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) | ||
224 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 | ||
225 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) | ||
226 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 | ||
227 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) | ||
228 | #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c | ||
229 | #define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) | ||
230 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 | ||
231 | #define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) | ||
232 | #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 | ||
233 | #define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) | ||
234 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 | ||
235 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) | ||
236 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c | ||
237 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) | ||
238 | #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 | ||
239 | #define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) | ||
240 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 | ||
241 | #define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) | ||
242 | #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 | ||
243 | #define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) | ||
244 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c | ||
245 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) | ||
246 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 | ||
247 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) | ||
248 | #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 | ||
249 | #define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) | ||
250 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 | ||
251 | #define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) | ||
252 | #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c | ||
253 | #define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) | ||
254 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 | ||
255 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) | ||
256 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 | ||
257 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) | ||
258 | #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 | ||
259 | #define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) | ||
260 | #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c | ||
261 | #define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) | ||
262 | #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 | ||
263 | #define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) | ||
264 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 | ||
265 | #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) | ||
266 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 | ||
267 | #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) | ||
268 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c | ||
269 | #define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) | ||
270 | #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 | ||
271 | #define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) | ||
272 | #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 | ||
273 | #define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) | ||
274 | #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 | ||
275 | #define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) | ||
276 | #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c | ||
277 | #define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) | ||
278 | #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 | ||
279 | #define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) | ||
280 | #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 | ||
281 | #define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) | ||
282 | #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 | ||
283 | #define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) | ||
284 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c | ||
285 | #define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) | ||
286 | #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 | ||
287 | #define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) | ||
288 | #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 | ||
289 | #define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) | ||
290 | #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 | ||
291 | #define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) | ||
292 | #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac | ||
293 | #define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) | ||
294 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 | ||
295 | #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) | ||
296 | #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 | ||
297 | #define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) | ||
298 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 | ||
299 | #define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) | ||
300 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc | ||
301 | #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) | ||
302 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 | ||
303 | #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) | ||
304 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 | ||
305 | #define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) | ||
306 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 | ||
307 | #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) | ||
308 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc | ||
309 | #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) | ||
310 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 | ||
311 | #define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) | ||
312 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 | ||
313 | #define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) | ||
314 | #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 | ||
315 | #define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) | ||
316 | |||
317 | /* CM.DPLL_CM register offsets */ | ||
318 | #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 | ||
319 | #define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) | ||
320 | #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 | ||
321 | #define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) | ||
322 | #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c | ||
323 | #define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) | ||
324 | #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 | ||
325 | #define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) | ||
326 | #define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 | ||
327 | #define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) | ||
328 | #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 | ||
329 | #define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) | ||
330 | #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c | ||
331 | #define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) | ||
332 | #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 | ||
333 | #define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) | ||
334 | #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 | ||
335 | #define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) | ||
336 | #define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c | ||
337 | #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) | ||
338 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 | ||
339 | #define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) | ||
340 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 | ||
341 | #define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) | ||
342 | #define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 | ||
343 | #define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) | ||
344 | #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c | ||
345 | #define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) | ||
346 | |||
347 | /* CM.MPU_CM register offsets */ | ||
348 | #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 | ||
349 | #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) | ||
350 | #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 | ||
351 | #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) | ||
352 | |||
353 | /* CM.DEVICE_CM register offsets */ | ||
354 | #define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 | ||
355 | #define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) | ||
356 | |||
357 | /* CM.RTC_CM register offsets */ | ||
358 | #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 | ||
359 | #define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) | ||
360 | #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 | ||
361 | #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) | ||
362 | |||
363 | /* CM.GFX_CM register offsets */ | ||
364 | #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 | ||
365 | #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) | ||
366 | #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 | ||
367 | #define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) | ||
368 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 | ||
369 | #define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) | ||
370 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c | ||
371 | #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) | ||
372 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 | ||
373 | #define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) | ||
374 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 | ||
375 | #define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) | ||
376 | |||
377 | /* CM.CEFUSE_CM register offsets */ | ||
378 | #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 | ||
379 | #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) | ||
380 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 | ||
381 | #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) | ||
382 | |||
383 | |||
384 | extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); | ||
385 | extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); | ||
386 | extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); | ||
387 | extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); | ||
388 | extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); | ||
389 | |||
390 | #ifdef CONFIG_SOC_AM33XX | ||
391 | extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, | ||
392 | u16 clkctrl_offs); | ||
393 | extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, | ||
394 | u16 clkctrl_offs); | ||
395 | extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs, | ||
396 | u16 clkctrl_offs); | ||
397 | extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, | ||
398 | u16 clkctrl_offs); | ||
399 | #else | ||
400 | static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, | ||
401 | u16 clkctrl_offs) | ||
402 | { | ||
403 | return 0; | ||
404 | } | ||
405 | static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, | ||
406 | u16 clkctrl_offs) | ||
407 | { | ||
408 | } | ||
409 | static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs, | ||
410 | u16 clkctrl_offs) | ||
411 | { | ||
412 | } | ||
413 | static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, | ||
414 | u16 clkctrl_offs) | ||
415 | { | ||
416 | return 0; | ||
417 | } | ||
418 | #endif | ||
419 | |||
420 | #endif | ||
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c index 1706ebcec08d..c1875862679f 100644 --- a/arch/arm/mach-omap2/common-board-devices.c +++ b/arch/arm/mach-omap2/common-board-devices.c | |||
@@ -63,28 +63,30 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce, | |||
63 | struct spi_board_info *spi_bi = &ads7846_spi_board_info; | 63 | struct spi_board_info *spi_bi = &ads7846_spi_board_info; |
64 | int err; | 64 | int err; |
65 | 65 | ||
66 | if (board_pdata && board_pdata->get_pendown_state) { | 66 | err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); |
67 | err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown"); | 67 | if (err) { |
68 | if (err) { | 68 | pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); |
69 | pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err); | 69 | return; |
70 | return; | ||
71 | } | ||
72 | gpio_export(gpio_pendown, 0); | ||
73 | |||
74 | if (gpio_debounce) | ||
75 | gpio_set_debounce(gpio_pendown, gpio_debounce); | ||
76 | } | 70 | } |
77 | 71 | ||
72 | if (gpio_debounce) | ||
73 | gpio_set_debounce(gpio_pendown, gpio_debounce); | ||
74 | |||
78 | spi_bi->bus_num = bus_num; | 75 | spi_bi->bus_num = bus_num; |
79 | spi_bi->irq = gpio_to_irq(gpio_pendown); | 76 | spi_bi->irq = gpio_to_irq(gpio_pendown); |
80 | 77 | ||
81 | if (board_pdata) { | 78 | if (board_pdata) { |
82 | board_pdata->gpio_pendown = gpio_pendown; | 79 | board_pdata->gpio_pendown = gpio_pendown; |
83 | spi_bi->platform_data = board_pdata; | 80 | spi_bi->platform_data = board_pdata; |
81 | if (board_pdata->get_pendown_state) | ||
82 | gpio_export(gpio_pendown, 0); | ||
84 | } else { | 83 | } else { |
85 | ads7846_config.gpio_pendown = gpio_pendown; | 84 | ads7846_config.gpio_pendown = gpio_pendown; |
86 | } | 85 | } |
87 | 86 | ||
87 | if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state)) | ||
88 | gpio_free(gpio_pendown); | ||
89 | |||
88 | spi_register_board_info(&ads7846_spi_board_info, 1); | 90 | spi_register_board_info(&ads7846_spi_board_info, 1); |
89 | } | 91 | } |
90 | #else | 92 | #else |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index be9dfd1abe60..5d99c1b2cb48 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
@@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void); | |||
120 | extern struct sys_timer omap2_timer; | 120 | extern struct sys_timer omap2_timer; |
121 | extern struct sys_timer omap3_timer; | 121 | extern struct sys_timer omap3_timer; |
122 | extern struct sys_timer omap3_secure_timer; | 122 | extern struct sys_timer omap3_secure_timer; |
123 | extern struct sys_timer omap3_am33xx_timer; | ||
123 | extern struct sys_timer omap4_timer; | 124 | extern struct sys_timer omap4_timer; |
124 | 125 | ||
125 | void omap2420_init_early(void); | 126 | void omap2420_init_early(void); |
@@ -128,8 +129,10 @@ void omap3430_init_early(void); | |||
128 | void omap35xx_init_early(void); | 129 | void omap35xx_init_early(void); |
129 | void omap3630_init_early(void); | 130 | void omap3630_init_early(void); |
130 | void omap3_init_early(void); /* Do not use this one */ | 131 | void omap3_init_early(void); /* Do not use this one */ |
132 | void am33xx_init_early(void); | ||
131 | void am35xx_init_early(void); | 133 | void am35xx_init_early(void); |
132 | void ti81xx_init_early(void); | 134 | void ti81xx_init_early(void); |
135 | void am33xx_init_early(void); | ||
133 | void omap4430_init_early(void); | 136 | void omap4430_init_early(void); |
134 | void omap3_init_late(void); /* Do not use this one */ | 137 | void omap3_init_late(void); /* Do not use this one */ |
135 | void omap4430_init_late(void); | 138 | void omap4430_init_late(void); |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 08e674bb0417..3223b81e7532 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
@@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode) | |||
241 | 241 | ||
242 | #endif | 242 | #endif |
243 | 243 | ||
244 | /** | ||
245 | * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor | ||
246 | * @bootaddr: physical address of the boot loader | ||
247 | * | ||
248 | * Set boot address for the boot loader of a supported processor | ||
249 | * when a power ON sequence occurs. | ||
250 | */ | ||
251 | void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) | ||
252 | { | ||
253 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : | ||
254 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : | ||
255 | cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : | ||
256 | 0; | ||
257 | |||
258 | if (!offset) { | ||
259 | pr_err("%s: unsupported omap type\n", __func__); | ||
260 | return; | ||
261 | } | ||
262 | |||
263 | omap_ctrl_writel(bootaddr, offset); | ||
264 | } | ||
265 | |||
266 | /** | ||
267 | * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor | ||
268 | * @bootmode: 8-bit value to pass to some boot code | ||
269 | * | ||
270 | * Sets boot mode for the boot loader of a supported processor | ||
271 | * when a power ON sequence occurs. | ||
272 | */ | ||
273 | void omap_ctrl_write_dsp_boot_mode(u8 bootmode) | ||
274 | { | ||
275 | u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : | ||
276 | cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : | ||
277 | 0; | ||
278 | |||
279 | if (!offset) { | ||
280 | pr_err("%s: unsupported omap type\n", __func__); | ||
281 | return; | ||
282 | } | ||
283 | |||
284 | omap_ctrl_writel(bootmode, offset); | ||
285 | } | ||
286 | |||
244 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) | 287 | #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) |
245 | /* | 288 | /* |
246 | * Clears the scratchpad contents in case of cold boot- | 289 | * Clears the scratchpad contents in case of cold boot- |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index a406fd045ce1..5baf305386e9 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
@@ -21,6 +21,8 @@ | |||
21 | #include <mach/ctrl_module_pad_core_44xx.h> | 21 | #include <mach/ctrl_module_pad_core_44xx.h> |
22 | #include <mach/ctrl_module_pad_wkup_44xx.h> | 22 | #include <mach/ctrl_module_pad_wkup_44xx.h> |
23 | 23 | ||
24 | #include <plat/am33xx.h> | ||
25 | |||
24 | #ifndef __ASSEMBLY__ | 26 | #ifndef __ASSEMBLY__ |
25 | #define OMAP242X_CTRL_REGADDR(reg) \ | 27 | #define OMAP242X_CTRL_REGADDR(reg) \ |
26 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 28 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
@@ -28,6 +30,8 @@ | |||
28 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 30 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
29 | #define OMAP343X_CTRL_REGADDR(reg) \ | 31 | #define OMAP343X_CTRL_REGADDR(reg) \ |
30 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 32 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
33 | #define AM33XX_CTRL_REGADDR(reg) \ | ||
34 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | ||
31 | #else | 35 | #else |
32 | #define OMAP242X_CTRL_REGADDR(reg) \ | 36 | #define OMAP242X_CTRL_REGADDR(reg) \ |
33 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) | 37 | OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) |
@@ -35,6 +39,8 @@ | |||
35 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) | 39 | OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) |
36 | #define OMAP343X_CTRL_REGADDR(reg) \ | 40 | #define OMAP343X_CTRL_REGADDR(reg) \ |
37 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) | 41 | OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) |
42 | #define AM33XX_CTRL_REGADDR(reg) \ | ||
43 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) | ||
38 | #endif /* __ASSEMBLY__ */ | 44 | #endif /* __ASSEMBLY__ */ |
39 | 45 | ||
40 | /* | 46 | /* |
@@ -312,15 +318,15 @@ | |||
312 | OMAP343X_SCRATCHPAD + reg) | 318 | OMAP343X_SCRATCHPAD + reg) |
313 | 319 | ||
314 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ | 320 | /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ |
315 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 | 321 | #define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 |
316 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 | 322 | #define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 |
317 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 | 323 | #define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 |
318 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 | 324 | #define AM35XX_HECC_VBUSP_CLK_SHIFT 3 |
319 | #define AM35XX_USBOTG_FCLK_SHIFT 8 | 325 | #define AM35XX_USBOTG_FCLK_SHIFT 8 |
320 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 | 326 | #define AM35XX_CPGMAC_FCLK_SHIFT 9 |
321 | #define AM35XX_VPFE_FCLK_SHIFT 10 | 327 | #define AM35XX_VPFE_FCLK_SHIFT 10 |
322 | 328 | ||
323 | /*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ | 329 | /* AM35XX CONTROL_LVL_INTR_CLEAR bits */ |
324 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) | 330 | #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) |
325 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) | 331 | #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) |
326 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) | 332 | #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) |
@@ -330,21 +336,22 @@ | |||
330 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) | 336 | #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) |
331 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) | 337 | #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) |
332 | 338 | ||
333 | /*AM35XX CONTROL_IP_SW_RESET bits*/ | 339 | /* AM35XX CONTROL_IP_SW_RESET bits */ |
334 | #define AM35XX_USBOTGSS_SW_RST BIT(0) | 340 | #define AM35XX_USBOTGSS_SW_RST BIT(0) |
335 | #define AM35XX_CPGMACSS_SW_RST BIT(1) | 341 | #define AM35XX_CPGMACSS_SW_RST BIT(1) |
336 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) | 342 | #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) |
337 | #define AM35XX_HECC_SW_RST BIT(3) | 343 | #define AM35XX_HECC_SW_RST BIT(3) |
338 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) | 344 | #define AM35XX_VPFE_PCLK_SW_RST BIT(4) |
339 | 345 | ||
340 | /* | 346 | /* AM33XX CONTROL_STATUS register */ |
341 | * CONTROL AM33XX STATUS register | ||
342 | */ | ||
343 | #define AM33XX_CONTROL_STATUS 0x040 | 347 | #define AM33XX_CONTROL_STATUS 0x040 |
348 | #define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc | ||
344 | 349 | ||
345 | /* | 350 | /* AM33XX CONTROL_STATUS bitfields (partial) */ |
346 | * CONTROL OMAP STATUS register to identify OMAP3 features | 351 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 |
347 | */ | 352 | #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) |
353 | |||
354 | /* CONTROL OMAP STATUS register to identify OMAP3 features */ | ||
348 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c | 355 | #define OMAP3_CONTROL_OMAP_STATUS 0x044c |
349 | 356 | ||
350 | #define OMAP3_SGX_SHIFT 13 | 357 | #define OMAP3_SGX_SHIFT 13 |
@@ -397,6 +404,8 @@ extern u32 omap3_arm_context[128]; | |||
397 | extern void omap3_control_save_context(void); | 404 | extern void omap3_control_save_context(void); |
398 | extern void omap3_control_restore_context(void); | 405 | extern void omap3_control_restore_context(void); |
399 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); | 406 | extern void omap3_ctrl_write_boot_mode(u8 bootmode); |
407 | extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); | ||
408 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); | ||
400 | extern void omap3630_ctrl_disable_rta(void); | 409 | extern void omap3630_ctrl_disable_rta(void); |
401 | extern int omap3_ctrl_save_padconf(void); | 410 | extern int omap3_ctrl_save_padconf(void); |
402 | #else | 411 | #else |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 207bc1c7759f..31344528eb54 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
@@ -36,8 +36,6 @@ | |||
36 | #include "control.h" | 36 | #include "control.h" |
37 | #include "common.h" | 37 | #include "common.h" |
38 | 38 | ||
39 | #ifdef CONFIG_CPU_IDLE | ||
40 | |||
41 | /* Mach specific information to be recorded in the C-state driver_data */ | 39 | /* Mach specific information to be recorded in the C-state driver_data */ |
42 | struct omap3_idle_statedata { | 40 | struct omap3_idle_statedata { |
43 | u32 mpu_state; | 41 | u32 mpu_state; |
@@ -379,9 +377,3 @@ int __init omap3_idle_init(void) | |||
379 | 377 | ||
380 | return 0; | 378 | return 0; |
381 | } | 379 | } |
382 | #else | ||
383 | int __init omap3_idle_init(void) | ||
384 | { | ||
385 | return 0; | ||
386 | } | ||
387 | #endif /* CONFIG_CPU_IDLE */ | ||
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index be1617ca84bd..02d15bbd4e35 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c | |||
@@ -22,8 +22,6 @@ | |||
22 | #include "pm.h" | 22 | #include "pm.h" |
23 | #include "prm.h" | 23 | #include "prm.h" |
24 | 24 | ||
25 | #ifdef CONFIG_CPU_IDLE | ||
26 | |||
27 | /* Machine specific information */ | 25 | /* Machine specific information */ |
28 | struct omap4_idle_statedata { | 26 | struct omap4_idle_statedata { |
29 | u32 cpu_state; | 27 | u32 cpu_state; |
@@ -199,9 +197,3 @@ int __init omap4_idle_init(void) | |||
199 | 197 | ||
200 | return 0; | 198 | return 0; |
201 | } | 199 | } |
202 | #else | ||
203 | int __init omap4_idle_init(void) | ||
204 | { | ||
205 | return 0; | ||
206 | } | ||
207 | #endif /* CONFIG_CPU_IDLE */ | ||
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 7b4b9327e543..527c0046064d 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
@@ -772,7 +772,7 @@ static int __init omap_init_wdt(void) | |||
772 | char *oh_name = "wd_timer2"; | 772 | char *oh_name = "wd_timer2"; |
773 | char *dev_name = "omap_wdt"; | 773 | char *dev_name = "omap_wdt"; |
774 | 774 | ||
775 | if (!cpu_class_is_omap2()) | 775 | if (!cpu_class_is_omap2() || of_have_populated_dt()) |
776 | return 0; | 776 | return 0; |
777 | 777 | ||
778 | oh = omap_hwmod_lookup(oh_name); | 778 | oh = omap_hwmod_lookup(oh_name); |
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 88ffa1e645cd..a636ebc16b39 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <asm/memblock.h> | 24 | #include <asm/memblock.h> |
25 | 25 | ||
26 | #include "control.h" | ||
26 | #include "cm2xxx_3xxx.h" | 27 | #include "cm2xxx_3xxx.h" |
27 | #include "prm2xxx_3xxx.h" | 28 | #include "prm2xxx_3xxx.h" |
28 | #ifdef CONFIG_BRIDGE_DVFS | 29 | #ifdef CONFIG_BRIDGE_DVFS |
@@ -46,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { | |||
46 | .dsp_cm_read = omap2_cm_read_mod_reg, | 47 | .dsp_cm_read = omap2_cm_read_mod_reg, |
47 | .dsp_cm_write = omap2_cm_write_mod_reg, | 48 | .dsp_cm_write = omap2_cm_write_mod_reg, |
48 | .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, | 49 | .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, |
50 | |||
51 | .set_bootaddr = omap_ctrl_write_dsp_boot_addr, | ||
52 | .set_bootmode = omap_ctrl_write_dsp_boot_mode, | ||
49 | }; | 53 | }; |
50 | 54 | ||
51 | static phys_addr_t omap_dsp_phys_mempool_base; | 55 | static phys_addr_t omap_dsp_phys_mempool_base; |
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h index f1e13d1ca5e7..95594495fcf6 100644 --- a/arch/arm/mach-omap2/include/mach/am35xx.h +++ b/arch/arm/mach-omap2/include/mach/am35xx.h | |||
@@ -36,6 +36,8 @@ | |||
36 | #define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) | 36 | #define AM35XX_EMAC_CNTRL_MOD_OFFSET (0x0) |
37 | #define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) | 37 | #define AM35XX_EMAC_CNTRL_RAM_OFFSET (0x20000) |
38 | #define AM35XX_EMAC_MDIO_OFFSET (0x30000) | 38 | #define AM35XX_EMAC_MDIO_OFFSET (0x30000) |
39 | #define AM35XX_IPSS_MDIO_BASE (AM35XX_IPSS_EMAC_BASE + \ | ||
40 | AM35XX_EMAC_MDIO_OFFSET) | ||
39 | #define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) | 41 | #define AM35XX_EMAC_CNTRL_RAM_SIZE (0x2000) |
40 | #define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ | 42 | #define AM35XX_EMAC_RAM_ADDR (AM3517_EMAC_BASE + \ |
41 | AM3517_EMAC_CNTRL_RAM_OFFSET) | 43 | AM3517_EMAC_CNTRL_RAM_OFFSET) |
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h index 2f7ac70a20d8..01970824e0e5 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h | |||
@@ -42,6 +42,7 @@ | |||
42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 | 42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 |
43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | 43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 |
44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 | 44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 |
45 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
45 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 | 46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 |
46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 | 47 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 |
47 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 | 48 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 |
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S index cdfc2a1f0e75..d7f844a99a7b 100644 --- a/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/arch/arm/mach-omap2/include/mach/debug-macro.S | |||
@@ -72,6 +72,8 @@ omap_uart_lsr: .word 0 | |||
72 | beq 82f @ configure UART2 | 72 | beq 82f @ configure UART2 |
73 | cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different | 73 | cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different |
74 | beq 83f @ configure UART3 | 74 | beq 83f @ configure UART3 |
75 | cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different | ||
76 | beq 84f @ configure UART1 | ||
75 | cmp \rp, #ZOOM_UART @ only on zoom2/3 | 77 | cmp \rp, #ZOOM_UART @ only on zoom2/3 |
76 | beq 95f @ configure ZOOM_UART | 78 | beq 95f @ configure ZOOM_UART |
77 | 79 | ||
@@ -100,7 +102,9 @@ omap_uart_lsr: .word 0 | |||
100 | b 98f | 102 | b 98f |
101 | 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) | 103 | 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) |
102 | b 98f | 104 | b 98f |
103 | 105 | 84: ldr \rp, =AM33XX_UART1_BASE | |
106 | and \rp, \rp, #0x00ffffff | ||
107 | b 97f | ||
104 | 95: ldr \rp, =ZOOM_UART_BASE | 108 | 95: ldr \rp, =ZOOM_UART_BASE |
105 | str \rp, [\tmp, #0] @ omap_uart_phys | 109 | str \rp, [\tmp, #0] @ omap_uart_phys |
106 | ldr \rp, =ZOOM_UART_VIRT | 110 | ldr \rp, =ZOOM_UART_VIRT |
@@ -109,6 +113,17 @@ omap_uart_lsr: .word 0 | |||
109 | str \rp, [\tmp, #8] @ omap_uart_lsr | 113 | str \rp, [\tmp, #8] @ omap_uart_lsr |
110 | b 10b | 114 | b 10b |
111 | 115 | ||
116 | /* AM33XX: Store both phys and virt address for the uart */ | ||
117 | 97: add \rp, \rp, #0x44000000 @ phys base | ||
118 | str \rp, [\tmp, #0] @ omap_uart_phys | ||
119 | sub \rp, \rp, #0x44000000 @ phys base | ||
120 | add \rp, \rp, #0xf9000000 @ virt base | ||
121 | str \rp, [\tmp, #4] @ omap_uart_virt | ||
122 | mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) | ||
123 | str \rp, [\tmp, #8] @ omap_uart_lsr | ||
124 | |||
125 | b 10b | ||
126 | |||
112 | /* Store both phys and virt address for the uart */ | 127 | /* Store both phys and virt address for the uart */ |
113 | 98: add \rp, \rp, #0x48000000 @ phys base | 128 | 98: add \rp, \rp, #0x48000000 @ phys base |
114 | str \rp, [\tmp, #0] @ omap_uart_phys | 129 | str \rp, [\tmp, #0] @ omap_uart_phys |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8d014ba04abc..cb6c11cd8df9 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -477,6 +477,19 @@ void __init ti81xx_init_late(void) | |||
477 | } | 477 | } |
478 | #endif | 478 | #endif |
479 | 479 | ||
480 | #ifdef CONFIG_SOC_AM33XX | ||
481 | void __init am33xx_init_early(void) | ||
482 | { | ||
483 | omap2_set_globals_am33xx(); | ||
484 | omap3xxx_check_revision(); | ||
485 | ti81xx_check_features(); | ||
486 | omap_common_init_early(); | ||
487 | am33xx_voltagedomains_init(); | ||
488 | am33xx_powerdomains_init(); | ||
489 | am33xx_clockdomains_init(); | ||
490 | } | ||
491 | #endif | ||
492 | |||
480 | #ifdef CONFIG_ARCH_OMAP4 | 493 | #ifdef CONFIG_ARCH_OMAP4 |
481 | void __init omap4430_init_early(void) | 494 | void __init omap4430_init_early(void) |
482 | { | 495 | { |
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c index 6038a8c84b74..a9c26b12cad2 100644 --- a/arch/arm/mach-omap2/irq.c +++ b/arch/arm/mach-omap2/irq.c | |||
@@ -262,7 +262,7 @@ int __init omap_intc_of_init(struct device_node *node, | |||
262 | struct device_node *parent) | 262 | struct device_node *parent) |
263 | { | 263 | { |
264 | struct resource res; | 264 | struct resource res; |
265 | u32 nr_irqs = 96; | 265 | u32 nr_irq = 96; |
266 | 266 | ||
267 | if (WARN_ON(!node)) | 267 | if (WARN_ON(!node)) |
268 | return -ENODEV; | 268 | return -ENODEV; |
@@ -272,15 +272,15 @@ int __init omap_intc_of_init(struct device_node *node, | |||
272 | return -EINVAL; | 272 | return -EINVAL; |
273 | } | 273 | } |
274 | 274 | ||
275 | if (of_property_read_u32(node, "ti,intc-size", &nr_irqs)) | 275 | if (of_property_read_u32(node, "ti,intc-size", &nr_irq)) |
276 | pr_warn("unable to get intc-size, default to %d\n", nr_irqs); | 276 | pr_warn("unable to get intc-size, default to %d\n", nr_irq); |
277 | 277 | ||
278 | omap_init_irq(res.start, nr_irqs, of_node_get(node)); | 278 | omap_init_irq(res.start, nr_irq, of_node_get(node)); |
279 | 279 | ||
280 | return 0; | 280 | return 0; |
281 | } | 281 | } |
282 | 282 | ||
283 | #ifdef CONFIG_ARCH_OMAP3 | 283 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) |
284 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; | 284 | static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; |
285 | 285 | ||
286 | void omap_intc_save_context(void) | 286 | void omap_intc_save_context(void) |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 19b8b6774862..6875be837d9f 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
@@ -83,8 +83,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
83 | l = mbox_read_reg(MAILBOX_REVISION); | 83 | l = mbox_read_reg(MAILBOX_REVISION); |
84 | pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | 84 | pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); |
85 | 85 | ||
86 | omap2_mbox_enable_irq(mbox, IRQ_RX); | ||
87 | |||
88 | return 0; | 86 | return 0; |
89 | } | 87 | } |
90 | 88 | ||
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index ac49384d0285..1be8bcb52e93 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c | |||
@@ -73,19 +73,17 @@ static struct iommu_device omap4_devices[] = { | |||
73 | .da_end = 0xFFFFF000, | 73 | .da_end = 0xFFFFF000, |
74 | }, | 74 | }, |
75 | }, | 75 | }, |
76 | #if defined(CONFIG_MPU_TESLA_IOMMU) | ||
77 | { | 76 | { |
78 | .base = OMAP4_MMU2_BASE, | 77 | .base = OMAP4_MMU2_BASE, |
79 | .irq = INT_44XX_DSP_MMU, | 78 | .irq = OMAP44XX_IRQ_TESLA_MMU, |
80 | .pdata = { | 79 | .pdata = { |
81 | .name = "tesla", | 80 | .name = "tesla", |
82 | .nr_tlb_entries = 32, | 81 | .nr_tlb_entries = 32, |
83 | .clk_name = "tesla_ick", | 82 | .clk_name = "dsp_fck", |
84 | .da_start = 0x0, | 83 | .da_start = 0x0, |
85 | .da_end = 0xFFFFF000, | 84 | .da_end = 0xFFFFF000, |
86 | }, | 85 | }, |
87 | }, | 86 | }, |
88 | #endif | ||
89 | }; | 87 | }; |
90 | #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) | 88 | #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices) |
91 | static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; | 89 | static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES]; |
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 773193670ea2..bdc1ec2edb4d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -166,6 +166,31 @@ | |||
166 | */ | 166 | */ |
167 | #define LINKS_PER_OCP_IF 2 | 167 | #define LINKS_PER_OCP_IF 2 |
168 | 168 | ||
169 | /** | ||
170 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | ||
171 | * @enable_module: function to enable a module (via MODULEMODE) | ||
172 | * @disable_module: function to disable a module (via MODULEMODE) | ||
173 | * | ||
174 | * XXX Eventually this functionality will be hidden inside the PRM/CM | ||
175 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | ||
176 | * conditionals in this code. | ||
177 | */ | ||
178 | struct omap_hwmod_soc_ops { | ||
179 | void (*enable_module)(struct omap_hwmod *oh); | ||
180 | int (*disable_module)(struct omap_hwmod *oh); | ||
181 | int (*wait_target_ready)(struct omap_hwmod *oh); | ||
182 | int (*assert_hardreset)(struct omap_hwmod *oh, | ||
183 | struct omap_hwmod_rst_info *ohri); | ||
184 | int (*deassert_hardreset)(struct omap_hwmod *oh, | ||
185 | struct omap_hwmod_rst_info *ohri); | ||
186 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | ||
187 | struct omap_hwmod_rst_info *ohri); | ||
188 | int (*init_clkdm)(struct omap_hwmod *oh); | ||
189 | }; | ||
190 | |||
191 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | ||
192 | static struct omap_hwmod_soc_ops soc_ops; | ||
193 | |||
169 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | 194 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
170 | static LIST_HEAD(omap_hwmod_list); | 195 | static LIST_HEAD(omap_hwmod_list); |
171 | 196 | ||
@@ -186,6 +211,9 @@ static struct omap_hwmod_link *linkspace; | |||
186 | */ | 211 | */ |
187 | static unsigned short free_ls, max_ls, ls_supp; | 212 | static unsigned short free_ls, max_ls, ls_supp; |
188 | 213 | ||
214 | /* inited: set to true once the hwmod code is initialized */ | ||
215 | static bool inited; | ||
216 | |||
189 | /* Private functions */ | 217 | /* Private functions */ |
190 | 218 | ||
191 | /** | 219 | /** |
@@ -771,23 +799,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh) | |||
771 | } | 799 | } |
772 | 800 | ||
773 | /** | 801 | /** |
774 | * _enable_module - enable CLKCTRL modulemode on OMAP4 | 802 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
775 | * @oh: struct omap_hwmod * | 803 | * @oh: struct omap_hwmod * |
776 | * | 804 | * |
777 | * Enables the PRCM module mode related to the hwmod @oh. | 805 | * Enables the PRCM module mode related to the hwmod @oh. |
778 | * No return value. | 806 | * No return value. |
779 | */ | 807 | */ |
780 | static void _enable_module(struct omap_hwmod *oh) | 808 | static void _omap4_enable_module(struct omap_hwmod *oh) |
781 | { | 809 | { |
782 | /* The module mode does not exist prior OMAP4 */ | ||
783 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | ||
784 | return; | ||
785 | |||
786 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | 810 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
787 | return; | 811 | return; |
788 | 812 | ||
789 | pr_debug("omap_hwmod: %s: _enable_module: %d\n", | 813 | pr_debug("omap_hwmod: %s: %s: %d\n", |
790 | oh->name, oh->prcm.omap4.modulemode); | 814 | oh->name, __func__, oh->prcm.omap4.modulemode); |
791 | 815 | ||
792 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | 816 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, |
793 | oh->clkdm->prcm_partition, | 817 | oh->clkdm->prcm_partition, |
@@ -807,10 +831,7 @@ static void _enable_module(struct omap_hwmod *oh) | |||
807 | */ | 831 | */ |
808 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | 832 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) |
809 | { | 833 | { |
810 | if (!cpu_is_omap44xx()) | 834 | if (!oh || !oh->clkdm) |
811 | return 0; | ||
812 | |||
813 | if (!oh) | ||
814 | return -EINVAL; | 835 | return -EINVAL; |
815 | 836 | ||
816 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | 837 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
@@ -1124,15 +1145,18 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap | |||
1124 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG | 1145 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
1125 | * @oh: struct omap_hwmod * | 1146 | * @oh: struct omap_hwmod * |
1126 | * | 1147 | * |
1127 | * If module is marked as SWSUP_SIDLE, force the module out of slave | 1148 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1128 | * idle; otherwise, configure it for smart-idle. If module is marked | 1149 | * by @oh is set to indicate to the PRCM that the IP block is active. |
1129 | * as SWSUP_MSUSPEND, force the module out of master standby; | 1150 | * Usually this means placing the module into smart-idle mode and |
1130 | * otherwise, configure it for smart-standby. No return value. | 1151 | * smart-standby, but if there is a bug in the automatic idle handling |
1152 | * for the IP block, it may need to be placed into the force-idle or | ||
1153 | * no-idle variants of these modes. No return value. | ||
1131 | */ | 1154 | */ |
1132 | static void _enable_sysc(struct omap_hwmod *oh) | 1155 | static void _enable_sysc(struct omap_hwmod *oh) |
1133 | { | 1156 | { |
1134 | u8 idlemode, sf; | 1157 | u8 idlemode, sf; |
1135 | u32 v; | 1158 | u32 v; |
1159 | bool clkdm_act; | ||
1136 | 1160 | ||
1137 | if (!oh->class->sysc) | 1161 | if (!oh->class->sysc) |
1138 | return; | 1162 | return; |
@@ -1141,8 +1165,16 @@ static void _enable_sysc(struct omap_hwmod *oh) | |||
1141 | sf = oh->class->sysc->sysc_flags; | 1165 | sf = oh->class->sysc->sysc_flags; |
1142 | 1166 | ||
1143 | if (sf & SYSC_HAS_SIDLEMODE) { | 1167 | if (sf & SYSC_HAS_SIDLEMODE) { |
1144 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 1168 | clkdm_act = ((oh->clkdm && |
1145 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | 1169 | oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || |
1170 | (oh->_clk && oh->_clk->clkdm && | ||
1171 | oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); | ||
1172 | if (clkdm_act && !(oh->class->sysc->idlemodes & | ||
1173 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | ||
1174 | idlemode = HWMOD_IDLEMODE_FORCE; | ||
1175 | else | ||
1176 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | ||
1177 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | ||
1146 | _set_slave_idlemode(oh, idlemode, &v); | 1178 | _set_slave_idlemode(oh, idlemode, &v); |
1147 | } | 1179 | } |
1148 | 1180 | ||
@@ -1208,8 +1240,13 @@ static void _idle_sysc(struct omap_hwmod *oh) | |||
1208 | sf = oh->class->sysc->sysc_flags; | 1240 | sf = oh->class->sysc->sysc_flags; |
1209 | 1241 | ||
1210 | if (sf & SYSC_HAS_SIDLEMODE) { | 1242 | if (sf & SYSC_HAS_SIDLEMODE) { |
1211 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | 1243 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
1212 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | 1244 | if (oh->flags & HWMOD_SWSUP_SIDLE || |
1245 | !(oh->class->sysc->idlemodes & | ||
1246 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | ||
1247 | idlemode = HWMOD_IDLEMODE_FORCE; | ||
1248 | else | ||
1249 | idlemode = HWMOD_IDLEMODE_SMART; | ||
1213 | _set_slave_idlemode(oh, idlemode, &v); | 1250 | _set_slave_idlemode(oh, idlemode, &v); |
1214 | } | 1251 | } |
1215 | 1252 | ||
@@ -1285,24 +1322,20 @@ static struct omap_hwmod *_lookup(const char *name) | |||
1285 | 1322 | ||
1286 | return oh; | 1323 | return oh; |
1287 | } | 1324 | } |
1325 | |||
1288 | /** | 1326 | /** |
1289 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | 1327 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod |
1290 | * @oh: struct omap_hwmod * | 1328 | * @oh: struct omap_hwmod * |
1291 | * | 1329 | * |
1292 | * Convert a clockdomain name stored in a struct omap_hwmod into a | 1330 | * Convert a clockdomain name stored in a struct omap_hwmod into a |
1293 | * clockdomain pointer, and save it into the struct omap_hwmod. | 1331 | * clockdomain pointer, and save it into the struct omap_hwmod. |
1294 | * return -EINVAL if clkdm_name does not exist or if the lookup failed. | 1332 | * Return -EINVAL if the clkdm_name lookup failed. |
1295 | */ | 1333 | */ |
1296 | static int _init_clkdm(struct omap_hwmod *oh) | 1334 | static int _init_clkdm(struct omap_hwmod *oh) |
1297 | { | 1335 | { |
1298 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 1336 | if (!oh->clkdm_name) |
1299 | return 0; | 1337 | return 0; |
1300 | 1338 | ||
1301 | if (!oh->clkdm_name) { | ||
1302 | pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name); | ||
1303 | return -EINVAL; | ||
1304 | } | ||
1305 | |||
1306 | oh->clkdm = clkdm_lookup(oh->clkdm_name); | 1339 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1307 | if (!oh->clkdm) { | 1340 | if (!oh->clkdm) { |
1308 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | 1341 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", |
@@ -1338,7 +1371,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) | |||
1338 | ret |= _init_main_clk(oh); | 1371 | ret |= _init_main_clk(oh); |
1339 | ret |= _init_interface_clks(oh); | 1372 | ret |= _init_interface_clks(oh); |
1340 | ret |= _init_opt_clks(oh); | 1373 | ret |= _init_opt_clks(oh); |
1341 | ret |= _init_clkdm(oh); | 1374 | if (soc_ops.init_clkdm) |
1375 | ret |= soc_ops.init_clkdm(oh); | ||
1342 | 1376 | ||
1343 | if (!ret) | 1377 | if (!ret) |
1344 | oh->_state = _HWMOD_STATE_CLKS_INITED; | 1378 | oh->_state = _HWMOD_STATE_CLKS_INITED; |
@@ -1349,53 +1383,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data) | |||
1349 | } | 1383 | } |
1350 | 1384 | ||
1351 | /** | 1385 | /** |
1352 | * _wait_target_ready - wait for a module to leave slave idle | ||
1353 | * @oh: struct omap_hwmod * | ||
1354 | * | ||
1355 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
1356 | * does not have an IDLEST bit or if the module successfully leaves | ||
1357 | * slave idle; otherwise, pass along the return value of the | ||
1358 | * appropriate *_cm*_wait_module_ready() function. | ||
1359 | */ | ||
1360 | static int _wait_target_ready(struct omap_hwmod *oh) | ||
1361 | { | ||
1362 | struct omap_hwmod_ocp_if *os; | ||
1363 | int ret; | ||
1364 | |||
1365 | if (!oh) | ||
1366 | return -EINVAL; | ||
1367 | |||
1368 | if (oh->flags & HWMOD_NO_IDLEST) | ||
1369 | return 0; | ||
1370 | |||
1371 | os = _find_mpu_rt_port(oh); | ||
1372 | if (!os) | ||
1373 | return 0; | ||
1374 | |||
1375 | /* XXX check module SIDLEMODE */ | ||
1376 | |||
1377 | /* XXX check clock enable states */ | ||
1378 | |||
1379 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
1380 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | ||
1381 | oh->prcm.omap2.idlest_reg_id, | ||
1382 | oh->prcm.omap2.idlest_idle_bit); | ||
1383 | } else if (cpu_is_omap44xx()) { | ||
1384 | if (!oh->clkdm) | ||
1385 | return -EINVAL; | ||
1386 | |||
1387 | ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | ||
1388 | oh->clkdm->cm_inst, | ||
1389 | oh->clkdm->clkdm_offs, | ||
1390 | oh->prcm.omap4.clkctrl_offs); | ||
1391 | } else { | ||
1392 | BUG(); | ||
1393 | }; | ||
1394 | |||
1395 | return ret; | ||
1396 | } | ||
1397 | |||
1398 | /** | ||
1399 | * _lookup_hardreset - fill register bit info for this hwmod/reset line | 1386 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
1400 | * @oh: struct omap_hwmod * | 1387 | * @oh: struct omap_hwmod * |
1401 | * @name: name of the reset line in the context of this hwmod | 1388 | * @name: name of the reset line in the context of this hwmod |
@@ -1431,32 +1418,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, | |||
1431 | * @oh: struct omap_hwmod * | 1418 | * @oh: struct omap_hwmod * |
1432 | * @name: name of the reset line to lookup and assert | 1419 | * @name: name of the reset line to lookup and assert |
1433 | * | 1420 | * |
1434 | * Some IP like dsp, ipu or iva contain processor that require | 1421 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1435 | * an HW reset line to be assert / deassert in order to enable fully | 1422 | * reset line to be assert / deassert in order to enable fully the IP. |
1436 | * the IP. | 1423 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of |
1424 | * asserting the hardreset line on the currently-booted SoC, or passes | ||
1425 | * along the return value from _lookup_hardreset() or the SoC's | ||
1426 | * assert_hardreset code. | ||
1437 | */ | 1427 | */ |
1438 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | 1428 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) |
1439 | { | 1429 | { |
1440 | struct omap_hwmod_rst_info ohri; | 1430 | struct omap_hwmod_rst_info ohri; |
1441 | u8 ret; | 1431 | u8 ret = -EINVAL; |
1442 | 1432 | ||
1443 | if (!oh) | 1433 | if (!oh) |
1444 | return -EINVAL; | 1434 | return -EINVAL; |
1445 | 1435 | ||
1436 | if (!soc_ops.assert_hardreset) | ||
1437 | return -ENOSYS; | ||
1438 | |||
1446 | ret = _lookup_hardreset(oh, name, &ohri); | 1439 | ret = _lookup_hardreset(oh, name, &ohri); |
1447 | if (IS_ERR_VALUE(ret)) | 1440 | if (IS_ERR_VALUE(ret)) |
1448 | return ret; | 1441 | return ret; |
1449 | 1442 | ||
1450 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 1443 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1451 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | 1444 | |
1452 | ohri.rst_shift); | 1445 | return ret; |
1453 | else if (cpu_is_omap44xx()) | ||
1454 | return omap4_prminst_assert_hardreset(ohri.rst_shift, | ||
1455 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
1456 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
1457 | oh->prcm.omap4.rstctrl_offs); | ||
1458 | else | ||
1459 | return -EINVAL; | ||
1460 | } | 1446 | } |
1461 | 1447 | ||
1462 | /** | 1448 | /** |
@@ -1465,38 +1451,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |||
1465 | * @oh: struct omap_hwmod * | 1451 | * @oh: struct omap_hwmod * |
1466 | * @name: name of the reset line to look up and deassert | 1452 | * @name: name of the reset line to look up and deassert |
1467 | * | 1453 | * |
1468 | * Some IP like dsp, ipu or iva contain processor that require | 1454 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1469 | * an HW reset line to be assert / deassert in order to enable fully | 1455 | * reset line to be assert / deassert in order to enable fully the IP. |
1470 | * the IP. | 1456 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of |
1457 | * deasserting the hardreset line on the currently-booted SoC, or passes | ||
1458 | * along the return value from _lookup_hardreset() or the SoC's | ||
1459 | * deassert_hardreset code. | ||
1471 | */ | 1460 | */ |
1472 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | 1461 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) |
1473 | { | 1462 | { |
1474 | struct omap_hwmod_rst_info ohri; | 1463 | struct omap_hwmod_rst_info ohri; |
1475 | int ret; | 1464 | int ret = -EINVAL; |
1476 | 1465 | ||
1477 | if (!oh) | 1466 | if (!oh) |
1478 | return -EINVAL; | 1467 | return -EINVAL; |
1479 | 1468 | ||
1469 | if (!soc_ops.deassert_hardreset) | ||
1470 | return -ENOSYS; | ||
1471 | |||
1480 | ret = _lookup_hardreset(oh, name, &ohri); | 1472 | ret = _lookup_hardreset(oh, name, &ohri); |
1481 | if (IS_ERR_VALUE(ret)) | 1473 | if (IS_ERR_VALUE(ret)) |
1482 | return ret; | 1474 | return ret; |
1483 | 1475 | ||
1484 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 1476 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
1485 | ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | ||
1486 | ohri.rst_shift, | ||
1487 | ohri.st_shift); | ||
1488 | } else if (cpu_is_omap44xx()) { | ||
1489 | if (ohri.st_shift) | ||
1490 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | ||
1491 | oh->name, name); | ||
1492 | ret = omap4_prminst_deassert_hardreset(ohri.rst_shift, | ||
1493 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
1494 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
1495 | oh->prcm.omap4.rstctrl_offs); | ||
1496 | } else { | ||
1497 | return -EINVAL; | ||
1498 | } | ||
1499 | |||
1500 | if (ret == -EBUSY) | 1477 | if (ret == -EBUSY) |
1501 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); | 1478 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1502 | 1479 | ||
@@ -1509,31 +1486,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |||
1509 | * @oh: struct omap_hwmod * | 1486 | * @oh: struct omap_hwmod * |
1510 | * @name: name of the reset line to look up and read | 1487 | * @name: name of the reset line to look up and read |
1511 | * | 1488 | * |
1512 | * Return the state of the reset line. | 1489 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1490 | * null, -ENOSYS if we have no way of reading the hardreset line | ||
1491 | * status on the currently-booted SoC, or passes along the return | ||
1492 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | ||
1493 | * code. | ||
1513 | */ | 1494 | */ |
1514 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | 1495 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) |
1515 | { | 1496 | { |
1516 | struct omap_hwmod_rst_info ohri; | 1497 | struct omap_hwmod_rst_info ohri; |
1517 | u8 ret; | 1498 | u8 ret = -EINVAL; |
1518 | 1499 | ||
1519 | if (!oh) | 1500 | if (!oh) |
1520 | return -EINVAL; | 1501 | return -EINVAL; |
1521 | 1502 | ||
1503 | if (!soc_ops.is_hardreset_asserted) | ||
1504 | return -ENOSYS; | ||
1505 | |||
1522 | ret = _lookup_hardreset(oh, name, &ohri); | 1506 | ret = _lookup_hardreset(oh, name, &ohri); |
1523 | if (IS_ERR_VALUE(ret)) | 1507 | if (IS_ERR_VALUE(ret)) |
1524 | return ret; | 1508 | return ret; |
1525 | 1509 | ||
1526 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | 1510 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
1527 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | ||
1528 | ohri.st_shift); | ||
1529 | } else if (cpu_is_omap44xx()) { | ||
1530 | return omap4_prminst_is_hardreset_asserted(ohri.rst_shift, | ||
1531 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
1532 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
1533 | oh->prcm.omap4.rstctrl_offs); | ||
1534 | } else { | ||
1535 | return -EINVAL; | ||
1536 | } | ||
1537 | } | 1511 | } |
1538 | 1512 | ||
1539 | /** | 1513 | /** |
@@ -1571,10 +1545,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh) | |||
1571 | { | 1545 | { |
1572 | int v; | 1546 | int v; |
1573 | 1547 | ||
1574 | /* The module mode does not exist prior OMAP4 */ | ||
1575 | if (!cpu_is_omap44xx()) | ||
1576 | return -EINVAL; | ||
1577 | |||
1578 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | 1548 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1579 | return -EINVAL; | 1549 | return -EINVAL; |
1580 | 1550 | ||
@@ -1814,9 +1784,11 @@ static int _enable(struct omap_hwmod *oh) | |||
1814 | } | 1784 | } |
1815 | 1785 | ||
1816 | _enable_clocks(oh); | 1786 | _enable_clocks(oh); |
1817 | _enable_module(oh); | 1787 | if (soc_ops.enable_module) |
1788 | soc_ops.enable_module(oh); | ||
1818 | 1789 | ||
1819 | r = _wait_target_ready(oh); | 1790 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
1791 | -EINVAL; | ||
1820 | if (!r) { | 1792 | if (!r) { |
1821 | /* | 1793 | /* |
1822 | * Set the clockdomain to HW_AUTO only if the target is ready, | 1794 | * Set the clockdomain to HW_AUTO only if the target is ready, |
@@ -1870,7 +1842,8 @@ static int _idle(struct omap_hwmod *oh) | |||
1870 | _idle_sysc(oh); | 1842 | _idle_sysc(oh); |
1871 | _del_initiator_dep(oh, mpu_oh); | 1843 | _del_initiator_dep(oh, mpu_oh); |
1872 | 1844 | ||
1873 | _omap4_disable_module(oh); | 1845 | if (soc_ops.disable_module) |
1846 | soc_ops.disable_module(oh); | ||
1874 | 1847 | ||
1875 | /* | 1848 | /* |
1876 | * The module must be in idle mode before disabling any parents | 1849 | * The module must be in idle mode before disabling any parents |
@@ -1975,7 +1948,8 @@ static int _shutdown(struct omap_hwmod *oh) | |||
1975 | if (oh->_state == _HWMOD_STATE_ENABLED) { | 1948 | if (oh->_state == _HWMOD_STATE_ENABLED) { |
1976 | _del_initiator_dep(oh, mpu_oh); | 1949 | _del_initiator_dep(oh, mpu_oh); |
1977 | /* XXX what about the other system initiators here? dma, dsp */ | 1950 | /* XXX what about the other system initiators here? dma, dsp */ |
1978 | _omap4_disable_module(oh); | 1951 | if (soc_ops.disable_module) |
1952 | soc_ops.disable_module(oh); | ||
1979 | _disable_clocks(oh); | 1953 | _disable_clocks(oh); |
1980 | if (oh->clkdm) | 1954 | if (oh->clkdm) |
1981 | clkdm_hwmod_disable(oh->clkdm, oh); | 1955 | clkdm_hwmod_disable(oh->clkdm, oh); |
@@ -2431,6 +2405,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |||
2431 | return 0; | 2405 | return 0; |
2432 | } | 2406 | } |
2433 | 2407 | ||
2408 | /* Static functions intended only for use in soc_ops field function pointers */ | ||
2409 | |||
2410 | /** | ||
2411 | * _omap2_wait_target_ready - wait for a module to leave slave idle | ||
2412 | * @oh: struct omap_hwmod * | ||
2413 | * | ||
2414 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
2415 | * does not have an IDLEST bit or if the module successfully leaves | ||
2416 | * slave idle; otherwise, pass along the return value of the | ||
2417 | * appropriate *_cm*_wait_module_ready() function. | ||
2418 | */ | ||
2419 | static int _omap2_wait_target_ready(struct omap_hwmod *oh) | ||
2420 | { | ||
2421 | if (!oh) | ||
2422 | return -EINVAL; | ||
2423 | |||
2424 | if (oh->flags & HWMOD_NO_IDLEST) | ||
2425 | return 0; | ||
2426 | |||
2427 | if (!_find_mpu_rt_port(oh)) | ||
2428 | return 0; | ||
2429 | |||
2430 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | ||
2431 | |||
2432 | return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | ||
2433 | oh->prcm.omap2.idlest_reg_id, | ||
2434 | oh->prcm.omap2.idlest_idle_bit); | ||
2435 | } | ||
2436 | |||
2437 | /** | ||
2438 | * _omap4_wait_target_ready - wait for a module to leave slave idle | ||
2439 | * @oh: struct omap_hwmod * | ||
2440 | * | ||
2441 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | ||
2442 | * does not have an IDLEST bit or if the module successfully leaves | ||
2443 | * slave idle; otherwise, pass along the return value of the | ||
2444 | * appropriate *_cm*_wait_module_ready() function. | ||
2445 | */ | ||
2446 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | ||
2447 | { | ||
2448 | if (!oh || !oh->clkdm) | ||
2449 | return -EINVAL; | ||
2450 | |||
2451 | if (oh->flags & HWMOD_NO_IDLEST) | ||
2452 | return 0; | ||
2453 | |||
2454 | if (!_find_mpu_rt_port(oh)) | ||
2455 | return 0; | ||
2456 | |||
2457 | /* XXX check module SIDLEMODE, hardreset status */ | ||
2458 | |||
2459 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | ||
2460 | oh->clkdm->cm_inst, | ||
2461 | oh->clkdm->clkdm_offs, | ||
2462 | oh->prcm.omap4.clkctrl_offs); | ||
2463 | } | ||
2464 | |||
2465 | /** | ||
2466 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | ||
2467 | * @oh: struct omap_hwmod * to assert hardreset | ||
2468 | * @ohri: hardreset line data | ||
2469 | * | ||
2470 | * Call omap2_prm_assert_hardreset() with parameters extracted from | ||
2471 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | ||
2472 | * use as an soc_ops function pointer. Passes along the return value | ||
2473 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | ||
2474 | * for removal when the PRM code is moved into drivers/. | ||
2475 | */ | ||
2476 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | ||
2477 | struct omap_hwmod_rst_info *ohri) | ||
2478 | { | ||
2479 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | ||
2480 | ohri->rst_shift); | ||
2481 | } | ||
2482 | |||
2483 | /** | ||
2484 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | ||
2485 | * @oh: struct omap_hwmod * to deassert hardreset | ||
2486 | * @ohri: hardreset line data | ||
2487 | * | ||
2488 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | ||
2489 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | ||
2490 | * use as an soc_ops function pointer. Passes along the return value | ||
2491 | * from omap2_prm_deassert_hardreset(). XXX This function is | ||
2492 | * scheduled for removal when the PRM code is moved into drivers/. | ||
2493 | */ | ||
2494 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | ||
2495 | struct omap_hwmod_rst_info *ohri) | ||
2496 | { | ||
2497 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | ||
2498 | ohri->rst_shift, | ||
2499 | ohri->st_shift); | ||
2500 | } | ||
2501 | |||
2502 | /** | ||
2503 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | ||
2504 | * @oh: struct omap_hwmod * to test hardreset | ||
2505 | * @ohri: hardreset line data | ||
2506 | * | ||
2507 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | ||
2508 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
2509 | * intended for use as an soc_ops function pointer. Passes along the | ||
2510 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | ||
2511 | * function is scheduled for removal when the PRM code is moved into | ||
2512 | * drivers/. | ||
2513 | */ | ||
2514 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | ||
2515 | struct omap_hwmod_rst_info *ohri) | ||
2516 | { | ||
2517 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | ||
2518 | ohri->st_shift); | ||
2519 | } | ||
2520 | |||
2521 | /** | ||
2522 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | ||
2523 | * @oh: struct omap_hwmod * to assert hardreset | ||
2524 | * @ohri: hardreset line data | ||
2525 | * | ||
2526 | * Call omap4_prminst_assert_hardreset() with parameters extracted | ||
2527 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
2528 | * intended for use as an soc_ops function pointer. Passes along the | ||
2529 | * return value from omap4_prminst_assert_hardreset(). XXX This | ||
2530 | * function is scheduled for removal when the PRM code is moved into | ||
2531 | * drivers/. | ||
2532 | */ | ||
2533 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | ||
2534 | struct omap_hwmod_rst_info *ohri) | ||
2535 | { | ||
2536 | if (!oh->clkdm) | ||
2537 | return -EINVAL; | ||
2538 | |||
2539 | return omap4_prminst_assert_hardreset(ohri->rst_shift, | ||
2540 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
2541 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
2542 | oh->prcm.omap4.rstctrl_offs); | ||
2543 | } | ||
2544 | |||
2545 | /** | ||
2546 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | ||
2547 | * @oh: struct omap_hwmod * to deassert hardreset | ||
2548 | * @ohri: hardreset line data | ||
2549 | * | ||
2550 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | ||
2551 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
2552 | * intended for use as an soc_ops function pointer. Passes along the | ||
2553 | * return value from omap4_prminst_deassert_hardreset(). XXX This | ||
2554 | * function is scheduled for removal when the PRM code is moved into | ||
2555 | * drivers/. | ||
2556 | */ | ||
2557 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | ||
2558 | struct omap_hwmod_rst_info *ohri) | ||
2559 | { | ||
2560 | if (!oh->clkdm) | ||
2561 | return -EINVAL; | ||
2562 | |||
2563 | if (ohri->st_shift) | ||
2564 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | ||
2565 | oh->name, ohri->name); | ||
2566 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | ||
2567 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
2568 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
2569 | oh->prcm.omap4.rstctrl_offs); | ||
2570 | } | ||
2571 | |||
2572 | /** | ||
2573 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | ||
2574 | * @oh: struct omap_hwmod * to test hardreset | ||
2575 | * @ohri: hardreset line data | ||
2576 | * | ||
2577 | * Call omap4_prminst_is_hardreset_asserted() with parameters | ||
2578 | * extracted from the hwmod @oh and the hardreset line data @ohri. | ||
2579 | * Only intended for use as an soc_ops function pointer. Passes along | ||
2580 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | ||
2581 | * This function is scheduled for removal when the PRM code is moved | ||
2582 | * into drivers/. | ||
2583 | */ | ||
2584 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | ||
2585 | struct omap_hwmod_rst_info *ohri) | ||
2586 | { | ||
2587 | if (!oh->clkdm) | ||
2588 | return -EINVAL; | ||
2589 | |||
2590 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, | ||
2591 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
2592 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
2593 | oh->prcm.omap4.rstctrl_offs); | ||
2594 | } | ||
2595 | |||
2434 | /* Public functions */ | 2596 | /* Public functions */ |
2435 | 2597 | ||
2436 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | 2598 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) |
@@ -2563,12 +2725,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), | |||
2563 | * | 2725 | * |
2564 | * Intended to be called early in boot before the clock framework is | 2726 | * Intended to be called early in boot before the clock framework is |
2565 | * initialized. If @ois is not null, will register all omap_hwmods | 2727 | * initialized. If @ois is not null, will register all omap_hwmods |
2566 | * listed in @ois that are valid for this chip. Returns 0. | 2728 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
2729 | * omap_hwmod_init() hasn't been called before calling this function, | ||
2730 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | ||
2731 | * success. | ||
2567 | */ | 2732 | */ |
2568 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | 2733 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) |
2569 | { | 2734 | { |
2570 | int r, i; | 2735 | int r, i; |
2571 | 2736 | ||
2737 | if (!inited) | ||
2738 | return -EINVAL; | ||
2739 | |||
2572 | if (!ois) | 2740 | if (!ois) |
2573 | return 0; | 2741 | return 0; |
2574 | 2742 | ||
@@ -3401,3 +3569,32 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |||
3401 | 3569 | ||
3402 | return 0; | 3570 | return 0; |
3403 | } | 3571 | } |
3572 | |||
3573 | /** | ||
3574 | * omap_hwmod_init - initialize the hwmod code | ||
3575 | * | ||
3576 | * Sets up some function pointers needed by the hwmod code to operate on the | ||
3577 | * currently-booted SoC. Intended to be called once during kernel init | ||
3578 | * before any hwmods are registered. No return value. | ||
3579 | */ | ||
3580 | void __init omap_hwmod_init(void) | ||
3581 | { | ||
3582 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
3583 | soc_ops.wait_target_ready = _omap2_wait_target_ready; | ||
3584 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | ||
3585 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | ||
3586 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | ||
3587 | } else if (cpu_is_omap44xx()) { | ||
3588 | soc_ops.enable_module = _omap4_enable_module; | ||
3589 | soc_ops.disable_module = _omap4_disable_module; | ||
3590 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | ||
3591 | soc_ops.assert_hardreset = _omap4_assert_hardreset; | ||
3592 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | ||
3593 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | ||
3594 | soc_ops.init_clkdm = _init_clkdm; | ||
3595 | } else { | ||
3596 | WARN(1, "omap_hwmod: unknown SoC type\n"); | ||
3597 | } | ||
3598 | |||
3599 | inited = true; | ||
3600 | } | ||
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index a7640d1b215e..50cfab61b0e2 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c | |||
@@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { | |||
192 | .name = "mcbsp", | 192 | .name = "mcbsp", |
193 | }; | 193 | }; |
194 | 194 | ||
195 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | ||
196 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
197 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | ||
198 | }; | ||
199 | |||
195 | /* mcbsp1 */ | 200 | /* mcbsp1 */ |
196 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { | 201 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
197 | { .name = "tx", .irq = 59 }, | 202 | { .name = "tx", .irq = 59 }, |
@@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = { | |||
214 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | 219 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
215 | }, | 220 | }, |
216 | }, | 221 | }, |
222 | .opt_clks = mcbsp_opt_clks, | ||
223 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
217 | }; | 224 | }; |
218 | 225 | ||
219 | /* mcbsp2 */ | 226 | /* mcbsp2 */ |
@@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = { | |||
238 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | 245 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
239 | }, | 246 | }, |
240 | }, | 247 | }, |
248 | .opt_clks = mcbsp_opt_clks, | ||
249 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
241 | }; | 250 | }; |
242 | 251 | ||
243 | static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { | 252 | static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = { |
@@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { | |||
585 | 594 | ||
586 | int __init omap2420_hwmod_init(void) | 595 | int __init omap2420_hwmod_init(void) |
587 | { | 596 | { |
597 | omap_hwmod_init(); | ||
588 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); | 598 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
589 | } | 599 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 4d7264981230..58b5bc196d32 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c | |||
@@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { | |||
296 | .rev = MCBSP_CONFIG_TYPE2, | 296 | .rev = MCBSP_CONFIG_TYPE2, |
297 | }; | 297 | }; |
298 | 298 | ||
299 | static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { | ||
300 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
301 | { .role = "prcm_fck", .clk = "func_96m_ck" }, | ||
302 | }; | ||
303 | |||
299 | /* mcbsp1 */ | 304 | /* mcbsp1 */ |
300 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { | 305 | static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = { |
301 | { .name = "tx", .irq = 59 }, | 306 | { .name = "tx", .irq = 59 }, |
@@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = { | |||
320 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, | 325 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
321 | }, | 326 | }, |
322 | }, | 327 | }, |
328 | .opt_clks = mcbsp_opt_clks, | ||
329 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
323 | }; | 330 | }; |
324 | 331 | ||
325 | /* mcbsp2 */ | 332 | /* mcbsp2 */ |
@@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = { | |||
345 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, | 352 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
346 | }, | 353 | }, |
347 | }, | 354 | }, |
355 | .opt_clks = mcbsp_opt_clks, | ||
356 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
348 | }; | 357 | }; |
349 | 358 | ||
350 | /* mcbsp3 */ | 359 | /* mcbsp3 */ |
@@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = { | |||
370 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, | 379 | .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, |
371 | }, | 380 | }, |
372 | }, | 381 | }, |
382 | .opt_clks = mcbsp_opt_clks, | ||
383 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
373 | }; | 384 | }; |
374 | 385 | ||
375 | /* mcbsp4 */ | 386 | /* mcbsp4 */ |
@@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = { | |||
401 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, | 412 | .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, |
402 | }, | 413 | }, |
403 | }, | 414 | }, |
415 | .opt_clks = mcbsp_opt_clks, | ||
416 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
404 | }; | 417 | }; |
405 | 418 | ||
406 | /* mcbsp5 */ | 419 | /* mcbsp5 */ |
@@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = { | |||
432 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, | 445 | .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, |
433 | }, | 446 | }, |
434 | }, | 447 | }, |
448 | .opt_clks = mcbsp_opt_clks, | ||
449 | .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), | ||
435 | }; | 450 | }; |
436 | 451 | ||
437 | /* MMC/SD/SDIO common */ | 452 | /* MMC/SD/SDIO common */ |
@@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { | |||
938 | 953 | ||
939 | int __init omap2430_hwmod_init(void) | 954 | int __init omap2430_hwmod_init(void) |
940 | { | 955 | { |
956 | omap_hwmod_init(); | ||
941 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); | 957 | return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
942 | } | 958 | } |
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index 0ea53bcc7d18..cdb9637aab19 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | |||
@@ -519,11 +519,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = { | |||
519 | 519 | ||
520 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { | 520 | static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = { |
521 | { .irq = INT_35XX_UART4_IRQ, }, | 521 | { .irq = INT_35XX_UART4_IRQ, }, |
522 | { .irq = -1 } | ||
522 | }; | 523 | }; |
523 | 524 | ||
524 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { | 525 | static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = { |
525 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, | 526 | { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, }, |
526 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, | 527 | { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, }, |
528 | { .dma_req = -1 } | ||
529 | }; | ||
530 | |||
531 | /* | ||
532 | * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or | ||
533 | * uart2_fck being enabled. So we add uart1_fck as an optional clock, | ||
534 | * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET. This really | ||
535 | * should not be needed. The functional clock structure of the AM35xx | ||
536 | * UART4 is extremely unclear and opaque; it is unclear what the role | ||
537 | * of uart1/2_fck is for the UART4. Any clarification from either | ||
538 | * empirical testing or the AM3505/3517 hardware designers would be | ||
539 | * most welcome. | ||
540 | */ | ||
541 | static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = { | ||
542 | { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, | ||
527 | }; | 543 | }; |
528 | 544 | ||
529 | static struct omap_hwmod am35xx_uart4_hwmod = { | 545 | static struct omap_hwmod am35xx_uart4_hwmod = { |
@@ -535,11 +551,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = { | |||
535 | .omap2 = { | 551 | .omap2 = { |
536 | .module_offs = CORE_MOD, | 552 | .module_offs = CORE_MOD, |
537 | .prcm_reg_id = 1, | 553 | .prcm_reg_id = 1, |
538 | .module_bit = OMAP3430_EN_UART4_SHIFT, | 554 | .module_bit = AM35XX_EN_UART4_SHIFT, |
539 | .idlest_reg_id = 1, | 555 | .idlest_reg_id = 1, |
540 | .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT, | 556 | .idlest_idle_bit = AM35XX_ST_UART4_SHIFT, |
541 | }, | 557 | }, |
542 | }, | 558 | }, |
559 | .opt_clks = am35xx_uart4_opt_clks, | ||
560 | .opt_clks_cnt = ARRAY_SIZE(am35xx_uart4_opt_clks), | ||
561 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, | ||
543 | .class = &omap2_uart_class, | 562 | .class = &omap2_uart_class, |
544 | }; | 563 | }; |
545 | 564 | ||
@@ -1066,6 +1085,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = { | |||
1066 | .rev = MCBSP_CONFIG_TYPE3, | 1085 | .rev = MCBSP_CONFIG_TYPE3, |
1067 | }; | 1086 | }; |
1068 | 1087 | ||
1088 | /* McBSP functional clock mapping */ | ||
1089 | static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = { | ||
1090 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
1091 | { .role = "prcm_fck", .clk = "core_96m_fck" }, | ||
1092 | }; | ||
1093 | |||
1094 | static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = { | ||
1095 | { .role = "pad_fck", .clk = "mcbsp_clks" }, | ||
1096 | { .role = "prcm_fck", .clk = "per_96m_fck" }, | ||
1097 | }; | ||
1098 | |||
1069 | /* mcbsp1 */ | 1099 | /* mcbsp1 */ |
1070 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { | 1100 | static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = { |
1071 | { .name = "common", .irq = 16 }, | 1101 | { .name = "common", .irq = 16 }, |
@@ -1089,6 +1119,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = { | |||
1089 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, | 1119 | .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT, |
1090 | }, | 1120 | }, |
1091 | }, | 1121 | }, |
1122 | .opt_clks = mcbsp15_opt_clks, | ||
1123 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | ||
1092 | }; | 1124 | }; |
1093 | 1125 | ||
1094 | /* mcbsp2 */ | 1126 | /* mcbsp2 */ |
@@ -1118,6 +1150,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = { | |||
1118 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, | 1150 | .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT, |
1119 | }, | 1151 | }, |
1120 | }, | 1152 | }, |
1153 | .opt_clks = mcbsp234_opt_clks, | ||
1154 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
1121 | .dev_attr = &omap34xx_mcbsp2_dev_attr, | 1155 | .dev_attr = &omap34xx_mcbsp2_dev_attr, |
1122 | }; | 1156 | }; |
1123 | 1157 | ||
@@ -1148,6 +1182,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = { | |||
1148 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, | 1182 | .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT, |
1149 | }, | 1183 | }, |
1150 | }, | 1184 | }, |
1185 | .opt_clks = mcbsp234_opt_clks, | ||
1186 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
1151 | .dev_attr = &omap34xx_mcbsp3_dev_attr, | 1187 | .dev_attr = &omap34xx_mcbsp3_dev_attr, |
1152 | }; | 1188 | }; |
1153 | 1189 | ||
@@ -1180,6 +1216,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = { | |||
1180 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, | 1216 | .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT, |
1181 | }, | 1217 | }, |
1182 | }, | 1218 | }, |
1219 | .opt_clks = mcbsp234_opt_clks, | ||
1220 | .opt_clks_cnt = ARRAY_SIZE(mcbsp234_opt_clks), | ||
1183 | }; | 1221 | }; |
1184 | 1222 | ||
1185 | /* mcbsp5 */ | 1223 | /* mcbsp5 */ |
@@ -1211,6 +1249,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = { | |||
1211 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, | 1249 | .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT, |
1212 | }, | 1250 | }, |
1213 | }, | 1251 | }, |
1252 | .opt_clks = mcbsp15_opt_clks, | ||
1253 | .opt_clks_cnt = ARRAY_SIZE(mcbsp15_opt_clks), | ||
1214 | }; | 1254 | }; |
1215 | 1255 | ||
1216 | /* 'mcbsp sidetone' class */ | 1256 | /* 'mcbsp sidetone' class */ |
@@ -1630,25 +1670,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = { | |||
1630 | 1670 | ||
1631 | /* usb_otg_hs */ | 1671 | /* usb_otg_hs */ |
1632 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { | 1672 | static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = { |
1633 | |||
1634 | { .name = "mc", .irq = 71 }, | 1673 | { .name = "mc", .irq = 71 }, |
1635 | { .irq = -1 } | 1674 | { .irq = -1 } |
1636 | }; | 1675 | }; |
1637 | 1676 | ||
1638 | static struct omap_hwmod_class am35xx_usbotg_class = { | 1677 | static struct omap_hwmod_class am35xx_usbotg_class = { |
1639 | .name = "am35xx_usbotg", | 1678 | .name = "am35xx_usbotg", |
1640 | .sysc = NULL, | ||
1641 | }; | 1679 | }; |
1642 | 1680 | ||
1643 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { | 1681 | static struct omap_hwmod am35xx_usbhsotg_hwmod = { |
1644 | .name = "am35x_otg_hs", | 1682 | .name = "am35x_otg_hs", |
1645 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, | 1683 | .mpu_irqs = am35xx_usbhsotg_mpu_irqs, |
1646 | .main_clk = NULL, | 1684 | .main_clk = "hsotgusb_fck", |
1647 | .prcm = { | ||
1648 | .omap2 = { | ||
1649 | }, | ||
1650 | }, | ||
1651 | .class = &am35xx_usbotg_class, | 1685 | .class = &am35xx_usbotg_class, |
1686 | .flags = HWMOD_NO_IDLEST, | ||
1652 | }; | 1687 | }; |
1653 | 1688 | ||
1654 | /* MMC/SD/SDIO common */ | 1689 | /* MMC/SD/SDIO common */ |
@@ -2089,9 +2124,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = { | |||
2089 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { | 2124 | static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = { |
2090 | .master = &am35xx_usbhsotg_hwmod, | 2125 | .master = &am35xx_usbhsotg_hwmod, |
2091 | .slave = &omap3xxx_l3_main_hwmod, | 2126 | .slave = &omap3xxx_l3_main_hwmod, |
2092 | .clk = "core_l3_ick", | 2127 | .clk = "hsotgusb_ick", |
2093 | .user = OCP_USER_MPU, | 2128 | .user = OCP_USER_MPU, |
2094 | }; | 2129 | }; |
2130 | |||
2095 | /* L4_CORE -> L4_WKUP interface */ | 2131 | /* L4_CORE -> L4_WKUP interface */ |
2096 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { | 2132 | static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = { |
2097 | .master = &omap3xxx_l4_core_hwmod, | 2133 | .master = &omap3xxx_l4_core_hwmod, |
@@ -2235,6 +2271,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = { | |||
2235 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, | 2271 | .pa_end = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1, |
2236 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, | 2272 | .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT, |
2237 | }, | 2273 | }, |
2274 | { } | ||
2238 | }; | 2275 | }; |
2239 | 2276 | ||
2240 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { | 2277 | static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = { |
@@ -2385,7 +2422,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = { | |||
2385 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { | 2422 | static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = { |
2386 | .master = &omap3xxx_l4_core_hwmod, | 2423 | .master = &omap3xxx_l4_core_hwmod, |
2387 | .slave = &am35xx_usbhsotg_hwmod, | 2424 | .slave = &am35xx_usbhsotg_hwmod, |
2388 | .clk = "l4_ick", | 2425 | .clk = "hsotgusb_ick", |
2389 | .addr = am35xx_usbhsotg_addrs, | 2426 | .addr = am35xx_usbhsotg_addrs, |
2390 | .user = OCP_USER_MPU, | 2427 | .user = OCP_USER_MPU, |
2391 | }; | 2428 | }; |
@@ -3130,6 +3167,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = { | |||
3130 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 3167 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
3131 | }; | 3168 | }; |
3132 | 3169 | ||
3170 | /* am35xx has Davinci MDIO & EMAC */ | ||
3171 | static struct omap_hwmod_class am35xx_mdio_class = { | ||
3172 | .name = "davinci_mdio", | ||
3173 | }; | ||
3174 | |||
3175 | static struct omap_hwmod am35xx_mdio_hwmod = { | ||
3176 | .name = "davinci_mdio", | ||
3177 | .class = &am35xx_mdio_class, | ||
3178 | .flags = HWMOD_NO_IDLEST, | ||
3179 | }; | ||
3180 | |||
3181 | /* | ||
3182 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | ||
3183 | * but this will probably require some additional hwmod core support, | ||
3184 | * so is left as a future to-do item. | ||
3185 | */ | ||
3186 | static struct omap_hwmod_ocp_if am35xx_mdio__l3 = { | ||
3187 | .master = &am35xx_mdio_hwmod, | ||
3188 | .slave = &omap3xxx_l3_main_hwmod, | ||
3189 | .clk = "emac_fck", | ||
3190 | .user = OCP_USER_MPU, | ||
3191 | }; | ||
3192 | |||
3193 | static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = { | ||
3194 | { | ||
3195 | .pa_start = AM35XX_IPSS_MDIO_BASE, | ||
3196 | .pa_end = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1, | ||
3197 | .flags = ADDR_TYPE_RT, | ||
3198 | }, | ||
3199 | { } | ||
3200 | }; | ||
3201 | |||
3202 | /* l4_core -> davinci mdio */ | ||
3203 | /* | ||
3204 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | ||
3205 | * but this will probably require some additional hwmod core support, | ||
3206 | * so is left as a future to-do item. | ||
3207 | */ | ||
3208 | static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = { | ||
3209 | .master = &omap3xxx_l4_core_hwmod, | ||
3210 | .slave = &am35xx_mdio_hwmod, | ||
3211 | .clk = "emac_fck", | ||
3212 | .addr = am35xx_mdio_addrs, | ||
3213 | .user = OCP_USER_MPU, | ||
3214 | }; | ||
3215 | |||
3216 | static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = { | ||
3217 | { .name = "rxthresh", .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ }, | ||
3218 | { .name = "rx_pulse", .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ }, | ||
3219 | { .name = "tx_pulse", .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ }, | ||
3220 | { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ }, | ||
3221 | { .irq = -1 } | ||
3222 | }; | ||
3223 | |||
3224 | static struct omap_hwmod_class am35xx_emac_class = { | ||
3225 | .name = "davinci_emac", | ||
3226 | }; | ||
3227 | |||
3228 | static struct omap_hwmod am35xx_emac_hwmod = { | ||
3229 | .name = "davinci_emac", | ||
3230 | .mpu_irqs = am35xx_emac_mpu_irqs, | ||
3231 | .class = &am35xx_emac_class, | ||
3232 | .flags = HWMOD_NO_IDLEST, | ||
3233 | }; | ||
3234 | |||
3235 | /* l3_core -> davinci emac interface */ | ||
3236 | /* | ||
3237 | * XXX Should be connected to an IPSS hwmod, not the L3 directly; | ||
3238 | * but this will probably require some additional hwmod core support, | ||
3239 | * so is left as a future to-do item. | ||
3240 | */ | ||
3241 | static struct omap_hwmod_ocp_if am35xx_emac__l3 = { | ||
3242 | .master = &am35xx_emac_hwmod, | ||
3243 | .slave = &omap3xxx_l3_main_hwmod, | ||
3244 | .clk = "emac_ick", | ||
3245 | .user = OCP_USER_MPU, | ||
3246 | }; | ||
3247 | |||
3248 | static struct omap_hwmod_addr_space am35xx_emac_addrs[] = { | ||
3249 | { | ||
3250 | .pa_start = AM35XX_IPSS_EMAC_BASE, | ||
3251 | .pa_end = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1, | ||
3252 | .flags = ADDR_TYPE_RT, | ||
3253 | }, | ||
3254 | { } | ||
3255 | }; | ||
3256 | |||
3257 | /* l4_core -> davinci emac */ | ||
3258 | /* | ||
3259 | * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly; | ||
3260 | * but this will probably require some additional hwmod core support, | ||
3261 | * so is left as a future to-do item. | ||
3262 | */ | ||
3263 | static struct omap_hwmod_ocp_if am35xx_l4_core__emac = { | ||
3264 | .master = &omap3xxx_l4_core_hwmod, | ||
3265 | .slave = &am35xx_emac_hwmod, | ||
3266 | .clk = "emac_ick", | ||
3267 | .addr = am35xx_emac_addrs, | ||
3268 | .user = OCP_USER_MPU, | ||
3269 | }; | ||
3270 | |||
3133 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { | 3271 | static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = { |
3134 | &omap3xxx_l3_main__l4_core, | 3272 | &omap3xxx_l3_main__l4_core, |
3135 | &omap3xxx_l3_main__l4_per, | 3273 | &omap3xxx_l3_main__l4_per, |
@@ -3258,6 +3396,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = { | |||
3258 | &omap3xxx_l4_core__usb_tll_hs, | 3396 | &omap3xxx_l4_core__usb_tll_hs, |
3259 | &omap3xxx_l4_core__es3plus_mmc1, | 3397 | &omap3xxx_l4_core__es3plus_mmc1, |
3260 | &omap3xxx_l4_core__es3plus_mmc2, | 3398 | &omap3xxx_l4_core__es3plus_mmc2, |
3399 | &am35xx_mdio__l3, | ||
3400 | &am35xx_l4_core__mdio, | ||
3401 | &am35xx_emac__l3, | ||
3402 | &am35xx_l4_core__emac, | ||
3261 | NULL | 3403 | NULL |
3262 | }; | 3404 | }; |
3263 | 3405 | ||
@@ -3275,6 +3417,8 @@ int __init omap3xxx_hwmod_init(void) | |||
3275 | struct omap_hwmod_ocp_if **h = NULL; | 3417 | struct omap_hwmod_ocp_if **h = NULL; |
3276 | unsigned int rev; | 3418 | unsigned int rev; |
3277 | 3419 | ||
3420 | omap_hwmod_init(); | ||
3421 | |||
3278 | /* Register hwmod links common to all OMAP3 */ | 3422 | /* Register hwmod links common to all OMAP3 */ |
3279 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); | 3423 | r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs); |
3280 | if (r < 0) | 3424 | if (r < 0) |
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index dfe9bc4d7b80..5c2ce7e77838 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c | |||
@@ -2544,14 +2544,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = { | |||
2544 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { | 2544 | static struct omap_hwmod omap44xx_cm_core_aon_hwmod = { |
2545 | .name = "cm_core_aon", | 2545 | .name = "cm_core_aon", |
2546 | .class = &omap44xx_prcm_hwmod_class, | 2546 | .class = &omap44xx_prcm_hwmod_class, |
2547 | .clkdm_name = "cm_clkdm", | ||
2548 | }; | 2547 | }; |
2549 | 2548 | ||
2550 | /* cm_core */ | 2549 | /* cm_core */ |
2551 | static struct omap_hwmod omap44xx_cm_core_hwmod = { | 2550 | static struct omap_hwmod omap44xx_cm_core_hwmod = { |
2552 | .name = "cm_core", | 2551 | .name = "cm_core", |
2553 | .class = &omap44xx_prcm_hwmod_class, | 2552 | .class = &omap44xx_prcm_hwmod_class, |
2554 | .clkdm_name = "cm_clkdm", | ||
2555 | }; | 2553 | }; |
2556 | 2554 | ||
2557 | /* prm */ | 2555 | /* prm */ |
@@ -2568,7 +2566,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = { | |||
2568 | static struct omap_hwmod omap44xx_prm_hwmod = { | 2566 | static struct omap_hwmod omap44xx_prm_hwmod = { |
2569 | .name = "prm", | 2567 | .name = "prm", |
2570 | .class = &omap44xx_prcm_hwmod_class, | 2568 | .class = &omap44xx_prcm_hwmod_class, |
2571 | .clkdm_name = "prm_clkdm", | ||
2572 | .mpu_irqs = omap44xx_prm_irqs, | 2569 | .mpu_irqs = omap44xx_prm_irqs, |
2573 | .rst_lines = omap44xx_prm_resets, | 2570 | .rst_lines = omap44xx_prm_resets, |
2574 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), | 2571 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets), |
@@ -6142,6 +6139,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { | |||
6142 | 6139 | ||
6143 | int __init omap44xx_hwmod_init(void) | 6140 | int __init omap44xx_hwmod_init(void) |
6144 | { | 6141 | { |
6142 | omap_hwmod_init(); | ||
6145 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); | 6143 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
6146 | } | 6144 | } |
6147 | 6145 | ||
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c index de6d46451746..d8f6dbf45d16 100644 --- a/arch/arm/mach-omap2/opp.c +++ b/arch/arm/mach-omap2/opp.c | |||
@@ -53,7 +53,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, | |||
53 | omap_table_init = 1; | 53 | omap_table_init = 1; |
54 | 54 | ||
55 | /* Lets now register with OPP library */ | 55 | /* Lets now register with OPP library */ |
56 | for (i = 0; i < opp_def_size; i++) { | 56 | for (i = 0; i < opp_def_size; i++, opp_def++) { |
57 | struct omap_hwmod *oh; | 57 | struct omap_hwmod *oh; |
58 | struct device *dev; | 58 | struct device *dev; |
59 | 59 | ||
@@ -86,7 +86,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def, | |||
86 | __func__, opp_def->freq, | 86 | __func__, opp_def->freq, |
87 | opp_def->hwmod_name, i, r); | 87 | opp_def->hwmod_name, i, r); |
88 | } | 88 | } |
89 | opp_def++; | ||
90 | } | 89 | } |
91 | 90 | ||
92 | return 0; | 91 | return 0; |
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 78564895e914..ab04d3bba2e7 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
@@ -15,12 +15,25 @@ | |||
15 | 15 | ||
16 | #include "powerdomain.h" | 16 | #include "powerdomain.h" |
17 | 17 | ||
18 | #ifdef CONFIG_CPU_IDLE | ||
19 | extern int __init omap3_idle_init(void); | ||
20 | extern int __init omap4_idle_init(void); | ||
21 | #else | ||
22 | static inline int omap3_idle_init(void) | ||
23 | { | ||
24 | return 0; | ||
25 | } | ||
26 | |||
27 | static inline int omap4_idle_init(void) | ||
28 | { | ||
29 | return 0; | ||
30 | } | ||
31 | #endif | ||
32 | |||
18 | extern void *omap3_secure_ram_storage; | 33 | extern void *omap3_secure_ram_storage; |
19 | extern void omap3_pm_off_mode_enable(int); | 34 | extern void omap3_pm_off_mode_enable(int); |
20 | extern void omap_sram_idle(void); | 35 | extern void omap_sram_idle(void); |
21 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | 36 | extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state); |
22 | extern int omap3_idle_init(void); | ||
23 | extern int omap4_idle_init(void); | ||
24 | extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); | 37 | extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused); |
25 | extern int (*omap_pm_suspend)(void); | 38 | extern int (*omap_pm_suspend)(void); |
26 | 39 | ||
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 3a595e899724..9b463c987508 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -581,10 +581,13 @@ static void __init prcm_setup_regs(void) | |||
581 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | 581 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
582 | 582 | ||
583 | /* Don't attach IVA interrupts */ | 583 | /* Don't attach IVA interrupts */ |
584 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | 584 | if (omap3_has_iva()) { |
585 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | 585 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
586 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | 586 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); |
587 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | 587 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); |
588 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, | ||
589 | OMAP3430_PM_IVAGRPSEL); | ||
590 | } | ||
588 | 591 | ||
589 | /* Clear any pending 'reset' flags */ | 592 | /* Clear any pending 'reset' flags */ |
590 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); | 593 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
@@ -598,7 +601,9 @@ static void __init prcm_setup_regs(void) | |||
598 | /* Clear any pending PRCM interrupts */ | 601 | /* Clear any pending PRCM interrupts */ |
599 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | 602 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
600 | 603 | ||
601 | omap3_iva_idle(); | 604 | if (omap3_has_iva()) |
605 | omap3_iva_idle(); | ||
606 | |||
602 | omap3_d2d_idle(); | 607 | omap3_d2d_idle(); |
603 | } | 608 | } |
604 | 609 | ||
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index 8f88d65c46ea..a8a95184243d 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h | |||
@@ -67,9 +67,9 @@ | |||
67 | 67 | ||
68 | /* | 68 | /* |
69 | * Maximum number of clockdomains that can be associated with a powerdomain. | 69 | * Maximum number of clockdomains that can be associated with a powerdomain. |
70 | * CORE powerdomain on OMAP4 is the worst case | 70 | * PER powerdomain on AM33XX is the worst case |
71 | */ | 71 | */ |
72 | #define PWRDM_MAX_CLKDMS 9 | 72 | #define PWRDM_MAX_CLKDMS 11 |
73 | 73 | ||
74 | /* XXX A completely arbitrary number. What is reasonable here? */ | 74 | /* XXX A completely arbitrary number. What is reasonable here? */ |
75 | #define PWRDM_TRANSITION_BAILOUT 100000 | 75 | #define PWRDM_TRANSITION_BAILOUT 100000 |
@@ -92,6 +92,15 @@ struct powerdomain; | |||
92 | * @pwrdm_clkdms: Clockdomains in this powerdomain | 92 | * @pwrdm_clkdms: Clockdomains in this powerdomain |
93 | * @node: list_head linking all powerdomains | 93 | * @node: list_head linking all powerdomains |
94 | * @voltdm_node: list_head linking all powerdomains in a voltagedomain | 94 | * @voltdm_node: list_head linking all powerdomains in a voltagedomain |
95 | * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs | ||
96 | * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs | ||
97 | * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield | ||
98 | * in @pwrstctrl_offs | ||
99 | * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs | ||
100 | * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs | ||
101 | * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs | ||
102 | * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield | ||
103 | * in @pwrstctrl_offs | ||
95 | * @state: | 104 | * @state: |
96 | * @state_counter: | 105 | * @state_counter: |
97 | * @timer: | 106 | * @timer: |
@@ -121,6 +130,14 @@ struct powerdomain { | |||
121 | unsigned ret_logic_off_counter; | 130 | unsigned ret_logic_off_counter; |
122 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | 131 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; |
123 | 132 | ||
133 | const u8 pwrstctrl_offs; | ||
134 | const u8 pwrstst_offs; | ||
135 | const u32 logicretstate_mask; | ||
136 | const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; | ||
137 | const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; | ||
138 | const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; | ||
139 | const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; | ||
140 | |||
124 | #ifdef CONFIG_PM_DEBUG | 141 | #ifdef CONFIG_PM_DEBUG |
125 | s64 timer; | 142 | s64 timer; |
126 | s64 state_timer[PWRDM_MAX_PWRSTS]; | 143 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
@@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); | |||
222 | extern void omap242x_powerdomains_init(void); | 239 | extern void omap242x_powerdomains_init(void); |
223 | extern void omap243x_powerdomains_init(void); | 240 | extern void omap243x_powerdomains_init(void); |
224 | extern void omap3xxx_powerdomains_init(void); | 241 | extern void omap3xxx_powerdomains_init(void); |
242 | extern void am33xx_powerdomains_init(void); | ||
225 | extern void omap44xx_powerdomains_init(void); | 243 | extern void omap44xx_powerdomains_init(void); |
226 | 244 | ||
227 | extern struct pwrdm_ops omap2_pwrdm_operations; | 245 | extern struct pwrdm_ops omap2_pwrdm_operations; |
228 | extern struct pwrdm_ops omap3_pwrdm_operations; | 246 | extern struct pwrdm_ops omap3_pwrdm_operations; |
247 | extern struct pwrdm_ops am33xx_pwrdm_operations; | ||
229 | extern struct pwrdm_ops omap4_pwrdm_operations; | 248 | extern struct pwrdm_ops omap4_pwrdm_operations; |
230 | 249 | ||
231 | /* Common Internal functions used across OMAP rev's */ | 250 | /* Common Internal functions used across OMAP rev's */ |
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c new file mode 100644 index 000000000000..67c5663899b6 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain33xx.c | |||
@@ -0,0 +1,229 @@ | |||
1 | /* | ||
2 | * AM33XX Powerdomain control | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak | ||
7 | * <rnayak@ti.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or | ||
10 | * modify it under the terms of the GNU General Public License as | ||
11 | * published by the Free Software Foundation version 2. | ||
12 | * | ||
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
14 | * kind, whether express or implied; without even the implied warranty | ||
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | */ | ||
18 | |||
19 | #include <linux/io.h> | ||
20 | #include <linux/errno.h> | ||
21 | #include <linux/delay.h> | ||
22 | |||
23 | #include <plat/prcm.h> | ||
24 | |||
25 | #include "powerdomain.h" | ||
26 | #include "prm33xx.h" | ||
27 | #include "prm-regbits-33xx.h" | ||
28 | |||
29 | |||
30 | static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | ||
31 | { | ||
32 | am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, | ||
33 | (pwrst << OMAP_POWERSTATE_SHIFT), | ||
34 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
35 | return 0; | ||
36 | } | ||
37 | |||
38 | static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | ||
39 | { | ||
40 | u32 v; | ||
41 | |||
42 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
43 | v &= OMAP_POWERSTATE_MASK; | ||
44 | v >>= OMAP_POWERSTATE_SHIFT; | ||
45 | |||
46 | return v; | ||
47 | } | ||
48 | |||
49 | static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) | ||
50 | { | ||
51 | u32 v; | ||
52 | |||
53 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
54 | v &= OMAP_POWERSTATEST_MASK; | ||
55 | v >>= OMAP_POWERSTATEST_SHIFT; | ||
56 | |||
57 | return v; | ||
58 | } | ||
59 | |||
60 | static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | ||
61 | { | ||
62 | u32 v; | ||
63 | |||
64 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
65 | v &= AM33XX_LASTPOWERSTATEENTERED_MASK; | ||
66 | v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; | ||
67 | |||
68 | return v; | ||
69 | } | ||
70 | |||
71 | static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | ||
72 | { | ||
73 | am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, | ||
74 | (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), | ||
75 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
76 | return 0; | ||
77 | } | ||
78 | |||
79 | static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | ||
80 | { | ||
81 | am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
82 | AM33XX_LASTPOWERSTATEENTERED_MASK, | ||
83 | pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
84 | return 0; | ||
85 | } | ||
86 | |||
87 | static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | ||
88 | { | ||
89 | u32 m; | ||
90 | |||
91 | m = pwrdm->logicretstate_mask; | ||
92 | if (!m) | ||
93 | return -EINVAL; | ||
94 | |||
95 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
96 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
97 | |||
98 | return 0; | ||
99 | } | ||
100 | |||
101 | static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | ||
102 | { | ||
103 | u32 v; | ||
104 | |||
105 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
106 | v &= AM33XX_LOGICSTATEST_MASK; | ||
107 | v >>= AM33XX_LOGICSTATEST_SHIFT; | ||
108 | |||
109 | return v; | ||
110 | } | ||
111 | |||
112 | static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | ||
113 | { | ||
114 | u32 v, m; | ||
115 | |||
116 | m = pwrdm->logicretstate_mask; | ||
117 | if (!m) | ||
118 | return -EINVAL; | ||
119 | |||
120 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
121 | v &= m; | ||
122 | v >>= __ffs(m); | ||
123 | |||
124 | return v; | ||
125 | } | ||
126 | |||
127 | static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | ||
128 | u8 pwrst) | ||
129 | { | ||
130 | u32 m; | ||
131 | |||
132 | m = pwrdm->mem_on_mask[bank]; | ||
133 | if (!m) | ||
134 | return -EINVAL; | ||
135 | |||
136 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
137 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
138 | |||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | ||
143 | u8 pwrst) | ||
144 | { | ||
145 | u32 m; | ||
146 | |||
147 | m = pwrdm->mem_ret_mask[bank]; | ||
148 | if (!m) | ||
149 | return -EINVAL; | ||
150 | |||
151 | am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), | ||
152 | pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
153 | |||
154 | return 0; | ||
155 | } | ||
156 | |||
157 | static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | ||
158 | { | ||
159 | u32 m, v; | ||
160 | |||
161 | m = pwrdm->mem_pwrst_mask[bank]; | ||
162 | if (!m) | ||
163 | return -EINVAL; | ||
164 | |||
165 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); | ||
166 | v &= m; | ||
167 | v >>= __ffs(m); | ||
168 | |||
169 | return v; | ||
170 | } | ||
171 | |||
172 | static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | ||
173 | { | ||
174 | u32 m, v; | ||
175 | |||
176 | m = pwrdm->mem_retst_mask[bank]; | ||
177 | if (!m) | ||
178 | return -EINVAL; | ||
179 | |||
180 | v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); | ||
181 | v &= m; | ||
182 | v >>= __ffs(m); | ||
183 | |||
184 | return v; | ||
185 | } | ||
186 | |||
187 | static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) | ||
188 | { | ||
189 | u32 c = 0; | ||
190 | |||
191 | /* | ||
192 | * REVISIT: pwrdm_wait_transition() may be better implemented | ||
193 | * via a callback and a periodic timer check -- how long do we expect | ||
194 | * powerdomain transitions to take? | ||
195 | */ | ||
196 | |||
197 | /* XXX Is this udelay() value meaningful? */ | ||
198 | while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) | ||
199 | & OMAP_INTRANSITION_MASK) && | ||
200 | (c++ < PWRDM_TRANSITION_BAILOUT)) | ||
201 | udelay(1); | ||
202 | |||
203 | if (c > PWRDM_TRANSITION_BAILOUT) { | ||
204 | pr_err("powerdomain: %s: waited too long to complete transition\n", | ||
205 | pwrdm->name); | ||
206 | return -EAGAIN; | ||
207 | } | ||
208 | |||
209 | pr_debug("powerdomain: completed transition in %d loops\n", c); | ||
210 | |||
211 | return 0; | ||
212 | } | ||
213 | |||
214 | struct pwrdm_ops am33xx_pwrdm_operations = { | ||
215 | .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, | ||
216 | .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, | ||
217 | .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, | ||
218 | .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, | ||
219 | .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, | ||
220 | .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, | ||
221 | .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, | ||
222 | .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, | ||
223 | .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, | ||
224 | .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, | ||
225 | .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, | ||
226 | .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, | ||
227 | .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, | ||
228 | .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, | ||
229 | }; | ||
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c new file mode 100644 index 000000000000..869adb82569e --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains33xx_data.c | |||
@@ -0,0 +1,185 @@ | |||
1 | /* | ||
2 | * AM33XX Power domain data | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | |||
19 | #include "powerdomain.h" | ||
20 | #include "prcm-common.h" | ||
21 | #include "prm-regbits-33xx.h" | ||
22 | #include "prm33xx.h" | ||
23 | |||
24 | static struct powerdomain gfx_33xx_pwrdm = { | ||
25 | .name = "gfx_pwrdm", | ||
26 | .voltdm = { .name = "core" }, | ||
27 | .prcm_offs = AM33XX_PRM_GFX_MOD, | ||
28 | .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET, | ||
29 | .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET, | ||
30 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
31 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
32 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
33 | .banks = 1, | ||
34 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
35 | .mem_on_mask = { | ||
36 | [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */ | ||
37 | }, | ||
38 | .mem_ret_mask = { | ||
39 | [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ | ||
40 | }, | ||
41 | .mem_pwrst_mask = { | ||
42 | [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */ | ||
43 | }, | ||
44 | .mem_retst_mask = { | ||
45 | [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ | ||
46 | }, | ||
47 | .pwrsts_mem_ret = { | ||
48 | [0] = PWRSTS_OFF_RET, /* gfx_mem */ | ||
49 | }, | ||
50 | .pwrsts_mem_on = { | ||
51 | [0] = PWRSTS_ON, /* gfx_mem */ | ||
52 | }, | ||
53 | }; | ||
54 | |||
55 | static struct powerdomain rtc_33xx_pwrdm = { | ||
56 | .name = "rtc_pwrdm", | ||
57 | .voltdm = { .name = "rtc" }, | ||
58 | .prcm_offs = AM33XX_PRM_RTC_MOD, | ||
59 | .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET, | ||
60 | .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET, | ||
61 | .pwrsts = PWRSTS_ON, | ||
62 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
63 | }; | ||
64 | |||
65 | static struct powerdomain wkup_33xx_pwrdm = { | ||
66 | .name = "wkup_pwrdm", | ||
67 | .voltdm = { .name = "core" }, | ||
68 | .prcm_offs = AM33XX_PRM_WKUP_MOD, | ||
69 | .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET, | ||
70 | .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET, | ||
71 | .pwrsts = PWRSTS_ON, | ||
72 | .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, | ||
73 | }; | ||
74 | |||
75 | static struct powerdomain per_33xx_pwrdm = { | ||
76 | .name = "per_pwrdm", | ||
77 | .voltdm = { .name = "core" }, | ||
78 | .prcm_offs = AM33XX_PRM_PER_MOD, | ||
79 | .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET, | ||
80 | .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET, | ||
81 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
82 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
83 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
84 | .banks = 3, | ||
85 | .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, | ||
86 | .mem_on_mask = { | ||
87 | [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */ | ||
88 | [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */ | ||
89 | [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */ | ||
90 | }, | ||
91 | .mem_ret_mask = { | ||
92 | [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ | ||
93 | [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ | ||
94 | [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ | ||
95 | }, | ||
96 | .mem_pwrst_mask = { | ||
97 | [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */ | ||
98 | [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */ | ||
99 | [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */ | ||
100 | }, | ||
101 | .mem_retst_mask = { | ||
102 | [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ | ||
103 | [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ | ||
104 | [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ | ||
105 | }, | ||
106 | .pwrsts_mem_ret = { | ||
107 | [0] = PWRSTS_OFF_RET, /* pruss_mem */ | ||
108 | [1] = PWRSTS_OFF_RET, /* per_mem */ | ||
109 | [2] = PWRSTS_OFF_RET, /* ram_mem */ | ||
110 | }, | ||
111 | .pwrsts_mem_on = { | ||
112 | [0] = PWRSTS_ON, /* pruss_mem */ | ||
113 | [1] = PWRSTS_ON, /* per_mem */ | ||
114 | [2] = PWRSTS_ON, /* ram_mem */ | ||
115 | }, | ||
116 | }; | ||
117 | |||
118 | static struct powerdomain mpu_33xx_pwrdm = { | ||
119 | .name = "mpu_pwrdm", | ||
120 | .voltdm = { .name = "mpu" }, | ||
121 | .prcm_offs = AM33XX_PRM_MPU_MOD, | ||
122 | .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET, | ||
123 | .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET, | ||
124 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
125 | .pwrsts_logic_ret = PWRSTS_OFF_RET, | ||
126 | .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, | ||
127 | .banks = 3, | ||
128 | .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, | ||
129 | .mem_on_mask = { | ||
130 | [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */ | ||
131 | [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */ | ||
132 | [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */ | ||
133 | }, | ||
134 | .mem_ret_mask = { | ||
135 | [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ | ||
136 | [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ | ||
137 | [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ | ||
138 | }, | ||
139 | .mem_pwrst_mask = { | ||
140 | [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */ | ||
141 | [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */ | ||
142 | [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */ | ||
143 | }, | ||
144 | .mem_retst_mask = { | ||
145 | [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ | ||
146 | [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ | ||
147 | [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ | ||
148 | }, | ||
149 | .pwrsts_mem_ret = { | ||
150 | [0] = PWRSTS_OFF_RET, /* mpu_l1 */ | ||
151 | [1] = PWRSTS_OFF_RET, /* mpu_l2 */ | ||
152 | [2] = PWRSTS_OFF_RET, /* mpu_ram */ | ||
153 | }, | ||
154 | .pwrsts_mem_on = { | ||
155 | [0] = PWRSTS_ON, /* mpu_l1 */ | ||
156 | [1] = PWRSTS_ON, /* mpu_l2 */ | ||
157 | [2] = PWRSTS_ON, /* mpu_ram */ | ||
158 | }, | ||
159 | }; | ||
160 | |||
161 | static struct powerdomain cefuse_33xx_pwrdm = { | ||
162 | .name = "cefuse_pwrdm", | ||
163 | .voltdm = { .name = "core" }, | ||
164 | .prcm_offs = AM33XX_PRM_CEFUSE_MOD, | ||
165 | .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET, | ||
166 | .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET, | ||
167 | .pwrsts = PWRSTS_OFF_ON, | ||
168 | }; | ||
169 | |||
170 | static struct powerdomain *powerdomains_am33xx[] __initdata = { | ||
171 | &gfx_33xx_pwrdm, | ||
172 | &rtc_33xx_pwrdm, | ||
173 | &wkup_33xx_pwrdm, | ||
174 | &per_33xx_pwrdm, | ||
175 | &mpu_33xx_pwrdm, | ||
176 | &cefuse_33xx_pwrdm, | ||
177 | NULL, | ||
178 | }; | ||
179 | |||
180 | void __init am33xx_powerdomains_init(void) | ||
181 | { | ||
182 | pwrdm_register_platform_funcs(&am33xx_pwrdm_operations); | ||
183 | pwrdm_register_pwrdms(powerdomains_am33xx); | ||
184 | pwrdm_complete_init(); | ||
185 | } | ||
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index fb0a0a6869d1..bb883e463078 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c | |||
@@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = { | |||
71 | .voltdm = { .name = "mpu_iva" }, | 71 | .voltdm = { .name = "mpu_iva" }, |
72 | }; | 72 | }; |
73 | 73 | ||
74 | static struct powerdomain mpu_am35x_pwrdm = { | ||
75 | .name = "mpu_pwrdm", | ||
76 | .prcm_offs = MPU_MOD, | ||
77 | .pwrsts = PWRSTS_ON, | ||
78 | .pwrsts_logic_ret = PWRSTS_ON, | ||
79 | .flags = PWRDM_HAS_MPU_QUIRK, | ||
80 | .banks = 1, | ||
81 | .pwrsts_mem_ret = { | ||
82 | [0] = PWRSTS_ON, | ||
83 | }, | ||
84 | .pwrsts_mem_on = { | ||
85 | [0] = PWRSTS_ON, | ||
86 | }, | ||
87 | .voltdm = { .name = "mpu_iva" }, | ||
88 | }; | ||
89 | |||
74 | /* | 90 | /* |
75 | * The USBTLL Save-and-Restore mechanism is broken on | 91 | * The USBTLL Save-and-Restore mechanism is broken on |
76 | * 3430s up to ES3.0 and 3630ES1.0. Hence this feature | 92 | * 3430s up to ES3.0 and 3630ES1.0. Hence this feature |
@@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = { | |||
120 | .voltdm = { .name = "core" }, | 136 | .voltdm = { .name = "core" }, |
121 | }; | 137 | }; |
122 | 138 | ||
139 | static struct powerdomain core_am35x_pwrdm = { | ||
140 | .name = "core_pwrdm", | ||
141 | .prcm_offs = CORE_MOD, | ||
142 | .pwrsts = PWRSTS_ON, | ||
143 | .pwrsts_logic_ret = PWRSTS_ON, | ||
144 | .banks = 2, | ||
145 | .pwrsts_mem_ret = { | ||
146 | [0] = PWRSTS_ON, /* MEM1RETSTATE */ | ||
147 | [1] = PWRSTS_ON, /* MEM2RETSTATE */ | ||
148 | }, | ||
149 | .pwrsts_mem_on = { | ||
150 | [0] = PWRSTS_ON, /* MEM1ONSTATE */ | ||
151 | [1] = PWRSTS_ON, /* MEM2ONSTATE */ | ||
152 | }, | ||
153 | .voltdm = { .name = "core" }, | ||
154 | }; | ||
155 | |||
123 | static struct powerdomain dss_pwrdm = { | 156 | static struct powerdomain dss_pwrdm = { |
124 | .name = "dss_pwrdm", | 157 | .name = "dss_pwrdm", |
125 | .prcm_offs = OMAP3430_DSS_MOD, | 158 | .prcm_offs = OMAP3430_DSS_MOD, |
@@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = { | |||
135 | .voltdm = { .name = "core" }, | 168 | .voltdm = { .name = "core" }, |
136 | }; | 169 | }; |
137 | 170 | ||
171 | static struct powerdomain dss_am35x_pwrdm = { | ||
172 | .name = "dss_pwrdm", | ||
173 | .prcm_offs = OMAP3430_DSS_MOD, | ||
174 | .pwrsts = PWRSTS_ON, | ||
175 | .pwrsts_logic_ret = PWRSTS_ON, | ||
176 | .banks = 1, | ||
177 | .pwrsts_mem_ret = { | ||
178 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
179 | }, | ||
180 | .pwrsts_mem_on = { | ||
181 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
182 | }, | ||
183 | .voltdm = { .name = "core" }, | ||
184 | }; | ||
185 | |||
138 | /* | 186 | /* |
139 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a | 187 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a |
140 | * possible SGX powerstate, the SGX device itself does not support | 188 | * possible SGX powerstate, the SGX device itself does not support |
@@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = { | |||
156 | .voltdm = { .name = "core" }, | 204 | .voltdm = { .name = "core" }, |
157 | }; | 205 | }; |
158 | 206 | ||
207 | static struct powerdomain sgx_am35x_pwrdm = { | ||
208 | .name = "sgx_pwrdm", | ||
209 | .prcm_offs = OMAP3430ES2_SGX_MOD, | ||
210 | .pwrsts = PWRSTS_ON, | ||
211 | .pwrsts_logic_ret = PWRSTS_ON, | ||
212 | .banks = 1, | ||
213 | .pwrsts_mem_ret = { | ||
214 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
215 | }, | ||
216 | .pwrsts_mem_on = { | ||
217 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
218 | }, | ||
219 | .voltdm = { .name = "core" }, | ||
220 | }; | ||
221 | |||
159 | static struct powerdomain cam_pwrdm = { | 222 | static struct powerdomain cam_pwrdm = { |
160 | .name = "cam_pwrdm", | 223 | .name = "cam_pwrdm", |
161 | .prcm_offs = OMAP3430_CAM_MOD, | 224 | .prcm_offs = OMAP3430_CAM_MOD, |
@@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = { | |||
186 | .voltdm = { .name = "core" }, | 249 | .voltdm = { .name = "core" }, |
187 | }; | 250 | }; |
188 | 251 | ||
252 | static struct powerdomain per_am35x_pwrdm = { | ||
253 | .name = "per_pwrdm", | ||
254 | .prcm_offs = OMAP3430_PER_MOD, | ||
255 | .pwrsts = PWRSTS_ON, | ||
256 | .pwrsts_logic_ret = PWRSTS_ON, | ||
257 | .banks = 1, | ||
258 | .pwrsts_mem_ret = { | ||
259 | [0] = PWRSTS_ON, /* MEMRETSTATE */ | ||
260 | }, | ||
261 | .pwrsts_mem_on = { | ||
262 | [0] = PWRSTS_ON, /* MEMONSTATE */ | ||
263 | }, | ||
264 | .voltdm = { .name = "core" }, | ||
265 | }; | ||
266 | |||
189 | static struct powerdomain emu_pwrdm = { | 267 | static struct powerdomain emu_pwrdm = { |
190 | .name = "emu_pwrdm", | 268 | .name = "emu_pwrdm", |
191 | .prcm_offs = OMAP3430_EMU_MOD, | 269 | .prcm_offs = OMAP3430_EMU_MOD, |
@@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = { | |||
200 | .voltdm = { .name = "mpu_iva" }, | 278 | .voltdm = { .name = "mpu_iva" }, |
201 | }; | 279 | }; |
202 | 280 | ||
281 | static struct powerdomain neon_am35x_pwrdm = { | ||
282 | .name = "neon_pwrdm", | ||
283 | .prcm_offs = OMAP3430_NEON_MOD, | ||
284 | .pwrsts = PWRSTS_ON, | ||
285 | .pwrsts_logic_ret = PWRSTS_ON, | ||
286 | .voltdm = { .name = "mpu_iva" }, | ||
287 | }; | ||
288 | |||
203 | static struct powerdomain usbhost_pwrdm = { | 289 | static struct powerdomain usbhost_pwrdm = { |
204 | .name = "usbhost_pwrdm", | 290 | .name = "usbhost_pwrdm", |
205 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 291 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
@@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = { | |||
293 | NULL | 379 | NULL |
294 | }; | 380 | }; |
295 | 381 | ||
382 | static struct powerdomain *powerdomains_am35x[] __initdata = { | ||
383 | &wkup_omap2_pwrdm, | ||
384 | &mpu_am35x_pwrdm, | ||
385 | &neon_am35x_pwrdm, | ||
386 | &core_am35x_pwrdm, | ||
387 | &sgx_am35x_pwrdm, | ||
388 | &dss_am35x_pwrdm, | ||
389 | &per_am35x_pwrdm, | ||
390 | &emu_pwrdm, | ||
391 | &dpll1_pwrdm, | ||
392 | &dpll3_pwrdm, | ||
393 | &dpll4_pwrdm, | ||
394 | &dpll5_pwrdm, | ||
395 | NULL | ||
396 | }; | ||
397 | |||
296 | void __init omap3xxx_powerdomains_init(void) | 398 | void __init omap3xxx_powerdomains_init(void) |
297 | { | 399 | { |
298 | unsigned int rev; | 400 | unsigned int rev; |
@@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void) | |||
301 | return; | 403 | return; |
302 | 404 | ||
303 | pwrdm_register_platform_funcs(&omap3_pwrdm_operations); | 405 | pwrdm_register_platform_funcs(&omap3_pwrdm_operations); |
304 | pwrdm_register_pwrdms(powerdomains_omap3430_common); | ||
305 | 406 | ||
306 | rev = omap_rev(); | 407 | rev = omap_rev(); |
307 | 408 | ||
308 | if (rev == OMAP3430_REV_ES1_0) | 409 | if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
309 | pwrdm_register_pwrdms(powerdomains_omap3430es1); | 410 | pwrdm_register_pwrdms(powerdomains_am35x); |
310 | else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 || | 411 | } else { |
311 | rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0) | 412 | pwrdm_register_pwrdms(powerdomains_omap3430_common); |
312 | pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); | 413 | |
313 | else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 || | 414 | switch (rev) { |
314 | rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 || | 415 | case OMAP3430_REV_ES1_0: |
315 | rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2) | 416 | pwrdm_register_pwrdms(powerdomains_omap3430es1); |
316 | pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); | 417 | break; |
317 | else | 418 | case OMAP3430_REV_ES2_0: |
318 | WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); | 419 | case OMAP3430_REV_ES2_1: |
420 | case OMAP3430_REV_ES3_0: | ||
421 | case OMAP3630_REV_ES1_0: | ||
422 | pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); | ||
423 | break; | ||
424 | case OMAP3430_REV_ES3_1: | ||
425 | case OMAP3430_REV_ES3_1_2: | ||
426 | case OMAP3630_REV_ES1_1: | ||
427 | case OMAP3630_REV_ES1_2: | ||
428 | pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); | ||
429 | break; | ||
430 | default: | ||
431 | WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); | ||
432 | } | ||
433 | } | ||
319 | 434 | ||
320 | pwrdm_complete_init(); | 435 | pwrdm_complete_init(); |
321 | } | 436 | } |
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 6da3ba483ad1..cc1398e8b469 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
@@ -203,8 +203,8 @@ | |||
203 | #define OMAP3430_EN_MMC2_SHIFT 25 | 203 | #define OMAP3430_EN_MMC2_SHIFT 25 |
204 | #define OMAP3430_EN_MMC1_MASK (1 << 24) | 204 | #define OMAP3430_EN_MMC1_MASK (1 << 24) |
205 | #define OMAP3430_EN_MMC1_SHIFT 24 | 205 | #define OMAP3430_EN_MMC1_SHIFT 24 |
206 | #define OMAP3430_EN_UART4_MASK (1 << 23) | 206 | #define AM35XX_EN_UART4_MASK (1 << 23) |
207 | #define OMAP3430_EN_UART4_SHIFT 23 | 207 | #define AM35XX_EN_UART4_SHIFT 23 |
208 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) | 208 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) |
209 | #define OMAP3430_EN_MCSPI4_SHIFT 21 | 209 | #define OMAP3430_EN_MCSPI4_SHIFT 21 |
210 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) | 210 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h new file mode 100644 index 000000000000..0221b5c20e87 --- /dev/null +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h | |||
@@ -0,0 +1,357 @@ | |||
1 | /* | ||
2 | * AM33XX PRM_XXX register bits | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | ||
17 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | ||
18 | |||
19 | #include "prm.h" | ||
20 | |||
21 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
22 | #define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 | ||
23 | #define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) | ||
24 | |||
25 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
26 | #define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 | ||
27 | #define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) | ||
28 | |||
29 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
30 | #define AM33XX_AIPOFF_SHIFT 8 | ||
31 | #define AM33XX_AIPOFF_MASK (1 << 8) | ||
32 | |||
33 | /* Used by PM_WKUP_PWRSTST */ | ||
34 | #define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 | ||
35 | #define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) | ||
36 | |||
37 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
38 | #define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 | ||
39 | #define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) | ||
40 | |||
41 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
42 | #define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 | ||
43 | #define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) | ||
44 | |||
45 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
46 | #define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 | ||
47 | #define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) | ||
48 | |||
49 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
50 | #define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 | ||
51 | #define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) | ||
52 | |||
53 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
54 | #define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 | ||
55 | #define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) | ||
56 | |||
57 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
58 | #define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 | ||
59 | #define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) | ||
60 | |||
61 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
62 | #define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 | ||
63 | #define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) | ||
64 | |||
65 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
66 | #define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 | ||
67 | #define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) | ||
68 | |||
69 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
70 | #define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 | ||
71 | #define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) | ||
72 | |||
73 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
74 | #define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 | ||
75 | #define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) | ||
76 | |||
77 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
78 | #define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 | ||
79 | #define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) | ||
80 | |||
81 | /* Used by RM_WKUP_RSTST */ | ||
82 | #define AM33XX_EMULATION_M3_RST_SHIFT 6 | ||
83 | #define AM33XX_EMULATION_M3_RST_MASK (1 << 6) | ||
84 | |||
85 | /* Used by RM_MPU_RSTST */ | ||
86 | #define AM33XX_EMULATION_MPU_RST_SHIFT 5 | ||
87 | #define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) | ||
88 | |||
89 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
90 | #define AM33XX_ENFUNC1_EXPORT_SHIFT 3 | ||
91 | #define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) | ||
92 | |||
93 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
94 | #define AM33XX_ENFUNC3_EXPORT_SHIFT 5 | ||
95 | #define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) | ||
96 | |||
97 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
98 | #define AM33XX_ENFUNC4_SHIFT 6 | ||
99 | #define AM33XX_ENFUNC4_MASK (1 << 6) | ||
100 | |||
101 | /* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ | ||
102 | #define AM33XX_ENFUNC5_SHIFT 7 | ||
103 | #define AM33XX_ENFUNC5_MASK (1 << 7) | ||
104 | |||
105 | /* Used by PRM_RSTST */ | ||
106 | #define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 | ||
107 | #define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) | ||
108 | |||
109 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
110 | #define AM33XX_FORCEWKUP_EN_SHIFT 10 | ||
111 | #define AM33XX_FORCEWKUP_EN_MASK (1 << 10) | ||
112 | |||
113 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
114 | #define AM33XX_FORCEWKUP_ST_SHIFT 10 | ||
115 | #define AM33XX_FORCEWKUP_ST_MASK (1 << 10) | ||
116 | |||
117 | /* Used by PM_GFX_PWRSTCTRL */ | ||
118 | #define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 | ||
119 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) | ||
120 | |||
121 | /* Used by PM_GFX_PWRSTCTRL */ | ||
122 | #define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 | ||
123 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) | ||
124 | |||
125 | /* Used by PM_GFX_PWRSTST */ | ||
126 | #define AM33XX_GFX_MEM_STATEST_SHIFT 4 | ||
127 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) | ||
128 | |||
129 | /* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ | ||
130 | #define AM33XX_GFX_RST_SHIFT 0 | ||
131 | #define AM33XX_GFX_RST_MASK (1 << 0) | ||
132 | |||
133 | /* Used by PRM_RSTST */ | ||
134 | #define AM33XX_GLOBAL_COLD_RST_SHIFT 0 | ||
135 | #define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) | ||
136 | |||
137 | /* Used by PRM_RSTST */ | ||
138 | #define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 | ||
139 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) | ||
140 | |||
141 | /* Used by RM_WKUP_RSTST */ | ||
142 | #define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 | ||
143 | #define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) | ||
144 | |||
145 | /* Used by RM_MPU_RSTST */ | ||
146 | #define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 | ||
147 | #define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) | ||
148 | |||
149 | /* Used by PRM_RSTST */ | ||
150 | #define AM33XX_ICEPICK_RST_SHIFT 9 | ||
151 | #define AM33XX_ICEPICK_RST_MASK (1 << 9) | ||
152 | |||
153 | /* Used by RM_PER_RSTCTRL */ | ||
154 | #define AM33XX_PRUSS_LRST_SHIFT 1 | ||
155 | #define AM33XX_PRUSS_LRST_MASK (1 << 1) | ||
156 | |||
157 | /* Used by PM_PER_PWRSTCTRL */ | ||
158 | #define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 | ||
159 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) | ||
160 | |||
161 | /* Used by PM_PER_PWRSTCTRL */ | ||
162 | #define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 | ||
163 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) | ||
164 | |||
165 | /* Used by PM_PER_PWRSTST */ | ||
166 | #define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 | ||
167 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) | ||
168 | |||
169 | /* | ||
170 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
171 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
172 | */ | ||
173 | #define AM33XX_INTRANSITION_SHIFT 20 | ||
174 | #define AM33XX_INTRANSITION_MASK (1 << 20) | ||
175 | |||
176 | /* Used by PM_CEFUSE_PWRSTST */ | ||
177 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 | ||
178 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | ||
179 | |||
180 | /* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ | ||
181 | #define AM33XX_LOGICRETSTATE_SHIFT 2 | ||
182 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) | ||
183 | |||
184 | /* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ | ||
185 | #define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 | ||
186 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) | ||
187 | |||
188 | /* | ||
189 | * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, | ||
190 | * PM_WKUP_PWRSTST, PM_RTC_PWRSTST | ||
191 | */ | ||
192 | #define AM33XX_LOGICSTATEST_SHIFT 2 | ||
193 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) | ||
194 | |||
195 | /* | ||
196 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
197 | * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL | ||
198 | */ | ||
199 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 | ||
200 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | ||
201 | |||
202 | /* Used by PM_MPU_PWRSTCTRL */ | ||
203 | #define AM33XX_MPU_L1_ONSTATE_SHIFT 18 | ||
204 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) | ||
205 | |||
206 | /* Used by PM_MPU_PWRSTCTRL */ | ||
207 | #define AM33XX_MPU_L1_RETSTATE_SHIFT 22 | ||
208 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) | ||
209 | |||
210 | /* Used by PM_MPU_PWRSTST */ | ||
211 | #define AM33XX_MPU_L1_STATEST_SHIFT 6 | ||
212 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) | ||
213 | |||
214 | /* Used by PM_MPU_PWRSTCTRL */ | ||
215 | #define AM33XX_MPU_L2_ONSTATE_SHIFT 20 | ||
216 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) | ||
217 | |||
218 | /* Used by PM_MPU_PWRSTCTRL */ | ||
219 | #define AM33XX_MPU_L2_RETSTATE_SHIFT 23 | ||
220 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) | ||
221 | |||
222 | /* Used by PM_MPU_PWRSTST */ | ||
223 | #define AM33XX_MPU_L2_STATEST_SHIFT 8 | ||
224 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) | ||
225 | |||
226 | /* Used by PM_MPU_PWRSTCTRL */ | ||
227 | #define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 | ||
228 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) | ||
229 | |||
230 | /* Used by PM_MPU_PWRSTCTRL */ | ||
231 | #define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 | ||
232 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) | ||
233 | |||
234 | /* Used by PM_MPU_PWRSTST */ | ||
235 | #define AM33XX_MPU_RAM_STATEST_SHIFT 4 | ||
236 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) | ||
237 | |||
238 | /* Used by PRM_RSTST */ | ||
239 | #define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 | ||
240 | #define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) | ||
241 | |||
242 | /* Used by PRM_SRAM_COUNT */ | ||
243 | #define AM33XX_PCHARGECNT_VALUE_SHIFT 0 | ||
244 | #define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) | ||
245 | |||
246 | /* Used by RM_PER_RSTCTRL */ | ||
247 | #define AM33XX_PCI_LRST_SHIFT 0 | ||
248 | #define AM33XX_PCI_LRST_MASK (1 << 0) | ||
249 | |||
250 | /* Renamed from PCI_LRST Used by RM_PER_RSTST */ | ||
251 | #define AM33XX_PCI_LRST_5_5_SHIFT 5 | ||
252 | #define AM33XX_PCI_LRST_5_5_MASK (1 << 5) | ||
253 | |||
254 | /* Used by PM_PER_PWRSTCTRL */ | ||
255 | #define AM33XX_PER_MEM_ONSTATE_SHIFT 25 | ||
256 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) | ||
257 | |||
258 | /* Used by PM_PER_PWRSTCTRL */ | ||
259 | #define AM33XX_PER_MEM_RETSTATE_SHIFT 29 | ||
260 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) | ||
261 | |||
262 | /* Used by PM_PER_PWRSTST */ | ||
263 | #define AM33XX_PER_MEM_STATEST_SHIFT 17 | ||
264 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) | ||
265 | |||
266 | /* | ||
267 | * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, | ||
268 | * PM_MPU_PWRSTCTRL | ||
269 | */ | ||
270 | #define AM33XX_POWERSTATE_SHIFT 0 | ||
271 | #define AM33XX_POWERSTATE_MASK (0x3 << 0) | ||
272 | |||
273 | /* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ | ||
274 | #define AM33XX_POWERSTATEST_SHIFT 0 | ||
275 | #define AM33XX_POWERSTATEST_MASK (0x3 << 0) | ||
276 | |||
277 | /* Used by PM_PER_PWRSTCTRL */ | ||
278 | #define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 | ||
279 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) | ||
280 | |||
281 | /* Used by PM_PER_PWRSTCTRL */ | ||
282 | #define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 | ||
283 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) | ||
284 | |||
285 | /* Used by PM_PER_PWRSTST */ | ||
286 | #define AM33XX_RAM_MEM_STATEST_SHIFT 21 | ||
287 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) | ||
288 | |||
289 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
290 | #define AM33XX_RETMODE_ENABLE_SHIFT 0 | ||
291 | #define AM33XX_RETMODE_ENABLE_MASK (1 << 0) | ||
292 | |||
293 | /* Used by REVISION_PRM */ | ||
294 | #define AM33XX_REV_SHIFT 0 | ||
295 | #define AM33XX_REV_MASK (0xff << 0) | ||
296 | |||
297 | /* Used by PRM_RSTTIME */ | ||
298 | #define AM33XX_RSTTIME1_SHIFT 0 | ||
299 | #define AM33XX_RSTTIME1_MASK (0xff << 0) | ||
300 | |||
301 | /* Used by PRM_RSTTIME */ | ||
302 | #define AM33XX_RSTTIME2_SHIFT 8 | ||
303 | #define AM33XX_RSTTIME2_MASK (0x1f << 8) | ||
304 | |||
305 | /* Used by PRM_RSTCTRL */ | ||
306 | #define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 | ||
307 | #define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) | ||
308 | |||
309 | /* Used by PRM_RSTCTRL */ | ||
310 | #define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 | ||
311 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) | ||
312 | |||
313 | /* Used by PRM_SRAM_COUNT */ | ||
314 | #define AM33XX_SLPCNT_VALUE_SHIFT 16 | ||
315 | #define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) | ||
316 | |||
317 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
318 | #define AM33XX_SRAMLDO_STATUS_SHIFT 8 | ||
319 | #define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) | ||
320 | |||
321 | /* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ | ||
322 | #define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 | ||
323 | #define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) | ||
324 | |||
325 | /* Used by PRM_SRAM_COUNT */ | ||
326 | #define AM33XX_STARTUP_COUNT_SHIFT 24 | ||
327 | #define AM33XX_STARTUP_COUNT_MASK (0xff << 24) | ||
328 | |||
329 | /* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ | ||
330 | #define AM33XX_TRANSITION_EN_SHIFT 8 | ||
331 | #define AM33XX_TRANSITION_EN_MASK (1 << 8) | ||
332 | |||
333 | /* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ | ||
334 | #define AM33XX_TRANSITION_ST_SHIFT 8 | ||
335 | #define AM33XX_TRANSITION_ST_MASK (1 << 8) | ||
336 | |||
337 | /* Used by PRM_SRAM_COUNT */ | ||
338 | #define AM33XX_VSETUPCNT_VALUE_SHIFT 8 | ||
339 | #define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) | ||
340 | |||
341 | /* Used by PRM_RSTST */ | ||
342 | #define AM33XX_WDT0_RST_SHIFT 3 | ||
343 | #define AM33XX_WDT0_RST_MASK (1 << 3) | ||
344 | |||
345 | /* Used by PRM_RSTST */ | ||
346 | #define AM33XX_WDT1_RST_SHIFT 4 | ||
347 | #define AM33XX_WDT1_RST_MASK (1 << 4) | ||
348 | |||
349 | /* Used by RM_WKUP_RSTCTRL */ | ||
350 | #define AM33XX_WKUP_M3_LRST_SHIFT 3 | ||
351 | #define AM33XX_WKUP_M3_LRST_MASK (1 << 3) | ||
352 | |||
353 | /* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ | ||
354 | #define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 | ||
355 | #define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) | ||
356 | |||
357 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c new file mode 100644 index 000000000000..e7dbb6cf1255 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.c | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * AM33XX PRM functions | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/types.h> | ||
18 | #include <linux/errno.h> | ||
19 | #include <linux/err.h> | ||
20 | #include <linux/io.h> | ||
21 | |||
22 | #include <plat/common.h> | ||
23 | |||
24 | #include "common.h" | ||
25 | #include "prm33xx.h" | ||
26 | #include "prm-regbits-33xx.h" | ||
27 | |||
28 | /* Read a register in a PRM instance */ | ||
29 | u32 am33xx_prm_read_reg(s16 inst, u16 idx) | ||
30 | { | ||
31 | return __raw_readl(prm_base + inst + idx); | ||
32 | } | ||
33 | |||
34 | /* Write into a register in a PRM instance */ | ||
35 | void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) | ||
36 | { | ||
37 | __raw_writel(val, prm_base + inst + idx); | ||
38 | } | ||
39 | |||
40 | /* Read-modify-write a register in PRM. Caller must lock */ | ||
41 | u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) | ||
42 | { | ||
43 | u32 v; | ||
44 | |||
45 | v = am33xx_prm_read_reg(inst, idx); | ||
46 | v &= ~mask; | ||
47 | v |= bits; | ||
48 | am33xx_prm_write_reg(v, inst, idx); | ||
49 | |||
50 | return v; | ||
51 | } | ||
52 | |||
53 | /** | ||
54 | * am33xx_prm_is_hardreset_asserted - read the HW reset line state of | ||
55 | * submodules contained in the hwmod module | ||
56 | * @shift: register bit shift corresponding to the reset line to check | ||
57 | * @inst: CM instance register offset (*_INST macro) | ||
58 | * @rstctrl_offs: RM_RSTCTRL register address offset for this module | ||
59 | * | ||
60 | * Returns 1 if the (sub)module hardreset line is currently asserted, | ||
61 | * 0 if the (sub)module hardreset line is not currently asserted, or | ||
62 | * -EINVAL upon parameter error. | ||
63 | */ | ||
64 | int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs) | ||
65 | { | ||
66 | u32 v; | ||
67 | |||
68 | v = am33xx_prm_read_reg(inst, rstctrl_offs); | ||
69 | v &= 1 << shift; | ||
70 | v >>= shift; | ||
71 | |||
72 | return v; | ||
73 | } | ||
74 | |||
75 | /** | ||
76 | * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule | ||
77 | * @shift: register bit shift corresponding to the reset line to assert | ||
78 | * @inst: CM instance register offset (*_INST macro) | ||
79 | * @rstctrl_reg: RM_RSTCTRL register address for this module | ||
80 | * | ||
81 | * Some IPs like dsp, ipu or iva contain processors that require an HW | ||
82 | * reset line to be asserted / deasserted in order to fully enable the | ||
83 | * IP. These modules may have multiple hard-reset lines that reset | ||
84 | * different 'submodules' inside the IP block. This function will | ||
85 | * place the submodule into reset. Returns 0 upon success or -EINVAL | ||
86 | * upon an argument error. | ||
87 | */ | ||
88 | int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs) | ||
89 | { | ||
90 | u32 mask = 1 << shift; | ||
91 | |||
92 | am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); | ||
93 | |||
94 | return 0; | ||
95 | } | ||
96 | |||
97 | /** | ||
98 | * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and | ||
99 | * wait | ||
100 | * @shift: register bit shift corresponding to the reset line to deassert | ||
101 | * @inst: CM instance register offset (*_INST macro) | ||
102 | * @rstctrl_reg: RM_RSTCTRL register address for this module | ||
103 | * @rstst_reg: RM_RSTST register address for this module | ||
104 | * | ||
105 | * Some IPs like dsp, ipu or iva contain processors that require an HW | ||
106 | * reset line to be asserted / deasserted in order to fully enable the | ||
107 | * IP. These modules may have multiple hard-reset lines that reset | ||
108 | * different 'submodules' inside the IP block. This function will | ||
109 | * take the submodule out of reset and wait until the PRCM indicates | ||
110 | * that the reset has completed before returning. Returns 0 upon success or | ||
111 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | ||
112 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | ||
113 | */ | ||
114 | int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, | ||
115 | u16 rstctrl_offs, u16 rstst_offs) | ||
116 | { | ||
117 | int c; | ||
118 | u32 mask = 1 << shift; | ||
119 | |||
120 | /* Check the current status to avoid de-asserting the line twice */ | ||
121 | if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) | ||
122 | return -EEXIST; | ||
123 | |||
124 | /* Clear the reset status by writing 1 to the status bit */ | ||
125 | am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); | ||
126 | /* de-assert the reset control line */ | ||
127 | am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); | ||
128 | /* wait the status to be set */ | ||
129 | |||
130 | omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, | ||
131 | rstst_offs), | ||
132 | MAX_MODULE_HARDRESET_WAIT, c); | ||
133 | |||
134 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | ||
135 | } | ||
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h new file mode 100644 index 000000000000..3f25c563a821 --- /dev/null +++ b/arch/arm/mach-omap2/prm33xx.h | |||
@@ -0,0 +1,129 @@ | |||
1 | /* | ||
2 | * AM33XX PRM instance offset macros | ||
3 | * | ||
4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H | ||
17 | #define __ARCH_ARM_MACH_OMAP2_PRM33XX_H | ||
18 | |||
19 | #include "prcm-common.h" | ||
20 | #include "prm.h" | ||
21 | |||
22 | #define AM33XX_PRM_BASE 0x44E00000 | ||
23 | |||
24 | #define AM33XX_PRM_REGADDR(inst, reg) \ | ||
25 | AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) | ||
26 | |||
27 | |||
28 | /* PRM instances */ | ||
29 | #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 | ||
30 | #define AM33XX_PRM_PER_MOD 0x0C00 | ||
31 | #define AM33XX_PRM_WKUP_MOD 0x0D00 | ||
32 | #define AM33XX_PRM_MPU_MOD 0x0E00 | ||
33 | #define AM33XX_PRM_DEVICE_MOD 0x0F00 | ||
34 | #define AM33XX_PRM_RTC_MOD 0x1000 | ||
35 | #define AM33XX_PRM_GFX_MOD 0x1100 | ||
36 | #define AM33XX_PRM_CEFUSE_MOD 0x1200 | ||
37 | |||
38 | /* PRM */ | ||
39 | |||
40 | /* PRM.OCP_SOCKET_PRM register offsets */ | ||
41 | #define AM33XX_REVISION_PRM_OFFSET 0x0000 | ||
42 | #define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) | ||
43 | #define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 | ||
44 | #define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) | ||
45 | #define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 | ||
46 | #define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) | ||
47 | #define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c | ||
48 | #define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) | ||
49 | #define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 | ||
50 | #define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) | ||
51 | |||
52 | /* PRM.PER_PRM register offsets */ | ||
53 | #define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 | ||
54 | #define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) | ||
55 | #define AM33XX_RM_PER_RSTST_OFFSET 0x0004 | ||
56 | #define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) | ||
57 | #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 | ||
58 | #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) | ||
59 | #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c | ||
60 | #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) | ||
61 | |||
62 | /* PRM.WKUP_PRM register offsets */ | ||
63 | #define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 | ||
64 | #define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) | ||
65 | #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 | ||
66 | #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) | ||
67 | #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 | ||
68 | #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) | ||
69 | #define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c | ||
70 | #define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) | ||
71 | |||
72 | /* PRM.MPU_PRM register offsets */ | ||
73 | #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 | ||
74 | #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) | ||
75 | #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 | ||
76 | #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) | ||
77 | #define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 | ||
78 | #define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) | ||
79 | |||
80 | /* PRM.DEVICE_PRM register offsets */ | ||
81 | #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 | ||
82 | #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) | ||
83 | #define AM33XX_PRM_RSTTIME_OFFSET 0x0004 | ||
84 | #define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) | ||
85 | #define AM33XX_PRM_RSTST_OFFSET 0x0008 | ||
86 | #define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) | ||
87 | #define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c | ||
88 | #define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) | ||
89 | #define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 | ||
90 | #define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) | ||
91 | #define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 | ||
92 | #define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) | ||
93 | #define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 | ||
94 | #define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) | ||
95 | #define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c | ||
96 | #define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) | ||
97 | |||
98 | /* PRM.RTC_PRM register offsets */ | ||
99 | #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 | ||
100 | #define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) | ||
101 | #define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 | ||
102 | #define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) | ||
103 | |||
104 | /* PRM.GFX_PRM register offsets */ | ||
105 | #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 | ||
106 | #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) | ||
107 | #define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 | ||
108 | #define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) | ||
109 | #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 | ||
110 | #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) | ||
111 | #define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 | ||
112 | #define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) | ||
113 | |||
114 | /* PRM.CEFUSE_PRM register offsets */ | ||
115 | #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 | ||
116 | #define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) | ||
117 | #define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 | ||
118 | #define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) | ||
119 | |||
120 | extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); | ||
121 | extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); | ||
122 | extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); | ||
123 | extern void am33xx_prm_global_warm_sw_reset(void); | ||
124 | extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, | ||
125 | u16 rstctrl_offs); | ||
126 | extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); | ||
127 | extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, | ||
128 | u16 rstctrl_offs, u16 rstst_offs); | ||
129 | #endif | ||
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index dfe00ddb5c60..534d732caa1e 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c | |||
@@ -85,7 +85,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
85 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; | 85 | unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG]; |
86 | struct irq_chip *chip = irq_desc_get_chip(desc); | 86 | struct irq_chip *chip = irq_desc_get_chip(desc); |
87 | unsigned int virtirq; | 87 | unsigned int virtirq; |
88 | int nr_irqs = prcm_irq_setup->nr_regs * 32; | 88 | int nr_irq = prcm_irq_setup->nr_regs * 32; |
89 | 89 | ||
90 | /* | 90 | /* |
91 | * If we are suspended, mask all interrupts from PRCM level, | 91 | * If we are suspended, mask all interrupts from PRCM level, |
@@ -110,7 +110,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
110 | prcm_irq_setup->read_pending_irqs(pending); | 110 | prcm_irq_setup->read_pending_irqs(pending); |
111 | 111 | ||
112 | /* No bit set, then all IRQs are handled */ | 112 | /* No bit set, then all IRQs are handled */ |
113 | if (find_first_bit(pending, nr_irqs) >= nr_irqs) | 113 | if (find_first_bit(pending, nr_irq) >= nr_irq) |
114 | break; | 114 | break; |
115 | 115 | ||
116 | omap_prcm_events_filter_priority(pending, priority_pending); | 116 | omap_prcm_events_filter_priority(pending, priority_pending); |
@@ -121,11 +121,11 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
121 | */ | 121 | */ |
122 | 122 | ||
123 | /* Serve priority events first */ | 123 | /* Serve priority events first */ |
124 | for_each_set_bit(virtirq, priority_pending, nr_irqs) | 124 | for_each_set_bit(virtirq, priority_pending, nr_irq) |
125 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | 125 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
126 | 126 | ||
127 | /* Serve normal events next */ | 127 | /* Serve normal events next */ |
128 | for_each_set_bit(virtirq, pending, nr_irqs) | 128 | for_each_set_bit(virtirq, pending, nr_irq) |
129 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); | 129 | generic_handle_irq(prcm_irq_setup->base_irq + virtirq); |
130 | } | 130 | } |
131 | if (chip->irq_ack) | 131 | if (chip->irq_ack) |
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 8fe75a81e12d..b5b5d92acd9d 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -364,6 +364,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, | |||
364 | OMAP_SYS_TIMER(3_secure) | 364 | OMAP_SYS_TIMER(3_secure) |
365 | #endif | 365 | #endif |
366 | 366 | ||
367 | #ifdef CONFIG_SOC_AM33XX | ||
368 | OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) | ||
369 | OMAP_SYS_TIMER(3_am33xx) | ||
370 | #endif | ||
371 | |||
367 | #ifdef CONFIG_ARCH_OMAP4 | 372 | #ifdef CONFIG_ARCH_OMAP4 |
368 | #ifdef CONFIG_LOCAL_TIMERS | 373 | #ifdef CONFIG_LOCAL_TIMERS |
369 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, | 374 | static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, |
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c index 43a979075338..3882f3c7608c 100644 --- a/arch/arm/mach-omap2/twl-common.c +++ b/arch/arm/mach-omap2/twl-common.c | |||
@@ -49,6 +49,7 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = { | |||
49 | }, | 49 | }, |
50 | }; | 50 | }; |
51 | 51 | ||
52 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
52 | static int twl_set_voltage(void *data, int target_uV) | 53 | static int twl_set_voltage(void *data, int target_uV) |
53 | { | 54 | { |
54 | struct voltagedomain *voltdm = (struct voltagedomain *)data; | 55 | struct voltagedomain *voltdm = (struct voltagedomain *)data; |
@@ -60,6 +61,7 @@ static int twl_get_voltage(void *data) | |||
60 | struct voltagedomain *voltdm = (struct voltagedomain *)data; | 61 | struct voltagedomain *voltdm = (struct voltagedomain *)data; |
61 | return voltdm_get_voltage(voltdm); | 62 | return voltdm_get_voltage(voltdm); |
62 | } | 63 | } |
64 | #endif | ||
63 | 65 | ||
64 | void __init omap_pmic_init(int bus, u32 clkrate, | 66 | void __init omap_pmic_init(int bus, u32 clkrate, |
65 | const char *pmic_type, int pmic_irq, | 67 | const char *pmic_type, int pmic_irq, |
@@ -213,10 +215,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = { | |||
213 | void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, | 215 | void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data, |
214 | u32 pdata_flags, u32 regulators_flags) | 216 | u32 pdata_flags, u32 regulators_flags) |
215 | { | 217 | { |
216 | if (!pmic_data->irq_base) | ||
217 | pmic_data->irq_base = TWL4030_IRQ_BASE; | ||
218 | if (!pmic_data->irq_end) | ||
219 | pmic_data->irq_end = TWL4030_IRQ_END; | ||
220 | if (!pmic_data->vdd1) { | 218 | if (!pmic_data->vdd1) { |
221 | omap3_vdd1.driver_data = &omap3_vdd1_drvdata; | 219 | omap3_vdd1.driver_data = &omap3_vdd1_drvdata; |
222 | omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); | 220 | omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva"); |
@@ -481,11 +479,6 @@ static struct regulator_init_data omap4_v2v1_idata = { | |||
481 | void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, | 479 | void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data, |
482 | u32 pdata_flags, u32 regulators_flags) | 480 | u32 pdata_flags, u32 regulators_flags) |
483 | { | 481 | { |
484 | if (!pmic_data->irq_base) | ||
485 | pmic_data->irq_base = TWL6030_IRQ_BASE; | ||
486 | if (!pmic_data->irq_end) | ||
487 | pmic_data->irq_end = TWL6030_IRQ_END; | ||
488 | |||
489 | if (!pmic_data->vdd1) { | 482 | if (!pmic_data->vdd1) { |
490 | omap4_vdd1.driver_data = &omap4_vdd1_drvdata; | 483 | omap4_vdd1.driver_data = &omap4_vdd1_drvdata; |
491 | omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); | 484 | omap4_vdd1_drvdata.data = voltdm_lookup("mpu"); |
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c deleted file mode 100644 index 1481078763b8..000000000000 --- a/arch/arm/mach-omap2/usb-fs.c +++ /dev/null | |||
@@ -1,359 +0,0 @@ | |||
1 | /* | ||
2 | * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx | ||
3 | * | ||
4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/module.h> | ||
22 | #include <linux/kernel.h> | ||
23 | #include <linux/types.h> | ||
24 | #include <linux/errno.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/clk.h> | ||
28 | #include <linux/err.h> | ||
29 | |||
30 | #include <asm/irq.h> | ||
31 | |||
32 | #include <plat/usb.h> | ||
33 | #include <plat/board.h> | ||
34 | |||
35 | #include "control.h" | ||
36 | #include "mux.h" | ||
37 | |||
38 | #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN | ||
39 | #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO | ||
40 | #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO | ||
41 | #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN | ||
42 | #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG | ||
43 | |||
44 | #if defined(CONFIG_ARCH_OMAP2) | ||
45 | |||
46 | #ifdef CONFIG_USB_GADGET_OMAP | ||
47 | |||
48 | static struct resource udc_resources[] = { | ||
49 | /* order is significant! */ | ||
50 | { /* registers */ | ||
51 | .start = UDC_BASE, | ||
52 | .end = UDC_BASE + 0xff, | ||
53 | .flags = IORESOURCE_MEM, | ||
54 | }, { /* general IRQ */ | ||
55 | .start = INT_USB_IRQ_GEN, | ||
56 | .flags = IORESOURCE_IRQ, | ||
57 | }, { /* PIO IRQ */ | ||
58 | .start = INT_USB_IRQ_NISO, | ||
59 | .flags = IORESOURCE_IRQ, | ||
60 | }, { /* SOF IRQ */ | ||
61 | .start = INT_USB_IRQ_ISO, | ||
62 | .flags = IORESOURCE_IRQ, | ||
63 | }, | ||
64 | }; | ||
65 | |||
66 | static u64 udc_dmamask = ~(u32)0; | ||
67 | |||
68 | static struct platform_device udc_device = { | ||
69 | .name = "omap_udc", | ||
70 | .id = -1, | ||
71 | .dev = { | ||
72 | .dma_mask = &udc_dmamask, | ||
73 | .coherent_dma_mask = 0xffffffff, | ||
74 | }, | ||
75 | .num_resources = ARRAY_SIZE(udc_resources), | ||
76 | .resource = udc_resources, | ||
77 | }; | ||
78 | |||
79 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
80 | { | ||
81 | pdata->udc_device = &udc_device; | ||
82 | } | ||
83 | |||
84 | #else | ||
85 | |||
86 | static inline void udc_device_init(struct omap_usb_config *pdata) | ||
87 | { | ||
88 | } | ||
89 | |||
90 | #endif | ||
91 | |||
92 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
93 | |||
94 | /* The dmamask must be set for OHCI to work */ | ||
95 | static u64 ohci_dmamask = ~(u32)0; | ||
96 | |||
97 | static struct resource ohci_resources[] = { | ||
98 | { | ||
99 | .start = OMAP_OHCI_BASE, | ||
100 | .end = OMAP_OHCI_BASE + 0xff, | ||
101 | .flags = IORESOURCE_MEM, | ||
102 | }, | ||
103 | { | ||
104 | .start = INT_USB_IRQ_HGEN, | ||
105 | .flags = IORESOURCE_IRQ, | ||
106 | }, | ||
107 | }; | ||
108 | |||
109 | static struct platform_device ohci_device = { | ||
110 | .name = "ohci", | ||
111 | .id = -1, | ||
112 | .dev = { | ||
113 | .dma_mask = &ohci_dmamask, | ||
114 | .coherent_dma_mask = 0xffffffff, | ||
115 | }, | ||
116 | .num_resources = ARRAY_SIZE(ohci_resources), | ||
117 | .resource = ohci_resources, | ||
118 | }; | ||
119 | |||
120 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
121 | { | ||
122 | pdata->ohci_device = &ohci_device; | ||
123 | } | ||
124 | |||
125 | #else | ||
126 | |||
127 | static inline void ohci_device_init(struct omap_usb_config *pdata) | ||
128 | { | ||
129 | } | ||
130 | |||
131 | #endif | ||
132 | |||
133 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | ||
134 | |||
135 | static struct resource otg_resources[] = { | ||
136 | /* order is significant! */ | ||
137 | { | ||
138 | .start = OTG_BASE, | ||
139 | .end = OTG_BASE + 0xff, | ||
140 | .flags = IORESOURCE_MEM, | ||
141 | }, { | ||
142 | .start = INT_USB_IRQ_OTG, | ||
143 | .flags = IORESOURCE_IRQ, | ||
144 | }, | ||
145 | }; | ||
146 | |||
147 | static struct platform_device otg_device = { | ||
148 | .name = "omap_otg", | ||
149 | .id = -1, | ||
150 | .num_resources = ARRAY_SIZE(otg_resources), | ||
151 | .resource = otg_resources, | ||
152 | }; | ||
153 | |||
154 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
155 | { | ||
156 | pdata->otg_device = &otg_device; | ||
157 | } | ||
158 | |||
159 | #else | ||
160 | |||
161 | static inline void otg_device_init(struct omap_usb_config *pdata) | ||
162 | { | ||
163 | } | ||
164 | |||
165 | #endif | ||
166 | |||
167 | static void omap2_usb_devconf_clear(u8 port, u32 mask) | ||
168 | { | ||
169 | u32 r; | ||
170 | |||
171 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
172 | r &= ~USBTXWRMODEI(port, mask); | ||
173 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
174 | } | ||
175 | |||
176 | static void omap2_usb_devconf_set(u8 port, u32 mask) | ||
177 | { | ||
178 | u32 r; | ||
179 | |||
180 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
181 | r |= USBTXWRMODEI(port, mask); | ||
182 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
183 | } | ||
184 | |||
185 | static void omap2_usb2_disable_5pinbitll(void) | ||
186 | { | ||
187 | u32 r; | ||
188 | |||
189 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
190 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | ||
191 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
192 | } | ||
193 | |||
194 | static void omap2_usb2_enable_5pinunitll(void) | ||
195 | { | ||
196 | u32 r; | ||
197 | |||
198 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | ||
199 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | ||
200 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | ||
201 | } | ||
202 | |||
203 | static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device) | ||
204 | { | ||
205 | u32 syscon1 = 0; | ||
206 | |||
207 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); | ||
208 | |||
209 | if (nwires == 0) | ||
210 | return 0; | ||
211 | |||
212 | if (is_device) | ||
213 | omap_mux_init_signal("usb0_puen", 0); | ||
214 | |||
215 | omap_mux_init_signal("usb0_dat", 0); | ||
216 | omap_mux_init_signal("usb0_txen", 0); | ||
217 | omap_mux_init_signal("usb0_se0", 0); | ||
218 | if (nwires != 3) | ||
219 | omap_mux_init_signal("usb0_rcv", 0); | ||
220 | |||
221 | switch (nwires) { | ||
222 | case 3: | ||
223 | syscon1 = 2; | ||
224 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
225 | break; | ||
226 | case 4: | ||
227 | syscon1 = 1; | ||
228 | omap2_usb_devconf_set(0, USB_BIDIR); | ||
229 | break; | ||
230 | case 6: | ||
231 | syscon1 = 3; | ||
232 | omap_mux_init_signal("usb0_vp", 0); | ||
233 | omap_mux_init_signal("usb0_vm", 0); | ||
234 | omap2_usb_devconf_set(0, USB_UNIDIR); | ||
235 | break; | ||
236 | default: | ||
237 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
238 | 0, nwires); | ||
239 | } | ||
240 | |||
241 | return syscon1 << 16; | ||
242 | } | ||
243 | |||
244 | static u32 __init omap2_usb1_init(unsigned nwires) | ||
245 | { | ||
246 | u32 syscon1 = 0; | ||
247 | |||
248 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); | ||
249 | |||
250 | if (nwires == 0) | ||
251 | return 0; | ||
252 | |||
253 | /* NOTE: board-specific code must set up pin muxing for usb1, | ||
254 | * since each signal could come out on either of two balls. | ||
255 | */ | ||
256 | |||
257 | switch (nwires) { | ||
258 | case 2: | ||
259 | /* NOTE: board-specific code must override this setting if | ||
260 | * this TLL link is not using DP/DM | ||
261 | */ | ||
262 | syscon1 = 1; | ||
263 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); | ||
264 | break; | ||
265 | case 3: | ||
266 | syscon1 = 2; | ||
267 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
268 | break; | ||
269 | case 4: | ||
270 | syscon1 = 1; | ||
271 | omap2_usb_devconf_set(1, USB_BIDIR); | ||
272 | break; | ||
273 | case 6: | ||
274 | default: | ||
275 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
276 | 1, nwires); | ||
277 | } | ||
278 | |||
279 | return syscon1 << 20; | ||
280 | } | ||
281 | |||
282 | static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup) | ||
283 | { | ||
284 | u32 syscon1 = 0; | ||
285 | |||
286 | omap2_usb2_disable_5pinbitll(); | ||
287 | alt_pingroup = 0; | ||
288 | |||
289 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | ||
290 | if (alt_pingroup || nwires == 0) | ||
291 | return 0; | ||
292 | |||
293 | omap_mux_init_signal("usb2_dat", 0); | ||
294 | omap_mux_init_signal("usb2_se0", 0); | ||
295 | if (nwires > 2) | ||
296 | omap_mux_init_signal("usb2_txen", 0); | ||
297 | if (nwires > 3) | ||
298 | omap_mux_init_signal("usb2_rcv", 0); | ||
299 | |||
300 | switch (nwires) { | ||
301 | case 2: | ||
302 | /* NOTE: board-specific code must override this setting if | ||
303 | * this TLL link is not using DP/DM | ||
304 | */ | ||
305 | syscon1 = 1; | ||
306 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); | ||
307 | break; | ||
308 | case 3: | ||
309 | syscon1 = 2; | ||
310 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
311 | break; | ||
312 | case 4: | ||
313 | syscon1 = 1; | ||
314 | omap2_usb_devconf_set(2, USB_BIDIR); | ||
315 | break; | ||
316 | case 5: | ||
317 | /* NOTE: board-specific code must mux this setting depending | ||
318 | * on TLL link using DP/DM. Something must also | ||
319 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | ||
320 | * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0 | ||
321 | * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0 | ||
322 | */ | ||
323 | |||
324 | syscon1 = 3; | ||
325 | omap2_usb2_enable_5pinunitll(); | ||
326 | break; | ||
327 | case 6: | ||
328 | default: | ||
329 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | ||
330 | 2, nwires); | ||
331 | } | ||
332 | |||
333 | return syscon1 << 24; | ||
334 | } | ||
335 | |||
336 | void __init omap2_usbfs_init(struct omap_usb_config *pdata) | ||
337 | { | ||
338 | struct clk *ick; | ||
339 | |||
340 | if (!cpu_is_omap24xx()) | ||
341 | return; | ||
342 | |||
343 | ick = clk_get(NULL, "usb_l4_ick"); | ||
344 | if (IS_ERR(ick)) | ||
345 | return; | ||
346 | |||
347 | clk_enable(ick); | ||
348 | pdata->usb0_init = omap2_usb0_init; | ||
349 | pdata->usb1_init = omap2_usb1_init; | ||
350 | pdata->usb2_init = omap2_usb2_init; | ||
351 | udc_device_init(pdata); | ||
352 | ohci_device_init(pdata); | ||
353 | otg_device_init(pdata); | ||
354 | omap_otg_init(pdata); | ||
355 | clk_disable(ick); | ||
356 | clk_put(ick); | ||
357 | } | ||
358 | |||
359 | #endif | ||
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h index 16a1b092cf36..a7c43c1042be 100644 --- a/arch/arm/mach-omap2/voltage.h +++ b/arch/arm/mach-omap2/voltage.h | |||
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void); | |||
156 | 156 | ||
157 | extern void omap2xxx_voltagedomains_init(void); | 157 | extern void omap2xxx_voltagedomains_init(void); |
158 | extern void omap3xxx_voltagedomains_init(void); | 158 | extern void omap3xxx_voltagedomains_init(void); |
159 | extern void am33xx_voltagedomains_init(void); | ||
159 | extern void omap44xx_voltagedomains_init(void); | 160 | extern void omap44xx_voltagedomains_init(void); |
160 | 161 | ||
161 | struct voltagedomain *voltdm_lookup(const char *name); | 162 | struct voltagedomain *voltdm_lookup(const char *name); |
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c new file mode 100644 index 000000000000..965458dc0cb9 --- /dev/null +++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * AM33XX voltage domain data | ||
3 | * | ||
4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License as | ||
8 | * published by the Free Software Foundation version 2. | ||
9 | * | ||
10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | ||
11 | * kind, whether express or implied; without even the implied warranty | ||
12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/init.h> | ||
18 | |||
19 | #include "voltage.h" | ||
20 | |||
21 | static struct voltagedomain am33xx_voltdm_mpu = { | ||
22 | .name = "mpu", | ||
23 | }; | ||
24 | |||
25 | static struct voltagedomain am33xx_voltdm_core = { | ||
26 | .name = "core", | ||
27 | }; | ||
28 | |||
29 | static struct voltagedomain am33xx_voltdm_rtc = { | ||
30 | .name = "rtc", | ||
31 | }; | ||
32 | |||
33 | static struct voltagedomain *voltagedomains_am33xx[] __initdata = { | ||
34 | &am33xx_voltdm_mpu, | ||
35 | &am33xx_voltdm_core, | ||
36 | &am33xx_voltdm_rtc, | ||
37 | NULL, | ||
38 | }; | ||
39 | |||
40 | void __init am33xx_voltagedomains_init(void) | ||
41 | { | ||
42 | voltdm_init(voltagedomains_am33xx); | ||
43 | } | ||
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c index 8702ecfaab30..14a81c2317a4 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2416.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c | |||
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = { | |||
144 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), | 144 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), |
145 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), | 145 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), |
146 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), | 146 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), |
147 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk), | 147 | /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */ |
148 | CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk), | ||
148 | }; | 149 | }; |
149 | 150 | ||
150 | void __init s3c2416_init_clocks(int xtal) | 151 | void __init s3c2416_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c index 414364eb426c..cb2883d553b5 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2440.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c | |||
@@ -106,7 +106,7 @@ static struct clk s3c2440_clk_cam_upll = { | |||
106 | static struct clk s3c2440_clk_ac97 = { | 106 | static struct clk s3c2440_clk_ac97 = { |
107 | .name = "ac97", | 107 | .name = "ac97", |
108 | .enable = s3c2410_clkcon_enable, | 108 | .enable = s3c2410_clkcon_enable, |
109 | .ctrlbit = S3C2440_CLKCON_CAMERA, | 109 | .ctrlbit = S3C2440_CLKCON_AC97, |
110 | }; | 110 | }; |
111 | 111 | ||
112 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) | 112 | static unsigned long s3c2440_fclk_n_getrate(struct clk *clk) |
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c index a4c5a520d994..7f689ce1be61 100644 --- a/arch/arm/mach-s3c24xx/clock-s3c2443.c +++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c | |||
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = { | |||
181 | 181 | ||
182 | static struct clk_lookup s3c2443_clk_lookup[] = { | 182 | static struct clk_lookup s3c2443_clk_lookup[] = { |
183 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), | 183 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), |
184 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk), | 184 | CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), |
185 | }; | 185 | }; |
186 | 186 | ||
187 | void __init s3c2443_init_clocks(int xtal) | 187 | void __init s3c2443_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c index aeeb2be283fa..aeb4a24ff3ed 100644 --- a/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/arch/arm/mach-s3c24xx/common-s3c2443.c | |||
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = { | |||
559 | 559 | ||
560 | static struct clk hsspi_clk = { | 560 | static struct clk hsspi_clk = { |
561 | .name = "spi", | 561 | .name = "spi", |
562 | .devname = "s3c64xx-spi.0", | 562 | .devname = "s3c2443-spi.0", |
563 | .parent = &clk_p, | 563 | .parent = &clk_p, |
564 | .enable = s3c2443_clkcon_enable_p, | 564 | .enable = s3c2443_clkcon_enable_p, |
565 | .ctrlbit = S3C2443_PCLKCON_HSSPI, | 565 | .ctrlbit = S3C2443_PCLKCON_HSSPI, |
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = { | |||
633 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | 633 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), |
634 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), | 634 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), |
635 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), | 635 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), |
636 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk), | 636 | CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk), |
637 | }; | 637 | }; |
638 | 638 | ||
639 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, | 639 | void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, |
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c index 084604be6ad1..87e75a250d5e 100644 --- a/arch/arm/mach-s3c24xx/common-smdk.c +++ b/arch/arm/mach-s3c24xx/common-smdk.c | |||
@@ -182,19 +182,21 @@ static struct platform_device __initdata *smdk_devs[] = { | |||
182 | &smdk_led7, | 182 | &smdk_led7, |
183 | }; | 183 | }; |
184 | 184 | ||
185 | static const struct gpio smdk_led_gpios[] = { | ||
186 | { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL }, | ||
187 | { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL }, | ||
188 | { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL }, | ||
189 | { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL }, | ||
190 | }; | ||
191 | |||
185 | void __init smdk_machine_init(void) | 192 | void __init smdk_machine_init(void) |
186 | { | 193 | { |
187 | /* Configure the LEDs (even if we have no LED support)*/ | 194 | /* Configure the LEDs (even if we have no LED support)*/ |
188 | 195 | ||
189 | s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT); | 196 | int ret = gpio_request_array(smdk_led_gpios, |
190 | s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT); | 197 | ARRAY_SIZE(smdk_led_gpios)); |
191 | s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT); | 198 | if (!WARN_ON(ret < 0)) |
192 | s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT); | 199 | gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios)); |
193 | |||
194 | s3c2410_gpio_setpin(S3C2410_GPF(4), 1); | ||
195 | s3c2410_gpio_setpin(S3C2410_GPF(5), 1); | ||
196 | s3c2410_gpio_setpin(S3C2410_GPF(6), 1); | ||
197 | s3c2410_gpio_setpin(S3C2410_GPF(7), 1); | ||
198 | 200 | ||
199 | if (machine_is_smdk2443()) | 201 | if (machine_is_smdk2443()) |
200 | smdk_nand_info.twrph0 = 50; | 202 | smdk_nand_info.twrph0 = 50; |
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 56cdd34cce41..0c9e9a785ef6 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c | |||
@@ -41,7 +41,6 @@ | |||
41 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
42 | #include <asm/mach/map.h> | 42 | #include <asm/mach/map.h> |
43 | 43 | ||
44 | #include <mach/regs-clock.h> | ||
45 | #include <mach/regs-gpio.h> | 44 | #include <mach/regs-gpio.h> |
46 | #include <plat/regs-serial.h> | 45 | #include <plat/regs-serial.h> |
47 | 46 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h deleted file mode 100644 index 4c38b39b741d..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h +++ /dev/null | |||
@@ -1,40 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/bast-pmu.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2004 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * Vincent Sanders <vince@simtec.co.uk> | ||
6 | * | ||
7 | * Machine BAST - Power Management chip | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_BASTPMU_H | ||
15 | #define __ASM_ARCH_BASTPMU_H "08_OCT_2004" | ||
16 | |||
17 | #define BASTPMU_REG_IDENT (0x00) | ||
18 | #define BASTPMU_REG_VERSION (0x01) | ||
19 | #define BASTPMU_REG_DDCCTRL (0x02) | ||
20 | #define BASTPMU_REG_POWER (0x03) | ||
21 | #define BASTPMU_REG_RESET (0x04) | ||
22 | #define BASTPMU_REG_GWO (0x05) | ||
23 | #define BASTPMU_REG_WOL (0x06) | ||
24 | #define BASTPMU_REG_WOR (0x07) | ||
25 | #define BASTPMU_REG_UID (0x09) | ||
26 | |||
27 | #define BASTPMU_EEPROM (0xC0) | ||
28 | |||
29 | #define BASTPMU_EEP_UID (BASTPMU_EEPROM + 0) | ||
30 | #define BASTPMU_EEP_WOL (BASTPMU_EEPROM + 8) | ||
31 | #define BASTPMU_EEP_WOR (BASTPMU_EEPROM + 9) | ||
32 | |||
33 | #define BASTPMU_IDENT_0 0x53 | ||
34 | #define BASTPMU_IDENT_1 0x42 | ||
35 | #define BASTPMU_IDENT_2 0x50 | ||
36 | #define BASTPMU_IDENT_3 0x4d | ||
37 | |||
38 | #define BASTPMU_RESET_GUARD (0x55) | ||
39 | |||
40 | #endif /* __ASM_ARCH_BASTPMU_H */ | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h index 019ea86057f6..3890a05948fb 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h +++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h | |||
@@ -93,26 +93,5 @@ enum s3c_gpio_number { | |||
93 | #define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) | 93 | #define S3C2410_GPL(_nr) (S3C2410_GPIO_L_START + (_nr)) |
94 | #define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) | 94 | #define S3C2410_GPM(_nr) (S3C2410_GPIO_M_START + (_nr)) |
95 | 95 | ||
96 | /* compatibility until drivers can be modified */ | ||
97 | |||
98 | #define S3C2410_GPA0 S3C2410_GPA(0) | ||
99 | #define S3C2410_GPA1 S3C2410_GPA(1) | ||
100 | #define S3C2410_GPA3 S3C2410_GPA(3) | ||
101 | #define S3C2410_GPA7 S3C2410_GPA(7) | ||
102 | |||
103 | #define S3C2410_GPE0 S3C2410_GPE(0) | ||
104 | #define S3C2410_GPE1 S3C2410_GPE(1) | ||
105 | #define S3C2410_GPE2 S3C2410_GPE(2) | ||
106 | #define S3C2410_GPE3 S3C2410_GPE(3) | ||
107 | #define S3C2410_GPE4 S3C2410_GPE(4) | ||
108 | #define S3C2410_GPE5 S3C2410_GPE(5) | ||
109 | #define S3C2410_GPE6 S3C2410_GPE(6) | ||
110 | #define S3C2410_GPE7 S3C2410_GPE(7) | ||
111 | #define S3C2410_GPE8 S3C2410_GPE(8) | ||
112 | #define S3C2410_GPE9 S3C2410_GPE(9) | ||
113 | #define S3C2410_GPE10 S3C2410_GPE(10) | ||
114 | |||
115 | #define S3C2410_GPH10 S3C2410_GPH(10) | ||
116 | |||
117 | #endif /* __MACH_GPIONRS_H */ | 96 | #endif /* __MACH_GPIONRS_H */ |
118 | 97 | ||
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h index 3a56a229cac6..217393482153 100644 --- a/arch/arm/mach-s3c24xx/include/mach/gta02.h +++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h | |||
@@ -3,82 +3,13 @@ | |||
3 | 3 | ||
4 | #include <mach/regs-gpio.h> | 4 | #include <mach/regs-gpio.h> |
5 | 5 | ||
6 | /* Different hardware revisions, passed in ATAG_REVISION by u-boot */ | ||
7 | #define GTA02v1_SYSTEM_REV 0x00000310 | ||
8 | #define GTA02v2_SYSTEM_REV 0x00000320 | ||
9 | #define GTA02v3_SYSTEM_REV 0x00000330 | ||
10 | #define GTA02v4_SYSTEM_REV 0x00000340 | ||
11 | #define GTA02v5_SYSTEM_REV 0x00000350 | ||
12 | /* since A7 is basically same as A6, we use A6 PCB ID */ | ||
13 | #define GTA02v6_SYSTEM_REV 0x00000360 | ||
14 | |||
15 | #define GTA02_GPIO_n3DL_GSM S3C2410_GPA(13) /* v1 + v2 + v3 only */ | ||
16 | |||
17 | #define GTA02_GPIO_PWR_LED1 S3C2410_GPB(0) | ||
18 | #define GTA02_GPIO_PWR_LED2 S3C2410_GPB(1) | ||
19 | #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) | 6 | #define GTA02_GPIO_AUX_LED S3C2410_GPB(2) |
20 | #define GTA02_GPIO_VIBRATOR_ON S3C2410_GPB(3) | ||
21 | #define GTA02_GPIO_MODEM_RST S3C2410_GPB(5) | ||
22 | #define GTA02_GPIO_BT_EN S3C2410_GPB(6) | ||
23 | #define GTA02_GPIO_MODEM_ON S3C2410_GPB(7) | ||
24 | #define GTA02_GPIO_EXTINT8 S3C2410_GPB(8) | ||
25 | #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) | 7 | #define GTA02_GPIO_USB_PULLUP S3C2410_GPB(9) |
26 | |||
27 | #define GTA02_GPIO_PIO5 S3C2410_GPC(5) /* v3 + v4 only */ | ||
28 | |||
29 | #define GTA02v3_GPIO_nG1_CS S3C2410_GPD(12) /* v3 + v4 only */ | ||
30 | #define GTA02v3_GPIO_nG2_CS S3C2410_GPD(13) /* v3 + v4 only */ | ||
31 | #define GTA02v5_GPIO_HDQ S3C2410_GPD(14) /* v5 + */ | ||
32 | |||
33 | #define GTA02_GPIO_nG1_INT S3C2410_GPF(0) | ||
34 | #define GTA02_GPIO_IO1 S3C2410_GPF(1) | ||
35 | #define GTA02_GPIO_PIO_2 S3C2410_GPF(2) /* v2 + v3 + v4 only */ | ||
36 | #define GTA02_GPIO_JACK_INSERT S3C2410_GPF(4) | ||
37 | #define GTA02_GPIO_WLAN_GPIO1 S3C2410_GPF(5) /* v2 + v3 + v4 only */ | ||
38 | #define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) | 8 | #define GTA02_GPIO_AUX_KEY S3C2410_GPF(6) |
39 | #define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) | 9 | #define GTA02_GPIO_HOLD_KEY S3C2410_GPF(7) |
40 | |||
41 | #define GTA02_GPIO_3D_IRQ S3C2410_GPG(4) | ||
42 | #define GTA02v2_GPIO_nG2_INT S3C2410_GPG(8) /* v2 + v3 + v4 only */ | ||
43 | #define GTA02v3_GPIO_nUSB_OC S3C2410_GPG(9) /* v3 + v4 only */ | ||
44 | #define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */ | ||
45 | #define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */ | ||
46 | |||
47 | #define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */ | 10 | #define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */ |
48 | #define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2) | ||
49 | #define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */ | 11 | #define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */ |
50 | #define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */ | ||
51 | #define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4) | ||
52 | #define GTA02_GPIO_3D_RESET S3C2410_GPJ(5) | ||
53 | #define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */ | ||
54 | #define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7) | ||
55 | #define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8) | ||
56 | #define GTA02_GPIO_KEEPACT S3C2410_GPJ(8) | ||
57 | #define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10) | ||
58 | #define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */ | ||
59 | #define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */ | ||
60 | 12 | ||
61 | #define GTA02_IRQ_GSENSOR_1 IRQ_EINT0 | ||
62 | #define GTA02_IRQ_MODEM IRQ_EINT1 | ||
63 | #define GTA02_IRQ_PIO_2 IRQ_EINT2 /* v2 + v3 + v4 only */ | ||
64 | #define GTA02_IRQ_nJACK_INSERT IRQ_EINT4 | ||
65 | #define GTA02_IRQ_WLAN_GPIO1 IRQ_EINT5 | ||
66 | #define GTA02_IRQ_AUX IRQ_EINT6 | ||
67 | #define GTA02_IRQ_nHOLD IRQ_EINT7 | ||
68 | #define GTA02_IRQ_PCF50633 IRQ_EINT9 | 13 | #define GTA02_IRQ_PCF50633 IRQ_EINT9 |
69 | #define GTA02_IRQ_3D IRQ_EINT12 | ||
70 | #define GTA02_IRQ_GSENSOR_2 IRQ_EINT16 /* v2 + v3 + v4 only */ | ||
71 | #define GTA02v3_IRQ_nUSB_OC IRQ_EINT17 /* v3 + v4 only */ | ||
72 | #define GTA02v3_IRQ_nUSB_FLT IRQ_EINT18 /* v3 + v4 only */ | ||
73 | #define GTA02v3_IRQ_nGSM_OC IRQ_EINT19 /* v3 + v4 only */ | ||
74 | |||
75 | /* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */ | ||
76 | #define GTA02_PCB_ID1_0 S3C2410_GPC(13) | ||
77 | #define GTA02_PCB_ID1_1 S3C2410_GPC(15) | ||
78 | #define GTA02_PCB_ID1_2 S3C2410_GPD(0) | ||
79 | #define GTA02_PCB_ID2_0 S3C2410_GPD(3) | ||
80 | #define GTA02_PCB_ID2_1 S3C2410_GPD(4) | ||
81 | |||
82 | int gta02_get_pcb_revision(void); | ||
83 | 14 | ||
84 | #endif /* _GTA02_H */ | 15 | #endif /* _GTA02_H */ |
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h index cac1ad6b582c..a11a638bd599 100644 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | |||
@@ -302,7 +302,7 @@ | |||
302 | /* S3C2410: | 302 | /* S3C2410: |
303 | * Port G consists of 8 GPIO/IRQ/Special function | 303 | * Port G consists of 8 GPIO/IRQ/Special function |
304 | * | 304 | * |
305 | * GPGCON has 2 bits for each of the input pins on port F | 305 | * GPGCON has 2 bits for each of the input pins on port G |
306 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 306 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
307 | * | 307 | * |
308 | * pull up works like all other ports. | 308 | * pull up works like all other ports. |
@@ -366,7 +366,7 @@ | |||
366 | 366 | ||
367 | /* Port H consists of11 GPIO/serial/Misc pins | 367 | /* Port H consists of11 GPIO/serial/Misc pins |
368 | * | 368 | * |
369 | * GPGCON has 2 bits for each of the input pins on port F | 369 | * GPHCON has 2 bits for each of the input pins on port H |
370 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func | 370 | * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func |
371 | * | 371 | * |
372 | * pull up works like all other ports. | 372 | * pull up works like all other ports. |
@@ -427,6 +427,19 @@ | |||
427 | * for the 2412/2413 from the 2410/2440/2442 | 427 | * for the 2412/2413 from the 2410/2440/2442 |
428 | */ | 428 | */ |
429 | 429 | ||
430 | /* | ||
431 | * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits | ||
432 | * for each of the pins on port J. | ||
433 | * 00 - input, 01 output, 10 - camera | ||
434 | * | ||
435 | * Pull up works like all other ports. | ||
436 | */ | ||
437 | |||
438 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
439 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
440 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
441 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
442 | |||
430 | /* S3C2443 and above */ | 443 | /* S3C2443 and above */ |
431 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) | 444 | #define S3C2440_GPJCON S3C2410_GPIOREG(0xD0) |
432 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) | 445 | #define S3C2440_GPJDAT S3C2410_GPIOREG(0xD4) |
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h deleted file mode 100644 index 19575e061114..000000000000 --- a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h | ||
2 | * | ||
3 | * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C2440 GPIO J register definitions | ||
11 | */ | ||
12 | |||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_GPIOJ_H | ||
15 | #define __ASM_ARCH_REGS_GPIOJ_H "gpioj" | ||
16 | |||
17 | /* Port J consists of 13 GPIO/Camera pins | ||
18 | * | ||
19 | * GPJCON has 2 bits for each of the input pins on port F | ||
20 | * 00 = 0 input, 1 output, 2 Camera | ||
21 | * | ||
22 | * pull up works like all other ports. | ||
23 | */ | ||
24 | |||
25 | #define S3C2413_GPJCON S3C2410_GPIOREG(0x80) | ||
26 | #define S3C2413_GPJDAT S3C2410_GPIOREG(0x84) | ||
27 | #define S3C2413_GPJUP S3C2410_GPIOREG(0x88) | ||
28 | #define S3C2413_GPJSLPCON S3C2410_GPIOREG(0x8C) | ||
29 | |||
30 | #define S3C2440_GPJ0_OUTP (0x01 << 0) | ||
31 | #define S3C2440_GPJ0_CAMDATA0 (0x02 << 0) | ||
32 | |||
33 | #define S3C2440_GPJ1_OUTP (0x01 << 2) | ||
34 | #define S3C2440_GPJ1_CAMDATA1 (0x02 << 2) | ||
35 | |||
36 | #define S3C2440_GPJ2_OUTP (0x01 << 4) | ||
37 | #define S3C2440_GPJ2_CAMDATA2 (0x02 << 4) | ||
38 | |||
39 | #define S3C2440_GPJ3_OUTP (0x01 << 6) | ||
40 | #define S3C2440_GPJ3_CAMDATA3 (0x02 << 6) | ||
41 | |||
42 | #define S3C2440_GPJ4_OUTP (0x01 << 8) | ||
43 | #define S3C2440_GPJ4_CAMDATA4 (0x02 << 8) | ||
44 | |||
45 | #define S3C2440_GPJ5_OUTP (0x01 << 10) | ||
46 | #define S3C2440_GPJ5_CAMDATA5 (0x02 << 10) | ||
47 | |||
48 | #define S3C2440_GPJ6_OUTP (0x01 << 12) | ||
49 | #define S3C2440_GPJ6_CAMDATA6 (0x02 << 12) | ||
50 | |||
51 | #define S3C2440_GPJ7_OUTP (0x01 << 14) | ||
52 | #define S3C2440_GPJ7_CAMDATA7 (0x02 << 14) | ||
53 | |||
54 | #define S3C2440_GPJ8_OUTP (0x01 << 16) | ||
55 | #define S3C2440_GPJ8_CAMPCLK (0x02 << 16) | ||
56 | |||
57 | #define S3C2440_GPJ9_OUTP (0x01 << 18) | ||
58 | #define S3C2440_GPJ9_CAMVSYNC (0x02 << 18) | ||
59 | |||
60 | #define S3C2440_GPJ10_OUTP (0x01 << 20) | ||
61 | #define S3C2440_GPJ10_CAMHREF (0x02 << 20) | ||
62 | |||
63 | #define S3C2440_GPJ11_OUTP (0x01 << 22) | ||
64 | #define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22) | ||
65 | |||
66 | #define S3C2440_GPJ12_OUTP (0x01 << 24) | ||
67 | #define S3C2440_GPJ12_CAMRESET (0x02 << 24) | ||
68 | |||
69 | #endif /* __ASM_ARCH_REGS_GPIOJ_H */ | ||
70 | |||
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c index 0f29f64a3eeb..92e1f93a6bca 100644 --- a/arch/arm/mach-s3c24xx/mach-gta02.c +++ b/arch/arm/mach-s3c24xx/mach-gta02.c | |||
@@ -71,7 +71,6 @@ | |||
71 | 71 | ||
72 | #include <mach/regs-irq.h> | 72 | #include <mach/regs-irq.h> |
73 | #include <mach/regs-gpio.h> | 73 | #include <mach/regs-gpio.h> |
74 | #include <mach/regs-gpioj.h> | ||
75 | #include <mach/fb.h> | 74 | #include <mach/fb.h> |
76 | 75 | ||
77 | #include <plat/usb-control.h> | 76 | #include <plat/usb-control.h> |
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c index f092b188ab70..bd6d2525debe 100644 --- a/arch/arm/mach-s3c24xx/mach-mini2440.c +++ b/arch/arm/mach-s3c24xx/mach-mini2440.c | |||
@@ -634,8 +634,8 @@ static void __init mini2440_init(void) | |||
634 | s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); | 634 | s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND); |
635 | 635 | ||
636 | /* Turn the backlight early on */ | 636 | /* Turn the backlight early on */ |
637 | WARN_ON(gpio_request(S3C2410_GPG(4), "backlight")); | 637 | WARN_ON(gpio_request_one(S3C2410_GPG(4), GPIOF_OUT_INIT_HIGH, NULL)); |
638 | gpio_direction_output(S3C2410_GPG(4), 1); | 638 | gpio_free(S3C2410_GPG(4)); |
639 | 639 | ||
640 | /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ | 640 | /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */ |
641 | s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); | 641 | s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c index b868dddcb836..678bbca2b5e5 100644 --- a/arch/arm/mach-s3c24xx/mach-qt2410.c +++ b/arch/arm/mach-s3c24xx/mach-qt2410.c | |||
@@ -47,7 +47,6 @@ | |||
47 | #include <asm/irq.h> | 47 | #include <asm/irq.h> |
48 | #include <asm/mach-types.h> | 48 | #include <asm/mach-types.h> |
49 | 49 | ||
50 | #include <mach/regs-gpio.h> | ||
51 | #include <mach/leds-gpio.h> | 50 | #include <mach/leds-gpio.h> |
52 | #include <mach/regs-lcd.h> | 51 | #include <mach/regs-lcd.h> |
53 | #include <plat/regs-serial.h> | 52 | #include <plat/regs-serial.h> |
@@ -325,8 +324,9 @@ static void __init qt2410_machine_init(void) | |||
325 | } | 324 | } |
326 | s3c24xx_fb_set_platdata(&qt2410_fb_info); | 325 | s3c24xx_fb_set_platdata(&qt2410_fb_info); |
327 | 326 | ||
328 | s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT); | 327 | /* set initial state of the LED GPIO */ |
329 | s3c2410_gpio_setpin(S3C2410_GPB(0), 1); | 328 | WARN_ON(gpio_request_one(S3C2410_GPB(0), GPIOF_OUT_INIT_HIGH, NULL)); |
329 | gpio_free(S3C2410_GPB(0)); | ||
330 | 330 | ||
331 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); | 331 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); |
332 | s3c_i2c0_set_platdata(NULL); | 332 | s3c_i2c0_set_platdata(NULL); |
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c index a6762aae4727..7ee73f27f207 100644 --- a/arch/arm/mach-s3c24xx/mach-rx1950.c +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c | |||
@@ -42,7 +42,6 @@ | |||
42 | #include <asm/mach-types.h> | 42 | #include <asm/mach-types.h> |
43 | 43 | ||
44 | #include <mach/regs-gpio.h> | 44 | #include <mach/regs-gpio.h> |
45 | #include <mach/regs-gpioj.h> | ||
46 | #include <mach/regs-lcd.h> | 45 | #include <mach/regs-lcd.h> |
47 | #include <mach/h1940.h> | 46 | #include <mach/h1940.h> |
48 | #include <mach/fb.h> | 47 | #include <mach/fb.h> |
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c index 03f706dd6009..949ae05e07c5 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2410.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c | |||
@@ -77,8 +77,10 @@ static void s3c2410_pm_prepare(void) | |||
77 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); | 77 | __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); |
78 | } | 78 | } |
79 | 79 | ||
80 | if ( machine_is_aml_m5900() ) | 80 | if (machine_is_aml_m5900()) { |
81 | s3c2410_gpio_setpin(S3C2410_GPF(2), 1); | 81 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL); |
82 | gpio_free(S3C2410_GPF(2)); | ||
83 | } | ||
82 | 84 | ||
83 | if (machine_is_rx1950()) { | 85 | if (machine_is_rx1950()) { |
84 | /* According to S3C2442 user's manual, page 7-17, | 86 | /* According to S3C2442 user's manual, page 7-17, |
@@ -103,8 +105,10 @@ static void s3c2410_pm_resume(void) | |||
103 | tmp &= S3C2410_GSTATUS2_OFFRESET; | 105 | tmp &= S3C2410_GSTATUS2_OFFRESET; |
104 | __raw_writel(tmp, S3C2410_GSTATUS2); | 106 | __raw_writel(tmp, S3C2410_GSTATUS2); |
105 | 107 | ||
106 | if ( machine_is_aml_m5900() ) | 108 | if (machine_is_aml_m5900()) { |
107 | s3c2410_gpio_setpin(S3C2410_GPF(2), 0); | 109 | gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL); |
110 | gpio_free(S3C2410_GPF(2)); | ||
111 | } | ||
108 | } | 112 | } |
109 | 113 | ||
110 | struct syscore_ops s3c2410_pm_syscore_ops = { | 114 | struct syscore_ops s3c2410_pm_syscore_ops = { |
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c index d04588506ec4..c60f67a75aff 100644 --- a/arch/arm/mach-s3c24xx/pm-s3c2412.c +++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
27 | 27 | ||
28 | #include <mach/regs-power.h> | 28 | #include <mach/regs-power.h> |
29 | #include <mach/regs-gpioj.h> | ||
30 | #include <mach/regs-gpio.h> | 29 | #include <mach/regs-gpio.h> |
31 | #include <mach/regs-dsc.h> | 30 | #include <mach/regs-dsc.h> |
32 | 31 | ||
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c index d4bc7f960bbb..6c5f4031ff0c 100644 --- a/arch/arm/mach-s3c24xx/s3c2412.c +++ b/arch/arm/mach-s3c24xx/s3c2412.c | |||
@@ -39,7 +39,6 @@ | |||
39 | #include <plat/regs-serial.h> | 39 | #include <plat/regs-serial.h> |
40 | #include <mach/regs-power.h> | 40 | #include <mach/regs-power.h> |
41 | #include <mach/regs-gpio.h> | 41 | #include <mach/regs-gpio.h> |
42 | #include <mach/regs-gpioj.h> | ||
43 | #include <mach/regs-dsc.h> | 42 | #include <mach/regs-dsc.h> |
44 | #include <plat/regs-spi.h> | 43 | #include <plat/regs-spi.h> |
45 | #include <mach/regs-s3c2412.h> | 44 | #include <mach/regs-s3c2412.h> |
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c index 6f74118f60c6..b0b60a1154d6 100644 --- a/arch/arm/mach-s3c24xx/s3c244x.c +++ b/arch/arm/mach-s3c24xx/s3c244x.c | |||
@@ -36,7 +36,6 @@ | |||
36 | #include <mach/regs-clock.h> | 36 | #include <mach/regs-clock.h> |
37 | #include <plat/regs-serial.h> | 37 | #include <plat/regs-serial.h> |
38 | #include <mach/regs-gpio.h> | 38 | #include <mach/regs-gpio.h> |
39 | #include <mach/regs-gpioj.h> | ||
40 | #include <mach/regs-dsc.h> | 39 | #include <mach/regs-dsc.h> |
41 | 40 | ||
42 | #include <plat/s3c2410.h> | 41 | #include <plat/s3c2410.h> |
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c index 5712c85f39b1..3d47e023ce94 100644 --- a/arch/arm/mach-s3c24xx/setup-spi.c +++ b/arch/arm/mach-s3c24xx/setup-spi.c | |||
@@ -13,20 +13,12 @@ | |||
13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
14 | 14 | ||
15 | #include <plat/gpio-cfg.h> | 15 | #include <plat/gpio-cfg.h> |
16 | #include <plat/s3c64xx-spi.h> | ||
17 | 16 | ||
18 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
19 | #include <mach/regs-gpio.h> | 18 | #include <mach/regs-gpio.h> |
20 | 19 | ||
21 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 20 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
22 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 21 | int s3c64xx_spi0_cfg_gpio(void) |
23 | .fifo_lvl_mask = 0x7f, | ||
24 | .rx_lvl_offset = 13, | ||
25 | .tx_st_done = 21, | ||
26 | .high_speed = 1, | ||
27 | }; | ||
28 | |||
29 | int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) | ||
30 | { | 22 | { |
31 | /* enable hsspi bit in misccr */ | 23 | /* enable hsspi bit in misccr */ |
32 | s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); | 24 | s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); |
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c index ed2638663675..4e11affce3a8 100644 --- a/arch/arm/mach-s3c24xx/setup-ts.c +++ b/arch/arm/mach-s3c24xx/setup-ts.c | |||
@@ -16,7 +16,6 @@ | |||
16 | struct platform_device; /* don't need the contents */ | 16 | struct platform_device; /* don't need the contents */ |
17 | 17 | ||
18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
19 | #include <mach/regs-gpio.h> | ||
20 | 19 | ||
21 | /** | 20 | /** |
22 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems | 21 | * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems |
@@ -27,8 +26,5 @@ struct platform_device; /* don't need the contents */ | |||
27 | */ | 26 | */ |
28 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) | 27 | void s3c24xx_ts_cfg_gpio(struct platform_device *dev) |
29 | { | 28 | { |
30 | s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON); | 29 | s3c_gpio_cfgpin_range(S3C2410_GPG(12), 4, S3C_GPIO_SFN(3)); |
31 | s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON); | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON); | ||
33 | s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON); | ||
34 | } | 30 | } |
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c index 52f079a691cb..28041e83dc82 100644 --- a/arch/arm/mach-s3c64xx/clock.c +++ b/arch/arm/mach-s3c64xx/clock.c | |||
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = { | |||
178 | .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, | 178 | .ctrlbit = S3C_CLKCON_PCLK_KEYPAD, |
179 | }, { | 179 | }, { |
180 | .name = "spi", | 180 | .name = "spi", |
181 | .devname = "s3c64xx-spi.0", | 181 | .devname = "s3c6410-spi.0", |
182 | .parent = &clk_p, | 182 | .parent = &clk_p, |
183 | .enable = s3c64xx_pclk_ctrl, | 183 | .enable = s3c64xx_pclk_ctrl, |
184 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, | 184 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, |
185 | }, { | 185 | }, { |
186 | .name = "spi", | 186 | .name = "spi", |
187 | .devname = "s3c64xx-spi.1", | 187 | .devname = "s3c6410-spi.1", |
188 | .parent = &clk_p, | 188 | .parent = &clk_p, |
189 | .enable = s3c64xx_pclk_ctrl, | 189 | .enable = s3c64xx_pclk_ctrl, |
190 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, | 190 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, |
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = { | |||
331 | 331 | ||
332 | static struct clk clk_48m_spi0 = { | 332 | static struct clk clk_48m_spi0 = { |
333 | .name = "spi_48m", | 333 | .name = "spi_48m", |
334 | .devname = "s3c64xx-spi.0", | 334 | .devname = "s3c6410-spi.0", |
335 | .parent = &clk_48m, | 335 | .parent = &clk_48m, |
336 | .enable = s3c64xx_sclk_ctrl, | 336 | .enable = s3c64xx_sclk_ctrl, |
337 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, | 337 | .ctrlbit = S3C_CLKCON_SCLK_SPI0_48, |
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = { | |||
339 | 339 | ||
340 | static struct clk clk_48m_spi1 = { | 340 | static struct clk clk_48m_spi1 = { |
341 | .name = "spi_48m", | 341 | .name = "spi_48m", |
342 | .devname = "s3c64xx-spi.1", | 342 | .devname = "s3c6410-spi.1", |
343 | .parent = &clk_48m, | 343 | .parent = &clk_48m, |
344 | .enable = s3c64xx_sclk_ctrl, | 344 | .enable = s3c64xx_sclk_ctrl, |
345 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, | 345 | .ctrlbit = S3C_CLKCON_SCLK_SPI1_48, |
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { | |||
802 | static struct clksrc_clk clk_sclk_spi0 = { | 802 | static struct clksrc_clk clk_sclk_spi0 = { |
803 | .clk = { | 803 | .clk = { |
804 | .name = "spi-bus", | 804 | .name = "spi-bus", |
805 | .devname = "s3c64xx-spi.0", | 805 | .devname = "s3c6410-spi.0", |
806 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | 806 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, |
807 | .enable = s3c64xx_sclk_ctrl, | 807 | .enable = s3c64xx_sclk_ctrl, |
808 | }, | 808 | }, |
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = { | |||
814 | static struct clksrc_clk clk_sclk_spi1 = { | 814 | static struct clksrc_clk clk_sclk_spi1 = { |
815 | .clk = { | 815 | .clk = { |
816 | .name = "spi-bus", | 816 | .name = "spi-bus", |
817 | .devname = "s3c64xx-spi.1", | 817 | .devname = "s3c6410-spi.1", |
818 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | 818 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, |
819 | .enable = s3c64xx_sclk_ctrl, | 819 | .enable = s3c64xx_sclk_ctrl, |
820 | }, | 820 | }, |
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = { | |||
858 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | 858 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), |
859 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | 859 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), |
860 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | 860 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
861 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | 861 | CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), |
862 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0), | 862 | CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0), |
863 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | 863 | CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), |
864 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1), | 864 | CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1), |
865 | }; | 865 | }; |
866 | 866 | ||
867 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | 867 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) |
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98cf0e4c..57b1ff4b2d7c 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h | |||
@@ -21,6 +21,7 @@ | |||
21 | */ | 21 | */ |
22 | enum dma_ch { | 22 | enum dma_ch { |
23 | /* DMA0/SDMA0 */ | 23 | /* DMA0/SDMA0 */ |
24 | DMACH_DT_PROP = -1, /* not yet supported, do not use */ | ||
24 | DMACH_UART0 = 0, | 25 | DMACH_UART0 = 0, |
25 | DMACH_UART0_SRC2, | 26 | DMACH_UART0_SRC2, |
26 | DMACH_UART1, | 27 | DMACH_UART1, |
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h deleted file mode 100644 index 9d0c43b4b687..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h | ||
2 | * | ||
3 | * Copyright (C) 2009 Samsung Electronics Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S3C64XX_PLAT_SPI_CLKS_H | ||
12 | #define __S3C64XX_PLAT_SPI_CLKS_H __FILE__ | ||
13 | |||
14 | #define S3C64XX_SPI_SRCCLK_PCLK 0 | ||
15 | #define S3C64XX_SPI_SRCCLK_SPIBUS 1 | ||
16 | #define S3C64XX_SPI_SRCCLK_48M 2 | ||
17 | |||
18 | #endif /* __S3C64XX_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c index d0c352d861f8..6dd4fae33a82 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410.c | |||
@@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void) | |||
799 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); | 799 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); |
800 | 800 | ||
801 | samsung_keypad_set_platdata(&crag6410_keypad_data); | 801 | samsung_keypad_set_platdata(&crag6410_keypad_data); |
802 | s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1); | 802 | s3c64xx_spi0_set_platdata(NULL, 0, 1); |
803 | 803 | ||
804 | platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); | 804 | platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices)); |
805 | 805 | ||
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c index d9592ad7a825..4dc53450d715 100644 --- a/arch/arm/mach-s3c64xx/setup-spi.c +++ b/arch/arm/mach-s3c64xx/setup-spi.c | |||
@@ -9,19 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
15 | #include <plat/s3c64xx-spi.h> | ||
16 | 13 | ||
17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
19 | .fifo_lvl_mask = 0x7f, | ||
20 | .rx_lvl_offset = 13, | ||
21 | .tx_st_done = 21, | ||
22 | }; | ||
23 | |||
24 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
25 | { | 16 | { |
26 | s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, | 17 | s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3, |
27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | 18 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
@@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
30 | #endif | 21 | #endif |
31 | 22 | ||
32 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 23 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
33 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { | 24 | int s3c64xx_spi1_cfg_gpio(void) |
34 | .fifo_lvl_mask = 0x7f, | ||
35 | .rx_lvl_offset = 13, | ||
36 | .tx_st_done = 21, | ||
37 | }; | ||
38 | |||
39 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
40 | { | 25 | { |
41 | s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, | 26 | s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3, |
42 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | 27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c index ee1e8e7f5631..000445596ec4 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c | |||
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = { | |||
227 | .ctrlbit = (1 << 17), | 227 | .ctrlbit = (1 << 17), |
228 | }, { | 228 | }, { |
229 | .name = "spi", | 229 | .name = "spi", |
230 | .devname = "s3c64xx-spi.0", | 230 | .devname = "s5p64x0-spi.0", |
231 | .parent = &clk_pclk_low.clk, | 231 | .parent = &clk_pclk_low.clk, |
232 | .enable = s5p64x0_pclk_ctrl, | 232 | .enable = s5p64x0_pclk_ctrl, |
233 | .ctrlbit = (1 << 21), | 233 | .ctrlbit = (1 << 21), |
234 | }, { | 234 | }, { |
235 | .name = "spi", | 235 | .name = "spi", |
236 | .devname = "s3c64xx-spi.1", | 236 | .devname = "s5p64x0-spi.1", |
237 | .parent = &clk_pclk_low.clk, | 237 | .parent = &clk_pclk_low.clk, |
238 | .enable = s5p64x0_pclk_ctrl, | 238 | .enable = s5p64x0_pclk_ctrl, |
239 | .ctrlbit = (1 << 22), | 239 | .ctrlbit = (1 << 22), |
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = { | |||
467 | static struct clksrc_clk clk_sclk_spi0 = { | 467 | static struct clksrc_clk clk_sclk_spi0 = { |
468 | .clk = { | 468 | .clk = { |
469 | .name = "sclk_spi", | 469 | .name = "sclk_spi", |
470 | .devname = "s3c64xx-spi.0", | 470 | .devname = "s5p64x0-spi.0", |
471 | .ctrlbit = (1 << 20), | 471 | .ctrlbit = (1 << 20), |
472 | .enable = s5p64x0_sclk_ctrl, | 472 | .enable = s5p64x0_sclk_ctrl, |
473 | }, | 473 | }, |
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = { | |||
479 | static struct clksrc_clk clk_sclk_spi1 = { | 479 | static struct clksrc_clk clk_sclk_spi1 = { |
480 | .clk = { | 480 | .clk = { |
481 | .name = "sclk_spi", | 481 | .name = "sclk_spi", |
482 | .devname = "s3c64xx-spi.1", | 482 | .devname = "s5p64x0-spi.1", |
483 | .ctrlbit = (1 << 21), | 483 | .ctrlbit = (1 << 21), |
484 | .enable = s5p64x0_sclk_ctrl, | 484 | .enable = s5p64x0_sclk_ctrl, |
485 | }, | 485 | }, |
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = { | |||
519 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), | 519 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), |
520 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | 520 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), |
521 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | 521 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
522 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | 522 | CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), |
523 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | 523 | CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), |
524 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | 524 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), |
525 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | 525 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), |
526 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | 526 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), |
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c index dae6a13f43bb..f3e0ef3d27c9 100644 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c | |||
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = { | |||
236 | .ctrlbit = (1 << 17), | 236 | .ctrlbit = (1 << 17), |
237 | }, { | 237 | }, { |
238 | .name = "spi", | 238 | .name = "spi", |
239 | .devname = "s3c64xx-spi.0", | 239 | .devname = "s5p64x0-spi.0", |
240 | .parent = &clk_pclk_low.clk, | 240 | .parent = &clk_pclk_low.clk, |
241 | .enable = s5p64x0_pclk_ctrl, | 241 | .enable = s5p64x0_pclk_ctrl, |
242 | .ctrlbit = (1 << 21), | 242 | .ctrlbit = (1 << 21), |
243 | }, { | 243 | }, { |
244 | .name = "spi", | 244 | .name = "spi", |
245 | .devname = "s3c64xx-spi.1", | 245 | .devname = "s5p64x0-spi.1", |
246 | .parent = &clk_pclk_low.clk, | 246 | .parent = &clk_pclk_low.clk, |
247 | .enable = s5p64x0_pclk_ctrl, | 247 | .enable = s5p64x0_pclk_ctrl, |
248 | .ctrlbit = (1 << 22), | 248 | .ctrlbit = (1 << 22), |
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = { | |||
528 | static struct clksrc_clk clk_sclk_spi0 = { | 528 | static struct clksrc_clk clk_sclk_spi0 = { |
529 | .clk = { | 529 | .clk = { |
530 | .name = "sclk_spi", | 530 | .name = "sclk_spi", |
531 | .devname = "s3c64xx-spi.0", | 531 | .devname = "s5p64x0-spi.0", |
532 | .ctrlbit = (1 << 20), | 532 | .ctrlbit = (1 << 20), |
533 | .enable = s5p64x0_sclk_ctrl, | 533 | .enable = s5p64x0_sclk_ctrl, |
534 | }, | 534 | }, |
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = { | |||
540 | static struct clksrc_clk clk_sclk_spi1 = { | 540 | static struct clksrc_clk clk_sclk_spi1 = { |
541 | .clk = { | 541 | .clk = { |
542 | .name = "sclk_spi", | 542 | .name = "sclk_spi", |
543 | .devname = "s3c64xx-spi.1", | 543 | .devname = "s5p64x0-spi.1", |
544 | .ctrlbit = (1 << 21), | 544 | .ctrlbit = (1 << 21), |
545 | .enable = s5p64x0_sclk_ctrl, | 545 | .enable = s5p64x0_sclk_ctrl, |
546 | }, | 546 | }, |
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = { | |||
562 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), | 562 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), |
563 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | 563 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), |
564 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | 564 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
565 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | 565 | CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), |
566 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | 566 | CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), |
567 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | 567 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), |
568 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | 568 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), |
569 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | 569 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), |
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c index 2ee5dc069b37..9c4ce085f585 100644 --- a/arch/arm/mach-s5p64x0/dma.c +++ b/arch/arm/mach-s5p64x0/dma.c | |||
@@ -36,8 +36,6 @@ | |||
36 | #include <plat/devs.h> | 36 | #include <plat/devs.h> |
37 | #include <plat/irqs.h> | 37 | #include <plat/irqs.h> |
38 | 38 | ||
39 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
40 | |||
41 | static u8 s5p6440_pdma_peri[] = { | 39 | static u8 s5p6440_pdma_peri[] = { |
42 | DMACH_UART0_RX, | 40 | DMACH_UART0_RX, |
43 | DMACH_UART0_TX, | 41 | DMACH_UART0_TX, |
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h deleted file mode 100644 index 170a20a9643a..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
7 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_SPI_CLKS_H | ||
15 | #define __ASM_ARCH_SPI_CLKS_H __FILE__ | ||
16 | |||
17 | #define S5P64X0_SPI_SRCCLK_PCLK 0 | ||
18 | #define S5P64X0_SPI_SRCCLK_SCLK 1 | ||
19 | |||
20 | #endif /* __ASM_ARCH_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c index e9b841240352..7664356720ca 100644 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ b/arch/arm/mach-s5p64x0/setup-spi.c | |||
@@ -9,21 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | #include <linux/io.h> | ||
14 | |||
15 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
16 | #include <plat/cpu.h> | ||
17 | #include <plat/s3c64xx-spi.h> | ||
18 | 13 | ||
19 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
20 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
21 | .fifo_lvl_mask = 0x1ff, | ||
22 | .rx_lvl_offset = 15, | ||
23 | .tx_st_done = 25, | ||
24 | }; | ||
25 | |||
26 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
27 | { | 16 | { |
28 | if (soc_is_s5p6450()) | 17 | if (soc_is_s5p6450()) |
29 | s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, | 18 | s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, |
@@ -36,13 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
36 | #endif | 25 | #endif |
37 | 26 | ||
38 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 27 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
39 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { | 28 | int s3c64xx_spi1_cfg_gpio(void) |
40 | .fifo_lvl_mask = 0x7f, | ||
41 | .rx_lvl_offset = 15, | ||
42 | .tx_st_done = 25, | ||
43 | }; | ||
44 | |||
45 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
46 | { | 29 | { |
47 | if (soc_is_s5p6450()) | 30 | if (soc_is_s5p6450()) |
48 | s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, | 31 | s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, |
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c index 16eca4ea2010..926219791f0d 100644 --- a/arch/arm/mach-s5pc100/clock.c +++ b/arch/arm/mach-s5pc100/clock.c | |||
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = { | |||
564 | .ctrlbit = (1 << 5), | 564 | .ctrlbit = (1 << 5), |
565 | }, { | 565 | }, { |
566 | .name = "spi", | 566 | .name = "spi", |
567 | .devname = "s3c64xx-spi.0", | 567 | .devname = "s5pc100-spi.0", |
568 | .parent = &clk_div_d1_bus.clk, | 568 | .parent = &clk_div_d1_bus.clk, |
569 | .enable = s5pc100_d1_4_ctrl, | 569 | .enable = s5pc100_d1_4_ctrl, |
570 | .ctrlbit = (1 << 6), | 570 | .ctrlbit = (1 << 6), |
571 | }, { | 571 | }, { |
572 | .name = "spi", | 572 | .name = "spi", |
573 | .devname = "s3c64xx-spi.1", | 573 | .devname = "s5pc100-spi.1", |
574 | .parent = &clk_div_d1_bus.clk, | 574 | .parent = &clk_div_d1_bus.clk, |
575 | .enable = s5pc100_d1_4_ctrl, | 575 | .enable = s5pc100_d1_4_ctrl, |
576 | .ctrlbit = (1 << 7), | 576 | .ctrlbit = (1 << 7), |
577 | }, { | 577 | }, { |
578 | .name = "spi", | 578 | .name = "spi", |
579 | .devname = "s3c64xx-spi.2", | 579 | .devname = "s5pc100-spi.2", |
580 | .parent = &clk_div_d1_bus.clk, | 580 | .parent = &clk_div_d1_bus.clk, |
581 | .enable = s5pc100_d1_4_ctrl, | 581 | .enable = s5pc100_d1_4_ctrl, |
582 | .ctrlbit = (1 << 8), | 582 | .ctrlbit = (1 << 8), |
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = { | |||
702 | 702 | ||
703 | static struct clk clk_48m_spi0 = { | 703 | static struct clk clk_48m_spi0 = { |
704 | .name = "spi_48m", | 704 | .name = "spi_48m", |
705 | .devname = "s3c64xx-spi.0", | 705 | .devname = "s5pc100-spi.0", |
706 | .parent = &clk_mout_48m.clk, | 706 | .parent = &clk_mout_48m.clk, |
707 | .enable = s5pc100_sclk0_ctrl, | 707 | .enable = s5pc100_sclk0_ctrl, |
708 | .ctrlbit = (1 << 7), | 708 | .ctrlbit = (1 << 7), |
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = { | |||
710 | 710 | ||
711 | static struct clk clk_48m_spi1 = { | 711 | static struct clk clk_48m_spi1 = { |
712 | .name = "spi_48m", | 712 | .name = "spi_48m", |
713 | .devname = "s3c64xx-spi.1", | 713 | .devname = "s5pc100-spi.1", |
714 | .parent = &clk_mout_48m.clk, | 714 | .parent = &clk_mout_48m.clk, |
715 | .enable = s5pc100_sclk0_ctrl, | 715 | .enable = s5pc100_sclk0_ctrl, |
716 | .ctrlbit = (1 << 8), | 716 | .ctrlbit = (1 << 8), |
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = { | |||
718 | 718 | ||
719 | static struct clk clk_48m_spi2 = { | 719 | static struct clk clk_48m_spi2 = { |
720 | .name = "spi_48m", | 720 | .name = "spi_48m", |
721 | .devname = "s3c64xx-spi.2", | 721 | .devname = "s5pc100-spi.2", |
722 | .parent = &clk_mout_48m.clk, | 722 | .parent = &clk_mout_48m.clk, |
723 | .enable = s5pc100_sclk0_ctrl, | 723 | .enable = s5pc100_sclk0_ctrl, |
724 | .ctrlbit = (1 << 9), | 724 | .ctrlbit = (1 << 9), |
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = { | |||
1085 | static struct clksrc_clk clk_sclk_spi0 = { | 1085 | static struct clksrc_clk clk_sclk_spi0 = { |
1086 | .clk = { | 1086 | .clk = { |
1087 | .name = "sclk_spi", | 1087 | .name = "sclk_spi", |
1088 | .devname = "s3c64xx-spi.0", | 1088 | .devname = "s5pc100-spi.0", |
1089 | .ctrlbit = (1 << 4), | 1089 | .ctrlbit = (1 << 4), |
1090 | .enable = s5pc100_sclk0_ctrl, | 1090 | .enable = s5pc100_sclk0_ctrl, |
1091 | }, | 1091 | }, |
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = { | |||
1097 | static struct clksrc_clk clk_sclk_spi1 = { | 1097 | static struct clksrc_clk clk_sclk_spi1 = { |
1098 | .clk = { | 1098 | .clk = { |
1099 | .name = "sclk_spi", | 1099 | .name = "sclk_spi", |
1100 | .devname = "s3c64xx-spi.1", | 1100 | .devname = "s5pc100-spi.1", |
1101 | .ctrlbit = (1 << 5), | 1101 | .ctrlbit = (1 << 5), |
1102 | .enable = s5pc100_sclk0_ctrl, | 1102 | .enable = s5pc100_sclk0_ctrl, |
1103 | }, | 1103 | }, |
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = { | |||
1109 | static struct clksrc_clk clk_sclk_spi2 = { | 1109 | static struct clksrc_clk clk_sclk_spi2 = { |
1110 | .clk = { | 1110 | .clk = { |
1111 | .name = "sclk_spi", | 1111 | .name = "sclk_spi", |
1112 | .devname = "s3c64xx-spi.2", | 1112 | .devname = "s5pc100-spi.2", |
1113 | .ctrlbit = (1 << 6), | 1113 | .ctrlbit = (1 << 6), |
1114 | .enable = s5pc100_sclk0_ctrl, | 1114 | .enable = s5pc100_sclk0_ctrl, |
1115 | }, | 1115 | }, |
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = { | |||
1315 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | 1315 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), |
1316 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | 1316 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), |
1317 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | 1317 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
1318 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), | 1318 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), |
1319 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), | 1319 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), |
1320 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), | 1320 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), |
1321 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), | 1321 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), |
1322 | CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), | 1322 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), |
1323 | CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), | 1323 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), |
1324 | }; | 1324 | }; |
1325 | 1325 | ||
1326 | void __init s5pc100_register_clocks(void) | 1326 | void __init s5pc100_register_clocks(void) |
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c index afd8db2d5991..b1418409709e 100644 --- a/arch/arm/mach-s5pc100/dma.c +++ b/arch/arm/mach-s5pc100/dma.c | |||
@@ -33,8 +33,6 @@ | |||
33 | #include <mach/irqs.h> | 33 | #include <mach/irqs.h> |
34 | #include <mach/dma.h> | 34 | #include <mach/dma.h> |
35 | 35 | ||
36 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
37 | |||
38 | static u8 pdma0_peri[] = { | 36 | static u8 pdma0_peri[] = { |
39 | DMACH_UART0_RX, | 37 | DMACH_UART0_RX, |
40 | DMACH_UART0_TX, | 38 | DMACH_UART0_TX, |
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h deleted file mode 100644 index 65e426370bb2..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S5PC100_PLAT_SPI_CLKS_H | ||
12 | #define __S5PC100_PLAT_SPI_CLKS_H __FILE__ | ||
13 | |||
14 | #define S5PC100_SPI_SRCCLK_PCLK 0 | ||
15 | #define S5PC100_SPI_SRCCLK_48M 1 | ||
16 | #define S5PC100_SPI_SRCCLK_SPIBUS 2 | ||
17 | |||
18 | #endif /* __S5PC100_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c index 431a6f747caa..183567961de1 100644 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ b/arch/arm/mach-s5pc100/setup-spi.c | |||
@@ -9,20 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
15 | #include <plat/s3c64xx-spi.h> | ||
16 | 13 | ||
17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
19 | .fifo_lvl_mask = 0x7f, | ||
20 | .rx_lvl_offset = 13, | ||
21 | .high_speed = 1, | ||
22 | .tx_st_done = 21, | ||
23 | }; | ||
24 | |||
25 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
26 | { | 16 | { |
27 | s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, | 17 | s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, |
28 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | 18 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
@@ -31,14 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
31 | #endif | 21 | #endif |
32 | 22 | ||
33 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 23 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
34 | struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = { | 24 | int s3c64xx_spi1_cfg_gpio(void) |
35 | .fifo_lvl_mask = 0x7f, | ||
36 | .rx_lvl_offset = 13, | ||
37 | .high_speed = 1, | ||
38 | .tx_st_done = 21, | ||
39 | }; | ||
40 | |||
41 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
42 | { | 25 | { |
43 | s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, | 26 | s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, |
44 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | 27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
@@ -47,14 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | |||
47 | #endif | 30 | #endif |
48 | 31 | ||
49 | #ifdef CONFIG_S3C64XX_DEV_SPI2 | 32 | #ifdef CONFIG_S3C64XX_DEV_SPI2 |
50 | struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = { | 33 | int s3c64xx_spi2_cfg_gpio(void) |
51 | .fifo_lvl_mask = 0x7f, | ||
52 | .rx_lvl_offset = 13, | ||
53 | .high_speed = 1, | ||
54 | .tx_st_done = 21, | ||
55 | }; | ||
56 | |||
57 | int s3c64xx_spi2_cfg_gpio(struct platform_device *dev) | ||
58 | { | 34 | { |
59 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); | 35 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); |
60 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); | 36 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c index 09609d50961d..fcdf52dbcc49 100644 --- a/arch/arm/mach-s5pv210/clock.c +++ b/arch/arm/mach-s5pv210/clock.c | |||
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = { | |||
445 | .ctrlbit = (1 << 11), | 445 | .ctrlbit = (1 << 11), |
446 | }, { | 446 | }, { |
447 | .name = "spi", | 447 | .name = "spi", |
448 | .devname = "s3c64xx-spi.0", | 448 | .devname = "s5pv210-spi.0", |
449 | .parent = &clk_pclk_psys.clk, | 449 | .parent = &clk_pclk_psys.clk, |
450 | .enable = s5pv210_clk_ip3_ctrl, | 450 | .enable = s5pv210_clk_ip3_ctrl, |
451 | .ctrlbit = (1<<12), | 451 | .ctrlbit = (1<<12), |
452 | }, { | 452 | }, { |
453 | .name = "spi", | 453 | .name = "spi", |
454 | .devname = "s3c64xx-spi.1", | 454 | .devname = "s5pv210-spi.1", |
455 | .parent = &clk_pclk_psys.clk, | 455 | .parent = &clk_pclk_psys.clk, |
456 | .enable = s5pv210_clk_ip3_ctrl, | 456 | .enable = s5pv210_clk_ip3_ctrl, |
457 | .ctrlbit = (1<<13), | 457 | .ctrlbit = (1<<13), |
458 | }, { | 458 | }, { |
459 | .name = "spi", | 459 | .name = "spi", |
460 | .devname = "s3c64xx-spi.2", | 460 | .devname = "s5pv210-spi.2", |
461 | .parent = &clk_pclk_psys.clk, | 461 | .parent = &clk_pclk_psys.clk, |
462 | .enable = s5pv210_clk_ip3_ctrl, | 462 | .enable = s5pv210_clk_ip3_ctrl, |
463 | .ctrlbit = (1<<14), | 463 | .ctrlbit = (1<<14), |
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = { | |||
1035 | static struct clksrc_clk clk_sclk_spi0 = { | 1035 | static struct clksrc_clk clk_sclk_spi0 = { |
1036 | .clk = { | 1036 | .clk = { |
1037 | .name = "sclk_spi", | 1037 | .name = "sclk_spi", |
1038 | .devname = "s3c64xx-spi.0", | 1038 | .devname = "s5pv210-spi.0", |
1039 | .enable = s5pv210_clk_mask0_ctrl, | 1039 | .enable = s5pv210_clk_mask0_ctrl, |
1040 | .ctrlbit = (1 << 16), | 1040 | .ctrlbit = (1 << 16), |
1041 | }, | 1041 | }, |
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = { | |||
1047 | static struct clksrc_clk clk_sclk_spi1 = { | 1047 | static struct clksrc_clk clk_sclk_spi1 = { |
1048 | .clk = { | 1048 | .clk = { |
1049 | .name = "sclk_spi", | 1049 | .name = "sclk_spi", |
1050 | .devname = "s3c64xx-spi.1", | 1050 | .devname = "s5pv210-spi.1", |
1051 | .enable = s5pv210_clk_mask0_ctrl, | 1051 | .enable = s5pv210_clk_mask0_ctrl, |
1052 | .ctrlbit = (1 << 17), | 1052 | .ctrlbit = (1 << 17), |
1053 | }, | 1053 | }, |
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = { | |||
1331 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | 1331 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), |
1332 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), | 1332 | CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), |
1333 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | 1333 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), |
1334 | CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | 1334 | CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), |
1335 | CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | 1335 | CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), |
1336 | }; | 1336 | }; |
1337 | 1337 | ||
1338 | void __init s5pv210_register_clocks(void) | 1338 | void __init s5pv210_register_clocks(void) |
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h deleted file mode 100644 index 02acded5f73d..000000000000 --- a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h | ||
2 | * | ||
3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __S5PV210_PLAT_SPI_CLKS_H | ||
12 | #define __S5PV210_PLAT_SPI_CLKS_H __FILE__ | ||
13 | |||
14 | #define S5PV210_SPI_SRCCLK_PCLK 0 | ||
15 | #define S5PV210_SPI_SRCCLK_SCLK 1 | ||
16 | |||
17 | #endif /* __S5PV210_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index f43c5048a37d..81aecc162f82 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c | |||
@@ -9,20 +9,10 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/gpio.h> |
12 | #include <linux/platform_device.h> | ||
13 | |||
14 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
15 | #include <plat/s3c64xx-spi.h> | ||
16 | 13 | ||
17 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
18 | struct s3c64xx_spi_info s3c64xx_spi0_pdata = { | 15 | int s3c64xx_spi0_cfg_gpio(void) |
19 | .fifo_lvl_mask = 0x1ff, | ||
20 | .rx_lvl_offset = 15, | ||
21 | .high_speed = 1, | ||
22 | .tx_st_done = 25, | ||
23 | }; | ||
24 | |||
25 | int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | ||
26 | { | 16 | { |
27 | s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); | 17 | s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); |
28 | s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); | 18 | s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); |
@@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev) | |||
33 | #endif | 23 | #endif |
34 | 24 | ||
35 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | 25 | #ifdef CONFIG_S3C64XX_DEV_SPI1 |
36 | struct s3c64xx_spi_info s3c64xx_spi1_pdata = { | 26 | int s3c64xx_spi1_cfg_gpio(void) |
37 | .fifo_lvl_mask = 0x7f, | ||
38 | .rx_lvl_offset = 15, | ||
39 | .high_speed = 1, | ||
40 | .tx_st_done = 25, | ||
41 | }; | ||
42 | |||
43 | int s3c64xx_spi1_cfg_gpio(struct platform_device *dev) | ||
44 | { | 27 | { |
45 | s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); | 28 | s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); |
46 | s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); | 29 | s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); |
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index e859fcdb3d58..fde0d23121dc 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c | |||
@@ -22,8 +22,13 @@ | |||
22 | #include <mach/common.h> | 22 | #include <mach/common.h> |
23 | #include <mach/emev2.h> | 23 | #include <mach/emev2.h> |
24 | 24 | ||
25 | #ifdef CONFIG_ARCH_SH73A0 | ||
25 | #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ | 26 | #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \ |
26 | of_machine_is_compatible("renesas,sh73a0")) | 27 | of_machine_is_compatible("renesas,sh73a0")) |
28 | #else | ||
29 | #define is_sh73a0() (0) | ||
30 | #endif | ||
31 | |||
27 | #define is_r8a7779() machine_is_marzen() | 32 | #define is_r8a7779() machine_is_marzen() |
28 | 33 | ||
29 | #ifdef CONFIG_ARCH_EMEV2 | 34 | #ifdef CONFIG_ARCH_EMEV2 |
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c index 0f41bd1c47c3..66db5f13af84 100644 --- a/arch/arm/mach-spear3xx/spear3xx.c +++ b/arch/arm/mach-spear3xx/spear3xx.c | |||
@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void) | |||
87 | 87 | ||
88 | static void __init spear3xx_timer_init(void) | 88 | static void __init spear3xx_timer_init(void) |
89 | { | 89 | { |
90 | char pclk_name[] = "pll3_48m_clk"; | 90 | char pclk_name[] = "pll3_clk"; |
91 | struct clk *gpt_clk, *pclk; | 91 | struct clk *gpt_clk, *pclk; |
92 | 92 | ||
93 | spear3xx_clk_init(); | 93 | spear3xx_clk_init(); |
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index 2e2e3596583e..9af67d003c62 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c | |||
@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void) | |||
423 | 423 | ||
424 | static void __init spear6xx_timer_init(void) | 424 | static void __init spear6xx_timer_init(void) |
425 | { | 425 | { |
426 | char pclk_name[] = "pll3_48m_clk"; | 426 | char pclk_name[] = "pll3_clk"; |
427 | struct clk *gpt_clk, *pclk; | 427 | struct clk *gpt_clk, *pclk; |
428 | 428 | ||
429 | spear6xx_clk_init(); | 429 | spear6xx_clk_init(); |
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 6a113a9bb87a..7c407393cd07 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
@@ -63,7 +63,6 @@ comment "Tegra board type" | |||
63 | config MACH_HARMONY | 63 | config MACH_HARMONY |
64 | bool "Harmony board" | 64 | bool "Harmony board" |
65 | depends on ARCH_TEGRA_2x_SOC | 65 | depends on ARCH_TEGRA_2x_SOC |
66 | select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC | ||
67 | help | 66 | help |
68 | Support for nVidia Harmony development platform | 67 | Support for nVidia Harmony development platform |
69 | 68 | ||
@@ -71,7 +70,6 @@ config MACH_KAEN | |||
71 | bool "Kaen board" | 70 | bool "Kaen board" |
72 | depends on ARCH_TEGRA_2x_SOC | 71 | depends on ARCH_TEGRA_2x_SOC |
73 | select MACH_SEABOARD | 72 | select MACH_SEABOARD |
74 | select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC | ||
75 | help | 73 | help |
76 | Support for the Kaen version of Seaboard | 74 | Support for the Kaen version of Seaboard |
77 | 75 | ||
@@ -84,7 +82,6 @@ config MACH_PAZ00 | |||
84 | config MACH_SEABOARD | 82 | config MACH_SEABOARD |
85 | bool "Seaboard board" | 83 | bool "Seaboard board" |
86 | depends on ARCH_TEGRA_2x_SOC | 84 | depends on ARCH_TEGRA_2x_SOC |
87 | select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC | ||
88 | help | 85 | help |
89 | Support for nVidia Seaboard development platform. It will | 86 | Support for nVidia Seaboard development platform. It will |
90 | also be included for some of the derivative boards that | 87 | also be included for some of the derivative boards that |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 2eb4445ddb14..90aae34245cd 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
@@ -8,9 +8,10 @@ obj-y += timer.o | |||
8 | obj-y += fuse.o | 8 | obj-y += fuse.o |
9 | obj-y += pmc.o | 9 | obj-y += pmc.o |
10 | obj-y += flowctrl.o | 10 | obj-y += flowctrl.o |
11 | obj-y += powergate.o | ||
12 | obj-y += apbio.o | ||
11 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 13 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
12 | obj-$(CONFIG_CPU_IDLE) += sleep.o | 14 | obj-$(CONFIG_CPU_IDLE) += sleep.o |
13 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o | ||
14 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o | 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o |
15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o | 16 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o |
16 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o | 17 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o |
@@ -18,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o | |||
18 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 19 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
19 | obj-$(CONFIG_SMP) += reset.o | 20 | obj-$(CONFIG_SMP) += reset.o |
20 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 21 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
21 | obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o | 22 | obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o |
22 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o | 23 | obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o |
23 | obj-$(CONFIG_TEGRA_PCI) += pcie.o | 24 | obj-$(CONFIG_TEGRA_PCI) += pcie.o |
24 | obj-$(CONFIG_USB_SUPPORT) += usb_phy.o | 25 | obj-$(CONFIG_USB_SUPPORT) += usb_phy.o |
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 9a82094092d7..435f00ca3c58 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot | |||
@@ -2,9 +2,10 @@ zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000 | |||
2 | params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 | 2 | params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 |
3 | initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 | 3 | initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 |
4 | 4 | ||
5 | dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb | 5 | dtb-$(CONFIG_MACH_HARMONY) += tegra20-harmony.dtb |
6 | dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb | 6 | dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb |
7 | dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb | 7 | dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb |
8 | dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb | 8 | dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb |
9 | dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb | 9 | dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb |
10 | dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb | 10 | dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb |
11 | dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb | ||
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c index e75451e517bd..dc0fe389be56 100644 --- a/arch/arm/mach-tegra/apbio.c +++ b/arch/arm/mach-tegra/apbio.c | |||
@@ -15,6 +15,9 @@ | |||
15 | 15 | ||
16 | #include <linux/kernel.h> | 16 | #include <linux/kernel.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <mach/iomap.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <linux/dmaengine.h> | ||
18 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
19 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
20 | #include <linux/completion.h> | 23 | #include <linux/completion.h> |
@@ -22,17 +25,21 @@ | |||
22 | #include <linux/mutex.h> | 25 | #include <linux/mutex.h> |
23 | 26 | ||
24 | #include <mach/dma.h> | 27 | #include <mach/dma.h> |
25 | #include <mach/iomap.h> | ||
26 | 28 | ||
27 | #include "apbio.h" | 29 | #include "apbio.h" |
28 | 30 | ||
31 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) | ||
29 | static DEFINE_MUTEX(tegra_apb_dma_lock); | 32 | static DEFINE_MUTEX(tegra_apb_dma_lock); |
30 | |||
31 | static struct tegra_dma_channel *tegra_apb_dma; | ||
32 | static u32 *tegra_apb_bb; | 33 | static u32 *tegra_apb_bb; |
33 | static dma_addr_t tegra_apb_bb_phys; | 34 | static dma_addr_t tegra_apb_bb_phys; |
34 | static DECLARE_COMPLETION(tegra_apb_wait); | 35 | static DECLARE_COMPLETION(tegra_apb_wait); |
35 | 36 | ||
37 | static u32 tegra_apb_readl_direct(unsigned long offset); | ||
38 | static void tegra_apb_writel_direct(u32 value, unsigned long offset); | ||
39 | |||
40 | #if defined(CONFIG_TEGRA_SYSTEM_DMA) | ||
41 | static struct tegra_dma_channel *tegra_apb_dma; | ||
42 | |||
36 | bool tegra_apb_init(void) | 43 | bool tegra_apb_init(void) |
37 | { | 44 | { |
38 | struct tegra_dma_channel *ch; | 45 | struct tegra_dma_channel *ch; |
@@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req) | |||
72 | complete(&tegra_apb_wait); | 79 | complete(&tegra_apb_wait); |
73 | } | 80 | } |
74 | 81 | ||
75 | u32 tegra_apb_readl(unsigned long offset) | 82 | static u32 tegra_apb_readl_using_dma(unsigned long offset) |
76 | { | 83 | { |
77 | struct tegra_dma_req req; | 84 | struct tegra_dma_req req; |
78 | int ret; | 85 | int ret; |
79 | 86 | ||
80 | if (!tegra_apb_dma && !tegra_apb_init()) | 87 | if (!tegra_apb_dma && !tegra_apb_init()) |
81 | return readl(IO_TO_VIRT(offset)); | 88 | return tegra_apb_readl_direct(offset); |
82 | 89 | ||
83 | mutex_lock(&tegra_apb_dma_lock); | 90 | mutex_lock(&tegra_apb_dma_lock); |
84 | req.complete = apb_dma_complete; | 91 | req.complete = apb_dma_complete; |
@@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset) | |||
108 | return *((u32 *)tegra_apb_bb); | 115 | return *((u32 *)tegra_apb_bb); |
109 | } | 116 | } |
110 | 117 | ||
111 | void tegra_apb_writel(u32 value, unsigned long offset) | 118 | static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) |
112 | { | 119 | { |
113 | struct tegra_dma_req req; | 120 | struct tegra_dma_req req; |
114 | int ret; | 121 | int ret; |
115 | 122 | ||
116 | if (!tegra_apb_dma && !tegra_apb_init()) { | 123 | if (!tegra_apb_dma && !tegra_apb_init()) { |
117 | writel(value, IO_TO_VIRT(offset)); | 124 | tegra_apb_writel_direct(value, offset); |
118 | return; | 125 | return; |
119 | } | 126 | } |
120 | 127 | ||
@@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset) | |||
143 | 150 | ||
144 | mutex_unlock(&tegra_apb_dma_lock); | 151 | mutex_unlock(&tegra_apb_dma_lock); |
145 | } | 152 | } |
153 | |||
154 | #else | ||
155 | static struct dma_chan *tegra_apb_dma_chan; | ||
156 | static struct dma_slave_config dma_sconfig; | ||
157 | |||
158 | bool tegra_apb_dma_init(void) | ||
159 | { | ||
160 | dma_cap_mask_t mask; | ||
161 | |||
162 | mutex_lock(&tegra_apb_dma_lock); | ||
163 | |||
164 | /* Check to see if we raced to setup */ | ||
165 | if (tegra_apb_dma_chan) | ||
166 | goto skip_init; | ||
167 | |||
168 | dma_cap_zero(mask); | ||
169 | dma_cap_set(DMA_SLAVE, mask); | ||
170 | tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL); | ||
171 | if (!tegra_apb_dma_chan) { | ||
172 | /* | ||
173 | * This is common until the device is probed, so don't | ||
174 | * shout about it. | ||
175 | */ | ||
176 | pr_debug("%s: can not allocate dma channel\n", __func__); | ||
177 | goto err_dma_alloc; | ||
178 | } | ||
179 | |||
180 | tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), | ||
181 | &tegra_apb_bb_phys, GFP_KERNEL); | ||
182 | if (!tegra_apb_bb) { | ||
183 | pr_err("%s: can not allocate bounce buffer\n", __func__); | ||
184 | goto err_buff_alloc; | ||
185 | } | ||
186 | |||
187 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
188 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
189 | dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR; | ||
190 | dma_sconfig.src_maxburst = 1; | ||
191 | dma_sconfig.dst_maxburst = 1; | ||
192 | |||
193 | skip_init: | ||
194 | mutex_unlock(&tegra_apb_dma_lock); | ||
195 | return true; | ||
196 | |||
197 | err_buff_alloc: | ||
198 | dma_release_channel(tegra_apb_dma_chan); | ||
199 | tegra_apb_dma_chan = NULL; | ||
200 | |||
201 | err_dma_alloc: | ||
202 | mutex_unlock(&tegra_apb_dma_lock); | ||
203 | return false; | ||
204 | } | ||
205 | |||
206 | static void apb_dma_complete(void *args) | ||
207 | { | ||
208 | complete(&tegra_apb_wait); | ||
209 | } | ||
210 | |||
211 | static int do_dma_transfer(unsigned long apb_add, | ||
212 | enum dma_transfer_direction dir) | ||
213 | { | ||
214 | struct dma_async_tx_descriptor *dma_desc; | ||
215 | int ret; | ||
216 | |||
217 | if (dir == DMA_DEV_TO_MEM) | ||
218 | dma_sconfig.src_addr = apb_add; | ||
219 | else | ||
220 | dma_sconfig.dst_addr = apb_add; | ||
221 | |||
222 | ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig); | ||
223 | if (ret) | ||
224 | return ret; | ||
225 | |||
226 | dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan, | ||
227 | tegra_apb_bb_phys, sizeof(u32), dir, | ||
228 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
229 | if (!dma_desc) | ||
230 | return -EINVAL; | ||
231 | |||
232 | dma_desc->callback = apb_dma_complete; | ||
233 | dma_desc->callback_param = NULL; | ||
234 | |||
235 | INIT_COMPLETION(tegra_apb_wait); | ||
236 | |||
237 | dmaengine_submit(dma_desc); | ||
238 | dma_async_issue_pending(tegra_apb_dma_chan); | ||
239 | ret = wait_for_completion_timeout(&tegra_apb_wait, | ||
240 | msecs_to_jiffies(50)); | ||
241 | |||
242 | if (WARN(ret == 0, "apb read dma timed out")) { | ||
243 | dmaengine_terminate_all(tegra_apb_dma_chan); | ||
244 | return -EFAULT; | ||
245 | } | ||
246 | return 0; | ||
247 | } | ||
248 | |||
249 | static u32 tegra_apb_readl_using_dma(unsigned long offset) | ||
250 | { | ||
251 | int ret; | ||
252 | |||
253 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) | ||
254 | return tegra_apb_readl_direct(offset); | ||
255 | |||
256 | mutex_lock(&tegra_apb_dma_lock); | ||
257 | ret = do_dma_transfer(offset, DMA_DEV_TO_MEM); | ||
258 | if (ret < 0) { | ||
259 | pr_err("error in reading offset 0x%08lx using dma\n", offset); | ||
260 | *(u32 *)tegra_apb_bb = 0; | ||
261 | } | ||
262 | mutex_unlock(&tegra_apb_dma_lock); | ||
263 | return *((u32 *)tegra_apb_bb); | ||
264 | } | ||
265 | |||
266 | static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) | ||
267 | { | ||
268 | int ret; | ||
269 | |||
270 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) { | ||
271 | tegra_apb_writel_direct(value, offset); | ||
272 | return; | ||
273 | } | ||
274 | |||
275 | mutex_lock(&tegra_apb_dma_lock); | ||
276 | *((u32 *)tegra_apb_bb) = value; | ||
277 | ret = do_dma_transfer(offset, DMA_MEM_TO_DEV); | ||
278 | if (ret < 0) | ||
279 | pr_err("error in writing offset 0x%08lx using dma\n", offset); | ||
280 | mutex_unlock(&tegra_apb_dma_lock); | ||
281 | } | ||
282 | #endif | ||
283 | #else | ||
284 | #define tegra_apb_readl_using_dma tegra_apb_readl_direct | ||
285 | #define tegra_apb_writel_using_dma tegra_apb_writel_direct | ||
286 | #endif | ||
287 | |||
288 | typedef u32 (*apbio_read_fptr)(unsigned long offset); | ||
289 | typedef void (*apbio_write_fptr)(u32 value, unsigned long offset); | ||
290 | |||
291 | static apbio_read_fptr apbio_read; | ||
292 | static apbio_write_fptr apbio_write; | ||
293 | |||
294 | static u32 tegra_apb_readl_direct(unsigned long offset) | ||
295 | { | ||
296 | return readl(IO_TO_VIRT(offset)); | ||
297 | } | ||
298 | |||
299 | static void tegra_apb_writel_direct(u32 value, unsigned long offset) | ||
300 | { | ||
301 | writel(value, IO_TO_VIRT(offset)); | ||
302 | } | ||
303 | |||
304 | void tegra_apb_io_init(void) | ||
305 | { | ||
306 | /* Need to use dma only when it is Tegra20 based platform */ | ||
307 | if (of_machine_is_compatible("nvidia,tegra20") || | ||
308 | !of_have_populated_dt()) { | ||
309 | apbio_read = tegra_apb_readl_using_dma; | ||
310 | apbio_write = tegra_apb_writel_using_dma; | ||
311 | } else { | ||
312 | apbio_read = tegra_apb_readl_direct; | ||
313 | apbio_write = tegra_apb_writel_direct; | ||
314 | } | ||
315 | } | ||
316 | |||
317 | u32 tegra_apb_readl(unsigned long offset) | ||
318 | { | ||
319 | return apbio_read(offset); | ||
320 | } | ||
321 | |||
322 | void tegra_apb_writel(u32 value, unsigned long offset) | ||
323 | { | ||
324 | apbio_write(value, offset); | ||
325 | } | ||
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h index 8b49e8c89a64..f05d71c303c7 100644 --- a/arch/arm/mach-tegra/apbio.h +++ b/arch/arm/mach-tegra/apbio.h | |||
@@ -16,24 +16,7 @@ | |||
16 | #ifndef __MACH_TEGRA_APBIO_H | 16 | #ifndef __MACH_TEGRA_APBIO_H |
17 | #define __MACH_TEGRA_APBIO_H | 17 | #define __MACH_TEGRA_APBIO_H |
18 | 18 | ||
19 | #ifdef CONFIG_TEGRA_SYSTEM_DMA | 19 | void tegra_apb_io_init(void); |
20 | |||
21 | u32 tegra_apb_readl(unsigned long offset); | 20 | u32 tegra_apb_readl(unsigned long offset); |
22 | void tegra_apb_writel(u32 value, unsigned long offset); | 21 | void tegra_apb_writel(u32 value, unsigned long offset); |
23 | |||
24 | #else | ||
25 | #include <asm/io.h> | ||
26 | #include <mach/io.h> | ||
27 | |||
28 | static inline u32 tegra_apb_readl(unsigned long offset) | ||
29 | { | ||
30 | return readl(IO_TO_VIRT(offset)); | ||
31 | } | ||
32 | |||
33 | static inline void tegra_apb_writel(u32 value, unsigned long offset) | ||
34 | { | ||
35 | writel(value, IO_TO_VIRT(offset)); | ||
36 | } | ||
37 | #endif | ||
38 | |||
39 | #endif | 22 | #endif |
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 204a5c8b0b57..96fef6bcc651 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include "clock.h" | 33 | #include "clock.h" |
34 | #include "fuse.h" | 34 | #include "fuse.h" |
35 | #include "pmc.h" | 35 | #include "pmc.h" |
36 | #include "apbio.h" | ||
36 | 37 | ||
37 | /* | 38 | /* |
38 | * Storage for debug-macro.S's state. | 39 | * Storage for debug-macro.S's state. |
@@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) | |||
127 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | 128 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC |
128 | void __init tegra20_init_early(void) | 129 | void __init tegra20_init_early(void) |
129 | { | 130 | { |
131 | tegra_apb_io_init(); | ||
130 | tegra_init_fuse(); | 132 | tegra_init_fuse(); |
131 | tegra2_init_clocks(); | 133 | tegra2_init_clocks(); |
132 | tegra_clk_init_from_table(tegra20_clk_init_table); | 134 | tegra_clk_init_from_table(tegra20_clk_init_table); |
@@ -138,6 +140,7 @@ void __init tegra20_init_early(void) | |||
138 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | 140 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC |
139 | void __init tegra30_init_early(void) | 141 | void __init tegra30_init_early(void) |
140 | { | 142 | { |
143 | tegra_apb_io_init(); | ||
141 | tegra_init_fuse(); | 144 | tegra_init_fuse(); |
142 | tegra30_init_clocks(); | 145 | tegra30_init_clocks(); |
143 | tegra_clk_init_from_table(tegra30_clk_init_table); | 146 | tegra_clk_init_from_table(tegra30_clk_init_table); |
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index d83a8c0296f5..566e2f88899b 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c | |||
@@ -27,9 +27,9 @@ | |||
27 | #include <linux/cpuidle.h> | 27 | #include <linux/cpuidle.h> |
28 | #include <linux/hrtimer.h> | 28 | #include <linux/hrtimer.h> |
29 | 29 | ||
30 | #include <mach/iomap.h> | 30 | #include <asm/proc-fns.h> |
31 | 31 | ||
32 | extern void tegra_cpu_wfi(void); | 32 | #include <mach/iomap.h> |
33 | 33 | ||
34 | static int tegra_idle_enter_lp3(struct cpuidle_device *dev, | 34 | static int tegra_idle_enter_lp3(struct cpuidle_device *dev, |
35 | struct cpuidle_driver *drv, int index); | 35 | struct cpuidle_driver *drv, int index); |
@@ -64,7 +64,7 @@ static int tegra_idle_enter_lp3(struct cpuidle_device *dev, | |||
64 | 64 | ||
65 | enter = ktime_get(); | 65 | enter = ktime_get(); |
66 | 66 | ||
67 | tegra_cpu_wfi(); | 67 | cpu_do_idle(); |
68 | 68 | ||
69 | exit = ktime_sub(ktime_get(), enter); | 69 | exit = ktime_sub(ktime_get(), enter); |
70 | us = ktime_to_us(exit); | 70 | us = ktime_to_us(exit); |
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 5b20197bae7f..d29b156a8011 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S | |||
@@ -62,32 +62,3 @@ | |||
62 | movw \reg, #:lower16:\val | 62 | movw \reg, #:lower16:\val |
63 | movt \reg, #:upper16:\val | 63 | movt \reg, #:upper16:\val |
64 | .endm | 64 | .endm |
65 | |||
66 | /* | ||
67 | * tegra_cpu_wfi | ||
68 | * | ||
69 | * puts current CPU in clock-gated wfi using the flow controller | ||
70 | * | ||
71 | * corrupts r0-r3 | ||
72 | * must be called with MMU on | ||
73 | */ | ||
74 | |||
75 | ENTRY(tegra_cpu_wfi) | ||
76 | cpu_id r0 | ||
77 | cpu_to_halt_reg r1, r0 | ||
78 | cpu_to_csr_reg r2, r0 | ||
79 | mov32 r0, TEGRA_FLOW_CTRL_VIRT | ||
80 | mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | ||
81 | str r3, [r0, r2] @ clear event & interrupt status | ||
82 | mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME | ||
83 | str r3, [r0, r1] @ put flow controller in wait irq mode | ||
84 | dsb | ||
85 | wfi | ||
86 | mov r3, #0 | ||
87 | str r3, [r0, r1] @ clear flow controller halt status | ||
88 | mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | ||
89 | str r3, [r0, r2] @ clear event & interrupt status | ||
90 | dsb | ||
91 | mov pc, lr | ||
92 | ENDPROC(tegra_cpu_wfi) | ||
93 | |||
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig index 53d3d46dec12..c013bbf79cac 100644 --- a/arch/arm/mach-ux500/Kconfig +++ b/arch/arm/mach-ux500/Kconfig | |||
@@ -41,6 +41,7 @@ config MACH_HREFV60 | |||
41 | config MACH_SNOWBALL | 41 | config MACH_SNOWBALL |
42 | bool "U8500 Snowball platform" | 42 | bool "U8500 Snowball platform" |
43 | select MACH_MOP500 | 43 | select MACH_MOP500 |
44 | select LEDS_GPIO | ||
44 | help | 45 | help |
45 | Include support for the snowball development platform. | 46 | Include support for the snowball development platform. |
46 | 47 | ||
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c index 920251cf834c..18ff781cfbe4 100644 --- a/arch/arm/mach-ux500/board-mop500-sdi.c +++ b/arch/arm/mach-ux500/board-mop500-sdi.c | |||
@@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = { | |||
80 | }; | 80 | }; |
81 | #endif | 81 | #endif |
82 | 82 | ||
83 | static struct mmci_platform_data mop500_sdi0_data = { | 83 | struct mmci_platform_data mop500_sdi0_data = { |
84 | .ios_handler = mop500_sdi0_ios_handler, | 84 | .ios_handler = mop500_sdi0_ios_handler, |
85 | .ocr_mask = MMC_VDD_29_30, | 85 | .ocr_mask = MMC_VDD_29_30, |
86 | .f_max = 50000000, | 86 | .f_max = 50000000, |
@@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = { | |||
227 | }; | 227 | }; |
228 | #endif | 228 | #endif |
229 | 229 | ||
230 | static struct mmci_platform_data mop500_sdi4_data = { | 230 | struct mmci_platform_data mop500_sdi4_data = { |
231 | .ocr_mask = MMC_VDD_29_30, | 231 | .ocr_mask = MMC_VDD_29_30, |
232 | .f_max = 50000000, | 232 | .f_max = 50000000, |
233 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | | 233 | .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 1509a3cb5833..84461fa2a3ba 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c | |||
@@ -58,7 +58,7 @@ | |||
58 | static struct gpio_led snowball_led_array[] = { | 58 | static struct gpio_led snowball_led_array[] = { |
59 | { | 59 | { |
60 | .name = "user_led", | 60 | .name = "user_led", |
61 | .default_trigger = "none", | 61 | .default_trigger = "heartbeat", |
62 | .gpio = 142, | 62 | .gpio = 142, |
63 | }, | 63 | }, |
64 | }; | 64 | }; |
@@ -331,43 +331,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = { | |||
331 | }, | 331 | }, |
332 | }; | 332 | }; |
333 | 333 | ||
334 | #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \ | ||
335 | static struct nmk_i2c_controller u8500_i2c##id##_data = { \ | ||
336 | /* \ | ||
337 | * slave data setup time, which is \ | ||
338 | * 250 ns,100ns,10ns which is 14,6,2 \ | ||
339 | * respectively for a 48 Mhz \ | ||
340 | * i2c clock \ | ||
341 | */ \ | ||
342 | .slsu = _slsu, \ | ||
343 | /* Tx FIFO threshold */ \ | ||
344 | .tft = _tft, \ | ||
345 | /* Rx FIFO threshold */ \ | ||
346 | .rft = _rft, \ | ||
347 | /* std. mode operation */ \ | ||
348 | .clk_freq = clk, \ | ||
349 | /* Slave response timeout(ms) */\ | ||
350 | .timeout = t_out, \ | ||
351 | .sm = _sm, \ | ||
352 | } | ||
353 | |||
354 | /* | ||
355 | * The board uses 4 i2c controllers, initialize all of | ||
356 | * them with slave data setup time of 250 ns, | ||
357 | * Tx & Rx FIFO threshold values as 8 and standard | ||
358 | * mode of operation | ||
359 | */ | ||
360 | U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); | ||
361 | U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); | ||
362 | U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); | ||
363 | U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); | ||
364 | |||
365 | static void __init mop500_i2c_init(struct device *parent) | 334 | static void __init mop500_i2c_init(struct device *parent) |
366 | { | 335 | { |
367 | db8500_add_i2c0(parent, &u8500_i2c0_data); | 336 | db8500_add_i2c0(parent, NULL); |
368 | db8500_add_i2c1(parent, &u8500_i2c1_data); | 337 | db8500_add_i2c1(parent, NULL); |
369 | db8500_add_i2c2(parent, &u8500_i2c2_data); | 338 | db8500_add_i2c2(parent, NULL); |
370 | db8500_add_i2c3(parent, &u8500_i2c3_data); | 339 | db8500_add_i2c3(parent, NULL); |
371 | } | 340 | } |
372 | 341 | ||
373 | static struct gpio_keys_button mop500_gpio_keys[] = { | 342 | static struct gpio_keys_button mop500_gpio_keys[] = { |
@@ -625,11 +594,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = { | |||
625 | &ab8500_device, | 594 | &ab8500_device, |
626 | }; | 595 | }; |
627 | 596 | ||
628 | static struct platform_device *snowball_of_platform_devs[] __initdata = { | ||
629 | &snowball_led_dev, | ||
630 | &snowball_key_dev, | ||
631 | }; | ||
632 | |||
633 | static void __init mop500_init_machine(void) | 597 | static void __init mop500_init_machine(void) |
634 | { | 598 | { |
635 | struct device *parent = NULL; | 599 | struct device *parent = NULL; |
@@ -769,6 +733,11 @@ MACHINE_END | |||
769 | 733 | ||
770 | #ifdef CONFIG_MACH_UX500_DT | 734 | #ifdef CONFIG_MACH_UX500_DT |
771 | 735 | ||
736 | static struct platform_device *snowball_of_platform_devs[] __initdata = { | ||
737 | &snowball_led_dev, | ||
738 | &snowball_key_dev, | ||
739 | }; | ||
740 | |||
772 | struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | 741 | struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { |
773 | /* Requires DMA and call-back bindings. */ | 742 | /* Requires DMA and call-back bindings. */ |
774 | OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), | 743 | OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat), |
@@ -776,6 +745,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
776 | OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), | 745 | OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat), |
777 | /* Requires DMA bindings. */ | 746 | /* Requires DMA bindings. */ |
778 | OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), | 747 | OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), |
748 | OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), | ||
749 | OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), | ||
779 | /* Requires clock name bindings. */ | 750 | /* Requires clock name bindings. */ |
780 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), | 751 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), |
781 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), | 752 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), |
@@ -786,6 +757,13 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = { | |||
786 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), | 757 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL), |
787 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), | 758 | OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL), |
788 | OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), | 759 | OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL), |
760 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL), | ||
761 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL), | ||
762 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL), | ||
763 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL), | ||
764 | OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL), | ||
765 | /* Requires device name bindings. */ | ||
766 | OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL), | ||
789 | {}, | 767 | {}, |
790 | }; | 768 | }; |
791 | 769 | ||
@@ -818,8 +796,6 @@ static void __init u8500_init_machine(void) | |||
818 | 796 | ||
819 | for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) | 797 | for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++) |
820 | mop500_platform_devs[i]->dev.parent = parent; | 798 | mop500_platform_devs[i]->dev.parent = parent; |
821 | for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++) | ||
822 | snowball_platform_devs[i]->dev.parent = parent; | ||
823 | 799 | ||
824 | /* automatically probe child nodes of db8500 device */ | 800 | /* automatically probe child nodes of db8500 device */ |
825 | of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); | 801 | of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent); |
@@ -838,18 +814,6 @@ static void __init u8500_init_machine(void) | |||
838 | 814 | ||
839 | mop500_uib_init(); | 815 | mop500_uib_init(); |
840 | 816 | ||
841 | } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) { | ||
842 | /* | ||
843 | * Devices to be DT:ed: | ||
844 | * snowball_led_dev = todo | ||
845 | * snowball_key_dev = todo | ||
846 | * snowball_sbnet_dev = done | ||
847 | * ab8500_device = done | ||
848 | */ | ||
849 | platform_add_devices(snowball_of_platform_devs, | ||
850 | ARRAY_SIZE(snowball_of_platform_devs)); | ||
851 | |||
852 | snowball_sdi_init(parent); | ||
853 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { | 817 | } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) { |
854 | /* | 818 | /* |
855 | * The HREFv60 board removed a GPIO expander and routed | 819 | * The HREFv60 board removed a GPIO expander and routed |
@@ -871,7 +835,6 @@ static void __init u8500_init_machine(void) | |||
871 | 835 | ||
872 | mop500_uib_init(); | 836 | mop500_uib_init(); |
873 | } | 837 | } |
874 | mop500_i2c_init(parent); | ||
875 | 838 | ||
876 | /* This board has full regulator constraints */ | 839 | /* This board has full regulator constraints */ |
877 | regulator_has_full_constraints(); | 840 | regulator_has_full_constraints(); |
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h index 2f87b25a908a..b5bfc1a78b1a 100644 --- a/arch/arm/mach-ux500/board-mop500.h +++ b/arch/arm/mach-ux500/board-mop500.h | |||
@@ -9,6 +9,7 @@ | |||
9 | 9 | ||
10 | /* For NOMADIK_NR_GPIO */ | 10 | /* For NOMADIK_NR_GPIO */ |
11 | #include <mach/irqs.h> | 11 | #include <mach/irqs.h> |
12 | #include <linux/amba/mmci.h> | ||
12 | 13 | ||
13 | /* Snowball specific GPIO assignments, this board has no GPIO expander */ | 14 | /* Snowball specific GPIO assignments, this board has no GPIO expander */ |
14 | #define SNOWBALL_ACCEL_INT1_GPIO 163 | 15 | #define SNOWBALL_ACCEL_INT1_GPIO 163 |
@@ -78,6 +79,8 @@ | |||
78 | 79 | ||
79 | struct device; | 80 | struct device; |
80 | struct i2c_board_info; | 81 | struct i2c_board_info; |
82 | extern struct mmci_platform_data mop500_sdi0_data; | ||
83 | extern struct mmci_platform_data mop500_sdi4_data; | ||
81 | 84 | ||
82 | extern void mop500_sdi_init(struct device *parent); | 85 | extern void mop500_sdi_init(struct device *parent); |
83 | extern void snowball_sdi_init(struct device *parent); | 86 | extern void snowball_sdi_init(struct device *parent); |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index 33275eb4c689..c8dd94f606dc 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
@@ -139,7 +139,6 @@ static struct platform_device *platform_devs[] __initdata = { | |||
139 | 139 | ||
140 | static struct platform_device *of_platform_devs[] __initdata = { | 140 | static struct platform_device *of_platform_devs[] __initdata = { |
141 | &u8500_dma40_device, | 141 | &u8500_dma40_device, |
142 | &db8500_pmu_device, | ||
143 | }; | 142 | }; |
144 | 143 | ||
145 | static resource_size_t __initdata db8500_gpio_base[] = { | 144 | static resource_size_t __initdata db8500_gpio_base[] = { |
@@ -237,7 +236,6 @@ struct device * __init u8500_of_init_devices(void) | |||
237 | 236 | ||
238 | parent = db8500_soc_device_init(); | 237 | parent = db8500_soc_device_init(); |
239 | 238 | ||
240 | db8500_add_rtc(parent); | ||
241 | db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); | 239 | db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); |
242 | 240 | ||
243 | platform_device_register_data(parent, | 241 | platform_device_register_data(parent, |
@@ -249,7 +247,7 @@ struct device * __init u8500_of_init_devices(void) | |||
249 | /* | 247 | /* |
250 | * Devices to be DT:ed: | 248 | * Devices to be DT:ed: |
251 | * u8500_dma40_device = todo | 249 | * u8500_dma40_device = todo |
252 | * db8500_pmu_device = todo | 250 | * db8500_pmu_device = done |
253 | * db8500_prcmu_device = done | 251 | * db8500_prcmu_device = done |
254 | */ | 252 | */ |
255 | platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); | 253 | platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs)); |
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 741e71feca78..66e7f00884ab 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c | |||
@@ -63,8 +63,10 @@ static void __init ux500_timer_init(void) | |||
63 | 63 | ||
64 | /* TODO: Once MTU has been DT:ed place code above into else. */ | 64 | /* TODO: Once MTU has been DT:ed place code above into else. */ |
65 | if (of_have_populated_dt()) { | 65 | if (of_have_populated_dt()) { |
66 | #ifdef CONFIG_OF | ||
66 | np = of_find_matching_node(NULL, prcmu_timer_of_match); | 67 | np = of_find_matching_node(NULL, prcmu_timer_of_match); |
67 | if (!np) | 68 | if (!np) |
69 | #endif | ||
68 | goto dt_fail; | 70 | goto dt_fail; |
69 | 71 | ||
70 | tmp_base = of_iomap(np, 0); | 72 | tmp_base = of_iomap(np, 0); |
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index cf8730d35e70..fc3730f01650 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig | |||
@@ -2,7 +2,8 @@ menu "Versatile Express platform type" | |||
2 | depends on ARCH_VEXPRESS | 2 | depends on ARCH_VEXPRESS |
3 | 3 | ||
4 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | 4 | config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA |
5 | bool | 5 | bool "Enable A5 and A9 only errata work-arounds" |
6 | default y | ||
6 | select ARM_ERRATA_720789 | 7 | select ARM_ERRATA_720789 |
7 | select ARM_ERRATA_751472 | 8 | select ARM_ERRATA_751472 |
8 | select PL310_ERRATA_753970 if CACHE_PL310 | 9 | select PL310_ERRATA_753970 if CACHE_PL310 |
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | |||
14 | 15 | ||
15 | config ARCH_VEXPRESS_CA9X4 | 16 | config ARCH_VEXPRESS_CA9X4 |
16 | bool "Versatile Express Cortex-A9x4 tile" | 17 | bool "Versatile Express Cortex-A9x4 tile" |
17 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
18 | select ARM_GIC | 18 | select ARM_GIC |
19 | select CPU_V7 | 19 | select CPU_V7 |
20 | select HAVE_SMP | 20 | select HAVE_SMP |
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4 | |||
22 | 22 | ||
23 | config ARCH_VEXPRESS_DT | 23 | config ARCH_VEXPRESS_DT |
24 | bool "Device Tree support for Versatile Express platforms" | 24 | bool "Device Tree support for Versatile Express platforms" |
25 | select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA | ||
26 | select ARM_GIC | 25 | select ARM_GIC |
27 | select ARM_PATCH_PHYS_VIRT | 26 | select ARM_PATCH_PHYS_VIRT |
28 | select AUTO_ZRELADDR | 27 | select AUTO_ZRELADDR |
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index 909f85ebf5f4..318d308dfb93 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot | |||
@@ -6,4 +6,5 @@ initrd_phys-y := 0x60800000 | |||
6 | 6 | ||
7 | dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ | 7 | dtb-$(CONFIG_ARCH_VEXPRESS_DT) += vexpress-v2p-ca5s.dtb \ |
8 | vexpress-v2p-ca9.dtb \ | 8 | vexpress-v2p-ca9.dtb \ |
9 | vexpress-v2p-ca15-tc1.dtb | 9 | vexpress-v2p-ca15-tc1.dtb \ |
10 | vexpress-v2p-ca15_a7.dtb | ||
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index c65cc3b462a5..61c492403b05 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
@@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void) | |||
66 | 66 | ||
67 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) | 67 | static void ct_ca9x4_clcd_enable(struct clcd_fb *fb) |
68 | { | 68 | { |
69 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0); | 69 | u32 site = v2m_get_master_site(); |
70 | v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2); | 70 | |
71 | /* | ||
72 | * Old firmware was using the "site" component of the command | ||
73 | * to control the DVI muxer (while it should be always 0 ie. MB). | ||
74 | * Newer firmware uses the data register. Keep both for compatibility. | ||
75 | */ | ||
76 | v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site); | ||
77 | v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2); | ||
71 | } | 78 | } |
72 | 79 | ||
73 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) | 80 | static int ct_ca9x4_clcd_setup(struct clcd_fb *fb) |
@@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = { | |||
105 | }; | 112 | }; |
106 | 113 | ||
107 | 114 | ||
108 | static long ct_round(struct clk *clk, unsigned long rate) | 115 | static struct v2m_osc ct_osc1 = { |
109 | { | 116 | .osc = 1, |
110 | return rate; | 117 | .rate_min = 10000000, |
111 | } | 118 | .rate_max = 80000000, |
112 | 119 | .rate_default = 23750000, | |
113 | static int ct_set(struct clk *clk, unsigned long rate) | ||
114 | { | ||
115 | return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate); | ||
116 | } | ||
117 | |||
118 | static const struct clk_ops osc1_clk_ops = { | ||
119 | .round = ct_round, | ||
120 | .set = ct_set, | ||
121 | }; | ||
122 | |||
123 | static struct clk osc1_clk = { | ||
124 | .ops = &osc1_clk_ops, | ||
125 | .rate = 24000000, | ||
126 | }; | ||
127 | |||
128 | static struct clk ct_sp804_clk = { | ||
129 | .rate = 1000000, | ||
130 | }; | ||
131 | |||
132 | static struct clk_lookup lookups[] = { | ||
133 | { /* CLCD */ | ||
134 | .dev_id = "ct:clcd", | ||
135 | .clk = &osc1_clk, | ||
136 | }, { /* SP804 timers */ | ||
137 | .dev_id = "sp804", | ||
138 | .con_id = "ct-timer0", | ||
139 | .clk = &ct_sp804_clk, | ||
140 | }, { /* SP804 timers */ | ||
141 | .dev_id = "sp804", | ||
142 | .con_id = "ct-timer1", | ||
143 | .clk = &ct_sp804_clk, | ||
144 | }, | ||
145 | }; | 120 | }; |
146 | 121 | ||
147 | static struct resource pmu_resources[] = { | 122 | static struct resource pmu_resources[] = { |
@@ -174,14 +149,10 @@ static struct platform_device pmu_device = { | |||
174 | .resource = pmu_resources, | 149 | .resource = pmu_resources, |
175 | }; | 150 | }; |
176 | 151 | ||
177 | static void __init ct_ca9x4_init_early(void) | ||
178 | { | ||
179 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); | ||
180 | } | ||
181 | |||
182 | static void __init ct_ca9x4_init(void) | 152 | static void __init ct_ca9x4_init(void) |
183 | { | 153 | { |
184 | int i; | 154 | int i; |
155 | struct clk *clk; | ||
185 | 156 | ||
186 | #ifdef CONFIG_CACHE_L2X0 | 157 | #ifdef CONFIG_CACHE_L2X0 |
187 | void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); | 158 | void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K); |
@@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void) | |||
193 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); | 164 | l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); |
194 | #endif | 165 | #endif |
195 | 166 | ||
167 | ct_osc1.site = v2m_get_master_site(); | ||
168 | clk = v2m_osc_register("ct:osc1", &ct_osc1); | ||
169 | clk_register_clkdev(clk, NULL, "ct:clcd"); | ||
170 | |||
196 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) | 171 | for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++) |
197 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); | 172 | amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource); |
198 | 173 | ||
@@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = { | |||
234 | .id = V2M_CT_ID_CA9, | 209 | .id = V2M_CT_ID_CA9, |
235 | .name = "CA9x4", | 210 | .name = "CA9x4", |
236 | .map_io = ct_ca9x4_map_io, | 211 | .map_io = ct_ca9x4_map_io, |
237 | .init_early = ct_ca9x4_init_early, | ||
238 | .init_irq = ct_ca9x4_init_irq, | 212 | .init_irq = ct_ca9x4_init_irq, |
239 | .init_tile = ct_ca9x4_init, | 213 | .init_tile = ct_ca9x4_init, |
240 | #ifdef CONFIG_SMP | 214 | #ifdef CONFIG_SMP |
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h deleted file mode 100644 index 3f8307d73cad..000000000000 --- a/arch/arm/mach-vexpress/include/mach/clkdev.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | #ifndef __ASM_MACH_CLKDEV_H | ||
2 | #define __ASM_MACH_CLKDEV_H | ||
3 | |||
4 | #include <plat/clock.h> | ||
5 | |||
6 | struct clk { | ||
7 | const struct clk_ops *ops; | ||
8 | unsigned long rate; | ||
9 | const struct icst_params *params; | ||
10 | }; | ||
11 | |||
12 | #define __clk_get(clk) ({ 1; }) | ||
13 | #define __clk_put(clk) do { } while (0) | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S index fa8224794e0b..9f509f55d078 100644 --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S | |||
@@ -18,6 +18,8 @@ | |||
18 | 18 | ||
19 | #define DEBUG_LL_VIRT_BASE 0xf8000000 | 19 | #define DEBUG_LL_VIRT_BASE 0xf8000000 |
20 | 20 | ||
21 | #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) | ||
22 | |||
21 | .macro addruart,rp,rv,tmp | 23 | .macro addruart,rp,rv,tmp |
22 | 24 | ||
23 | @ Make an educated guess regarding the memory map: | 25 | @ Make an educated guess regarding the memory map: |
@@ -41,3 +43,42 @@ | |||
41 | .endm | 43 | .endm |
42 | 44 | ||
43 | #include <asm/hardware/debug-pl01x.S> | 45 | #include <asm/hardware/debug-pl01x.S> |
46 | |||
47 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) | ||
48 | |||
49 | .macro addruart,rp,rv,tmp | ||
50 | mov \rp, #DEBUG_LL_UART_OFFSET | ||
51 | orr \rv, \rp, #DEBUG_LL_VIRT_BASE | ||
52 | orr \rp, \rp, #DEBUG_LL_PHYS_BASE | ||
53 | .endm | ||
54 | |||
55 | #include <asm/hardware/debug-pl01x.S> | ||
56 | |||
57 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) | ||
58 | |||
59 | .macro addruart,rp,rv,tmp | ||
60 | mov \rp, #DEBUG_LL_UART_OFFSET_RS1 | ||
61 | orr \rv, \rp, #DEBUG_LL_VIRT_BASE | ||
62 | orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 | ||
63 | .endm | ||
64 | |||
65 | #include <asm/hardware/debug-pl01x.S> | ||
66 | |||
67 | #else /* CONFIG_DEBUG_LL_UART_NONE */ | ||
68 | |||
69 | .macro addruart, rp, rv, tmp | ||
70 | /* Safe dummy values */ | ||
71 | mov \rp, #0 | ||
72 | mov \rv, #DEBUG_LL_VIRT_BASE | ||
73 | .endm | ||
74 | |||
75 | .macro senduart,rd,rx | ||
76 | .endm | ||
77 | |||
78 | .macro waituart,rd,rx | ||
79 | .endm | ||
80 | |||
81 | .macro busyuart,rd,rx | ||
82 | .endm | ||
83 | |||
84 | #endif | ||
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h index 31a92890893d..1e388c7bf4d7 100644 --- a/arch/arm/mach-vexpress/include/mach/motherboard.h +++ b/arch/arm/mach-vexpress/include/mach/motherboard.h | |||
@@ -1,6 +1,8 @@ | |||
1 | #ifndef __MACH_MOTHERBOARD_H | 1 | #ifndef __MACH_MOTHERBOARD_H |
2 | #define __MACH_MOTHERBOARD_H | 2 | #define __MACH_MOTHERBOARD_H |
3 | 3 | ||
4 | #include <linux/clk-provider.h> | ||
5 | |||
4 | /* | 6 | /* |
5 | * Physical addresses, offset from V2M_PA_CS0-3 | 7 | * Physical addresses, offset from V2M_PA_CS0-3 |
6 | */ | 8 | */ |
@@ -104,9 +106,10 @@ | |||
104 | #define SYS_CFG_REBOOT (9 << 20) | 106 | #define SYS_CFG_REBOOT (9 << 20) |
105 | #define SYS_CFG_DVIMODE (11 << 20) | 107 | #define SYS_CFG_DVIMODE (11 << 20) |
106 | #define SYS_CFG_POWER (12 << 20) | 108 | #define SYS_CFG_POWER (12 << 20) |
107 | #define SYS_CFG_SITE_MB (0 << 16) | 109 | #define SYS_CFG_SITE(n) ((n) << 16) |
108 | #define SYS_CFG_SITE_DB1 (1 << 16) | 110 | #define SYS_CFG_SITE_MB 0 |
109 | #define SYS_CFG_SITE_DB2 (2 << 16) | 111 | #define SYS_CFG_SITE_DB1 1 |
112 | #define SYS_CFG_SITE_DB2 2 | ||
110 | #define SYS_CFG_STACK(n) ((n) << 12) | 113 | #define SYS_CFG_STACK(n) ((n) << 12) |
111 | 114 | ||
112 | #define SYS_CFG_ERR (1 << 1) | 115 | #define SYS_CFG_ERR (1 << 1) |
@@ -122,6 +125,8 @@ void v2m_flags_set(u32 data); | |||
122 | #define SYS_MISC_MASTERSITE (1 << 14) | 125 | #define SYS_MISC_MASTERSITE (1 << 14) |
123 | #define SYS_PROCIDx_HBI_MASK 0xfff | 126 | #define SYS_PROCIDx_HBI_MASK 0xfff |
124 | 127 | ||
128 | int v2m_get_master_site(void); | ||
129 | |||
125 | /* | 130 | /* |
126 | * Core tile IDs | 131 | * Core tile IDs |
127 | */ | 132 | */ |
@@ -144,4 +149,21 @@ struct ct_desc { | |||
144 | 149 | ||
145 | extern struct ct_desc *ct_desc; | 150 | extern struct ct_desc *ct_desc; |
146 | 151 | ||
152 | /* | ||
153 | * OSC clock provider | ||
154 | */ | ||
155 | struct v2m_osc { | ||
156 | struct clk_hw hw; | ||
157 | u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */ | ||
158 | u8 stack; /* board stack position */ | ||
159 | u16 osc; | ||
160 | unsigned long rate_min; | ||
161 | unsigned long rate_max; | ||
162 | unsigned long rate_default; | ||
163 | }; | ||
164 | |||
165 | #define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw) | ||
166 | |||
167 | struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc); | ||
168 | |||
147 | #endif | 169 | #endif |
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h index 7dab5596b868..1e472eb0bbdc 100644 --- a/arch/arm/mach-vexpress/include/mach/uncompress.h +++ b/arch/arm/mach-vexpress/include/mach/uncompress.h | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | static unsigned long get_uart_base(void) | 28 | static unsigned long get_uart_base(void) |
29 | { | 29 | { |
30 | #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) | ||
30 | unsigned long mpcore_periph; | 31 | unsigned long mpcore_periph; |
31 | 32 | ||
32 | /* | 33 | /* |
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void) | |||
42 | return UART_BASE; | 43 | return UART_BASE; |
43 | else | 44 | else |
44 | return UART_BASE_RS1; | 45 | return UART_BASE_RS1; |
46 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9) | ||
47 | return UART_BASE; | ||
48 | #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1) | ||
49 | return UART_BASE_RS1; | ||
50 | #else | ||
51 | return 0; | ||
52 | #endif | ||
45 | } | 53 | } |
46 | 54 | ||
47 | /* | 55 | /* |
@@ -51,6 +59,9 @@ static inline void putc(int c) | |||
51 | { | 59 | { |
52 | unsigned long base = get_uart_base(); | 60 | unsigned long base = get_uart_base(); |
53 | 61 | ||
62 | if (!base) | ||
63 | return; | ||
64 | |||
54 | while (AMBA_UART_FR(base) & (1 << 5)) | 65 | while (AMBA_UART_FR(base) & (1 << 5)) |
55 | barrier(); | 66 | barrier(); |
56 | 67 | ||
@@ -61,6 +72,9 @@ static inline void flush(void) | |||
61 | { | 72 | { |
62 | unsigned long base = get_uart_base(); | 73 | unsigned long base = get_uart_base(); |
63 | 74 | ||
75 | if (!base) | ||
76 | return; | ||
77 | |||
64 | while (AMBA_UART_FR(base) & (1 << 3)) | 78 | while (AMBA_UART_FR(base) & (1 << 3)) |
65 | barrier(); | 79 | barrier(); |
66 | } | 80 | } |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index fde26adaef32..37608f22ee31 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
@@ -16,7 +16,10 @@ | |||
16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
17 | #include <linux/usb/isp1760.h> | 17 | #include <linux/usb/isp1760.h> |
18 | #include <linux/clkdev.h> | 18 | #include <linux/clkdev.h> |
19 | #include <linux/clk-provider.h> | ||
19 | #include <linux/mtd/physmap.h> | 20 | #include <linux/mtd/physmap.h> |
21 | #include <linux/regulator/fixed.h> | ||
22 | #include <linux/regulator/machine.h> | ||
20 | 23 | ||
21 | #include <asm/arch_timer.h> | 24 | #include <asm/arch_timer.h> |
22 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
@@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq) | |||
81 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); | 84 | sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0"); |
82 | } | 85 | } |
83 | 86 | ||
84 | static void __init v2m_timer_init(void) | ||
85 | { | ||
86 | v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K)); | ||
87 | v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0); | ||
88 | } | ||
89 | |||
90 | static struct sys_timer v2m_timer = { | ||
91 | .init = v2m_timer_init, | ||
92 | }; | ||
93 | |||
94 | 87 | ||
95 | static DEFINE_SPINLOCK(v2m_cfg_lock); | 88 | static DEFINE_SPINLOCK(v2m_cfg_lock); |
96 | 89 | ||
@@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data) | |||
147 | writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); | 140 | writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET); |
148 | } | 141 | } |
149 | 142 | ||
143 | int v2m_get_master_site(void) | ||
144 | { | ||
145 | u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); | ||
146 | |||
147 | return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1; | ||
148 | } | ||
149 | |||
150 | 150 | ||
151 | static struct resource v2m_pcie_i2c_resource = { | 151 | static struct resource v2m_pcie_i2c_resource = { |
152 | .start = V2M_SERIAL_BUS_PCI, | 152 | .start = V2M_SERIAL_BUS_PCI, |
@@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = { | |||
201 | .dev.platform_data = &v2m_eth_config, | 201 | .dev.platform_data = &v2m_eth_config, |
202 | }; | 202 | }; |
203 | 203 | ||
204 | static struct regulator_consumer_supply v2m_eth_supplies[] = { | ||
205 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
206 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
207 | }; | ||
208 | |||
204 | static struct resource v2m_usb_resources[] = { | 209 | static struct resource v2m_usb_resources[] = { |
205 | { | 210 | { |
206 | .start = V2M_ISP1761, | 211 | .start = V2M_ISP1761, |
@@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = { | |||
319 | }; | 324 | }; |
320 | 325 | ||
321 | 326 | ||
322 | static long v2m_osc_round(struct clk *clk, unsigned long rate) | 327 | static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw, |
328 | unsigned long parent_rate) | ||
329 | { | ||
330 | struct v2m_osc *osc = to_v2m_osc(hw); | ||
331 | |||
332 | return !parent_rate ? osc->rate_default : parent_rate; | ||
333 | } | ||
334 | |||
335 | static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate, | ||
336 | unsigned long *parent_rate) | ||
323 | { | 337 | { |
338 | struct v2m_osc *osc = to_v2m_osc(hw); | ||
339 | |||
340 | if (WARN_ON(rate < osc->rate_min)) | ||
341 | rate = osc->rate_min; | ||
342 | |||
343 | if (WARN_ON(rate > osc->rate_max)) | ||
344 | rate = osc->rate_max; | ||
345 | |||
324 | return rate; | 346 | return rate; |
325 | } | 347 | } |
326 | 348 | ||
327 | static int v2m_osc1_set(struct clk *clk, unsigned long rate) | 349 | static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate, |
350 | unsigned long parent_rate) | ||
328 | { | 351 | { |
329 | return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate); | 352 | struct v2m_osc *osc = to_v2m_osc(hw); |
353 | |||
354 | v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) | | ||
355 | SYS_CFG_STACK(osc->stack) | osc->osc, rate); | ||
356 | |||
357 | return 0; | ||
330 | } | 358 | } |
331 | 359 | ||
332 | static const struct clk_ops osc1_clk_ops = { | 360 | static struct clk_ops v2m_osc_ops = { |
333 | .round = v2m_osc_round, | 361 | .recalc_rate = v2m_osc_recalc_rate, |
334 | .set = v2m_osc1_set, | 362 | .round_rate = v2m_osc_round_rate, |
335 | }; | 363 | .set_rate = v2m_osc_set_rate, |
336 | 364 | }; | |
337 | static struct clk osc1_clk = { | 365 | |
338 | .ops = &osc1_clk_ops, | 366 | struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc) |
339 | .rate = 24000000, | 367 | { |
340 | }; | 368 | struct clk_init_data init; |
341 | 369 | ||
342 | static struct clk osc2_clk = { | 370 | WARN_ON(osc->site > 2); |
343 | .rate = 24000000, | 371 | WARN_ON(osc->stack > 15); |
344 | }; | 372 | WARN_ON(osc->osc > 4095); |
345 | 373 | ||
346 | static struct clk v2m_sp804_clk = { | 374 | init.name = name; |
347 | .rate = 1000000, | 375 | init.ops = &v2m_osc_ops; |
348 | }; | 376 | init.flags = CLK_IS_ROOT; |
349 | 377 | init.num_parents = 0; | |
350 | static struct clk v2m_ref_clk = { | 378 | |
351 | .rate = 32768, | 379 | osc->hw.init = &init; |
352 | }; | 380 | |
353 | 381 | return clk_register(NULL, &osc->hw); | |
354 | static struct clk dummy_apb_pclk; | 382 | } |
355 | 383 | ||
356 | static struct clk_lookup v2m_lookups[] = { | 384 | static struct v2m_osc v2m_mb_osc1 = { |
357 | { /* AMBA bus clock */ | 385 | .site = SYS_CFG_SITE_MB, |
358 | .con_id = "apb_pclk", | 386 | .osc = 1, |
359 | .clk = &dummy_apb_pclk, | 387 | .rate_min = 23750000, |
360 | }, { /* UART0 */ | 388 | .rate_max = 63500000, |
361 | .dev_id = "mb:uart0", | 389 | .rate_default = 23750000, |
362 | .clk = &osc2_clk, | 390 | }; |
363 | }, { /* UART1 */ | 391 | |
364 | .dev_id = "mb:uart1", | 392 | static const char *v2m_ref_clk_periphs[] __initconst = { |
365 | .clk = &osc2_clk, | 393 | "mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */ |
366 | }, { /* UART2 */ | 394 | }; |
367 | .dev_id = "mb:uart2", | 395 | |
368 | .clk = &osc2_clk, | 396 | static const char *v2m_osc1_periphs[] __initconst = { |
369 | }, { /* UART3 */ | 397 | "mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */ |
370 | .dev_id = "mb:uart3", | 398 | }; |
371 | .clk = &osc2_clk, | 399 | |
372 | }, { /* KMI0 */ | 400 | static const char *v2m_osc2_periphs[] __initconst = { |
373 | .dev_id = "mb:kmi0", | 401 | "mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */ |
374 | .clk = &osc2_clk, | 402 | "mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */ |
375 | }, { /* KMI1 */ | 403 | "mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */ |
376 | .dev_id = "mb:kmi1", | 404 | "mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */ |
377 | .clk = &osc2_clk, | 405 | "mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */ |
378 | }, { /* MMC0 */ | 406 | "mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */ |
379 | .dev_id = "mb:mmci", | 407 | "mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */ |
380 | .clk = &osc2_clk, | 408 | }; |
381 | }, { /* CLCD */ | 409 | |
382 | .dev_id = "mb:clcd", | 410 | static void __init v2m_clk_init(void) |
383 | .clk = &osc1_clk, | 411 | { |
384 | }, { /* SP805 WDT */ | 412 | struct clk *clk; |
385 | .dev_id = "mb:wdt", | 413 | int i; |
386 | .clk = &v2m_ref_clk, | 414 | |
387 | }, { /* SP804 timers */ | 415 | clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL, |
388 | .dev_id = "sp804", | 416 | CLK_IS_ROOT, 0); |
389 | .con_id = "v2m-timer0", | 417 | WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL)); |
390 | .clk = &v2m_sp804_clk, | 418 | |
391 | }, { /* SP804 timers */ | 419 | clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL, |
392 | .dev_id = "sp804", | 420 | CLK_IS_ROOT, 32768); |
393 | .con_id = "v2m-timer1", | 421 | for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++) |
394 | .clk = &v2m_sp804_clk, | 422 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i])); |
395 | }, | 423 | |
424 | clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL, | ||
425 | CLK_IS_ROOT, 1000000); | ||
426 | WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804")); | ||
427 | WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804")); | ||
428 | |||
429 | clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1); | ||
430 | for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++) | ||
431 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i])); | ||
432 | |||
433 | clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL, | ||
434 | CLK_IS_ROOT, 24000000); | ||
435 | for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++) | ||
436 | WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i])); | ||
437 | } | ||
438 | |||
439 | static void __init v2m_timer_init(void) | ||
440 | { | ||
441 | v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K)); | ||
442 | v2m_clk_init(); | ||
443 | v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0); | ||
444 | } | ||
445 | |||
446 | static struct sys_timer v2m_timer = { | ||
447 | .init = v2m_timer_init, | ||
396 | }; | 448 | }; |
397 | 449 | ||
398 | static void __init v2m_init_early(void) | 450 | static void __init v2m_init_early(void) |
399 | { | 451 | { |
400 | ct_desc->init_early(); | 452 | if (ct_desc->init_early) |
401 | clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups)); | 453 | ct_desc->init_early(); |
402 | versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); | 454 | versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000); |
403 | } | 455 | } |
404 | 456 | ||
405 | static void v2m_power_off(void) | 457 | static void v2m_power_off(void) |
406 | { | 458 | { |
407 | if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0)) | 459 | if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) |
408 | printk(KERN_EMERG "Unable to shutdown\n"); | 460 | printk(KERN_EMERG "Unable to shutdown\n"); |
409 | } | 461 | } |
410 | 462 | ||
411 | static void v2m_restart(char str, const char *cmd) | 463 | static void v2m_restart(char str, const char *cmd) |
412 | { | 464 | { |
413 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0)) | 465 | if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0)) |
414 | printk(KERN_EMERG "Unable to reboot\n"); | 466 | printk(KERN_EMERG "Unable to reboot\n"); |
415 | } | 467 | } |
416 | 468 | ||
@@ -458,6 +510,9 @@ static void __init v2m_init(void) | |||
458 | { | 510 | { |
459 | int i; | 511 | int i; |
460 | 512 | ||
513 | regulator_register_fixed(0, v2m_eth_supplies, | ||
514 | ARRAY_SIZE(v2m_eth_supplies)); | ||
515 | |||
461 | platform_device_register(&v2m_pcie_i2c_device); | 516 | platform_device_register(&v2m_pcie_i2c_device); |
462 | platform_device_register(&v2m_ddc_i2c_device); | 517 | platform_device_register(&v2m_ddc_i2c_device); |
463 | platform_device_register(&v2m_flash_device); | 518 | platform_device_register(&v2m_flash_device); |
@@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void) | |||
522 | #endif | 577 | #endif |
523 | } | 578 | } |
524 | 579 | ||
525 | static struct clk_lookup v2m_dt_lookups[] = { | ||
526 | { /* AMBA bus clock */ | ||
527 | .con_id = "apb_pclk", | ||
528 | .clk = &dummy_apb_pclk, | ||
529 | }, { /* SP804 timers */ | ||
530 | .dev_id = "sp804", | ||
531 | .con_id = "v2m-timer0", | ||
532 | .clk = &v2m_sp804_clk, | ||
533 | }, { /* SP804 timers */ | ||
534 | .dev_id = "sp804", | ||
535 | .con_id = "v2m-timer1", | ||
536 | .clk = &v2m_sp804_clk, | ||
537 | }, { /* PL180 MMCI */ | ||
538 | .dev_id = "mb:mmci", /* 10005000.mmci */ | ||
539 | .clk = &osc2_clk, | ||
540 | }, { /* PL050 KMI0 */ | ||
541 | .dev_id = "10006000.kmi", | ||
542 | .clk = &osc2_clk, | ||
543 | }, { /* PL050 KMI1 */ | ||
544 | .dev_id = "10007000.kmi", | ||
545 | .clk = &osc2_clk, | ||
546 | }, { /* PL011 UART0 */ | ||
547 | .dev_id = "10009000.uart", | ||
548 | .clk = &osc2_clk, | ||
549 | }, { /* PL011 UART1 */ | ||
550 | .dev_id = "1000a000.uart", | ||
551 | .clk = &osc2_clk, | ||
552 | }, { /* PL011 UART2 */ | ||
553 | .dev_id = "1000b000.uart", | ||
554 | .clk = &osc2_clk, | ||
555 | }, { /* PL011 UART3 */ | ||
556 | .dev_id = "1000c000.uart", | ||
557 | .clk = &osc2_clk, | ||
558 | }, { /* SP805 WDT */ | ||
559 | .dev_id = "1000f000.wdt", | ||
560 | .clk = &v2m_ref_clk, | ||
561 | }, { /* PL111 CLCD */ | ||
562 | .dev_id = "1001f000.clcd", | ||
563 | .clk = &osc1_clk, | ||
564 | }, | ||
565 | /* RS1 memory map */ | ||
566 | { /* PL180 MMCI */ | ||
567 | .dev_id = "mb:mmci", /* 1c050000.mmci */ | ||
568 | .clk = &osc2_clk, | ||
569 | }, { /* PL050 KMI0 */ | ||
570 | .dev_id = "1c060000.kmi", | ||
571 | .clk = &osc2_clk, | ||
572 | }, { /* PL050 KMI1 */ | ||
573 | .dev_id = "1c070000.kmi", | ||
574 | .clk = &osc2_clk, | ||
575 | }, { /* PL011 UART0 */ | ||
576 | .dev_id = "1c090000.uart", | ||
577 | .clk = &osc2_clk, | ||
578 | }, { /* PL011 UART1 */ | ||
579 | .dev_id = "1c0a0000.uart", | ||
580 | .clk = &osc2_clk, | ||
581 | }, { /* PL011 UART2 */ | ||
582 | .dev_id = "1c0b0000.uart", | ||
583 | .clk = &osc2_clk, | ||
584 | }, { /* PL011 UART3 */ | ||
585 | .dev_id = "1c0c0000.uart", | ||
586 | .clk = &osc2_clk, | ||
587 | }, { /* SP805 WDT */ | ||
588 | .dev_id = "1c0f0000.wdt", | ||
589 | .clk = &v2m_ref_clk, | ||
590 | }, { /* PL111 CLCD */ | ||
591 | .dev_id = "1c1f0000.clcd", | ||
592 | .clk = &osc1_clk, | ||
593 | }, | ||
594 | }; | ||
595 | |||
596 | void __init v2m_dt_init_early(void) | 580 | void __init v2m_dt_init_early(void) |
597 | { | 581 | { |
598 | struct device_node *node; | 582 | struct device_node *node; |
@@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void) | |||
605 | 589 | ||
606 | /* Confirm board type against DT property, if available */ | 590 | /* Confirm board type against DT property, if available */ |
607 | if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { | 591 | if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) { |
608 | u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC); | 592 | int site = v2m_get_master_site(); |
609 | u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ? | 593 | u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ? |
610 | V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); | 594 | V2M_SYS_PROCID1 : V2M_SYS_PROCID0)); |
611 | u32 hbi = id & SYS_PROCIDx_HBI_MASK; | 595 | u32 hbi = id & SYS_PROCIDx_HBI_MASK; |
612 | 596 | ||
@@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void) | |||
614 | pr_warning("vexpress: DT HBI (%x) is not matching " | 598 | pr_warning("vexpress: DT HBI (%x) is not matching " |
615 | "hardware (%x)!\n", dt_hbi, hbi); | 599 | "hardware (%x)!\n", dt_hbi, hbi); |
616 | } | 600 | } |
617 | |||
618 | clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups)); | ||
619 | } | 601 | } |
620 | 602 | ||
621 | static struct of_device_id vexpress_irq_match[] __initdata = { | 603 | static struct of_device_id vexpress_irq_match[] __initdata = { |
@@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void) | |||
637 | node = of_find_compatible_node(NULL, NULL, "arm,sp810"); | 619 | node = of_find_compatible_node(NULL, NULL, "arm,sp810"); |
638 | v2m_sysctl_init(of_iomap(node, 0)); | 620 | v2m_sysctl_init(of_iomap(node, 0)); |
639 | 621 | ||
622 | v2m_clk_init(); | ||
623 | |||
640 | err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); | 624 | err = of_property_read_string(of_aliases, "arm,v2m_timer", &path); |
641 | if (WARN_ON(err)) | 625 | if (WARN_ON(err)) |
642 | return; | 626 | return; |
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile index 81aedb7c893c..54e69973f39b 100644 --- a/arch/arm/mach-vt8500/Makefile +++ b/arch/arm/mach-vt8500/Makefile | |||
@@ -1,4 +1,4 @@ | |||
1 | obj-y += devices.o gpio.o irq.o timer.o | 1 | obj-y += devices.o gpio.o irq.o timer.o restart.o |
2 | 2 | ||
3 | obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o | 3 | obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o |
4 | obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o | 4 | obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o |
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c index a464c7584411..f9fbeb2d10e9 100644 --- a/arch/arm/mach-vt8500/bv07.c +++ b/arch/arm/mach-vt8500/bv07.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <mach/restart.h> | ||
26 | 27 | ||
27 | #include "devices.h" | 28 | #include "devices.h" |
28 | 29 | ||
@@ -62,6 +63,7 @@ void __init bv07_init(void) | |||
62 | else | 63 | else |
63 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); | 64 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); |
64 | 65 | ||
66 | wmt_setup_restart(); | ||
65 | vt8500_set_resources(); | 67 | vt8500_set_resources(); |
66 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 68 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
67 | vt8500_gpio_init(); | 69 | vt8500_gpio_init(); |
@@ -69,6 +71,7 @@ void __init bv07_init(void) | |||
69 | 71 | ||
70 | MACHINE_START(BV07, "Benign BV07 Mini Netbook") | 72 | MACHINE_START(BV07, "Benign BV07 Mini Netbook") |
71 | .atag_offset = 0x100, | 73 | .atag_offset = 0x100, |
74 | .restart = wmt_restart, | ||
72 | .reserve = vt8500_reserve_mem, | 75 | .reserve = vt8500_reserve_mem, |
73 | .map_io = vt8500_map_io, | 76 | .map_io = vt8500_map_io, |
74 | .init_irq = vt8500_init_irq, | 77 | .init_irq = vt8500_init_irq, |
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h new file mode 100644 index 000000000000..89f9b787d2a0 --- /dev/null +++ b/arch/arm/mach-vt8500/include/mach/restart.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* linux/arch/arm/mach-vt8500/restart.h | ||
2 | * | ||
3 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
4 | * | ||
5 | * This software is licensed under the terms of the GNU General Public | ||
6 | * License version 2, as published by the Free Software Foundation, and | ||
7 | * may be copied, distributed, and modified under those terms. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | void wmt_setup_restart(void); | ||
17 | void wmt_restart(char mode, const char *cmd); | ||
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h deleted file mode 100644 index 58fa8010ee61..000000000000 --- a/arch/arm/mach-vt8500/include/mach/system.h +++ /dev/null | |||
@@ -1,13 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-vt8500/include/mach/system.h | ||
3 | * | ||
4 | */ | ||
5 | #include <asm/io.h> | ||
6 | |||
7 | /* PM Software Reset request register */ | ||
8 | #define VT8500_PMSR_VIRT 0xf8130060 | ||
9 | |||
10 | static inline void arch_reset(char mode, const char *cmd) | ||
11 | { | ||
12 | writel(1, VT8500_PMSR_VIRT); | ||
13 | } | ||
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c new file mode 100644 index 000000000000..497e89a5e130 --- /dev/null +++ b/arch/arm/mach-vt8500/restart.c | |||
@@ -0,0 +1,54 @@ | |||
1 | /* linux/arch/arm/mach-vt8500/restart.c | ||
2 | * | ||
3 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | ||
4 | * | ||
5 | * This software is licensed under the terms of the GNU General Public | ||
6 | * License version 2, as published by the Free Software Foundation, and | ||
7 | * may be copied, distributed, and modified under those terms. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | */ | ||
15 | #include <asm/io.h> | ||
16 | #include <linux/of.h> | ||
17 | #include <linux/of_address.h> | ||
18 | |||
19 | #define LEGACY_PMC_BASE 0xD8130000 | ||
20 | #define WMT_PRIZM_PMSR_REG 0x60 | ||
21 | |||
22 | static void __iomem *pmc_base; | ||
23 | |||
24 | void wmt_setup_restart(void) | ||
25 | { | ||
26 | struct device_node *np; | ||
27 | |||
28 | /* | ||
29 | * Check if Power Mgmt Controller node is present in device tree. If no | ||
30 | * device tree node, use the legacy PMSR value (valid for all current | ||
31 | * SoCs). | ||
32 | */ | ||
33 | np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc"); | ||
34 | if (np) { | ||
35 | pmc_base = of_iomap(np, 0); | ||
36 | |||
37 | if (!pmc_base) | ||
38 | pr_err("%s:of_iomap(pmc) failed\n", __func__); | ||
39 | |||
40 | of_node_put(np); | ||
41 | } else { | ||
42 | pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000); | ||
43 | if (!pmc_base) { | ||
44 | pr_err("%s:ioremap(rstc) failed\n", __func__); | ||
45 | return; | ||
46 | } | ||
47 | } | ||
48 | } | ||
49 | |||
50 | void wmt_restart(char mode, const char *cmd) | ||
51 | { | ||
52 | if (pmc_base) | ||
53 | writel(1, pmc_base + WMT_PRIZM_PMSR_REG); | ||
54 | } | ||
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c index cf910a956080..db19886caf7c 100644 --- a/arch/arm/mach-vt8500/wm8505_7in.c +++ b/arch/arm/mach-vt8500/wm8505_7in.c | |||
@@ -23,6 +23,7 @@ | |||
23 | 23 | ||
24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include <mach/restart.h> | ||
26 | 27 | ||
27 | #include "devices.h" | 28 | #include "devices.h" |
28 | 29 | ||
@@ -61,7 +62,7 @@ void __init wm8505_7in_init(void) | |||
61 | pm_power_off = &vt8500_power_off; | 62 | pm_power_off = &vt8500_power_off; |
62 | else | 63 | else |
63 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); | 64 | printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n"); |
64 | 65 | wmt_setup_restart(); | |
65 | wm8505_set_resources(); | 66 | wm8505_set_resources(); |
66 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 67 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
67 | vt8500_gpio_init(); | 68 | vt8500_gpio_init(); |
@@ -69,6 +70,7 @@ void __init wm8505_7in_init(void) | |||
69 | 70 | ||
70 | MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") | 71 | MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") |
71 | .atag_offset = 0x100, | 72 | .atag_offset = 0x100, |
73 | .restart = wmt_restart, | ||
72 | .reserve = wm8505_reserve_mem, | 74 | .reserve = wm8505_reserve_mem, |
73 | .map_io = wm8505_map_io, | 75 | .map_io = wm8505_map_io, |
74 | .init_irq = wm8505_init_irq, | 76 | .init_irq = wm8505_init_irq, |
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 4044abcf6f9d..655878bcc96d 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
@@ -1091,7 +1091,7 @@ error: | |||
1091 | while (--i) | 1091 | while (--i) |
1092 | if (pages[i]) | 1092 | if (pages[i]) |
1093 | __free_pages(pages[i], 0); | 1093 | __free_pages(pages[i], 0); |
1094 | if (array_size < PAGE_SIZE) | 1094 | if (array_size <= PAGE_SIZE) |
1095 | kfree(pages); | 1095 | kfree(pages); |
1096 | else | 1096 | else |
1097 | vfree(pages); | 1097 | vfree(pages); |
@@ -1106,7 +1106,7 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s | |||
1106 | for (i = 0; i < count; i++) | 1106 | for (i = 0; i < count; i++) |
1107 | if (pages[i]) | 1107 | if (pages[i]) |
1108 | __free_pages(pages[i], 0); | 1108 | __free_pages(pages[i], 0); |
1109 | if (array_size < PAGE_SIZE) | 1109 | if (array_size <= PAGE_SIZE) |
1110 | kfree(pages); | 1110 | kfree(pages); |
1111 | else | 1111 | else |
1112 | vfree(pages); | 1112 | vfree(pages); |
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c index 16d0ec4df5f6..a5c9ad5721c2 100644 --- a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c +++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c | |||
@@ -20,6 +20,11 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = | |||
20 | imx_mxc_rtc_data_entry_single(MX31); | 20 | imx_mxc_rtc_data_entry_single(MX31); |
21 | #endif /* ifdef CONFIG_SOC_IMX31 */ | 21 | #endif /* ifdef CONFIG_SOC_IMX31 */ |
22 | 22 | ||
23 | #ifdef CONFIG_SOC_IMX35 | ||
24 | const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst = | ||
25 | imx_mxc_rtc_data_entry_single(MX35); | ||
26 | #endif /* ifdef CONFIG_SOC_IMX35 */ | ||
27 | |||
23 | struct platform_device *__init imx_add_mxc_rtc( | 28 | struct platform_device *__init imx_add_mxc_rtc( |
24 | const struct imx_mxc_rtc_data *data) | 29 | const struct imx_mxc_rtc_data *data) |
25 | { | 30 | { |
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index e429ca1b814a..7cfcc44537f0 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
@@ -67,6 +67,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
67 | extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, | 67 | extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, |
68 | unsigned long ckih1, unsigned long ckih2); | 68 | unsigned long ckih1, unsigned long ckih2); |
69 | extern int mx27_clocks_init_dt(void); | 69 | extern int mx27_clocks_init_dt(void); |
70 | extern int mx31_clocks_init_dt(void); | ||
70 | extern int mx51_clocks_init_dt(void); | 71 | extern int mx51_clocks_init_dt(void); |
71 | extern int mx53_clocks_init_dt(void); | 72 | extern int mx53_clocks_init_dt(void); |
72 | extern int mx6q_clocks_init(void); | 73 | extern int mx6q_clocks_init(void); |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 36c8989d9de6..2623e7a2e190 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h | |||
@@ -107,11 +107,13 @@ | |||
107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) | 107 | #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) |
108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) | 108 | #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) |
109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) | 109 | #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) |
110 | #define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) | ||
110 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) | 111 | #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) |
111 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) | 112 | #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) |
112 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) | 113 | #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) |
113 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) | 114 | #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) |
114 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) | 115 | #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) |
116 | #define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) | ||
115 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) | 117 | #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) |
116 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) | 118 | #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) |
117 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) | 119 | #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) |
@@ -228,6 +230,7 @@ | |||
228 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) | 230 | #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) |
229 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) | 231 | #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) |
230 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) | 232 | #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) |
233 | #define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) | ||
231 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) | 234 | #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) |
232 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) | 235 | #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) |
233 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) | 236 | #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) |
@@ -256,12 +259,14 @@ | |||
256 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | 259 | #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
257 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) | 260 | #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) |
258 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) | 261 | #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) |
262 | #define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) | ||
259 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) | 263 | #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) |
260 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) | 264 | #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) |
261 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) | 265 | #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) |
262 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) | 266 | #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) |
263 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) | 267 | #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) |
264 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) | 268 | #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) |
269 | #define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) | ||
265 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) | 270 | #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) |
266 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) | 271 | #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) |
267 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) | 272 | #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) |
@@ -637,7 +642,9 @@ | |||
637 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) | 642 | #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) |
638 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) | 643 | #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) |
639 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) | 644 | #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) |
645 | #define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
640 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) | 646 | #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) |
647 | #define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) | ||
641 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) | 648 | #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) |
642 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) | 649 | #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) |
643 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) | 650 | #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) |
@@ -780,6 +787,8 @@ | |||
780 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) | 787 | #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) |
781 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 788 | #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
782 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) | 789 | #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) |
790 | #define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) | ||
791 | #define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) | ||
783 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) | 792 | #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) |
784 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) | 793 | #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) |
785 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) | 794 | #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) |
@@ -788,13 +797,16 @@ | |||
788 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) | 797 | #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) |
789 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 798 | #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
790 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) | 799 | #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) |
800 | #define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) | ||
791 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) | 801 | #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) |
792 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) | 802 | #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) |
793 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 803 | #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
794 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) | 804 | #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) |
805 | #define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) | ||
795 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) | 806 | #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) |
796 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 807 | #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
797 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) | 808 | #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) |
809 | #define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) | ||
798 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) | 810 | #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) |
799 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 811 | #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
800 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | 812 | #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
@@ -803,11 +815,13 @@ | |||
803 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 815 | #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
804 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) | 816 | #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) |
805 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) | 817 | #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) |
818 | #define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) | ||
806 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) | 819 | #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) |
807 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) | 820 | #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) |
808 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) | 821 | #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) |
809 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) | 822 | #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) |
810 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) | 823 | #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) |
811 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) | 824 | #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) |
825 | #define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) | ||
812 | 826 | ||
813 | #endif /* __MACH_IOMUX_MX51_H__ */ | 827 | #endif /* __MACH_IOMUX_MX51_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 9ffd1bbe615f..7eb9d1329671 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h | |||
@@ -20,13 +20,15 @@ | |||
20 | #define MXC_EHCI_INTERFACE_MASK (0xf) | 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) |
21 | 21 | ||
22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) | 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) |
23 | #define MXC_EHCI_TTL_ENABLED (1 << 6) | 23 | #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) |
24 | 24 | #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) | |
25 | #define MXC_EHCI_INTERNAL_PHY (1 << 7) | 25 | #define MXC_EHCI_TTL_ENABLED (1 << 8) |
26 | #define MXC_EHCI_IPPUE_DOWN (1 << 8) | 26 | |
27 | #define MXC_EHCI_IPPUE_UP (1 << 9) | 27 | #define MXC_EHCI_INTERNAL_PHY (1 << 9) |
28 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 10) | 28 | #define MXC_EHCI_IPPUE_DOWN (1 << 10) |
29 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) | 29 | #define MXC_EHCI_IPPUE_UP (1 << 11) |
30 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 12) | ||
31 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) | ||
30 | 32 | ||
31 | #define MXC_USBCTRL_OFFSET 0 | 33 | #define MXC_USBCTRL_OFFSET 0 |
32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | 34 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index ed8605f01155..6d87532871cd 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
@@ -4,7 +4,7 @@ | |||
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ | 6 | obj-y := common.o sram.o clock.o devices.o dma.o mux.o \ |
7 | usb.o fb.o counter_32k.o | 7 | fb.o counter_32k.o |
8 | obj-m := | 8 | obj-m := |
9 | obj-n := | 9 | obj-n := |
10 | obj- := | 10 | obj- := |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index cb16ade437cb..7fe626761e53 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode); | |||
573 | 573 | ||
574 | static inline void omap_enable_channel_irq(int lch) | 574 | static inline void omap_enable_channel_irq(int lch) |
575 | { | 575 | { |
576 | u32 status; | ||
577 | |||
578 | /* Clear CSR */ | 576 | /* Clear CSR */ |
579 | if (cpu_class_is_omap1()) | 577 | if (cpu_class_is_omap1()) |
580 | status = p->dma_read(CSR, lch); | 578 | p->dma_read(CSR, lch); |
581 | else if (cpu_class_is_omap2()) | 579 | else |
582 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | 580 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); |
583 | 581 | ||
584 | /* Enable some nice interrupts. */ | 582 | /* Enable some nice interrupts. */ |
585 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); | 583 | p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch); |
586 | } | 584 | } |
587 | 585 | ||
588 | static void omap_disable_channel_irq(int lch) | 586 | static inline void omap_disable_channel_irq(int lch) |
589 | { | 587 | { |
590 | if (cpu_class_is_omap2()) | 588 | /* disable channel interrupts */ |
591 | p->dma_write(0, CICR, lch); | 589 | p->dma_write(0, CICR, lch); |
590 | /* Clear CSR */ | ||
591 | if (cpu_class_is_omap1()) | ||
592 | p->dma_read(CSR, lch); | ||
593 | else | ||
594 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | ||
592 | } | 595 | } |
593 | 596 | ||
594 | void omap_enable_dma_irq(int lch, u16 bits) | 597 | void omap_enable_dma_irq(int lch, u16 bits) |
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch) | |||
632 | l = p->dma_read(CLNK_CTRL, lch); | 635 | l = p->dma_read(CLNK_CTRL, lch); |
633 | 636 | ||
634 | /* Disable interrupts */ | 637 | /* Disable interrupts */ |
638 | omap_disable_channel_irq(lch); | ||
639 | |||
635 | if (cpu_class_is_omap1()) { | 640 | if (cpu_class_is_omap1()) { |
636 | p->dma_write(0, CICR, lch); | ||
637 | /* Set the STOP_LNK bit */ | 641 | /* Set the STOP_LNK bit */ |
638 | l |= 1 << 14; | 642 | l |= 1 << 14; |
639 | } | 643 | } |
640 | 644 | ||
641 | if (cpu_class_is_omap2()) { | 645 | if (cpu_class_is_omap2()) { |
642 | omap_disable_channel_irq(lch); | ||
643 | /* Clear the ENABLE_LNK bit */ | 646 | /* Clear the ENABLE_LNK bit */ |
644 | l &= ~(1 << 15); | 647 | l &= ~(1 << 15); |
645 | } | 648 | } |
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch) | |||
657 | return; | 660 | return; |
658 | 661 | ||
659 | spin_lock_irqsave(&dma_chan_lock, flags); | 662 | spin_lock_irqsave(&dma_chan_lock, flags); |
663 | /* clear IRQ STATUS */ | ||
664 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
665 | /* Enable interrupt */ | ||
660 | val = p->dma_read(IRQENABLE_L0, lch); | 666 | val = p->dma_read(IRQENABLE_L0, lch); |
661 | val |= 1 << lch; | 667 | val |= 1 << lch; |
662 | p->dma_write(val, IRQENABLE_L0, lch); | 668 | p->dma_write(val, IRQENABLE_L0, lch); |
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch) | |||
672 | return; | 678 | return; |
673 | 679 | ||
674 | spin_lock_irqsave(&dma_chan_lock, flags); | 680 | spin_lock_irqsave(&dma_chan_lock, flags); |
681 | /* Disable interrupt */ | ||
675 | val = p->dma_read(IRQENABLE_L0, lch); | 682 | val = p->dma_read(IRQENABLE_L0, lch); |
676 | val &= ~(1 << lch); | 683 | val &= ~(1 << lch); |
677 | p->dma_write(val, IRQENABLE_L0, lch); | 684 | p->dma_write(val, IRQENABLE_L0, lch); |
685 | /* clear IRQ STATUS */ | ||
686 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
678 | spin_unlock_irqrestore(&dma_chan_lock, flags); | 687 | spin_unlock_irqrestore(&dma_chan_lock, flags); |
679 | } | 688 | } |
680 | 689 | ||
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
745 | } | 754 | } |
746 | 755 | ||
747 | if (cpu_class_is_omap2()) { | 756 | if (cpu_class_is_omap2()) { |
748 | omap2_enable_irq_lch(free_ch); | ||
749 | omap_enable_channel_irq(free_ch); | 757 | omap_enable_channel_irq(free_ch); |
750 | /* Clear the CSR register and IRQ status register */ | 758 | omap2_enable_irq_lch(free_ch); |
751 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch); | ||
752 | p->dma_write(1 << free_ch, IRQSTATUS_L0, 0); | ||
753 | } | 759 | } |
754 | 760 | ||
755 | *dma_ch_out = free_ch; | 761 | *dma_ch_out = free_ch; |
@@ -768,27 +774,19 @@ void omap_free_dma(int lch) | |||
768 | return; | 774 | return; |
769 | } | 775 | } |
770 | 776 | ||
771 | if (cpu_class_is_omap1()) { | 777 | /* Disable interrupt for logical channel */ |
772 | /* Disable all DMA interrupts for the channel. */ | 778 | if (cpu_class_is_omap2()) |
773 | p->dma_write(0, CICR, lch); | ||
774 | /* Make sure the DMA transfer is stopped. */ | ||
775 | p->dma_write(0, CCR, lch); | ||
776 | } | ||
777 | |||
778 | if (cpu_class_is_omap2()) { | ||
779 | omap2_disable_irq_lch(lch); | 779 | omap2_disable_irq_lch(lch); |
780 | 780 | ||
781 | /* Clear the CSR register and IRQ status register */ | 781 | /* Disable all DMA interrupts for the channel. */ |
782 | p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); | 782 | omap_disable_channel_irq(lch); |
783 | p->dma_write(1 << lch, IRQSTATUS_L0, lch); | ||
784 | 783 | ||
785 | /* Disable all DMA interrupts for the channel. */ | 784 | /* Make sure the DMA transfer is stopped. */ |
786 | p->dma_write(0, CICR, lch); | 785 | p->dma_write(0, CCR, lch); |
787 | 786 | ||
788 | /* Make sure the DMA transfer is stopped. */ | 787 | /* Clear registers */ |
789 | p->dma_write(0, CCR, lch); | 788 | if (cpu_class_is_omap2()) |
790 | omap_clear_dma(lch); | 789 | omap_clear_dma(lch); |
791 | } | ||
792 | 790 | ||
793 | spin_lock_irqsave(&dma_chan_lock, flags); | 791 | spin_lock_irqsave(&dma_chan_lock, flags); |
794 | dma_chan[lch].dev_id = -1; | 792 | dma_chan[lch].dev_id = -1; |
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch) | |||
943 | u32 l; | 941 | u32 l; |
944 | 942 | ||
945 | /* Disable all interrupts on the channel */ | 943 | /* Disable all interrupts on the channel */ |
946 | if (cpu_class_is_omap1()) | 944 | omap_disable_channel_irq(lch); |
947 | p->dma_write(0, CICR, lch); | ||
948 | 945 | ||
949 | l = p->dma_read(CCR, lch); | 946 | l = p->dma_read(CCR, lch); |
950 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && | 947 | if (IS_DMA_ERRATA(DMA_ERRATA_i541) && |
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h index 4814c5b65306..e62f20a5c0af 100644 --- a/arch/arm/plat-omap/include/plat/board.h +++ b/arch/arm/plat-omap/include/plat/board.h | |||
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config { | |||
57 | int (*power_off)(void * data); | 57 | int (*power_off)(void * data); |
58 | }; | 58 | }; |
59 | 59 | ||
60 | struct omap_usb_config { | ||
61 | /* Configure drivers according to the connectors on your board: | ||
62 | * - "A" connector (rectagular) | ||
63 | * ... for host/OHCI use, set "register_host". | ||
64 | * - "B" connector (squarish) or "Mini-B" | ||
65 | * ... for device/gadget use, set "register_dev". | ||
66 | * - "Mini-AB" connector (very similar to Mini-B) | ||
67 | * ... for OTG use as device OR host, initialize "otg" | ||
68 | */ | ||
69 | unsigned register_host:1; | ||
70 | unsigned register_dev:1; | ||
71 | u8 otg; /* port number, 1-based: usb1 == 2 */ | ||
72 | |||
73 | u8 hmc_mode; | ||
74 | |||
75 | /* implicitly true if otg: host supports remote wakeup? */ | ||
76 | u8 rwc; | ||
77 | |||
78 | /* signaling pins used to talk to transceiver on usbN: | ||
79 | * 0 == usbN unused | ||
80 | * 2 == usb0-only, using internal transceiver | ||
81 | * 3 == 3 wire bidirectional | ||
82 | * 4 == 4 wire bidirectional | ||
83 | * 6 == 6 wire unidirectional (or TLL) | ||
84 | */ | ||
85 | u8 pins[3]; | ||
86 | |||
87 | struct platform_device *udc_device; | ||
88 | struct platform_device *ohci_device; | ||
89 | struct platform_device *otg_device; | ||
90 | |||
91 | u32 (*usb0_init)(unsigned nwires, unsigned is_device); | ||
92 | u32 (*usb1_init)(unsigned nwires); | ||
93 | u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup); | ||
94 | |||
95 | int (*ocpi_enable)(void); | ||
96 | }; | ||
97 | |||
98 | struct omap_lcd_config { | 60 | struct omap_lcd_config { |
99 | char panel_name[16]; | 61 | char panel_name[16]; |
100 | char ctrl_name[16]; | 62 | char ctrl_name[16]; |
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h index d0ef57c1d71b..656b9862279e 100644 --- a/arch/arm/plat-omap/include/plat/clock.h +++ b/arch/arm/plat-omap/include/plat/clock.h | |||
@@ -156,7 +156,6 @@ struct dpll_data { | |||
156 | u8 min_divider; | 156 | u8 min_divider; |
157 | u16 max_divider; | 157 | u16 max_divider; |
158 | u8 modes; | 158 | u8 modes; |
159 | #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) | ||
160 | void __iomem *autoidle_reg; | 159 | void __iomem *autoidle_reg; |
161 | void __iomem *idlest_reg; | 160 | void __iomem *idlest_reg; |
162 | u32 autoidle_mask; | 161 | u32 autoidle_mask; |
@@ -167,7 +166,6 @@ struct dpll_data { | |||
167 | u8 auto_recal_bit; | 166 | u8 auto_recal_bit; |
168 | u8 recal_en_bit; | 167 | u8 recal_en_bit; |
169 | u8 recal_st_bit; | 168 | u8 recal_st_bit; |
170 | # endif | ||
171 | u8 flags; | 169 | u8 flags; |
172 | }; | 170 | }; |
173 | 171 | ||
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h index de6c0a08f461..430081ac0c47 100644 --- a/arch/arm/plat-omap/include/plat/cpu.h +++ b/arch/arm/plat-omap/include/plat/cpu.h | |||
@@ -238,9 +238,7 @@ IS_AM_SUBCLASS(335x, 0x335) | |||
238 | /* | 238 | /* |
239 | * Macros to detect individual cpu types. | 239 | * Macros to detect individual cpu types. |
240 | * These are only rarely needed. | 240 | * These are only rarely needed. |
241 | * cpu_is_omap330(): True for OMAP330 | 241 | * cpu_is_omap310(): True for OMAP310 |
242 | * cpu_is_omap730(): True for OMAP730 | ||
243 | * cpu_is_omap850(): True for OMAP850 | ||
244 | * cpu_is_omap1510(): True for OMAP1510 | 242 | * cpu_is_omap1510(): True for OMAP1510 |
245 | * cpu_is_omap1610(): True for OMAP1610 | 243 | * cpu_is_omap1610(): True for OMAP1610 |
246 | * cpu_is_omap1611(): True for OMAP1611 | 244 | * cpu_is_omap1611(): True for OMAP1611 |
@@ -262,8 +260,6 @@ static inline int is_omap ##type (void) \ | |||
262 | } | 260 | } |
263 | 261 | ||
264 | IS_OMAP_TYPE(310, 0x0310) | 262 | IS_OMAP_TYPE(310, 0x0310) |
265 | IS_OMAP_TYPE(730, 0x0730) | ||
266 | IS_OMAP_TYPE(850, 0x0850) | ||
267 | IS_OMAP_TYPE(1510, 0x1510) | 263 | IS_OMAP_TYPE(1510, 0x1510) |
268 | IS_OMAP_TYPE(1610, 0x1610) | 264 | IS_OMAP_TYPE(1610, 0x1610) |
269 | IS_OMAP_TYPE(1611, 0x1611) | 265 | IS_OMAP_TYPE(1611, 0x1611) |
@@ -277,8 +273,6 @@ IS_OMAP_TYPE(2430, 0x2430) | |||
277 | IS_OMAP_TYPE(3430, 0x3430) | 273 | IS_OMAP_TYPE(3430, 0x3430) |
278 | 274 | ||
279 | #define cpu_is_omap310() 0 | 275 | #define cpu_is_omap310() 0 |
280 | #define cpu_is_omap730() 0 | ||
281 | #define cpu_is_omap850() 0 | ||
282 | #define cpu_is_omap1510() 0 | 276 | #define cpu_is_omap1510() 0 |
283 | #define cpu_is_omap1610() 0 | 277 | #define cpu_is_omap1610() 0 |
284 | #define cpu_is_omap5912() 0 | 278 | #define cpu_is_omap5912() 0 |
@@ -294,19 +288,9 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
294 | 288 | ||
295 | /* | 289 | /* |
296 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish | 290 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish |
297 | * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710. | 291 | * between 310 vs. 1510 and 1611B/5912 vs. 1710. |
298 | */ | 292 | */ |
299 | 293 | ||
300 | #if defined(CONFIG_ARCH_OMAP730) | ||
301 | # undef cpu_is_omap730 | ||
302 | # define cpu_is_omap730() is_omap730() | ||
303 | #endif | ||
304 | |||
305 | #if defined(CONFIG_ARCH_OMAP850) | ||
306 | # undef cpu_is_omap850 | ||
307 | # define cpu_is_omap850() is_omap850() | ||
308 | #endif | ||
309 | |||
310 | #if defined(CONFIG_ARCH_OMAP15XX) | 294 | #if defined(CONFIG_ARCH_OMAP15XX) |
311 | # undef cpu_is_omap310 | 295 | # undef cpu_is_omap310 |
312 | # undef cpu_is_omap1510 | 296 | # undef cpu_is_omap1510 |
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h index 9c604b390f9f..5927709b1908 100644 --- a/arch/arm/plat-omap/include/plat/dsp.h +++ b/arch/arm/plat-omap/include/plat/dsp.h | |||
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data { | |||
18 | u32 (*dsp_cm_read)(s16 , u16); | 18 | u32 (*dsp_cm_read)(s16 , u16); |
19 | u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); | 19 | u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16); |
20 | 20 | ||
21 | void (*set_bootaddr)(u32); | ||
22 | void (*set_bootmode)(u8); | ||
23 | |||
21 | phys_addr_t phys_mempool_base; | 24 | phys_addr_t phys_mempool_base; |
22 | phys_addr_t phys_mempool_size; | 25 | phys_addr_t phys_mempool_size; |
23 | }; | 26 | }; |
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h index aeba71796ad9..323948959200 100644 --- a/arch/arm/plat-omap/include/plat/mux.h +++ b/arch/arm/plat-omap/include/plat/mux.h | |||
@@ -99,7 +99,7 @@ | |||
99 | 99 | ||
100 | /* | 100 | /* |
101 | * OMAP730/850 has a slightly different config for the pin mux. | 101 | * OMAP730/850 has a slightly different config for the pin mux. |
102 | * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and | 102 | * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and |
103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h |
104 | * - for pull-up/down, only has one enable bit which is is in the same register | 104 | * - for pull-up/down, only has one enable bit which is is in the same register |
105 | * as mux config | 105 | * as mux config |
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h deleted file mode 100644 index 14272bc1a6fd..000000000000 --- a/arch/arm/plat-omap/include/plat/omap730.h +++ /dev/null | |||
@@ -1,102 +0,0 @@ | |||
1 | /* arch/arm/plat-omap/include/mach/omap730.h | ||
2 | * | ||
3 | * Hardware definitions for TI OMAP730 processor. | ||
4 | * | ||
5 | * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | * | ||
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License along | ||
24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
26 | */ | ||
27 | |||
28 | #ifndef __ASM_ARCH_OMAP730_H | ||
29 | #define __ASM_ARCH_OMAP730_H | ||
30 | |||
31 | /* | ||
32 | * ---------------------------------------------------------------------------- | ||
33 | * Base addresses | ||
34 | * ---------------------------------------------------------------------------- | ||
35 | */ | ||
36 | |||
37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
38 | |||
39 | #define OMAP730_DSP_BASE 0xE0000000 | ||
40 | #define OMAP730_DSP_SIZE 0x50000 | ||
41 | #define OMAP730_DSP_START 0xE0000000 | ||
42 | |||
43 | #define OMAP730_DSPREG_BASE 0xE1000000 | ||
44 | #define OMAP730_DSPREG_SIZE SZ_128K | ||
45 | #define OMAP730_DSPREG_START 0xE1000000 | ||
46 | |||
47 | /* | ||
48 | * ---------------------------------------------------------------------------- | ||
49 | * OMAP730 specific configuration registers | ||
50 | * ---------------------------------------------------------------------------- | ||
51 | */ | ||
52 | #define OMAP730_CONFIG_BASE 0xfffe1000 | ||
53 | #define OMAP730_IO_CONF_0 0xfffe1070 | ||
54 | #define OMAP730_IO_CONF_1 0xfffe1074 | ||
55 | #define OMAP730_IO_CONF_2 0xfffe1078 | ||
56 | #define OMAP730_IO_CONF_3 0xfffe107c | ||
57 | #define OMAP730_IO_CONF_4 0xfffe1080 | ||
58 | #define OMAP730_IO_CONF_5 0xfffe1084 | ||
59 | #define OMAP730_IO_CONF_6 0xfffe1088 | ||
60 | #define OMAP730_IO_CONF_7 0xfffe108c | ||
61 | #define OMAP730_IO_CONF_8 0xfffe1090 | ||
62 | #define OMAP730_IO_CONF_9 0xfffe1094 | ||
63 | #define OMAP730_IO_CONF_10 0xfffe1098 | ||
64 | #define OMAP730_IO_CONF_11 0xfffe109c | ||
65 | #define OMAP730_IO_CONF_12 0xfffe10a0 | ||
66 | #define OMAP730_IO_CONF_13 0xfffe10a4 | ||
67 | |||
68 | #define OMAP730_MODE_1 0xfffe1010 | ||
69 | #define OMAP730_MODE_2 0xfffe1014 | ||
70 | |||
71 | /* CSMI specials: in terms of base + offset */ | ||
72 | #define OMAP730_MODE2_OFFSET 0x14 | ||
73 | |||
74 | /* | ||
75 | * ---------------------------------------------------------------------------- | ||
76 | * OMAP730 traffic controller configuration registers | ||
77 | * ---------------------------------------------------------------------------- | ||
78 | */ | ||
79 | #define OMAP730_FLASH_CFG_0 0xfffecc10 | ||
80 | #define OMAP730_FLASH_ACFG_0 0xfffecc50 | ||
81 | #define OMAP730_FLASH_CFG_1 0xfffecc14 | ||
82 | #define OMAP730_FLASH_ACFG_1 0xfffecc54 | ||
83 | |||
84 | /* | ||
85 | * ---------------------------------------------------------------------------- | ||
86 | * OMAP730 DSP control registers | ||
87 | * ---------------------------------------------------------------------------- | ||
88 | */ | ||
89 | #define OMAP730_ICR_BASE 0xfffbb800 | ||
90 | #define OMAP730_DSP_M_CTL 0xfffbb804 | ||
91 | #define OMAP730_DSP_MMU_BASE 0xfffed200 | ||
92 | |||
93 | /* | ||
94 | * ---------------------------------------------------------------------------- | ||
95 | * OMAP730 PCC_UPLD configuration registers | ||
96 | * ---------------------------------------------------------------------------- | ||
97 | */ | ||
98 | #define OMAP730_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
99 | #define OMAP730_PCC_UPLD_CTRL (OMAP730_PCC_UPLD_CTRL_BASE + 0x00) | ||
100 | |||
101 | #endif /* __ASM_ARCH_OMAP730_H */ | ||
102 | |||
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h deleted file mode 100644 index c33f67981712..000000000000 --- a/arch/arm/plat-omap/include/plat/omap850.h +++ /dev/null | |||
@@ -1,102 +0,0 @@ | |||
1 | /* arch/arm/plat-omap/include/mach/omap850.h | ||
2 | * | ||
3 | * Hardware definitions for TI OMAP850 processor. | ||
4 | * | ||
5 | * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net> | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify it | ||
8 | * under the terms of the GNU General Public License as published by the | ||
9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
10 | * option) any later version. | ||
11 | * | ||
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
22 | * | ||
23 | * You should have received a copy of the GNU General Public License along | ||
24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
26 | */ | ||
27 | |||
28 | #ifndef __ASM_ARCH_OMAP850_H | ||
29 | #define __ASM_ARCH_OMAP850_H | ||
30 | |||
31 | /* | ||
32 | * ---------------------------------------------------------------------------- | ||
33 | * Base addresses | ||
34 | * ---------------------------------------------------------------------------- | ||
35 | */ | ||
36 | |||
37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
38 | |||
39 | #define OMAP850_DSP_BASE 0xE0000000 | ||
40 | #define OMAP850_DSP_SIZE 0x50000 | ||
41 | #define OMAP850_DSP_START 0xE0000000 | ||
42 | |||
43 | #define OMAP850_DSPREG_BASE 0xE1000000 | ||
44 | #define OMAP850_DSPREG_SIZE SZ_128K | ||
45 | #define OMAP850_DSPREG_START 0xE1000000 | ||
46 | |||
47 | /* | ||
48 | * ---------------------------------------------------------------------------- | ||
49 | * OMAP850 specific configuration registers | ||
50 | * ---------------------------------------------------------------------------- | ||
51 | */ | ||
52 | #define OMAP850_CONFIG_BASE 0xfffe1000 | ||
53 | #define OMAP850_IO_CONF_0 0xfffe1070 | ||
54 | #define OMAP850_IO_CONF_1 0xfffe1074 | ||
55 | #define OMAP850_IO_CONF_2 0xfffe1078 | ||
56 | #define OMAP850_IO_CONF_3 0xfffe107c | ||
57 | #define OMAP850_IO_CONF_4 0xfffe1080 | ||
58 | #define OMAP850_IO_CONF_5 0xfffe1084 | ||
59 | #define OMAP850_IO_CONF_6 0xfffe1088 | ||
60 | #define OMAP850_IO_CONF_7 0xfffe108c | ||
61 | #define OMAP850_IO_CONF_8 0xfffe1090 | ||
62 | #define OMAP850_IO_CONF_9 0xfffe1094 | ||
63 | #define OMAP850_IO_CONF_10 0xfffe1098 | ||
64 | #define OMAP850_IO_CONF_11 0xfffe109c | ||
65 | #define OMAP850_IO_CONF_12 0xfffe10a0 | ||
66 | #define OMAP850_IO_CONF_13 0xfffe10a4 | ||
67 | |||
68 | #define OMAP850_MODE_1 0xfffe1010 | ||
69 | #define OMAP850_MODE_2 0xfffe1014 | ||
70 | |||
71 | /* CSMI specials: in terms of base + offset */ | ||
72 | #define OMAP850_MODE2_OFFSET 0x14 | ||
73 | |||
74 | /* | ||
75 | * ---------------------------------------------------------------------------- | ||
76 | * OMAP850 traffic controller configuration registers | ||
77 | * ---------------------------------------------------------------------------- | ||
78 | */ | ||
79 | #define OMAP850_FLASH_CFG_0 0xfffecc10 | ||
80 | #define OMAP850_FLASH_ACFG_0 0xfffecc50 | ||
81 | #define OMAP850_FLASH_CFG_1 0xfffecc14 | ||
82 | #define OMAP850_FLASH_ACFG_1 0xfffecc54 | ||
83 | |||
84 | /* | ||
85 | * ---------------------------------------------------------------------------- | ||
86 | * OMAP850 DSP control registers | ||
87 | * ---------------------------------------------------------------------------- | ||
88 | */ | ||
89 | #define OMAP850_ICR_BASE 0xfffbb800 | ||
90 | #define OMAP850_DSP_M_CTL 0xfffbb804 | ||
91 | #define OMAP850_DSP_MMU_BASE 0xfffed200 | ||
92 | |||
93 | /* | ||
94 | * ---------------------------------------------------------------------------- | ||
95 | * OMAP850 PCC_UPLD configuration registers | ||
96 | * ---------------------------------------------------------------------------- | ||
97 | */ | ||
98 | #define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
99 | #define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) | ||
100 | |||
101 | #endif /* __ASM_ARCH_OMAP850_H */ | ||
102 | |||
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h index c835b7194ff5..a8ecc53b3670 100644 --- a/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h | |||
@@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh); | |||
629 | 629 | ||
630 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); | 630 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx); |
631 | 631 | ||
632 | extern void __init omap_hwmod_init(void); | ||
633 | |||
632 | /* | 634 | /* |
633 | * Chip variant-specific hwmod init routines - XXX should be converted | 635 | * Chip variant-specific hwmod init routines - XXX should be converted |
634 | * to use initcalls once the initial boot ordering is straightened out | 636 | * to use initcalls once the initial boot ordering is straightened out |
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h index b073e5f2b190..28e2d250c2fd 100644 --- a/arch/arm/plat-omap/include/plat/serial.h +++ b/arch/arm/plat-omap/include/plat/serial.h | |||
@@ -60,6 +60,9 @@ | |||
60 | /* AM3505/3517 UART4 */ | 60 | /* AM3505/3517 UART4 */ |
61 | #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ | 61 | #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ |
62 | 62 | ||
63 | /* AM33XX serial port */ | ||
64 | #define AM33XX_UART1_BASE 0x44E09000 | ||
65 | |||
63 | /* External port on Zoom2/3 */ | 66 | /* External port on Zoom2/3 */ |
64 | #define ZOOM_UART_BASE 0x10000000 | 67 | #define ZOOM_UART_BASE 0x10000000 |
65 | #define ZOOM_UART_VIRT 0xfa400000 | 68 | #define ZOOM_UART_VIRT 0xfa400000 |
@@ -93,6 +96,7 @@ | |||
93 | #define TI81XXUART1 81 | 96 | #define TI81XXUART1 81 |
94 | #define TI81XXUART2 82 | 97 | #define TI81XXUART2 82 |
95 | #define TI81XXUART3 83 | 98 | #define TI81XXUART3 83 |
99 | #define AM33XXUART1 84 | ||
96 | #define ZOOM_UART 95 /* Only on zoom2/3 */ | 100 | #define ZOOM_UART 95 /* Only on zoom2/3 */ |
97 | 101 | ||
98 | /* This is only used by 8250.c for omap1510 */ | 102 | /* This is only used by 8250.c for omap1510 */ |
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index cc3f11ba7a99..ac4323390213 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h | |||
@@ -103,6 +103,10 @@ static inline void flush(void) | |||
103 | _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ | 103 | _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ |
104 | TI81XXUART##p) | 104 | TI81XXUART##p) |
105 | 105 | ||
106 | #define DEBUG_LL_AM33XX(p, mach) \ | ||
107 | _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ | ||
108 | AM33XXUART##p) | ||
109 | |||
106 | static inline void __arch_decomp_setup(unsigned long arch_id) | 110 | static inline void __arch_decomp_setup(unsigned long arch_id) |
107 | { | 111 | { |
108 | int port = 0; | 112 | int port = 0; |
@@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id) | |||
183 | /* TI8148 base boards using UART1 */ | 187 | /* TI8148 base boards using UART1 */ |
184 | DEBUG_LL_TI81XX(1, ti8148evm); | 188 | DEBUG_LL_TI81XX(1, ti8148evm); |
185 | 189 | ||
190 | /* AM33XX base boards using UART1 */ | ||
191 | DEBUG_LL_AM33XX(1, am335xevm); | ||
186 | } while (0); | 192 | } while (0); |
187 | } | 193 | } |
188 | 194 | ||
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h index 762eeb0626c1..548a4c8d63df 100644 --- a/arch/arm/plat-omap/include/plat/usb.h +++ b/arch/arm/plat-omap/include/plat/usb.h | |||
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data { | |||
44 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; | 44 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; |
45 | }; | 45 | }; |
46 | 46 | ||
47 | #ifdef CONFIG_ARCH_OMAP2PLUS | ||
48 | |||
47 | struct ehci_hcd_omap_platform_data { | 49 | struct ehci_hcd_omap_platform_data { |
48 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | 50 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; |
49 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; | 51 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; |
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data { | |||
64 | }; | 66 | }; |
65 | /*-------------------------------------------------------------------------*/ | 67 | /*-------------------------------------------------------------------------*/ |
66 | 68 | ||
67 | #define OMAP1_OTG_BASE 0xfffb0400 | ||
68 | #define OMAP1_UDC_BASE 0xfffb4000 | ||
69 | #define OMAP1_OHCI_BASE 0xfffba000 | ||
70 | |||
71 | #define OMAP2_OHCI_BASE 0x4805e000 | ||
72 | #define OMAP2_UDC_BASE 0x4805e200 | ||
73 | #define OMAP2_OTG_BASE 0x4805e300 | ||
74 | |||
75 | #ifdef CONFIG_ARCH_OMAP1 | ||
76 | |||
77 | #define OTG_BASE OMAP1_OTG_BASE | ||
78 | #define UDC_BASE OMAP1_UDC_BASE | ||
79 | #define OMAP_OHCI_BASE OMAP1_OHCI_BASE | ||
80 | |||
81 | #else | ||
82 | |||
83 | #define OTG_BASE OMAP2_OTG_BASE | ||
84 | #define UDC_BASE OMAP2_UDC_BASE | ||
85 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | ||
86 | |||
87 | struct omap_musb_board_data { | 69 | struct omap_musb_board_data { |
88 | u8 interface_type; | 70 | u8 interface_type; |
89 | u8 mode; | 71 | u8 mode; |
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev); | |||
107 | extern int omap4430_phy_exit(struct device *dev); | 89 | extern int omap4430_phy_exit(struct device *dev); |
108 | extern int omap4430_phy_suspend(struct device *dev, int suspend); | 90 | extern int omap4430_phy_suspend(struct device *dev, int suspend); |
109 | 91 | ||
110 | /* | ||
111 | * NOTE: Please update omap USB drivers to use ioremap + read/write | ||
112 | */ | ||
113 | |||
114 | #define OMAP2_L4_IO_OFFSET 0xb2000000 | ||
115 | #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) | ||
116 | |||
117 | static inline u8 omap_readb(u32 pa) | ||
118 | { | ||
119 | return __raw_readb(OMAP2_L4_IO_ADDRESS(pa)); | ||
120 | } | ||
121 | |||
122 | static inline u16 omap_readw(u32 pa) | ||
123 | { | ||
124 | return __raw_readw(OMAP2_L4_IO_ADDRESS(pa)); | ||
125 | } | ||
126 | |||
127 | static inline u32 omap_readl(u32 pa) | ||
128 | { | ||
129 | return __raw_readl(OMAP2_L4_IO_ADDRESS(pa)); | ||
130 | } | ||
131 | |||
132 | static inline void omap_writeb(u8 v, u32 pa) | ||
133 | { | ||
134 | __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
135 | } | ||
136 | |||
137 | |||
138 | static inline void omap_writew(u16 v, u32 pa) | ||
139 | { | ||
140 | __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
141 | } | ||
142 | |||
143 | static inline void omap_writel(u32 v, u32 pa) | ||
144 | { | ||
145 | __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa)); | ||
146 | } | ||
147 | |||
148 | #endif | 92 | #endif |
149 | 93 | ||
150 | extern void am35x_musb_reset(void); | 94 | extern void am35x_musb_reset(void); |
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void); | |||
153 | extern void am35x_set_mode(u8 musb_mode); | 97 | extern void am35x_set_mode(u8 musb_mode); |
154 | extern void ti81xx_musb_phy_power(u8 on); | 98 | extern void ti81xx_musb_phy_power(u8 on); |
155 | 99 | ||
156 | /* | ||
157 | * FIXME correct answer depends on hmc_mode, | ||
158 | * as does (on omap1) any nonzero value for config->otg port number | ||
159 | */ | ||
160 | #ifdef CONFIG_USB_GADGET_OMAP | ||
161 | #define is_usb0_device(config) 1 | ||
162 | #else | ||
163 | #define is_usb0_device(config) 0 | ||
164 | #endif | ||
165 | |||
166 | void omap_otg_init(struct omap_usb_config *config); | ||
167 | |||
168 | #if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE) | ||
169 | void omap1_usb_init(struct omap_usb_config *pdata); | ||
170 | #else | ||
171 | static inline void omap1_usb_init(struct omap_usb_config *pdata) | ||
172 | { | ||
173 | } | ||
174 | #endif | ||
175 | |||
176 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE) | ||
177 | void omap2_usbfs_init(struct omap_usb_config *pdata); | ||
178 | #else | ||
179 | static inline void omap2_usbfs_init(struct omap_usb_config *pdata) | ||
180 | { | ||
181 | } | ||
182 | #endif | ||
183 | |||
184 | /*-------------------------------------------------------------------------*/ | ||
185 | |||
186 | /* | ||
187 | * OTG and transceiver registers, for OMAPs starting with ARM926 | ||
188 | */ | ||
189 | #define OTG_REV (OTG_BASE + 0x00) | ||
190 | #define OTG_SYSCON_1 (OTG_BASE + 0x04) | ||
191 | # define USB2_TRX_MODE(w) (((w)>>24)&0x07) | ||
192 | # define USB1_TRX_MODE(w) (((w)>>20)&0x07) | ||
193 | # define USB0_TRX_MODE(w) (((w)>>16)&0x07) | ||
194 | # define OTG_IDLE_EN (1 << 15) | ||
195 | # define HST_IDLE_EN (1 << 14) | ||
196 | # define DEV_IDLE_EN (1 << 13) | ||
197 | # define OTG_RESET_DONE (1 << 2) | ||
198 | # define OTG_SOFT_RESET (1 << 1) | ||
199 | #define OTG_SYSCON_2 (OTG_BASE + 0x08) | ||
200 | # define OTG_EN (1 << 31) | ||
201 | # define USBX_SYNCHRO (1 << 30) | ||
202 | # define OTG_MST16 (1 << 29) | ||
203 | # define SRP_GPDATA (1 << 28) | ||
204 | # define SRP_GPDVBUS (1 << 27) | ||
205 | # define SRP_GPUVBUS(w) (((w)>>24)&0x07) | ||
206 | # define A_WAIT_VRISE(w) (((w)>>20)&0x07) | ||
207 | # define B_ASE_BRST(w) (((w)>>16)&0x07) | ||
208 | # define SRP_DPW (1 << 14) | ||
209 | # define SRP_DATA (1 << 13) | ||
210 | # define SRP_VBUS (1 << 12) | ||
211 | # define OTG_PADEN (1 << 10) | ||
212 | # define HMC_PADEN (1 << 9) | ||
213 | # define UHOST_EN (1 << 8) | ||
214 | # define HMC_TLLSPEED (1 << 7) | ||
215 | # define HMC_TLLATTACH (1 << 6) | ||
216 | # define OTG_HMC(w) (((w)>>0)&0x3f) | ||
217 | #define OTG_CTRL (OTG_BASE + 0x0c) | ||
218 | # define OTG_USB2_EN (1 << 29) | ||
219 | # define OTG_USB2_DP (1 << 28) | ||
220 | # define OTG_USB2_DM (1 << 27) | ||
221 | # define OTG_USB1_EN (1 << 26) | ||
222 | # define OTG_USB1_DP (1 << 25) | ||
223 | # define OTG_USB1_DM (1 << 24) | ||
224 | # define OTG_USB0_EN (1 << 23) | ||
225 | # define OTG_USB0_DP (1 << 22) | ||
226 | # define OTG_USB0_DM (1 << 21) | ||
227 | # define OTG_ASESSVLD (1 << 20) | ||
228 | # define OTG_BSESSEND (1 << 19) | ||
229 | # define OTG_BSESSVLD (1 << 18) | ||
230 | # define OTG_VBUSVLD (1 << 17) | ||
231 | # define OTG_ID (1 << 16) | ||
232 | # define OTG_DRIVER_SEL (1 << 15) | ||
233 | # define OTG_A_SETB_HNPEN (1 << 12) | ||
234 | # define OTG_A_BUSREQ (1 << 11) | ||
235 | # define OTG_B_HNPEN (1 << 9) | ||
236 | # define OTG_B_BUSREQ (1 << 8) | ||
237 | # define OTG_BUSDROP (1 << 7) | ||
238 | # define OTG_PULLDOWN (1 << 5) | ||
239 | # define OTG_PULLUP (1 << 4) | ||
240 | # define OTG_DRV_VBUS (1 << 3) | ||
241 | # define OTG_PD_VBUS (1 << 2) | ||
242 | # define OTG_PU_VBUS (1 << 1) | ||
243 | # define OTG_PU_ID (1 << 0) | ||
244 | #define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */ | ||
245 | # define DRIVER_SWITCH (1 << 15) | ||
246 | # define A_VBUS_ERR (1 << 13) | ||
247 | # define A_REQ_TMROUT (1 << 12) | ||
248 | # define A_SRP_DETECT (1 << 11) | ||
249 | # define B_HNP_FAIL (1 << 10) | ||
250 | # define B_SRP_TMROUT (1 << 9) | ||
251 | # define B_SRP_DONE (1 << 8) | ||
252 | # define B_SRP_STARTED (1 << 7) | ||
253 | # define OPRT_CHG (1 << 0) | ||
254 | #define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */ | ||
255 | // same bits as in IRQ_EN | ||
256 | #define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */ | ||
257 | # define OTGVPD (1 << 14) | ||
258 | # define OTGVPU (1 << 13) | ||
259 | # define OTGPUID (1 << 12) | ||
260 | # define USB2VDR (1 << 10) | ||
261 | # define USB2PDEN (1 << 9) | ||
262 | # define USB2PUEN (1 << 8) | ||
263 | # define USB1VDR (1 << 6) | ||
264 | # define USB1PDEN (1 << 5) | ||
265 | # define USB1PUEN (1 << 4) | ||
266 | # define USB0VDR (1 << 2) | ||
267 | # define USB0PDEN (1 << 1) | ||
268 | # define USB0PUEN (1 << 0) | ||
269 | #define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */ | ||
270 | #define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */ | ||
271 | |||
272 | /*-------------------------------------------------------------------------*/ | ||
273 | |||
274 | /* OMAP1 */ | ||
275 | #define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064) | ||
276 | # define CONF_USB2_UNI_R (1 << 8) | ||
277 | # define CONF_USB1_UNI_R (1 << 7) | ||
278 | # define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) | ||
279 | # define CONF_USB0_ISOLATE_R (1 << 3) | ||
280 | # define CONF_USB_PWRDN_DM_R (1 << 2) | ||
281 | # define CONF_USB_PWRDN_DP_R (1 << 1) | ||
282 | |||
283 | /* OMAP2 */ | ||
284 | # define USB_UNIDIR 0x0 | ||
285 | # define USB_UNIDIR_TLL 0x1 | ||
286 | # define USB_BIDIR 0x2 | ||
287 | # define USB_BIDIR_TLL 0x3 | ||
288 | # define USBTXWRMODEI(port, x) ((x) << (22 - (port * 2))) | ||
289 | # define USBT2TLL5PI (1 << 17) | ||
290 | # define USB0PUENACTLOI (1 << 16) | ||
291 | # define USBSTANDBYCTRL (1 << 15) | ||
292 | /* AM35x */ | 100 | /* AM35x */ |
293 | /* USB 2.0 PHY Control */ | 101 | /* USB 2.0 PHY Control */ |
294 | #define CONF2_PHY_GPIOMODE (1 << 23) | 102 | #define CONF2_PHY_GPIOMODE (1 << 23) |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index ad32621aa52e..5e13c3884aa4 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
@@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox) | |||
282 | } | 282 | } |
283 | mbox->rxq = mq; | 283 | mbox->rxq = mq; |
284 | mq->mbox = mbox; | 284 | mq->mbox = mbox; |
285 | |||
286 | omap_mbox_enable_irq(mbox, IRQ_RX); | ||
285 | } | 287 | } |
286 | mutex_unlock(&mbox_configured_lock); | 288 | mutex_unlock(&mbox_configured_lock); |
287 | return 0; | 289 | return 0; |
@@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox) | |||
305 | mutex_lock(&mbox_configured_lock); | 307 | mutex_lock(&mbox_configured_lock); |
306 | 308 | ||
307 | if (!--mbox->use_count) { | 309 | if (!--mbox->use_count) { |
310 | omap_mbox_disable_irq(mbox, IRQ_RX); | ||
308 | free_irq(mbox->irq, mbox); | 311 | free_irq(mbox->irq, mbox); |
309 | tasklet_kill(&mbox->txq->tasklet); | 312 | tasklet_kill(&mbox->txq->tasklet); |
310 | flush_work_sync(&mbox->rxq->work); | 313 | flush_work_sync(&mbox->rxq->work); |
@@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb) | |||
338 | if (!mbox) | 341 | if (!mbox) |
339 | return ERR_PTR(-ENOENT); | 342 | return ERR_PTR(-ENOENT); |
340 | 343 | ||
341 | ret = omap_mbox_startup(mbox); | ||
342 | if (ret) | ||
343 | return ERR_PTR(-ENODEV); | ||
344 | |||
345 | if (nb) | 344 | if (nb) |
346 | blocking_notifier_chain_register(&mbox->notifier, nb); | 345 | blocking_notifier_chain_register(&mbox->notifier, nb); |
347 | 346 | ||
347 | ret = omap_mbox_startup(mbox); | ||
348 | if (ret) { | ||
349 | blocking_notifier_chain_unregister(&mbox->notifier, nb); | ||
350 | return ERR_PTR(-ENODEV); | ||
351 | } | ||
352 | |||
348 | return mbox; | 353 | return mbox; |
349 | } | 354 | } |
350 | EXPORT_SYMBOL(omap_mbox_get); | 355 | EXPORT_SYMBOL(omap_mbox_get); |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c deleted file mode 100644 index daa0327381b5..000000000000 --- a/arch/arm/plat-omap/usb.c +++ /dev/null | |||
@@ -1,145 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/plat-omap/usb.c -- platform level USB initialization | ||
3 | * | ||
4 | * Copyright (C) 2004 Texas Instruments, Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #undef DEBUG | ||
22 | |||
23 | #include <linux/module.h> | ||
24 | #include <linux/kernel.h> | ||
25 | #include <linux/init.h> | ||
26 | #include <linux/platform_device.h> | ||
27 | #include <linux/io.h> | ||
28 | |||
29 | #include <plat/usb.h> | ||
30 | #include <plat/board.h> | ||
31 | |||
32 | #include <mach/hardware.h> | ||
33 | |||
34 | #ifdef CONFIG_ARCH_OMAP_OTG | ||
35 | |||
36 | void __init | ||
37 | omap_otg_init(struct omap_usb_config *config) | ||
38 | { | ||
39 | u32 syscon; | ||
40 | int alt_pingroup = 0; | ||
41 | |||
42 | /* NOTE: no bus or clock setup (yet?) */ | ||
43 | |||
44 | syscon = omap_readl(OTG_SYSCON_1) & 0xffff; | ||
45 | if (!(syscon & OTG_RESET_DONE)) | ||
46 | pr_debug("USB resets not complete?\n"); | ||
47 | |||
48 | //omap_writew(0, OTG_IRQ_EN); | ||
49 | |||
50 | /* pin muxing and transceiver pinouts */ | ||
51 | if (config->pins[0] > 2) /* alt pingroup 2 */ | ||
52 | alt_pingroup = 1; | ||
53 | syscon |= config->usb0_init(config->pins[0], is_usb0_device(config)); | ||
54 | syscon |= config->usb1_init(config->pins[1]); | ||
55 | syscon |= config->usb2_init(config->pins[2], alt_pingroup); | ||
56 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
57 | omap_writel(syscon, OTG_SYSCON_1); | ||
58 | |||
59 | syscon = config->hmc_mode; | ||
60 | syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; | ||
61 | #ifdef CONFIG_USB_OTG | ||
62 | if (config->otg) | ||
63 | syscon |= OTG_EN; | ||
64 | #endif | ||
65 | if (cpu_class_is_omap1()) | ||
66 | pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", | ||
67 | omap_readl(USB_TRANSCEIVER_CTRL)); | ||
68 | pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); | ||
69 | omap_writel(syscon, OTG_SYSCON_2); | ||
70 | |||
71 | printk("USB: hmc %d", config->hmc_mode); | ||
72 | if (!alt_pingroup) | ||
73 | printk(", usb2 alt %d wires", config->pins[2]); | ||
74 | else if (config->pins[0]) | ||
75 | printk(", usb0 %d wires%s", config->pins[0], | ||
76 | is_usb0_device(config) ? " (dev)" : ""); | ||
77 | if (config->pins[1]) | ||
78 | printk(", usb1 %d wires", config->pins[1]); | ||
79 | if (!alt_pingroup && config->pins[2]) | ||
80 | printk(", usb2 %d wires", config->pins[2]); | ||
81 | if (config->otg) | ||
82 | printk(", Mini-AB on usb%d", config->otg - 1); | ||
83 | printk("\n"); | ||
84 | |||
85 | if (cpu_class_is_omap1()) { | ||
86 | u16 w; | ||
87 | |||
88 | /* leave USB clocks/controllers off until needed */ | ||
89 | w = omap_readw(ULPD_SOFT_REQ); | ||
90 | w &= ~SOFT_USB_CLK_REQ; | ||
91 | omap_writew(w, ULPD_SOFT_REQ); | ||
92 | |||
93 | w = omap_readw(ULPD_CLOCK_CTRL); | ||
94 | w &= ~USB_MCLK_EN; | ||
95 | w |= DIS_USB_PVCI_CLK; | ||
96 | omap_writew(w, ULPD_CLOCK_CTRL); | ||
97 | } | ||
98 | syscon = omap_readl(OTG_SYSCON_1); | ||
99 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; | ||
100 | |||
101 | #ifdef CONFIG_USB_GADGET_OMAP | ||
102 | if (config->otg || config->register_dev) { | ||
103 | struct platform_device *udc_device = config->udc_device; | ||
104 | int status; | ||
105 | |||
106 | syscon &= ~DEV_IDLE_EN; | ||
107 | udc_device->dev.platform_data = config; | ||
108 | status = platform_device_register(udc_device); | ||
109 | if (status) | ||
110 | pr_debug("can't register UDC device, %d\n", status); | ||
111 | } | ||
112 | #endif | ||
113 | |||
114 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
115 | if (config->otg || config->register_host) { | ||
116 | struct platform_device *ohci_device = config->ohci_device; | ||
117 | int status; | ||
118 | |||
119 | syscon &= ~HST_IDLE_EN; | ||
120 | ohci_device->dev.platform_data = config; | ||
121 | status = platform_device_register(ohci_device); | ||
122 | if (status) | ||
123 | pr_debug("can't register OHCI device, %d\n", status); | ||
124 | } | ||
125 | #endif | ||
126 | |||
127 | #ifdef CONFIG_USB_OTG | ||
128 | if (config->otg) { | ||
129 | struct platform_device *otg_device = config->otg_device; | ||
130 | int status; | ||
131 | |||
132 | syscon &= ~OTG_IDLE_EN; | ||
133 | otg_device->dev.platform_data = config; | ||
134 | status = platform_device_register(otg_device); | ||
135 | if (status) | ||
136 | pr_debug("can't register OTG device, %d\n", status); | ||
137 | } | ||
138 | #endif | ||
139 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); | ||
140 | omap_writel(syscon, OTG_SYSCON_1); | ||
141 | } | ||
142 | |||
143 | #else | ||
144 | void omap_otg_init(struct omap_usb_config *config) {} | ||
145 | #endif | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a2fae4ea0936..7aca31c1df1f 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -78,6 +78,10 @@ config S5P_HRT | |||
78 | 78 | ||
79 | # clock options | 79 | # clock options |
80 | 80 | ||
81 | config SAMSUNG_CLOCK | ||
82 | bool | ||
83 | default y if !COMMON_CLK | ||
84 | |||
81 | config SAMSUNG_CLKSRC | 85 | config SAMSUNG_CLKSRC |
82 | bool | 86 | bool |
83 | help | 87 | help |
@@ -491,14 +495,6 @@ config S5P_SLEEP | |||
491 | Internal config node to apply common S5P sleep management code. | 495 | Internal config node to apply common S5P sleep management code. |
492 | Can be selected by S5P and newer SoCs with similar sleep procedure. | 496 | Can be selected by S5P and newer SoCs with similar sleep procedure. |
493 | 497 | ||
494 | comment "Power Domain" | ||
495 | |||
496 | config SAMSUNG_PD | ||
497 | bool "Samsung Power Domain" | ||
498 | depends on PM_RUNTIME | ||
499 | help | ||
500 | Say Y here if you want to control Power Domain by Runtime PM. | ||
501 | |||
502 | config DEBUG_S3C_UART | 498 | config DEBUG_S3C_UART |
503 | depends on PLAT_SAMSUNG | 499 | depends on PLAT_SAMSUNG |
504 | int | 500 | int |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 860b2db4db15..b78717496677 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -15,8 +15,8 @@ obj-y += init.o cpu.o | |||
15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o | 15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o |
16 | obj-$(CONFIG_S5P_HRT) += s5p-time.o | 16 | obj-$(CONFIG_S5P_HRT) += s5p-time.o |
17 | 17 | ||
18 | obj-y += clock.o | 18 | obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o |
19 | obj-y += pwm-clock.o | 19 | obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o |
20 | 20 | ||
21 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o | 21 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o |
22 | obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o | 22 | obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o |
@@ -60,10 +60,6 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o | |||
60 | obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o | 60 | obj-$(CONFIG_S5P_PM) += s5p-pm.o s5p-irq-pm.o |
61 | obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o | 61 | obj-$(CONFIG_S5P_SLEEP) += s5p-sleep.o |
62 | 62 | ||
63 | # PD support | ||
64 | |||
65 | obj-$(CONFIG_SAMSUNG_PD) += pd.o | ||
66 | |||
67 | # PWM support | 63 | # PWM support |
68 | 64 | ||
69 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 65 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 33ecd0c9f0c3..b1e05ccff3ac 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
@@ -157,11 +157,13 @@ int s3c_adc_start(struct s3c_adc_client *client, | |||
157 | return -EINVAL; | 157 | return -EINVAL; |
158 | } | 158 | } |
159 | 159 | ||
160 | if (client->is_ts && adc->ts_pend) | ||
161 | return -EAGAIN; | ||
162 | |||
163 | spin_lock_irqsave(&adc->lock, flags); | 160 | spin_lock_irqsave(&adc->lock, flags); |
164 | 161 | ||
162 | if (client->is_ts && adc->ts_pend) { | ||
163 | spin_unlock_irqrestore(&adc->lock, flags); | ||
164 | return -EAGAIN; | ||
165 | } | ||
166 | |||
165 | client->channel = channel; | 167 | client->channel = channel; |
166 | client->nr_samples = nr_samples; | 168 | client->nr_samples = nr_samples; |
167 | 169 | ||
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 1d214cb9d770..74e31ce35538 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
@@ -126,7 +126,8 @@ struct platform_device s3c_device_adc = { | |||
126 | #ifdef CONFIG_CPU_S3C2440 | 126 | #ifdef CONFIG_CPU_S3C2440 |
127 | static struct resource s3c_camif_resource[] = { | 127 | static struct resource s3c_camif_resource[] = { |
128 | [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), | 128 | [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF), |
129 | [1] = DEFINE_RES_IRQ(IRQ_CAM), | 129 | [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C), |
130 | [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P), | ||
130 | }; | 131 | }; |
131 | 132 | ||
132 | struct platform_device s3c_device_camif = { | 133 | struct platform_device s3c_device_camif = { |
@@ -1512,7 +1513,7 @@ static struct resource s3c64xx_spi0_resource[] = { | |||
1512 | }; | 1513 | }; |
1513 | 1514 | ||
1514 | struct platform_device s3c64xx_device_spi0 = { | 1515 | struct platform_device s3c64xx_device_spi0 = { |
1515 | .name = "s3c64xx-spi", | 1516 | .name = "s3c6410-spi", |
1516 | .id = 0, | 1517 | .id = 0, |
1517 | .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), | 1518 | .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource), |
1518 | .resource = s3c64xx_spi0_resource, | 1519 | .resource = s3c64xx_spi0_resource, |
@@ -1522,13 +1523,10 @@ struct platform_device s3c64xx_device_spi0 = { | |||
1522 | }, | 1523 | }, |
1523 | }; | 1524 | }; |
1524 | 1525 | ||
1525 | void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, | 1526 | void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
1526 | int src_clk_nr, int num_cs) | 1527 | int num_cs) |
1527 | { | 1528 | { |
1528 | if (!pd) { | 1529 | struct s3c64xx_spi_info pd; |
1529 | pr_err("%s:Need to pass platform data\n", __func__); | ||
1530 | return; | ||
1531 | } | ||
1532 | 1530 | ||
1533 | /* Reject invalid configuration */ | 1531 | /* Reject invalid configuration */ |
1534 | if (!num_cs || src_clk_nr < 0) { | 1532 | if (!num_cs || src_clk_nr < 0) { |
@@ -1536,12 +1534,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, | |||
1536 | return; | 1534 | return; |
1537 | } | 1535 | } |
1538 | 1536 | ||
1539 | pd->num_cs = num_cs; | 1537 | pd.num_cs = num_cs; |
1540 | pd->src_clk_nr = src_clk_nr; | 1538 | pd.src_clk_nr = src_clk_nr; |
1541 | if (!pd->cfg_gpio) | 1539 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; |
1542 | pd->cfg_gpio = s3c64xx_spi0_cfg_gpio; | ||
1543 | 1540 | ||
1544 | s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0); | 1541 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0); |
1545 | } | 1542 | } |
1546 | #endif /* CONFIG_S3C64XX_DEV_SPI0 */ | 1543 | #endif /* CONFIG_S3C64XX_DEV_SPI0 */ |
1547 | 1544 | ||
@@ -1554,7 +1551,7 @@ static struct resource s3c64xx_spi1_resource[] = { | |||
1554 | }; | 1551 | }; |
1555 | 1552 | ||
1556 | struct platform_device s3c64xx_device_spi1 = { | 1553 | struct platform_device s3c64xx_device_spi1 = { |
1557 | .name = "s3c64xx-spi", | 1554 | .name = "s3c6410-spi", |
1558 | .id = 1, | 1555 | .id = 1, |
1559 | .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), | 1556 | .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource), |
1560 | .resource = s3c64xx_spi1_resource, | 1557 | .resource = s3c64xx_spi1_resource, |
@@ -1564,26 +1561,20 @@ struct platform_device s3c64xx_device_spi1 = { | |||
1564 | }, | 1561 | }, |
1565 | }; | 1562 | }; |
1566 | 1563 | ||
1567 | void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, | 1564 | void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
1568 | int src_clk_nr, int num_cs) | 1565 | int num_cs) |
1569 | { | 1566 | { |
1570 | if (!pd) { | ||
1571 | pr_err("%s:Need to pass platform data\n", __func__); | ||
1572 | return; | ||
1573 | } | ||
1574 | |||
1575 | /* Reject invalid configuration */ | 1567 | /* Reject invalid configuration */ |
1576 | if (!num_cs || src_clk_nr < 0) { | 1568 | if (!num_cs || src_clk_nr < 0) { |
1577 | pr_err("%s: Invalid SPI configuration\n", __func__); | 1569 | pr_err("%s: Invalid SPI configuration\n", __func__); |
1578 | return; | 1570 | return; |
1579 | } | 1571 | } |
1580 | 1572 | ||
1581 | pd->num_cs = num_cs; | 1573 | pd.num_cs = num_cs; |
1582 | pd->src_clk_nr = src_clk_nr; | 1574 | pd.src_clk_nr = src_clk_nr; |
1583 | if (!pd->cfg_gpio) | 1575 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; |
1584 | pd->cfg_gpio = s3c64xx_spi1_cfg_gpio; | ||
1585 | 1576 | ||
1586 | s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1); | 1577 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); |
1587 | } | 1578 | } |
1588 | #endif /* CONFIG_S3C64XX_DEV_SPI1 */ | 1579 | #endif /* CONFIG_S3C64XX_DEV_SPI1 */ |
1589 | 1580 | ||
@@ -1596,7 +1587,7 @@ static struct resource s3c64xx_spi2_resource[] = { | |||
1596 | }; | 1587 | }; |
1597 | 1588 | ||
1598 | struct platform_device s3c64xx_device_spi2 = { | 1589 | struct platform_device s3c64xx_device_spi2 = { |
1599 | .name = "s3c64xx-spi", | 1590 | .name = "s3c6410-spi", |
1600 | .id = 2, | 1591 | .id = 2, |
1601 | .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), | 1592 | .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource), |
1602 | .resource = s3c64xx_spi2_resource, | 1593 | .resource = s3c64xx_spi2_resource, |
@@ -1606,13 +1597,10 @@ struct platform_device s3c64xx_device_spi2 = { | |||
1606 | }, | 1597 | }, |
1607 | }; | 1598 | }; |
1608 | 1599 | ||
1609 | void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, | 1600 | void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
1610 | int src_clk_nr, int num_cs) | 1601 | int num_cs) |
1611 | { | 1602 | { |
1612 | if (!pd) { | 1603 | struct s3c64xx_spi_info pd; |
1613 | pr_err("%s:Need to pass platform data\n", __func__); | ||
1614 | return; | ||
1615 | } | ||
1616 | 1604 | ||
1617 | /* Reject invalid configuration */ | 1605 | /* Reject invalid configuration */ |
1618 | if (!num_cs || src_clk_nr < 0) { | 1606 | if (!num_cs || src_clk_nr < 0) { |
@@ -1620,11 +1608,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, | |||
1620 | return; | 1608 | return; |
1621 | } | 1609 | } |
1622 | 1610 | ||
1623 | pd->num_cs = num_cs; | 1611 | pd.num_cs = num_cs; |
1624 | pd->src_clk_nr = src_clk_nr; | 1612 | pd.src_clk_nr = src_clk_nr; |
1625 | if (!pd->cfg_gpio) | 1613 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; |
1626 | pd->cfg_gpio = s3c64xx_spi2_cfg_gpio; | ||
1627 | 1614 | ||
1628 | s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2); | 1615 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); |
1629 | } | 1616 | } |
1630 | #endif /* CONFIG_S3C64XX_DEV_SPI2 */ | 1617 | #endif /* CONFIG_S3C64XX_DEV_SPI2 */ |
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index eb9f4f534006..c38d75489240 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c | |||
@@ -19,72 +19,79 @@ | |||
19 | #include <mach/dma.h> | 19 | #include <mach/dma.h> |
20 | 20 | ||
21 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | 21 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, |
22 | struct samsung_dma_info *info) | 22 | struct samsung_dma_req *param) |
23 | { | 23 | { |
24 | struct dma_chan *chan; | ||
25 | dma_cap_mask_t mask; | 24 | dma_cap_mask_t mask; |
26 | struct dma_slave_config slave_config; | ||
27 | void *filter_param; | 25 | void *filter_param; |
28 | 26 | ||
29 | dma_cap_zero(mask); | 27 | dma_cap_zero(mask); |
30 | dma_cap_set(info->cap, mask); | 28 | dma_cap_set(param->cap, mask); |
31 | 29 | ||
32 | /* | 30 | /* |
33 | * If a dma channel property of a device node from device tree is | 31 | * If a dma channel property of a device node from device tree is |
34 | * specified, use that as the fliter parameter. | 32 | * specified, use that as the fliter parameter. |
35 | */ | 33 | */ |
36 | filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop : | 34 | filter_param = (dma_ch == DMACH_DT_PROP) ? |
37 | (void *)dma_ch; | 35 | (void *)param->dt_dmach_prop : (void *)dma_ch; |
38 | chan = dma_request_channel(mask, pl330_filter, filter_param); | 36 | return (unsigned)dma_request_channel(mask, pl330_filter, filter_param); |
37 | } | ||
38 | |||
39 | static int samsung_dmadev_release(unsigned ch, void *param) | ||
40 | { | ||
41 | dma_release_channel((struct dma_chan *)ch); | ||
39 | 42 | ||
40 | if (info->direction == DMA_DEV_TO_MEM) { | 43 | return 0; |
44 | } | ||
45 | |||
46 | static int samsung_dmadev_config(unsigned ch, | ||
47 | struct samsung_dma_config *param) | ||
48 | { | ||
49 | struct dma_chan *chan = (struct dma_chan *)ch; | ||
50 | struct dma_slave_config slave_config; | ||
51 | |||
52 | if (param->direction == DMA_DEV_TO_MEM) { | ||
41 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); | 53 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); |
42 | slave_config.direction = info->direction; | 54 | slave_config.direction = param->direction; |
43 | slave_config.src_addr = info->fifo; | 55 | slave_config.src_addr = param->fifo; |
44 | slave_config.src_addr_width = info->width; | 56 | slave_config.src_addr_width = param->width; |
45 | slave_config.src_maxburst = 1; | 57 | slave_config.src_maxburst = 1; |
46 | dmaengine_slave_config(chan, &slave_config); | 58 | dmaengine_slave_config(chan, &slave_config); |
47 | } else if (info->direction == DMA_MEM_TO_DEV) { | 59 | } else if (param->direction == DMA_MEM_TO_DEV) { |
48 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); | 60 | memset(&slave_config, 0, sizeof(struct dma_slave_config)); |
49 | slave_config.direction = info->direction; | 61 | slave_config.direction = param->direction; |
50 | slave_config.dst_addr = info->fifo; | 62 | slave_config.dst_addr = param->fifo; |
51 | slave_config.dst_addr_width = info->width; | 63 | slave_config.dst_addr_width = param->width; |
52 | slave_config.dst_maxburst = 1; | 64 | slave_config.dst_maxburst = 1; |
53 | dmaengine_slave_config(chan, &slave_config); | 65 | dmaengine_slave_config(chan, &slave_config); |
66 | } else { | ||
67 | pr_warn("unsupported direction\n"); | ||
68 | return -EINVAL; | ||
54 | } | 69 | } |
55 | 70 | ||
56 | return (unsigned)chan; | ||
57 | } | ||
58 | |||
59 | static int samsung_dmadev_release(unsigned ch, | ||
60 | struct s3c2410_dma_client *client) | ||
61 | { | ||
62 | dma_release_channel((struct dma_chan *)ch); | ||
63 | |||
64 | return 0; | 71 | return 0; |
65 | } | 72 | } |
66 | 73 | ||
67 | static int samsung_dmadev_prepare(unsigned ch, | 74 | static int samsung_dmadev_prepare(unsigned ch, |
68 | struct samsung_dma_prep_info *info) | 75 | struct samsung_dma_prep *param) |
69 | { | 76 | { |
70 | struct scatterlist sg; | 77 | struct scatterlist sg; |
71 | struct dma_chan *chan = (struct dma_chan *)ch; | 78 | struct dma_chan *chan = (struct dma_chan *)ch; |
72 | struct dma_async_tx_descriptor *desc; | 79 | struct dma_async_tx_descriptor *desc; |
73 | 80 | ||
74 | switch (info->cap) { | 81 | switch (param->cap) { |
75 | case DMA_SLAVE: | 82 | case DMA_SLAVE: |
76 | sg_init_table(&sg, 1); | 83 | sg_init_table(&sg, 1); |
77 | sg_dma_len(&sg) = info->len; | 84 | sg_dma_len(&sg) = param->len; |
78 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(info->buf)), | 85 | sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)), |
79 | info->len, offset_in_page(info->buf)); | 86 | param->len, offset_in_page(param->buf)); |
80 | sg_dma_address(&sg) = info->buf; | 87 | sg_dma_address(&sg) = param->buf; |
81 | 88 | ||
82 | desc = dmaengine_prep_slave_sg(chan, | 89 | desc = dmaengine_prep_slave_sg(chan, |
83 | &sg, 1, info->direction, DMA_PREP_INTERRUPT); | 90 | &sg, 1, param->direction, DMA_PREP_INTERRUPT); |
84 | break; | 91 | break; |
85 | case DMA_CYCLIC: | 92 | case DMA_CYCLIC: |
86 | desc = dmaengine_prep_dma_cyclic(chan, | 93 | desc = dmaengine_prep_dma_cyclic(chan, param->buf, |
87 | info->buf, info->len, info->period, info->direction); | 94 | param->len, param->period, param->direction); |
88 | break; | 95 | break; |
89 | default: | 96 | default: |
90 | dev_err(&chan->dev->device, "unsupported format\n"); | 97 | dev_err(&chan->dev->device, "unsupported format\n"); |
@@ -96,8 +103,8 @@ static int samsung_dmadev_prepare(unsigned ch, | |||
96 | return -EFAULT; | 103 | return -EFAULT; |
97 | } | 104 | } |
98 | 105 | ||
99 | desc->callback = info->fp; | 106 | desc->callback = param->fp; |
100 | desc->callback_param = info->fp_param; | 107 | desc->callback_param = param->fp_param; |
101 | 108 | ||
102 | dmaengine_submit((struct dma_async_tx_descriptor *)desc); | 109 | dmaengine_submit((struct dma_async_tx_descriptor *)desc); |
103 | 110 | ||
@@ -119,6 +126,7 @@ static inline int samsung_dmadev_flush(unsigned ch) | |||
119 | static struct samsung_dma_ops dmadev_ops = { | 126 | static struct samsung_dma_ops dmadev_ops = { |
120 | .request = samsung_dmadev_request, | 127 | .request = samsung_dmadev_request, |
121 | .release = samsung_dmadev_release, | 128 | .release = samsung_dmadev_release, |
129 | .config = samsung_dmadev_config, | ||
122 | .prepare = samsung_dmadev_prepare, | 130 | .prepare = samsung_dmadev_prepare, |
123 | .trigger = samsung_dmadev_trigger, | 131 | .trigger = samsung_dmadev_trigger, |
124 | .started = NULL, | 132 | .started = NULL, |
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 0721293fad63..ace4451b7651 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) | |||
132 | 132 | ||
133 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } | 133 | #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } |
134 | 134 | ||
135 | #ifndef KHZ | ||
136 | #define KHZ (1000) | ||
137 | #endif | ||
138 | |||
135 | #ifndef MHZ | 139 | #ifndef MHZ |
136 | #define MHZ (1000*1000) | 140 | #define MHZ (1000*1000) |
137 | #endif | 141 | #endif |
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index 61ca2f356c52..5da4b4f38f40 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -131,7 +131,6 @@ extern struct platform_device exynos4_device_ohci; | |||
131 | extern struct platform_device exynos4_device_pcm0; | 131 | extern struct platform_device exynos4_device_pcm0; |
132 | extern struct platform_device exynos4_device_pcm1; | 132 | extern struct platform_device exynos4_device_pcm1; |
133 | extern struct platform_device exynos4_device_pcm2; | 133 | extern struct platform_device exynos4_device_pcm2; |
134 | extern struct platform_device exynos4_device_pd[]; | ||
135 | extern struct platform_device exynos4_device_spdif; | 134 | extern struct platform_device exynos4_device_spdif; |
136 | 135 | ||
137 | extern struct platform_device exynos_device_drm; | 136 | extern struct platform_device exynos_device_drm; |
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h index 71a6827c7706..f5144cdd3001 100644 --- a/arch/arm/plat-samsung/include/plat/dma-ops.h +++ b/arch/arm/plat-samsung/include/plat/dma-ops.h | |||
@@ -16,7 +16,13 @@ | |||
16 | #include <linux/dmaengine.h> | 16 | #include <linux/dmaengine.h> |
17 | #include <mach/dma.h> | 17 | #include <mach/dma.h> |
18 | 18 | ||
19 | struct samsung_dma_prep_info { | 19 | struct samsung_dma_req { |
20 | enum dma_transaction_type cap; | ||
21 | struct property *dt_dmach_prop; | ||
22 | struct s3c2410_dma_client *client; | ||
23 | }; | ||
24 | |||
25 | struct samsung_dma_prep { | ||
20 | enum dma_transaction_type cap; | 26 | enum dma_transaction_type cap; |
21 | enum dma_transfer_direction direction; | 27 | enum dma_transfer_direction direction; |
22 | dma_addr_t buf; | 28 | dma_addr_t buf; |
@@ -26,19 +32,17 @@ struct samsung_dma_prep_info { | |||
26 | void *fp_param; | 32 | void *fp_param; |
27 | }; | 33 | }; |
28 | 34 | ||
29 | struct samsung_dma_info { | 35 | struct samsung_dma_config { |
30 | enum dma_transaction_type cap; | ||
31 | enum dma_transfer_direction direction; | 36 | enum dma_transfer_direction direction; |
32 | enum dma_slave_buswidth width; | 37 | enum dma_slave_buswidth width; |
33 | dma_addr_t fifo; | 38 | dma_addr_t fifo; |
34 | struct s3c2410_dma_client *client; | ||
35 | struct property *dt_dmach_prop; | ||
36 | }; | 39 | }; |
37 | 40 | ||
38 | struct samsung_dma_ops { | 41 | struct samsung_dma_ops { |
39 | unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info); | 42 | unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param); |
40 | int (*release)(unsigned ch, struct s3c2410_dma_client *client); | 43 | int (*release)(unsigned ch, void *param); |
41 | int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info); | 44 | int (*config)(unsigned ch, struct samsung_dma_config *param); |
45 | int (*prepare)(unsigned ch, struct samsung_dma_prep *param); | ||
42 | int (*trigger)(unsigned ch); | 46 | int (*trigger)(unsigned ch); |
43 | int (*started)(unsigned ch); | 47 | int (*started)(unsigned ch); |
44 | int (*flush)(unsigned ch); | 48 | int (*flush)(unsigned ch); |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 536002ff2ab8..b885322717a1 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
@@ -43,7 +43,6 @@ struct s3c_fb_pd_win { | |||
43 | * @setup_gpio: Setup the external GPIO pins to the right state to transfer | 43 | * @setup_gpio: Setup the external GPIO pins to the right state to transfer |
44 | * the data from the display system to the connected display | 44 | * the data from the display system to the connected display |
45 | * device. | 45 | * device. |
46 | * @default_win: default window layer number to be used for UI layer. | ||
47 | * @vidcon0: The base vidcon0 values to control the panel data format. | 46 | * @vidcon0: The base vidcon0 values to control the panel data format. |
48 | * @vidcon1: The base vidcon1 values to control the panel data output. | 47 | * @vidcon1: The base vidcon1 values to control the panel data output. |
49 | * @vtiming: Video timing when connected to a RGB type panel. | 48 | * @vtiming: Video timing when connected to a RGB type panel. |
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h deleted file mode 100644 index abb4bc32716a..000000000000 --- a/arch/arm/plat-samsung/include/plat/pd.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/include/plat/pd.h | ||
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_SAMSUNG_PD_H | ||
12 | #define __ASM_PLAT_SAMSUNG_PD_H __FILE__ | ||
13 | |||
14 | struct samsung_pd_info { | ||
15 | int (*enable)(struct device *dev); | ||
16 | int (*disable)(struct device *dev); | ||
17 | void __iomem *base; | ||
18 | }; | ||
19 | |||
20 | enum exynos4_pd_block { | ||
21 | PD_MFC, | ||
22 | PD_G3D, | ||
23 | PD_LCD0, | ||
24 | PD_LCD1, | ||
25 | PD_TV, | ||
26 | PD_CAM, | ||
27 | PD_GPS | ||
28 | }; | ||
29 | |||
30 | #endif /* __ASM_PLAT_SAMSUNG_PD_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index fa95e9a00972..ceba18d23a5a 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
@@ -18,7 +18,6 @@ struct platform_device; | |||
18 | * @fb_delay: Slave specific feedback delay. | 18 | * @fb_delay: Slave specific feedback delay. |
19 | * Refer to FB_CLK_SEL register definition in SPI chapter. | 19 | * Refer to FB_CLK_SEL register definition in SPI chapter. |
20 | * @line: Custom 'identity' of the CS line. | 20 | * @line: Custom 'identity' of the CS line. |
21 | * @set_level: CS line control. | ||
22 | * | 21 | * |
23 | * This is per SPI-Slave Chipselect information. | 22 | * This is per SPI-Slave Chipselect information. |
24 | * Allocate and initialize one in machine init code and make the | 23 | * Allocate and initialize one in machine init code and make the |
@@ -27,57 +26,41 @@ struct platform_device; | |||
27 | struct s3c64xx_spi_csinfo { | 26 | struct s3c64xx_spi_csinfo { |
28 | u8 fb_delay; | 27 | u8 fb_delay; |
29 | unsigned line; | 28 | unsigned line; |
30 | void (*set_level)(unsigned line_id, int lvl); | ||
31 | }; | 29 | }; |
32 | 30 | ||
33 | /** | 31 | /** |
34 | * struct s3c64xx_spi_info - SPI Controller defining structure | 32 | * struct s3c64xx_spi_info - SPI Controller defining structure |
35 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. | 33 | * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field. |
36 | * @clk_from_cmu: If the SPI clock/prescalar control block is present | ||
37 | * by the platform's clock-management-unit and not in SPI controller. | ||
38 | * @num_cs: Number of CS this controller emulates. | 34 | * @num_cs: Number of CS this controller emulates. |
39 | * @cfg_gpio: Configure pins for this SPI controller. | 35 | * @cfg_gpio: Configure pins for this SPI controller. |
40 | * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6 | ||
41 | * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number | ||
42 | * @high_speed: If the controller supports HIGH_SPEED_EN bit | ||
43 | * @tx_st_done: Depends on tx fifo_lvl field | ||
44 | */ | 36 | */ |
45 | struct s3c64xx_spi_info { | 37 | struct s3c64xx_spi_info { |
46 | int src_clk_nr; | 38 | int src_clk_nr; |
47 | bool clk_from_cmu; | ||
48 | |||
49 | int num_cs; | 39 | int num_cs; |
50 | 40 | int (*cfg_gpio)(void); | |
51 | int (*cfg_gpio)(struct platform_device *pdev); | ||
52 | |||
53 | /* Following two fields are for future compatibility */ | ||
54 | int fifo_lvl_mask; | ||
55 | int rx_lvl_offset; | ||
56 | int high_speed; | ||
57 | int tx_st_done; | ||
58 | }; | 41 | }; |
59 | 42 | ||
60 | /** | 43 | /** |
61 | * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board | 44 | * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board |
62 | * initialization code. | 45 | * initialization code. |
63 | * @pd: SPI platform data to set. | 46 | * @cfg_gpio: Pointer to gpio setup function. |
64 | * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. | 47 | * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks. |
65 | * @num_cs: Number of elements in the 'cs' array. | 48 | * @num_cs: Number of elements in the 'cs' array. |
66 | * | 49 | * |
67 | * Call this from machine init code for each SPI Controller that | 50 | * Call this from machine init code for each SPI Controller that |
68 | * has some chips attached to it. | 51 | * has some chips attached to it. |
69 | */ | 52 | */ |
70 | extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd, | 53 | extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
71 | int src_clk_nr, int num_cs); | 54 | int num_cs); |
72 | extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd, | 55 | extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
73 | int src_clk_nr, int num_cs); | 56 | int num_cs); |
74 | extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd, | 57 | extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, |
75 | int src_clk_nr, int num_cs); | 58 | int num_cs); |
76 | 59 | ||
77 | /* defined by architecture to configure gpio */ | 60 | /* defined by architecture to configure gpio */ |
78 | extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev); | 61 | extern int s3c64xx_spi0_cfg_gpio(void); |
79 | extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev); | 62 | extern int s3c64xx_spi1_cfg_gpio(void); |
80 | extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev); | 63 | extern int s3c64xx_spi2_cfg_gpio(void); |
81 | 64 | ||
82 | extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; | 65 | extern struct s3c64xx_spi_info s3c64xx_spi0_pdata; |
83 | extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; | 66 | extern struct s3c64xx_spi_info s3c64xx_spi1_pdata; |
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c deleted file mode 100644 index 312b510d86b7..000000000000 --- a/arch/arm/plat-samsung/pd.c +++ /dev/null | |||
@@ -1,95 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-samsung/pd.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Samsung Power domain support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/export.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/err.h> | ||
17 | #include <linux/pm_runtime.h> | ||
18 | |||
19 | #include <plat/pd.h> | ||
20 | |||
21 | static int samsung_pd_probe(struct platform_device *pdev) | ||
22 | { | ||
23 | struct samsung_pd_info *pdata = pdev->dev.platform_data; | ||
24 | struct device *dev = &pdev->dev; | ||
25 | |||
26 | if (!pdata) { | ||
27 | dev_err(dev, "no device data specified\n"); | ||
28 | return -ENOENT; | ||
29 | } | ||
30 | |||
31 | pm_runtime_set_active(dev); | ||
32 | pm_runtime_enable(dev); | ||
33 | |||
34 | dev_info(dev, "power domain registered\n"); | ||
35 | return 0; | ||
36 | } | ||
37 | |||
38 | static int __devexit samsung_pd_remove(struct platform_device *pdev) | ||
39 | { | ||
40 | struct device *dev = &pdev->dev; | ||
41 | |||
42 | pm_runtime_disable(dev); | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | static int samsung_pd_runtime_suspend(struct device *dev) | ||
47 | { | ||
48 | struct samsung_pd_info *pdata = dev->platform_data; | ||
49 | int ret = 0; | ||
50 | |||
51 | if (pdata->disable) | ||
52 | ret = pdata->disable(dev); | ||
53 | |||
54 | dev_dbg(dev, "suspended\n"); | ||
55 | return ret; | ||
56 | } | ||
57 | |||
58 | static int samsung_pd_runtime_resume(struct device *dev) | ||
59 | { | ||
60 | struct samsung_pd_info *pdata = dev->platform_data; | ||
61 | int ret = 0; | ||
62 | |||
63 | if (pdata->enable) | ||
64 | ret = pdata->enable(dev); | ||
65 | |||
66 | dev_dbg(dev, "resumed\n"); | ||
67 | return ret; | ||
68 | } | ||
69 | |||
70 | static const struct dev_pm_ops samsung_pd_pm_ops = { | ||
71 | .runtime_suspend = samsung_pd_runtime_suspend, | ||
72 | .runtime_resume = samsung_pd_runtime_resume, | ||
73 | }; | ||
74 | |||
75 | static struct platform_driver samsung_pd_driver = { | ||
76 | .driver = { | ||
77 | .name = "samsung-pd", | ||
78 | .owner = THIS_MODULE, | ||
79 | .pm = &samsung_pd_pm_ops, | ||
80 | }, | ||
81 | .probe = samsung_pd_probe, | ||
82 | .remove = __devexit_p(samsung_pd_remove), | ||
83 | }; | ||
84 | |||
85 | static int __init samsung_pd_init(void) | ||
86 | { | ||
87 | int ret; | ||
88 | |||
89 | ret = platform_driver_register(&samsung_pd_driver); | ||
90 | if (ret) | ||
91 | printk(KERN_ERR "%s: failed to add PD driver\n", __func__); | ||
92 | |||
93 | return ret; | ||
94 | } | ||
95 | arch_initcall(samsung_pd_init); | ||
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c index c559d8438c70..d3583050fb05 100644 --- a/arch/arm/plat-samsung/pwm.c +++ b/arch/arm/plat-samsung/pwm.c | |||
@@ -36,7 +36,6 @@ struct pwm_device { | |||
36 | unsigned int duty_ns; | 36 | unsigned int duty_ns; |
37 | 37 | ||
38 | unsigned char tcon_base; | 38 | unsigned char tcon_base; |
39 | unsigned char running; | ||
40 | unsigned char use_count; | 39 | unsigned char use_count; |
41 | unsigned char pwm_id; | 40 | unsigned char pwm_id; |
42 | }; | 41 | }; |
@@ -116,7 +115,6 @@ int pwm_enable(struct pwm_device *pwm) | |||
116 | 115 | ||
117 | local_irq_restore(flags); | 116 | local_irq_restore(flags); |
118 | 117 | ||
119 | pwm->running = 1; | ||
120 | return 0; | 118 | return 0; |
121 | } | 119 | } |
122 | 120 | ||
@@ -134,8 +132,6 @@ void pwm_disable(struct pwm_device *pwm) | |||
134 | __raw_writel(tcon, S3C2410_TCON); | 132 | __raw_writel(tcon, S3C2410_TCON); |
135 | 133 | ||
136 | local_irq_restore(flags); | 134 | local_irq_restore(flags); |
137 | |||
138 | pwm->running = 0; | ||
139 | } | 135 | } |
140 | 136 | ||
141 | EXPORT_SYMBOL(pwm_disable); | 137 | EXPORT_SYMBOL(pwm_disable); |
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c index 781494912827..f99448c48d30 100644 --- a/arch/arm/plat-samsung/s3c-dma-ops.c +++ b/arch/arm/plat-samsung/s3c-dma-ops.c | |||
@@ -36,30 +36,26 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param, | |||
36 | } | 36 | } |
37 | 37 | ||
38 | static unsigned s3c_dma_request(enum dma_ch dma_ch, | 38 | static unsigned s3c_dma_request(enum dma_ch dma_ch, |
39 | struct samsung_dma_info *info) | 39 | struct samsung_dma_req *param) |
40 | { | 40 | { |
41 | struct cb_data *data; | 41 | struct cb_data *data; |
42 | 42 | ||
43 | if (s3c2410_dma_request(dma_ch, info->client, NULL) < 0) { | 43 | if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) { |
44 | s3c2410_dma_free(dma_ch, info->client); | 44 | s3c2410_dma_free(dma_ch, param->client); |
45 | return 0; | 45 | return 0; |
46 | } | 46 | } |
47 | 47 | ||
48 | if (param->cap == DMA_CYCLIC) | ||
49 | s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR); | ||
50 | |||
48 | data = kzalloc(sizeof(struct cb_data), GFP_KERNEL); | 51 | data = kzalloc(sizeof(struct cb_data), GFP_KERNEL); |
49 | data->ch = dma_ch; | 52 | data->ch = dma_ch; |
50 | list_add_tail(&data->node, &dma_list); | 53 | list_add_tail(&data->node, &dma_list); |
51 | 54 | ||
52 | s3c2410_dma_devconfig(dma_ch, info->direction, info->fifo); | ||
53 | |||
54 | if (info->cap == DMA_CYCLIC) | ||
55 | s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR); | ||
56 | |||
57 | s3c2410_dma_config(dma_ch, info->width); | ||
58 | |||
59 | return (unsigned)dma_ch; | 55 | return (unsigned)dma_ch; |
60 | } | 56 | } |
61 | 57 | ||
62 | static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client) | 58 | static int s3c_dma_release(unsigned ch, void *param) |
63 | { | 59 | { |
64 | struct cb_data *data; | 60 | struct cb_data *data; |
65 | 61 | ||
@@ -68,16 +64,24 @@ static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client) | |||
68 | break; | 64 | break; |
69 | list_del(&data->node); | 65 | list_del(&data->node); |
70 | 66 | ||
71 | s3c2410_dma_free(ch, client); | 67 | s3c2410_dma_free(ch, param); |
72 | kfree(data); | 68 | kfree(data); |
73 | 69 | ||
74 | return 0; | 70 | return 0; |
75 | } | 71 | } |
76 | 72 | ||
77 | static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info) | 73 | static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param) |
74 | { | ||
75 | s3c2410_dma_devconfig(ch, param->direction, param->fifo); | ||
76 | s3c2410_dma_config(ch, param->width); | ||
77 | |||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param) | ||
78 | { | 82 | { |
79 | struct cb_data *data; | 83 | struct cb_data *data; |
80 | int len = (info->cap == DMA_CYCLIC) ? info->period : info->len; | 84 | int len = (param->cap == DMA_CYCLIC) ? param->period : param->len; |
81 | 85 | ||
82 | list_for_each_entry(data, &dma_list, node) | 86 | list_for_each_entry(data, &dma_list, node) |
83 | if (data->ch == ch) | 87 | if (data->ch == ch) |
@@ -85,11 +89,11 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info) | |||
85 | 89 | ||
86 | if (!data->fp) { | 90 | if (!data->fp) { |
87 | s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb); | 91 | s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb); |
88 | data->fp = info->fp; | 92 | data->fp = param->fp; |
89 | data->fp_param = info->fp_param; | 93 | data->fp_param = param->fp_param; |
90 | } | 94 | } |
91 | 95 | ||
92 | s3c2410_dma_enqueue(ch, (void *)data, info->buf, len); | 96 | s3c2410_dma_enqueue(ch, (void *)data, param->buf, len); |
93 | 97 | ||
94 | return 0; | 98 | return 0; |
95 | } | 99 | } |
@@ -117,6 +121,7 @@ static inline int s3c_dma_stop(unsigned ch) | |||
117 | static struct samsung_dma_ops s3c_dma_ops = { | 121 | static struct samsung_dma_ops s3c_dma_ops = { |
118 | .request = s3c_dma_request, | 122 | .request = s3c_dma_request, |
119 | .release = s3c_dma_release, | 123 | .release = s3c_dma_release, |
124 | .config = s3c_dma_config, | ||
120 | .prepare = s3c_dma_prepare, | 125 | .prepare = s3c_dma_prepare, |
121 | .trigger = s3c_dma_trigger, | 126 | .trigger = s3c_dma_trigger, |
122 | .started = s3c_dma_started, | 127 | .started = s3c_dma_started, |
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c index 031a61899bef..48a159911037 100644 --- a/arch/arm/plat-samsung/s5p-clock.c +++ b/arch/arm/plat-samsung/s5p-clock.c | |||
@@ -37,6 +37,7 @@ struct clk clk_ext_xtal_mux = { | |||
37 | struct clk clk_xusbxti = { | 37 | struct clk clk_xusbxti = { |
38 | .name = "xusbxti", | 38 | .name = "xusbxti", |
39 | .id = -1, | 39 | .id = -1, |
40 | .rate = 24000000, | ||
40 | }; | 41 | }; |
41 | 42 | ||
42 | struct clk s5p_clk_27m = { | 43 | struct clk s5p_clk_27m = { |
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index 81ee7cc34457..8d5c10a5084d 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig | |||
@@ -1,5 +1,8 @@ | |||
1 | if PLAT_VERSATILE | 1 | if PLAT_VERSATILE |
2 | 2 | ||
3 | config PLAT_VERSATILE_CLOCK | ||
4 | bool | ||
5 | |||
3 | config PLAT_VERSATILE_CLCD | 6 | config PLAT_VERSATILE_CLCD |
4 | bool | 7 | bool |
5 | 8 | ||
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index a5cb1945bdcc..272769a8a7d6 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile | |||
@@ -1,4 +1,4 @@ | |||
1 | obj-y := clock.o | 1 | obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o |
2 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o | 2 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o |
3 | obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o | 3 | obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o |
4 | obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o | 4 | obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o |
diff --git a/arch/h8300/include/asm/pgtable.h b/arch/h8300/include/asm/pgtable.h index a09230a08e02..62ef17676b40 100644 --- a/arch/h8300/include/asm/pgtable.h +++ b/arch/h8300/include/asm/pgtable.h | |||
@@ -70,4 +70,7 @@ extern int is_in_rom(unsigned long); | |||
70 | #define VMALLOC_END 0xffffffff | 70 | #define VMALLOC_END 0xffffffff |
71 | 71 | ||
72 | #define arch_enter_lazy_cpu_mode() do {} while (0) | 72 | #define arch_enter_lazy_cpu_mode() do {} while (0) |
73 | |||
74 | #include <asm-generic/pgtable.h> | ||
75 | |||
73 | #endif /* _H8300_PGTABLE_H */ | 76 | #endif /* _H8300_PGTABLE_H */ |
diff --git a/arch/h8300/include/asm/uaccess.h b/arch/h8300/include/asm/uaccess.h index 356068cd0879..8725d1ad4272 100644 --- a/arch/h8300/include/asm/uaccess.h +++ b/arch/h8300/include/asm/uaccess.h | |||
@@ -100,7 +100,6 @@ extern int __put_user_bad(void); | |||
100 | break; \ | 100 | break; \ |
101 | default: \ | 101 | default: \ |
102 | __gu_err = __get_user_bad(); \ | 102 | __gu_err = __get_user_bad(); \ |
103 | __gu_val = 0; \ | ||
104 | break; \ | 103 | break; \ |
105 | } \ | 104 | } \ |
106 | (x) = __gu_val; \ | 105 | (x) = __gu_val; \ |
@@ -159,4 +158,6 @@ clear_user(void *to, unsigned long n) | |||
159 | return 0; | 158 | return 0; |
160 | } | 159 | } |
161 | 160 | ||
161 | #define __clear_user clear_user | ||
162 | |||
162 | #endif /* _H8300_UACCESS_H */ | 163 | #endif /* _H8300_UACCESS_H */ |
diff --git a/arch/h8300/kernel/signal.c b/arch/h8300/kernel/signal.c index fca10378701b..5adaadaf9218 100644 --- a/arch/h8300/kernel/signal.c +++ b/arch/h8300/kernel/signal.c | |||
@@ -447,7 +447,7 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, | |||
447 | * want to handle. Thus you cannot kill init even with a SIGKILL even by | 447 | * want to handle. Thus you cannot kill init even with a SIGKILL even by |
448 | * mistake. | 448 | * mistake. |
449 | */ | 449 | */ |
450 | statis void do_signal(struct pt_regs *regs) | 450 | static void do_signal(struct pt_regs *regs) |
451 | { | 451 | { |
452 | siginfo_t info; | 452 | siginfo_t info; |
453 | int signr; | 453 | int signr; |
diff --git a/arch/h8300/kernel/time.c b/arch/h8300/kernel/time.c index 32263a138aa6..e0f74191d553 100644 --- a/arch/h8300/kernel/time.c +++ b/arch/h8300/kernel/time.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include <linux/profile.h> | 27 | #include <linux/profile.h> |
28 | 28 | ||
29 | #include <asm/io.h> | 29 | #include <asm/io.h> |
30 | #include <asm/irq_regs.h> | ||
30 | #include <asm/timer.h> | 31 | #include <asm/timer.h> |
31 | 32 | ||
32 | #define TICK_SIZE (tick_nsec / 1000) | 33 | #define TICK_SIZE (tick_nsec / 1000) |
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c index f7264621e58d..149fbefc1a4d 100644 --- a/arch/hexagon/kernel/smp.c +++ b/arch/hexagon/kernel/smp.c | |||
@@ -180,9 +180,7 @@ void __cpuinit start_secondary(void) | |||
180 | 180 | ||
181 | notify_cpu_starting(cpu); | 181 | notify_cpu_starting(cpu); |
182 | 182 | ||
183 | ipi_call_lock(); | ||
184 | set_cpu_online(cpu, true); | 183 | set_cpu_online(cpu, true); |
185 | ipi_call_unlock(); | ||
186 | 184 | ||
187 | local_irq_enable(); | 185 | local_irq_enable(); |
188 | 186 | ||
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c index 1113b8aba07f..963d2db53bfa 100644 --- a/arch/ia64/kernel/smpboot.c +++ b/arch/ia64/kernel/smpboot.c | |||
@@ -382,7 +382,6 @@ smp_callin (void) | |||
382 | set_numa_node(cpu_to_node_map[cpuid]); | 382 | set_numa_node(cpu_to_node_map[cpuid]); |
383 | set_numa_mem(local_memory_node(cpu_to_node_map[cpuid])); | 383 | set_numa_mem(local_memory_node(cpu_to_node_map[cpuid])); |
384 | 384 | ||
385 | ipi_call_lock_irq(); | ||
386 | spin_lock(&vector_lock); | 385 | spin_lock(&vector_lock); |
387 | /* Setup the per cpu irq handling data structures */ | 386 | /* Setup the per cpu irq handling data structures */ |
388 | __setup_vector_irq(cpuid); | 387 | __setup_vector_irq(cpuid); |
@@ -390,7 +389,6 @@ smp_callin (void) | |||
390 | set_cpu_online(cpuid, true); | 389 | set_cpu_online(cpuid, true); |
391 | per_cpu(cpu_state, cpuid) = CPU_ONLINE; | 390 | per_cpu(cpu_state, cpuid) = CPU_ONLINE; |
392 | spin_unlock(&vector_lock); | 391 | spin_unlock(&vector_lock); |
393 | ipi_call_unlock_irq(); | ||
394 | 392 | ||
395 | smp_setup_percpu_timer(); | 393 | smp_setup_percpu_timer(); |
396 | 394 | ||
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile index 177716b1d613..01729c2979ba 100644 --- a/arch/m32r/boot/compressed/Makefile +++ b/arch/m32r/boot/compressed/Makefile | |||
@@ -43,9 +43,9 @@ endif | |||
43 | 43 | ||
44 | OBJCOPYFLAGS += -R .empty_zero_page | 44 | OBJCOPYFLAGS += -R .empty_zero_page |
45 | 45 | ||
46 | suffix_$(CONFIG_KERNEL_GZIP) = gz | 46 | suffix-$(CONFIG_KERNEL_GZIP) = gz |
47 | suffix_$(CONFIG_KERNEL_BZIP2) = bz2 | 47 | suffix-$(CONFIG_KERNEL_BZIP2) = bz2 |
48 | suffix_$(CONFIG_KERNEL_LZMA) = lzma | 48 | suffix-$(CONFIG_KERNEL_LZMA) = lzma |
49 | 49 | ||
50 | $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE | 50 | $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE |
51 | $(call if_changed,ld) | 51 | $(call if_changed,ld) |
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c index 370d60881977..28a09529f206 100644 --- a/arch/m32r/boot/compressed/misc.c +++ b/arch/m32r/boot/compressed/misc.c | |||
@@ -28,7 +28,7 @@ static unsigned long free_mem_ptr; | |||
28 | static unsigned long free_mem_end_ptr; | 28 | static unsigned long free_mem_end_ptr; |
29 | 29 | ||
30 | #ifdef CONFIG_KERNEL_BZIP2 | 30 | #ifdef CONFIG_KERNEL_BZIP2 |
31 | static void *memset(void *s, int c, size_t n) | 31 | void *memset(void *s, int c, size_t n) |
32 | { | 32 | { |
33 | char *ss = s; | 33 | char *ss = s; |
34 | 34 | ||
@@ -39,6 +39,16 @@ static void *memset(void *s, int c, size_t n) | |||
39 | #endif | 39 | #endif |
40 | 40 | ||
41 | #ifdef CONFIG_KERNEL_GZIP | 41 | #ifdef CONFIG_KERNEL_GZIP |
42 | void *memcpy(void *dest, const void *src, size_t n) | ||
43 | { | ||
44 | char *d = dest; | ||
45 | const char *s = src; | ||
46 | while (n--) | ||
47 | *d++ = *s++; | ||
48 | |||
49 | return dest; | ||
50 | } | ||
51 | |||
42 | #define BOOT_HEAP_SIZE 0x10000 | 52 | #define BOOT_HEAP_SIZE 0x10000 |
43 | #include "../../../../lib/decompress_inflate.c" | 53 | #include "../../../../lib/decompress_inflate.c" |
44 | #endif | 54 | #endif |
diff --git a/arch/m32r/include/asm/ptrace.h b/arch/m32r/include/asm/ptrace.h index 527527584dd0..4313aa62b51b 100644 --- a/arch/m32r/include/asm/ptrace.h +++ b/arch/m32r/include/asm/ptrace.h | |||
@@ -113,9 +113,6 @@ struct pt_regs { | |||
113 | 113 | ||
114 | #define PTRACE_OLDSETOPTIONS 21 | 114 | #define PTRACE_OLDSETOPTIONS 21 |
115 | 115 | ||
116 | /* options set using PTRACE_SETOPTIONS */ | ||
117 | #define PTRACE_O_TRACESYSGOOD 0x00000001 | ||
118 | |||
119 | #ifdef __KERNEL__ | 116 | #ifdef __KERNEL__ |
120 | 117 | ||
121 | #include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */ | 118 | #include <asm/m32r.h> /* M32R_PSW_BSM, M32R_PSW_BPM */ |
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h index cf7829a61551..c689b828dfe2 100644 --- a/arch/m32r/include/asm/smp.h +++ b/arch/m32r/include/asm/smp.h | |||
@@ -79,11 +79,6 @@ static __inline__ int cpu_number_map(int cpu) | |||
79 | return cpu; | 79 | return cpu; |
80 | } | 80 | } |
81 | 81 | ||
82 | static __inline__ unsigned int num_booting_cpus(void) | ||
83 | { | ||
84 | return cpumask_weight(&cpu_callout_map); | ||
85 | } | ||
86 | |||
87 | extern void smp_send_timer(void); | 82 | extern void smp_send_timer(void); |
88 | extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int); | 83 | extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int); |
89 | 84 | ||
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c index 4c03361537aa..51f5e9aa4901 100644 --- a/arch/m32r/kernel/ptrace.c +++ b/arch/m32r/kernel/ptrace.c | |||
@@ -591,17 +591,16 @@ void user_enable_single_step(struct task_struct *child) | |||
591 | 591 | ||
592 | if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0) | 592 | if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0) |
593 | != sizeof(insn)) | 593 | != sizeof(insn)) |
594 | return -EIO; | 594 | return; |
595 | 595 | ||
596 | compute_next_pc(insn, pc, &next_pc, child); | 596 | compute_next_pc(insn, pc, &next_pc, child); |
597 | if (next_pc & 0x80000000) | 597 | if (next_pc & 0x80000000) |
598 | return -EIO; | 598 | return; |
599 | 599 | ||
600 | if (embed_debug_trap(child, next_pc)) | 600 | if (embed_debug_trap(child, next_pc)) |
601 | return -EIO; | 601 | return; |
602 | 602 | ||
603 | invalidate_cache(); | 603 | invalidate_cache(); |
604 | return 0; | ||
605 | } | 604 | } |
606 | 605 | ||
607 | void user_disable_single_step(struct task_struct *child) | 606 | void user_disable_single_step(struct task_struct *child) |
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c index f3fb2c029cfc..d0f60b97bbc5 100644 --- a/arch/m32r/kernel/signal.c +++ b/arch/m32r/kernel/signal.c | |||
@@ -286,7 +286,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info, | |||
286 | case -ERESTARTNOINTR: | 286 | case -ERESTARTNOINTR: |
287 | regs->r0 = regs->orig_r0; | 287 | regs->r0 = regs->orig_r0; |
288 | if (prev_insn(regs) < 0) | 288 | if (prev_insn(regs) < 0) |
289 | return -EFAULT; | 289 | return; |
290 | } | 290 | } |
291 | } | 291 | } |
292 | 292 | ||
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 09ab87ee6fef..b3e10fdd3898 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
@@ -288,6 +288,7 @@ config MIPS_MALTA | |||
288 | select SYS_HAS_CPU_MIPS32_R1 | 288 | select SYS_HAS_CPU_MIPS32_R1 |
289 | select SYS_HAS_CPU_MIPS32_R2 | 289 | select SYS_HAS_CPU_MIPS32_R2 |
290 | select SYS_HAS_CPU_MIPS64_R1 | 290 | select SYS_HAS_CPU_MIPS64_R1 |
291 | select SYS_HAS_CPU_MIPS64_R2 | ||
291 | select SYS_HAS_CPU_NEVADA | 292 | select SYS_HAS_CPU_NEVADA |
292 | select SYS_HAS_CPU_RM7000 | 293 | select SYS_HAS_CPU_RM7000 |
293 | select SYS_HAS_EARLY_PRINTK | 294 | select SYS_HAS_EARLY_PRINTK |
@@ -1423,6 +1424,7 @@ config CPU_SB1 | |||
1423 | config CPU_CAVIUM_OCTEON | 1424 | config CPU_CAVIUM_OCTEON |
1424 | bool "Cavium Octeon processor" | 1425 | bool "Cavium Octeon processor" |
1425 | depends on SYS_HAS_CPU_CAVIUM_OCTEON | 1426 | depends on SYS_HAS_CPU_CAVIUM_OCTEON |
1427 | select ARCH_SPARSEMEM_ENABLE | ||
1426 | select CPU_HAS_PREFETCH | 1428 | select CPU_HAS_PREFETCH |
1427 | select CPU_SUPPORTS_64BIT_KERNEL | 1429 | select CPU_SUPPORTS_64BIT_KERNEL |
1428 | select SYS_SUPPORTS_SMP | 1430 | select SYS_SUPPORTS_SMP |
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig index 6210b8d84109..b311be45a720 100644 --- a/arch/mips/bcm47xx/Kconfig +++ b/arch/mips/bcm47xx/Kconfig | |||
@@ -21,6 +21,7 @@ config BCM47XX_BCMA | |||
21 | select BCMA | 21 | select BCMA |
22 | select BCMA_HOST_SOC | 22 | select BCMA_HOST_SOC |
23 | select BCMA_DRIVER_MIPS | 23 | select BCMA_DRIVER_MIPS |
24 | select BCMA_HOST_PCI if PCI | ||
24 | select BCMA_DRIVER_PCI_HOSTMODE if PCI | 25 | select BCMA_DRIVER_PCI_HOSTMODE if PCI |
25 | default y | 26 | default y |
26 | help | 27 | help |
diff --git a/arch/mips/bcm63xx/dev-pcmcia.c b/arch/mips/bcm63xx/dev-pcmcia.c index de4d917fd54d..a551bab5ecb9 100644 --- a/arch/mips/bcm63xx/dev-pcmcia.c +++ b/arch/mips/bcm63xx/dev-pcmcia.c | |||
@@ -79,11 +79,11 @@ static int __init config_pcmcia_cs(unsigned int cs, | |||
79 | return ret; | 79 | return ret; |
80 | } | 80 | } |
81 | 81 | ||
82 | static const __initdata struct { | 82 | static const struct { |
83 | unsigned int cs; | 83 | unsigned int cs; |
84 | unsigned int base; | 84 | unsigned int base; |
85 | unsigned int size; | 85 | unsigned int size; |
86 | } pcmcia_cs[3] = { | 86 | } pcmcia_cs[3] __initconst = { |
87 | { | 87 | { |
88 | .cs = MPI_CS_PCMCIA_COMMON, | 88 | .cs = MPI_CS_PCMCIA_COMMON, |
89 | .base = BCM_PCMCIA_COMMON_BASE_PA, | 89 | .base = BCM_PCMCIA_COMMON_BASE_PA, |
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index f9e275a50d98..2f4f6d5e05b6 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig | |||
@@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY | |||
82 | help | 82 | help |
83 | Lock the kernel's implementation of memcpy() into L2. | 83 | Lock the kernel's implementation of memcpy() into L2. |
84 | 84 | ||
85 | config ARCH_SPARSEMEM_ENABLE | ||
86 | def_bool y | ||
87 | select SPARSEMEM_STATIC | ||
88 | |||
89 | config IOMMU_HELPER | 85 | config IOMMU_HELPER |
90 | bool | 86 | bool |
91 | 87 | ||
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 4b93048044eb..ee1fb9f7f517 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c | |||
@@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void) | |||
185 | octeon_init_cvmcount(); | 185 | octeon_init_cvmcount(); |
186 | 186 | ||
187 | octeon_irq_setup_secondary(); | 187 | octeon_irq_setup_secondary(); |
188 | raw_local_irq_enable(); | ||
189 | } | 188 | } |
190 | 189 | ||
191 | /** | 190 | /** |
@@ -233,6 +232,7 @@ static void octeon_smp_finish(void) | |||
233 | 232 | ||
234 | /* to generate the first CPU timer interrupt */ | 233 | /* to generate the first CPU timer interrupt */ |
235 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); | 234 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); |
235 | local_irq_enable(); | ||
236 | } | 236 | } |
237 | 237 | ||
238 | /** | 238 | /** |
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h index 2e1ad4c652b7..82ad35ce2b45 100644 --- a/arch/mips/include/asm/bitops.h +++ b/arch/mips/include/asm/bitops.h | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/irqflags.h> | 17 | #include <linux/irqflags.h> |
18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
19 | #include <asm/barrier.h> | 19 | #include <asm/barrier.h> |
20 | #include <asm/bug.h> | ||
21 | #include <asm/byteorder.h> /* sigh ... */ | 20 | #include <asm/byteorder.h> /* sigh ... */ |
22 | #include <asm/cpu-features.h> | 21 | #include <asm/cpu-features.h> |
23 | #include <asm/sgidefs.h> | 22 | #include <asm/sgidefs.h> |
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h index 285a41fa0b18..eee10dc07ac1 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h | |||
@@ -8,6 +8,7 @@ | |||
8 | #ifndef __ASM_CMPXCHG_H | 8 | #ifndef __ASM_CMPXCHG_H |
9 | #define __ASM_CMPXCHG_H | 9 | #define __ASM_CMPXCHG_H |
10 | 10 | ||
11 | #include <linux/bug.h> | ||
11 | #include <linux/irqflags.h> | 12 | #include <linux/irqflags.h> |
12 | #include <asm/war.h> | 13 | #include <asm/war.h> |
13 | 14 | ||
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index f9fa2a479dd0..95e40c1e8ed1 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h | |||
@@ -94,6 +94,7 @@ | |||
94 | #define PRID_IMP_24KE 0x9600 | 94 | #define PRID_IMP_24KE 0x9600 |
95 | #define PRID_IMP_74K 0x9700 | 95 | #define PRID_IMP_74K 0x9700 |
96 | #define PRID_IMP_1004K 0x9900 | 96 | #define PRID_IMP_1004K 0x9900 |
97 | #define PRID_IMP_M14KC 0x9c00 | ||
97 | 98 | ||
98 | /* | 99 | /* |
99 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE | 100 | * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE |
@@ -260,12 +261,12 @@ enum cpu_type_enum { | |||
260 | */ | 261 | */ |
261 | CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, | 262 | CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, |
262 | CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, | 263 | CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350, |
263 | CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, | 264 | CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC, |
264 | 265 | ||
265 | /* | 266 | /* |
266 | * MIPS64 class processors | 267 | * MIPS64 class processors |
267 | */ | 268 | */ |
268 | CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, | 269 | CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, |
269 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, | 270 | CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2, |
270 | CPU_XLR, CPU_XLP, | 271 | CPU_XLR, CPU_XLP, |
271 | 272 | ||
@@ -288,7 +289,7 @@ enum cpu_type_enum { | |||
288 | #define MIPS_CPU_ISA_M64R2 0x00000100 | 289 | #define MIPS_CPU_ISA_M64R2 0x00000100 |
289 | 290 | ||
290 | #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ | 291 | #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \ |
291 | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 ) | 292 | MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2) |
292 | #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ | 293 | #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \ |
293 | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) | 294 | MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2) |
294 | 295 | ||
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 86548da650e7..991b659e2548 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h | |||
@@ -206,7 +206,7 @@ | |||
206 | 206 | ||
207 | #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 | 207 | #define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 |
208 | #define GIC_VPE_EIC_SS(intr) \ | 208 | #define GIC_VPE_EIC_SS(intr) \ |
209 | (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) | 209 | (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr)) |
210 | 210 | ||
211 | #define GIC_VPE_EIC_VEC_BASE 0x0800 | 211 | #define GIC_VPE_EIC_VEC_BASE 0x0800 |
212 | #define GIC_VPE_EIC_VEC(intr) \ | 212 | #define GIC_VPE_EIC_VEC(intr) \ |
@@ -330,6 +330,17 @@ struct gic_intr_map { | |||
330 | #define GIC_FLAG_TRANSPARENT 0x02 | 330 | #define GIC_FLAG_TRANSPARENT 0x02 |
331 | }; | 331 | }; |
332 | 332 | ||
333 | /* | ||
334 | * This is only used in EIC mode. This helps to figure out which | ||
335 | * shared interrupts we need to process when we get a vector interrupt. | ||
336 | */ | ||
337 | #define GIC_MAX_SHARED_INTR 0x5 | ||
338 | struct gic_shared_intr_map { | ||
339 | unsigned int num_shared_intr; | ||
340 | unsigned int intr_list[GIC_MAX_SHARED_INTR]; | ||
341 | unsigned int local_intr_mask; | ||
342 | }; | ||
343 | |||
333 | extern void gic_init(unsigned long gic_base_addr, | 344 | extern void gic_init(unsigned long gic_base_addr, |
334 | unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, | 345 | unsigned long gic_addrspace_size, struct gic_intr_map *intrmap, |
335 | unsigned int intrmap_size, unsigned int irqbase); | 346 | unsigned int intrmap_size, unsigned int irqbase); |
@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void); | |||
338 | extern void gic_send_ipi(unsigned int intr); | 349 | extern void gic_send_ipi(unsigned int intr); |
339 | extern unsigned int plat_ipi_call_int_xlate(unsigned int); | 350 | extern unsigned int plat_ipi_call_int_xlate(unsigned int); |
340 | extern unsigned int plat_ipi_resched_int_xlate(unsigned int); | 351 | extern unsigned int plat_ipi_resched_int_xlate(unsigned int); |
352 | extern void gic_bind_eic_interrupt(int irq, int set); | ||
353 | extern unsigned int gic_get_timer_pending(void); | ||
341 | 354 | ||
342 | #endif /* _ASM_GICREGS_H */ | 355 | #endif /* _ASM_GICREGS_H */ |
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h index 7ebfc392e58d..ab84064283db 100644 --- a/arch/mips/include/asm/inst.h +++ b/arch/mips/include/asm/inst.h | |||
@@ -251,7 +251,7 @@ struct f_format { /* FPU register format */ | |||
251 | unsigned int func : 6; | 251 | unsigned int func : 6; |
252 | }; | 252 | }; |
253 | 253 | ||
254 | struct ma_format { /* FPU multipy and add format (MIPS IV) */ | 254 | struct ma_format { /* FPU multiply and add format (MIPS IV) */ |
255 | unsigned int opcode : 6; | 255 | unsigned int opcode : 6; |
256 | unsigned int fr : 5; | 256 | unsigned int fr : 5; |
257 | unsigned int ft : 5; | 257 | unsigned int ft : 5; |
@@ -324,7 +324,7 @@ struct f_format { /* FPU register format */ | |||
324 | unsigned int opcode : 6; | 324 | unsigned int opcode : 6; |
325 | }; | 325 | }; |
326 | 326 | ||
327 | struct ma_format { /* FPU multipy and add format (MIPS IV) */ | 327 | struct ma_format { /* FPU multiply and add format (MIPS IV) */ |
328 | unsigned int fmt : 2; | 328 | unsigned int fmt : 2; |
329 | unsigned int func : 4; | 329 | unsigned int func : 4; |
330 | unsigned int fd : 5; | 330 | unsigned int fd : 5; |
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index a58f22998a86..29d9c23c20c7 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/types.h> | 17 | #include <linux/types.h> |
18 | 18 | ||
19 | #include <asm/addrspace.h> | 19 | #include <asm/addrspace.h> |
20 | #include <asm/bug.h> | ||
20 | #include <asm/byteorder.h> | 21 | #include <asm/byteorder.h> |
21 | #include <asm/cpu.h> | 22 | #include <asm/cpu.h> |
22 | #include <asm/cpu-features.h> | 23 | #include <asm/cpu-features.h> |
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index fb698dc09bc9..78dbb8a86da2 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h | |||
@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq); | |||
136 | * IE7. Since R2 their number has to be read from the c0_intctl register. | 136 | * IE7. Since R2 their number has to be read from the c0_intctl register. |
137 | */ | 137 | */ |
138 | #define CP0_LEGACY_COMPARE_IRQ 7 | 138 | #define CP0_LEGACY_COMPARE_IRQ 7 |
139 | #define CP0_LEGACY_PERFCNT_IRQ 7 | ||
139 | 140 | ||
140 | extern int cp0_compare_irq; | 141 | extern int cp0_compare_irq; |
141 | extern int cp0_compare_irq_shift; | 142 | extern int cp0_compare_irq_shift; |
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 94d4faad29a1..fdcd78ca1b03 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | |||
@@ -99,7 +99,7 @@ | |||
99 | #define CKCTL_6368_USBH_CLK_EN (1 << 15) | 99 | #define CKCTL_6368_USBH_CLK_EN (1 << 15) |
100 | #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) | 100 | #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) |
101 | #define CKCTL_6368_NAND_CLK_EN (1 << 17) | 101 | #define CKCTL_6368_NAND_CLK_EN (1 << 17) |
102 | #define CKCTL_6368_IPSEC_CLK_EN (1 << 17) | 102 | #define CKCTL_6368_IPSEC_CLK_EN (1 << 18) |
103 | 103 | ||
104 | #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ | 104 | #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ |
105 | CKCTL_6368_SWPKT_SAR_EN | \ | 105 | CKCTL_6368_SWPKT_SAR_EN | \ |
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h index d11aa02a956a..5447d9fc4219 100644 --- a/arch/mips/include/asm/mips-boards/maltaint.h +++ b/arch/mips/include/asm/mips-boards/maltaint.h | |||
@@ -86,6 +86,16 @@ | |||
86 | #define GIC_CPU_INT4 4 /* . */ | 86 | #define GIC_CPU_INT4 4 /* . */ |
87 | #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ | 87 | #define GIC_CPU_INT5 5 /* Core Interrupt 5 */ |
88 | 88 | ||
89 | /* MALTA GIC local interrupts */ | ||
90 | #define GIC_INT_TMR (GIC_CPU_INT5) | ||
91 | #define GIC_INT_PERFCTR (GIC_CPU_INT5) | ||
92 | |||
93 | /* GIC constants */ | ||
94 | /* Add 2 to convert non-eic hw int # to eic vector # */ | ||
95 | #define GIC_CPU_TO_VEC_OFFSET (2) | ||
96 | /* If we map an intr to pin X, GIC will actually generate vector X+1 */ | ||
97 | #define GIC_PIN_TO_VEC_OFFSET (1) | ||
98 | |||
89 | #define GIC_EXT_INTR(x) x | 99 | #define GIC_EXT_INTR(x) x |
90 | 100 | ||
91 | /* External Interrupts used for IPI */ | 101 | /* External Interrupts used for IPI */ |
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index c9420aa97e32..e71ff4c317f2 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h | |||
@@ -48,7 +48,7 @@ | |||
48 | #define CP0_VPECONF0 $1, 2 | 48 | #define CP0_VPECONF0 $1, 2 |
49 | #define CP0_VPECONF1 $1, 3 | 49 | #define CP0_VPECONF1 $1, 3 |
50 | #define CP0_YQMASK $1, 4 | 50 | #define CP0_YQMASK $1, 4 |
51 | #define CP0_VPESCHEDULE $1, 5 | 51 | #define CP0_VPESCHEDULE $1, 5 |
52 | #define CP0_VPESCHEFBK $1, 6 | 52 | #define CP0_VPESCHEFBK $1, 6 |
53 | #define CP0_TCSTATUS $2, 1 | 53 | #define CP0_TCSTATUS $2, 1 |
54 | #define CP0_TCBIND $2, 2 | 54 | #define CP0_TCBIND $2, 2 |
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h index 5d33621b5658..4f8ddba8c360 100644 --- a/arch/mips/include/asm/switch_to.h +++ b/arch/mips/include/asm/switch_to.h | |||
@@ -22,7 +22,7 @@ struct task_struct; | |||
22 | * switch_to(n) should switch tasks to task nr n, first | 22 | * switch_to(n) should switch tasks to task nr n, first |
23 | * checking that n isn't the current task, in which case it does nothing. | 23 | * checking that n isn't the current task, in which case it does nothing. |
24 | */ | 24 | */ |
25 | extern asmlinkage void *resume(void *last, void *next, void *next_ti); | 25 | extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu); |
26 | 26 | ||
27 | extern unsigned int ll_bit; | 27 | extern unsigned int ll_bit; |
28 | extern struct task_struct *ll_task; | 28 | extern struct task_struct *ll_task; |
@@ -66,11 +66,13 @@ do { \ | |||
66 | 66 | ||
67 | #define switch_to(prev, next, last) \ | 67 | #define switch_to(prev, next, last) \ |
68 | do { \ | 68 | do { \ |
69 | u32 __usedfpu; \ | ||
69 | __mips_mt_fpaff_switch_to(prev); \ | 70 | __mips_mt_fpaff_switch_to(prev); \ |
70 | if (cpu_has_dsp) \ | 71 | if (cpu_has_dsp) \ |
71 | __save_dsp(prev); \ | 72 | __save_dsp(prev); \ |
72 | __clear_software_ll_bit(); \ | 73 | __clear_software_ll_bit(); \ |
73 | (last) = resume(prev, next, task_thread_info(next)); \ | 74 | __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU); \ |
75 | (last) = resume(prev, next, task_thread_info(next), __usedfpu); \ | ||
74 | } while (0) | 76 | } while (0) |
75 | 77 | ||
76 | #define finish_arch_switch(prev) \ | 78 | #define finish_arch_switch(prev) \ |
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index e2eca7d10598..ca97e0ecb64b 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h | |||
@@ -60,6 +60,8 @@ struct thread_info { | |||
60 | register struct thread_info *__current_thread_info __asm__("$28"); | 60 | register struct thread_info *__current_thread_info __asm__("$28"); |
61 | #define current_thread_info() __current_thread_info | 61 | #define current_thread_info() __current_thread_info |
62 | 62 | ||
63 | #endif /* !__ASSEMBLY__ */ | ||
64 | |||
63 | /* thread information allocation */ | 65 | /* thread information allocation */ |
64 | #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) | 66 | #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT) |
65 | #define THREAD_SIZE_ORDER (1) | 67 | #define THREAD_SIZE_ORDER (1) |
@@ -85,8 +87,6 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
85 | 87 | ||
86 | #define STACK_WARN (THREAD_SIZE / 8) | 88 | #define STACK_WARN (THREAD_SIZE / 8) |
87 | 89 | ||
88 | #endif /* !__ASSEMBLY__ */ | ||
89 | |||
90 | #define PREEMPT_ACTIVE 0x10000000 | 90 | #define PREEMPT_ACTIVE 0x10000000 |
91 | 91 | ||
92 | /* | 92 | /* |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 6ae7ce4ac63e..f4630e1082ab 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
@@ -4,7 +4,7 @@ | |||
4 | * Copyright (C) xxxx the Anonymous | 4 | * Copyright (C) xxxx the Anonymous |
5 | * Copyright (C) 1994 - 2006 Ralf Baechle | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
7 | * Copyright (C) 2001, 2004 MIPS Inc. | 7 | * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc. |
8 | * | 8 | * |
9 | * This program is free software; you can redistribute it and/or | 9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License | 10 | * modify it under the terms of the GNU General Public License |
@@ -199,6 +199,7 @@ void __init check_wait(void) | |||
199 | cpu_wait = rm7k_wait_irqoff; | 199 | cpu_wait = rm7k_wait_irqoff; |
200 | break; | 200 | break; |
201 | 201 | ||
202 | case CPU_M14KC: | ||
202 | case CPU_24K: | 203 | case CPU_24K: |
203 | case CPU_34K: | 204 | case CPU_34K: |
204 | case CPU_1004K: | 205 | case CPU_1004K: |
@@ -810,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | |||
810 | c->cputype = CPU_5KC; | 811 | c->cputype = CPU_5KC; |
811 | __cpu_name[cpu] = "MIPS 5Kc"; | 812 | __cpu_name[cpu] = "MIPS 5Kc"; |
812 | break; | 813 | break; |
814 | case PRID_IMP_5KE: | ||
815 | c->cputype = CPU_5KE; | ||
816 | __cpu_name[cpu] = "MIPS 5KE"; | ||
817 | break; | ||
813 | case PRID_IMP_20KC: | 818 | case PRID_IMP_20KC: |
814 | c->cputype = CPU_20KC; | 819 | c->cputype = CPU_20KC; |
815 | __cpu_name[cpu] = "MIPS 20Kc"; | 820 | __cpu_name[cpu] = "MIPS 20Kc"; |
@@ -831,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) | |||
831 | c->cputype = CPU_74K; | 836 | c->cputype = CPU_74K; |
832 | __cpu_name[cpu] = "MIPS 74Kc"; | 837 | __cpu_name[cpu] = "MIPS 74Kc"; |
833 | break; | 838 | break; |
839 | case PRID_IMP_M14KC: | ||
840 | c->cputype = CPU_M14KC; | ||
841 | __cpu_name[cpu] = "MIPS M14Kc"; | ||
842 | break; | ||
834 | case PRID_IMP_1004K: | 843 | case PRID_IMP_1004K: |
835 | c->cputype = CPU_1004K; | 844 | c->cputype = CPU_1004K; |
836 | __cpu_name[cpu] = "MIPS 1004Kc"; | 845 | __cpu_name[cpu] = "MIPS 1004Kc"; |
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c index 57ba13edb03a..3fc1691110dc 100644 --- a/arch/mips/kernel/mips_ksyms.c +++ b/arch/mips/kernel/mips_ksyms.c | |||
@@ -5,7 +5,7 @@ | |||
5 | * License. See the file "COPYING" in the main directory of this archive | 5 | * License. See the file "COPYING" in the main directory of this archive |
6 | * for more details. | 6 | * for more details. |
7 | * | 7 | * |
8 | * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle | 8 | * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle |
9 | * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc. | 9 | * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc. |
10 | */ | 10 | */ |
11 | #include <linux/interrupt.h> | 11 | #include <linux/interrupt.h> |
@@ -35,6 +35,12 @@ EXPORT_SYMBOL(memmove); | |||
35 | EXPORT_SYMBOL(kernel_thread); | 35 | EXPORT_SYMBOL(kernel_thread); |
36 | 36 | ||
37 | /* | 37 | /* |
38 | * Functions that operate on entire pages. Mostly used by memory management. | ||
39 | */ | ||
40 | EXPORT_SYMBOL(clear_page); | ||
41 | EXPORT_SYMBOL(copy_page); | ||
42 | |||
43 | /* | ||
38 | * Userspace access stuff. | 44 | * Userspace access stuff. |
39 | */ | 45 | */ |
40 | EXPORT_SYMBOL(__copy_user); | 46 | EXPORT_SYMBOL(__copy_user); |
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index ce89c8061708..0441f54b2a6a 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S | |||
@@ -31,7 +31,7 @@ | |||
31 | 31 | ||
32 | /* | 32 | /* |
33 | * task_struct *resume(task_struct *prev, task_struct *next, | 33 | * task_struct *resume(task_struct *prev, task_struct *next, |
34 | * struct thread_info *next_ti) | 34 | * struct thread_info *next_ti, int usedfpu) |
35 | */ | 35 | */ |
36 | .align 7 | 36 | .align 7 |
37 | LEAF(resume) | 37 | LEAF(resume) |
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index f29099b104c4..eb5e394a4650 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c | |||
@@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters) | |||
162 | return counters >> vpe_shift(); | 162 | return counters >> vpe_shift(); |
163 | } | 163 | } |
164 | 164 | ||
165 | static unsigned int counters_per_cpu_to_total(unsigned int counters) | ||
166 | { | ||
167 | return counters << vpe_shift(); | ||
168 | } | ||
169 | |||
170 | #else /* !CONFIG_MIPS_MT_SMP */ | 165 | #else /* !CONFIG_MIPS_MT_SMP */ |
171 | #define vpe_id() 0 | 166 | #define vpe_id() 0 |
172 | 167 | ||
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S index 293898391e67..9c51be5a163a 100644 --- a/arch/mips/kernel/r2300_switch.S +++ b/arch/mips/kernel/r2300_switch.S | |||
@@ -43,7 +43,7 @@ | |||
43 | 43 | ||
44 | /* | 44 | /* |
45 | * task_struct *resume(task_struct *prev, task_struct *next, | 45 | * task_struct *resume(task_struct *prev, task_struct *next, |
46 | * struct thread_info *next_ti) ) | 46 | * struct thread_info *next_ti, int usedfpu) |
47 | */ | 47 | */ |
48 | LEAF(resume) | 48 | LEAF(resume) |
49 | mfc0 t1, CP0_STATUS | 49 | mfc0 t1, CP0_STATUS |
@@ -51,18 +51,9 @@ LEAF(resume) | |||
51 | cpu_save_nonscratch a0 | 51 | cpu_save_nonscratch a0 |
52 | sw ra, THREAD_REG31(a0) | 52 | sw ra, THREAD_REG31(a0) |
53 | 53 | ||
54 | /* | 54 | beqz a3, 1f |
55 | * check if we need to save FPU registers | ||
56 | */ | ||
57 | lw t3, TASK_THREAD_INFO(a0) | ||
58 | lw t0, TI_FLAGS(t3) | ||
59 | li t1, _TIF_USEDFPU | ||
60 | and t2, t0, t1 | ||
61 | beqz t2, 1f | ||
62 | nor t1, zero, t1 | ||
63 | 55 | ||
64 | and t0, t0, t1 | 56 | PTR_L t3, TASK_THREAD_INFO(a0) |
65 | sw t0, TI_FLAGS(t3) | ||
66 | 57 | ||
67 | /* | 58 | /* |
68 | * clear saved user stack CU1 bit | 59 | * clear saved user stack CU1 bit |
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S index 9414f9354469..42d2a3938420 100644 --- a/arch/mips/kernel/r4k_switch.S +++ b/arch/mips/kernel/r4k_switch.S | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | /* | 42 | /* |
43 | * task_struct *resume(task_struct *prev, task_struct *next, | 43 | * task_struct *resume(task_struct *prev, task_struct *next, |
44 | * struct thread_info *next_ti) | 44 | * struct thread_info *next_ti, int usedfpu) |
45 | */ | 45 | */ |
46 | .align 5 | 46 | .align 5 |
47 | LEAF(resume) | 47 | LEAF(resume) |
@@ -53,16 +53,10 @@ | |||
53 | /* | 53 | /* |
54 | * check if we need to save FPU registers | 54 | * check if we need to save FPU registers |
55 | */ | 55 | */ |
56 | PTR_L t3, TASK_THREAD_INFO(a0) | ||
57 | LONG_L t0, TI_FLAGS(t3) | ||
58 | li t1, _TIF_USEDFPU | ||
59 | and t2, t0, t1 | ||
60 | beqz t2, 1f | ||
61 | nor t1, zero, t1 | ||
62 | 56 | ||
63 | and t0, t0, t1 | 57 | beqz a3, 1f |
64 | LONG_S t0, TI_FLAGS(t3) | ||
65 | 58 | ||
59 | PTR_L t3, TASK_THREAD_INFO(a0) | ||
66 | /* | 60 | /* |
67 | * clear saved user stack CU1 bit | 61 | * clear saved user stack CU1 bit |
68 | */ | 62 | */ |
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c index 3046e2986006..8e393b8443f7 100644 --- a/arch/mips/kernel/smp-bmips.c +++ b/arch/mips/kernel/smp-bmips.c | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <linux/smp.h> | 15 | #include <linux/smp.h> |
16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
17 | #include <linux/spinlock.h> | 17 | #include <linux/spinlock.h> |
18 | #include <linux/init.h> | ||
19 | #include <linux/cpu.h> | 18 | #include <linux/cpu.h> |
20 | #include <linux/cpumask.h> | 19 | #include <linux/cpumask.h> |
21 | #include <linux/reboot.h> | 20 | #include <linux/reboot.h> |
@@ -197,13 +196,6 @@ static void bmips_init_secondary(void) | |||
197 | 196 | ||
198 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); | 197 | write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0)); |
199 | #endif | 198 | #endif |
200 | |||
201 | /* make sure there won't be a timer interrupt for a little while */ | ||
202 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); | ||
203 | |||
204 | irq_enable_hazard(); | ||
205 | set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); | ||
206 | irq_enable_hazard(); | ||
207 | } | 199 | } |
208 | 200 | ||
209 | /* | 201 | /* |
@@ -212,6 +204,13 @@ static void bmips_init_secondary(void) | |||
212 | static void bmips_smp_finish(void) | 204 | static void bmips_smp_finish(void) |
213 | { | 205 | { |
214 | pr_info("SMP: CPU%d is running\n", smp_processor_id()); | 206 | pr_info("SMP: CPU%d is running\n", smp_processor_id()); |
207 | |||
208 | /* make sure there won't be a timer interrupt for a little while */ | ||
209 | write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); | ||
210 | |||
211 | irq_enable_hazard(); | ||
212 | set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE); | ||
213 | irq_enable_hazard(); | ||
215 | } | 214 | } |
216 | 215 | ||
217 | /* | 216 | /* |
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 48650c818040..1268392f1d27 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c | |||
@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void) | |||
122 | 122 | ||
123 | notify_cpu_starting(cpu); | 123 | notify_cpu_starting(cpu); |
124 | 124 | ||
125 | mp_ops->smp_finish(); | 125 | set_cpu_online(cpu, true); |
126 | |||
126 | set_cpu_sibling_map(cpu); | 127 | set_cpu_sibling_map(cpu); |
127 | 128 | ||
128 | cpu_set(cpu, cpu_callin_map); | 129 | cpu_set(cpu, cpu_callin_map); |
129 | 130 | ||
130 | synchronise_count_slave(); | 131 | synchronise_count_slave(); |
131 | 132 | ||
133 | /* | ||
134 | * irq will be enabled in ->smp_finish(), enabling it too early | ||
135 | * is dangerous. | ||
136 | */ | ||
137 | WARN_ON_ONCE(!irqs_disabled()); | ||
138 | mp_ops->smp_finish(); | ||
139 | |||
132 | cpu_idle(); | 140 | cpu_idle(); |
133 | } | 141 | } |
134 | 142 | ||
@@ -196,8 +204,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle) | |||
196 | while (!cpu_isset(cpu, cpu_callin_map)) | 204 | while (!cpu_isset(cpu, cpu_callin_map)) |
197 | udelay(100); | 205 | udelay(100); |
198 | 206 | ||
199 | set_cpu_online(cpu, true); | ||
200 | |||
201 | return 0; | 207 | return 0; |
202 | } | 208 | } |
203 | 209 | ||
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index f5dd38f1d015..15b5f3cfd20c 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -322,7 +322,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot) | |||
322 | 322 | ||
323 | /* | 323 | /* |
324 | * Common setup before any secondaries are started | 324 | * Common setup before any secondaries are started |
325 | * Make sure all CPU's are in a sensible state before we boot any of the | 325 | * Make sure all CPUs are in a sensible state before we boot any of the |
326 | * secondaries. | 326 | * secondaries. |
327 | * | 327 | * |
328 | * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly | 328 | * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly |
@@ -340,12 +340,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu) | |||
340 | /* | 340 | /* |
341 | * TCContext gets an offset from the base of the IPIQ array | 341 | * TCContext gets an offset from the base of the IPIQ array |
342 | * to be used in low-level code to detect the presence of | 342 | * to be used in low-level code to detect the presence of |
343 | * an active IPI queue | 343 | * an active IPI queue. |
344 | */ | 344 | */ |
345 | write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); | 345 | write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16); |
346 | /* Bind tc to vpe */ | 346 | /* Bind tc to vpe */ |
347 | write_tc_c0_tcbind(vpe); | 347 | write_tc_c0_tcbind(vpe); |
348 | /* In general, all TCs should have the same cpu_data indications */ | 348 | /* In general, all TCs should have the same cpu_data indications. */ |
349 | memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); | 349 | memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips)); |
350 | /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ | 350 | /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */ |
351 | if (cpu_data[0].cputype == CPU_34K || | 351 | if (cpu_data[0].cputype == CPU_34K || |
@@ -358,8 +358,8 @@ static void smtc_tc_setup(int vpe, int tc, int cpu) | |||
358 | } | 358 | } |
359 | 359 | ||
360 | /* | 360 | /* |
361 | * Tweak to get Count registes in as close a sync as possible. | 361 | * Tweak to get Count registes in as close a sync as possible. The |
362 | * Value seems good for 34K-class cores. | 362 | * value seems good for 34K-class cores. |
363 | */ | 363 | */ |
364 | 364 | ||
365 | #define CP0_SKEW 8 | 365 | #define CP0_SKEW 8 |
@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle) | |||
615 | 615 | ||
616 | void smtc_init_secondary(void) | 616 | void smtc_init_secondary(void) |
617 | { | 617 | { |
618 | local_irq_enable(); | ||
619 | } | 618 | } |
620 | 619 | ||
621 | void smtc_smp_finish(void) | 620 | void smtc_smp_finish(void) |
@@ -631,6 +630,8 @@ void smtc_smp_finish(void) | |||
631 | if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) | 630 | if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id)) |
632 | write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); | 631 | write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ); |
633 | 632 | ||
633 | local_irq_enable(); | ||
634 | |||
634 | printk("TC %d going on-line as CPU %d\n", | 635 | printk("TC %d going on-line as CPU %d\n", |
635 | cpu_data[smp_processor_id()].tc_id, smp_processor_id()); | 636 | cpu_data[smp_processor_id()].tc_id, smp_processor_id()); |
636 | } | 637 | } |
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c index 99f913c8d7a6..842d55e411fd 100644 --- a/arch/mips/kernel/sync-r4k.c +++ b/arch/mips/kernel/sync-r4k.c | |||
@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void) | |||
111 | void __cpuinit synchronise_count_slave(void) | 111 | void __cpuinit synchronise_count_slave(void) |
112 | { | 112 | { |
113 | int i; | 113 | int i; |
114 | unsigned long flags; | ||
115 | unsigned int initcount; | 114 | unsigned int initcount; |
116 | int ncpus; | 115 | int ncpus; |
117 | 116 | ||
@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void) | |||
123 | return; | 122 | return; |
124 | #endif | 123 | #endif |
125 | 124 | ||
126 | local_irq_save(flags); | ||
127 | |||
128 | /* | 125 | /* |
129 | * Not every cpu is online at the time this gets called, | 126 | * Not every cpu is online at the time this gets called, |
130 | * so we first wait for the master to say everyone is ready | 127 | * so we first wait for the master to say everyone is ready |
@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void) | |||
154 | } | 151 | } |
155 | /* Arrange for an interrupt in a short while */ | 152 | /* Arrange for an interrupt in a short while */ |
156 | write_c0_compare(read_c0_count() + COUNTON); | 153 | write_c0_compare(read_c0_count() + COUNTON); |
157 | |||
158 | local_irq_restore(flags); | ||
159 | } | 154 | } |
160 | #undef NR_LOOPS | 155 | #undef NR_LOOPS |
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 2d0c2a277f52..c3c293543703 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -132,6 +132,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) | |||
132 | unsigned long ra = regs->regs[31]; | 132 | unsigned long ra = regs->regs[31]; |
133 | unsigned long pc = regs->cp0_epc; | 133 | unsigned long pc = regs->cp0_epc; |
134 | 134 | ||
135 | if (!task) | ||
136 | task = current; | ||
137 | |||
135 | if (raw_show_trace || !__kernel_text_address(pc)) { | 138 | if (raw_show_trace || !__kernel_text_address(pc)) { |
136 | show_raw_backtrace(sp); | 139 | show_raw_backtrace(sp); |
137 | return; | 140 | return; |
@@ -1249,6 +1252,7 @@ static inline void parity_protection_init(void) | |||
1249 | break; | 1252 | break; |
1250 | 1253 | ||
1251 | case CPU_5KC: | 1254 | case CPU_5KC: |
1255 | case CPU_5KE: | ||
1252 | write_c0_ecc(0x80000000); | 1256 | write_c0_ecc(0x80000000); |
1253 | back_to_back_c0_hazard(); | 1257 | back_to_back_c0_hazard(); |
1254 | /* Set the PE bit (bit 31) in the c0_errctl register. */ | 1258 | /* Set the PE bit (bit 31) in the c0_errctl register. */ |
@@ -1498,6 +1502,7 @@ extern void flush_tlb_handlers(void); | |||
1498 | * Timer interrupt | 1502 | * Timer interrupt |
1499 | */ | 1503 | */ |
1500 | int cp0_compare_irq; | 1504 | int cp0_compare_irq; |
1505 | EXPORT_SYMBOL_GPL(cp0_compare_irq); | ||
1501 | int cp0_compare_irq_shift; | 1506 | int cp0_compare_irq_shift; |
1502 | 1507 | ||
1503 | /* | 1508 | /* |
@@ -1597,7 +1602,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu) | |||
1597 | cp0_perfcount_irq = -1; | 1602 | cp0_perfcount_irq = -1; |
1598 | } else { | 1603 | } else { |
1599 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; | 1604 | cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; |
1600 | cp0_compare_irq_shift = cp0_compare_irq; | 1605 | cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; |
1601 | cp0_perfcount_irq = -1; | 1606 | cp0_perfcount_irq = -1; |
1602 | } | 1607 | } |
1603 | 1608 | ||
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 924da5eb7031..df243a64f430 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S | |||
@@ -1,5 +1,6 @@ | |||
1 | #include <asm/asm-offsets.h> | 1 | #include <asm/asm-offsets.h> |
2 | #include <asm/page.h> | 2 | #include <asm/page.h> |
3 | #include <asm/thread_info.h> | ||
3 | #include <asm-generic/vmlinux.lds.h> | 4 | #include <asm-generic/vmlinux.lds.h> |
4 | 5 | ||
5 | #undef mips | 6 | #undef mips |
@@ -72,7 +73,7 @@ SECTIONS | |||
72 | .data : { /* Data */ | 73 | .data : { /* Data */ |
73 | . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ | 74 | . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ |
74 | 75 | ||
75 | INIT_TASK_DATA(PAGE_SIZE) | 76 | INIT_TASK_DATA(THREAD_SIZE) |
76 | NOSAVE_DATA | 77 | NOSAVE_DATA |
77 | CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) | 78 | CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) |
78 | READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) | 79 | READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) |
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile index 4aa20280613e..fd6203f14f1f 100644 --- a/arch/mips/mm/Makefile +++ b/arch/mips/mm/Makefile | |||
@@ -3,8 +3,8 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | obj-y += cache.o dma-default.o extable.o fault.o \ | 5 | obj-y += cache.o dma-default.o extable.o fault.o \ |
6 | gup.o init.o mmap.o page.o tlbex.o \ | 6 | gup.o init.o mmap.o page.o page-funcs.o \ |
7 | tlbex-fault.o uasm.o | 7 | tlbex.o tlbex-fault.o uasm.o |
8 | 8 | ||
9 | obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o | 9 | obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o |
10 | obj-$(CONFIG_64BIT) += pgtable-64.o | 10 | obj-$(CONFIG_64BIT) += pgtable-64.o |
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 5109be96d98d..f092c265dc63 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c | |||
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void) | |||
977 | c->icache.linesz = 2 << lsize; | 977 | c->icache.linesz = 2 << lsize; |
978 | else | 978 | else |
979 | c->icache.linesz = lsize; | 979 | c->icache.linesz = lsize; |
980 | c->icache.sets = 64 << ((config1 >> 22) & 7); | 980 | c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); |
981 | c->icache.ways = 1 + ((config1 >> 16) & 7); | 981 | c->icache.ways = 1 + ((config1 >> 16) & 7); |
982 | 982 | ||
983 | icache_size = c->icache.sets * | 983 | icache_size = c->icache.sets * |
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void) | |||
997 | c->dcache.linesz = 2 << lsize; | 997 | c->dcache.linesz = 2 << lsize; |
998 | else | 998 | else |
999 | c->dcache.linesz= lsize; | 999 | c->dcache.linesz= lsize; |
1000 | c->dcache.sets = 64 << ((config1 >> 13) & 7); | 1000 | c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); |
1001 | c->dcache.ways = 1 + ((config1 >> 7) & 7); | 1001 | c->dcache.ways = 1 + ((config1 >> 7) & 7); |
1002 | 1002 | ||
1003 | dcache_size = c->dcache.sets * | 1003 | dcache_size = c->dcache.sets * |
@@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void) | |||
1051 | case CPU_R14000: | 1051 | case CPU_R14000: |
1052 | break; | 1052 | break; |
1053 | 1053 | ||
1054 | case CPU_M14KC: | ||
1054 | case CPU_24K: | 1055 | case CPU_24K: |
1055 | case CPU_34K: | 1056 | case CPU_34K: |
1056 | case CPU_74K: | 1057 | case CPU_74K: |
diff --git a/arch/mips/mm/page-funcs.S b/arch/mips/mm/page-funcs.S new file mode 100644 index 000000000000..48a6b38ff13e --- /dev/null +++ b/arch/mips/mm/page-funcs.S | |||
@@ -0,0 +1,50 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Micro-assembler generated clear_page/copy_page functions. | ||
7 | * | ||
8 | * Copyright (C) 2012 MIPS Technologies, Inc. | ||
9 | * Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org> | ||
10 | */ | ||
11 | #include <asm/asm.h> | ||
12 | #include <asm/regdef.h> | ||
13 | |||
14 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | ||
15 | #define cpu_clear_page_function_name clear_page_cpu | ||
16 | #define cpu_copy_page_function_name copy_page_cpu | ||
17 | #else | ||
18 | #define cpu_clear_page_function_name clear_page | ||
19 | #define cpu_copy_page_function_name copy_page | ||
20 | #endif | ||
21 | |||
22 | /* | ||
23 | * Maximum sizes: | ||
24 | * | ||
25 | * R4000 128 bytes S-cache: 0x058 bytes | ||
26 | * R4600 v1.7: 0x05c bytes | ||
27 | * R4600 v2.0: 0x060 bytes | ||
28 | * With prefetching, 16 word strides 0x120 bytes | ||
29 | */ | ||
30 | EXPORT(__clear_page_start) | ||
31 | LEAF(cpu_clear_page_function_name) | ||
32 | 1: j 1b /* Dummy, will be replaced. */ | ||
33 | .space 288 | ||
34 | END(cpu_clear_page_function_name) | ||
35 | EXPORT(__clear_page_end) | ||
36 | |||
37 | /* | ||
38 | * Maximum sizes: | ||
39 | * | ||
40 | * R4000 128 bytes S-cache: 0x11c bytes | ||
41 | * R4600 v1.7: 0x080 bytes | ||
42 | * R4600 v2.0: 0x07c bytes | ||
43 | * With prefetching, 16 word strides 0x540 bytes | ||
44 | */ | ||
45 | EXPORT(__copy_page_start) | ||
46 | LEAF(cpu_copy_page_function_name) | ||
47 | 1: j 1b /* Dummy, will be replaced. */ | ||
48 | .space 1344 | ||
49 | END(cpu_copy_page_function_name) | ||
50 | EXPORT(__copy_page_end) | ||
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index cc0b626858b3..98f530e18216 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c | |||
@@ -6,6 +6,7 @@ | |||
6 | * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) | 6 | * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org) |
7 | * Copyright (C) 2007 Maciej W. Rozycki | 7 | * Copyright (C) 2007 Maciej W. Rozycki |
8 | * Copyright (C) 2008 Thiemo Seufer | 8 | * Copyright (C) 2008 Thiemo Seufer |
9 | * Copyright (C) 2012 MIPS Technologies, Inc. | ||
9 | */ | 10 | */ |
10 | #include <linux/init.h> | 11 | #include <linux/init.h> |
11 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5]; | |||
71 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) | 72 | #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010) |
72 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) | 73 | #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020) |
73 | 74 | ||
74 | /* | ||
75 | * Maximum sizes: | ||
76 | * | ||
77 | * R4000 128 bytes S-cache: 0x058 bytes | ||
78 | * R4600 v1.7: 0x05c bytes | ||
79 | * R4600 v2.0: 0x060 bytes | ||
80 | * With prefetching, 16 word strides 0x120 bytes | ||
81 | */ | ||
82 | |||
83 | static u32 clear_page_array[0x120 / 4]; | ||
84 | |||
85 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | ||
86 | void clear_page_cpu(void *page) __attribute__((alias("clear_page_array"))); | ||
87 | #else | ||
88 | void clear_page(void *page) __attribute__((alias("clear_page_array"))); | ||
89 | #endif | ||
90 | |||
91 | EXPORT_SYMBOL(clear_page); | ||
92 | |||
93 | /* | ||
94 | * Maximum sizes: | ||
95 | * | ||
96 | * R4000 128 bytes S-cache: 0x11c bytes | ||
97 | * R4600 v1.7: 0x080 bytes | ||
98 | * R4600 v2.0: 0x07c bytes | ||
99 | * With prefetching, 16 word strides 0x540 bytes | ||
100 | */ | ||
101 | static u32 copy_page_array[0x540 / 4]; | ||
102 | |||
103 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | ||
104 | void | ||
105 | copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array"))); | ||
106 | #else | ||
107 | void copy_page(void *to, void *from) __attribute__((alias("copy_page_array"))); | ||
108 | #endif | ||
109 | |||
110 | EXPORT_SYMBOL(copy_page); | ||
111 | |||
112 | |||
113 | static int pref_bias_clear_store __cpuinitdata; | 75 | static int pref_bias_clear_store __cpuinitdata; |
114 | static int pref_bias_copy_load __cpuinitdata; | 76 | static int pref_bias_copy_load __cpuinitdata; |
115 | static int pref_bias_copy_store __cpuinitdata; | 77 | static int pref_bias_copy_store __cpuinitdata; |
@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off) | |||
282 | } | 244 | } |
283 | } | 245 | } |
284 | 246 | ||
247 | extern u32 __clear_page_start; | ||
248 | extern u32 __clear_page_end; | ||
249 | extern u32 __copy_page_start; | ||
250 | extern u32 __copy_page_end; | ||
251 | |||
285 | void __cpuinit build_clear_page(void) | 252 | void __cpuinit build_clear_page(void) |
286 | { | 253 | { |
287 | int off; | 254 | int off; |
288 | u32 *buf = (u32 *)&clear_page_array; | 255 | u32 *buf = &__clear_page_start; |
289 | struct uasm_label *l = labels; | 256 | struct uasm_label *l = labels; |
290 | struct uasm_reloc *r = relocs; | 257 | struct uasm_reloc *r = relocs; |
291 | int i; | 258 | int i; |
@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void) | |||
356 | uasm_i_jr(&buf, RA); | 323 | uasm_i_jr(&buf, RA); |
357 | uasm_i_nop(&buf); | 324 | uasm_i_nop(&buf); |
358 | 325 | ||
359 | BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array)); | 326 | BUG_ON(buf > &__clear_page_end); |
360 | 327 | ||
361 | uasm_resolve_relocs(relocs, labels); | 328 | uasm_resolve_relocs(relocs, labels); |
362 | 329 | ||
363 | pr_debug("Synthesized clear page handler (%u instructions).\n", | 330 | pr_debug("Synthesized clear page handler (%u instructions).\n", |
364 | (u32)(buf - clear_page_array)); | 331 | (u32)(buf - &__clear_page_start)); |
365 | 332 | ||
366 | pr_debug("\t.set push\n"); | 333 | pr_debug("\t.set push\n"); |
367 | pr_debug("\t.set noreorder\n"); | 334 | pr_debug("\t.set noreorder\n"); |
368 | for (i = 0; i < (buf - clear_page_array); i++) | 335 | for (i = 0; i < (buf - &__clear_page_start); i++) |
369 | pr_debug("\t.word 0x%08x\n", clear_page_array[i]); | 336 | pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]); |
370 | pr_debug("\t.set pop\n"); | 337 | pr_debug("\t.set pop\n"); |
371 | } | 338 | } |
372 | 339 | ||
@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off) | |||
427 | void __cpuinit build_copy_page(void) | 394 | void __cpuinit build_copy_page(void) |
428 | { | 395 | { |
429 | int off; | 396 | int off; |
430 | u32 *buf = (u32 *)©_page_array; | 397 | u32 *buf = &__copy_page_start; |
431 | struct uasm_label *l = labels; | 398 | struct uasm_label *l = labels; |
432 | struct uasm_reloc *r = relocs; | 399 | struct uasm_reloc *r = relocs; |
433 | int i; | 400 | int i; |
@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void) | |||
595 | uasm_i_jr(&buf, RA); | 562 | uasm_i_jr(&buf, RA); |
596 | uasm_i_nop(&buf); | 563 | uasm_i_nop(&buf); |
597 | 564 | ||
598 | BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array)); | 565 | BUG_ON(buf > &__copy_page_end); |
599 | 566 | ||
600 | uasm_resolve_relocs(relocs, labels); | 567 | uasm_resolve_relocs(relocs, labels); |
601 | 568 | ||
602 | pr_debug("Synthesized copy page handler (%u instructions).\n", | 569 | pr_debug("Synthesized copy page handler (%u instructions).\n", |
603 | (u32)(buf - copy_page_array)); | 570 | (u32)(buf - &__copy_page_start)); |
604 | 571 | ||
605 | pr_debug("\t.set push\n"); | 572 | pr_debug("\t.set push\n"); |
606 | pr_debug("\t.set noreorder\n"); | 573 | pr_debug("\t.set noreorder\n"); |
607 | for (i = 0; i < (buf - copy_page_array); i++) | 574 | for (i = 0; i < (buf - &__copy_page_start); i++) |
608 | pr_debug("\t.word 0x%08x\n", copy_page_array[i]); | 575 | pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]); |
609 | pr_debug("\t.set pop\n"); | 576 | pr_debug("\t.set pop\n"); |
610 | } | 577 | } |
611 | 578 | ||
612 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS | 579 | #ifdef CONFIG_SIBYTE_DMA_PAGEOPS |
580 | extern void clear_page_cpu(void *page); | ||
581 | extern void copy_page_cpu(void *to, void *from); | ||
613 | 582 | ||
614 | /* | 583 | /* |
615 | * Pad descriptors to cacheline, since each is exclusively owned by a | 584 | * Pad descriptors to cacheline, since each is exclusively owned by a |
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 0bc485b3cd60..03eb0ef91580 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
@@ -9,6 +9,7 @@ | |||
9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki | 9 | * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki |
10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) | 10 | * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) |
11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. | 11 | * Copyright (C) 2008, 2009 Cavium Networks, Inc. |
12 | * Copyright (C) 2011 MIPS Technologies, Inc. | ||
12 | * | 13 | * |
13 | * ... and the days got worse and worse and now you see | 14 | * ... and the days got worse and worse and now you see |
14 | * I've gone completly out of my mind. | 15 | * I've gone completly out of my mind. |
@@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, | |||
494 | case CPU_R14000: | 495 | case CPU_R14000: |
495 | case CPU_4KC: | 496 | case CPU_4KC: |
496 | case CPU_4KEC: | 497 | case CPU_4KEC: |
498 | case CPU_M14KC: | ||
497 | case CPU_SB1: | 499 | case CPU_SB1: |
498 | case CPU_SB1A: | 500 | case CPU_SB1A: |
499 | case CPU_4KSC: | 501 | case CPU_4KSC: |
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index bf80921f2f56..284dea54faf5 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c | |||
@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void) | |||
241 | return; | 241 | return; |
242 | } | 242 | } |
243 | 243 | ||
244 | if (controller->io_resource->start < 0x00001000UL) /* FIXME */ | 244 | /* Change start address to avoid conflicts with ACPI and SMB devices */ |
245 | controller->io_resource->start = 0x00001000UL; | 245 | if (controller->io_resource->start < 0x00002000UL) |
246 | controller->io_resource->start = 0x00002000UL; | ||
246 | 247 | ||
247 | iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ | 248 | iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ |
248 | ioport_resource.end = controller->io_resource->end; | 249 | ioport_resource.end = controller->io_resource->end; |
@@ -253,7 +254,7 @@ void __init mips_pcibios_init(void) | |||
253 | } | 254 | } |
254 | 255 | ||
255 | /* Enable PCI 2.1 compatibility in PIIX4 */ | 256 | /* Enable PCI 2.1 compatibility in PIIX4 */ |
256 | static void __init quirk_dlcsetup(struct pci_dev *dev) | 257 | static void __devinit quirk_dlcsetup(struct pci_dev *dev) |
257 | { | 258 | { |
258 | u8 odlc, ndlc; | 259 | u8 odlc, ndlc; |
259 | (void) pci_read_config_byte(dev, 0x82, &odlc); | 260 | (void) pci_read_config_byte(dev, 0x82, &odlc); |
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index b7f37d4982fa..2e28f653f66d 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c | |||
@@ -111,7 +111,7 @@ static void __init pci_clock_check(void) | |||
111 | unsigned int __iomem *jmpr_p = | 111 | unsigned int __iomem *jmpr_p = |
112 | (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); | 112 | (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int)); |
113 | int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; | 113 | int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07; |
114 | static const int pciclocks[] __initdata = { | 114 | static const int pciclocks[] __initconst = { |
115 | 33, 20, 25, 30, 12, 16, 37, 10 | 115 | 33, 20, 25, 30, 12, 16, 37, 10 |
116 | }; | 116 | }; |
117 | int pciclock = pciclocks[jmpr]; | 117 | int pciclock = pciclocks[jmpr]; |
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c index acb677a1227c..b3df7c2aad1e 100644 --- a/arch/mips/netlogic/xlp/setup.c +++ b/arch/mips/netlogic/xlp/setup.c | |||
@@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void) | |||
82 | 82 | ||
83 | void xlp_mmu_init(void) | 83 | void xlp_mmu_init(void) |
84 | { | 84 | { |
85 | /* enable extended TLB and Large Fixed TLB */ | ||
85 | write_c0_config6(read_c0_config6() | 0x24); | 86 | write_c0_config6(read_c0_config6() | 0x24); |
86 | current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | 87 | |
88 | /* set page mask of Fixed TLB in config7 */ | ||
87 | write_c0_config7(PM_DEFAULT_MASK >> | 89 | write_c0_config7(PM_DEFAULT_MASK >> |
88 | (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); | 90 | (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2))); |
89 | } | 91 | } |
@@ -100,6 +102,10 @@ void __init prom_init(void) | |||
100 | nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); | 102 | nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1)); |
101 | #ifdef CONFIG_SMP | 103 | #ifdef CONFIG_SMP |
102 | nlm_wakeup_secondary_cpus(0xffffffff); | 104 | nlm_wakeup_secondary_cpus(0xffffffff); |
105 | |||
106 | /* update TLB size after waking up threads */ | ||
107 | current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1; | ||
108 | |||
103 | register_smp_ops(&nlm_smp_ops); | 109 | register_smp_ops(&nlm_smp_ops); |
104 | #endif | 110 | #endif |
105 | } | 111 | } |
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index d1f2d4c52d42..b6e378211a2c 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c | |||
@@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) | |||
78 | 78 | ||
79 | switch (current_cpu_type()) { | 79 | switch (current_cpu_type()) { |
80 | case CPU_5KC: | 80 | case CPU_5KC: |
81 | case CPU_M14KC: | ||
81 | case CPU_20KC: | 82 | case CPU_20KC: |
82 | case CPU_24K: | 83 | case CPU_24K: |
83 | case CPU_25KF: | 84 | case CPU_25KF: |
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index baba3bcaa3c2..4d80a856048d 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c | |||
@@ -322,6 +322,10 @@ static int __init mipsxx_init(void) | |||
322 | 322 | ||
323 | op_model_mipsxx_ops.num_counters = counters; | 323 | op_model_mipsxx_ops.num_counters = counters; |
324 | switch (current_cpu_type()) { | 324 | switch (current_cpu_type()) { |
325 | case CPU_M14KC: | ||
326 | op_model_mipsxx_ops.cpu_type = "mips/M14Kc"; | ||
327 | break; | ||
328 | |||
325 | case CPU_20KC: | 329 | case CPU_20KC: |
326 | op_model_mipsxx_ops.cpu_type = "mips/20K"; | 330 | op_model_mipsxx_ops.cpu_type = "mips/20K"; |
327 | break; | 331 | break; |
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c index d5d4c018fb04..0857ab8c3919 100644 --- a/arch/mips/pci/fixup-fuloong2e.c +++ b/arch/mips/pci/fixup-fuloong2e.c | |||
@@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
48 | return 0; | 48 | return 0; |
49 | } | 49 | } |
50 | 50 | ||
51 | static void __init loongson2e_nec_fixup(struct pci_dev *pdev) | 51 | static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev) |
52 | { | 52 | { |
53 | unsigned int val; | 53 | unsigned int val; |
54 | 54 | ||
@@ -60,7 +60,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev) | |||
60 | pci_write_config_dword(pdev, 0xe4, 1 << 5); | 60 | pci_write_config_dword(pdev, 0xe4, 1 << 5); |
61 | } | 61 | } |
62 | 62 | ||
63 | static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) | 63 | static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev) |
64 | { | 64 | { |
65 | unsigned char c; | 65 | unsigned char c; |
66 | 66 | ||
@@ -135,7 +135,7 @@ static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) | |||
135 | printk(KERN_INFO"via686b fix: ISA bridge done\n"); | 135 | printk(KERN_INFO"via686b fix: ISA bridge done\n"); |
136 | } | 136 | } |
137 | 137 | ||
138 | static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) | 138 | static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev) |
139 | { | 139 | { |
140 | printk(KERN_INFO"via686b fix: IDE\n"); | 140 | printk(KERN_INFO"via686b fix: IDE\n"); |
141 | 141 | ||
@@ -168,19 +168,19 @@ static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) | |||
168 | printk(KERN_INFO"via686b fix: IDE done\n"); | 168 | printk(KERN_INFO"via686b fix: IDE done\n"); |
169 | } | 169 | } |
170 | 170 | ||
171 | static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) | 171 | static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev) |
172 | { | 172 | { |
173 | /* irq routing */ | 173 | /* irq routing */ |
174 | pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); | 174 | pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); |
175 | } | 175 | } |
176 | 176 | ||
177 | static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) | 177 | static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev) |
178 | { | 178 | { |
179 | /* irq routing */ | 179 | /* irq routing */ |
180 | pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); | 180 | pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); |
181 | } | 181 | } |
182 | 182 | ||
183 | static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) | 183 | static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev) |
184 | { | 184 | { |
185 | unsigned int val; | 185 | unsigned int val; |
186 | unsigned char c; | 186 | unsigned char c; |
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c index 4b9768d5d729..a7b917dcf604 100644 --- a/arch/mips/pci/fixup-lemote2f.c +++ b/arch/mips/pci/fixup-lemote2f.c | |||
@@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
96 | } | 96 | } |
97 | 97 | ||
98 | /* CS5536 SPEC. fixup */ | 98 | /* CS5536 SPEC. fixup */ |
99 | static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) | 99 | static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev) |
100 | { | 100 | { |
101 | /* the uart1 and uart2 interrupt in PIC is enabled as default */ | 101 | /* the uart1 and uart2 interrupt in PIC is enabled as default */ |
102 | pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); | 102 | pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); |
103 | pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); | 103 | pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); |
104 | } | 104 | } |
105 | 105 | ||
106 | static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) | 106 | static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev) |
107 | { | 107 | { |
108 | /* setting the mutex pin as IDE function */ | 108 | /* setting the mutex pin as IDE function */ |
109 | pci_write_config_dword(pdev, PCI_IDE_CFG_REG, | 109 | pci_write_config_dword(pdev, PCI_IDE_CFG_REG, |
110 | CS5536_IDE_FLASH_SIGNATURE); | 110 | CS5536_IDE_FLASH_SIGNATURE); |
111 | } | 111 | } |
112 | 112 | ||
113 | static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) | 113 | static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev) |
114 | { | 114 | { |
115 | /* enable the AUDIO interrupt in PIC */ | 115 | /* enable the AUDIO interrupt in PIC */ |
116 | pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); | 116 | pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); |
@@ -118,14 +118,14 @@ static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) | |||
118 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); | 118 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); |
119 | } | 119 | } |
120 | 120 | ||
121 | static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) | 121 | static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev) |
122 | { | 122 | { |
123 | /* enable the OHCI interrupt in PIC */ | 123 | /* enable the OHCI interrupt in PIC */ |
124 | /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ | 124 | /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ |
125 | pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); | 125 | pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); |
126 | } | 126 | } |
127 | 127 | ||
128 | static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) | 128 | static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev) |
129 | { | 129 | { |
130 | u32 hi, lo; | 130 | u32 hi, lo; |
131 | 131 | ||
@@ -137,7 +137,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) | |||
137 | pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); | 137 | pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); |
138 | } | 138 | } |
139 | 139 | ||
140 | static void __init loongson_nec_fixup(struct pci_dev *pdev) | 140 | static void __devinit loongson_nec_fixup(struct pci_dev *pdev) |
141 | { | 141 | { |
142 | unsigned int val; | 142 | unsigned int val; |
143 | 143 | ||
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index 0f48498bc231..70073c98ed32 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c | |||
@@ -49,10 +49,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev) | |||
49 | return 0; | 49 | return 0; |
50 | } | 50 | } |
51 | 51 | ||
52 | static void __init malta_piix_func0_fixup(struct pci_dev *pdev) | 52 | static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev) |
53 | { | 53 | { |
54 | unsigned char reg_val; | 54 | unsigned char reg_val; |
55 | static int piixirqmap[16] __initdata = { /* PIIX PIRQC[A:D] irq mappings */ | 55 | static int piixirqmap[16] __devinitdata = { /* PIIX PIRQC[A:D] irq mappings */ |
56 | 0, 0, 0, 3, | 56 | 0, 0, 0, 3, |
57 | 4, 5, 6, 7, | 57 | 4, 5, 6, 7, |
58 | 0, 9, 10, 11, | 58 | 0, 9, 10, 11, |
@@ -83,7 +83,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev) | |||
83 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, | 83 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, |
84 | malta_piix_func0_fixup); | 84 | malta_piix_func0_fixup); |
85 | 85 | ||
86 | static void __init malta_piix_func1_fixup(struct pci_dev *pdev) | 86 | static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev) |
87 | { | 87 | { |
88 | unsigned char reg_val; | 88 | unsigned char reg_val; |
89 | 89 | ||
diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c index e08f49cb6875..8e4f8288eca2 100644 --- a/arch/mips/pci/fixup-mpc30x.c +++ b/arch/mips/pci/fixup-mpc30x.c | |||
@@ -22,13 +22,13 @@ | |||
22 | 22 | ||
23 | #include <asm/vr41xx/mpc30x.h> | 23 | #include <asm/vr41xx/mpc30x.h> |
24 | 24 | ||
25 | static const int internal_func_irqs[] __initdata = { | 25 | static const int internal_func_irqs[] __initconst = { |
26 | VRC4173_CASCADE_IRQ, | 26 | VRC4173_CASCADE_IRQ, |
27 | VRC4173_AC97_IRQ, | 27 | VRC4173_AC97_IRQ, |
28 | VRC4173_USB_IRQ, | 28 | VRC4173_USB_IRQ, |
29 | }; | 29 | }; |
30 | 30 | ||
31 | static const int irq_tab_mpc30x[] __initdata = { | 31 | static const int irq_tab_mpc30x[] __initconst = { |
32 | [12] = VRC4173_PCMCIA1_IRQ, | 32 | [12] = VRC4173_PCMCIA1_IRQ, |
33 | [13] = VRC4173_PCMCIA2_IRQ, | 33 | [13] = VRC4173_PCMCIA2_IRQ, |
34 | [29] = MQ200_IRQ, | 34 | [29] = MQ200_IRQ, |
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c index f0bb9146e6c0..d02900a72916 100644 --- a/arch/mips/pci/fixup-sb1250.c +++ b/arch/mips/pci/fixup-sb1250.c | |||
@@ -15,7 +15,7 @@ | |||
15 | * Set the BCM1250, etc. PCI host bridge's TRDY timeout | 15 | * Set the BCM1250, etc. PCI host bridge's TRDY timeout |
16 | * to the finite max. | 16 | * to the finite max. |
17 | */ | 17 | */ |
18 | static void __init quirk_sb1250_pci(struct pci_dev *dev) | 18 | static void __devinit quirk_sb1250_pci(struct pci_dev *dev) |
19 | { | 19 | { |
20 | pci_write_config_byte(dev, 0x40, 0xff); | 20 | pci_write_config_byte(dev, 0x40, 0xff); |
21 | } | 21 | } |
@@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI, | |||
25 | /* | 25 | /* |
26 | * The BCM1250, etc. PCI/HT bridge reports as a host bridge. | 26 | * The BCM1250, etc. PCI/HT bridge reports as a host bridge. |
27 | */ | 27 | */ |
28 | static void __init quirk_sb1250_ht(struct pci_dev *dev) | 28 | static void __devinit quirk_sb1250_ht(struct pci_dev *dev) |
29 | { | 29 | { |
30 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; | 30 | dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
31 | } | 31 | } |
@@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT, | |||
35 | /* | 35 | /* |
36 | * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max. | 36 | * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max. |
37 | */ | 37 | */ |
38 | static void __init quirk_sp1011(struct pci_dev *dev) | 38 | static void __devinit quirk_sp1011(struct pci_dev *dev) |
39 | { | 39 | { |
40 | pci_write_config_byte(dev, 0x64, 0xff); | 40 | pci_write_config_byte(dev, 0x64, 0xff); |
41 | } | 41 | } |
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c index a1e7e6d80c8c..bc13e29d2bb3 100644 --- a/arch/mips/pci/ops-tx4927.c +++ b/arch/mips/pci/ops-tx4927.c | |||
@@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id) | |||
495 | } | 495 | } |
496 | 496 | ||
497 | #ifdef CONFIG_TOSHIBA_FPCIB0 | 497 | #ifdef CONFIG_TOSHIBA_FPCIB0 |
498 | static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) | 498 | static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev) |
499 | { | 499 | { |
500 | struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); | 500 | struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus); |
501 | 501 | ||
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 0fbe4c0c170a..fdc24440294c 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c | |||
@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev) | |||
212 | bridge->b_widget.w_tflush; /* Flush */ | 212 | bridge->b_widget.w_tflush; /* Flush */ |
213 | } | 213 | } |
214 | 214 | ||
215 | static void __init pci_fixup_ioc3(struct pci_dev *d) | 215 | static void __devinit pci_fixup_ioc3(struct pci_dev *d) |
216 | { | 216 | { |
217 | pci_disable_swapping(d); | 217 | pci_disable_swapping(d); |
218 | } | 218 | } |
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c index ea453532a33c..075d87acd12a 100644 --- a/arch/mips/pci/pci-lantiq.c +++ b/arch/mips/pci/pci-lantiq.c | |||
@@ -129,7 +129,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev) | |||
129 | 129 | ||
130 | /* setup reset gpio used by pci */ | 130 | /* setup reset gpio used by pci */ |
131 | reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); | 131 | reset_gpio = of_get_named_gpio(node, "gpio-reset", 0); |
132 | if (reset_gpio > 0) | 132 | if (gpio_is_valid(reset_gpio)) |
133 | devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset"); | 133 | devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset"); |
134 | 134 | ||
135 | /* enable auto-switching between PCI and EBU */ | 135 | /* enable auto-switching between PCI and EBU */ |
@@ -192,7 +192,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev) | |||
192 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); | 192 | ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN); |
193 | 193 | ||
194 | /* toggle reset pin */ | 194 | /* toggle reset pin */ |
195 | if (reset_gpio > 0) { | 195 | if (gpio_is_valid(reset_gpio)) { |
196 | __gpio_set_value(reset_gpio, 0); | 196 | __gpio_set_value(reset_gpio, 0); |
197 | wmb(); | 197 | wmb(); |
198 | mdelay(1); | 198 | mdelay(1); |
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c index 1644805a6730..172af1cd5867 100644 --- a/arch/mips/pci/pci-xlr.c +++ b/arch/mips/pci/pci-xlr.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #include <linux/irq.h> | 41 | #include <linux/irq.h> |
42 | #include <linux/irqdesc.h> | 42 | #include <linux/irqdesc.h> |
43 | #include <linux/console.h> | 43 | #include <linux/console.h> |
44 | #include <linux/pci_regs.h> | ||
44 | 45 | ||
45 | #include <asm/io.h> | 46 | #include <asm/io.h> |
46 | 47 | ||
@@ -156,35 +157,55 @@ struct pci_controller nlm_pci_controller = { | |||
156 | .io_offset = 0x00000000UL, | 157 | .io_offset = 0x00000000UL, |
157 | }; | 158 | }; |
158 | 159 | ||
160 | /* | ||
161 | * The top level PCIe links on the XLS PCIe controller appear as | ||
162 | * bridges. Given a device, this function finds which link it is | ||
163 | * on. | ||
164 | */ | ||
165 | static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) | ||
166 | { | ||
167 | struct pci_bus *bus, *p; | ||
168 | |||
169 | /* Find the bridge on bus 0 */ | ||
170 | bus = dev->bus; | ||
171 | for (p = bus->parent; p && p->number != 0; p = p->parent) | ||
172 | bus = p; | ||
173 | |||
174 | return p ? bus->self : NULL; | ||
175 | } | ||
176 | |||
159 | static int get_irq_vector(const struct pci_dev *dev) | 177 | static int get_irq_vector(const struct pci_dev *dev) |
160 | { | 178 | { |
179 | struct pci_dev *lnk; | ||
180 | |||
161 | if (!nlm_chip_is_xls()) | 181 | if (!nlm_chip_is_xls()) |
162 | return PIC_PCIX_IRQ; /* for XLR just one IRQ*/ | 182 | return PIC_PCIX_IRQ; /* for XLR just one IRQ */ |
163 | 183 | ||
164 | /* | 184 | /* |
165 | * For XLS PCIe, there is an IRQ per Link, find out which | 185 | * For XLS PCIe, there is an IRQ per Link, find out which |
166 | * link the device is on to assign interrupts | 186 | * link the device is on to assign interrupts |
167 | */ | 187 | */ |
168 | if (dev->bus->self == NULL) | 188 | lnk = xls_get_pcie_link(dev); |
189 | if (lnk == NULL) | ||
169 | return 0; | 190 | return 0; |
170 | 191 | ||
171 | switch (dev->bus->self->devfn) { | 192 | switch (PCI_SLOT(lnk->devfn)) { |
172 | case 0x0: | 193 | case 0: |
173 | return PIC_PCIE_LINK0_IRQ; | 194 | return PIC_PCIE_LINK0_IRQ; |
174 | case 0x8: | 195 | case 1: |
175 | return PIC_PCIE_LINK1_IRQ; | 196 | return PIC_PCIE_LINK1_IRQ; |
176 | case 0x10: | 197 | case 2: |
177 | if (nlm_chip_is_xls_b()) | 198 | if (nlm_chip_is_xls_b()) |
178 | return PIC_PCIE_XLSB0_LINK2_IRQ; | 199 | return PIC_PCIE_XLSB0_LINK2_IRQ; |
179 | else | 200 | else |
180 | return PIC_PCIE_LINK2_IRQ; | 201 | return PIC_PCIE_LINK2_IRQ; |
181 | case 0x18: | 202 | case 3: |
182 | if (nlm_chip_is_xls_b()) | 203 | if (nlm_chip_is_xls_b()) |
183 | return PIC_PCIE_XLSB0_LINK3_IRQ; | 204 | return PIC_PCIE_XLSB0_LINK3_IRQ; |
184 | else | 205 | else |
185 | return PIC_PCIE_LINK3_IRQ; | 206 | return PIC_PCIE_LINK3_IRQ; |
186 | } | 207 | } |
187 | WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn); | 208 | WARN(1, "Unexpected devfn %d\n", lnk->devfn); |
188 | return 0; | 209 | return 0; |
189 | } | 210 | } |
190 | 211 | ||
@@ -202,7 +223,27 @@ void arch_teardown_msi_irq(unsigned int irq) | |||
202 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) | 223 | int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) |
203 | { | 224 | { |
204 | struct msi_msg msg; | 225 | struct msi_msg msg; |
226 | struct pci_dev *lnk; | ||
205 | int irq, ret; | 227 | int irq, ret; |
228 | u16 val; | ||
229 | |||
230 | /* MSI not supported on XLR */ | ||
231 | if (!nlm_chip_is_xls()) | ||
232 | return 1; | ||
233 | |||
234 | /* | ||
235 | * Enable MSI on the XLS PCIe controller bridge which was disabled | ||
236 | * at enumeration, the bridge MSI capability is at 0x50 | ||
237 | */ | ||
238 | lnk = xls_get_pcie_link(dev); | ||
239 | if (lnk == NULL) | ||
240 | return 1; | ||
241 | |||
242 | pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); | ||
243 | if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { | ||
244 | val |= PCI_MSI_FLAGS_ENABLE; | ||
245 | pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); | ||
246 | } | ||
206 | 247 | ||
207 | irq = get_irq_vector(dev); | 248 | irq = get_irq_vector(dev); |
208 | if (irq <= 0) | 249 | if (irq <= 0) |
@@ -327,7 +368,7 @@ static int __init pcibios_init(void) | |||
327 | } | 368 | } |
328 | } else { | 369 | } else { |
329 | /* XLR PCI controller ACK */ | 370 | /* XLR PCI controller ACK */ |
330 | irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack); | 371 | irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack); |
331 | } | 372 | } |
332 | 373 | ||
333 | return 0; | 374 | return 0; |
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index b71fae231049..5edab2bc6fc0 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c | |||
@@ -115,11 +115,11 @@ static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action) | |||
115 | */ | 115 | */ |
116 | static void __cpuinit yos_init_secondary(void) | 116 | static void __cpuinit yos_init_secondary(void) |
117 | { | 117 | { |
118 | set_c0_status(ST0_CO | ST0_IE | ST0_IM); | ||
119 | } | 118 | } |
120 | 119 | ||
121 | static void __cpuinit yos_smp_finish(void) | 120 | static void __cpuinit yos_smp_finish(void) |
122 | { | 121 | { |
122 | set_c0_status(ST0_CO | ST0_IM | ST0_IE); | ||
123 | } | 123 | } |
124 | 124 | ||
125 | /* Hook for after all CPUs are online */ | 125 | /* Hook for after all CPUs are online */ |
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c index 0a170e0ffeaa..7773f3d956b0 100644 --- a/arch/mips/powertv/asic/asic-calliope.c +++ b/arch/mips/powertv/asic/asic-calliope.c | |||
@@ -28,7 +28,7 @@ | |||
28 | 28 | ||
29 | #define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) | 29 | #define CALLIOPE_ADDR(x) (CALLIOPE_IO_BASE + (x)) |
30 | 30 | ||
31 | const struct register_map calliope_register_map __initdata = { | 31 | const struct register_map calliope_register_map __initconst = { |
32 | .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, | 32 | .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)}, |
33 | .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, | 33 | .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)}, |
34 | .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)}, | 34 | .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)}, |
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c index bbc0c122be5e..da076db7b7ed 100644 --- a/arch/mips/powertv/asic/asic-cronus.c +++ b/arch/mips/powertv/asic/asic-cronus.c | |||
@@ -28,7 +28,7 @@ | |||
28 | 28 | ||
29 | #define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) | 29 | #define CRONUS_ADDR(x) (CRONUS_IO_BASE + (x)) |
30 | 30 | ||
31 | const struct register_map cronus_register_map __initdata = { | 31 | const struct register_map cronus_register_map __initconst = { |
32 | .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, | 32 | .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)}, |
33 | .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, | 33 | .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)}, |
34 | .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, | 34 | .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)}, |
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c index 91dda682752c..47683b370e74 100644 --- a/arch/mips/powertv/asic/asic-gaia.c +++ b/arch/mips/powertv/asic/asic-gaia.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
24 | #include <asm/mach-powertv/asic.h> | 24 | #include <asm/mach-powertv/asic.h> |
25 | 25 | ||
26 | const struct register_map gaia_register_map __initdata = { | 26 | const struct register_map gaia_register_map __initconst = { |
27 | .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, | 27 | .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000}, |
28 | .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, | 28 | .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038}, |
29 | .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, | 29 | .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C}, |
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c index 4a05bb096476..6ff4b10f09da 100644 --- a/arch/mips/powertv/asic/asic-zeus.c +++ b/arch/mips/powertv/asic/asic-zeus.c | |||
@@ -28,7 +28,7 @@ | |||
28 | 28 | ||
29 | #define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) | 29 | #define ZEUS_ADDR(x) (ZEUS_IO_BASE + (x)) |
30 | 30 | ||
31 | const struct register_map zeus_register_map __initdata = { | 31 | const struct register_map zeus_register_map __initconst = { |
32 | .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, | 32 | .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)}, |
33 | .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, | 33 | .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)}, |
34 | .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)}, | 34 | .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)}, |
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 682efb0c108d..64eb71b15280 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c | |||
@@ -269,7 +269,7 @@ txx9_i8259_irq_setup(int irq) | |||
269 | return err; | 269 | return err; |
270 | } | 270 | } |
271 | 271 | ||
272 | static void __init quirk_slc90e66_bridge(struct pci_dev *dev) | 272 | static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev) |
273 | { | 273 | { |
274 | int irq; /* PCI/ISA Bridge interrupt */ | 274 | int irq; /* PCI/ISA Bridge interrupt */ |
275 | u8 reg_64; | 275 | u8 reg_64; |
diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h index 55b79ef10028..44251b974f1d 100644 --- a/arch/mn10300/include/asm/ptrace.h +++ b/arch/mn10300/include/asm/ptrace.h | |||
@@ -81,9 +81,6 @@ struct pt_regs { | |||
81 | #define PTRACE_GETFPREGS 14 | 81 | #define PTRACE_GETFPREGS 14 |
82 | #define PTRACE_SETFPREGS 15 | 82 | #define PTRACE_SETFPREGS 15 |
83 | 83 | ||
84 | /* options set using PTRACE_SETOPTIONS */ | ||
85 | #define PTRACE_O_TRACESYSGOOD 0x00000001 | ||
86 | |||
87 | #ifdef __KERNEL__ | 84 | #ifdef __KERNEL__ |
88 | 85 | ||
89 | #define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) | 86 | #define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL) |
diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h index 08251d6f6b11..ac519bbd42ff 100644 --- a/arch/mn10300/include/asm/thread_info.h +++ b/arch/mn10300/include/asm/thread_info.h | |||
@@ -123,7 +123,7 @@ static inline unsigned long current_stack_pointer(void) | |||
123 | } | 123 | } |
124 | 124 | ||
125 | #ifndef CONFIG_KGDB | 125 | #ifndef CONFIG_KGDB |
126 | void arch_release_thread_info(struct thread_info *ti) | 126 | void arch_release_thread_info(struct thread_info *ti); |
127 | #endif | 127 | #endif |
128 | #define get_thread_info(ti) get_task_struct((ti)->task) | 128 | #define get_thread_info(ti) get_task_struct((ti)->task) |
129 | #define put_thread_info(ti) put_task_struct((ti)->task) | 129 | #define put_thread_info(ti) put_task_struct((ti)->task) |
diff --git a/arch/mn10300/include/asm/timex.h b/arch/mn10300/include/asm/timex.h index bd4e90dfe6c2..f8e66425cbf8 100644 --- a/arch/mn10300/include/asm/timex.h +++ b/arch/mn10300/include/asm/timex.h | |||
@@ -11,7 +11,6 @@ | |||
11 | #ifndef _ASM_TIMEX_H | 11 | #ifndef _ASM_TIMEX_H |
12 | #define _ASM_TIMEX_H | 12 | #define _ASM_TIMEX_H |
13 | 13 | ||
14 | #include <asm/hardirq.h> | ||
15 | #include <unit/timex.h> | 14 | #include <unit/timex.h> |
16 | 15 | ||
17 | #define TICK_SIZE (tick_nsec / 1000) | 16 | #define TICK_SIZE (tick_nsec / 1000) |
@@ -30,16 +29,6 @@ static inline cycles_t get_cycles(void) | |||
30 | extern int init_clockevents(void); | 29 | extern int init_clockevents(void); |
31 | extern int init_clocksource(void); | 30 | extern int init_clocksource(void); |
32 | 31 | ||
33 | static inline void setup_jiffies_interrupt(int irq, | ||
34 | struct irqaction *action) | ||
35 | { | ||
36 | u16 tmp; | ||
37 | setup_irq(irq, action); | ||
38 | set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL)); | ||
39 | GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; | ||
40 | tmp = GxICR(irq); | ||
41 | } | ||
42 | |||
43 | #endif /* __KERNEL__ */ | 32 | #endif /* __KERNEL__ */ |
44 | 33 | ||
45 | #endif /* _ASM_TIMEX_H */ | 34 | #endif /* _ASM_TIMEX_H */ |
diff --git a/arch/mn10300/kernel/cevt-mn10300.c b/arch/mn10300/kernel/cevt-mn10300.c index 69cae0260786..ccce35e3e179 100644 --- a/arch/mn10300/kernel/cevt-mn10300.c +++ b/arch/mn10300/kernel/cevt-mn10300.c | |||
@@ -70,6 +70,16 @@ static void event_handler(struct clock_event_device *dev) | |||
70 | { | 70 | { |
71 | } | 71 | } |
72 | 72 | ||
73 | static inline void setup_jiffies_interrupt(int irq, | ||
74 | struct irqaction *action) | ||
75 | { | ||
76 | u16 tmp; | ||
77 | setup_irq(irq, action); | ||
78 | set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL)); | ||
79 | GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST; | ||
80 | tmp = GxICR(irq); | ||
81 | } | ||
82 | |||
73 | int __init init_clockevents(void) | 83 | int __init init_clockevents(void) |
74 | { | 84 | { |
75 | struct clock_event_device *cd; | 85 | struct clock_event_device *cd; |
diff --git a/arch/mn10300/kernel/internal.h b/arch/mn10300/kernel/internal.h index a5ac755dd69f..2df440105a80 100644 --- a/arch/mn10300/kernel/internal.h +++ b/arch/mn10300/kernel/internal.h | |||
@@ -9,6 +9,8 @@ | |||
9 | * 2 of the Licence, or (at your option) any later version. | 9 | * 2 of the Licence, or (at your option) any later version. |
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/irqreturn.h> | ||
13 | |||
12 | struct clocksource; | 14 | struct clocksource; |
13 | struct clock_event_device; | 15 | struct clock_event_device; |
14 | 16 | ||
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c index 2381df83bd00..35932a8de8b8 100644 --- a/arch/mn10300/kernel/irq.c +++ b/arch/mn10300/kernel/irq.c | |||
@@ -170,9 +170,9 @@ mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask, | |||
170 | case SC1TXIRQ: | 170 | case SC1TXIRQ: |
171 | #ifdef CONFIG_MN10300_TTYSM1_TIMER12 | 171 | #ifdef CONFIG_MN10300_TTYSM1_TIMER12 |
172 | case TM12IRQ: | 172 | case TM12IRQ: |
173 | #elif CONFIG_MN10300_TTYSM1_TIMER9 | 173 | #elif defined(CONFIG_MN10300_TTYSM1_TIMER9) |
174 | case TM9IRQ: | 174 | case TM9IRQ: |
175 | #elif CONFIG_MN10300_TTYSM1_TIMER3 | 175 | #elif defined(CONFIG_MN10300_TTYSM1_TIMER3) |
176 | case TM3IRQ: | 176 | case TM3IRQ: |
177 | #endif /* CONFIG_MN10300_TTYSM1_TIMER12 */ | 177 | #endif /* CONFIG_MN10300_TTYSM1_TIMER12 */ |
178 | #endif /* CONFIG_MN10300_TTYSM1 */ | 178 | #endif /* CONFIG_MN10300_TTYSM1 */ |
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c index 6ab0bee2a54f..4d584ae29ae1 100644 --- a/arch/mn10300/kernel/signal.c +++ b/arch/mn10300/kernel/signal.c | |||
@@ -459,10 +459,11 @@ static int handle_signal(int sig, | |||
459 | else | 459 | else |
460 | ret = setup_frame(sig, ka, oldset, regs); | 460 | ret = setup_frame(sig, ka, oldset, regs); |
461 | if (ret) | 461 | if (ret) |
462 | return; | 462 | return ret; |
463 | 463 | ||
464 | signal_delivered(sig, info, ka, regs, | 464 | signal_delivered(sig, info, ka, regs, |
465 | test_thread_flag(TIF_SINGLESTEP)); | 465 | test_thread_flag(TIF_SINGLESTEP)); |
466 | return 0; | ||
466 | } | 467 | } |
467 | 468 | ||
468 | /* | 469 | /* |
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c index 090d35d36973..e62c223e4c45 100644 --- a/arch/mn10300/kernel/smp.c +++ b/arch/mn10300/kernel/smp.c | |||
@@ -876,9 +876,7 @@ static void __init smp_online(void) | |||
876 | 876 | ||
877 | notify_cpu_starting(cpu); | 877 | notify_cpu_starting(cpu); |
878 | 878 | ||
879 | ipi_call_lock(); | ||
880 | set_cpu_online(cpu, true); | 879 | set_cpu_online(cpu, true); |
881 | ipi_call_unlock(); | ||
882 | 880 | ||
883 | local_irq_enable(); | 881 | local_irq_enable(); |
884 | } | 882 | } |
diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c index 94a9c6d53e1b..b900e5afa0ae 100644 --- a/arch/mn10300/kernel/traps.c +++ b/arch/mn10300/kernel/traps.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/kdebug.h> | 26 | #include <linux/kdebug.h> |
27 | #include <linux/bug.h> | 27 | #include <linux/bug.h> |
28 | #include <linux/irq.h> | 28 | #include <linux/irq.h> |
29 | #include <linux/export.h> | ||
29 | #include <asm/processor.h> | 30 | #include <asm/processor.h> |
30 | #include <linux/uaccess.h> | 31 | #include <linux/uaccess.h> |
31 | #include <asm/io.h> | 32 | #include <asm/io.h> |
diff --git a/arch/mn10300/mm/dma-alloc.c b/arch/mn10300/mm/dma-alloc.c index 159acb02cfd4..e244ebe637e1 100644 --- a/arch/mn10300/mm/dma-alloc.c +++ b/arch/mn10300/mm/dma-alloc.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/string.h> | 15 | #include <linux/string.h> |
16 | #include <linux/pci.h> | 16 | #include <linux/pci.h> |
17 | #include <linux/gfp.h> | 17 | #include <linux/gfp.h> |
18 | #include <linux/export.h> | ||
18 | #include <asm/io.h> | 19 | #include <asm/io.h> |
19 | 20 | ||
20 | static unsigned long pci_sram_allocated = 0xbc000000; | 21 | static unsigned long pci_sram_allocated = 0xbc000000; |
diff --git a/arch/mn10300/unit-asb2303/include/unit/timex.h b/arch/mn10300/unit-asb2303/include/unit/timex.h index cc18fe7d8b90..c37f9832cf17 100644 --- a/arch/mn10300/unit-asb2303/include/unit/timex.h +++ b/arch/mn10300/unit-asb2303/include/unit/timex.h | |||
@@ -11,10 +11,6 @@ | |||
11 | #ifndef _ASM_UNIT_TIMEX_H | 11 | #ifndef _ASM_UNIT_TIMEX_H |
12 | #define _ASM_UNIT_TIMEX_H | 12 | #define _ASM_UNIT_TIMEX_H |
13 | 13 | ||
14 | #ifndef __ASSEMBLY__ | ||
15 | #include <linux/irq.h> | ||
16 | #endif /* __ASSEMBLY__ */ | ||
17 | |||
18 | #include <asm/timer-regs.h> | 14 | #include <asm/timer-regs.h> |
19 | #include <unit/clock.h> | 15 | #include <unit/clock.h> |
20 | #include <asm/param.h> | 16 | #include <asm/param.h> |
diff --git a/arch/mn10300/unit-asb2303/smc91111.c b/arch/mn10300/unit-asb2303/smc91111.c index 43c246439413..53677694b165 100644 --- a/arch/mn10300/unit-asb2303/smc91111.c +++ b/arch/mn10300/unit-asb2303/smc91111.c | |||
@@ -15,6 +15,7 @@ | |||
15 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
16 | 16 | ||
17 | #include <asm/io.h> | 17 | #include <asm/io.h> |
18 | #include <asm/irq.h> | ||
18 | #include <asm/timex.h> | 19 | #include <asm/timex.h> |
19 | #include <asm/processor.h> | 20 | #include <asm/processor.h> |
20 | #include <asm/intctl-regs.h> | 21 | #include <asm/intctl-regs.h> |
diff --git a/arch/mn10300/unit-asb2305/include/unit/timex.h b/arch/mn10300/unit-asb2305/include/unit/timex.h index 758af30d1a16..4cefc224f448 100644 --- a/arch/mn10300/unit-asb2305/include/unit/timex.h +++ b/arch/mn10300/unit-asb2305/include/unit/timex.h | |||
@@ -11,10 +11,6 @@ | |||
11 | #ifndef _ASM_UNIT_TIMEX_H | 11 | #ifndef _ASM_UNIT_TIMEX_H |
12 | #define _ASM_UNIT_TIMEX_H | 12 | #define _ASM_UNIT_TIMEX_H |
13 | 13 | ||
14 | #ifndef __ASSEMBLY__ | ||
15 | #include <linux/irq.h> | ||
16 | #endif /* __ASSEMBLY__ */ | ||
17 | |||
18 | #include <asm/timer-regs.h> | 14 | #include <asm/timer-regs.h> |
19 | #include <unit/clock.h> | 15 | #include <unit/clock.h> |
20 | #include <asm/param.h> | 16 | #include <asm/param.h> |
diff --git a/arch/mn10300/unit-asb2305/unit-init.c b/arch/mn10300/unit-asb2305/unit-init.c index e1becd6b7571..bc4adfaf815c 100644 --- a/arch/mn10300/unit-asb2305/unit-init.c +++ b/arch/mn10300/unit-asb2305/unit-init.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <linux/pci.h> | 14 | #include <linux/pci.h> |
15 | #include <asm/io.h> | 15 | #include <asm/io.h> |
16 | #include <asm/irq.h> | ||
16 | #include <asm/setup.h> | 17 | #include <asm/setup.h> |
17 | #include <asm/processor.h> | 18 | #include <asm/processor.h> |
18 | #include <asm/intctl-regs.h> | 19 | #include <asm/intctl-regs.h> |
diff --git a/arch/mn10300/unit-asb2364/include/unit/timex.h b/arch/mn10300/unit-asb2364/include/unit/timex.h index ddb7ed010706..42f32db75087 100644 --- a/arch/mn10300/unit-asb2364/include/unit/timex.h +++ b/arch/mn10300/unit-asb2364/include/unit/timex.h | |||
@@ -11,10 +11,6 @@ | |||
11 | #ifndef _ASM_UNIT_TIMEX_H | 11 | #ifndef _ASM_UNIT_TIMEX_H |
12 | #define _ASM_UNIT_TIMEX_H | 12 | #define _ASM_UNIT_TIMEX_H |
13 | 13 | ||
14 | #ifndef __ASSEMBLY__ | ||
15 | #include <linux/irq.h> | ||
16 | #endif /* __ASSEMBLY__ */ | ||
17 | |||
18 | #include <asm/timer-regs.h> | 14 | #include <asm/timer-regs.h> |
19 | #include <unit/clock.h> | 15 | #include <unit/clock.h> |
20 | #include <asm/param.h> | 16 | #include <asm/param.h> |
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c index a47828d31fe6..6266730efd61 100644 --- a/arch/parisc/kernel/smp.c +++ b/arch/parisc/kernel/smp.c | |||
@@ -300,9 +300,7 @@ smp_cpu_init(int cpunum) | |||
300 | 300 | ||
301 | notify_cpu_starting(cpunum); | 301 | notify_cpu_starting(cpunum); |
302 | 302 | ||
303 | ipi_call_lock(); | ||
304 | set_cpu_online(cpunum, true); | 303 | set_cpu_online(cpunum, true); |
305 | ipi_call_unlock(); | ||
306 | 304 | ||
307 | /* Initialise the idle task for this CPU */ | 305 | /* Initialise the idle task for this CPU */ |
308 | atomic_inc(&init_mm.mm_count); | 306 | atomic_inc(&init_mm.mm_count); |
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index 6eb75b80488c..0554ab062bdc 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h | |||
@@ -86,8 +86,8 @@ static inline bool arch_irqs_disabled(void) | |||
86 | } | 86 | } |
87 | 87 | ||
88 | #ifdef CONFIG_PPC_BOOK3E | 88 | #ifdef CONFIG_PPC_BOOK3E |
89 | #define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory"); | 89 | #define __hard_irq_enable() asm volatile("wrteei 1" : : : "memory") |
90 | #define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory"); | 90 | #define __hard_irq_disable() asm volatile("wrteei 0" : : : "memory") |
91 | #else | 91 | #else |
92 | #define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1) | 92 | #define __hard_irq_enable() __mtmsrd(local_paca->kernel_msr | MSR_EE, 1) |
93 | #define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1) | 93 | #define __hard_irq_disable() __mtmsrd(local_paca->kernel_msr, 1) |
@@ -125,6 +125,8 @@ static inline bool arch_irq_disabled_regs(struct pt_regs *regs) | |||
125 | return !regs->softe; | 125 | return !regs->softe; |
126 | } | 126 | } |
127 | 127 | ||
128 | extern bool prep_irq_for_idle(void); | ||
129 | |||
128 | #else /* CONFIG_PPC64 */ | 130 | #else /* CONFIG_PPC64 */ |
129 | 131 | ||
130 | #define SET_MSR_EE(x) mtmsr(x) | 132 | #define SET_MSR_EE(x) mtmsr(x) |
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c index 1b415027ec0e..1f017bb7a7ce 100644 --- a/arch/powerpc/kernel/irq.c +++ b/arch/powerpc/kernel/irq.c | |||
@@ -229,7 +229,7 @@ notrace void arch_local_irq_restore(unsigned long en) | |||
229 | */ | 229 | */ |
230 | if (unlikely(irq_happened != PACA_IRQ_HARD_DIS)) | 230 | if (unlikely(irq_happened != PACA_IRQ_HARD_DIS)) |
231 | __hard_irq_disable(); | 231 | __hard_irq_disable(); |
232 | #ifdef CONFIG_TRACE_IRQFLAG | 232 | #ifdef CONFIG_TRACE_IRQFLAGS |
233 | else { | 233 | else { |
234 | /* | 234 | /* |
235 | * We should already be hard disabled here. We had bugs | 235 | * We should already be hard disabled here. We had bugs |
@@ -286,6 +286,52 @@ void notrace restore_interrupts(void) | |||
286 | __hard_irq_enable(); | 286 | __hard_irq_enable(); |
287 | } | 287 | } |
288 | 288 | ||
289 | /* | ||
290 | * This is a helper to use when about to go into idle low-power | ||
291 | * when the latter has the side effect of re-enabling interrupts | ||
292 | * (such as calling H_CEDE under pHyp). | ||
293 | * | ||
294 | * You call this function with interrupts soft-disabled (this is | ||
295 | * already the case when ppc_md.power_save is called). The function | ||
296 | * will return whether to enter power save or just return. | ||
297 | * | ||
298 | * In the former case, it will have notified lockdep of interrupts | ||
299 | * being re-enabled and generally sanitized the lazy irq state, | ||
300 | * and in the latter case it will leave with interrupts hard | ||
301 | * disabled and marked as such, so the local_irq_enable() call | ||
302 | * in cpu_idle() will properly re-enable everything. | ||
303 | */ | ||
304 | bool prep_irq_for_idle(void) | ||
305 | { | ||
306 | /* | ||
307 | * First we need to hard disable to ensure no interrupt | ||
308 | * occurs before we effectively enter the low power state | ||
309 | */ | ||
310 | hard_irq_disable(); | ||
311 | |||
312 | /* | ||
313 | * If anything happened while we were soft-disabled, | ||
314 | * we return now and do not enter the low power state. | ||
315 | */ | ||
316 | if (lazy_irq_pending()) | ||
317 | return false; | ||
318 | |||
319 | /* Tell lockdep we are about to re-enable */ | ||
320 | trace_hardirqs_on(); | ||
321 | |||
322 | /* | ||
323 | * Mark interrupts as soft-enabled and clear the | ||
324 | * PACA_IRQ_HARD_DIS from the pending mask since we | ||
325 | * are about to hard enable as well as a side effect | ||
326 | * of entering the low power state. | ||
327 | */ | ||
328 | local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS; | ||
329 | local_paca->soft_enabled = 1; | ||
330 | |||
331 | /* Tell the caller to enter the low power state */ | ||
332 | return true; | ||
333 | } | ||
334 | |||
289 | #endif /* CONFIG_PPC64 */ | 335 | #endif /* CONFIG_PPC64 */ |
290 | 336 | ||
291 | int arch_show_interrupts(struct seq_file *p, int prec) | 337 | int arch_show_interrupts(struct seq_file *p, int prec) |
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index e4cb34322de4..e1417c42155c 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c | |||
@@ -571,7 +571,6 @@ void __devinit start_secondary(void *unused) | |||
571 | if (system_state == SYSTEM_RUNNING) | 571 | if (system_state == SYSTEM_RUNNING) |
572 | vdso_data->processorCount++; | 572 | vdso_data->processorCount++; |
573 | #endif | 573 | #endif |
574 | ipi_call_lock(); | ||
575 | notify_cpu_starting(cpu); | 574 | notify_cpu_starting(cpu); |
576 | set_cpu_online(cpu, true); | 575 | set_cpu_online(cpu, true); |
577 | /* Update sibling maps */ | 576 | /* Update sibling maps */ |
@@ -601,7 +600,6 @@ void __devinit start_secondary(void *unused) | |||
601 | of_node_put(np); | 600 | of_node_put(np); |
602 | } | 601 | } |
603 | of_node_put(l2_cache); | 602 | of_node_put(l2_cache); |
604 | ipi_call_unlock(); | ||
605 | 603 | ||
606 | local_irq_enable(); | 604 | local_irq_enable(); |
607 | 605 | ||
diff --git a/arch/powerpc/kvm/book3s_pr_papr.c b/arch/powerpc/kvm/book3s_pr_papr.c index 3ff9013d6e79..ee02b30878ed 100644 --- a/arch/powerpc/kvm/book3s_pr_papr.c +++ b/arch/powerpc/kvm/book3s_pr_papr.c | |||
@@ -241,6 +241,7 @@ int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd) | |||
241 | case H_PUT_TCE: | 241 | case H_PUT_TCE: |
242 | return kvmppc_h_pr_put_tce(vcpu); | 242 | return kvmppc_h_pr_put_tce(vcpu); |
243 | case H_CEDE: | 243 | case H_CEDE: |
244 | vcpu->arch.shared->msr |= MSR_EE; | ||
244 | kvm_vcpu_block(vcpu); | 245 | kvm_vcpu_block(vcpu); |
245 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); | 246 | clear_bit(KVM_REQ_UNHALT, &vcpu->requests); |
246 | vcpu->stat.halt_wakeup++; | 247 | vcpu->stat.halt_wakeup++; |
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 6e8f677f5646..1e95556dc692 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c | |||
@@ -639,7 +639,7 @@ static void __init parse_drconf_memory(struct device_node *memory) | |||
639 | unsigned int n, rc, ranges, is_kexec_kdump = 0; | 639 | unsigned int n, rc, ranges, is_kexec_kdump = 0; |
640 | unsigned long lmb_size, base, size, sz; | 640 | unsigned long lmb_size, base, size, sz; |
641 | int nid; | 641 | int nid; |
642 | struct assoc_arrays aa; | 642 | struct assoc_arrays aa = { .arrays = NULL }; |
643 | 643 | ||
644 | n = of_get_drconf_memory(memory, &dm); | 644 | n = of_get_drconf_memory(memory, &dm); |
645 | if (!n) | 645 | if (!n) |
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c index efdacc829576..d17e98bc0c10 100644 --- a/arch/powerpc/platforms/cell/pervasive.c +++ b/arch/powerpc/platforms/cell/pervasive.c | |||
@@ -42,11 +42,9 @@ static void cbe_power_save(void) | |||
42 | { | 42 | { |
43 | unsigned long ctrl, thread_switch_control; | 43 | unsigned long ctrl, thread_switch_control; |
44 | 44 | ||
45 | /* | 45 | /* Ensure our interrupt state is properly tracked */ |
46 | * We need to hard disable interrupts, the local_irq_enable() done by | 46 | if (!prep_irq_for_idle()) |
47 | * our caller upon return will hard re-enable. | 47 | return; |
48 | */ | ||
49 | hard_irq_disable(); | ||
50 | 48 | ||
51 | ctrl = mfspr(SPRN_CTRLF); | 49 | ctrl = mfspr(SPRN_CTRLF); |
52 | 50 | ||
@@ -81,6 +79,9 @@ static void cbe_power_save(void) | |||
81 | */ | 79 | */ |
82 | ctrl &= ~(CTRL_RUNLATCH | CTRL_TE); | 80 | ctrl &= ~(CTRL_RUNLATCH | CTRL_TE); |
83 | mtspr(SPRN_CTRLT, ctrl); | 81 | mtspr(SPRN_CTRLT, ctrl); |
82 | |||
83 | /* Re-enable interrupts in MSR */ | ||
84 | __hard_irq_enable(); | ||
84 | } | 85 | } |
85 | 86 | ||
86 | static int cbe_system_reset_exception(struct pt_regs *regs) | 87 | static int cbe_system_reset_exception(struct pt_regs *regs) |
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c index 66519d263da7..d544d7816df3 100644 --- a/arch/powerpc/platforms/cell/spufs/inode.c +++ b/arch/powerpc/platforms/cell/spufs/inode.c | |||
@@ -317,28 +317,23 @@ out: | |||
317 | return ret; | 317 | return ret; |
318 | } | 318 | } |
319 | 319 | ||
320 | static int spufs_context_open(struct dentry *dentry, struct vfsmount *mnt) | 320 | static int spufs_context_open(struct path *path) |
321 | { | 321 | { |
322 | int ret; | 322 | int ret; |
323 | struct file *filp; | 323 | struct file *filp; |
324 | 324 | ||
325 | ret = get_unused_fd(); | 325 | ret = get_unused_fd(); |
326 | if (ret < 0) { | 326 | if (ret < 0) |
327 | dput(dentry); | 327 | return ret; |
328 | mntput(mnt); | ||
329 | goto out; | ||
330 | } | ||
331 | 328 | ||
332 | filp = dentry_open(dentry, mnt, O_RDONLY, current_cred()); | 329 | filp = dentry_open(path, O_RDONLY, current_cred()); |
333 | if (IS_ERR(filp)) { | 330 | if (IS_ERR(filp)) { |
334 | put_unused_fd(ret); | 331 | put_unused_fd(ret); |
335 | ret = PTR_ERR(filp); | 332 | return PTR_ERR(filp); |
336 | goto out; | ||
337 | } | 333 | } |
338 | 334 | ||
339 | filp->f_op = &spufs_context_fops; | 335 | filp->f_op = &spufs_context_fops; |
340 | fd_install(ret, filp); | 336 | fd_install(ret, filp); |
341 | out: | ||
342 | return ret; | 337 | return ret; |
343 | } | 338 | } |
344 | 339 | ||
@@ -453,6 +448,7 @@ spufs_create_context(struct inode *inode, struct dentry *dentry, | |||
453 | int affinity; | 448 | int affinity; |
454 | struct spu_gang *gang; | 449 | struct spu_gang *gang; |
455 | struct spu_context *neighbor; | 450 | struct spu_context *neighbor; |
451 | struct path path = {.mnt = mnt, .dentry = dentry}; | ||
456 | 452 | ||
457 | ret = -EPERM; | 453 | ret = -EPERM; |
458 | if ((flags & SPU_CREATE_NOSCHED) && | 454 | if ((flags & SPU_CREATE_NOSCHED) && |
@@ -495,11 +491,7 @@ spufs_create_context(struct inode *inode, struct dentry *dentry, | |||
495 | put_spu_context(neighbor); | 491 | put_spu_context(neighbor); |
496 | } | 492 | } |
497 | 493 | ||
498 | /* | 494 | ret = spufs_context_open(&path); |
499 | * get references for dget and mntget, will be released | ||
500 | * in error path of *_open(). | ||
501 | */ | ||
502 | ret = spufs_context_open(dget(dentry), mntget(mnt)); | ||
503 | if (ret < 0) { | 495 | if (ret < 0) { |
504 | WARN_ON(spufs_rmdir(inode, dentry)); | 496 | WARN_ON(spufs_rmdir(inode, dentry)); |
505 | if (affinity) | 497 | if (affinity) |
@@ -556,28 +548,27 @@ out: | |||
556 | return ret; | 548 | return ret; |
557 | } | 549 | } |
558 | 550 | ||
559 | static int spufs_gang_open(struct dentry *dentry, struct vfsmount *mnt) | 551 | static int spufs_gang_open(struct path *path) |
560 | { | 552 | { |
561 | int ret; | 553 | int ret; |
562 | struct file *filp; | 554 | struct file *filp; |
563 | 555 | ||
564 | ret = get_unused_fd(); | 556 | ret = get_unused_fd(); |
565 | if (ret < 0) { | 557 | if (ret < 0) |
566 | dput(dentry); | 558 | return ret; |
567 | mntput(mnt); | ||
568 | goto out; | ||
569 | } | ||
570 | 559 | ||
571 | filp = dentry_open(dentry, mnt, O_RDONLY, current_cred()); | 560 | /* |
561 | * get references for dget and mntget, will be released | ||
562 | * in error path of *_open(). | ||
563 | */ | ||
564 | filp = dentry_open(path, O_RDONLY, current_cred()); | ||
572 | if (IS_ERR(filp)) { | 565 | if (IS_ERR(filp)) { |
573 | put_unused_fd(ret); | 566 | put_unused_fd(ret); |
574 | ret = PTR_ERR(filp); | 567 | return PTR_ERR(filp); |
575 | goto out; | ||
576 | } | 568 | } |
577 | 569 | ||
578 | filp->f_op = &simple_dir_operations; | 570 | filp->f_op = &simple_dir_operations; |
579 | fd_install(ret, filp); | 571 | fd_install(ret, filp); |
580 | out: | ||
581 | return ret; | 572 | return ret; |
582 | } | 573 | } |
583 | 574 | ||
@@ -585,17 +576,14 @@ static int spufs_create_gang(struct inode *inode, | |||
585 | struct dentry *dentry, | 576 | struct dentry *dentry, |
586 | struct vfsmount *mnt, umode_t mode) | 577 | struct vfsmount *mnt, umode_t mode) |
587 | { | 578 | { |
579 | struct path path = {.mnt = mnt, .dentry = dentry}; | ||
588 | int ret; | 580 | int ret; |
589 | 581 | ||
590 | ret = spufs_mkgang(inode, dentry, mode & S_IRWXUGO); | 582 | ret = spufs_mkgang(inode, dentry, mode & S_IRWXUGO); |
591 | if (ret) | 583 | if (ret) |
592 | goto out; | 584 | goto out; |
593 | 585 | ||
594 | /* | 586 | ret = spufs_gang_open(&path); |
595 | * get references for dget and mntget, will be released | ||
596 | * in error path of *_open(). | ||
597 | */ | ||
598 | ret = spufs_gang_open(dget(dentry), mntget(mnt)); | ||
599 | if (ret < 0) { | 587 | if (ret < 0) { |
600 | int err = simple_rmdir(inode, dentry); | 588 | int err = simple_rmdir(inode, dentry); |
601 | WARN_ON(err); | 589 | WARN_ON(err); |
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c index e61483e8e960..c71be66bd5dc 100644 --- a/arch/powerpc/platforms/pseries/processor_idle.c +++ b/arch/powerpc/platforms/pseries/processor_idle.c | |||
@@ -99,15 +99,18 @@ out: | |||
99 | static void check_and_cede_processor(void) | 99 | static void check_and_cede_processor(void) |
100 | { | 100 | { |
101 | /* | 101 | /* |
102 | * Interrupts are soft-disabled at this point, | 102 | * Ensure our interrupt state is properly tracked, |
103 | * but not hard disabled. So an interrupt might have | 103 | * also checks if no interrupt has occurred while we |
104 | * occurred before entering NAP, and would be potentially | 104 | * were soft-disabled |
105 | * lost (edge events, decrementer events, etc...) unless | ||
106 | * we first hard disable then check. | ||
107 | */ | 105 | */ |
108 | hard_irq_disable(); | 106 | if (prep_irq_for_idle()) { |
109 | if (!lazy_irq_pending()) | ||
110 | cede_processor(); | 107 | cede_processor(); |
108 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
109 | /* Ensure that H_CEDE returns with IRQs on */ | ||
110 | if (WARN_ON(!(mfmsr() & MSR_EE))) | ||
111 | __hard_irq_enable(); | ||
112 | #endif | ||
113 | } | ||
111 | } | 114 | } |
112 | 115 | ||
113 | static int dedicated_cede_loop(struct cpuidle_device *dev, | 116 | static int dedicated_cede_loop(struct cpuidle_device *dev, |
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index 15cca26ccb6c..8dca9c248ac7 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c | |||
@@ -717,9 +717,7 @@ static void __cpuinit smp_start_secondary(void *cpuvoid) | |||
717 | init_cpu_vtimer(); | 717 | init_cpu_vtimer(); |
718 | pfault_init(); | 718 | pfault_init(); |
719 | notify_cpu_starting(smp_processor_id()); | 719 | notify_cpu_starting(smp_processor_id()); |
720 | ipi_call_lock(); | ||
721 | set_cpu_online(smp_processor_id(), true); | 720 | set_cpu_online(smp_processor_id(), true); |
722 | ipi_call_unlock(); | ||
723 | local_irq_enable(); | 721 | local_irq_enable(); |
724 | /* cpu_idle will call schedule for us */ | 722 | /* cpu_idle will call schedule for us */ |
725 | cpu_idle(); | 723 | cpu_idle(); |
diff --git a/arch/sh/include/asm/io_noioport.h b/arch/sh/include/asm/io_noioport.h index e136d28d1d2e..4d48f1436a63 100644 --- a/arch/sh/include/asm/io_noioport.h +++ b/arch/sh/include/asm/io_noioport.h | |||
@@ -19,9 +19,20 @@ static inline u32 inl(unsigned long addr) | |||
19 | return -1; | 19 | return -1; |
20 | } | 20 | } |
21 | 21 | ||
22 | #define outb(x, y) BUG() | 22 | static inline void outb(unsigned char x, unsigned long port) |
23 | #define outw(x, y) BUG() | 23 | { |
24 | #define outl(x, y) BUG() | 24 | BUG(); |
25 | } | ||
26 | |||
27 | static inline void outw(unsigned short x, unsigned long port) | ||
28 | { | ||
29 | BUG(); | ||
30 | } | ||
31 | |||
32 | static inline void outl(unsigned int x, unsigned long port) | ||
33 | { | ||
34 | BUG(); | ||
35 | } | ||
25 | 36 | ||
26 | #define inb_p(addr) inb(addr) | 37 | #define inb_p(addr) inb(addr) |
27 | #define inw_p(addr) inw(addr) | 38 | #define inw_p(addr) inw(addr) |
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7720.c b/arch/sh/kernel/cpu/sh3/serial-sh7720.c index 8832c526cdf9..c4a0336660dd 100644 --- a/arch/sh/kernel/cpu/sh3/serial-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/serial-sh7720.c | |||
@@ -2,7 +2,7 @@ | |||
2 | #include <linux/serial_core.h> | 2 | #include <linux/serial_core.h> |
3 | #include <linux/io.h> | 3 | #include <linux/io.h> |
4 | #include <cpu/serial.h> | 4 | #include <cpu/serial.h> |
5 | #include <asm/gpio.h> | 5 | #include <cpu/gpio.h> |
6 | 6 | ||
7 | static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag) | 7 | static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag) |
8 | { | 8 | { |
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c index f591598d92f6..781bcb10b8bd 100644 --- a/arch/sparc/kernel/smp_64.c +++ b/arch/sparc/kernel/smp_64.c | |||
@@ -103,8 +103,6 @@ void __cpuinit smp_callin(void) | |||
103 | if (cheetah_pcache_forced_on) | 103 | if (cheetah_pcache_forced_on) |
104 | cheetah_enable_pcache(); | 104 | cheetah_enable_pcache(); |
105 | 105 | ||
106 | local_irq_enable(); | ||
107 | |||
108 | callin_flag = 1; | 106 | callin_flag = 1; |
109 | __asm__ __volatile__("membar #Sync\n\t" | 107 | __asm__ __volatile__("membar #Sync\n\t" |
110 | "flush %%g6" : : : "memory"); | 108 | "flush %%g6" : : : "memory"); |
@@ -124,9 +122,8 @@ void __cpuinit smp_callin(void) | |||
124 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) | 122 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
125 | rmb(); | 123 | rmb(); |
126 | 124 | ||
127 | ipi_call_lock_irq(); | ||
128 | set_cpu_online(cpuid, true); | 125 | set_cpu_online(cpuid, true); |
129 | ipi_call_unlock_irq(); | 126 | local_irq_enable(); |
130 | 127 | ||
131 | /* idle thread is expected to have preempt disabled */ | 128 | /* idle thread is expected to have preempt disabled */ |
132 | preempt_disable(); | 129 | preempt_disable(); |
@@ -1308,9 +1305,7 @@ int __cpu_disable(void) | |||
1308 | mdelay(1); | 1305 | mdelay(1); |
1309 | local_irq_disable(); | 1306 | local_irq_disable(); |
1310 | 1307 | ||
1311 | ipi_call_lock(); | ||
1312 | set_cpu_online(cpu, false); | 1308 | set_cpu_online(cpu, false); |
1313 | ipi_call_unlock(); | ||
1314 | 1309 | ||
1315 | cpu_map_rebuild(); | 1310 | cpu_map_rebuild(); |
1316 | 1311 | ||
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c index 9092ce8aa6b4..f8b74ca83b92 100644 --- a/arch/tile/kernel/backtrace.c +++ b/arch/tile/kernel/backtrace.c | |||
@@ -14,6 +14,7 @@ | |||
14 | 14 | ||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/string.h> | 16 | #include <linux/string.h> |
17 | #include <asm/byteorder.h> | ||
17 | #include <asm/backtrace.h> | 18 | #include <asm/backtrace.h> |
18 | #include <asm/tile-desc.h> | 19 | #include <asm/tile-desc.h> |
19 | #include <arch/abi.h> | 20 | #include <arch/abi.h> |
@@ -336,8 +337,12 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location, | |||
336 | bytes_to_prefetch / sizeof(tile_bundle_bits); | 337 | bytes_to_prefetch / sizeof(tile_bundle_bits); |
337 | } | 338 | } |
338 | 339 | ||
339 | /* Decode the next bundle. */ | 340 | /* |
340 | bundle.bits = prefetched_bundles[next_bundle++]; | 341 | * Decode the next bundle. |
342 | * TILE always stores instruction bundles in little-endian | ||
343 | * mode, even when the chip is running in big-endian mode. | ||
344 | */ | ||
345 | bundle.bits = le64_to_cpu(prefetched_bundles[next_bundle++]); | ||
341 | bundle.num_insns = | 346 | bundle.num_insns = |
342 | parse_insn_tile(bundle.bits, pc, bundle.insns); | 347 | parse_insn_tile(bundle.bits, pc, bundle.insns); |
343 | num_info_ops = bt_get_info_ops(&bundle, info_operands); | 348 | num_info_ops = bt_get_info_ops(&bundle, info_operands); |
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c index 84873fbe8f27..e686c5ac90be 100644 --- a/arch/tile/kernel/smpboot.c +++ b/arch/tile/kernel/smpboot.c | |||
@@ -198,17 +198,7 @@ void __cpuinit online_secondary(void) | |||
198 | 198 | ||
199 | notify_cpu_starting(smp_processor_id()); | 199 | notify_cpu_starting(smp_processor_id()); |
200 | 200 | ||
201 | /* | ||
202 | * We need to hold call_lock, so there is no inconsistency | ||
203 | * between the time smp_call_function() determines number of | ||
204 | * IPI recipients, and the time when the determination is made | ||
205 | * for which cpus receive the IPI. Holding this | ||
206 | * lock helps us to not include this cpu in a currently in progress | ||
207 | * smp_call_function(). | ||
208 | */ | ||
209 | ipi_call_lock(); | ||
210 | set_cpu_online(smp_processor_id(), 1); | 201 | set_cpu_online(smp_processor_id(), 1); |
211 | ipi_call_unlock(); | ||
212 | __get_cpu_var(cpu_state) = CPU_ONLINE; | 202 | __get_cpu_var(cpu_state) = CPU_ONLINE; |
213 | 203 | ||
214 | /* Set up tile-specific state for this cpu. */ | 204 | /* Set up tile-specific state for this cpu. */ |
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c index 88e466b159dc..43b39d61b538 100644 --- a/arch/um/drivers/mconsole_kern.c +++ b/arch/um/drivers/mconsole_kern.c | |||
@@ -705,7 +705,6 @@ static void stack_proc(void *arg) | |||
705 | struct task_struct *from = current, *to = arg; | 705 | struct task_struct *from = current, *to = arg; |
706 | 706 | ||
707 | to->thread.saved_task = from; | 707 | to->thread.saved_task = from; |
708 | rcu_switch_from(from); | ||
709 | switch_to(from, to, from); | 708 | switch_to(from, to, from); |
710 | } | 709 | } |
711 | 710 | ||
diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 1f2521434554..b0c5276861ec 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile | |||
@@ -49,6 +49,9 @@ else | |||
49 | KBUILD_AFLAGS += -m64 | 49 | KBUILD_AFLAGS += -m64 |
50 | KBUILD_CFLAGS += -m64 | 50 | KBUILD_CFLAGS += -m64 |
51 | 51 | ||
52 | # Use -mpreferred-stack-boundary=3 if supported. | ||
53 | KBUILD_CFLAGS += $(call cc-option,-mno-sse -mpreferred-stack-boundary=3) | ||
54 | |||
52 | # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) | 55 | # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu) |
53 | cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) | 56 | cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8) |
54 | cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) | 57 | cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona) |
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h index 49331bedc158..70780689599a 100644 --- a/arch/x86/include/asm/alternative.h +++ b/arch/x86/include/asm/alternative.h | |||
@@ -75,23 +75,54 @@ static inline int alternatives_text_reserved(void *start, void *end) | |||
75 | } | 75 | } |
76 | #endif /* CONFIG_SMP */ | 76 | #endif /* CONFIG_SMP */ |
77 | 77 | ||
78 | #define OLDINSTR(oldinstr) "661:\n\t" oldinstr "\n662:\n" | ||
79 | |||
80 | #define b_replacement(number) "663"#number | ||
81 | #define e_replacement(number) "664"#number | ||
82 | |||
83 | #define alt_slen "662b-661b" | ||
84 | #define alt_rlen(number) e_replacement(number)"f-"b_replacement(number)"f" | ||
85 | |||
86 | #define ALTINSTR_ENTRY(feature, number) \ | ||
87 | " .long 661b - .\n" /* label */ \ | ||
88 | " .long " b_replacement(number)"f - .\n" /* new instruction */ \ | ||
89 | " .word " __stringify(feature) "\n" /* feature bit */ \ | ||
90 | " .byte " alt_slen "\n" /* source len */ \ | ||
91 | " .byte " alt_rlen(number) "\n" /* replacement len */ | ||
92 | |||
93 | #define DISCARD_ENTRY(number) /* rlen <= slen */ \ | ||
94 | " .byte 0xff + (" alt_rlen(number) ") - (" alt_slen ")\n" | ||
95 | |||
96 | #define ALTINSTR_REPLACEMENT(newinstr, feature, number) /* replacement */ \ | ||
97 | b_replacement(number)":\n\t" newinstr "\n" e_replacement(number) ":\n\t" | ||
98 | |||
78 | /* alternative assembly primitive: */ | 99 | /* alternative assembly primitive: */ |
79 | #define ALTERNATIVE(oldinstr, newinstr, feature) \ | 100 | #define ALTERNATIVE(oldinstr, newinstr, feature) \ |
80 | \ | 101 | OLDINSTR(oldinstr) \ |
81 | "661:\n\t" oldinstr "\n662:\n" \ | 102 | ".section .altinstructions,\"a\"\n" \ |
82 | ".section .altinstructions,\"a\"\n" \ | 103 | ALTINSTR_ENTRY(feature, 1) \ |
83 | " .long 661b - .\n" /* label */ \ | 104 | ".previous\n" \ |
84 | " .long 663f - .\n" /* new instruction */ \ | 105 | ".section .discard,\"aw\",@progbits\n" \ |
85 | " .word " __stringify(feature) "\n" /* feature bit */ \ | 106 | DISCARD_ENTRY(1) \ |
86 | " .byte 662b-661b\n" /* sourcelen */ \ | 107 | ".previous\n" \ |
87 | " .byte 664f-663f\n" /* replacementlen */ \ | 108 | ".section .altinstr_replacement, \"ax\"\n" \ |
88 | ".previous\n" \ | 109 | ALTINSTR_REPLACEMENT(newinstr, feature, 1) \ |
89 | ".section .discard,\"aw\",@progbits\n" \ | 110 | ".previous" |
90 | " .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */ \ | 111 | |
91 | ".previous\n" \ | 112 | #define ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, feature2)\ |
92 | ".section .altinstr_replacement, \"ax\"\n" \ | 113 | OLDINSTR(oldinstr) \ |
93 | "663:\n\t" newinstr "\n664:\n" /* replacement */ \ | 114 | ".section .altinstructions,\"a\"\n" \ |
94 | ".previous" | 115 | ALTINSTR_ENTRY(feature1, 1) \ |
116 | ALTINSTR_ENTRY(feature2, 2) \ | ||
117 | ".previous\n" \ | ||
118 | ".section .discard,\"aw\",@progbits\n" \ | ||
119 | DISCARD_ENTRY(1) \ | ||
120 | DISCARD_ENTRY(2) \ | ||
121 | ".previous\n" \ | ||
122 | ".section .altinstr_replacement, \"ax\"\n" \ | ||
123 | ALTINSTR_REPLACEMENT(newinstr1, feature1, 1) \ | ||
124 | ALTINSTR_REPLACEMENT(newinstr2, feature2, 2) \ | ||
125 | ".previous" | ||
95 | 126 | ||
96 | /* | 127 | /* |
97 | * This must be included *after* the definition of ALTERNATIVE due to | 128 | * This must be included *after* the definition of ALTERNATIVE due to |
@@ -140,6 +171,19 @@ static inline int alternatives_text_reserved(void *start, void *end) | |||
140 | : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input) | 171 | : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input) |
141 | 172 | ||
142 | /* | 173 | /* |
174 | * Like alternative_call, but there are two features and respective functions. | ||
175 | * If CPU has feature2, function2 is used. | ||
176 | * Otherwise, if CPU has feature1, function1 is used. | ||
177 | * Otherwise, old function is used. | ||
178 | */ | ||
179 | #define alternative_call_2(oldfunc, newfunc1, feature1, newfunc2, feature2, \ | ||
180 | output, input...) \ | ||
181 | asm volatile (ALTERNATIVE_2("call %P[old]", "call %P[new1]", feature1,\ | ||
182 | "call %P[new2]", feature2) \ | ||
183 | : output : [old] "i" (oldfunc), [new1] "i" (newfunc1), \ | ||
184 | [new2] "i" (newfunc2), ## input) | ||
185 | |||
186 | /* | ||
143 | * use this macro(s) if you need more than one output parameter | 187 | * use this macro(s) if you need more than one output parameter |
144 | * in alternative_io | 188 | * in alternative_io |
145 | */ | 189 | */ |
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 49ad773f4b9f..b3341e9cd8fd 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h | |||
@@ -26,10 +26,31 @@ struct amd_l3_cache { | |||
26 | u8 subcaches[4]; | 26 | u8 subcaches[4]; |
27 | }; | 27 | }; |
28 | 28 | ||
29 | struct threshold_block { | ||
30 | unsigned int block; | ||
31 | unsigned int bank; | ||
32 | unsigned int cpu; | ||
33 | u32 address; | ||
34 | u16 interrupt_enable; | ||
35 | bool interrupt_capable; | ||
36 | u16 threshold_limit; | ||
37 | struct kobject kobj; | ||
38 | struct list_head miscj; | ||
39 | }; | ||
40 | |||
41 | struct threshold_bank { | ||
42 | struct kobject *kobj; | ||
43 | struct threshold_block *blocks; | ||
44 | |||
45 | /* initialized to the number of CPUs on the node sharing this bank */ | ||
46 | atomic_t cpus; | ||
47 | }; | ||
48 | |||
29 | struct amd_northbridge { | 49 | struct amd_northbridge { |
30 | struct pci_dev *misc; | 50 | struct pci_dev *misc; |
31 | struct pci_dev *link; | 51 | struct pci_dev *link; |
32 | struct amd_l3_cache l3_cache; | 52 | struct amd_l3_cache l3_cache; |
53 | struct threshold_bank *bank4; | ||
33 | }; | 54 | }; |
34 | 55 | ||
35 | struct amd_northbridge_info { | 56 | struct amd_northbridge_info { |
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index eaff4790ed96..88093c1d44fd 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h | |||
@@ -306,7 +306,8 @@ struct apic { | |||
306 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); | 306 | unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); |
307 | unsigned long (*check_apicid_present)(int apicid); | 307 | unsigned long (*check_apicid_present)(int apicid); |
308 | 308 | ||
309 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); | 309 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, |
310 | const struct cpumask *mask); | ||
310 | void (*init_apic_ldr)(void); | 311 | void (*init_apic_ldr)(void); |
311 | 312 | ||
312 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); | 313 | void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); |
@@ -331,9 +332,9 @@ struct apic { | |||
331 | unsigned long (*set_apic_id)(unsigned int id); | 332 | unsigned long (*set_apic_id)(unsigned int id); |
332 | unsigned long apic_id_mask; | 333 | unsigned long apic_id_mask; |
333 | 334 | ||
334 | unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); | 335 | int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, |
335 | unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, | 336 | const struct cpumask *andmask, |
336 | const struct cpumask *andmask); | 337 | unsigned int *apicid); |
337 | 338 | ||
338 | /* ipi */ | 339 | /* ipi */ |
339 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | 340 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); |
@@ -537,6 +538,11 @@ static inline const struct cpumask *default_target_cpus(void) | |||
537 | #endif | 538 | #endif |
538 | } | 539 | } |
539 | 540 | ||
541 | static inline const struct cpumask *online_target_cpus(void) | ||
542 | { | ||
543 | return cpu_online_mask; | ||
544 | } | ||
545 | |||
540 | DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); | 546 | DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); |
541 | 547 | ||
542 | 548 | ||
@@ -586,21 +592,50 @@ static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) | |||
586 | 592 | ||
587 | #endif | 593 | #endif |
588 | 594 | ||
589 | static inline unsigned int | 595 | static inline int |
590 | default_cpu_mask_to_apicid(const struct cpumask *cpumask) | 596 | flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
597 | const struct cpumask *andmask, | ||
598 | unsigned int *apicid) | ||
591 | { | 599 | { |
592 | return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS; | 600 | unsigned long cpu_mask = cpumask_bits(cpumask)[0] & |
601 | cpumask_bits(andmask)[0] & | ||
602 | cpumask_bits(cpu_online_mask)[0] & | ||
603 | APIC_ALL_CPUS; | ||
604 | |||
605 | if (likely(cpu_mask)) { | ||
606 | *apicid = (unsigned int)cpu_mask; | ||
607 | return 0; | ||
608 | } else { | ||
609 | return -EINVAL; | ||
610 | } | ||
593 | } | 611 | } |
594 | 612 | ||
595 | static inline unsigned int | 613 | extern int |
596 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | 614 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
597 | const struct cpumask *andmask) | 615 | const struct cpumask *andmask, |
616 | unsigned int *apicid); | ||
617 | |||
618 | static inline void | ||
619 | flat_vector_allocation_domain(int cpu, struct cpumask *retmask, | ||
620 | const struct cpumask *mask) | ||
598 | { | 621 | { |
599 | unsigned long mask1 = cpumask_bits(cpumask)[0]; | 622 | /* Careful. Some cpus do not strictly honor the set of cpus |
600 | unsigned long mask2 = cpumask_bits(andmask)[0]; | 623 | * specified in the interrupt destination when using lowest |
601 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; | 624 | * priority interrupt delivery mode. |
625 | * | ||
626 | * In particular there was a hyperthreading cpu observed to | ||
627 | * deliver interrupts to the wrong hyperthread when only one | ||
628 | * hyperthread was specified in the interrupt desitination. | ||
629 | */ | ||
630 | cpumask_clear(retmask); | ||
631 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
632 | } | ||
602 | 633 | ||
603 | return (unsigned int)(mask1 & mask2 & mask3); | 634 | static inline void |
635 | default_vector_allocation_domain(int cpu, struct cpumask *retmask, | ||
636 | const struct cpumask *mask) | ||
637 | { | ||
638 | cpumask_copy(retmask, cpumask_of(cpu)); | ||
604 | } | 639 | } |
605 | 640 | ||
606 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) | 641 | static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid) |
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h index cc70c1c78ca4..75ce3f47d204 100644 --- a/arch/x86/include/asm/emergency-restart.h +++ b/arch/x86/include/asm/emergency-restart.h | |||
@@ -4,9 +4,7 @@ | |||
4 | enum reboot_type { | 4 | enum reboot_type { |
5 | BOOT_TRIPLE = 't', | 5 | BOOT_TRIPLE = 't', |
6 | BOOT_KBD = 'k', | 6 | BOOT_KBD = 'k', |
7 | #ifdef CONFIG_X86_32 | ||
8 | BOOT_BIOS = 'b', | 7 | BOOT_BIOS = 'b', |
9 | #endif | ||
10 | BOOT_ACPI = 'a', | 8 | BOOT_ACPI = 'a', |
11 | BOOT_EFI = 'e', | 9 | BOOT_EFI = 'e', |
12 | BOOT_CF9 = 'p', | 10 | BOOT_CF9 = 'p', |
diff --git a/arch/x86/include/asm/floppy.h b/arch/x86/include/asm/floppy.h index dbe82a5c5eac..d3d74698dce9 100644 --- a/arch/x86/include/asm/floppy.h +++ b/arch/x86/include/asm/floppy.h | |||
@@ -99,7 +99,7 @@ static irqreturn_t floppy_hardint(int irq, void *dev_id) | |||
99 | virtual_dma_residue += virtual_dma_count; | 99 | virtual_dma_residue += virtual_dma_count; |
100 | virtual_dma_count = 0; | 100 | virtual_dma_count = 0; |
101 | #ifdef TRACE_FLPY_INT | 101 | #ifdef TRACE_FLPY_INT |
102 | printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", | 102 | printk(KERN_DEBUG "count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", |
103 | virtual_dma_count, virtual_dma_residue, calls, bytes, | 103 | virtual_dma_count, virtual_dma_residue, calls, bytes, |
104 | dma_wait); | 104 | dma_wait); |
105 | calls = 0; | 105 | calls = 0; |
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index db7c1f2709a2..2da88c0cda14 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h | |||
@@ -313,8 +313,8 @@ struct kvm_pmu { | |||
313 | u64 counter_bitmask[2]; | 313 | u64 counter_bitmask[2]; |
314 | u64 global_ctrl_mask; | 314 | u64 global_ctrl_mask; |
315 | u8 version; | 315 | u8 version; |
316 | struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC]; | 316 | struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC]; |
317 | struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED]; | 317 | struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED]; |
318 | struct irq_work irq_work; | 318 | struct irq_work irq_work; |
319 | u64 reprogram_pmi; | 319 | u64 reprogram_pmi; |
320 | }; | 320 | }; |
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 084ef95274cd..813ed103f45e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h | |||
@@ -115,8 +115,8 @@ notrace static inline int native_write_msr_safe(unsigned int msr, | |||
115 | 115 | ||
116 | extern unsigned long long native_read_tsc(void); | 116 | extern unsigned long long native_read_tsc(void); |
117 | 117 | ||
118 | extern int native_rdmsr_safe_regs(u32 regs[8]); | 118 | extern int rdmsr_safe_regs(u32 regs[8]); |
119 | extern int native_wrmsr_safe_regs(u32 regs[8]); | 119 | extern int wrmsr_safe_regs(u32 regs[8]); |
120 | 120 | ||
121 | static __always_inline unsigned long long __native_read_tsc(void) | 121 | static __always_inline unsigned long long __native_read_tsc(void) |
122 | { | 122 | { |
@@ -187,43 +187,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) | |||
187 | return err; | 187 | return err; |
188 | } | 188 | } |
189 | 189 | ||
190 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) | ||
191 | { | ||
192 | u32 gprs[8] = { 0 }; | ||
193 | int err; | ||
194 | |||
195 | gprs[1] = msr; | ||
196 | gprs[7] = 0x9c5a203a; | ||
197 | |||
198 | err = native_rdmsr_safe_regs(gprs); | ||
199 | |||
200 | *p = gprs[0] | ((u64)gprs[2] << 32); | ||
201 | |||
202 | return err; | ||
203 | } | ||
204 | |||
205 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | ||
206 | { | ||
207 | u32 gprs[8] = { 0 }; | ||
208 | |||
209 | gprs[0] = (u32)val; | ||
210 | gprs[1] = msr; | ||
211 | gprs[2] = val >> 32; | ||
212 | gprs[7] = 0x9c5a203a; | ||
213 | |||
214 | return native_wrmsr_safe_regs(gprs); | ||
215 | } | ||
216 | |||
217 | static inline int rdmsr_safe_regs(u32 regs[8]) | ||
218 | { | ||
219 | return native_rdmsr_safe_regs(regs); | ||
220 | } | ||
221 | |||
222 | static inline int wrmsr_safe_regs(u32 regs[8]) | ||
223 | { | ||
224 | return native_wrmsr_safe_regs(regs); | ||
225 | } | ||
226 | |||
227 | #define rdtscl(low) \ | 190 | #define rdtscl(low) \ |
228 | ((low) = (u32)__native_read_tsc()) | 191 | ((low) = (u32)__native_read_tsc()) |
229 | 192 | ||
@@ -237,6 +200,8 @@ do { \ | |||
237 | (high) = (u32)(_l >> 32); \ | 200 | (high) = (u32)(_l >> 32); \ |
238 | } while (0) | 201 | } while (0) |
239 | 202 | ||
203 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) | ||
204 | |||
240 | #define rdtscp(low, high, aux) \ | 205 | #define rdtscp(low, high, aux) \ |
241 | do { \ | 206 | do { \ |
242 | unsigned long long _val = native_read_tscp(&(aux)); \ | 207 | unsigned long long _val = native_read_tscp(&(aux)); \ |
@@ -248,8 +213,7 @@ do { \ | |||
248 | 213 | ||
249 | #endif /* !CONFIG_PARAVIRT */ | 214 | #endif /* !CONFIG_PARAVIRT */ |
250 | 215 | ||
251 | 216 | #define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val), \ | |
252 | #define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val), \ | ||
253 | (u32)((val) >> 32)) | 217 | (u32)((val) >> 32)) |
254 | 218 | ||
255 | #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) | 219 | #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2)) |
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h index dc580c42851c..c0fa356e90de 100644 --- a/arch/x86/include/asm/nmi.h +++ b/arch/x86/include/asm/nmi.h | |||
@@ -44,28 +44,14 @@ struct nmiaction { | |||
44 | const char *name; | 44 | const char *name; |
45 | }; | 45 | }; |
46 | 46 | ||
47 | #define register_nmi_handler(t, fn, fg, n) \ | 47 | #define register_nmi_handler(t, fn, fg, n, init...) \ |
48 | ({ \ | 48 | ({ \ |
49 | static struct nmiaction fn##_na = { \ | 49 | static struct nmiaction init fn##_na = { \ |
50 | .handler = (fn), \ | 50 | .handler = (fn), \ |
51 | .name = (n), \ | 51 | .name = (n), \ |
52 | .flags = (fg), \ | 52 | .flags = (fg), \ |
53 | }; \ | 53 | }; \ |
54 | __register_nmi_handler((t), &fn##_na); \ | 54 | __register_nmi_handler((t), &fn##_na); \ |
55 | }) | ||
56 | |||
57 | /* | ||
58 | * For special handlers that register/unregister in the | ||
59 | * init section only. This should be considered rare. | ||
60 | */ | ||
61 | #define register_nmi_handler_initonly(t, fn, fg, n) \ | ||
62 | ({ \ | ||
63 | static struct nmiaction fn##_na __initdata = { \ | ||
64 | .handler = (fn), \ | ||
65 | .name = (n), \ | ||
66 | .flags = (fg), \ | ||
67 | }; \ | ||
68 | __register_nmi_handler((t), &fn##_na); \ | ||
69 | }) | 55 | }) |
70 | 56 | ||
71 | int __register_nmi_handler(unsigned int, struct nmiaction *); | 57 | int __register_nmi_handler(unsigned int, struct nmiaction *); |
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h index 6cbbabf52707..0b47ddb6f00b 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h | |||
@@ -128,21 +128,11 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err) | |||
128 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); | 128 | return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err); |
129 | } | 129 | } |
130 | 130 | ||
131 | static inline int paravirt_rdmsr_regs(u32 *regs) | ||
132 | { | ||
133 | return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs); | ||
134 | } | ||
135 | |||
136 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) | 131 | static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high) |
137 | { | 132 | { |
138 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); | 133 | return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high); |
139 | } | 134 | } |
140 | 135 | ||
141 | static inline int paravirt_wrmsr_regs(u32 *regs) | ||
142 | { | ||
143 | return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs); | ||
144 | } | ||
145 | |||
146 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ | 136 | /* These should all do BUG_ON(_err), but our headers are too tangled. */ |
147 | #define rdmsr(msr, val1, val2) \ | 137 | #define rdmsr(msr, val1, val2) \ |
148 | do { \ | 138 | do { \ |
@@ -176,9 +166,6 @@ do { \ | |||
176 | _err; \ | 166 | _err; \ |
177 | }) | 167 | }) |
178 | 168 | ||
179 | #define rdmsr_safe_regs(regs) paravirt_rdmsr_regs(regs) | ||
180 | #define wrmsr_safe_regs(regs) paravirt_wrmsr_regs(regs) | ||
181 | |||
182 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) | 169 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
183 | { | 170 | { |
184 | int err; | 171 | int err; |
@@ -186,32 +173,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) | |||
186 | *p = paravirt_read_msr(msr, &err); | 173 | *p = paravirt_read_msr(msr, &err); |
187 | return err; | 174 | return err; |
188 | } | 175 | } |
189 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) | ||
190 | { | ||
191 | u32 gprs[8] = { 0 }; | ||
192 | int err; | ||
193 | |||
194 | gprs[1] = msr; | ||
195 | gprs[7] = 0x9c5a203a; | ||
196 | |||
197 | err = paravirt_rdmsr_regs(gprs); | ||
198 | |||
199 | *p = gprs[0] | ((u64)gprs[2] << 32); | ||
200 | |||
201 | return err; | ||
202 | } | ||
203 | |||
204 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | ||
205 | { | ||
206 | u32 gprs[8] = { 0 }; | ||
207 | |||
208 | gprs[0] = (u32)val; | ||
209 | gprs[1] = msr; | ||
210 | gprs[2] = val >> 32; | ||
211 | gprs[7] = 0x9c5a203a; | ||
212 | |||
213 | return paravirt_wrmsr_regs(gprs); | ||
214 | } | ||
215 | 176 | ||
216 | static inline u64 paravirt_read_tsc(void) | 177 | static inline u64 paravirt_read_tsc(void) |
217 | { | 178 | { |
@@ -252,6 +213,8 @@ do { \ | |||
252 | high = _l >> 32; \ | 213 | high = _l >> 32; \ |
253 | } while (0) | 214 | } while (0) |
254 | 215 | ||
216 | #define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter)) | ||
217 | |||
255 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) | 218 | static inline unsigned long long paravirt_rdtscp(unsigned int *aux) |
256 | { | 219 | { |
257 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); | 220 | return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux); |
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h index 8e8b9a4987ee..8613cbb7ba41 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h | |||
@@ -153,9 +153,7 @@ struct pv_cpu_ops { | |||
153 | /* MSR, PMC and TSR operations. | 153 | /* MSR, PMC and TSR operations. |
154 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ | 154 | err = 0/-EFAULT. wrmsr returns 0/-EFAULT. */ |
155 | u64 (*read_msr)(unsigned int msr, int *err); | 155 | u64 (*read_msr)(unsigned int msr, int *err); |
156 | int (*rdmsr_regs)(u32 *regs); | ||
157 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); | 156 | int (*write_msr)(unsigned int msr, unsigned low, unsigned high); |
158 | int (*wrmsr_regs)(u32 *regs); | ||
159 | 157 | ||
160 | u64 (*read_tsc)(void); | 158 | u64 (*read_tsc)(void); |
161 | u64 (*read_pmc)(int counter); | 159 | u64 (*read_pmc)(int counter); |
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index b3a531746026..5ad24a89b19b 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h | |||
@@ -7,9 +7,13 @@ | |||
7 | #undef DEBUG | 7 | #undef DEBUG |
8 | 8 | ||
9 | #ifdef DEBUG | 9 | #ifdef DEBUG |
10 | #define DBG(x...) printk(x) | 10 | #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__) |
11 | #else | 11 | #else |
12 | #define DBG(x...) | 12 | #define DBG(fmt, ...) \ |
13 | do { \ | ||
14 | if (0) \ | ||
15 | printk(fmt, ##__VA_ARGS__); \ | ||
16 | } while (0) | ||
13 | #endif | 17 | #endif |
14 | 18 | ||
15 | #define PCI_PROBE_BIOS 0x0001 | 19 | #define PCI_PROBE_BIOS 0x0001 |
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 588f52ea810e..c78f14a0df00 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h | |||
@@ -5,11 +5,10 @@ | |||
5 | * Performance event hw details: | 5 | * Performance event hw details: |
6 | */ | 6 | */ |
7 | 7 | ||
8 | #define X86_PMC_MAX_GENERIC 32 | 8 | #define INTEL_PMC_MAX_GENERIC 32 |
9 | #define X86_PMC_MAX_FIXED 3 | 9 | #define INTEL_PMC_MAX_FIXED 3 |
10 | #define INTEL_PMC_IDX_FIXED 32 | ||
10 | 11 | ||
11 | #define X86_PMC_IDX_GENERIC 0 | ||
12 | #define X86_PMC_IDX_FIXED 32 | ||
13 | #define X86_PMC_IDX_MAX 64 | 12 | #define X86_PMC_IDX_MAX 64 |
14 | 13 | ||
15 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 | 14 | #define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
@@ -48,8 +47,7 @@ | |||
48 | (X86_RAW_EVENT_MASK | \ | 47 | (X86_RAW_EVENT_MASK | \ |
49 | AMD64_EVENTSEL_EVENT) | 48 | AMD64_EVENTSEL_EVENT) |
50 | #define AMD64_NUM_COUNTERS 4 | 49 | #define AMD64_NUM_COUNTERS 4 |
51 | #define AMD64_NUM_COUNTERS_F15H 6 | 50 | #define AMD64_NUM_COUNTERS_CORE 6 |
52 | #define AMD64_NUM_COUNTERS_MAX AMD64_NUM_COUNTERS_F15H | ||
53 | 51 | ||
54 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c | 52 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
55 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) | 53 | #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) |
@@ -121,16 +119,16 @@ struct x86_pmu_capability { | |||
121 | 119 | ||
122 | /* Instr_Retired.Any: */ | 120 | /* Instr_Retired.Any: */ |
123 | #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 | 121 | #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 |
124 | #define X86_PMC_IDX_FIXED_INSTRUCTIONS (X86_PMC_IDX_FIXED + 0) | 122 | #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0) |
125 | 123 | ||
126 | /* CPU_CLK_Unhalted.Core: */ | 124 | /* CPU_CLK_Unhalted.Core: */ |
127 | #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a | 125 | #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a |
128 | #define X86_PMC_IDX_FIXED_CPU_CYCLES (X86_PMC_IDX_FIXED + 1) | 126 | #define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1) |
129 | 127 | ||
130 | /* CPU_CLK_Unhalted.Ref: */ | 128 | /* CPU_CLK_Unhalted.Ref: */ |
131 | #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b | 129 | #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b |
132 | #define X86_PMC_IDX_FIXED_REF_CYCLES (X86_PMC_IDX_FIXED + 2) | 130 | #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2) |
133 | #define X86_PMC_MSK_FIXED_REF_CYCLES (1ULL << X86_PMC_IDX_FIXED_REF_CYCLES) | 131 | #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES) |
134 | 132 | ||
135 | /* | 133 | /* |
136 | * We model BTS tracing as another fixed-mode PMC. | 134 | * We model BTS tracing as another fixed-mode PMC. |
@@ -139,7 +137,7 @@ struct x86_pmu_capability { | |||
139 | * values are used by actual fixed events and higher values are used | 137 | * values are used by actual fixed events and higher values are used |
140 | * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. | 138 | * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. |
141 | */ | 139 | */ |
142 | #define X86_PMC_IDX_FIXED_BTS (X86_PMC_IDX_FIXED + 16) | 140 | #define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16) |
143 | 141 | ||
144 | /* | 142 | /* |
145 | * IBS cpuid feature detection | 143 | * IBS cpuid feature detection |
@@ -234,6 +232,7 @@ struct perf_guest_switch_msr { | |||
234 | 232 | ||
235 | extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); | 233 | extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); |
236 | extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); | 234 | extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); |
235 | extern void perf_check_microcode(void); | ||
237 | #else | 236 | #else |
238 | static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr) | 237 | static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
239 | { | 238 | { |
@@ -247,6 +246,7 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |||
247 | } | 246 | } |
248 | 247 | ||
249 | static inline void perf_events_lapic_init(void) { } | 248 | static inline void perf_events_lapic_init(void) { } |
249 | static inline void perf_check_microcode(void) { } | ||
250 | #endif | 250 | #endif |
251 | 251 | ||
252 | #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) | 252 | #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) |
diff --git a/arch/x86/include/asm/pgtable-2level.h b/arch/x86/include/asm/pgtable-2level.h index 98391db840c6..f2b489cf1602 100644 --- a/arch/x86/include/asm/pgtable-2level.h +++ b/arch/x86/include/asm/pgtable-2level.h | |||
@@ -2,9 +2,9 @@ | |||
2 | #define _ASM_X86_PGTABLE_2LEVEL_H | 2 | #define _ASM_X86_PGTABLE_2LEVEL_H |
3 | 3 | ||
4 | #define pte_ERROR(e) \ | 4 | #define pte_ERROR(e) \ |
5 | printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low) | 5 | pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low) |
6 | #define pgd_ERROR(e) \ | 6 | #define pgd_ERROR(e) \ |
7 | printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) | 7 | pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e)) |
8 | 8 | ||
9 | /* | 9 | /* |
10 | * Certain architectures need to do special things when PTEs | 10 | * Certain architectures need to do special things when PTEs |
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index cb00ccc7d571..4cc9f2b7cdc3 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h | |||
@@ -9,13 +9,13 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #define pte_ERROR(e) \ | 11 | #define pte_ERROR(e) \ |
12 | printk("%s:%d: bad pte %p(%08lx%08lx).\n", \ | 12 | pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \ |
13 | __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) | 13 | __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low) |
14 | #define pmd_ERROR(e) \ | 14 | #define pmd_ERROR(e) \ |
15 | printk("%s:%d: bad pmd %p(%016Lx).\n", \ | 15 | pr_err("%s:%d: bad pmd %p(%016Lx)\n", \ |
16 | __FILE__, __LINE__, &(e), pmd_val(e)) | 16 | __FILE__, __LINE__, &(e), pmd_val(e)) |
17 | #define pgd_ERROR(e) \ | 17 | #define pgd_ERROR(e) \ |
18 | printk("%s:%d: bad pgd %p(%016Lx).\n", \ | 18 | pr_err("%s:%d: bad pgd %p(%016Lx)\n", \ |
19 | __FILE__, __LINE__, &(e), pgd_val(e)) | 19 | __FILE__, __LINE__, &(e), pgd_val(e)) |
20 | 20 | ||
21 | /* Rules for using set_pte: the pte being assigned *must* be | 21 | /* Rules for using set_pte: the pte being assigned *must* be |
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h index 975f709e09ae..8251be02301e 100644 --- a/arch/x86/include/asm/pgtable_64.h +++ b/arch/x86/include/asm/pgtable_64.h | |||
@@ -26,16 +26,16 @@ extern pgd_t init_level4_pgt[]; | |||
26 | extern void paging_init(void); | 26 | extern void paging_init(void); |
27 | 27 | ||
28 | #define pte_ERROR(e) \ | 28 | #define pte_ERROR(e) \ |
29 | printk("%s:%d: bad pte %p(%016lx).\n", \ | 29 | pr_err("%s:%d: bad pte %p(%016lx)\n", \ |
30 | __FILE__, __LINE__, &(e), pte_val(e)) | 30 | __FILE__, __LINE__, &(e), pte_val(e)) |
31 | #define pmd_ERROR(e) \ | 31 | #define pmd_ERROR(e) \ |
32 | printk("%s:%d: bad pmd %p(%016lx).\n", \ | 32 | pr_err("%s:%d: bad pmd %p(%016lx)\n", \ |
33 | __FILE__, __LINE__, &(e), pmd_val(e)) | 33 | __FILE__, __LINE__, &(e), pmd_val(e)) |
34 | #define pud_ERROR(e) \ | 34 | #define pud_ERROR(e) \ |
35 | printk("%s:%d: bad pud %p(%016lx).\n", \ | 35 | pr_err("%s:%d: bad pud %p(%016lx)\n", \ |
36 | __FILE__, __LINE__, &(e), pud_val(e)) | 36 | __FILE__, __LINE__, &(e), pud_val(e)) |
37 | #define pgd_ERROR(e) \ | 37 | #define pgd_ERROR(e) \ |
38 | printk("%s:%d: bad pgd %p(%016lx).\n", \ | 38 | pr_err("%s:%d: bad pgd %p(%016lx)\n", \ |
39 | __FILE__, __LINE__, &(e), pgd_val(e)) | 39 | __FILE__, __LINE__, &(e), pgd_val(e)) |
40 | 40 | ||
41 | struct mm_struct; | 41 | struct mm_struct; |
diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h index fce3f4ae5bd6..fe1ec5bcd846 100644 --- a/arch/x86/include/asm/realmode.h +++ b/arch/x86/include/asm/realmode.h | |||
@@ -21,8 +21,9 @@ struct real_mode_header { | |||
21 | u32 wakeup_header; | 21 | u32 wakeup_header; |
22 | #endif | 22 | #endif |
23 | /* APM/BIOS reboot */ | 23 | /* APM/BIOS reboot */ |
24 | #ifdef CONFIG_X86_32 | ||
25 | u32 machine_real_restart_asm; | 24 | u32 machine_real_restart_asm; |
25 | #ifdef CONFIG_X86_64 | ||
26 | u32 machine_real_restart_seg; | ||
26 | #endif | 27 | #endif |
27 | }; | 28 | }; |
28 | 29 | ||
diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h index 92f297069e87..a82c4f1b4d83 100644 --- a/arch/x86/include/asm/reboot.h +++ b/arch/x86/include/asm/reboot.h | |||
@@ -18,8 +18,8 @@ extern struct machine_ops machine_ops; | |||
18 | 18 | ||
19 | void native_machine_crash_shutdown(struct pt_regs *regs); | 19 | void native_machine_crash_shutdown(struct pt_regs *regs); |
20 | void native_machine_shutdown(void); | 20 | void native_machine_shutdown(void); |
21 | void machine_real_restart(unsigned int type); | 21 | void __noreturn machine_real_restart(unsigned int type); |
22 | /* These must match dispatch_table in reboot_32.S */ | 22 | /* These must match dispatch in arch/x86/realmore/rm/reboot.S */ |
23 | #define MRR_BIOS 0 | 23 | #define MRR_BIOS 0 |
24 | #define MRR_APM 1 | 24 | #define MRR_APM 1 |
25 | 25 | ||
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h index f48394513c37..2ffa95dc2333 100644 --- a/arch/x86/include/asm/smp.h +++ b/arch/x86/include/asm/smp.h | |||
@@ -169,11 +169,6 @@ void x86_idle_thread_init(unsigned int cpu, struct task_struct *idle); | |||
169 | void smp_store_cpu_info(int id); | 169 | void smp_store_cpu_info(int id); |
170 | #define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu) | 170 | #define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu) |
171 | 171 | ||
172 | /* We don't mark CPUs online until __cpu_up(), so we need another measure */ | ||
173 | static inline int num_booting_cpus(void) | ||
174 | { | ||
175 | return cpumask_weight(cpu_callout_mask); | ||
176 | } | ||
177 | #else /* !CONFIG_SMP */ | 172 | #else /* !CONFIG_SMP */ |
178 | #define wbinvd_on_cpu(cpu) wbinvd() | 173 | #define wbinvd_on_cpu(cpu) wbinvd() |
179 | static inline int wbinvd_on_all_cpus(void) | 174 | static inline int wbinvd_on_all_cpus(void) |
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h index 8e796fbbf9c6..d8def8b3dba0 100644 --- a/arch/x86/include/asm/uaccess_64.h +++ b/arch/x86/include/asm/uaccess_64.h | |||
@@ -17,6 +17,8 @@ | |||
17 | 17 | ||
18 | /* Handles exceptions in both to and from, but doesn't do access_ok */ | 18 | /* Handles exceptions in both to and from, but doesn't do access_ok */ |
19 | __must_check unsigned long | 19 | __must_check unsigned long |
20 | copy_user_enhanced_fast_string(void *to, const void *from, unsigned len); | ||
21 | __must_check unsigned long | ||
20 | copy_user_generic_string(void *to, const void *from, unsigned len); | 22 | copy_user_generic_string(void *to, const void *from, unsigned len); |
21 | __must_check unsigned long | 23 | __must_check unsigned long |
22 | copy_user_generic_unrolled(void *to, const void *from, unsigned len); | 24 | copy_user_generic_unrolled(void *to, const void *from, unsigned len); |
@@ -26,9 +28,16 @@ copy_user_generic(void *to, const void *from, unsigned len) | |||
26 | { | 28 | { |
27 | unsigned ret; | 29 | unsigned ret; |
28 | 30 | ||
29 | alternative_call(copy_user_generic_unrolled, | 31 | /* |
32 | * If CPU has ERMS feature, use copy_user_enhanced_fast_string. | ||
33 | * Otherwise, if CPU has rep_good feature, use copy_user_generic_string. | ||
34 | * Otherwise, use copy_user_generic_unrolled. | ||
35 | */ | ||
36 | alternative_call_2(copy_user_generic_unrolled, | ||
30 | copy_user_generic_string, | 37 | copy_user_generic_string, |
31 | X86_FEATURE_REP_GOOD, | 38 | X86_FEATURE_REP_GOOD, |
39 | copy_user_enhanced_fast_string, | ||
40 | X86_FEATURE_ERMS, | ||
32 | ASM_OUTPUT2("=a" (ret), "=D" (to), "=S" (from), | 41 | ASM_OUTPUT2("=a" (ret), "=D" (to), "=S" (from), |
33 | "=d" (len)), | 42 | "=d" (len)), |
34 | "1" (to), "2" (from), "3" (len) | 43 | "1" (to), "2" (from), "3" (len) |
diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h index 1e9bed14f7ae..f3971bbcd1de 100644 --- a/arch/x86/include/asm/uprobes.h +++ b/arch/x86/include/asm/uprobes.h | |||
@@ -48,7 +48,7 @@ struct arch_uprobe_task { | |||
48 | #endif | 48 | #endif |
49 | }; | 49 | }; |
50 | 50 | ||
51 | extern int arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm); | 51 | extern int arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm, unsigned long addr); |
52 | extern int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs); | 52 | extern int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs); |
53 | extern int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs); | 53 | extern int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs); |
54 | extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk); | 54 | extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk); |
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h index 6149b476d9df..a06983cdc125 100644 --- a/arch/x86/include/asm/uv/uv_bau.h +++ b/arch/x86/include/asm/uv/uv_bau.h | |||
@@ -140,6 +140,9 @@ | |||
140 | #define IPI_RESET_LIMIT 1 | 140 | #define IPI_RESET_LIMIT 1 |
141 | /* after this # consecutive successes, bump up the throttle if it was lowered */ | 141 | /* after this # consecutive successes, bump up the throttle if it was lowered */ |
142 | #define COMPLETE_THRESHOLD 5 | 142 | #define COMPLETE_THRESHOLD 5 |
143 | /* after this # of giveups (fall back to kernel IPI's) disable the use of | ||
144 | the BAU for a period of time */ | ||
145 | #define GIVEUP_LIMIT 100 | ||
143 | 146 | ||
144 | #define UV_LB_SUBNODEID 0x10 | 147 | #define UV_LB_SUBNODEID 0x10 |
145 | 148 | ||
@@ -166,7 +169,6 @@ | |||
166 | #define FLUSH_RETRY_TIMEOUT 2 | 169 | #define FLUSH_RETRY_TIMEOUT 2 |
167 | #define FLUSH_GIVEUP 3 | 170 | #define FLUSH_GIVEUP 3 |
168 | #define FLUSH_COMPLETE 4 | 171 | #define FLUSH_COMPLETE 4 |
169 | #define FLUSH_RETRY_BUSYBUG 5 | ||
170 | 172 | ||
171 | /* | 173 | /* |
172 | * tuning the action when the numalink network is extremely delayed | 174 | * tuning the action when the numalink network is extremely delayed |
@@ -175,7 +177,7 @@ | |||
175 | microseconds */ | 177 | microseconds */ |
176 | #define CONGESTED_REPS 10 /* long delays averaged over | 178 | #define CONGESTED_REPS 10 /* long delays averaged over |
177 | this many broadcasts */ | 179 | this many broadcasts */ |
178 | #define CONGESTED_PERIOD 30 /* time for the bau to be | 180 | #define DISABLED_PERIOD 10 /* time for the bau to be |
179 | disabled, in seconds */ | 181 | disabled, in seconds */ |
180 | /* see msg_type: */ | 182 | /* see msg_type: */ |
181 | #define MSG_NOOP 0 | 183 | #define MSG_NOOP 0 |
@@ -520,6 +522,12 @@ struct ptc_stats { | |||
520 | unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */ | 522 | unsigned long s_uv2_wars; /* uv2 workaround, perm. busy */ |
521 | unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */ | 523 | unsigned long s_uv2_wars_hw; /* uv2 workaround, hiwater */ |
522 | unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */ | 524 | unsigned long s_uv2_war_waits; /* uv2 workaround, long waits */ |
525 | unsigned long s_overipilimit; /* over the ipi reset limit */ | ||
526 | unsigned long s_giveuplimit; /* disables, over giveup limit*/ | ||
527 | unsigned long s_enters; /* entries to the driver */ | ||
528 | unsigned long s_ipifordisabled; /* fall back to IPI; disabled */ | ||
529 | unsigned long s_plugged; /* plugged by h/w bug*/ | ||
530 | unsigned long s_congested; /* giveup on long wait */ | ||
523 | /* destination statistics */ | 531 | /* destination statistics */ |
524 | unsigned long d_alltlb; /* times all tlb's on this | 532 | unsigned long d_alltlb; /* times all tlb's on this |
525 | cpu were flushed */ | 533 | cpu were flushed */ |
@@ -586,8 +594,8 @@ struct bau_control { | |||
586 | int timeout_tries; | 594 | int timeout_tries; |
587 | int ipi_attempts; | 595 | int ipi_attempts; |
588 | int conseccompletes; | 596 | int conseccompletes; |
589 | int baudisabled; | 597 | short nobau; |
590 | int set_bau_off; | 598 | short baudisabled; |
591 | short cpu; | 599 | short cpu; |
592 | short osnode; | 600 | short osnode; |
593 | short uvhub_cpu; | 601 | short uvhub_cpu; |
@@ -596,14 +604,16 @@ struct bau_control { | |||
596 | short cpus_in_socket; | 604 | short cpus_in_socket; |
597 | short cpus_in_uvhub; | 605 | short cpus_in_uvhub; |
598 | short partition_base_pnode; | 606 | short partition_base_pnode; |
599 | short using_desc; /* an index, like uvhub_cpu */ | 607 | short busy; /* all were busy (war) */ |
600 | unsigned int inuse_map; | ||
601 | unsigned short message_number; | 608 | unsigned short message_number; |
602 | unsigned short uvhub_quiesce; | 609 | unsigned short uvhub_quiesce; |
603 | short socket_acknowledge_count[DEST_Q_SIZE]; | 610 | short socket_acknowledge_count[DEST_Q_SIZE]; |
604 | cycles_t send_message; | 611 | cycles_t send_message; |
612 | cycles_t period_end; | ||
613 | cycles_t period_time; | ||
605 | spinlock_t uvhub_lock; | 614 | spinlock_t uvhub_lock; |
606 | spinlock_t queue_lock; | 615 | spinlock_t queue_lock; |
616 | spinlock_t disable_lock; | ||
607 | /* tunables */ | 617 | /* tunables */ |
608 | int max_concurr; | 618 | int max_concurr; |
609 | int max_concurr_const; | 619 | int max_concurr_const; |
@@ -614,9 +624,9 @@ struct bau_control { | |||
614 | int complete_threshold; | 624 | int complete_threshold; |
615 | int cong_response_us; | 625 | int cong_response_us; |
616 | int cong_reps; | 626 | int cong_reps; |
617 | int cong_period; | 627 | cycles_t disabled_period; |
618 | unsigned long clocks_per_100_usec; | 628 | int period_giveups; |
619 | cycles_t period_time; | 629 | int giveup_limit; |
620 | long period_requests; | 630 | long period_requests; |
621 | struct hub_and_pnode *thp; | 631 | struct hub_and_pnode *thp; |
622 | }; | 632 | }; |
diff --git a/arch/x86/include/asm/x2apic.h b/arch/x86/include/asm/x2apic.h index 92e54abf89e0..f90f0a587c66 100644 --- a/arch/x86/include/asm/x2apic.h +++ b/arch/x86/include/asm/x2apic.h | |||
@@ -9,15 +9,6 @@ | |||
9 | #include <asm/ipi.h> | 9 | #include <asm/ipi.h> |
10 | #include <linux/cpumask.h> | 10 | #include <linux/cpumask.h> |
11 | 11 | ||
12 | /* | ||
13 | * Need to use more than cpu 0, because we need more vectors | ||
14 | * when MSI-X are used. | ||
15 | */ | ||
16 | static const struct cpumask *x2apic_target_cpus(void) | ||
17 | { | ||
18 | return cpu_online_mask; | ||
19 | } | ||
20 | |||
21 | static int x2apic_apic_id_valid(int apicid) | 12 | static int x2apic_apic_id_valid(int apicid) |
22 | { | 13 | { |
23 | return 1; | 14 | return 1; |
@@ -28,15 +19,6 @@ static int x2apic_apic_id_registered(void) | |||
28 | return 1; | 19 | return 1; |
29 | } | 20 | } |
30 | 21 | ||
31 | /* | ||
32 | * For now each logical cpu is in its own vector allocation domain. | ||
33 | */ | ||
34 | static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
35 | { | ||
36 | cpumask_clear(retmask); | ||
37 | cpumask_set_cpu(cpu, retmask); | ||
38 | } | ||
39 | |||
40 | static void | 22 | static void |
41 | __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) | 23 | __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) |
42 | { | 24 | { |
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h index c090af10ac7d..38155f667144 100644 --- a/arch/x86/include/asm/x86_init.h +++ b/arch/x86/include/asm/x86_init.h | |||
@@ -156,7 +156,6 @@ struct x86_cpuinit_ops { | |||
156 | /** | 156 | /** |
157 | * struct x86_platform_ops - platform specific runtime functions | 157 | * struct x86_platform_ops - platform specific runtime functions |
158 | * @calibrate_tsc: calibrate TSC | 158 | * @calibrate_tsc: calibrate TSC |
159 | * @wallclock_init: init the wallclock device | ||
160 | * @get_wallclock: get time from HW clock like RTC etc. | 159 | * @get_wallclock: get time from HW clock like RTC etc. |
161 | * @set_wallclock: set time back to HW clock | 160 | * @set_wallclock: set time back to HW clock |
162 | * @is_untracked_pat_range exclude from PAT logic | 161 | * @is_untracked_pat_range exclude from PAT logic |
@@ -164,10 +163,10 @@ struct x86_cpuinit_ops { | |||
164 | * @i8042_detect pre-detect if i8042 controller exists | 163 | * @i8042_detect pre-detect if i8042 controller exists |
165 | * @save_sched_clock_state: save state for sched_clock() on suspend | 164 | * @save_sched_clock_state: save state for sched_clock() on suspend |
166 | * @restore_sched_clock_state: restore state for sched_clock() on resume | 165 | * @restore_sched_clock_state: restore state for sched_clock() on resume |
166 | * @apic_post_init: adjust apic if neeeded | ||
167 | */ | 167 | */ |
168 | struct x86_platform_ops { | 168 | struct x86_platform_ops { |
169 | unsigned long (*calibrate_tsc)(void); | 169 | unsigned long (*calibrate_tsc)(void); |
170 | void (*wallclock_init)(void); | ||
171 | unsigned long (*get_wallclock)(void); | 170 | unsigned long (*get_wallclock)(void); |
172 | int (*set_wallclock)(unsigned long nowtime); | 171 | int (*set_wallclock)(unsigned long nowtime); |
173 | void (*iommu_shutdown)(void); | 172 | void (*iommu_shutdown)(void); |
@@ -177,6 +176,7 @@ struct x86_platform_ops { | |||
177 | int (*i8042_detect)(void); | 176 | int (*i8042_detect)(void); |
178 | void (*save_sched_clock_state)(void); | 177 | void (*save_sched_clock_state)(void); |
179 | void (*restore_sched_clock_state)(void); | 178 | void (*restore_sched_clock_state)(void); |
179 | void (*apic_post_init)(void); | ||
180 | }; | 180 | }; |
181 | 181 | ||
182 | struct pci_dev; | 182 | struct pci_dev; |
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 1f84794f0759..931280ff8299 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c | |||
@@ -1,3 +1,5 @@ | |||
1 | #define pr_fmt(fmt) "SMP alternatives: " fmt | ||
2 | |||
1 | #include <linux/module.h> | 3 | #include <linux/module.h> |
2 | #include <linux/sched.h> | 4 | #include <linux/sched.h> |
3 | #include <linux/mutex.h> | 5 | #include <linux/mutex.h> |
@@ -63,8 +65,11 @@ static int __init setup_noreplace_paravirt(char *str) | |||
63 | __setup("noreplace-paravirt", setup_noreplace_paravirt); | 65 | __setup("noreplace-paravirt", setup_noreplace_paravirt); |
64 | #endif | 66 | #endif |
65 | 67 | ||
66 | #define DPRINTK(fmt, args...) if (debug_alternative) \ | 68 | #define DPRINTK(fmt, ...) \ |
67 | printk(KERN_DEBUG fmt, args) | 69 | do { \ |
70 | if (debug_alternative) \ | ||
71 | printk(KERN_DEBUG fmt, ##__VA_ARGS__); \ | ||
72 | } while (0) | ||
68 | 73 | ||
69 | /* | 74 | /* |
70 | * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes | 75 | * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes |
@@ -428,7 +433,7 @@ void alternatives_smp_switch(int smp) | |||
428 | * If this still occurs then you should see a hang | 433 | * If this still occurs then you should see a hang |
429 | * or crash shortly after this line: | 434 | * or crash shortly after this line: |
430 | */ | 435 | */ |
431 | printk("lockdep: fixing up alternatives.\n"); | 436 | pr_info("lockdep: fixing up alternatives\n"); |
432 | #endif | 437 | #endif |
433 | 438 | ||
434 | if (noreplace_smp || smp_alt_once || skip_smp_alternatives) | 439 | if (noreplace_smp || smp_alt_once || skip_smp_alternatives) |
@@ -444,14 +449,14 @@ void alternatives_smp_switch(int smp) | |||
444 | if (smp == smp_mode) { | 449 | if (smp == smp_mode) { |
445 | /* nothing */ | 450 | /* nothing */ |
446 | } else if (smp) { | 451 | } else if (smp) { |
447 | printk(KERN_INFO "SMP alternatives: switching to SMP code\n"); | 452 | pr_info("switching to SMP code\n"); |
448 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); | 453 | clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); |
449 | clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP); | 454 | clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP); |
450 | list_for_each_entry(mod, &smp_alt_modules, next) | 455 | list_for_each_entry(mod, &smp_alt_modules, next) |
451 | alternatives_smp_lock(mod->locks, mod->locks_end, | 456 | alternatives_smp_lock(mod->locks, mod->locks_end, |
452 | mod->text, mod->text_end); | 457 | mod->text, mod->text_end); |
453 | } else { | 458 | } else { |
454 | printk(KERN_INFO "SMP alternatives: switching to UP code\n"); | 459 | pr_info("switching to UP code\n"); |
455 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); | 460 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); |
456 | set_cpu_cap(&cpu_data(0), X86_FEATURE_UP); | 461 | set_cpu_cap(&cpu_data(0), X86_FEATURE_UP); |
457 | list_for_each_entry(mod, &smp_alt_modules, next) | 462 | list_for_each_entry(mod, &smp_alt_modules, next) |
@@ -546,7 +551,7 @@ void __init alternative_instructions(void) | |||
546 | #ifdef CONFIG_SMP | 551 | #ifdef CONFIG_SMP |
547 | if (smp_alt_once) { | 552 | if (smp_alt_once) { |
548 | if (1 == num_possible_cpus()) { | 553 | if (1 == num_possible_cpus()) { |
549 | printk(KERN_INFO "SMP alternatives: switching to UP code\n"); | 554 | pr_info("switching to UP code\n"); |
550 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); | 555 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP); |
551 | set_cpu_cap(&cpu_data(0), X86_FEATURE_UP); | 556 | set_cpu_cap(&cpu_data(0), X86_FEATURE_UP); |
552 | 557 | ||
@@ -664,7 +669,7 @@ static int __kprobes stop_machine_text_poke(void *data) | |||
664 | struct text_poke_param *p; | 669 | struct text_poke_param *p; |
665 | int i; | 670 | int i; |
666 | 671 | ||
667 | if (atomic_dec_and_test(&stop_machine_first)) { | 672 | if (atomic_xchg(&stop_machine_first, 0)) { |
668 | for (i = 0; i < tpp->nparams; i++) { | 673 | for (i = 0; i < tpp->nparams; i++) { |
669 | p = &tpp->params[i]; | 674 | p = &tpp->params[i]; |
670 | text_poke(p->addr, p->opcode, p->len); | 675 | text_poke(p->addr, p->opcode, p->len); |
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index be16854591cc..aadf3359e2a7 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c | |||
@@ -2,6 +2,9 @@ | |||
2 | * Shared support code for AMD K8 northbridges and derivates. | 2 | * Shared support code for AMD K8 northbridges and derivates. |
3 | * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2. | 3 | * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2. |
4 | */ | 4 | */ |
5 | |||
6 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
7 | |||
5 | #include <linux/types.h> | 8 | #include <linux/types.h> |
6 | #include <linux/slab.h> | 9 | #include <linux/slab.h> |
7 | #include <linux/init.h> | 10 | #include <linux/init.h> |
@@ -16,6 +19,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { | |||
16 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, | 19 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) }, |
17 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, | 20 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) }, |
18 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, | 21 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) }, |
22 | { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) }, | ||
19 | {} | 23 | {} |
20 | }; | 24 | }; |
21 | EXPORT_SYMBOL(amd_nb_misc_ids); | 25 | EXPORT_SYMBOL(amd_nb_misc_ids); |
@@ -258,7 +262,7 @@ void amd_flush_garts(void) | |||
258 | } | 262 | } |
259 | spin_unlock_irqrestore(&gart_lock, flags); | 263 | spin_unlock_irqrestore(&gart_lock, flags); |
260 | if (!flushed) | 264 | if (!flushed) |
261 | printk("nothing to flush?\n"); | 265 | pr_notice("nothing to flush?\n"); |
262 | } | 266 | } |
263 | EXPORT_SYMBOL_GPL(amd_flush_garts); | 267 | EXPORT_SYMBOL_GPL(amd_flush_garts); |
264 | 268 | ||
@@ -269,11 +273,10 @@ static __init int init_amd_nbs(void) | |||
269 | err = amd_cache_northbridges(); | 273 | err = amd_cache_northbridges(); |
270 | 274 | ||
271 | if (err < 0) | 275 | if (err < 0) |
272 | printk(KERN_NOTICE "AMD NB: Cannot enumerate AMD northbridges.\n"); | 276 | pr_notice("Cannot enumerate AMD northbridges\n"); |
273 | 277 | ||
274 | if (amd_cache_gart() < 0) | 278 | if (amd_cache_gart() < 0) |
275 | printk(KERN_NOTICE "AMD NB: Cannot initialize GART flush words, " | 279 | pr_notice("Cannot initialize GART flush words, GART support disabled\n"); |
276 | "GART support disabled.\n"); | ||
277 | 280 | ||
278 | return err; | 281 | return err; |
279 | } | 282 | } |
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 39a222e094af..c421512ca5eb 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c | |||
@@ -2123,6 +2123,25 @@ void default_init_apic_ldr(void) | |||
2123 | apic_write(APIC_LDR, val); | 2123 | apic_write(APIC_LDR, val); |
2124 | } | 2124 | } |
2125 | 2125 | ||
2126 | int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
2127 | const struct cpumask *andmask, | ||
2128 | unsigned int *apicid) | ||
2129 | { | ||
2130 | unsigned int cpu; | ||
2131 | |||
2132 | for_each_cpu_and(cpu, cpumask, andmask) { | ||
2133 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | ||
2134 | break; | ||
2135 | } | ||
2136 | |||
2137 | if (likely(cpu < nr_cpu_ids)) { | ||
2138 | *apicid = per_cpu(x86_cpu_to_apicid, cpu); | ||
2139 | return 0; | ||
2140 | } | ||
2141 | |||
2142 | return -EINVAL; | ||
2143 | } | ||
2144 | |||
2126 | /* | 2145 | /* |
2127 | * Power management | 2146 | * Power management |
2128 | */ | 2147 | */ |
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c index 0e881c46e8c8..00c77cf78e9e 100644 --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c | |||
@@ -36,25 +36,6 @@ static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |||
36 | return 1; | 36 | return 1; |
37 | } | 37 | } |
38 | 38 | ||
39 | static const struct cpumask *flat_target_cpus(void) | ||
40 | { | ||
41 | return cpu_online_mask; | ||
42 | } | ||
43 | |||
44 | static void flat_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
45 | { | ||
46 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
47 | * specified in the interrupt destination when using lowest | ||
48 | * priority interrupt delivery mode. | ||
49 | * | ||
50 | * In particular there was a hyperthreading cpu observed to | ||
51 | * deliver interrupts to the wrong hyperthread when only one | ||
52 | * hyperthread was specified in the interrupt desitination. | ||
53 | */ | ||
54 | cpumask_clear(retmask); | ||
55 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
56 | } | ||
57 | |||
58 | /* | 39 | /* |
59 | * Set up the logical destination ID. | 40 | * Set up the logical destination ID. |
60 | * | 41 | * |
@@ -92,7 +73,7 @@ static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector) | |||
92 | } | 73 | } |
93 | 74 | ||
94 | static void | 75 | static void |
95 | flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) | 76 | flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) |
96 | { | 77 | { |
97 | unsigned long mask = cpumask_bits(cpumask)[0]; | 78 | unsigned long mask = cpumask_bits(cpumask)[0]; |
98 | int cpu = smp_processor_id(); | 79 | int cpu = smp_processor_id(); |
@@ -186,7 +167,7 @@ static struct apic apic_flat = { | |||
186 | .irq_delivery_mode = dest_LowestPrio, | 167 | .irq_delivery_mode = dest_LowestPrio, |
187 | .irq_dest_mode = 1, /* logical */ | 168 | .irq_dest_mode = 1, /* logical */ |
188 | 169 | ||
189 | .target_cpus = flat_target_cpus, | 170 | .target_cpus = online_target_cpus, |
190 | .disable_esr = 0, | 171 | .disable_esr = 0, |
191 | .dest_logical = APIC_DEST_LOGICAL, | 172 | .dest_logical = APIC_DEST_LOGICAL, |
192 | .check_apicid_used = NULL, | 173 | .check_apicid_used = NULL, |
@@ -210,8 +191,7 @@ static struct apic apic_flat = { | |||
210 | .set_apic_id = set_apic_id, | 191 | .set_apic_id = set_apic_id, |
211 | .apic_id_mask = 0xFFu << 24, | 192 | .apic_id_mask = 0xFFu << 24, |
212 | 193 | ||
213 | .cpu_mask_to_apicid = default_cpu_mask_to_apicid, | 194 | .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and, |
214 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, | ||
215 | 195 | ||
216 | .send_IPI_mask = flat_send_IPI_mask, | 196 | .send_IPI_mask = flat_send_IPI_mask, |
217 | .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself, | 197 | .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself, |
@@ -262,17 +242,6 @@ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) | |||
262 | return 0; | 242 | return 0; |
263 | } | 243 | } |
264 | 244 | ||
265 | static const struct cpumask *physflat_target_cpus(void) | ||
266 | { | ||
267 | return cpu_online_mask; | ||
268 | } | ||
269 | |||
270 | static void physflat_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
271 | { | ||
272 | cpumask_clear(retmask); | ||
273 | cpumask_set_cpu(cpu, retmask); | ||
274 | } | ||
275 | |||
276 | static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector) | 245 | static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector) |
277 | { | 246 | { |
278 | default_send_IPI_mask_sequence_phys(cpumask, vector); | 247 | default_send_IPI_mask_sequence_phys(cpumask, vector); |
@@ -294,38 +263,6 @@ static void physflat_send_IPI_all(int vector) | |||
294 | physflat_send_IPI_mask(cpu_online_mask, vector); | 263 | physflat_send_IPI_mask(cpu_online_mask, vector); |
295 | } | 264 | } |
296 | 265 | ||
297 | static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask) | ||
298 | { | ||
299 | int cpu; | ||
300 | |||
301 | /* | ||
302 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
303 | * May as well be the first. | ||
304 | */ | ||
305 | cpu = cpumask_first(cpumask); | ||
306 | if ((unsigned)cpu < nr_cpu_ids) | ||
307 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
308 | else | ||
309 | return BAD_APICID; | ||
310 | } | ||
311 | |||
312 | static unsigned int | ||
313 | physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
314 | const struct cpumask *andmask) | ||
315 | { | ||
316 | int cpu; | ||
317 | |||
318 | /* | ||
319 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
320 | * May as well be the first. | ||
321 | */ | ||
322 | for_each_cpu_and(cpu, cpumask, andmask) { | ||
323 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | ||
324 | break; | ||
325 | } | ||
326 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
327 | } | ||
328 | |||
329 | static int physflat_probe(void) | 266 | static int physflat_probe(void) |
330 | { | 267 | { |
331 | if (apic == &apic_physflat || num_possible_cpus() > 8) | 268 | if (apic == &apic_physflat || num_possible_cpus() > 8) |
@@ -345,13 +282,13 @@ static struct apic apic_physflat = { | |||
345 | .irq_delivery_mode = dest_Fixed, | 282 | .irq_delivery_mode = dest_Fixed, |
346 | .irq_dest_mode = 0, /* physical */ | 283 | .irq_dest_mode = 0, /* physical */ |
347 | 284 | ||
348 | .target_cpus = physflat_target_cpus, | 285 | .target_cpus = online_target_cpus, |
349 | .disable_esr = 0, | 286 | .disable_esr = 0, |
350 | .dest_logical = 0, | 287 | .dest_logical = 0, |
351 | .check_apicid_used = NULL, | 288 | .check_apicid_used = NULL, |
352 | .check_apicid_present = NULL, | 289 | .check_apicid_present = NULL, |
353 | 290 | ||
354 | .vector_allocation_domain = physflat_vector_allocation_domain, | 291 | .vector_allocation_domain = default_vector_allocation_domain, |
355 | /* not needed, but shouldn't hurt: */ | 292 | /* not needed, but shouldn't hurt: */ |
356 | .init_apic_ldr = flat_init_apic_ldr, | 293 | .init_apic_ldr = flat_init_apic_ldr, |
357 | 294 | ||
@@ -370,8 +307,7 @@ static struct apic apic_physflat = { | |||
370 | .set_apic_id = set_apic_id, | 307 | .set_apic_id = set_apic_id, |
371 | .apic_id_mask = 0xFFu << 24, | 308 | .apic_id_mask = 0xFFu << 24, |
372 | 309 | ||
373 | .cpu_mask_to_apicid = physflat_cpu_mask_to_apicid, | 310 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, |
374 | .cpu_mask_to_apicid_and = physflat_cpu_mask_to_apicid_and, | ||
375 | 311 | ||
376 | .send_IPI_mask = physflat_send_IPI_mask, | 312 | .send_IPI_mask = physflat_send_IPI_mask, |
377 | .send_IPI_mask_allbutself = physflat_send_IPI_mask_allbutself, | 313 | .send_IPI_mask_allbutself = physflat_send_IPI_mask_allbutself, |
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c index a6e4c6e06c08..e145f28b4099 100644 --- a/arch/x86/kernel/apic/apic_noop.c +++ b/arch/x86/kernel/apic/apic_noop.c | |||
@@ -100,12 +100,12 @@ static unsigned long noop_check_apicid_present(int bit) | |||
100 | return physid_isset(bit, phys_cpu_present_map); | 100 | return physid_isset(bit, phys_cpu_present_map); |
101 | } | 101 | } |
102 | 102 | ||
103 | static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask) | 103 | static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask, |
104 | const struct cpumask *mask) | ||
104 | { | 105 | { |
105 | if (cpu != 0) | 106 | if (cpu != 0) |
106 | pr_warning("APIC: Vector allocated for non-BSP cpu\n"); | 107 | pr_warning("APIC: Vector allocated for non-BSP cpu\n"); |
107 | cpumask_clear(retmask); | 108 | cpumask_copy(retmask, cpumask_of(cpu)); |
108 | cpumask_set_cpu(cpu, retmask); | ||
109 | } | 109 | } |
110 | 110 | ||
111 | static u32 noop_apic_read(u32 reg) | 111 | static u32 noop_apic_read(u32 reg) |
@@ -159,8 +159,7 @@ struct apic apic_noop = { | |||
159 | .set_apic_id = NULL, | 159 | .set_apic_id = NULL, |
160 | .apic_id_mask = 0x0F << 24, | 160 | .apic_id_mask = 0x0F << 24, |
161 | 161 | ||
162 | .cpu_mask_to_apicid = default_cpu_mask_to_apicid, | 162 | .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and, |
163 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, | ||
164 | 163 | ||
165 | .send_IPI_mask = noop_send_IPI_mask, | 164 | .send_IPI_mask = noop_send_IPI_mask, |
166 | .send_IPI_mask_allbutself = noop_send_IPI_mask_allbutself, | 165 | .send_IPI_mask_allbutself = noop_send_IPI_mask_allbutself, |
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c index 6ec6d5d297c3..bc552cff2578 100644 --- a/arch/x86/kernel/apic/apic_numachip.c +++ b/arch/x86/kernel/apic/apic_numachip.c | |||
@@ -72,17 +72,6 @@ static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) | |||
72 | return initial_apic_id >> index_msb; | 72 | return initial_apic_id >> index_msb; |
73 | } | 73 | } |
74 | 74 | ||
75 | static const struct cpumask *numachip_target_cpus(void) | ||
76 | { | ||
77 | return cpu_online_mask; | ||
78 | } | ||
79 | |||
80 | static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
81 | { | ||
82 | cpumask_clear(retmask); | ||
83 | cpumask_set_cpu(cpu, retmask); | ||
84 | } | ||
85 | |||
86 | static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) | 75 | static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
87 | { | 76 | { |
88 | union numachip_csr_g3_ext_irq_gen int_gen; | 77 | union numachip_csr_g3_ext_irq_gen int_gen; |
@@ -157,38 +146,6 @@ static void numachip_send_IPI_self(int vector) | |||
157 | __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL); | 146 | __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL); |
158 | } | 147 | } |
159 | 148 | ||
160 | static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask) | ||
161 | { | ||
162 | int cpu; | ||
163 | |||
164 | /* | ||
165 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
166 | * May as well be the first. | ||
167 | */ | ||
168 | cpu = cpumask_first(cpumask); | ||
169 | if (likely((unsigned)cpu < nr_cpu_ids)) | ||
170 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
171 | |||
172 | return BAD_APICID; | ||
173 | } | ||
174 | |||
175 | static unsigned int | ||
176 | numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
177 | const struct cpumask *andmask) | ||
178 | { | ||
179 | int cpu; | ||
180 | |||
181 | /* | ||
182 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
183 | * May as well be the first. | ||
184 | */ | ||
185 | for_each_cpu_and(cpu, cpumask, andmask) { | ||
186 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | ||
187 | break; | ||
188 | } | ||
189 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
190 | } | ||
191 | |||
192 | static int __init numachip_probe(void) | 149 | static int __init numachip_probe(void) |
193 | { | 150 | { |
194 | return apic == &apic_numachip; | 151 | return apic == &apic_numachip; |
@@ -253,13 +210,13 @@ static struct apic apic_numachip __refconst = { | |||
253 | .irq_delivery_mode = dest_Fixed, | 210 | .irq_delivery_mode = dest_Fixed, |
254 | .irq_dest_mode = 0, /* physical */ | 211 | .irq_dest_mode = 0, /* physical */ |
255 | 212 | ||
256 | .target_cpus = numachip_target_cpus, | 213 | .target_cpus = online_target_cpus, |
257 | .disable_esr = 0, | 214 | .disable_esr = 0, |
258 | .dest_logical = 0, | 215 | .dest_logical = 0, |
259 | .check_apicid_used = NULL, | 216 | .check_apicid_used = NULL, |
260 | .check_apicid_present = NULL, | 217 | .check_apicid_present = NULL, |
261 | 218 | ||
262 | .vector_allocation_domain = numachip_vector_allocation_domain, | 219 | .vector_allocation_domain = default_vector_allocation_domain, |
263 | .init_apic_ldr = flat_init_apic_ldr, | 220 | .init_apic_ldr = flat_init_apic_ldr, |
264 | 221 | ||
265 | .ioapic_phys_id_map = NULL, | 222 | .ioapic_phys_id_map = NULL, |
@@ -277,8 +234,7 @@ static struct apic apic_numachip __refconst = { | |||
277 | .set_apic_id = set_apic_id, | 234 | .set_apic_id = set_apic_id, |
278 | .apic_id_mask = 0xffU << 24, | 235 | .apic_id_mask = 0xffU << 24, |
279 | 236 | ||
280 | .cpu_mask_to_apicid = numachip_cpu_mask_to_apicid, | 237 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, |
281 | .cpu_mask_to_apicid_and = numachip_cpu_mask_to_apicid_and, | ||
282 | 238 | ||
283 | .send_IPI_mask = numachip_send_IPI_mask, | 239 | .send_IPI_mask = numachip_send_IPI_mask, |
284 | .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, | 240 | .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, |
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c index 31fbdbfbf960..d50e3640d5ae 100644 --- a/arch/x86/kernel/apic/bigsmp_32.c +++ b/arch/x86/kernel/apic/bigsmp_32.c | |||
@@ -26,15 +26,6 @@ static int bigsmp_apic_id_registered(void) | |||
26 | return 1; | 26 | return 1; |
27 | } | 27 | } |
28 | 28 | ||
29 | static const struct cpumask *bigsmp_target_cpus(void) | ||
30 | { | ||
31 | #ifdef CONFIG_SMP | ||
32 | return cpu_online_mask; | ||
33 | #else | ||
34 | return cpumask_of(0); | ||
35 | #endif | ||
36 | } | ||
37 | |||
38 | static unsigned long bigsmp_check_apicid_used(physid_mask_t *map, int apicid) | 29 | static unsigned long bigsmp_check_apicid_used(physid_mask_t *map, int apicid) |
39 | { | 30 | { |
40 | return 0; | 31 | return 0; |
@@ -105,32 +96,6 @@ static int bigsmp_check_phys_apicid_present(int phys_apicid) | |||
105 | return 1; | 96 | return 1; |
106 | } | 97 | } |
107 | 98 | ||
108 | /* As we are using single CPU as destination, pick only one CPU here */ | ||
109 | static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask) | ||
110 | { | ||
111 | int cpu = cpumask_first(cpumask); | ||
112 | |||
113 | if (cpu < nr_cpu_ids) | ||
114 | return cpu_physical_id(cpu); | ||
115 | return BAD_APICID; | ||
116 | } | ||
117 | |||
118 | static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
119 | const struct cpumask *andmask) | ||
120 | { | ||
121 | int cpu; | ||
122 | |||
123 | /* | ||
124 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
125 | * May as well be the first. | ||
126 | */ | ||
127 | for_each_cpu_and(cpu, cpumask, andmask) { | ||
128 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | ||
129 | return cpu_physical_id(cpu); | ||
130 | } | ||
131 | return BAD_APICID; | ||
132 | } | ||
133 | |||
134 | static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) | 99 | static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb) |
135 | { | 100 | { |
136 | return cpuid_apic >> index_msb; | 101 | return cpuid_apic >> index_msb; |
@@ -177,12 +142,6 @@ static const struct dmi_system_id bigsmp_dmi_table[] = { | |||
177 | { } /* NULL entry stops DMI scanning */ | 142 | { } /* NULL entry stops DMI scanning */ |
178 | }; | 143 | }; |
179 | 144 | ||
180 | static void bigsmp_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
181 | { | ||
182 | cpumask_clear(retmask); | ||
183 | cpumask_set_cpu(cpu, retmask); | ||
184 | } | ||
185 | |||
186 | static int probe_bigsmp(void) | 145 | static int probe_bigsmp(void) |
187 | { | 146 | { |
188 | if (def_to_bigsmp) | 147 | if (def_to_bigsmp) |
@@ -205,13 +164,13 @@ static struct apic apic_bigsmp = { | |||
205 | /* phys delivery to target CPU: */ | 164 | /* phys delivery to target CPU: */ |
206 | .irq_dest_mode = 0, | 165 | .irq_dest_mode = 0, |
207 | 166 | ||
208 | .target_cpus = bigsmp_target_cpus, | 167 | .target_cpus = default_target_cpus, |
209 | .disable_esr = 1, | 168 | .disable_esr = 1, |
210 | .dest_logical = 0, | 169 | .dest_logical = 0, |
211 | .check_apicid_used = bigsmp_check_apicid_used, | 170 | .check_apicid_used = bigsmp_check_apicid_used, |
212 | .check_apicid_present = bigsmp_check_apicid_present, | 171 | .check_apicid_present = bigsmp_check_apicid_present, |
213 | 172 | ||
214 | .vector_allocation_domain = bigsmp_vector_allocation_domain, | 173 | .vector_allocation_domain = default_vector_allocation_domain, |
215 | .init_apic_ldr = bigsmp_init_apic_ldr, | 174 | .init_apic_ldr = bigsmp_init_apic_ldr, |
216 | 175 | ||
217 | .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, | 176 | .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, |
@@ -229,8 +188,7 @@ static struct apic apic_bigsmp = { | |||
229 | .set_apic_id = NULL, | 188 | .set_apic_id = NULL, |
230 | .apic_id_mask = 0xFF << 24, | 189 | .apic_id_mask = 0xFF << 24, |
231 | 190 | ||
232 | .cpu_mask_to_apicid = bigsmp_cpu_mask_to_apicid, | 191 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, |
233 | .cpu_mask_to_apicid_and = bigsmp_cpu_mask_to_apicid_and, | ||
234 | 192 | ||
235 | .send_IPI_mask = bigsmp_send_IPI_mask, | 193 | .send_IPI_mask = bigsmp_send_IPI_mask, |
236 | .send_IPI_mask_allbutself = NULL, | 194 | .send_IPI_mask_allbutself = NULL, |
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c index db4ab1be3c79..0874799a98c6 100644 --- a/arch/x86/kernel/apic/es7000_32.c +++ b/arch/x86/kernel/apic/es7000_32.c | |||
@@ -394,21 +394,6 @@ static void es7000_enable_apic_mode(void) | |||
394 | WARN(1, "Command failed, status = %x\n", mip_status); | 394 | WARN(1, "Command failed, status = %x\n", mip_status); |
395 | } | 395 | } |
396 | 396 | ||
397 | static void es7000_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
398 | { | ||
399 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
400 | * specified in the interrupt destination when using lowest | ||
401 | * priority interrupt delivery mode. | ||
402 | * | ||
403 | * In particular there was a hyperthreading cpu observed to | ||
404 | * deliver interrupts to the wrong hyperthread when only one | ||
405 | * hyperthread was specified in the interrupt desitination. | ||
406 | */ | ||
407 | cpumask_clear(retmask); | ||
408 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
409 | } | ||
410 | |||
411 | |||
412 | static void es7000_wait_for_init_deassert(atomic_t *deassert) | 397 | static void es7000_wait_for_init_deassert(atomic_t *deassert) |
413 | { | 398 | { |
414 | while (!atomic_read(deassert)) | 399 | while (!atomic_read(deassert)) |
@@ -540,45 +525,49 @@ static int es7000_check_phys_apicid_present(int cpu_physical_apicid) | |||
540 | return 1; | 525 | return 1; |
541 | } | 526 | } |
542 | 527 | ||
543 | static unsigned int es7000_cpu_mask_to_apicid(const struct cpumask *cpumask) | 528 | static inline int |
529 | es7000_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id) | ||
544 | { | 530 | { |
545 | unsigned int round = 0; | 531 | unsigned int round = 0; |
546 | int cpu, uninitialized_var(apicid); | 532 | unsigned int cpu, uninitialized_var(apicid); |
547 | 533 | ||
548 | /* | 534 | /* |
549 | * The cpus in the mask must all be on the apic cluster. | 535 | * The cpus in the mask must all be on the apic cluster. |
550 | */ | 536 | */ |
551 | for_each_cpu(cpu, cpumask) { | 537 | for_each_cpu_and(cpu, cpumask, cpu_online_mask) { |
552 | int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); | 538 | int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
553 | 539 | ||
554 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { | 540 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { |
555 | WARN(1, "Not a valid mask!"); | 541 | WARN(1, "Not a valid mask!"); |
556 | 542 | ||
557 | return BAD_APICID; | 543 | return -EINVAL; |
558 | } | 544 | } |
559 | apicid = new_apicid; | 545 | apicid |= new_apicid; |
560 | round++; | 546 | round++; |
561 | } | 547 | } |
562 | return apicid; | 548 | if (!round) |
549 | return -EINVAL; | ||
550 | *dest_id = apicid; | ||
551 | return 0; | ||
563 | } | 552 | } |
564 | 553 | ||
565 | static unsigned int | 554 | static int |
566 | es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask, | 555 | es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask, |
567 | const struct cpumask *andmask) | 556 | const struct cpumask *andmask, |
557 | unsigned int *apicid) | ||
568 | { | 558 | { |
569 | int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); | ||
570 | cpumask_var_t cpumask; | 559 | cpumask_var_t cpumask; |
560 | *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); | ||
571 | 561 | ||
572 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) | 562 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) |
573 | return apicid; | 563 | return 0; |
574 | 564 | ||
575 | cpumask_and(cpumask, inmask, andmask); | 565 | cpumask_and(cpumask, inmask, andmask); |
576 | cpumask_and(cpumask, cpumask, cpu_online_mask); | 566 | es7000_cpu_mask_to_apicid(cpumask, apicid); |
577 | apicid = es7000_cpu_mask_to_apicid(cpumask); | ||
578 | 567 | ||
579 | free_cpumask_var(cpumask); | 568 | free_cpumask_var(cpumask); |
580 | 569 | ||
581 | return apicid; | 570 | return 0; |
582 | } | 571 | } |
583 | 572 | ||
584 | static int es7000_phys_pkg_id(int cpuid_apic, int index_msb) | 573 | static int es7000_phys_pkg_id(int cpuid_apic, int index_msb) |
@@ -638,7 +627,7 @@ static struct apic __refdata apic_es7000_cluster = { | |||
638 | .check_apicid_used = es7000_check_apicid_used, | 627 | .check_apicid_used = es7000_check_apicid_used, |
639 | .check_apicid_present = es7000_check_apicid_present, | 628 | .check_apicid_present = es7000_check_apicid_present, |
640 | 629 | ||
641 | .vector_allocation_domain = es7000_vector_allocation_domain, | 630 | .vector_allocation_domain = flat_vector_allocation_domain, |
642 | .init_apic_ldr = es7000_init_apic_ldr_cluster, | 631 | .init_apic_ldr = es7000_init_apic_ldr_cluster, |
643 | 632 | ||
644 | .ioapic_phys_id_map = es7000_ioapic_phys_id_map, | 633 | .ioapic_phys_id_map = es7000_ioapic_phys_id_map, |
@@ -656,7 +645,6 @@ static struct apic __refdata apic_es7000_cluster = { | |||
656 | .set_apic_id = NULL, | 645 | .set_apic_id = NULL, |
657 | .apic_id_mask = 0xFF << 24, | 646 | .apic_id_mask = 0xFF << 24, |
658 | 647 | ||
659 | .cpu_mask_to_apicid = es7000_cpu_mask_to_apicid, | ||
660 | .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and, | 648 | .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and, |
661 | 649 | ||
662 | .send_IPI_mask = es7000_send_IPI_mask, | 650 | .send_IPI_mask = es7000_send_IPI_mask, |
@@ -705,7 +693,7 @@ static struct apic __refdata apic_es7000 = { | |||
705 | .check_apicid_used = es7000_check_apicid_used, | 693 | .check_apicid_used = es7000_check_apicid_used, |
706 | .check_apicid_present = es7000_check_apicid_present, | 694 | .check_apicid_present = es7000_check_apicid_present, |
707 | 695 | ||
708 | .vector_allocation_domain = es7000_vector_allocation_domain, | 696 | .vector_allocation_domain = flat_vector_allocation_domain, |
709 | .init_apic_ldr = es7000_init_apic_ldr, | 697 | .init_apic_ldr = es7000_init_apic_ldr, |
710 | 698 | ||
711 | .ioapic_phys_id_map = es7000_ioapic_phys_id_map, | 699 | .ioapic_phys_id_map = es7000_ioapic_phys_id_map, |
@@ -723,7 +711,6 @@ static struct apic __refdata apic_es7000 = { | |||
723 | .set_apic_id = NULL, | 711 | .set_apic_id = NULL, |
724 | .apic_id_mask = 0xFF << 24, | 712 | .apic_id_mask = 0xFF << 24, |
725 | 713 | ||
726 | .cpu_mask_to_apicid = es7000_cpu_mask_to_apicid, | ||
727 | .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and, | 714 | .cpu_mask_to_apicid_and = es7000_cpu_mask_to_apicid_and, |
728 | 715 | ||
729 | .send_IPI_mask = es7000_send_IPI_mask, | 716 | .send_IPI_mask = es7000_send_IPI_mask, |
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 5f0ff597437c..406eee784684 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c | |||
@@ -448,8 +448,8 @@ static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pi | |||
448 | 448 | ||
449 | entry = alloc_irq_pin_list(node); | 449 | entry = alloc_irq_pin_list(node); |
450 | if (!entry) { | 450 | if (!entry) { |
451 | printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", | 451 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
452 | node, apic, pin); | 452 | node, apic, pin); |
453 | return -ENOMEM; | 453 | return -ENOMEM; |
454 | } | 454 | } |
455 | entry->apic = apic; | 455 | entry->apic = apic; |
@@ -661,7 +661,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) | |||
661 | ioapic_mask_entry(apic, pin); | 661 | ioapic_mask_entry(apic, pin); |
662 | entry = ioapic_read_entry(apic, pin); | 662 | entry = ioapic_read_entry(apic, pin); |
663 | if (entry.irr) | 663 | if (entry.irr) |
664 | printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n", | 664 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
665 | mpc_ioapic_id(apic), pin); | 665 | mpc_ioapic_id(apic), pin); |
666 | } | 666 | } |
667 | 667 | ||
@@ -895,7 +895,7 @@ static int irq_polarity(int idx) | |||
895 | } | 895 | } |
896 | case 2: /* reserved */ | 896 | case 2: /* reserved */ |
897 | { | 897 | { |
898 | printk(KERN_WARNING "broken BIOS!!\n"); | 898 | pr_warn("broken BIOS!!\n"); |
899 | polarity = 1; | 899 | polarity = 1; |
900 | break; | 900 | break; |
901 | } | 901 | } |
@@ -906,7 +906,7 @@ static int irq_polarity(int idx) | |||
906 | } | 906 | } |
907 | default: /* invalid */ | 907 | default: /* invalid */ |
908 | { | 908 | { |
909 | printk(KERN_WARNING "broken BIOS!!\n"); | 909 | pr_warn("broken BIOS!!\n"); |
910 | polarity = 1; | 910 | polarity = 1; |
911 | break; | 911 | break; |
912 | } | 912 | } |
@@ -948,7 +948,7 @@ static int irq_trigger(int idx) | |||
948 | } | 948 | } |
949 | default: | 949 | default: |
950 | { | 950 | { |
951 | printk(KERN_WARNING "broken BIOS!!\n"); | 951 | pr_warn("broken BIOS!!\n"); |
952 | trigger = 1; | 952 | trigger = 1; |
953 | break; | 953 | break; |
954 | } | 954 | } |
@@ -962,7 +962,7 @@ static int irq_trigger(int idx) | |||
962 | } | 962 | } |
963 | case 2: /* reserved */ | 963 | case 2: /* reserved */ |
964 | { | 964 | { |
965 | printk(KERN_WARNING "broken BIOS!!\n"); | 965 | pr_warn("broken BIOS!!\n"); |
966 | trigger = 1; | 966 | trigger = 1; |
967 | break; | 967 | break; |
968 | } | 968 | } |
@@ -973,7 +973,7 @@ static int irq_trigger(int idx) | |||
973 | } | 973 | } |
974 | default: /* invalid */ | 974 | default: /* invalid */ |
975 | { | 975 | { |
976 | printk(KERN_WARNING "broken BIOS!!\n"); | 976 | pr_warn("broken BIOS!!\n"); |
977 | trigger = 0; | 977 | trigger = 0; |
978 | break; | 978 | break; |
979 | } | 979 | } |
@@ -991,7 +991,7 @@ static int pin_2_irq(int idx, int apic, int pin) | |||
991 | * Debugging check, we are in big trouble if this message pops up! | 991 | * Debugging check, we are in big trouble if this message pops up! |
992 | */ | 992 | */ |
993 | if (mp_irqs[idx].dstirq != pin) | 993 | if (mp_irqs[idx].dstirq != pin) |
994 | printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); | 994 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
995 | 995 | ||
996 | if (test_bit(bus, mp_bus_not_pci)) { | 996 | if (test_bit(bus, mp_bus_not_pci)) { |
997 | irq = mp_irqs[idx].srcbusirq; | 997 | irq = mp_irqs[idx].srcbusirq; |
@@ -1112,8 +1112,7 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |||
1112 | * 0x80, because int 0x80 is hm, kind of importantish. ;) | 1112 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
1113 | */ | 1113 | */ |
1114 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; | 1114 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
1115 | static int current_offset = VECTOR_OFFSET_START % 8; | 1115 | static int current_offset = VECTOR_OFFSET_START % 16; |
1116 | unsigned int old_vector; | ||
1117 | int cpu, err; | 1116 | int cpu, err; |
1118 | cpumask_var_t tmp_mask; | 1117 | cpumask_var_t tmp_mask; |
1119 | 1118 | ||
@@ -1123,35 +1122,45 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) | |||
1123 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) | 1122 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
1124 | return -ENOMEM; | 1123 | return -ENOMEM; |
1125 | 1124 | ||
1126 | old_vector = cfg->vector; | ||
1127 | if (old_vector) { | ||
1128 | cpumask_and(tmp_mask, mask, cpu_online_mask); | ||
1129 | cpumask_and(tmp_mask, cfg->domain, tmp_mask); | ||
1130 | if (!cpumask_empty(tmp_mask)) { | ||
1131 | free_cpumask_var(tmp_mask); | ||
1132 | return 0; | ||
1133 | } | ||
1134 | } | ||
1135 | |||
1136 | /* Only try and allocate irqs on cpus that are present */ | 1125 | /* Only try and allocate irqs on cpus that are present */ |
1137 | err = -ENOSPC; | 1126 | err = -ENOSPC; |
1138 | for_each_cpu_and(cpu, mask, cpu_online_mask) { | 1127 | cpumask_clear(cfg->old_domain); |
1139 | int new_cpu; | 1128 | cpu = cpumask_first_and(mask, cpu_online_mask); |
1140 | int vector, offset; | 1129 | while (cpu < nr_cpu_ids) { |
1130 | int new_cpu, vector, offset; | ||
1141 | 1131 | ||
1142 | apic->vector_allocation_domain(cpu, tmp_mask); | 1132 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
1133 | |||
1134 | if (cpumask_subset(tmp_mask, cfg->domain)) { | ||
1135 | err = 0; | ||
1136 | if (cpumask_equal(tmp_mask, cfg->domain)) | ||
1137 | break; | ||
1138 | /* | ||
1139 | * New cpumask using the vector is a proper subset of | ||
1140 | * the current in use mask. So cleanup the vector | ||
1141 | * allocation for the members that are not used anymore. | ||
1142 | */ | ||
1143 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); | ||
1144 | cfg->move_in_progress = 1; | ||
1145 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); | ||
1146 | break; | ||
1147 | } | ||
1143 | 1148 | ||
1144 | vector = current_vector; | 1149 | vector = current_vector; |
1145 | offset = current_offset; | 1150 | offset = current_offset; |
1146 | next: | 1151 | next: |
1147 | vector += 8; | 1152 | vector += 16; |
1148 | if (vector >= first_system_vector) { | 1153 | if (vector >= first_system_vector) { |
1149 | /* If out of vectors on large boxen, must share them. */ | 1154 | offset = (offset + 1) % 16; |
1150 | offset = (offset + 1) % 8; | ||
1151 | vector = FIRST_EXTERNAL_VECTOR + offset; | 1155 | vector = FIRST_EXTERNAL_VECTOR + offset; |
1152 | } | 1156 | } |
1153 | if (unlikely(current_vector == vector)) | 1157 | |
1158 | if (unlikely(current_vector == vector)) { | ||
1159 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); | ||
1160 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); | ||
1161 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); | ||
1154 | continue; | 1162 | continue; |
1163 | } | ||
1155 | 1164 | ||
1156 | if (test_bit(vector, used_vectors)) | 1165 | if (test_bit(vector, used_vectors)) |
1157 | goto next; | 1166 | goto next; |
@@ -1162,7 +1171,7 @@ next: | |||
1162 | /* Found one! */ | 1171 | /* Found one! */ |
1163 | current_vector = vector; | 1172 | current_vector = vector; |
1164 | current_offset = offset; | 1173 | current_offset = offset; |
1165 | if (old_vector) { | 1174 | if (cfg->vector) { |
1166 | cfg->move_in_progress = 1; | 1175 | cfg->move_in_progress = 1; |
1167 | cpumask_copy(cfg->old_domain, cfg->domain); | 1176 | cpumask_copy(cfg->old_domain, cfg->domain); |
1168 | } | 1177 | } |
@@ -1346,18 +1355,18 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, | |||
1346 | 1355 | ||
1347 | if (!IO_APIC_IRQ(irq)) | 1356 | if (!IO_APIC_IRQ(irq)) |
1348 | return; | 1357 | return; |
1349 | /* | ||
1350 | * For legacy irqs, cfg->domain starts with cpu 0 for legacy | ||
1351 | * controllers like 8259. Now that IO-APIC can handle this irq, update | ||
1352 | * the cfg->domain. | ||
1353 | */ | ||
1354 | if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) | ||
1355 | apic->vector_allocation_domain(0, cfg->domain); | ||
1356 | 1358 | ||
1357 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) | 1359 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
1358 | return; | 1360 | return; |
1359 | 1361 | ||
1360 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); | 1362 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
1363 | &dest)) { | ||
1364 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", | ||
1365 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | ||
1366 | __clear_irq_vector(irq, cfg); | ||
1367 | |||
1368 | return; | ||
1369 | } | ||
1361 | 1370 | ||
1362 | apic_printk(APIC_VERBOSE,KERN_DEBUG | 1371 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
1363 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " | 1372 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " |
@@ -1366,7 +1375,7 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, | |||
1366 | cfg->vector, irq, attr->trigger, attr->polarity, dest); | 1375 | cfg->vector, irq, attr->trigger, attr->polarity, dest); |
1367 | 1376 | ||
1368 | if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) { | 1377 | if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) { |
1369 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", | 1378 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
1370 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); | 1379 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
1371 | __clear_irq_vector(irq, cfg); | 1380 | __clear_irq_vector(irq, cfg); |
1372 | 1381 | ||
@@ -1469,9 +1478,10 @@ void setup_IO_APIC_irq_extra(u32 gsi) | |||
1469 | * Set up the timer pin, possibly with the 8259A-master behind. | 1478 | * Set up the timer pin, possibly with the 8259A-master behind. |
1470 | */ | 1479 | */ |
1471 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, | 1480 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
1472 | unsigned int pin, int vector) | 1481 | unsigned int pin, int vector) |
1473 | { | 1482 | { |
1474 | struct IO_APIC_route_entry entry; | 1483 | struct IO_APIC_route_entry entry; |
1484 | unsigned int dest; | ||
1475 | 1485 | ||
1476 | if (irq_remapping_enabled) | 1486 | if (irq_remapping_enabled) |
1477 | return; | 1487 | return; |
@@ -1482,9 +1492,13 @@ static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, | |||
1482 | * We use logical delivery to get the timer IRQ | 1492 | * We use logical delivery to get the timer IRQ |
1483 | * to the first CPU. | 1493 | * to the first CPU. |
1484 | */ | 1494 | */ |
1495 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), | ||
1496 | apic->target_cpus(), &dest))) | ||
1497 | dest = BAD_APICID; | ||
1498 | |||
1485 | entry.dest_mode = apic->irq_dest_mode; | 1499 | entry.dest_mode = apic->irq_dest_mode; |
1486 | entry.mask = 0; /* don't mask IRQ for edge */ | 1500 | entry.mask = 0; /* don't mask IRQ for edge */ |
1487 | entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); | 1501 | entry.dest = dest; |
1488 | entry.delivery_mode = apic->irq_delivery_mode; | 1502 | entry.delivery_mode = apic->irq_delivery_mode; |
1489 | entry.polarity = 0; | 1503 | entry.polarity = 0; |
1490 | entry.trigger = 0; | 1504 | entry.trigger = 0; |
@@ -1521,7 +1535,6 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx) | |||
1521 | reg_03.raw = io_apic_read(ioapic_idx, 3); | 1535 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
1522 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | 1536 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
1523 | 1537 | ||
1524 | printk("\n"); | ||
1525 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); | 1538 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
1526 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); | 1539 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
1527 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); | 1540 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
@@ -1578,7 +1591,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx) | |||
1578 | i, | 1591 | i, |
1579 | ir_entry->index | 1592 | ir_entry->index |
1580 | ); | 1593 | ); |
1581 | printk("%1d %1d %1d %1d %1d " | 1594 | pr_cont("%1d %1d %1d %1d %1d " |
1582 | "%1d %1d %X %02X\n", | 1595 | "%1d %1d %X %02X\n", |
1583 | ir_entry->format, | 1596 | ir_entry->format, |
1584 | ir_entry->mask, | 1597 | ir_entry->mask, |
@@ -1598,7 +1611,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx) | |||
1598 | i, | 1611 | i, |
1599 | entry.dest | 1612 | entry.dest |
1600 | ); | 1613 | ); |
1601 | printk("%1d %1d %1d %1d %1d " | 1614 | pr_cont("%1d %1d %1d %1d %1d " |
1602 | "%1d %1d %02X\n", | 1615 | "%1d %1d %02X\n", |
1603 | entry.mask, | 1616 | entry.mask, |
1604 | entry.trigger, | 1617 | entry.trigger, |
@@ -1651,8 +1664,8 @@ __apicdebuginit(void) print_IO_APICs(void) | |||
1651 | continue; | 1664 | continue; |
1652 | printk(KERN_DEBUG "IRQ%d ", irq); | 1665 | printk(KERN_DEBUG "IRQ%d ", irq); |
1653 | for_each_irq_pin(entry, cfg->irq_2_pin) | 1666 | for_each_irq_pin(entry, cfg->irq_2_pin) |
1654 | printk("-> %d:%d", entry->apic, entry->pin); | 1667 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
1655 | printk("\n"); | 1668 | pr_cont("\n"); |
1656 | } | 1669 | } |
1657 | 1670 | ||
1658 | printk(KERN_INFO ".................................... done.\n"); | 1671 | printk(KERN_INFO ".................................... done.\n"); |
@@ -1665,9 +1678,9 @@ __apicdebuginit(void) print_APIC_field(int base) | |||
1665 | printk(KERN_DEBUG); | 1678 | printk(KERN_DEBUG); |
1666 | 1679 | ||
1667 | for (i = 0; i < 8; i++) | 1680 | for (i = 0; i < 8; i++) |
1668 | printk(KERN_CONT "%08x", apic_read(base + i*0x10)); | 1681 | pr_cont("%08x", apic_read(base + i*0x10)); |
1669 | 1682 | ||
1670 | printk(KERN_CONT "\n"); | 1683 | pr_cont("\n"); |
1671 | } | 1684 | } |
1672 | 1685 | ||
1673 | __apicdebuginit(void) print_local_APIC(void *dummy) | 1686 | __apicdebuginit(void) print_local_APIC(void *dummy) |
@@ -1769,7 +1782,7 @@ __apicdebuginit(void) print_local_APIC(void *dummy) | |||
1769 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); | 1782 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); |
1770 | } | 1783 | } |
1771 | } | 1784 | } |
1772 | printk("\n"); | 1785 | pr_cont("\n"); |
1773 | } | 1786 | } |
1774 | 1787 | ||
1775 | __apicdebuginit(void) print_local_APICs(int maxcpu) | 1788 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
@@ -2065,7 +2078,7 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void) | |||
2065 | reg_00.raw = io_apic_read(ioapic_idx, 0); | 2078 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
2066 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | 2079 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
2067 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) | 2080 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
2068 | printk("could not set ID!\n"); | 2081 | pr_cont("could not set ID!\n"); |
2069 | else | 2082 | else |
2070 | apic_printk(APIC_VERBOSE, " ok.\n"); | 2083 | apic_printk(APIC_VERBOSE, " ok.\n"); |
2071 | } | 2084 | } |
@@ -2210,71 +2223,6 @@ void send_cleanup_vector(struct irq_cfg *cfg) | |||
2210 | cfg->move_in_progress = 0; | 2223 | cfg->move_in_progress = 0; |
2211 | } | 2224 | } |
2212 | 2225 | ||
2213 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) | ||
2214 | { | ||
2215 | int apic, pin; | ||
2216 | struct irq_pin_list *entry; | ||
2217 | u8 vector = cfg->vector; | ||
2218 | |||
2219 | for_each_irq_pin(entry, cfg->irq_2_pin) { | ||
2220 | unsigned int reg; | ||
2221 | |||
2222 | apic = entry->apic; | ||
2223 | pin = entry->pin; | ||
2224 | /* | ||
2225 | * With interrupt-remapping, destination information comes | ||
2226 | * from interrupt-remapping table entry. | ||
2227 | */ | ||
2228 | if (!irq_remapped(cfg)) | ||
2229 | io_apic_write(apic, 0x11 + pin*2, dest); | ||
2230 | reg = io_apic_read(apic, 0x10 + pin*2); | ||
2231 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | ||
2232 | reg |= vector; | ||
2233 | io_apic_modify(apic, 0x10 + pin*2, reg); | ||
2234 | } | ||
2235 | } | ||
2236 | |||
2237 | /* | ||
2238 | * Either sets data->affinity to a valid value, and returns | ||
2239 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | ||
2240 | * leaves data->affinity untouched. | ||
2241 | */ | ||
2242 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | ||
2243 | unsigned int *dest_id) | ||
2244 | { | ||
2245 | struct irq_cfg *cfg = data->chip_data; | ||
2246 | |||
2247 | if (!cpumask_intersects(mask, cpu_online_mask)) | ||
2248 | return -1; | ||
2249 | |||
2250 | if (assign_irq_vector(data->irq, data->chip_data, mask)) | ||
2251 | return -1; | ||
2252 | |||
2253 | cpumask_copy(data->affinity, mask); | ||
2254 | |||
2255 | *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); | ||
2256 | return 0; | ||
2257 | } | ||
2258 | |||
2259 | static int | ||
2260 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | ||
2261 | bool force) | ||
2262 | { | ||
2263 | unsigned int dest, irq = data->irq; | ||
2264 | unsigned long flags; | ||
2265 | int ret; | ||
2266 | |||
2267 | raw_spin_lock_irqsave(&ioapic_lock, flags); | ||
2268 | ret = __ioapic_set_affinity(data, mask, &dest); | ||
2269 | if (!ret) { | ||
2270 | /* Only the high 8 bits are valid. */ | ||
2271 | dest = SET_APIC_LOGICAL_ID(dest); | ||
2272 | __target_IO_APIC_irq(irq, dest, data->chip_data); | ||
2273 | } | ||
2274 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | ||
2275 | return ret; | ||
2276 | } | ||
2277 | |||
2278 | asmlinkage void smp_irq_move_cleanup_interrupt(void) | 2226 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
2279 | { | 2227 | { |
2280 | unsigned vector, me; | 2228 | unsigned vector, me; |
@@ -2362,6 +2310,87 @@ void irq_force_complete_move(int irq) | |||
2362 | static inline void irq_complete_move(struct irq_cfg *cfg) { } | 2310 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
2363 | #endif | 2311 | #endif |
2364 | 2312 | ||
2313 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) | ||
2314 | { | ||
2315 | int apic, pin; | ||
2316 | struct irq_pin_list *entry; | ||
2317 | u8 vector = cfg->vector; | ||
2318 | |||
2319 | for_each_irq_pin(entry, cfg->irq_2_pin) { | ||
2320 | unsigned int reg; | ||
2321 | |||
2322 | apic = entry->apic; | ||
2323 | pin = entry->pin; | ||
2324 | /* | ||
2325 | * With interrupt-remapping, destination information comes | ||
2326 | * from interrupt-remapping table entry. | ||
2327 | */ | ||
2328 | if (!irq_remapped(cfg)) | ||
2329 | io_apic_write(apic, 0x11 + pin*2, dest); | ||
2330 | reg = io_apic_read(apic, 0x10 + pin*2); | ||
2331 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; | ||
2332 | reg |= vector; | ||
2333 | io_apic_modify(apic, 0x10 + pin*2, reg); | ||
2334 | } | ||
2335 | } | ||
2336 | |||
2337 | /* | ||
2338 | * Either sets data->affinity to a valid value, and returns | ||
2339 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and | ||
2340 | * leaves data->affinity untouched. | ||
2341 | */ | ||
2342 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | ||
2343 | unsigned int *dest_id) | ||
2344 | { | ||
2345 | struct irq_cfg *cfg = data->chip_data; | ||
2346 | unsigned int irq = data->irq; | ||
2347 | int err; | ||
2348 | |||
2349 | if (!config_enabled(CONFIG_SMP)) | ||
2350 | return -1; | ||
2351 | |||
2352 | if (!cpumask_intersects(mask, cpu_online_mask)) | ||
2353 | return -EINVAL; | ||
2354 | |||
2355 | err = assign_irq_vector(irq, cfg, mask); | ||
2356 | if (err) | ||
2357 | return err; | ||
2358 | |||
2359 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); | ||
2360 | if (err) { | ||
2361 | if (assign_irq_vector(irq, cfg, data->affinity)) | ||
2362 | pr_err("Failed to recover vector for irq %d\n", irq); | ||
2363 | return err; | ||
2364 | } | ||
2365 | |||
2366 | cpumask_copy(data->affinity, mask); | ||
2367 | |||
2368 | return 0; | ||
2369 | } | ||
2370 | |||
2371 | static int | ||
2372 | ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, | ||
2373 | bool force) | ||
2374 | { | ||
2375 | unsigned int dest, irq = data->irq; | ||
2376 | unsigned long flags; | ||
2377 | int ret; | ||
2378 | |||
2379 | if (!config_enabled(CONFIG_SMP)) | ||
2380 | return -1; | ||
2381 | |||
2382 | raw_spin_lock_irqsave(&ioapic_lock, flags); | ||
2383 | ret = __ioapic_set_affinity(data, mask, &dest); | ||
2384 | if (!ret) { | ||
2385 | /* Only the high 8 bits are valid. */ | ||
2386 | dest = SET_APIC_LOGICAL_ID(dest); | ||
2387 | __target_IO_APIC_irq(irq, dest, data->chip_data); | ||
2388 | ret = IRQ_SET_MASK_OK_NOCOPY; | ||
2389 | } | ||
2390 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | ||
2391 | return ret; | ||
2392 | } | ||
2393 | |||
2365 | static void ack_apic_edge(struct irq_data *data) | 2394 | static void ack_apic_edge(struct irq_data *data) |
2366 | { | 2395 | { |
2367 | irq_complete_move(data->chip_data); | 2396 | irq_complete_move(data->chip_data); |
@@ -2541,9 +2570,7 @@ static void irq_remap_modify_chip_defaults(struct irq_chip *chip) | |||
2541 | chip->irq_ack = ir_ack_apic_edge; | 2570 | chip->irq_ack = ir_ack_apic_edge; |
2542 | chip->irq_eoi = ir_ack_apic_level; | 2571 | chip->irq_eoi = ir_ack_apic_level; |
2543 | 2572 | ||
2544 | #ifdef CONFIG_SMP | ||
2545 | chip->irq_set_affinity = set_remapped_irq_affinity; | 2573 | chip->irq_set_affinity = set_remapped_irq_affinity; |
2546 | #endif | ||
2547 | } | 2574 | } |
2548 | #endif /* CONFIG_IRQ_REMAP */ | 2575 | #endif /* CONFIG_IRQ_REMAP */ |
2549 | 2576 | ||
@@ -2554,9 +2581,7 @@ static struct irq_chip ioapic_chip __read_mostly = { | |||
2554 | .irq_unmask = unmask_ioapic_irq, | 2581 | .irq_unmask = unmask_ioapic_irq, |
2555 | .irq_ack = ack_apic_edge, | 2582 | .irq_ack = ack_apic_edge, |
2556 | .irq_eoi = ack_apic_level, | 2583 | .irq_eoi = ack_apic_level, |
2557 | #ifdef CONFIG_SMP | ||
2558 | .irq_set_affinity = ioapic_set_affinity, | 2584 | .irq_set_affinity = ioapic_set_affinity, |
2559 | #endif | ||
2560 | .irq_retrigger = ioapic_retrigger_irq, | 2585 | .irq_retrigger = ioapic_retrigger_irq, |
2561 | }; | 2586 | }; |
2562 | 2587 | ||
@@ -3038,7 +3063,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |||
3038 | if (err) | 3063 | if (err) |
3039 | return err; | 3064 | return err; |
3040 | 3065 | ||
3041 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); | 3066 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
3067 | apic->target_cpus(), &dest); | ||
3068 | if (err) | ||
3069 | return err; | ||
3042 | 3070 | ||
3043 | if (irq_remapped(cfg)) { | 3071 | if (irq_remapped(cfg)) { |
3044 | compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id); | 3072 | compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id); |
@@ -3072,7 +3100,6 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, | |||
3072 | return err; | 3100 | return err; |
3073 | } | 3101 | } |
3074 | 3102 | ||
3075 | #ifdef CONFIG_SMP | ||
3076 | static int | 3103 | static int |
3077 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | 3104 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) |
3078 | { | 3105 | { |
@@ -3092,9 +3119,8 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |||
3092 | 3119 | ||
3093 | __write_msi_msg(data->msi_desc, &msg); | 3120 | __write_msi_msg(data->msi_desc, &msg); |
3094 | 3121 | ||
3095 | return 0; | 3122 | return IRQ_SET_MASK_OK_NOCOPY; |
3096 | } | 3123 | } |
3097 | #endif /* CONFIG_SMP */ | ||
3098 | 3124 | ||
3099 | /* | 3125 | /* |
3100 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | 3126 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, |
@@ -3105,9 +3131,7 @@ static struct irq_chip msi_chip = { | |||
3105 | .irq_unmask = unmask_msi_irq, | 3131 | .irq_unmask = unmask_msi_irq, |
3106 | .irq_mask = mask_msi_irq, | 3132 | .irq_mask = mask_msi_irq, |
3107 | .irq_ack = ack_apic_edge, | 3133 | .irq_ack = ack_apic_edge, |
3108 | #ifdef CONFIG_SMP | ||
3109 | .irq_set_affinity = msi_set_affinity, | 3134 | .irq_set_affinity = msi_set_affinity, |
3110 | #endif | ||
3111 | .irq_retrigger = ioapic_retrigger_irq, | 3135 | .irq_retrigger = ioapic_retrigger_irq, |
3112 | }; | 3136 | }; |
3113 | 3137 | ||
@@ -3192,7 +3216,6 @@ void native_teardown_msi_irq(unsigned int irq) | |||
3192 | } | 3216 | } |
3193 | 3217 | ||
3194 | #ifdef CONFIG_DMAR_TABLE | 3218 | #ifdef CONFIG_DMAR_TABLE |
3195 | #ifdef CONFIG_SMP | ||
3196 | static int | 3219 | static int |
3197 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | 3220 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
3198 | bool force) | 3221 | bool force) |
@@ -3214,19 +3237,15 @@ dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, | |||
3214 | 3237 | ||
3215 | dmar_msi_write(irq, &msg); | 3238 | dmar_msi_write(irq, &msg); |
3216 | 3239 | ||
3217 | return 0; | 3240 | return IRQ_SET_MASK_OK_NOCOPY; |
3218 | } | 3241 | } |
3219 | 3242 | ||
3220 | #endif /* CONFIG_SMP */ | ||
3221 | |||
3222 | static struct irq_chip dmar_msi_type = { | 3243 | static struct irq_chip dmar_msi_type = { |
3223 | .name = "DMAR_MSI", | 3244 | .name = "DMAR_MSI", |
3224 | .irq_unmask = dmar_msi_unmask, | 3245 | .irq_unmask = dmar_msi_unmask, |
3225 | .irq_mask = dmar_msi_mask, | 3246 | .irq_mask = dmar_msi_mask, |
3226 | .irq_ack = ack_apic_edge, | 3247 | .irq_ack = ack_apic_edge, |
3227 | #ifdef CONFIG_SMP | ||
3228 | .irq_set_affinity = dmar_msi_set_affinity, | 3248 | .irq_set_affinity = dmar_msi_set_affinity, |
3229 | #endif | ||
3230 | .irq_retrigger = ioapic_retrigger_irq, | 3249 | .irq_retrigger = ioapic_retrigger_irq, |
3231 | }; | 3250 | }; |
3232 | 3251 | ||
@@ -3247,7 +3266,6 @@ int arch_setup_dmar_msi(unsigned int irq) | |||
3247 | 3266 | ||
3248 | #ifdef CONFIG_HPET_TIMER | 3267 | #ifdef CONFIG_HPET_TIMER |
3249 | 3268 | ||
3250 | #ifdef CONFIG_SMP | ||
3251 | static int hpet_msi_set_affinity(struct irq_data *data, | 3269 | static int hpet_msi_set_affinity(struct irq_data *data, |
3252 | const struct cpumask *mask, bool force) | 3270 | const struct cpumask *mask, bool force) |
3253 | { | 3271 | { |
@@ -3267,19 +3285,15 @@ static int hpet_msi_set_affinity(struct irq_data *data, | |||
3267 | 3285 | ||
3268 | hpet_msi_write(data->handler_data, &msg); | 3286 | hpet_msi_write(data->handler_data, &msg); |
3269 | 3287 | ||
3270 | return 0; | 3288 | return IRQ_SET_MASK_OK_NOCOPY; |
3271 | } | 3289 | } |
3272 | 3290 | ||
3273 | #endif /* CONFIG_SMP */ | ||
3274 | |||
3275 | static struct irq_chip hpet_msi_type = { | 3291 | static struct irq_chip hpet_msi_type = { |
3276 | .name = "HPET_MSI", | 3292 | .name = "HPET_MSI", |
3277 | .irq_unmask = hpet_msi_unmask, | 3293 | .irq_unmask = hpet_msi_unmask, |
3278 | .irq_mask = hpet_msi_mask, | 3294 | .irq_mask = hpet_msi_mask, |
3279 | .irq_ack = ack_apic_edge, | 3295 | .irq_ack = ack_apic_edge, |
3280 | #ifdef CONFIG_SMP | ||
3281 | .irq_set_affinity = hpet_msi_set_affinity, | 3296 | .irq_set_affinity = hpet_msi_set_affinity, |
3282 | #endif | ||
3283 | .irq_retrigger = ioapic_retrigger_irq, | 3297 | .irq_retrigger = ioapic_retrigger_irq, |
3284 | }; | 3298 | }; |
3285 | 3299 | ||
@@ -3314,8 +3328,6 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id) | |||
3314 | */ | 3328 | */ |
3315 | #ifdef CONFIG_HT_IRQ | 3329 | #ifdef CONFIG_HT_IRQ |
3316 | 3330 | ||
3317 | #ifdef CONFIG_SMP | ||
3318 | |||
3319 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) | 3331 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
3320 | { | 3332 | { |
3321 | struct ht_irq_msg msg; | 3333 | struct ht_irq_msg msg; |
@@ -3340,25 +3352,23 @@ ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) | |||
3340 | return -1; | 3352 | return -1; |
3341 | 3353 | ||
3342 | target_ht_irq(data->irq, dest, cfg->vector); | 3354 | target_ht_irq(data->irq, dest, cfg->vector); |
3343 | return 0; | 3355 | return IRQ_SET_MASK_OK_NOCOPY; |
3344 | } | 3356 | } |
3345 | 3357 | ||
3346 | #endif | ||
3347 | |||
3348 | static struct irq_chip ht_irq_chip = { | 3358 | static struct irq_chip ht_irq_chip = { |
3349 | .name = "PCI-HT", | 3359 | .name = "PCI-HT", |
3350 | .irq_mask = mask_ht_irq, | 3360 | .irq_mask = mask_ht_irq, |
3351 | .irq_unmask = unmask_ht_irq, | 3361 | .irq_unmask = unmask_ht_irq, |
3352 | .irq_ack = ack_apic_edge, | 3362 | .irq_ack = ack_apic_edge, |
3353 | #ifdef CONFIG_SMP | ||
3354 | .irq_set_affinity = ht_set_affinity, | 3363 | .irq_set_affinity = ht_set_affinity, |
3355 | #endif | ||
3356 | .irq_retrigger = ioapic_retrigger_irq, | 3364 | .irq_retrigger = ioapic_retrigger_irq, |
3357 | }; | 3365 | }; |
3358 | 3366 | ||
3359 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | 3367 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) |
3360 | { | 3368 | { |
3361 | struct irq_cfg *cfg; | 3369 | struct irq_cfg *cfg; |
3370 | struct ht_irq_msg msg; | ||
3371 | unsigned dest; | ||
3362 | int err; | 3372 | int err; |
3363 | 3373 | ||
3364 | if (disable_apic) | 3374 | if (disable_apic) |
@@ -3366,36 +3376,37 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |||
3366 | 3376 | ||
3367 | cfg = irq_cfg(irq); | 3377 | cfg = irq_cfg(irq); |
3368 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); | 3378 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
3369 | if (!err) { | 3379 | if (err) |
3370 | struct ht_irq_msg msg; | 3380 | return err; |
3371 | unsigned dest; | 3381 | |
3382 | err = apic->cpu_mask_to_apicid_and(cfg->domain, | ||
3383 | apic->target_cpus(), &dest); | ||
3384 | if (err) | ||
3385 | return err; | ||
3372 | 3386 | ||
3373 | dest = apic->cpu_mask_to_apicid_and(cfg->domain, | 3387 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
3374 | apic->target_cpus()); | ||
3375 | 3388 | ||
3376 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); | 3389 | msg.address_lo = |
3390 | HT_IRQ_LOW_BASE | | ||
3391 | HT_IRQ_LOW_DEST_ID(dest) | | ||
3392 | HT_IRQ_LOW_VECTOR(cfg->vector) | | ||
3393 | ((apic->irq_dest_mode == 0) ? | ||
3394 | HT_IRQ_LOW_DM_PHYSICAL : | ||
3395 | HT_IRQ_LOW_DM_LOGICAL) | | ||
3396 | HT_IRQ_LOW_RQEOI_EDGE | | ||
3397 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | ||
3398 | HT_IRQ_LOW_MT_FIXED : | ||
3399 | HT_IRQ_LOW_MT_ARBITRATED) | | ||
3400 | HT_IRQ_LOW_IRQ_MASKED; | ||
3377 | 3401 | ||
3378 | msg.address_lo = | 3402 | write_ht_irq_msg(irq, &msg); |
3379 | HT_IRQ_LOW_BASE | | ||
3380 | HT_IRQ_LOW_DEST_ID(dest) | | ||
3381 | HT_IRQ_LOW_VECTOR(cfg->vector) | | ||
3382 | ((apic->irq_dest_mode == 0) ? | ||
3383 | HT_IRQ_LOW_DM_PHYSICAL : | ||
3384 | HT_IRQ_LOW_DM_LOGICAL) | | ||
3385 | HT_IRQ_LOW_RQEOI_EDGE | | ||
3386 | ((apic->irq_delivery_mode != dest_LowestPrio) ? | ||
3387 | HT_IRQ_LOW_MT_FIXED : | ||
3388 | HT_IRQ_LOW_MT_ARBITRATED) | | ||
3389 | HT_IRQ_LOW_IRQ_MASKED; | ||
3390 | 3403 | ||
3391 | write_ht_irq_msg(irq, &msg); | 3404 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
3405 | handle_edge_irq, "edge"); | ||
3392 | 3406 | ||
3393 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, | 3407 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
3394 | handle_edge_irq, "edge"); | ||
3395 | 3408 | ||
3396 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); | 3409 | return 0; |
3397 | } | ||
3398 | return err; | ||
3399 | } | 3410 | } |
3400 | #endif /* CONFIG_HT_IRQ */ | 3411 | #endif /* CONFIG_HT_IRQ */ |
3401 | 3412 | ||
@@ -3563,7 +3574,8 @@ static int __init io_apic_get_unique_id(int ioapic, int apic_id) | |||
3563 | 3574 | ||
3564 | /* Sanity check */ | 3575 | /* Sanity check */ |
3565 | if (reg_00.bits.ID != apic_id) { | 3576 | if (reg_00.bits.ID != apic_id) { |
3566 | printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); | 3577 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
3578 | ioapic); | ||
3567 | return -1; | 3579 | return -1; |
3568 | } | 3580 | } |
3569 | } | 3581 | } |
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c index f00a68cca37a..d661ee95cabf 100644 --- a/arch/x86/kernel/apic/numaq_32.c +++ b/arch/x86/kernel/apic/numaq_32.c | |||
@@ -406,16 +406,13 @@ static inline int numaq_check_phys_apicid_present(int phys_apicid) | |||
406 | * We use physical apicids here, not logical, so just return the default | 406 | * We use physical apicids here, not logical, so just return the default |
407 | * physical broadcast to stop people from breaking us | 407 | * physical broadcast to stop people from breaking us |
408 | */ | 408 | */ |
409 | static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask) | 409 | static int |
410 | { | ||
411 | return 0x0F; | ||
412 | } | ||
413 | |||
414 | static inline unsigned int | ||
415 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | 410 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
416 | const struct cpumask *andmask) | 411 | const struct cpumask *andmask, |
412 | unsigned int *apicid) | ||
417 | { | 413 | { |
418 | return 0x0F; | 414 | *apicid = 0x0F; |
415 | return 0; | ||
419 | } | 416 | } |
420 | 417 | ||
421 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | 418 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ |
@@ -441,20 +438,6 @@ static int probe_numaq(void) | |||
441 | return found_numaq; | 438 | return found_numaq; |
442 | } | 439 | } |
443 | 440 | ||
444 | static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
445 | { | ||
446 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
447 | * specified in the interrupt destination when using lowest | ||
448 | * priority interrupt delivery mode. | ||
449 | * | ||
450 | * In particular there was a hyperthreading cpu observed to | ||
451 | * deliver interrupts to the wrong hyperthread when only one | ||
452 | * hyperthread was specified in the interrupt desitination. | ||
453 | */ | ||
454 | cpumask_clear(retmask); | ||
455 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
456 | } | ||
457 | |||
458 | static void numaq_setup_portio_remap(void) | 441 | static void numaq_setup_portio_remap(void) |
459 | { | 442 | { |
460 | int num_quads = num_online_nodes(); | 443 | int num_quads = num_online_nodes(); |
@@ -491,7 +474,7 @@ static struct apic __refdata apic_numaq = { | |||
491 | .check_apicid_used = numaq_check_apicid_used, | 474 | .check_apicid_used = numaq_check_apicid_used, |
492 | .check_apicid_present = numaq_check_apicid_present, | 475 | .check_apicid_present = numaq_check_apicid_present, |
493 | 476 | ||
494 | .vector_allocation_domain = numaq_vector_allocation_domain, | 477 | .vector_allocation_domain = flat_vector_allocation_domain, |
495 | .init_apic_ldr = numaq_init_apic_ldr, | 478 | .init_apic_ldr = numaq_init_apic_ldr, |
496 | 479 | ||
497 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, | 480 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, |
@@ -509,7 +492,6 @@ static struct apic __refdata apic_numaq = { | |||
509 | .set_apic_id = NULL, | 492 | .set_apic_id = NULL, |
510 | .apic_id_mask = 0x0F << 24, | 493 | .apic_id_mask = 0x0F << 24, |
511 | 494 | ||
512 | .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid, | ||
513 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, | 495 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, |
514 | 496 | ||
515 | .send_IPI_mask = numaq_send_IPI_mask, | 497 | .send_IPI_mask = numaq_send_IPI_mask, |
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c index 1b291da09e60..eb35ef9ee63f 100644 --- a/arch/x86/kernel/apic/probe_32.c +++ b/arch/x86/kernel/apic/probe_32.c | |||
@@ -66,21 +66,6 @@ static void setup_apic_flat_routing(void) | |||
66 | #endif | 66 | #endif |
67 | } | 67 | } |
68 | 68 | ||
69 | static void default_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
70 | { | ||
71 | /* | ||
72 | * Careful. Some cpus do not strictly honor the set of cpus | ||
73 | * specified in the interrupt destination when using lowest | ||
74 | * priority interrupt delivery mode. | ||
75 | * | ||
76 | * In particular there was a hyperthreading cpu observed to | ||
77 | * deliver interrupts to the wrong hyperthread when only one | ||
78 | * hyperthread was specified in the interrupt desitination. | ||
79 | */ | ||
80 | cpumask_clear(retmask); | ||
81 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
82 | } | ||
83 | |||
84 | /* should be called last. */ | 69 | /* should be called last. */ |
85 | static int probe_default(void) | 70 | static int probe_default(void) |
86 | { | 71 | { |
@@ -105,7 +90,7 @@ static struct apic apic_default = { | |||
105 | .check_apicid_used = default_check_apicid_used, | 90 | .check_apicid_used = default_check_apicid_used, |
106 | .check_apicid_present = default_check_apicid_present, | 91 | .check_apicid_present = default_check_apicid_present, |
107 | 92 | ||
108 | .vector_allocation_domain = default_vector_allocation_domain, | 93 | .vector_allocation_domain = flat_vector_allocation_domain, |
109 | .init_apic_ldr = default_init_apic_ldr, | 94 | .init_apic_ldr = default_init_apic_ldr, |
110 | 95 | ||
111 | .ioapic_phys_id_map = default_ioapic_phys_id_map, | 96 | .ioapic_phys_id_map = default_ioapic_phys_id_map, |
@@ -123,8 +108,7 @@ static struct apic apic_default = { | |||
123 | .set_apic_id = NULL, | 108 | .set_apic_id = NULL, |
124 | .apic_id_mask = 0x0F << 24, | 109 | .apic_id_mask = 0x0F << 24, |
125 | 110 | ||
126 | .cpu_mask_to_apicid = default_cpu_mask_to_apicid, | 111 | .cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and, |
127 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, | ||
128 | 112 | ||
129 | .send_IPI_mask = default_send_IPI_mask_logical, | 113 | .send_IPI_mask = default_send_IPI_mask_logical, |
130 | .send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical, | 114 | .send_IPI_mask_allbutself = default_send_IPI_mask_allbutself_logical, |
@@ -208,6 +192,9 @@ void __init default_setup_apic_routing(void) | |||
208 | 192 | ||
209 | if (apic->setup_apic_routing) | 193 | if (apic->setup_apic_routing) |
210 | apic->setup_apic_routing(); | 194 | apic->setup_apic_routing(); |
195 | |||
196 | if (x86_platform.apic_post_init) | ||
197 | x86_platform.apic_post_init(); | ||
211 | } | 198 | } |
212 | 199 | ||
213 | void __init generic_apic_probe(void) | 200 | void __init generic_apic_probe(void) |
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c index 3fe986698929..1793dba7a741 100644 --- a/arch/x86/kernel/apic/probe_64.c +++ b/arch/x86/kernel/apic/probe_64.c | |||
@@ -23,11 +23,6 @@ | |||
23 | #include <asm/ipi.h> | 23 | #include <asm/ipi.h> |
24 | #include <asm/setup.h> | 24 | #include <asm/setup.h> |
25 | 25 | ||
26 | static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) | ||
27 | { | ||
28 | return hard_smp_processor_id() >> index_msb; | ||
29 | } | ||
30 | |||
31 | /* | 26 | /* |
32 | * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode. | 27 | * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode. |
33 | */ | 28 | */ |
@@ -48,10 +43,8 @@ void __init default_setup_apic_routing(void) | |||
48 | } | 43 | } |
49 | } | 44 | } |
50 | 45 | ||
51 | if (is_vsmp_box()) { | 46 | if (x86_platform.apic_post_init) |
52 | /* need to update phys_pkg_id */ | 47 | x86_platform.apic_post_init(); |
53 | apic->phys_pkg_id = apicid_phys_pkg_id; | ||
54 | } | ||
55 | } | 48 | } |
56 | 49 | ||
57 | /* Same for both flat and physical. */ | 50 | /* Same for both flat and physical. */ |
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c index 659897c00755..77c95c0e1bf7 100644 --- a/arch/x86/kernel/apic/summit_32.c +++ b/arch/x86/kernel/apic/summit_32.c | |||
@@ -26,6 +26,8 @@ | |||
26 | * | 26 | * |
27 | */ | 27 | */ |
28 | 28 | ||
29 | #define pr_fmt(fmt) "summit: %s: " fmt, __func__ | ||
30 | |||
29 | #include <linux/mm.h> | 31 | #include <linux/mm.h> |
30 | #include <linux/init.h> | 32 | #include <linux/init.h> |
31 | #include <asm/io.h> | 33 | #include <asm/io.h> |
@@ -235,8 +237,8 @@ static int summit_apic_id_registered(void) | |||
235 | 237 | ||
236 | static void summit_setup_apic_routing(void) | 238 | static void summit_setup_apic_routing(void) |
237 | { | 239 | { |
238 | printk("Enabling APIC mode: Summit. Using %d I/O APICs\n", | 240 | pr_info("Enabling APIC mode: Summit. Using %d I/O APICs\n", |
239 | nr_ioapics); | 241 | nr_ioapics); |
240 | } | 242 | } |
241 | 243 | ||
242 | static int summit_cpu_present_to_apicid(int mps_cpu) | 244 | static int summit_cpu_present_to_apicid(int mps_cpu) |
@@ -263,43 +265,48 @@ static int summit_check_phys_apicid_present(int physical_apicid) | |||
263 | return 1; | 265 | return 1; |
264 | } | 266 | } |
265 | 267 | ||
266 | static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask) | 268 | static inline int |
269 | summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id) | ||
267 | { | 270 | { |
268 | unsigned int round = 0; | 271 | unsigned int round = 0; |
269 | int cpu, apicid = 0; | 272 | unsigned int cpu, apicid = 0; |
270 | 273 | ||
271 | /* | 274 | /* |
272 | * The cpus in the mask must all be on the apic cluster. | 275 | * The cpus in the mask must all be on the apic cluster. |
273 | */ | 276 | */ |
274 | for_each_cpu(cpu, cpumask) { | 277 | for_each_cpu_and(cpu, cpumask, cpu_online_mask) { |
275 | int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); | 278 | int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); |
276 | 279 | ||
277 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { | 280 | if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) { |
278 | printk("%s: Not a valid mask!\n", __func__); | 281 | pr_err("Not a valid mask!\n"); |
279 | return BAD_APICID; | 282 | return -EINVAL; |
280 | } | 283 | } |
281 | apicid |= new_apicid; | 284 | apicid |= new_apicid; |
282 | round++; | 285 | round++; |
283 | } | 286 | } |
284 | return apicid; | 287 | if (!round) |
288 | return -EINVAL; | ||
289 | *dest_id = apicid; | ||
290 | return 0; | ||
285 | } | 291 | } |
286 | 292 | ||
287 | static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, | 293 | static int |
288 | const struct cpumask *andmask) | 294 | summit_cpu_mask_to_apicid_and(const struct cpumask *inmask, |
295 | const struct cpumask *andmask, | ||
296 | unsigned int *apicid) | ||
289 | { | 297 | { |
290 | int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); | ||
291 | cpumask_var_t cpumask; | 298 | cpumask_var_t cpumask; |
299 | *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0); | ||
292 | 300 | ||
293 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) | 301 | if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC)) |
294 | return apicid; | 302 | return 0; |
295 | 303 | ||
296 | cpumask_and(cpumask, inmask, andmask); | 304 | cpumask_and(cpumask, inmask, andmask); |
297 | cpumask_and(cpumask, cpumask, cpu_online_mask); | 305 | summit_cpu_mask_to_apicid(cpumask, apicid); |
298 | apicid = summit_cpu_mask_to_apicid(cpumask); | ||
299 | 306 | ||
300 | free_cpumask_var(cpumask); | 307 | free_cpumask_var(cpumask); |
301 | 308 | ||
302 | return apicid; | 309 | return 0; |
303 | } | 310 | } |
304 | 311 | ||
305 | /* | 312 | /* |
@@ -320,20 +327,6 @@ static int probe_summit(void) | |||
320 | return 0; | 327 | return 0; |
321 | } | 328 | } |
322 | 329 | ||
323 | static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
324 | { | ||
325 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
326 | * specified in the interrupt destination when using lowest | ||
327 | * priority interrupt delivery mode. | ||
328 | * | ||
329 | * In particular there was a hyperthreading cpu observed to | ||
330 | * deliver interrupts to the wrong hyperthread when only one | ||
331 | * hyperthread was specified in the interrupt desitination. | ||
332 | */ | ||
333 | cpumask_clear(retmask); | ||
334 | cpumask_bits(retmask)[0] = APIC_ALL_CPUS; | ||
335 | } | ||
336 | |||
337 | #ifdef CONFIG_X86_SUMMIT_NUMA | 330 | #ifdef CONFIG_X86_SUMMIT_NUMA |
338 | static struct rio_table_hdr *rio_table_hdr; | 331 | static struct rio_table_hdr *rio_table_hdr; |
339 | static struct scal_detail *scal_devs[MAX_NUMNODES]; | 332 | static struct scal_detail *scal_devs[MAX_NUMNODES]; |
@@ -355,7 +348,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) | |||
355 | } | 348 | } |
356 | } | 349 | } |
357 | if (i == rio_table_hdr->num_rio_dev) { | 350 | if (i == rio_table_hdr->num_rio_dev) { |
358 | printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__); | 351 | pr_err("Couldn't find owner Cyclone for Winnipeg!\n"); |
359 | return last_bus; | 352 | return last_bus; |
360 | } | 353 | } |
361 | 354 | ||
@@ -366,7 +359,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) | |||
366 | } | 359 | } |
367 | } | 360 | } |
368 | if (i == rio_table_hdr->num_scal_dev) { | 361 | if (i == rio_table_hdr->num_scal_dev) { |
369 | printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__); | 362 | pr_err("Couldn't find owner Twister for Cyclone!\n"); |
370 | return last_bus; | 363 | return last_bus; |
371 | } | 364 | } |
372 | 365 | ||
@@ -396,7 +389,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus) | |||
396 | num_buses = 9; | 389 | num_buses = 9; |
397 | break; | 390 | break; |
398 | default: | 391 | default: |
399 | printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__); | 392 | pr_info("Unsupported Winnipeg type!\n"); |
400 | return last_bus; | 393 | return last_bus; |
401 | } | 394 | } |
402 | 395 | ||
@@ -411,13 +404,15 @@ static int build_detail_arrays(void) | |||
411 | int i, scal_detail_size, rio_detail_size; | 404 | int i, scal_detail_size, rio_detail_size; |
412 | 405 | ||
413 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { | 406 | if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) { |
414 | printk(KERN_WARNING "%s: MAX_NUMNODES too low! Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev); | 407 | pr_warn("MAX_NUMNODES too low! Defined as %d, but system has %d nodes\n", |
408 | MAX_NUMNODES, rio_table_hdr->num_scal_dev); | ||
415 | return 0; | 409 | return 0; |
416 | } | 410 | } |
417 | 411 | ||
418 | switch (rio_table_hdr->version) { | 412 | switch (rio_table_hdr->version) { |
419 | default: | 413 | default: |
420 | printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version); | 414 | pr_warn("Invalid Rio Grande Table Version: %d\n", |
415 | rio_table_hdr->version); | ||
421 | return 0; | 416 | return 0; |
422 | case 2: | 417 | case 2: |
423 | scal_detail_size = 11; | 418 | scal_detail_size = 11; |
@@ -462,7 +457,7 @@ void setup_summit(void) | |||
462 | offset = *((unsigned short *)(ptr + offset)); | 457 | offset = *((unsigned short *)(ptr + offset)); |
463 | } | 458 | } |
464 | if (!rio_table_hdr) { | 459 | if (!rio_table_hdr) { |
465 | printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__); | 460 | pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n"); |
466 | return; | 461 | return; |
467 | } | 462 | } |
468 | 463 | ||
@@ -509,7 +504,7 @@ static struct apic apic_summit = { | |||
509 | .check_apicid_used = summit_check_apicid_used, | 504 | .check_apicid_used = summit_check_apicid_used, |
510 | .check_apicid_present = summit_check_apicid_present, | 505 | .check_apicid_present = summit_check_apicid_present, |
511 | 506 | ||
512 | .vector_allocation_domain = summit_vector_allocation_domain, | 507 | .vector_allocation_domain = flat_vector_allocation_domain, |
513 | .init_apic_ldr = summit_init_apic_ldr, | 508 | .init_apic_ldr = summit_init_apic_ldr, |
514 | 509 | ||
515 | .ioapic_phys_id_map = summit_ioapic_phys_id_map, | 510 | .ioapic_phys_id_map = summit_ioapic_phys_id_map, |
@@ -527,7 +522,6 @@ static struct apic apic_summit = { | |||
527 | .set_apic_id = NULL, | 522 | .set_apic_id = NULL, |
528 | .apic_id_mask = 0xFF << 24, | 523 | .apic_id_mask = 0xFF << 24, |
529 | 524 | ||
530 | .cpu_mask_to_apicid = summit_cpu_mask_to_apicid, | ||
531 | .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, | 525 | .cpu_mask_to_apicid_and = summit_cpu_mask_to_apicid_and, |
532 | 526 | ||
533 | .send_IPI_mask = summit_send_IPI_mask, | 527 | .send_IPI_mask = summit_send_IPI_mask, |
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c index ff35cff0e1a7..c88baa4ff0e5 100644 --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c | |||
@@ -81,7 +81,7 @@ static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) | |||
81 | } | 81 | } |
82 | 82 | ||
83 | static void | 83 | static void |
84 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) | 84 | x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) |
85 | { | 85 | { |
86 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); | 86 | __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); |
87 | } | 87 | } |
@@ -96,36 +96,37 @@ static void x2apic_send_IPI_all(int vector) | |||
96 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); | 96 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
97 | } | 97 | } |
98 | 98 | ||
99 | static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask) | 99 | static int |
100 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
101 | const struct cpumask *andmask, | ||
102 | unsigned int *apicid) | ||
100 | { | 103 | { |
101 | /* | 104 | u32 dest = 0; |
102 | * We're using fixed IRQ delivery, can only return one logical APIC ID. | 105 | u16 cluster; |
103 | * May as well be the first. | 106 | int i; |
104 | */ | ||
105 | int cpu = cpumask_first(cpumask); | ||
106 | 107 | ||
107 | if ((unsigned)cpu < nr_cpu_ids) | 108 | for_each_cpu_and(i, cpumask, andmask) { |
108 | return per_cpu(x86_cpu_to_logical_apicid, cpu); | 109 | if (!cpumask_test_cpu(i, cpu_online_mask)) |
109 | else | 110 | continue; |
110 | return BAD_APICID; | 111 | dest = per_cpu(x86_cpu_to_logical_apicid, i); |
111 | } | 112 | cluster = x2apic_cluster(i); |
113 | break; | ||
114 | } | ||
112 | 115 | ||
113 | static unsigned int | 116 | if (!dest) |
114 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | 117 | return -EINVAL; |
115 | const struct cpumask *andmask) | ||
116 | { | ||
117 | int cpu; | ||
118 | 118 | ||
119 | /* | 119 | for_each_cpu_and(i, cpumask, andmask) { |
120 | * We're using fixed IRQ delivery, can only return one logical APIC ID. | 120 | if (!cpumask_test_cpu(i, cpu_online_mask)) |
121 | * May as well be the first. | 121 | continue; |
122 | */ | 122 | if (cluster != x2apic_cluster(i)) |
123 | for_each_cpu_and(cpu, cpumask, andmask) { | 123 | continue; |
124 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | 124 | dest |= per_cpu(x86_cpu_to_logical_apicid, i); |
125 | break; | ||
126 | } | 125 | } |
127 | 126 | ||
128 | return per_cpu(x86_cpu_to_logical_apicid, cpu); | 127 | *apicid = dest; |
128 | |||
129 | return 0; | ||
129 | } | 130 | } |
130 | 131 | ||
131 | static void init_x2apic_ldr(void) | 132 | static void init_x2apic_ldr(void) |
@@ -208,6 +209,32 @@ static int x2apic_cluster_probe(void) | |||
208 | return 0; | 209 | return 0; |
209 | } | 210 | } |
210 | 211 | ||
212 | static const struct cpumask *x2apic_cluster_target_cpus(void) | ||
213 | { | ||
214 | return cpu_all_mask; | ||
215 | } | ||
216 | |||
217 | /* | ||
218 | * Each x2apic cluster is an allocation domain. | ||
219 | */ | ||
220 | static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask, | ||
221 | const struct cpumask *mask) | ||
222 | { | ||
223 | /* | ||
224 | * To minimize vector pressure, default case of boot, device bringup | ||
225 | * etc will use a single cpu for the interrupt destination. | ||
226 | * | ||
227 | * On explicit migration requests coming from irqbalance etc, | ||
228 | * interrupts will be routed to the x2apic cluster (cluster-id | ||
229 | * derived from the first cpu in the mask) members specified | ||
230 | * in the mask. | ||
231 | */ | ||
232 | if (mask == x2apic_cluster_target_cpus()) | ||
233 | cpumask_copy(retmask, cpumask_of(cpu)); | ||
234 | else | ||
235 | cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu)); | ||
236 | } | ||
237 | |||
211 | static struct apic apic_x2apic_cluster = { | 238 | static struct apic apic_x2apic_cluster = { |
212 | 239 | ||
213 | .name = "cluster x2apic", | 240 | .name = "cluster x2apic", |
@@ -219,13 +246,13 @@ static struct apic apic_x2apic_cluster = { | |||
219 | .irq_delivery_mode = dest_LowestPrio, | 246 | .irq_delivery_mode = dest_LowestPrio, |
220 | .irq_dest_mode = 1, /* logical */ | 247 | .irq_dest_mode = 1, /* logical */ |
221 | 248 | ||
222 | .target_cpus = x2apic_target_cpus, | 249 | .target_cpus = x2apic_cluster_target_cpus, |
223 | .disable_esr = 0, | 250 | .disable_esr = 0, |
224 | .dest_logical = APIC_DEST_LOGICAL, | 251 | .dest_logical = APIC_DEST_LOGICAL, |
225 | .check_apicid_used = NULL, | 252 | .check_apicid_used = NULL, |
226 | .check_apicid_present = NULL, | 253 | .check_apicid_present = NULL, |
227 | 254 | ||
228 | .vector_allocation_domain = x2apic_vector_allocation_domain, | 255 | .vector_allocation_domain = cluster_vector_allocation_domain, |
229 | .init_apic_ldr = init_x2apic_ldr, | 256 | .init_apic_ldr = init_x2apic_ldr, |
230 | 257 | ||
231 | .ioapic_phys_id_map = NULL, | 258 | .ioapic_phys_id_map = NULL, |
@@ -243,7 +270,6 @@ static struct apic apic_x2apic_cluster = { | |||
243 | .set_apic_id = x2apic_set_apic_id, | 270 | .set_apic_id = x2apic_set_apic_id, |
244 | .apic_id_mask = 0xFFFFFFFFu, | 271 | .apic_id_mask = 0xFFFFFFFFu, |
245 | 272 | ||
246 | .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, | ||
247 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, | 273 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, |
248 | 274 | ||
249 | .send_IPI_mask = x2apic_send_IPI_mask, | 275 | .send_IPI_mask = x2apic_send_IPI_mask, |
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index c17e982db275..e03a1e180e81 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c | |||
@@ -76,38 +76,6 @@ static void x2apic_send_IPI_all(int vector) | |||
76 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); | 76 | __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); |
77 | } | 77 | } |
78 | 78 | ||
79 | static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask) | ||
80 | { | ||
81 | /* | ||
82 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
83 | * May as well be the first. | ||
84 | */ | ||
85 | int cpu = cpumask_first(cpumask); | ||
86 | |||
87 | if ((unsigned)cpu < nr_cpu_ids) | ||
88 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
89 | else | ||
90 | return BAD_APICID; | ||
91 | } | ||
92 | |||
93 | static unsigned int | ||
94 | x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
95 | const struct cpumask *andmask) | ||
96 | { | ||
97 | int cpu; | ||
98 | |||
99 | /* | ||
100 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
101 | * May as well be the first. | ||
102 | */ | ||
103 | for_each_cpu_and(cpu, cpumask, andmask) { | ||
104 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | ||
105 | break; | ||
106 | } | ||
107 | |||
108 | return per_cpu(x86_cpu_to_apicid, cpu); | ||
109 | } | ||
110 | |||
111 | static void init_x2apic_ldr(void) | 79 | static void init_x2apic_ldr(void) |
112 | { | 80 | { |
113 | } | 81 | } |
@@ -131,13 +99,13 @@ static struct apic apic_x2apic_phys = { | |||
131 | .irq_delivery_mode = dest_Fixed, | 99 | .irq_delivery_mode = dest_Fixed, |
132 | .irq_dest_mode = 0, /* physical */ | 100 | .irq_dest_mode = 0, /* physical */ |
133 | 101 | ||
134 | .target_cpus = x2apic_target_cpus, | 102 | .target_cpus = online_target_cpus, |
135 | .disable_esr = 0, | 103 | .disable_esr = 0, |
136 | .dest_logical = 0, | 104 | .dest_logical = 0, |
137 | .check_apicid_used = NULL, | 105 | .check_apicid_used = NULL, |
138 | .check_apicid_present = NULL, | 106 | .check_apicid_present = NULL, |
139 | 107 | ||
140 | .vector_allocation_domain = x2apic_vector_allocation_domain, | 108 | .vector_allocation_domain = default_vector_allocation_domain, |
141 | .init_apic_ldr = init_x2apic_ldr, | 109 | .init_apic_ldr = init_x2apic_ldr, |
142 | 110 | ||
143 | .ioapic_phys_id_map = NULL, | 111 | .ioapic_phys_id_map = NULL, |
@@ -155,8 +123,7 @@ static struct apic apic_x2apic_phys = { | |||
155 | .set_apic_id = x2apic_set_apic_id, | 123 | .set_apic_id = x2apic_set_apic_id, |
156 | .apic_id_mask = 0xFFFFFFFFu, | 124 | .apic_id_mask = 0xFFFFFFFFu, |
157 | 125 | ||
158 | .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, | 126 | .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and, |
159 | .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, | ||
160 | 127 | ||
161 | .send_IPI_mask = x2apic_send_IPI_mask, | 128 | .send_IPI_mask = x2apic_send_IPI_mask, |
162 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, | 129 | .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, |
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c index c6d03f7a4401..8cfade9510a4 100644 --- a/arch/x86/kernel/apic/x2apic_uv_x.c +++ b/arch/x86/kernel/apic/x2apic_uv_x.c | |||
@@ -185,17 +185,6 @@ EXPORT_SYMBOL_GPL(uv_possible_blades); | |||
185 | unsigned long sn_rtc_cycles_per_second; | 185 | unsigned long sn_rtc_cycles_per_second; |
186 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); | 186 | EXPORT_SYMBOL(sn_rtc_cycles_per_second); |
187 | 187 | ||
188 | static const struct cpumask *uv_target_cpus(void) | ||
189 | { | ||
190 | return cpu_online_mask; | ||
191 | } | ||
192 | |||
193 | static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) | ||
194 | { | ||
195 | cpumask_clear(retmask); | ||
196 | cpumask_set_cpu(cpu, retmask); | ||
197 | } | ||
198 | |||
199 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) | 188 | static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
200 | { | 189 | { |
201 | #ifdef CONFIG_SMP | 190 | #ifdef CONFIG_SMP |
@@ -280,25 +269,12 @@ static void uv_init_apic_ldr(void) | |||
280 | { | 269 | { |
281 | } | 270 | } |
282 | 271 | ||
283 | static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) | 272 | static int |
284 | { | ||
285 | /* | ||
286 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | ||
287 | * May as well be the first. | ||
288 | */ | ||
289 | int cpu = cpumask_first(cpumask); | ||
290 | |||
291 | if ((unsigned)cpu < nr_cpu_ids) | ||
292 | return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; | ||
293 | else | ||
294 | return BAD_APICID; | ||
295 | } | ||
296 | |||
297 | static unsigned int | ||
298 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | 273 | uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, |
299 | const struct cpumask *andmask) | 274 | const struct cpumask *andmask, |
275 | unsigned int *apicid) | ||
300 | { | 276 | { |
301 | int cpu; | 277 | int unsigned cpu; |
302 | 278 | ||
303 | /* | 279 | /* |
304 | * We're using fixed IRQ delivery, can only return one phys APIC ID. | 280 | * We're using fixed IRQ delivery, can only return one phys APIC ID. |
@@ -308,7 +284,13 @@ uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |||
308 | if (cpumask_test_cpu(cpu, cpu_online_mask)) | 284 | if (cpumask_test_cpu(cpu, cpu_online_mask)) |
309 | break; | 285 | break; |
310 | } | 286 | } |
311 | return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; | 287 | |
288 | if (likely(cpu < nr_cpu_ids)) { | ||
289 | *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; | ||
290 | return 0; | ||
291 | } | ||
292 | |||
293 | return -EINVAL; | ||
312 | } | 294 | } |
313 | 295 | ||
314 | static unsigned int x2apic_get_apic_id(unsigned long x) | 296 | static unsigned int x2apic_get_apic_id(unsigned long x) |
@@ -362,13 +344,13 @@ static struct apic __refdata apic_x2apic_uv_x = { | |||
362 | .irq_delivery_mode = dest_Fixed, | 344 | .irq_delivery_mode = dest_Fixed, |
363 | .irq_dest_mode = 0, /* physical */ | 345 | .irq_dest_mode = 0, /* physical */ |
364 | 346 | ||
365 | .target_cpus = uv_target_cpus, | 347 | .target_cpus = online_target_cpus, |
366 | .disable_esr = 0, | 348 | .disable_esr = 0, |
367 | .dest_logical = APIC_DEST_LOGICAL, | 349 | .dest_logical = APIC_DEST_LOGICAL, |
368 | .check_apicid_used = NULL, | 350 | .check_apicid_used = NULL, |
369 | .check_apicid_present = NULL, | 351 | .check_apicid_present = NULL, |
370 | 352 | ||
371 | .vector_allocation_domain = uv_vector_allocation_domain, | 353 | .vector_allocation_domain = default_vector_allocation_domain, |
372 | .init_apic_ldr = uv_init_apic_ldr, | 354 | .init_apic_ldr = uv_init_apic_ldr, |
373 | 355 | ||
374 | .ioapic_phys_id_map = NULL, | 356 | .ioapic_phys_id_map = NULL, |
@@ -386,7 +368,6 @@ static struct apic __refdata apic_x2apic_uv_x = { | |||
386 | .set_apic_id = set_apic_id, | 368 | .set_apic_id = set_apic_id, |
387 | .apic_id_mask = 0xFFFFFFFFu, | 369 | .apic_id_mask = 0xFFFFFFFFu, |
388 | 370 | ||
389 | .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, | ||
390 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, | 371 | .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, |
391 | 372 | ||
392 | .send_IPI_mask = uv_send_IPI_mask, | 373 | .send_IPI_mask = uv_send_IPI_mask, |
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index 07b0c0db466c..d65464e43503 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c | |||
@@ -201,6 +201,8 @@ | |||
201 | * http://www.microsoft.com/whdc/archive/amp_12.mspx] | 201 | * http://www.microsoft.com/whdc/archive/amp_12.mspx] |
202 | */ | 202 | */ |
203 | 203 | ||
204 | #define pr_fmt(fmt) "apm: " fmt | ||
205 | |||
204 | #include <linux/module.h> | 206 | #include <linux/module.h> |
205 | 207 | ||
206 | #include <linux/poll.h> | 208 | #include <linux/poll.h> |
@@ -485,11 +487,11 @@ static void apm_error(char *str, int err) | |||
485 | if (error_table[i].key == err) | 487 | if (error_table[i].key == err) |
486 | break; | 488 | break; |
487 | if (i < ERROR_COUNT) | 489 | if (i < ERROR_COUNT) |
488 | printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg); | 490 | pr_notice("%s: %s\n", str, error_table[i].msg); |
489 | else if (err < 0) | 491 | else if (err < 0) |
490 | printk(KERN_NOTICE "apm: %s: linux error code %i\n", str, err); | 492 | pr_notice("%s: linux error code %i\n", str, err); |
491 | else | 493 | else |
492 | printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n", | 494 | pr_notice("%s: unknown error code %#2.2x\n", |
493 | str, err); | 495 | str, err); |
494 | } | 496 | } |
495 | 497 | ||
@@ -1184,7 +1186,7 @@ static void queue_event(apm_event_t event, struct apm_user *sender) | |||
1184 | static int notified; | 1186 | static int notified; |
1185 | 1187 | ||
1186 | if (notified++ == 0) | 1188 | if (notified++ == 0) |
1187 | printk(KERN_ERR "apm: an event queue overflowed\n"); | 1189 | pr_err("an event queue overflowed\n"); |
1188 | if (++as->event_tail >= APM_MAX_EVENTS) | 1190 | if (++as->event_tail >= APM_MAX_EVENTS) |
1189 | as->event_tail = 0; | 1191 | as->event_tail = 0; |
1190 | } | 1192 | } |
@@ -1447,7 +1449,7 @@ static void apm_mainloop(void) | |||
1447 | static int check_apm_user(struct apm_user *as, const char *func) | 1449 | static int check_apm_user(struct apm_user *as, const char *func) |
1448 | { | 1450 | { |
1449 | if (as == NULL || as->magic != APM_BIOS_MAGIC) { | 1451 | if (as == NULL || as->magic != APM_BIOS_MAGIC) { |
1450 | printk(KERN_ERR "apm: %s passed bad filp\n", func); | 1452 | pr_err("%s passed bad filp\n", func); |
1451 | return 1; | 1453 | return 1; |
1452 | } | 1454 | } |
1453 | return 0; | 1455 | return 0; |
@@ -1586,7 +1588,7 @@ static int do_release(struct inode *inode, struct file *filp) | |||
1586 | as1 = as1->next) | 1588 | as1 = as1->next) |
1587 | ; | 1589 | ; |
1588 | if (as1 == NULL) | 1590 | if (as1 == NULL) |
1589 | printk(KERN_ERR "apm: filp not in user list\n"); | 1591 | pr_err("filp not in user list\n"); |
1590 | else | 1592 | else |
1591 | as1->next = as->next; | 1593 | as1->next = as->next; |
1592 | } | 1594 | } |
@@ -1600,11 +1602,9 @@ static int do_open(struct inode *inode, struct file *filp) | |||
1600 | struct apm_user *as; | 1602 | struct apm_user *as; |
1601 | 1603 | ||
1602 | as = kmalloc(sizeof(*as), GFP_KERNEL); | 1604 | as = kmalloc(sizeof(*as), GFP_KERNEL); |
1603 | if (as == NULL) { | 1605 | if (as == NULL) |
1604 | printk(KERN_ERR "apm: cannot allocate struct of size %d bytes\n", | ||
1605 | sizeof(*as)); | ||
1606 | return -ENOMEM; | 1606 | return -ENOMEM; |
1607 | } | 1607 | |
1608 | as->magic = APM_BIOS_MAGIC; | 1608 | as->magic = APM_BIOS_MAGIC; |
1609 | as->event_tail = as->event_head = 0; | 1609 | as->event_tail = as->event_head = 0; |
1610 | as->suspends_pending = as->standbys_pending = 0; | 1610 | as->suspends_pending = as->standbys_pending = 0; |
@@ -2313,16 +2313,16 @@ static int __init apm_init(void) | |||
2313 | } | 2313 | } |
2314 | 2314 | ||
2315 | if (apm_info.disabled) { | 2315 | if (apm_info.disabled) { |
2316 | printk(KERN_NOTICE "apm: disabled on user request.\n"); | 2316 | pr_notice("disabled on user request.\n"); |
2317 | return -ENODEV; | 2317 | return -ENODEV; |
2318 | } | 2318 | } |
2319 | if ((num_online_cpus() > 1) && !power_off && !smp) { | 2319 | if ((num_online_cpus() > 1) && !power_off && !smp) { |
2320 | printk(KERN_NOTICE "apm: disabled - APM is not SMP safe.\n"); | 2320 | pr_notice("disabled - APM is not SMP safe.\n"); |
2321 | apm_info.disabled = 1; | 2321 | apm_info.disabled = 1; |
2322 | return -ENODEV; | 2322 | return -ENODEV; |
2323 | } | 2323 | } |
2324 | if (!acpi_disabled) { | 2324 | if (!acpi_disabled) { |
2325 | printk(KERN_NOTICE "apm: overridden by ACPI.\n"); | 2325 | pr_notice("overridden by ACPI.\n"); |
2326 | apm_info.disabled = 1; | 2326 | apm_info.disabled = 1; |
2327 | return -ENODEV; | 2327 | return -ENODEV; |
2328 | } | 2328 | } |
@@ -2356,8 +2356,7 @@ static int __init apm_init(void) | |||
2356 | 2356 | ||
2357 | kapmd_task = kthread_create(apm, NULL, "kapmd"); | 2357 | kapmd_task = kthread_create(apm, NULL, "kapmd"); |
2358 | if (IS_ERR(kapmd_task)) { | 2358 | if (IS_ERR(kapmd_task)) { |
2359 | printk(KERN_ERR "apm: disabled - Unable to start kernel " | 2359 | pr_err("disabled - Unable to start kernel thread\n"); |
2360 | "thread.\n"); | ||
2361 | err = PTR_ERR(kapmd_task); | 2360 | err = PTR_ERR(kapmd_task); |
2362 | kapmd_task = NULL; | 2361 | kapmd_task = NULL; |
2363 | remove_proc_entry("apm", NULL); | 2362 | remove_proc_entry("apm", NULL); |
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 6ab6aa2fdfdd..bac4c3804cc7 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile | |||
@@ -32,7 +32,9 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o | |||
32 | 32 | ||
33 | ifdef CONFIG_PERF_EVENTS | 33 | ifdef CONFIG_PERF_EVENTS |
34 | obj-$(CONFIG_CPU_SUP_AMD) += perf_event_amd.o | 34 | obj-$(CONFIG_CPU_SUP_AMD) += perf_event_amd.o |
35 | obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_p4.o perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o | 35 | obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_p6.o perf_event_p4.o |
36 | obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o | ||
37 | obj-$(CONFIG_CPU_SUP_INTEL) += perf_event_intel_uncore.o | ||
36 | endif | 38 | endif |
37 | 39 | ||
38 | obj-$(CONFIG_X86_MCE) += mcheck/ | 40 | obj-$(CONFIG_X86_MCE) += mcheck/ |
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 146bb6218eec..9d92e19039f0 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c | |||
@@ -19,6 +19,39 @@ | |||
19 | 19 | ||
20 | #include "cpu.h" | 20 | #include "cpu.h" |
21 | 21 | ||
22 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) | ||
23 | { | ||
24 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); | ||
25 | u32 gprs[8] = { 0 }; | ||
26 | int err; | ||
27 | |||
28 | WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__); | ||
29 | |||
30 | gprs[1] = msr; | ||
31 | gprs[7] = 0x9c5a203a; | ||
32 | |||
33 | err = rdmsr_safe_regs(gprs); | ||
34 | |||
35 | *p = gprs[0] | ((u64)gprs[2] << 32); | ||
36 | |||
37 | return err; | ||
38 | } | ||
39 | |||
40 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | ||
41 | { | ||
42 | struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); | ||
43 | u32 gprs[8] = { 0 }; | ||
44 | |||
45 | WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__); | ||
46 | |||
47 | gprs[0] = (u32)val; | ||
48 | gprs[1] = msr; | ||
49 | gprs[2] = val >> 32; | ||
50 | gprs[7] = 0x9c5a203a; | ||
51 | |||
52 | return wrmsr_safe_regs(gprs); | ||
53 | } | ||
54 | |||
22 | #ifdef CONFIG_X86_32 | 55 | #ifdef CONFIG_X86_32 |
23 | /* | 56 | /* |
24 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | 57 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause |
@@ -586,9 +619,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |||
586 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { | 619 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
587 | u64 val; | 620 | u64 val; |
588 | 621 | ||
589 | if (!rdmsrl_amd_safe(0xc0011005, &val)) { | 622 | if (!rdmsrl_safe(0xc0011005, &val)) { |
590 | val |= 1ULL << 54; | 623 | val |= 1ULL << 54; |
591 | wrmsrl_amd_safe(0xc0011005, val); | 624 | wrmsrl_safe(0xc0011005, val); |
592 | rdmsrl(0xc0011005, val); | 625 | rdmsrl(0xc0011005, val); |
593 | if (val & (1ULL << 54)) { | 626 | if (val & (1ULL << 54)) { |
594 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | 627 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); |
@@ -679,7 +712,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c) | |||
679 | err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); | 712 | err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask); |
680 | if (err == 0) { | 713 | if (err == 0) { |
681 | mask |= (1 << 10); | 714 | mask |= (1 << 10); |
682 | checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask); | 715 | wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask); |
683 | } | 716 | } |
684 | } | 717 | } |
685 | 718 | ||
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 46674fbb62ba..c97bb7b5a9f8 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c | |||
@@ -55,8 +55,8 @@ static void __init check_fpu(void) | |||
55 | 55 | ||
56 | if (!boot_cpu_data.hard_math) { | 56 | if (!boot_cpu_data.hard_math) { |
57 | #ifndef CONFIG_MATH_EMULATION | 57 | #ifndef CONFIG_MATH_EMULATION |
58 | printk(KERN_EMERG "No coprocessor found and no math emulation present.\n"); | 58 | pr_emerg("No coprocessor found and no math emulation present\n"); |
59 | printk(KERN_EMERG "Giving up.\n"); | 59 | pr_emerg("Giving up\n"); |
60 | for (;;) ; | 60 | for (;;) ; |
61 | #endif | 61 | #endif |
62 | return; | 62 | return; |
@@ -86,7 +86,7 @@ static void __init check_fpu(void) | |||
86 | 86 | ||
87 | boot_cpu_data.fdiv_bug = fdiv_bug; | 87 | boot_cpu_data.fdiv_bug = fdiv_bug; |
88 | if (boot_cpu_data.fdiv_bug) | 88 | if (boot_cpu_data.fdiv_bug) |
89 | printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n"); | 89 | pr_warn("Hmm, FPU with FDIV bug\n"); |
90 | } | 90 | } |
91 | 91 | ||
92 | static void __init check_hlt(void) | 92 | static void __init check_hlt(void) |
@@ -94,16 +94,16 @@ static void __init check_hlt(void) | |||
94 | if (boot_cpu_data.x86 >= 5 || paravirt_enabled()) | 94 | if (boot_cpu_data.x86 >= 5 || paravirt_enabled()) |
95 | return; | 95 | return; |
96 | 96 | ||
97 | printk(KERN_INFO "Checking 'hlt' instruction... "); | 97 | pr_info("Checking 'hlt' instruction... "); |
98 | if (!boot_cpu_data.hlt_works_ok) { | 98 | if (!boot_cpu_data.hlt_works_ok) { |
99 | printk("disabled\n"); | 99 | pr_cont("disabled\n"); |
100 | return; | 100 | return; |
101 | } | 101 | } |
102 | halt(); | 102 | halt(); |
103 | halt(); | 103 | halt(); |
104 | halt(); | 104 | halt(); |
105 | halt(); | 105 | halt(); |
106 | printk(KERN_CONT "OK.\n"); | 106 | pr_cont("OK\n"); |
107 | } | 107 | } |
108 | 108 | ||
109 | /* | 109 | /* |
@@ -116,7 +116,7 @@ static void __init check_popad(void) | |||
116 | #ifndef CONFIG_X86_POPAD_OK | 116 | #ifndef CONFIG_X86_POPAD_OK |
117 | int res, inp = (int) &res; | 117 | int res, inp = (int) &res; |
118 | 118 | ||
119 | printk(KERN_INFO "Checking for popad bug... "); | 119 | pr_info("Checking for popad bug... "); |
120 | __asm__ __volatile__( | 120 | __asm__ __volatile__( |
121 | "movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx " | 121 | "movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx " |
122 | : "=&a" (res) | 122 | : "=&a" (res) |
@@ -127,9 +127,9 @@ static void __init check_popad(void) | |||
127 | * CPU hard. Too bad. | 127 | * CPU hard. Too bad. |
128 | */ | 128 | */ |
129 | if (res != 12345678) | 129 | if (res != 12345678) |
130 | printk(KERN_CONT "Buggy.\n"); | 130 | pr_cont("Buggy\n"); |
131 | else | 131 | else |
132 | printk(KERN_CONT "OK.\n"); | 132 | pr_cont("OK\n"); |
133 | #endif | 133 | #endif |
134 | } | 134 | } |
135 | 135 | ||
@@ -161,7 +161,7 @@ void __init check_bugs(void) | |||
161 | { | 161 | { |
162 | identify_boot_cpu(); | 162 | identify_boot_cpu(); |
163 | #ifndef CONFIG_SMP | 163 | #ifndef CONFIG_SMP |
164 | printk(KERN_INFO "CPU: "); | 164 | pr_info("CPU: "); |
165 | print_cpu_info(&boot_cpu_data); | 165 | print_cpu_info(&boot_cpu_data); |
166 | #endif | 166 | #endif |
167 | check_config(); | 167 | check_config(); |
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 6b9333b429ba..5bbc082c47ad 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c | |||
@@ -947,7 +947,7 @@ static void __cpuinit __print_cpu_msr(void) | |||
947 | index_max = msr_range_array[i].max; | 947 | index_max = msr_range_array[i].max; |
948 | 948 | ||
949 | for (index = index_min; index < index_max; index++) { | 949 | for (index = index_min; index < index_max; index++) { |
950 | if (rdmsrl_amd_safe(index, &val)) | 950 | if (rdmsrl_safe(index, &val)) |
951 | continue; | 951 | continue; |
952 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); | 952 | printk(KERN_INFO " MSR%08x: %016llx\n", index, val); |
953 | } | 953 | } |
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index da27c5d2168a..9473e8772fd1 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -7,6 +7,9 @@ | |||
7 | * Copyright 2008 Intel Corporation | 7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | 8 | * Author: Andi Kleen |
9 | */ | 9 | */ |
10 | |||
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
12 | |||
10 | #include <linux/thread_info.h> | 13 | #include <linux/thread_info.h> |
11 | #include <linux/capability.h> | 14 | #include <linux/capability.h> |
12 | #include <linux/miscdevice.h> | 15 | #include <linux/miscdevice.h> |
@@ -210,7 +213,7 @@ static void drain_mcelog_buffer(void) | |||
210 | cpu_relax(); | 213 | cpu_relax(); |
211 | 214 | ||
212 | if (!m->finished && retries >= 4) { | 215 | if (!m->finished && retries >= 4) { |
213 | pr_err("MCE: skipping error being logged currently!\n"); | 216 | pr_err("skipping error being logged currently!\n"); |
214 | break; | 217 | break; |
215 | } | 218 | } |
216 | } | 219 | } |
@@ -1167,8 +1170,9 @@ int memory_failure(unsigned long pfn, int vector, int flags) | |||
1167 | { | 1170 | { |
1168 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ | 1171 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1169 | BUG_ON(flags & MF_ACTION_REQUIRED); | 1172 | BUG_ON(flags & MF_ACTION_REQUIRED); |
1170 | printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n" | 1173 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1171 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn); | 1174 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", |
1175 | pfn); | ||
1172 | 1176 | ||
1173 | return 0; | 1177 | return 0; |
1174 | } | 1178 | } |
@@ -1186,6 +1190,7 @@ void mce_notify_process(void) | |||
1186 | { | 1190 | { |
1187 | unsigned long pfn; | 1191 | unsigned long pfn; |
1188 | struct mce_info *mi = mce_find_info(); | 1192 | struct mce_info *mi = mce_find_info(); |
1193 | int flags = MF_ACTION_REQUIRED; | ||
1189 | 1194 | ||
1190 | if (!mi) | 1195 | if (!mi) |
1191 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); | 1196 | mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL); |
@@ -1200,8 +1205,9 @@ void mce_notify_process(void) | |||
1200 | * doomed. We still need to mark the page as poisoned and alert any | 1205 | * doomed. We still need to mark the page as poisoned and alert any |
1201 | * other users of the page. | 1206 | * other users of the page. |
1202 | */ | 1207 | */ |
1203 | if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 || | 1208 | if (!mi->restartable) |
1204 | mi->restartable == 0) { | 1209 | flags |= MF_MUST_KILL; |
1210 | if (memory_failure(pfn, MCE_VECTOR, flags) < 0) { | ||
1205 | pr_err("Memory error not recovered"); | 1211 | pr_err("Memory error not recovered"); |
1206 | force_sig(SIGBUS, current); | 1212 | force_sig(SIGBUS, current); |
1207 | } | 1213 | } |
@@ -1358,11 +1364,10 @@ static int __cpuinit __mcheck_cpu_cap_init(void) | |||
1358 | 1364 | ||
1359 | b = cap & MCG_BANKCNT_MASK; | 1365 | b = cap & MCG_BANKCNT_MASK; |
1360 | if (!banks) | 1366 | if (!banks) |
1361 | printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b); | 1367 | pr_info("CPU supports %d MCE banks\n", b); |
1362 | 1368 | ||
1363 | if (b > MAX_NR_BANKS) { | 1369 | if (b > MAX_NR_BANKS) { |
1364 | printk(KERN_WARNING | 1370 | pr_warn("Using only %u machine check banks out of %u\n", |
1365 | "MCE: Using only %u machine check banks out of %u\n", | ||
1366 | MAX_NR_BANKS, b); | 1371 | MAX_NR_BANKS, b); |
1367 | b = MAX_NR_BANKS; | 1372 | b = MAX_NR_BANKS; |
1368 | } | 1373 | } |
@@ -1419,7 +1424,7 @@ static void __mcheck_cpu_init_generic(void) | |||
1419 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) | 1424 | static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
1420 | { | 1425 | { |
1421 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { | 1426 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
1422 | pr_info("MCE: unknown CPU type - not enabling MCE support.\n"); | 1427 | pr_info("unknown CPU type - not enabling MCE support\n"); |
1423 | return -EOPNOTSUPP; | 1428 | return -EOPNOTSUPP; |
1424 | } | 1429 | } |
1425 | 1430 | ||
@@ -1574,7 +1579,7 @@ static void __mcheck_cpu_init_timer(void) | |||
1574 | /* Handle unconfigured int18 (should never happen) */ | 1579 | /* Handle unconfigured int18 (should never happen) */ |
1575 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | 1580 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) |
1576 | { | 1581 | { |
1577 | printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n", | 1582 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
1578 | smp_processor_id()); | 1583 | smp_processor_id()); |
1579 | } | 1584 | } |
1580 | 1585 | ||
@@ -1893,8 +1898,7 @@ static int __init mcheck_enable(char *str) | |||
1893 | get_option(&str, &monarch_timeout); | 1898 | get_option(&str, &monarch_timeout); |
1894 | } | 1899 | } |
1895 | } else { | 1900 | } else { |
1896 | printk(KERN_INFO "mce argument %s ignored. Please use /sys\n", | 1901 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
1897 | str); | ||
1898 | return 0; | 1902 | return 0; |
1899 | } | 1903 | } |
1900 | return 1; | 1904 | return 1; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index f4873a64f46d..671b95a2ffb5 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c | |||
@@ -1,15 +1,17 @@ | |||
1 | /* | 1 | /* |
2 | * (c) 2005, 2006 Advanced Micro Devices, Inc. | 2 | * (c) 2005-2012 Advanced Micro Devices, Inc. |
3 | * Your use of this code is subject to the terms and conditions of the | 3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | 4 | * GNU general public license version 2. See "COPYING" or |
5 | * http://www.gnu.org/licenses/gpl.html | 5 | * http://www.gnu.org/licenses/gpl.html |
6 | * | 6 | * |
7 | * Written by Jacob Shin - AMD, Inc. | 7 | * Written by Jacob Shin - AMD, Inc. |
8 | * | 8 | * |
9 | * Support : jacob.shin@amd.com | 9 | * Support: borislav.petkov@amd.com |
10 | * | 10 | * |
11 | * April 2006 | 11 | * April 2006 |
12 | * - added support for AMD Family 0x10 processors | 12 | * - added support for AMD Family 0x10 processors |
13 | * May 2012 | ||
14 | * - major scrubbing | ||
13 | * | 15 | * |
14 | * All MC4_MISCi registers are shared between multi-cores | 16 | * All MC4_MISCi registers are shared between multi-cores |
15 | */ | 17 | */ |
@@ -25,6 +27,7 @@ | |||
25 | #include <linux/cpu.h> | 27 | #include <linux/cpu.h> |
26 | #include <linux/smp.h> | 28 | #include <linux/smp.h> |
27 | 29 | ||
30 | #include <asm/amd_nb.h> | ||
28 | #include <asm/apic.h> | 31 | #include <asm/apic.h> |
29 | #include <asm/idle.h> | 32 | #include <asm/idle.h> |
30 | #include <asm/mce.h> | 33 | #include <asm/mce.h> |
@@ -45,23 +48,15 @@ | |||
45 | #define MASK_BLKPTR_LO 0xFF000000 | 48 | #define MASK_BLKPTR_LO 0xFF000000 |
46 | #define MCG_XBLK_ADDR 0xC0000400 | 49 | #define MCG_XBLK_ADDR 0xC0000400 |
47 | 50 | ||
48 | struct threshold_block { | 51 | static const char * const th_names[] = { |
49 | unsigned int block; | 52 | "load_store", |
50 | unsigned int bank; | 53 | "insn_fetch", |
51 | unsigned int cpu; | 54 | "combined_unit", |
52 | u32 address; | 55 | "", |
53 | u16 interrupt_enable; | 56 | "northbridge", |
54 | bool interrupt_capable; | 57 | "execution_unit", |
55 | u16 threshold_limit; | ||
56 | struct kobject kobj; | ||
57 | struct list_head miscj; | ||
58 | }; | 58 | }; |
59 | 59 | ||
60 | struct threshold_bank { | ||
61 | struct kobject *kobj; | ||
62 | struct threshold_block *blocks; | ||
63 | cpumask_var_t cpus; | ||
64 | }; | ||
65 | static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks); | 60 | static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks); |
66 | 61 | ||
67 | static unsigned char shared_bank[NR_BANKS] = { | 62 | static unsigned char shared_bank[NR_BANKS] = { |
@@ -84,6 +79,26 @@ struct thresh_restart { | |||
84 | u16 old_limit; | 79 | u16 old_limit; |
85 | }; | 80 | }; |
86 | 81 | ||
82 | static const char * const bank4_names(struct threshold_block *b) | ||
83 | { | ||
84 | switch (b->address) { | ||
85 | /* MSR4_MISC0 */ | ||
86 | case 0x00000413: | ||
87 | return "dram"; | ||
88 | |||
89 | case 0xc0000408: | ||
90 | return "ht_links"; | ||
91 | |||
92 | case 0xc0000409: | ||
93 | return "l3_cache"; | ||
94 | |||
95 | default: | ||
96 | WARN(1, "Funny MSR: 0x%08x\n", b->address); | ||
97 | return ""; | ||
98 | } | ||
99 | }; | ||
100 | |||
101 | |||
87 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) | 102 | static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) |
88 | { | 103 | { |
89 | /* | 104 | /* |
@@ -224,8 +239,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) | |||
224 | 239 | ||
225 | if (!block) | 240 | if (!block) |
226 | per_cpu(bank_map, cpu) |= (1 << bank); | 241 | per_cpu(bank_map, cpu) |= (1 << bank); |
227 | if (shared_bank[bank] && c->cpu_core_id) | ||
228 | break; | ||
229 | 242 | ||
230 | memset(&b, 0, sizeof(b)); | 243 | memset(&b, 0, sizeof(b)); |
231 | b.cpu = cpu; | 244 | b.cpu = cpu; |
@@ -326,7 +339,7 @@ struct threshold_attr { | |||
326 | #define SHOW_FIELDS(name) \ | 339 | #define SHOW_FIELDS(name) \ |
327 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ | 340 | static ssize_t show_ ## name(struct threshold_block *b, char *buf) \ |
328 | { \ | 341 | { \ |
329 | return sprintf(buf, "%lx\n", (unsigned long) b->name); \ | 342 | return sprintf(buf, "%lu\n", (unsigned long) b->name); \ |
330 | } | 343 | } |
331 | SHOW_FIELDS(interrupt_enable) | 344 | SHOW_FIELDS(interrupt_enable) |
332 | SHOW_FIELDS(threshold_limit) | 345 | SHOW_FIELDS(threshold_limit) |
@@ -377,38 +390,21 @@ store_threshold_limit(struct threshold_block *b, const char *buf, size_t size) | |||
377 | return size; | 390 | return size; |
378 | } | 391 | } |
379 | 392 | ||
380 | struct threshold_block_cross_cpu { | ||
381 | struct threshold_block *tb; | ||
382 | long retval; | ||
383 | }; | ||
384 | |||
385 | static void local_error_count_handler(void *_tbcc) | ||
386 | { | ||
387 | struct threshold_block_cross_cpu *tbcc = _tbcc; | ||
388 | struct threshold_block *b = tbcc->tb; | ||
389 | u32 low, high; | ||
390 | |||
391 | rdmsr(b->address, low, high); | ||
392 | tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit); | ||
393 | } | ||
394 | |||
395 | static ssize_t show_error_count(struct threshold_block *b, char *buf) | 393 | static ssize_t show_error_count(struct threshold_block *b, char *buf) |
396 | { | 394 | { |
397 | struct threshold_block_cross_cpu tbcc = { .tb = b, }; | 395 | u32 lo, hi; |
398 | 396 | ||
399 | smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1); | 397 | rdmsr_on_cpu(b->cpu, b->address, &lo, &hi); |
400 | return sprintf(buf, "%lx\n", tbcc.retval); | ||
401 | } | ||
402 | 398 | ||
403 | static ssize_t store_error_count(struct threshold_block *b, | 399 | return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - |
404 | const char *buf, size_t count) | 400 | (THRESHOLD_MAX - b->threshold_limit))); |
405 | { | ||
406 | struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 }; | ||
407 | |||
408 | smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1); | ||
409 | return 1; | ||
410 | } | 401 | } |
411 | 402 | ||
403 | static struct threshold_attr error_count = { | ||
404 | .attr = {.name = __stringify(error_count), .mode = 0444 }, | ||
405 | .show = show_error_count, | ||
406 | }; | ||
407 | |||
412 | #define RW_ATTR(val) \ | 408 | #define RW_ATTR(val) \ |
413 | static struct threshold_attr val = { \ | 409 | static struct threshold_attr val = { \ |
414 | .attr = {.name = __stringify(val), .mode = 0644 }, \ | 410 | .attr = {.name = __stringify(val), .mode = 0644 }, \ |
@@ -418,7 +414,6 @@ static struct threshold_attr val = { \ | |||
418 | 414 | ||
419 | RW_ATTR(interrupt_enable); | 415 | RW_ATTR(interrupt_enable); |
420 | RW_ATTR(threshold_limit); | 416 | RW_ATTR(threshold_limit); |
421 | RW_ATTR(error_count); | ||
422 | 417 | ||
423 | static struct attribute *default_attrs[] = { | 418 | static struct attribute *default_attrs[] = { |
424 | &threshold_limit.attr, | 419 | &threshold_limit.attr, |
@@ -517,7 +512,7 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu, | |||
517 | 512 | ||
518 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, | 513 | err = kobject_init_and_add(&b->kobj, &threshold_ktype, |
519 | per_cpu(threshold_banks, cpu)[bank]->kobj, | 514 | per_cpu(threshold_banks, cpu)[bank]->kobj, |
520 | "misc%i", block); | 515 | (bank == 4 ? bank4_names(b) : th_names[bank])); |
521 | if (err) | 516 | if (err) |
522 | goto out_free; | 517 | goto out_free; |
523 | recurse: | 518 | recurse: |
@@ -548,98 +543,91 @@ out_free: | |||
548 | return err; | 543 | return err; |
549 | } | 544 | } |
550 | 545 | ||
551 | static __cpuinit long | 546 | static __cpuinit int __threshold_add_blocks(struct threshold_bank *b) |
552 | local_allocate_threshold_blocks(int cpu, unsigned int bank) | ||
553 | { | 547 | { |
554 | return allocate_threshold_blocks(cpu, bank, 0, | 548 | struct list_head *head = &b->blocks->miscj; |
555 | MSR_IA32_MC0_MISC + bank * 4); | 549 | struct threshold_block *pos = NULL; |
550 | struct threshold_block *tmp = NULL; | ||
551 | int err = 0; | ||
552 | |||
553 | err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name); | ||
554 | if (err) | ||
555 | return err; | ||
556 | |||
557 | list_for_each_entry_safe(pos, tmp, head, miscj) { | ||
558 | |||
559 | err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name); | ||
560 | if (err) { | ||
561 | list_for_each_entry_safe_reverse(pos, tmp, head, miscj) | ||
562 | kobject_del(&pos->kobj); | ||
563 | |||
564 | return err; | ||
565 | } | ||
566 | } | ||
567 | return err; | ||
556 | } | 568 | } |
557 | 569 | ||
558 | /* symlinks sibling shared banks to first core. first core owns dir/files. */ | ||
559 | static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) | 570 | static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) |
560 | { | 571 | { |
561 | int i, err = 0; | ||
562 | struct threshold_bank *b = NULL; | ||
563 | struct device *dev = per_cpu(mce_device, cpu); | 572 | struct device *dev = per_cpu(mce_device, cpu); |
564 | char name[32]; | 573 | struct amd_northbridge *nb = NULL; |
565 | 574 | struct threshold_bank *b = NULL; | |
566 | sprintf(name, "threshold_bank%i", bank); | 575 | const char *name = th_names[bank]; |
576 | int err = 0; | ||
567 | 577 | ||
568 | #ifdef CONFIG_SMP | 578 | if (shared_bank[bank]) { |
569 | if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */ | ||
570 | i = cpumask_first(cpu_llc_shared_mask(cpu)); | ||
571 | 579 | ||
572 | /* first core not up yet */ | 580 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
573 | if (cpu_data(i).cpu_core_id) | 581 | WARN_ON(!nb); |
574 | goto out; | ||
575 | 582 | ||
576 | /* already linked */ | 583 | /* threshold descriptor already initialized on this node? */ |
577 | if (per_cpu(threshold_banks, cpu)[bank]) | 584 | if (nb->bank4) { |
578 | goto out; | 585 | /* yes, use it */ |
586 | b = nb->bank4; | ||
587 | err = kobject_add(b->kobj, &dev->kobj, name); | ||
588 | if (err) | ||
589 | goto out; | ||
579 | 590 | ||
580 | b = per_cpu(threshold_banks, i)[bank]; | 591 | per_cpu(threshold_banks, cpu)[bank] = b; |
592 | atomic_inc(&b->cpus); | ||
581 | 593 | ||
582 | if (!b) | 594 | err = __threshold_add_blocks(b); |
583 | goto out; | ||
584 | 595 | ||
585 | err = sysfs_create_link(&dev->kobj, b->kobj, name); | ||
586 | if (err) | ||
587 | goto out; | 596 | goto out; |
588 | 597 | } | |
589 | cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu)); | ||
590 | per_cpu(threshold_banks, cpu)[bank] = b; | ||
591 | |||
592 | goto out; | ||
593 | } | 598 | } |
594 | #endif | ||
595 | 599 | ||
596 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); | 600 | b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL); |
597 | if (!b) { | 601 | if (!b) { |
598 | err = -ENOMEM; | 602 | err = -ENOMEM; |
599 | goto out; | 603 | goto out; |
600 | } | 604 | } |
601 | if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) { | ||
602 | kfree(b); | ||
603 | err = -ENOMEM; | ||
604 | goto out; | ||
605 | } | ||
606 | 605 | ||
607 | b->kobj = kobject_create_and_add(name, &dev->kobj); | 606 | b->kobj = kobject_create_and_add(name, &dev->kobj); |
608 | if (!b->kobj) | 607 | if (!b->kobj) { |
608 | err = -EINVAL; | ||
609 | goto out_free; | 609 | goto out_free; |
610 | 610 | } | |
611 | #ifndef CONFIG_SMP | ||
612 | cpumask_setall(b->cpus); | ||
613 | #else | ||
614 | cpumask_set_cpu(cpu, b->cpus); | ||
615 | #endif | ||
616 | 611 | ||
617 | per_cpu(threshold_banks, cpu)[bank] = b; | 612 | per_cpu(threshold_banks, cpu)[bank] = b; |
618 | 613 | ||
619 | err = local_allocate_threshold_blocks(cpu, bank); | 614 | if (shared_bank[bank]) { |
620 | if (err) | 615 | atomic_set(&b->cpus, 1); |
621 | goto out_free; | ||
622 | |||
623 | for_each_cpu(i, b->cpus) { | ||
624 | if (i == cpu) | ||
625 | continue; | ||
626 | 616 | ||
627 | dev = per_cpu(mce_device, i); | 617 | /* nb is already initialized, see above */ |
628 | if (dev) | 618 | WARN_ON(nb->bank4); |
629 | err = sysfs_create_link(&dev->kobj,b->kobj, name); | 619 | nb->bank4 = b; |
630 | if (err) | ||
631 | goto out; | ||
632 | |||
633 | per_cpu(threshold_banks, i)[bank] = b; | ||
634 | } | 620 | } |
635 | 621 | ||
636 | goto out; | 622 | err = allocate_threshold_blocks(cpu, bank, 0, |
623 | MSR_IA32_MC0_MISC + bank * 4); | ||
624 | if (!err) | ||
625 | goto out; | ||
637 | 626 | ||
638 | out_free: | 627 | out_free: |
639 | per_cpu(threshold_banks, cpu)[bank] = NULL; | ||
640 | free_cpumask_var(b->cpus); | ||
641 | kfree(b); | 628 | kfree(b); |
642 | out: | 629 | |
630 | out: | ||
643 | return err; | 631 | return err; |
644 | } | 632 | } |
645 | 633 | ||
@@ -660,12 +648,6 @@ static __cpuinit int threshold_create_device(unsigned int cpu) | |||
660 | return err; | 648 | return err; |
661 | } | 649 | } |
662 | 650 | ||
663 | /* | ||
664 | * let's be hotplug friendly. | ||
665 | * in case of multiple core processors, the first core always takes ownership | ||
666 | * of shared sysfs dir/files, and rest of the cores will be symlinked to it. | ||
667 | */ | ||
668 | |||
669 | static void deallocate_threshold_block(unsigned int cpu, | 651 | static void deallocate_threshold_block(unsigned int cpu, |
670 | unsigned int bank) | 652 | unsigned int bank) |
671 | { | 653 | { |
@@ -686,41 +668,42 @@ static void deallocate_threshold_block(unsigned int cpu, | |||
686 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; | 668 | per_cpu(threshold_banks, cpu)[bank]->blocks = NULL; |
687 | } | 669 | } |
688 | 670 | ||
671 | static void __threshold_remove_blocks(struct threshold_bank *b) | ||
672 | { | ||
673 | struct threshold_block *pos = NULL; | ||
674 | struct threshold_block *tmp = NULL; | ||
675 | |||
676 | kobject_del(b->kobj); | ||
677 | |||
678 | list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj) | ||
679 | kobject_del(&pos->kobj); | ||
680 | } | ||
681 | |||
689 | static void threshold_remove_bank(unsigned int cpu, int bank) | 682 | static void threshold_remove_bank(unsigned int cpu, int bank) |
690 | { | 683 | { |
684 | struct amd_northbridge *nb; | ||
691 | struct threshold_bank *b; | 685 | struct threshold_bank *b; |
692 | struct device *dev; | ||
693 | char name[32]; | ||
694 | int i = 0; | ||
695 | 686 | ||
696 | b = per_cpu(threshold_banks, cpu)[bank]; | 687 | b = per_cpu(threshold_banks, cpu)[bank]; |
697 | if (!b) | 688 | if (!b) |
698 | return; | 689 | return; |
690 | |||
699 | if (!b->blocks) | 691 | if (!b->blocks) |
700 | goto free_out; | 692 | goto free_out; |
701 | 693 | ||
702 | sprintf(name, "threshold_bank%i", bank); | 694 | if (shared_bank[bank]) { |
703 | 695 | if (!atomic_dec_and_test(&b->cpus)) { | |
704 | #ifdef CONFIG_SMP | 696 | __threshold_remove_blocks(b); |
705 | /* sibling symlink */ | 697 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
706 | if (shared_bank[bank] && b->blocks->cpu != cpu) { | 698 | return; |
707 | dev = per_cpu(mce_device, cpu); | 699 | } else { |
708 | sysfs_remove_link(&dev->kobj, name); | 700 | /* |
709 | per_cpu(threshold_banks, cpu)[bank] = NULL; | 701 | * the last CPU on this node using the shared bank is |
710 | 702 | * going away, remove that bank now. | |
711 | return; | 703 | */ |
712 | } | 704 | nb = node_to_amd_nb(amd_get_nb_id(cpu)); |
713 | #endif | 705 | nb->bank4 = NULL; |
714 | 706 | } | |
715 | /* remove all sibling symlinks before unregistering */ | ||
716 | for_each_cpu(i, b->cpus) { | ||
717 | if (i == cpu) | ||
718 | continue; | ||
719 | |||
720 | dev = per_cpu(mce_device, i); | ||
721 | if (dev) | ||
722 | sysfs_remove_link(&dev->kobj, name); | ||
723 | per_cpu(threshold_banks, i)[bank] = NULL; | ||
724 | } | 707 | } |
725 | 708 | ||
726 | deallocate_threshold_block(cpu, bank); | 709 | deallocate_threshold_block(cpu, bank); |
@@ -728,7 +711,6 @@ static void threshold_remove_bank(unsigned int cpu, int bank) | |||
728 | free_out: | 711 | free_out: |
729 | kobject_del(b->kobj); | 712 | kobject_del(b->kobj); |
730 | kobject_put(b->kobj); | 713 | kobject_put(b->kobj); |
731 | free_cpumask_var(b->cpus); | ||
732 | kfree(b); | 714 | kfree(b); |
733 | per_cpu(threshold_banks, cpu)[bank] = NULL; | 715 | per_cpu(threshold_banks, cpu)[bank] = NULL; |
734 | } | 716 | } |
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c index bdda2e6c673b..35ffda5d0727 100644 --- a/arch/x86/kernel/cpu/mtrr/cleanup.c +++ b/arch/x86/kernel/cpu/mtrr/cleanup.c | |||
@@ -258,11 +258,11 @@ range_to_mtrr(unsigned int reg, unsigned long range_startk, | |||
258 | 258 | ||
259 | /* Compute the maximum size with which we can make a range: */ | 259 | /* Compute the maximum size with which we can make a range: */ |
260 | if (range_startk) | 260 | if (range_startk) |
261 | max_align = ffs(range_startk) - 1; | 261 | max_align = __ffs(range_startk); |
262 | else | 262 | else |
263 | max_align = 32; | 263 | max_align = BITS_PER_LONG - 1; |
264 | 264 | ||
265 | align = fls(range_sizek) - 1; | 265 | align = __fls(range_sizek); |
266 | if (align > max_align) | 266 | if (align > max_align) |
267 | align = max_align; | 267 | align = max_align; |
268 | 268 | ||
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c index 75772ae6c65f..e9fe907cd249 100644 --- a/arch/x86/kernel/cpu/mtrr/generic.c +++ b/arch/x86/kernel/cpu/mtrr/generic.c | |||
@@ -361,11 +361,7 @@ static void __init print_mtrr_state(void) | |||
361 | } | 361 | } |
362 | pr_debug("MTRR variable ranges %sabled:\n", | 362 | pr_debug("MTRR variable ranges %sabled:\n", |
363 | mtrr_state.enabled & 2 ? "en" : "dis"); | 363 | mtrr_state.enabled & 2 ? "en" : "dis"); |
364 | if (size_or_mask & 0xffffffffUL) | 364 | high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4; |
365 | high_width = ffs(size_or_mask & 0xffffffffUL) - 1; | ||
366 | else | ||
367 | high_width = ffs(size_or_mask>>32) + 32 - 1; | ||
368 | high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4; | ||
369 | 365 | ||
370 | for (i = 0; i < num_var_ranges; ++i) { | 366 | for (i = 0; i < num_var_ranges; ++i) { |
371 | if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) | 367 | if (mtrr_state.var_ranges[i].mask_lo & (1 << 11)) |
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c index c4706cf9c011..29557aa06dda 100644 --- a/arch/x86/kernel/cpu/perf_event.c +++ b/arch/x86/kernel/cpu/perf_event.c | |||
@@ -35,17 +35,6 @@ | |||
35 | 35 | ||
36 | #include "perf_event.h" | 36 | #include "perf_event.h" |
37 | 37 | ||
38 | #if 0 | ||
39 | #undef wrmsrl | ||
40 | #define wrmsrl(msr, val) \ | ||
41 | do { \ | ||
42 | trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\ | ||
43 | (unsigned long)(val)); \ | ||
44 | native_write_msr((msr), (u32)((u64)(val)), \ | ||
45 | (u32)((u64)(val) >> 32)); \ | ||
46 | } while (0) | ||
47 | #endif | ||
48 | |||
49 | struct x86_pmu x86_pmu __read_mostly; | 38 | struct x86_pmu x86_pmu __read_mostly; |
50 | 39 | ||
51 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { | 40 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
@@ -74,7 +63,7 @@ u64 x86_perf_event_update(struct perf_event *event) | |||
74 | int idx = hwc->idx; | 63 | int idx = hwc->idx; |
75 | s64 delta; | 64 | s64 delta; |
76 | 65 | ||
77 | if (idx == X86_PMC_IDX_FIXED_BTS) | 66 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
78 | return 0; | 67 | return 0; |
79 | 68 | ||
80 | /* | 69 | /* |
@@ -86,7 +75,7 @@ u64 x86_perf_event_update(struct perf_event *event) | |||
86 | */ | 75 | */ |
87 | again: | 76 | again: |
88 | prev_raw_count = local64_read(&hwc->prev_count); | 77 | prev_raw_count = local64_read(&hwc->prev_count); |
89 | rdmsrl(hwc->event_base, new_raw_count); | 78 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
90 | 79 | ||
91 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | 80 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
92 | new_raw_count) != prev_raw_count) | 81 | new_raw_count) != prev_raw_count) |
@@ -189,7 +178,7 @@ static void release_pmc_hardware(void) {} | |||
189 | 178 | ||
190 | static bool check_hw_exists(void) | 179 | static bool check_hw_exists(void) |
191 | { | 180 | { |
192 | u64 val, val_new = 0; | 181 | u64 val, val_new = ~0; |
193 | int i, reg, ret = 0; | 182 | int i, reg, ret = 0; |
194 | 183 | ||
195 | /* | 184 | /* |
@@ -222,8 +211,9 @@ static bool check_hw_exists(void) | |||
222 | * that don't trap on the MSR access and always return 0s. | 211 | * that don't trap on the MSR access and always return 0s. |
223 | */ | 212 | */ |
224 | val = 0xabcdUL; | 213 | val = 0xabcdUL; |
225 | ret = checking_wrmsrl(x86_pmu_event_addr(0), val); | 214 | reg = x86_pmu_event_addr(0); |
226 | ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new); | 215 | ret = wrmsrl_safe(reg, val); |
216 | ret |= rdmsrl_safe(reg, &val_new); | ||
227 | if (ret || val != val_new) | 217 | if (ret || val != val_new) |
228 | goto msr_fail; | 218 | goto msr_fail; |
229 | 219 | ||
@@ -240,6 +230,7 @@ bios_fail: | |||
240 | 230 | ||
241 | msr_fail: | 231 | msr_fail: |
242 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); | 232 | printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n"); |
233 | printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new); | ||
243 | 234 | ||
244 | return false; | 235 | return false; |
245 | } | 236 | } |
@@ -388,7 +379,7 @@ int x86_pmu_hw_config(struct perf_event *event) | |||
388 | int precise = 0; | 379 | int precise = 0; |
389 | 380 | ||
390 | /* Support for constant skid */ | 381 | /* Support for constant skid */ |
391 | if (x86_pmu.pebs_active) { | 382 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
392 | precise++; | 383 | precise++; |
393 | 384 | ||
394 | /* Support for IP fixup */ | 385 | /* Support for IP fixup */ |
@@ -637,8 +628,8 @@ static bool __perf_sched_find_counter(struct perf_sched *sched) | |||
637 | c = sched->constraints[sched->state.event]; | 628 | c = sched->constraints[sched->state.event]; |
638 | 629 | ||
639 | /* Prefer fixed purpose counters */ | 630 | /* Prefer fixed purpose counters */ |
640 | if (x86_pmu.num_counters_fixed) { | 631 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
641 | idx = X86_PMC_IDX_FIXED; | 632 | idx = INTEL_PMC_IDX_FIXED; |
642 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { | 633 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
643 | if (!__test_and_set_bit(idx, sched->state.used)) | 634 | if (!__test_and_set_bit(idx, sched->state.used)) |
644 | goto done; | 635 | goto done; |
@@ -646,7 +637,7 @@ static bool __perf_sched_find_counter(struct perf_sched *sched) | |||
646 | } | 637 | } |
647 | /* Grab the first unused counter starting with idx */ | 638 | /* Grab the first unused counter starting with idx */ |
648 | idx = sched->state.counter; | 639 | idx = sched->state.counter; |
649 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) { | 640 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
650 | if (!__test_and_set_bit(idx, sched->state.used)) | 641 | if (!__test_and_set_bit(idx, sched->state.used)) |
651 | goto done; | 642 | goto done; |
652 | } | 643 | } |
@@ -704,8 +695,8 @@ static bool perf_sched_next_event(struct perf_sched *sched) | |||
704 | /* | 695 | /* |
705 | * Assign a counter for each event. | 696 | * Assign a counter for each event. |
706 | */ | 697 | */ |
707 | static int perf_assign_events(struct event_constraint **constraints, int n, | 698 | int perf_assign_events(struct event_constraint **constraints, int n, |
708 | int wmin, int wmax, int *assign) | 699 | int wmin, int wmax, int *assign) |
709 | { | 700 | { |
710 | struct perf_sched sched; | 701 | struct perf_sched sched; |
711 | 702 | ||
@@ -824,15 +815,17 @@ static inline void x86_assign_hw_event(struct perf_event *event, | |||
824 | hwc->last_cpu = smp_processor_id(); | 815 | hwc->last_cpu = smp_processor_id(); |
825 | hwc->last_tag = ++cpuc->tags[i]; | 816 | hwc->last_tag = ++cpuc->tags[i]; |
826 | 817 | ||
827 | if (hwc->idx == X86_PMC_IDX_FIXED_BTS) { | 818 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
828 | hwc->config_base = 0; | 819 | hwc->config_base = 0; |
829 | hwc->event_base = 0; | 820 | hwc->event_base = 0; |
830 | } else if (hwc->idx >= X86_PMC_IDX_FIXED) { | 821 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
831 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | 822 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
832 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED); | 823 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
824 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | ||
833 | } else { | 825 | } else { |
834 | hwc->config_base = x86_pmu_config_addr(hwc->idx); | 826 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
835 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | 827 | hwc->event_base = x86_pmu_event_addr(hwc->idx); |
828 | hwc->event_base_rdpmc = hwc->idx; | ||
836 | } | 829 | } |
837 | } | 830 | } |
838 | 831 | ||
@@ -930,7 +923,7 @@ int x86_perf_event_set_period(struct perf_event *event) | |||
930 | s64 period = hwc->sample_period; | 923 | s64 period = hwc->sample_period; |
931 | int ret = 0, idx = hwc->idx; | 924 | int ret = 0, idx = hwc->idx; |
932 | 925 | ||
933 | if (idx == X86_PMC_IDX_FIXED_BTS) | 926 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
934 | return 0; | 927 | return 0; |
935 | 928 | ||
936 | /* | 929 | /* |
@@ -1316,7 +1309,6 @@ static struct attribute_group x86_pmu_format_group = { | |||
1316 | static int __init init_hw_perf_events(void) | 1309 | static int __init init_hw_perf_events(void) |
1317 | { | 1310 | { |
1318 | struct x86_pmu_quirk *quirk; | 1311 | struct x86_pmu_quirk *quirk; |
1319 | struct event_constraint *c; | ||
1320 | int err; | 1312 | int err; |
1321 | 1313 | ||
1322 | pr_info("Performance Events: "); | 1314 | pr_info("Performance Events: "); |
@@ -1347,21 +1339,8 @@ static int __init init_hw_perf_events(void) | |||
1347 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) | 1339 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1348 | quirk->func(); | 1340 | quirk->func(); |
1349 | 1341 | ||
1350 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | 1342 | if (!x86_pmu.intel_ctrl) |
1351 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | 1343 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; |
1352 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); | ||
1353 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | ||
1354 | } | ||
1355 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | ||
1356 | |||
1357 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { | ||
1358 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | ||
1359 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); | ||
1360 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | ||
1361 | } | ||
1362 | |||
1363 | x86_pmu.intel_ctrl |= | ||
1364 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | ||
1365 | 1344 | ||
1366 | perf_events_lapic_init(); | 1345 | perf_events_lapic_init(); |
1367 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); | 1346 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
@@ -1370,22 +1349,6 @@ static int __init init_hw_perf_events(void) | |||
1370 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, | 1349 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
1371 | 0, x86_pmu.num_counters, 0); | 1350 | 0, x86_pmu.num_counters, 0); |
1372 | 1351 | ||
1373 | if (x86_pmu.event_constraints) { | ||
1374 | /* | ||
1375 | * event on fixed counter2 (REF_CYCLES) only works on this | ||
1376 | * counter, so do not extend mask to generic counters | ||
1377 | */ | ||
1378 | for_each_event_constraint(c, x86_pmu.event_constraints) { | ||
1379 | if (c->cmask != X86_RAW_EVENT_MASK | ||
1380 | || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) { | ||
1381 | continue; | ||
1382 | } | ||
1383 | |||
1384 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; | ||
1385 | c->weight += x86_pmu.num_counters; | ||
1386 | } | ||
1387 | } | ||
1388 | |||
1389 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ | 1352 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1390 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; | 1353 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
1391 | 1354 | ||
@@ -1620,8 +1583,8 @@ static int x86_pmu_event_idx(struct perf_event *event) | |||
1620 | if (!x86_pmu.attr_rdpmc) | 1583 | if (!x86_pmu.attr_rdpmc) |
1621 | return 0; | 1584 | return 0; |
1622 | 1585 | ||
1623 | if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) { | 1586 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
1624 | idx -= X86_PMC_IDX_FIXED; | 1587 | idx -= INTEL_PMC_IDX_FIXED; |
1625 | idx |= 1 << 30; | 1588 | idx |= 1 << 30; |
1626 | } | 1589 | } |
1627 | 1590 | ||
@@ -1649,7 +1612,12 @@ static ssize_t set_attr_rdpmc(struct device *cdev, | |||
1649 | struct device_attribute *attr, | 1612 | struct device_attribute *attr, |
1650 | const char *buf, size_t count) | 1613 | const char *buf, size_t count) |
1651 | { | 1614 | { |
1652 | unsigned long val = simple_strtoul(buf, NULL, 0); | 1615 | unsigned long val; |
1616 | ssize_t ret; | ||
1617 | |||
1618 | ret = kstrtoul(buf, 0, &val); | ||
1619 | if (ret) | ||
1620 | return ret; | ||
1653 | 1621 | ||
1654 | if (!!val != !!x86_pmu.attr_rdpmc) { | 1622 | if (!!val != !!x86_pmu.attr_rdpmc) { |
1655 | x86_pmu.attr_rdpmc = !!val; | 1623 | x86_pmu.attr_rdpmc = !!val; |
@@ -1682,13 +1650,20 @@ static void x86_pmu_flush_branch_stack(void) | |||
1682 | x86_pmu.flush_branch_stack(); | 1650 | x86_pmu.flush_branch_stack(); |
1683 | } | 1651 | } |
1684 | 1652 | ||
1653 | void perf_check_microcode(void) | ||
1654 | { | ||
1655 | if (x86_pmu.check_microcode) | ||
1656 | x86_pmu.check_microcode(); | ||
1657 | } | ||
1658 | EXPORT_SYMBOL_GPL(perf_check_microcode); | ||
1659 | |||
1685 | static struct pmu pmu = { | 1660 | static struct pmu pmu = { |
1686 | .pmu_enable = x86_pmu_enable, | 1661 | .pmu_enable = x86_pmu_enable, |
1687 | .pmu_disable = x86_pmu_disable, | 1662 | .pmu_disable = x86_pmu_disable, |
1688 | 1663 | ||
1689 | .attr_groups = x86_pmu_attr_groups, | 1664 | .attr_groups = x86_pmu_attr_groups, |
1690 | 1665 | ||
1691 | .event_init = x86_pmu_event_init, | 1666 | .event_init = x86_pmu_event_init, |
1692 | 1667 | ||
1693 | .add = x86_pmu_add, | 1668 | .add = x86_pmu_add, |
1694 | .del = x86_pmu_del, | 1669 | .del = x86_pmu_del, |
@@ -1696,11 +1671,11 @@ static struct pmu pmu = { | |||
1696 | .stop = x86_pmu_stop, | 1671 | .stop = x86_pmu_stop, |
1697 | .read = x86_pmu_read, | 1672 | .read = x86_pmu_read, |
1698 | 1673 | ||
1699 | .start_txn = x86_pmu_start_txn, | 1674 | .start_txn = x86_pmu_start_txn, |
1700 | .cancel_txn = x86_pmu_cancel_txn, | 1675 | .cancel_txn = x86_pmu_cancel_txn, |
1701 | .commit_txn = x86_pmu_commit_txn, | 1676 | .commit_txn = x86_pmu_commit_txn, |
1702 | 1677 | ||
1703 | .event_idx = x86_pmu_event_idx, | 1678 | .event_idx = x86_pmu_event_idx, |
1704 | .flush_branch_stack = x86_pmu_flush_branch_stack, | 1679 | .flush_branch_stack = x86_pmu_flush_branch_stack, |
1705 | }; | 1680 | }; |
1706 | 1681 | ||
@@ -1863,7 +1838,7 @@ unsigned long perf_misc_flags(struct pt_regs *regs) | |||
1863 | else | 1838 | else |
1864 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | 1839 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; |
1865 | } else { | 1840 | } else { |
1866 | if (user_mode(regs)) | 1841 | if (!kernel_ip(regs->ip)) |
1867 | misc |= PERF_RECORD_MISC_USER; | 1842 | misc |= PERF_RECORD_MISC_USER; |
1868 | else | 1843 | else |
1869 | misc |= PERF_RECORD_MISC_KERNEL; | 1844 | misc |= PERF_RECORD_MISC_KERNEL; |
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h index 7241e2fc3c17..a15df4be151f 100644 --- a/arch/x86/kernel/cpu/perf_event.h +++ b/arch/x86/kernel/cpu/perf_event.h | |||
@@ -14,6 +14,18 @@ | |||
14 | 14 | ||
15 | #include <linux/perf_event.h> | 15 | #include <linux/perf_event.h> |
16 | 16 | ||
17 | #if 0 | ||
18 | #undef wrmsrl | ||
19 | #define wrmsrl(msr, val) \ | ||
20 | do { \ | ||
21 | unsigned int _msr = (msr); \ | ||
22 | u64 _val = (val); \ | ||
23 | trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \ | ||
24 | (unsigned long long)(_val)); \ | ||
25 | native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \ | ||
26 | } while (0) | ||
27 | #endif | ||
28 | |||
17 | /* | 29 | /* |
18 | * | NHM/WSM | SNB | | 30 | * | NHM/WSM | SNB | |
19 | * register ------------------------------- | 31 | * register ------------------------------- |
@@ -57,7 +69,7 @@ struct amd_nb { | |||
57 | }; | 69 | }; |
58 | 70 | ||
59 | /* The maximal number of PEBS events: */ | 71 | /* The maximal number of PEBS events: */ |
60 | #define MAX_PEBS_EVENTS 4 | 72 | #define MAX_PEBS_EVENTS 8 |
61 | 73 | ||
62 | /* | 74 | /* |
63 | * A debug store configuration. | 75 | * A debug store configuration. |
@@ -349,6 +361,8 @@ struct x86_pmu { | |||
349 | void (*cpu_starting)(int cpu); | 361 | void (*cpu_starting)(int cpu); |
350 | void (*cpu_dying)(int cpu); | 362 | void (*cpu_dying)(int cpu); |
351 | void (*cpu_dead)(int cpu); | 363 | void (*cpu_dead)(int cpu); |
364 | |||
365 | void (*check_microcode)(void); | ||
352 | void (*flush_branch_stack)(void); | 366 | void (*flush_branch_stack)(void); |
353 | 367 | ||
354 | /* | 368 | /* |
@@ -360,12 +374,16 @@ struct x86_pmu { | |||
360 | /* | 374 | /* |
361 | * Intel DebugStore bits | 375 | * Intel DebugStore bits |
362 | */ | 376 | */ |
363 | int bts, pebs; | 377 | int bts :1, |
364 | int bts_active, pebs_active; | 378 | bts_active :1, |
379 | pebs :1, | ||
380 | pebs_active :1, | ||
381 | pebs_broken :1; | ||
365 | int pebs_record_size; | 382 | int pebs_record_size; |
366 | void (*drain_pebs)(struct pt_regs *regs); | 383 | void (*drain_pebs)(struct pt_regs *regs); |
367 | struct event_constraint *pebs_constraints; | 384 | struct event_constraint *pebs_constraints; |
368 | void (*pebs_aliases)(struct perf_event *event); | 385 | void (*pebs_aliases)(struct perf_event *event); |
386 | int max_pebs_events; | ||
369 | 387 | ||
370 | /* | 388 | /* |
371 | * Intel LBR | 389 | * Intel LBR |
@@ -468,6 +486,8 @@ static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, | |||
468 | 486 | ||
469 | void x86_pmu_enable_all(int added); | 487 | void x86_pmu_enable_all(int added); |
470 | 488 | ||
489 | int perf_assign_events(struct event_constraint **constraints, int n, | ||
490 | int wmin, int wmax, int *assign); | ||
471 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); | 491 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign); |
472 | 492 | ||
473 | void x86_pmu_stop(struct perf_event *event, int flags); | 493 | void x86_pmu_stop(struct perf_event *event, int flags); |
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c index 11a4eb9131d5..4528ae7b6ec4 100644 --- a/arch/x86/kernel/cpu/perf_event_amd.c +++ b/arch/x86/kernel/cpu/perf_event_amd.c | |||
@@ -366,7 +366,7 @@ static void amd_pmu_cpu_starting(int cpu) | |||
366 | 366 | ||
367 | cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY; | 367 | cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY; |
368 | 368 | ||
369 | if (boot_cpu_data.x86_max_cores < 2 || boot_cpu_data.x86 == 0x15) | 369 | if (boot_cpu_data.x86_max_cores < 2) |
370 | return; | 370 | return; |
371 | 371 | ||
372 | nb_id = amd_get_nb_id(cpu); | 372 | nb_id = amd_get_nb_id(cpu); |
@@ -422,35 +422,6 @@ static struct attribute *amd_format_attr[] = { | |||
422 | NULL, | 422 | NULL, |
423 | }; | 423 | }; |
424 | 424 | ||
425 | static __initconst const struct x86_pmu amd_pmu = { | ||
426 | .name = "AMD", | ||
427 | .handle_irq = x86_pmu_handle_irq, | ||
428 | .disable_all = x86_pmu_disable_all, | ||
429 | .enable_all = x86_pmu_enable_all, | ||
430 | .enable = x86_pmu_enable_event, | ||
431 | .disable = x86_pmu_disable_event, | ||
432 | .hw_config = amd_pmu_hw_config, | ||
433 | .schedule_events = x86_schedule_events, | ||
434 | .eventsel = MSR_K7_EVNTSEL0, | ||
435 | .perfctr = MSR_K7_PERFCTR0, | ||
436 | .event_map = amd_pmu_event_map, | ||
437 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), | ||
438 | .num_counters = AMD64_NUM_COUNTERS, | ||
439 | .cntval_bits = 48, | ||
440 | .cntval_mask = (1ULL << 48) - 1, | ||
441 | .apic = 1, | ||
442 | /* use highest bit to detect overflow */ | ||
443 | .max_period = (1ULL << 47) - 1, | ||
444 | .get_event_constraints = amd_get_event_constraints, | ||
445 | .put_event_constraints = amd_put_event_constraints, | ||
446 | |||
447 | .format_attrs = amd_format_attr, | ||
448 | |||
449 | .cpu_prepare = amd_pmu_cpu_prepare, | ||
450 | .cpu_starting = amd_pmu_cpu_starting, | ||
451 | .cpu_dead = amd_pmu_cpu_dead, | ||
452 | }; | ||
453 | |||
454 | /* AMD Family 15h */ | 425 | /* AMD Family 15h */ |
455 | 426 | ||
456 | #define AMD_EVENT_TYPE_MASK 0x000000F0ULL | 427 | #define AMD_EVENT_TYPE_MASK 0x000000F0ULL |
@@ -597,8 +568,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev | |||
597 | } | 568 | } |
598 | } | 569 | } |
599 | 570 | ||
600 | static __initconst const struct x86_pmu amd_pmu_f15h = { | 571 | static __initconst const struct x86_pmu amd_pmu = { |
601 | .name = "AMD Family 15h", | 572 | .name = "AMD", |
602 | .handle_irq = x86_pmu_handle_irq, | 573 | .handle_irq = x86_pmu_handle_irq, |
603 | .disable_all = x86_pmu_disable_all, | 574 | .disable_all = x86_pmu_disable_all, |
604 | .enable_all = x86_pmu_enable_all, | 575 | .enable_all = x86_pmu_enable_all, |
@@ -606,50 +577,68 @@ static __initconst const struct x86_pmu amd_pmu_f15h = { | |||
606 | .disable = x86_pmu_disable_event, | 577 | .disable = x86_pmu_disable_event, |
607 | .hw_config = amd_pmu_hw_config, | 578 | .hw_config = amd_pmu_hw_config, |
608 | .schedule_events = x86_schedule_events, | 579 | .schedule_events = x86_schedule_events, |
609 | .eventsel = MSR_F15H_PERF_CTL, | 580 | .eventsel = MSR_K7_EVNTSEL0, |
610 | .perfctr = MSR_F15H_PERF_CTR, | 581 | .perfctr = MSR_K7_PERFCTR0, |
611 | .event_map = amd_pmu_event_map, | 582 | .event_map = amd_pmu_event_map, |
612 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), | 583 | .max_events = ARRAY_SIZE(amd_perfmon_event_map), |
613 | .num_counters = AMD64_NUM_COUNTERS_F15H, | 584 | .num_counters = AMD64_NUM_COUNTERS, |
614 | .cntval_bits = 48, | 585 | .cntval_bits = 48, |
615 | .cntval_mask = (1ULL << 48) - 1, | 586 | .cntval_mask = (1ULL << 48) - 1, |
616 | .apic = 1, | 587 | .apic = 1, |
617 | /* use highest bit to detect overflow */ | 588 | /* use highest bit to detect overflow */ |
618 | .max_period = (1ULL << 47) - 1, | 589 | .max_period = (1ULL << 47) - 1, |
619 | .get_event_constraints = amd_get_event_constraints_f15h, | 590 | .get_event_constraints = amd_get_event_constraints, |
620 | /* nortbridge counters not yet implemented: */ | ||
621 | #if 0 | ||
622 | .put_event_constraints = amd_put_event_constraints, | 591 | .put_event_constraints = amd_put_event_constraints, |
623 | 592 | ||
593 | .format_attrs = amd_format_attr, | ||
594 | |||
624 | .cpu_prepare = amd_pmu_cpu_prepare, | 595 | .cpu_prepare = amd_pmu_cpu_prepare, |
625 | .cpu_dead = amd_pmu_cpu_dead, | ||
626 | #endif | ||
627 | .cpu_starting = amd_pmu_cpu_starting, | 596 | .cpu_starting = amd_pmu_cpu_starting, |
628 | .format_attrs = amd_format_attr, | 597 | .cpu_dead = amd_pmu_cpu_dead, |
629 | }; | 598 | }; |
630 | 599 | ||
600 | static int setup_event_constraints(void) | ||
601 | { | ||
602 | if (boot_cpu_data.x86 >= 0x15) | ||
603 | x86_pmu.get_event_constraints = amd_get_event_constraints_f15h; | ||
604 | return 0; | ||
605 | } | ||
606 | |||
607 | static int setup_perfctr_core(void) | ||
608 | { | ||
609 | if (!cpu_has_perfctr_core) { | ||
610 | WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h, | ||
611 | KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!"); | ||
612 | return -ENODEV; | ||
613 | } | ||
614 | |||
615 | WARN(x86_pmu.get_event_constraints == amd_get_event_constraints, | ||
616 | KERN_ERR "hw perf events core counters need constraints handler!"); | ||
617 | |||
618 | /* | ||
619 | * If core performance counter extensions exists, we must use | ||
620 | * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also | ||
621 | * x86_pmu_addr_offset(). | ||
622 | */ | ||
623 | x86_pmu.eventsel = MSR_F15H_PERF_CTL; | ||
624 | x86_pmu.perfctr = MSR_F15H_PERF_CTR; | ||
625 | x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE; | ||
626 | |||
627 | printk(KERN_INFO "perf: AMD core performance counters detected\n"); | ||
628 | |||
629 | return 0; | ||
630 | } | ||
631 | |||
631 | __init int amd_pmu_init(void) | 632 | __init int amd_pmu_init(void) |
632 | { | 633 | { |
633 | /* Performance-monitoring supported from K7 and later: */ | 634 | /* Performance-monitoring supported from K7 and later: */ |
634 | if (boot_cpu_data.x86 < 6) | 635 | if (boot_cpu_data.x86 < 6) |
635 | return -ENODEV; | 636 | return -ENODEV; |
636 | 637 | ||
637 | /* | 638 | x86_pmu = amd_pmu; |
638 | * If core performance counter extensions exists, it must be | 639 | |
639 | * family 15h, otherwise fail. See x86_pmu_addr_offset(). | 640 | setup_event_constraints(); |
640 | */ | 641 | setup_perfctr_core(); |
641 | switch (boot_cpu_data.x86) { | ||
642 | case 0x15: | ||
643 | if (!cpu_has_perfctr_core) | ||
644 | return -ENODEV; | ||
645 | x86_pmu = amd_pmu_f15h; | ||
646 | break; | ||
647 | default: | ||
648 | if (cpu_has_perfctr_core) | ||
649 | return -ENODEV; | ||
650 | x86_pmu = amd_pmu; | ||
651 | break; | ||
652 | } | ||
653 | 642 | ||
654 | /* Events are common for all AMDs */ | 643 | /* Events are common for all AMDs */ |
655 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, | 644 | memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, |
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 187c294bc658..7a8b9d0abcaa 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c | |||
@@ -5,6 +5,8 @@ | |||
5 | * among events on a single PMU. | 5 | * among events on a single PMU. |
6 | */ | 6 | */ |
7 | 7 | ||
8 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
9 | |||
8 | #include <linux/stddef.h> | 10 | #include <linux/stddef.h> |
9 | #include <linux/types.h> | 11 | #include <linux/types.h> |
10 | #include <linux/init.h> | 12 | #include <linux/init.h> |
@@ -21,14 +23,14 @@ | |||
21 | */ | 23 | */ |
22 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = | 24 | static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly = |
23 | { | 25 | { |
24 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, | 26 | [PERF_COUNT_HW_CPU_CYCLES] = 0x003c, |
25 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, | 27 | [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
26 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, | 28 | [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e, |
27 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, | 29 | [PERF_COUNT_HW_CACHE_MISSES] = 0x412e, |
28 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, | 30 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, |
29 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, | 31 | [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, |
30 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, | 32 | [PERF_COUNT_HW_BUS_CYCLES] = 0x013c, |
31 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ | 33 | [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */ |
32 | }; | 34 | }; |
33 | 35 | ||
34 | static struct event_constraint intel_core_event_constraints[] __read_mostly = | 36 | static struct event_constraint intel_core_event_constraints[] __read_mostly = |
@@ -747,7 +749,7 @@ static void intel_pmu_disable_all(void) | |||
747 | 749 | ||
748 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); | 750 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0); |
749 | 751 | ||
750 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) | 752 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) |
751 | intel_pmu_disable_bts(); | 753 | intel_pmu_disable_bts(); |
752 | 754 | ||
753 | intel_pmu_pebs_disable_all(); | 755 | intel_pmu_pebs_disable_all(); |
@@ -763,9 +765,9 @@ static void intel_pmu_enable_all(int added) | |||
763 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, | 765 | wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, |
764 | x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); | 766 | x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); |
765 | 767 | ||
766 | if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { | 768 | if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { |
767 | struct perf_event *event = | 769 | struct perf_event *event = |
768 | cpuc->events[X86_PMC_IDX_FIXED_BTS]; | 770 | cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
769 | 771 | ||
770 | if (WARN_ON_ONCE(!event)) | 772 | if (WARN_ON_ONCE(!event)) |
771 | return; | 773 | return; |
@@ -871,7 +873,7 @@ static inline void intel_pmu_ack_status(u64 ack) | |||
871 | 873 | ||
872 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) | 874 | static void intel_pmu_disable_fixed(struct hw_perf_event *hwc) |
873 | { | 875 | { |
874 | int idx = hwc->idx - X86_PMC_IDX_FIXED; | 876 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
875 | u64 ctrl_val, mask; | 877 | u64 ctrl_val, mask; |
876 | 878 | ||
877 | mask = 0xfULL << (idx * 4); | 879 | mask = 0xfULL << (idx * 4); |
@@ -886,7 +888,7 @@ static void intel_pmu_disable_event(struct perf_event *event) | |||
886 | struct hw_perf_event *hwc = &event->hw; | 888 | struct hw_perf_event *hwc = &event->hw; |
887 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | 889 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
888 | 890 | ||
889 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | 891 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
890 | intel_pmu_disable_bts(); | 892 | intel_pmu_disable_bts(); |
891 | intel_pmu_drain_bts_buffer(); | 893 | intel_pmu_drain_bts_buffer(); |
892 | return; | 894 | return; |
@@ -915,7 +917,7 @@ static void intel_pmu_disable_event(struct perf_event *event) | |||
915 | 917 | ||
916 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) | 918 | static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) |
917 | { | 919 | { |
918 | int idx = hwc->idx - X86_PMC_IDX_FIXED; | 920 | int idx = hwc->idx - INTEL_PMC_IDX_FIXED; |
919 | u64 ctrl_val, bits, mask; | 921 | u64 ctrl_val, bits, mask; |
920 | 922 | ||
921 | /* | 923 | /* |
@@ -949,7 +951,7 @@ static void intel_pmu_enable_event(struct perf_event *event) | |||
949 | struct hw_perf_event *hwc = &event->hw; | 951 | struct hw_perf_event *hwc = &event->hw; |
950 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | 952 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
951 | 953 | ||
952 | if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) { | 954 | if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) { |
953 | if (!__this_cpu_read(cpu_hw_events.enabled)) | 955 | if (!__this_cpu_read(cpu_hw_events.enabled)) |
954 | return; | 956 | return; |
955 | 957 | ||
@@ -1000,14 +1002,14 @@ static void intel_pmu_reset(void) | |||
1000 | 1002 | ||
1001 | local_irq_save(flags); | 1003 | local_irq_save(flags); |
1002 | 1004 | ||
1003 | printk("clearing PMU state on CPU#%d\n", smp_processor_id()); | 1005 | pr_info("clearing PMU state on CPU#%d\n", smp_processor_id()); |
1004 | 1006 | ||
1005 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { | 1007 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
1006 | checking_wrmsrl(x86_pmu_config_addr(idx), 0ull); | 1008 | wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); |
1007 | checking_wrmsrl(x86_pmu_event_addr(idx), 0ull); | 1009 | wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); |
1008 | } | 1010 | } |
1009 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) | 1011 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) |
1010 | checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); | 1012 | wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); |
1011 | 1013 | ||
1012 | if (ds) | 1014 | if (ds) |
1013 | ds->bts_index = ds->bts_buffer_base; | 1015 | ds->bts_index = ds->bts_buffer_base; |
@@ -1707,16 +1709,61 @@ static __init void intel_clovertown_quirk(void) | |||
1707 | * But taken together it might just make sense to not enable PEBS on | 1709 | * But taken together it might just make sense to not enable PEBS on |
1708 | * these chips. | 1710 | * these chips. |
1709 | */ | 1711 | */ |
1710 | printk(KERN_WARNING "PEBS disabled due to CPU errata.\n"); | 1712 | pr_warn("PEBS disabled due to CPU errata\n"); |
1711 | x86_pmu.pebs = 0; | 1713 | x86_pmu.pebs = 0; |
1712 | x86_pmu.pebs_constraints = NULL; | 1714 | x86_pmu.pebs_constraints = NULL; |
1713 | } | 1715 | } |
1714 | 1716 | ||
1717 | static int intel_snb_pebs_broken(int cpu) | ||
1718 | { | ||
1719 | u32 rev = UINT_MAX; /* default to broken for unknown models */ | ||
1720 | |||
1721 | switch (cpu_data(cpu).x86_model) { | ||
1722 | case 42: /* SNB */ | ||
1723 | rev = 0x28; | ||
1724 | break; | ||
1725 | |||
1726 | case 45: /* SNB-EP */ | ||
1727 | switch (cpu_data(cpu).x86_mask) { | ||
1728 | case 6: rev = 0x618; break; | ||
1729 | case 7: rev = 0x70c; break; | ||
1730 | } | ||
1731 | } | ||
1732 | |||
1733 | return (cpu_data(cpu).microcode < rev); | ||
1734 | } | ||
1735 | |||
1736 | static void intel_snb_check_microcode(void) | ||
1737 | { | ||
1738 | int pebs_broken = 0; | ||
1739 | int cpu; | ||
1740 | |||
1741 | get_online_cpus(); | ||
1742 | for_each_online_cpu(cpu) { | ||
1743 | if ((pebs_broken = intel_snb_pebs_broken(cpu))) | ||
1744 | break; | ||
1745 | } | ||
1746 | put_online_cpus(); | ||
1747 | |||
1748 | if (pebs_broken == x86_pmu.pebs_broken) | ||
1749 | return; | ||
1750 | |||
1751 | /* | ||
1752 | * Serialized by the microcode lock.. | ||
1753 | */ | ||
1754 | if (x86_pmu.pebs_broken) { | ||
1755 | pr_info("PEBS enabled due to microcode update\n"); | ||
1756 | x86_pmu.pebs_broken = 0; | ||
1757 | } else { | ||
1758 | pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n"); | ||
1759 | x86_pmu.pebs_broken = 1; | ||
1760 | } | ||
1761 | } | ||
1762 | |||
1715 | static __init void intel_sandybridge_quirk(void) | 1763 | static __init void intel_sandybridge_quirk(void) |
1716 | { | 1764 | { |
1717 | printk(KERN_WARNING "PEBS disabled due to CPU errata.\n"); | 1765 | x86_pmu.check_microcode = intel_snb_check_microcode; |
1718 | x86_pmu.pebs = 0; | 1766 | intel_snb_check_microcode(); |
1719 | x86_pmu.pebs_constraints = NULL; | ||
1720 | } | 1767 | } |
1721 | 1768 | ||
1722 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { | 1769 | static const struct { int id; char *name; } intel_arch_events_map[] __initconst = { |
@@ -1736,8 +1783,8 @@ static __init void intel_arch_events_quirk(void) | |||
1736 | /* disable event that reported as not presend by cpuid */ | 1783 | /* disable event that reported as not presend by cpuid */ |
1737 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { | 1784 | for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { |
1738 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; | 1785 | intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0; |
1739 | printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n", | 1786 | pr_warn("CPUID marked event: \'%s\' unavailable\n", |
1740 | intel_arch_events_map[bit].name); | 1787 | intel_arch_events_map[bit].name); |
1741 | } | 1788 | } |
1742 | } | 1789 | } |
1743 | 1790 | ||
@@ -1756,7 +1803,7 @@ static __init void intel_nehalem_quirk(void) | |||
1756 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; | 1803 | intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89; |
1757 | ebx.split.no_branch_misses_retired = 0; | 1804 | ebx.split.no_branch_misses_retired = 0; |
1758 | x86_pmu.events_maskl = ebx.full; | 1805 | x86_pmu.events_maskl = ebx.full; |
1759 | printk(KERN_INFO "CPU erratum AAJ80 worked around\n"); | 1806 | pr_info("CPU erratum AAJ80 worked around\n"); |
1760 | } | 1807 | } |
1761 | } | 1808 | } |
1762 | 1809 | ||
@@ -1765,6 +1812,7 @@ __init int intel_pmu_init(void) | |||
1765 | union cpuid10_edx edx; | 1812 | union cpuid10_edx edx; |
1766 | union cpuid10_eax eax; | 1813 | union cpuid10_eax eax; |
1767 | union cpuid10_ebx ebx; | 1814 | union cpuid10_ebx ebx; |
1815 | struct event_constraint *c; | ||
1768 | unsigned int unused; | 1816 | unsigned int unused; |
1769 | int version; | 1817 | int version; |
1770 | 1818 | ||
@@ -1800,6 +1848,8 @@ __init int intel_pmu_init(void) | |||
1800 | x86_pmu.events_maskl = ebx.full; | 1848 | x86_pmu.events_maskl = ebx.full; |
1801 | x86_pmu.events_mask_len = eax.split.mask_length; | 1849 | x86_pmu.events_mask_len = eax.split.mask_length; |
1802 | 1850 | ||
1851 | x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); | ||
1852 | |||
1803 | /* | 1853 | /* |
1804 | * Quirk: v2 perfmon does not report fixed-purpose events, so | 1854 | * Quirk: v2 perfmon does not report fixed-purpose events, so |
1805 | * assume at least 3 events: | 1855 | * assume at least 3 events: |
@@ -1951,5 +2001,37 @@ __init int intel_pmu_init(void) | |||
1951 | } | 2001 | } |
1952 | } | 2002 | } |
1953 | 2003 | ||
2004 | if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { | ||
2005 | WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!", | ||
2006 | x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); | ||
2007 | x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; | ||
2008 | } | ||
2009 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | ||
2010 | |||
2011 | if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { | ||
2012 | WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!", | ||
2013 | x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); | ||
2014 | x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; | ||
2015 | } | ||
2016 | |||
2017 | x86_pmu.intel_ctrl |= | ||
2018 | ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; | ||
2019 | |||
2020 | if (x86_pmu.event_constraints) { | ||
2021 | /* | ||
2022 | * event on fixed counter2 (REF_CYCLES) only works on this | ||
2023 | * counter, so do not extend mask to generic counters | ||
2024 | */ | ||
2025 | for_each_event_constraint(c, x86_pmu.event_constraints) { | ||
2026 | if (c->cmask != X86_RAW_EVENT_MASK | ||
2027 | || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) { | ||
2028 | continue; | ||
2029 | } | ||
2030 | |||
2031 | c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; | ||
2032 | c->weight += x86_pmu.num_counters; | ||
2033 | } | ||
2034 | } | ||
2035 | |||
1954 | return 0; | 2036 | return 0; |
1955 | } | 2037 | } |
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 35e2192df9f4..629ae0b7ad90 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c | |||
@@ -248,7 +248,7 @@ void reserve_ds_buffers(void) | |||
248 | */ | 248 | */ |
249 | 249 | ||
250 | struct event_constraint bts_constraint = | 250 | struct event_constraint bts_constraint = |
251 | EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0); | 251 | EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0); |
252 | 252 | ||
253 | void intel_pmu_enable_bts(u64 config) | 253 | void intel_pmu_enable_bts(u64 config) |
254 | { | 254 | { |
@@ -295,7 +295,7 @@ int intel_pmu_drain_bts_buffer(void) | |||
295 | u64 to; | 295 | u64 to; |
296 | u64 flags; | 296 | u64 flags; |
297 | }; | 297 | }; |
298 | struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS]; | 298 | struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; |
299 | struct bts_record *at, *top; | 299 | struct bts_record *at, *top; |
300 | struct perf_output_handle handle; | 300 | struct perf_output_handle handle; |
301 | struct perf_event_header header; | 301 | struct perf_event_header header; |
@@ -620,7 +620,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs) | |||
620 | * Should not happen, we program the threshold at 1 and do not | 620 | * Should not happen, we program the threshold at 1 and do not |
621 | * set a reset value. | 621 | * set a reset value. |
622 | */ | 622 | */ |
623 | WARN_ON_ONCE(n > 1); | 623 | WARN_ONCE(n > 1, "bad leftover pebs %d\n", n); |
624 | at += n - 1; | 624 | at += n - 1; |
625 | 625 | ||
626 | __intel_pmu_pebs_event(event, iregs, at); | 626 | __intel_pmu_pebs_event(event, iregs, at); |
@@ -651,10 +651,10 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) | |||
651 | * Should not happen, we program the threshold at 1 and do not | 651 | * Should not happen, we program the threshold at 1 and do not |
652 | * set a reset value. | 652 | * set a reset value. |
653 | */ | 653 | */ |
654 | WARN_ON_ONCE(n > MAX_PEBS_EVENTS); | 654 | WARN_ONCE(n > x86_pmu.max_pebs_events, "Unexpected number of pebs records %d\n", n); |
655 | 655 | ||
656 | for ( ; at < top; at++) { | 656 | for ( ; at < top; at++) { |
657 | for_each_set_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) { | 657 | for_each_set_bit(bit, (unsigned long *)&at->status, x86_pmu.max_pebs_events) { |
658 | event = cpuc->events[bit]; | 658 | event = cpuc->events[bit]; |
659 | if (!test_bit(bit, cpuc->active_mask)) | 659 | if (!test_bit(bit, cpuc->active_mask)) |
660 | continue; | 660 | continue; |
@@ -670,7 +670,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) | |||
670 | break; | 670 | break; |
671 | } | 671 | } |
672 | 672 | ||
673 | if (!event || bit >= MAX_PEBS_EVENTS) | 673 | if (!event || bit >= x86_pmu.max_pebs_events) |
674 | continue; | 674 | continue; |
675 | 675 | ||
676 | __intel_pmu_pebs_event(event, iregs, at); | 676 | __intel_pmu_pebs_event(event, iregs, at); |
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c new file mode 100644 index 000000000000..19faffc60886 --- /dev/null +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c | |||
@@ -0,0 +1,1850 @@ | |||
1 | #include "perf_event_intel_uncore.h" | ||
2 | |||
3 | static struct intel_uncore_type *empty_uncore[] = { NULL, }; | ||
4 | static struct intel_uncore_type **msr_uncores = empty_uncore; | ||
5 | static struct intel_uncore_type **pci_uncores = empty_uncore; | ||
6 | /* pci bus to socket mapping */ | ||
7 | static int pcibus_to_physid[256] = { [0 ... 255] = -1, }; | ||
8 | |||
9 | static DEFINE_RAW_SPINLOCK(uncore_box_lock); | ||
10 | |||
11 | /* mask of cpus that collect uncore events */ | ||
12 | static cpumask_t uncore_cpu_mask; | ||
13 | |||
14 | /* constraint for the fixed counter */ | ||
15 | static struct event_constraint constraint_fixed = | ||
16 | EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL); | ||
17 | static struct event_constraint constraint_empty = | ||
18 | EVENT_CONSTRAINT(0, 0, 0); | ||
19 | |||
20 | DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7"); | ||
21 | DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15"); | ||
22 | DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18"); | ||
23 | DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19"); | ||
24 | DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); | ||
25 | DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); | ||
26 | DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); | ||
27 | DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31"); | ||
28 | DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28"); | ||
29 | DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15"); | ||
30 | DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30"); | ||
31 | DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51"); | ||
32 | DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4"); | ||
33 | DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17"); | ||
34 | DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22"); | ||
35 | DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31"); | ||
36 | DEFINE_UNCORE_FORMAT_ATTR(filter_brand0, filter_brand0, "config1:0-7"); | ||
37 | DEFINE_UNCORE_FORMAT_ATTR(filter_brand1, filter_brand1, "config1:8-15"); | ||
38 | DEFINE_UNCORE_FORMAT_ATTR(filter_brand2, filter_brand2, "config1:16-23"); | ||
39 | DEFINE_UNCORE_FORMAT_ATTR(filter_brand3, filter_brand3, "config1:24-31"); | ||
40 | |||
41 | /* Sandy Bridge-EP uncore support */ | ||
42 | static struct intel_uncore_type snbep_uncore_cbox; | ||
43 | static struct intel_uncore_type snbep_uncore_pcu; | ||
44 | |||
45 | static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box) | ||
46 | { | ||
47 | struct pci_dev *pdev = box->pci_dev; | ||
48 | int box_ctl = uncore_pci_box_ctl(box); | ||
49 | u32 config; | ||
50 | |||
51 | pci_read_config_dword(pdev, box_ctl, &config); | ||
52 | config |= SNBEP_PMON_BOX_CTL_FRZ; | ||
53 | pci_write_config_dword(pdev, box_ctl, config); | ||
54 | } | ||
55 | |||
56 | static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box) | ||
57 | { | ||
58 | struct pci_dev *pdev = box->pci_dev; | ||
59 | int box_ctl = uncore_pci_box_ctl(box); | ||
60 | u32 config; | ||
61 | |||
62 | pci_read_config_dword(pdev, box_ctl, &config); | ||
63 | config &= ~SNBEP_PMON_BOX_CTL_FRZ; | ||
64 | pci_write_config_dword(pdev, box_ctl, config); | ||
65 | } | ||
66 | |||
67 | static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, | ||
68 | struct perf_event *event) | ||
69 | { | ||
70 | struct pci_dev *pdev = box->pci_dev; | ||
71 | struct hw_perf_event *hwc = &event->hw; | ||
72 | |||
73 | pci_write_config_dword(pdev, hwc->config_base, hwc->config | | ||
74 | SNBEP_PMON_CTL_EN); | ||
75 | } | ||
76 | |||
77 | static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, | ||
78 | struct perf_event *event) | ||
79 | { | ||
80 | struct pci_dev *pdev = box->pci_dev; | ||
81 | struct hw_perf_event *hwc = &event->hw; | ||
82 | |||
83 | pci_write_config_dword(pdev, hwc->config_base, hwc->config); | ||
84 | } | ||
85 | |||
86 | static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, | ||
87 | struct perf_event *event) | ||
88 | { | ||
89 | struct pci_dev *pdev = box->pci_dev; | ||
90 | struct hw_perf_event *hwc = &event->hw; | ||
91 | u64 count; | ||
92 | |||
93 | pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count); | ||
94 | pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1); | ||
95 | return count; | ||
96 | } | ||
97 | |||
98 | static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) | ||
99 | { | ||
100 | struct pci_dev *pdev = box->pci_dev; | ||
101 | pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, | ||
102 | SNBEP_PMON_BOX_CTL_INT); | ||
103 | } | ||
104 | |||
105 | static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) | ||
106 | { | ||
107 | u64 config; | ||
108 | unsigned msr; | ||
109 | |||
110 | msr = uncore_msr_box_ctl(box); | ||
111 | if (msr) { | ||
112 | rdmsrl(msr, config); | ||
113 | config |= SNBEP_PMON_BOX_CTL_FRZ; | ||
114 | wrmsrl(msr, config); | ||
115 | return; | ||
116 | } | ||
117 | } | ||
118 | |||
119 | static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box) | ||
120 | { | ||
121 | u64 config; | ||
122 | unsigned msr; | ||
123 | |||
124 | msr = uncore_msr_box_ctl(box); | ||
125 | if (msr) { | ||
126 | rdmsrl(msr, config); | ||
127 | config &= ~SNBEP_PMON_BOX_CTL_FRZ; | ||
128 | wrmsrl(msr, config); | ||
129 | return; | ||
130 | } | ||
131 | } | ||
132 | |||
133 | static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, | ||
134 | struct perf_event *event) | ||
135 | { | ||
136 | struct hw_perf_event *hwc = &event->hw; | ||
137 | struct hw_perf_event_extra *reg1 = &hwc->extra_reg; | ||
138 | |||
139 | if (reg1->idx != EXTRA_REG_NONE) | ||
140 | wrmsrl(reg1->reg, reg1->config); | ||
141 | |||
142 | wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN); | ||
143 | } | ||
144 | |||
145 | static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box, | ||
146 | struct perf_event *event) | ||
147 | { | ||
148 | struct hw_perf_event *hwc = &event->hw; | ||
149 | |||
150 | wrmsrl(hwc->config_base, hwc->config); | ||
151 | } | ||
152 | |||
153 | static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box, | ||
154 | struct perf_event *event) | ||
155 | { | ||
156 | struct hw_perf_event *hwc = &event->hw; | ||
157 | u64 count; | ||
158 | |||
159 | rdmsrl(hwc->event_base, count); | ||
160 | return count; | ||
161 | } | ||
162 | |||
163 | static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) | ||
164 | { | ||
165 | unsigned msr = uncore_msr_box_ctl(box); | ||
166 | if (msr) | ||
167 | wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT); | ||
168 | } | ||
169 | |||
170 | static struct event_constraint * | ||
171 | snbep_uncore_get_constraint(struct intel_uncore_box *box, | ||
172 | struct perf_event *event) | ||
173 | { | ||
174 | struct intel_uncore_extra_reg *er; | ||
175 | struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; | ||
176 | unsigned long flags; | ||
177 | bool ok = false; | ||
178 | |||
179 | if (reg1->idx == EXTRA_REG_NONE || (box->phys_id >= 0 && reg1->alloc)) | ||
180 | return NULL; | ||
181 | |||
182 | er = &box->shared_regs[reg1->idx]; | ||
183 | raw_spin_lock_irqsave(&er->lock, flags); | ||
184 | if (!atomic_read(&er->ref) || er->config1 == reg1->config) { | ||
185 | atomic_inc(&er->ref); | ||
186 | er->config1 = reg1->config; | ||
187 | ok = true; | ||
188 | } | ||
189 | raw_spin_unlock_irqrestore(&er->lock, flags); | ||
190 | |||
191 | if (ok) { | ||
192 | if (box->phys_id >= 0) | ||
193 | reg1->alloc = 1; | ||
194 | return NULL; | ||
195 | } | ||
196 | return &constraint_empty; | ||
197 | } | ||
198 | |||
199 | static void snbep_uncore_put_constraint(struct intel_uncore_box *box, | ||
200 | struct perf_event *event) | ||
201 | { | ||
202 | struct intel_uncore_extra_reg *er; | ||
203 | struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; | ||
204 | |||
205 | if (box->phys_id < 0 || !reg1->alloc) | ||
206 | return; | ||
207 | |||
208 | er = &box->shared_regs[reg1->idx]; | ||
209 | atomic_dec(&er->ref); | ||
210 | reg1->alloc = 0; | ||
211 | } | ||
212 | |||
213 | static int snbep_uncore_hw_config(struct intel_uncore_box *box, | ||
214 | struct perf_event *event) | ||
215 | { | ||
216 | struct hw_perf_event *hwc = &event->hw; | ||
217 | struct hw_perf_event_extra *reg1 = &hwc->extra_reg; | ||
218 | |||
219 | if (box->pmu->type == &snbep_uncore_cbox) { | ||
220 | reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + | ||
221 | SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx; | ||
222 | reg1->config = event->attr.config1 & | ||
223 | SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK; | ||
224 | } else if (box->pmu->type == &snbep_uncore_pcu) { | ||
225 | reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; | ||
226 | reg1->config = event->attr.config1 & | ||
227 | SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK; | ||
228 | } else { | ||
229 | return 0; | ||
230 | } | ||
231 | reg1->idx = 0; | ||
232 | return 0; | ||
233 | } | ||
234 | |||
235 | static struct attribute *snbep_uncore_formats_attr[] = { | ||
236 | &format_attr_event.attr, | ||
237 | &format_attr_umask.attr, | ||
238 | &format_attr_edge.attr, | ||
239 | &format_attr_inv.attr, | ||
240 | &format_attr_thresh8.attr, | ||
241 | NULL, | ||
242 | }; | ||
243 | |||
244 | static struct attribute *snbep_uncore_ubox_formats_attr[] = { | ||
245 | &format_attr_event.attr, | ||
246 | &format_attr_umask.attr, | ||
247 | &format_attr_edge.attr, | ||
248 | &format_attr_inv.attr, | ||
249 | &format_attr_thresh5.attr, | ||
250 | NULL, | ||
251 | }; | ||
252 | |||
253 | static struct attribute *snbep_uncore_cbox_formats_attr[] = { | ||
254 | &format_attr_event.attr, | ||
255 | &format_attr_umask.attr, | ||
256 | &format_attr_edge.attr, | ||
257 | &format_attr_tid_en.attr, | ||
258 | &format_attr_inv.attr, | ||
259 | &format_attr_thresh8.attr, | ||
260 | &format_attr_filter_tid.attr, | ||
261 | &format_attr_filter_nid.attr, | ||
262 | &format_attr_filter_state.attr, | ||
263 | &format_attr_filter_opc.attr, | ||
264 | NULL, | ||
265 | }; | ||
266 | |||
267 | static struct attribute *snbep_uncore_pcu_formats_attr[] = { | ||
268 | &format_attr_event.attr, | ||
269 | &format_attr_occ_sel.attr, | ||
270 | &format_attr_edge.attr, | ||
271 | &format_attr_inv.attr, | ||
272 | &format_attr_thresh5.attr, | ||
273 | &format_attr_occ_invert.attr, | ||
274 | &format_attr_occ_edge.attr, | ||
275 | &format_attr_filter_brand0.attr, | ||
276 | &format_attr_filter_brand1.attr, | ||
277 | &format_attr_filter_brand2.attr, | ||
278 | &format_attr_filter_brand3.attr, | ||
279 | NULL, | ||
280 | }; | ||
281 | |||
282 | static struct uncore_event_desc snbep_uncore_imc_events[] = { | ||
283 | INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), | ||
284 | INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"), | ||
285 | INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"), | ||
286 | { /* end: all zeroes */ }, | ||
287 | }; | ||
288 | |||
289 | static struct uncore_event_desc snbep_uncore_qpi_events[] = { | ||
290 | INTEL_UNCORE_EVENT_DESC(clockticks, "event=0x14"), | ||
291 | INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"), | ||
292 | INTEL_UNCORE_EVENT_DESC(drs_data, "event=0x02,umask=0x08"), | ||
293 | INTEL_UNCORE_EVENT_DESC(ncb_data, "event=0x03,umask=0x04"), | ||
294 | { /* end: all zeroes */ }, | ||
295 | }; | ||
296 | |||
297 | static struct attribute_group snbep_uncore_format_group = { | ||
298 | .name = "format", | ||
299 | .attrs = snbep_uncore_formats_attr, | ||
300 | }; | ||
301 | |||
302 | static struct attribute_group snbep_uncore_ubox_format_group = { | ||
303 | .name = "format", | ||
304 | .attrs = snbep_uncore_ubox_formats_attr, | ||
305 | }; | ||
306 | |||
307 | static struct attribute_group snbep_uncore_cbox_format_group = { | ||
308 | .name = "format", | ||
309 | .attrs = snbep_uncore_cbox_formats_attr, | ||
310 | }; | ||
311 | |||
312 | static struct attribute_group snbep_uncore_pcu_format_group = { | ||
313 | .name = "format", | ||
314 | .attrs = snbep_uncore_pcu_formats_attr, | ||
315 | }; | ||
316 | |||
317 | static struct intel_uncore_ops snbep_uncore_msr_ops = { | ||
318 | .init_box = snbep_uncore_msr_init_box, | ||
319 | .disable_box = snbep_uncore_msr_disable_box, | ||
320 | .enable_box = snbep_uncore_msr_enable_box, | ||
321 | .disable_event = snbep_uncore_msr_disable_event, | ||
322 | .enable_event = snbep_uncore_msr_enable_event, | ||
323 | .read_counter = snbep_uncore_msr_read_counter, | ||
324 | .get_constraint = snbep_uncore_get_constraint, | ||
325 | .put_constraint = snbep_uncore_put_constraint, | ||
326 | .hw_config = snbep_uncore_hw_config, | ||
327 | }; | ||
328 | |||
329 | static struct intel_uncore_ops snbep_uncore_pci_ops = { | ||
330 | .init_box = snbep_uncore_pci_init_box, | ||
331 | .disable_box = snbep_uncore_pci_disable_box, | ||
332 | .enable_box = snbep_uncore_pci_enable_box, | ||
333 | .disable_event = snbep_uncore_pci_disable_event, | ||
334 | .enable_event = snbep_uncore_pci_enable_event, | ||
335 | .read_counter = snbep_uncore_pci_read_counter, | ||
336 | }; | ||
337 | |||
338 | static struct event_constraint snbep_uncore_cbox_constraints[] = { | ||
339 | UNCORE_EVENT_CONSTRAINT(0x01, 0x1), | ||
340 | UNCORE_EVENT_CONSTRAINT(0x02, 0x3), | ||
341 | UNCORE_EVENT_CONSTRAINT(0x04, 0x3), | ||
342 | UNCORE_EVENT_CONSTRAINT(0x05, 0x3), | ||
343 | UNCORE_EVENT_CONSTRAINT(0x07, 0x3), | ||
344 | UNCORE_EVENT_CONSTRAINT(0x11, 0x1), | ||
345 | UNCORE_EVENT_CONSTRAINT(0x12, 0x3), | ||
346 | UNCORE_EVENT_CONSTRAINT(0x13, 0x3), | ||
347 | UNCORE_EVENT_CONSTRAINT(0x1b, 0xc), | ||
348 | UNCORE_EVENT_CONSTRAINT(0x1c, 0xc), | ||
349 | UNCORE_EVENT_CONSTRAINT(0x1d, 0xc), | ||
350 | UNCORE_EVENT_CONSTRAINT(0x1e, 0xc), | ||
351 | EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff), | ||
352 | UNCORE_EVENT_CONSTRAINT(0x21, 0x3), | ||
353 | UNCORE_EVENT_CONSTRAINT(0x23, 0x3), | ||
354 | UNCORE_EVENT_CONSTRAINT(0x31, 0x3), | ||
355 | UNCORE_EVENT_CONSTRAINT(0x32, 0x3), | ||
356 | UNCORE_EVENT_CONSTRAINT(0x33, 0x3), | ||
357 | UNCORE_EVENT_CONSTRAINT(0x34, 0x3), | ||
358 | UNCORE_EVENT_CONSTRAINT(0x35, 0x3), | ||
359 | UNCORE_EVENT_CONSTRAINT(0x36, 0x1), | ||
360 | UNCORE_EVENT_CONSTRAINT(0x37, 0x3), | ||
361 | UNCORE_EVENT_CONSTRAINT(0x38, 0x3), | ||
362 | UNCORE_EVENT_CONSTRAINT(0x39, 0x3), | ||
363 | UNCORE_EVENT_CONSTRAINT(0x3b, 0x1), | ||
364 | EVENT_CONSTRAINT_END | ||
365 | }; | ||
366 | |||
367 | static struct event_constraint snbep_uncore_r2pcie_constraints[] = { | ||
368 | UNCORE_EVENT_CONSTRAINT(0x10, 0x3), | ||
369 | UNCORE_EVENT_CONSTRAINT(0x11, 0x3), | ||
370 | UNCORE_EVENT_CONSTRAINT(0x12, 0x1), | ||
371 | UNCORE_EVENT_CONSTRAINT(0x23, 0x3), | ||
372 | UNCORE_EVENT_CONSTRAINT(0x24, 0x3), | ||
373 | UNCORE_EVENT_CONSTRAINT(0x25, 0x3), | ||
374 | UNCORE_EVENT_CONSTRAINT(0x26, 0x3), | ||
375 | UNCORE_EVENT_CONSTRAINT(0x32, 0x3), | ||
376 | UNCORE_EVENT_CONSTRAINT(0x33, 0x3), | ||
377 | UNCORE_EVENT_CONSTRAINT(0x34, 0x3), | ||
378 | EVENT_CONSTRAINT_END | ||
379 | }; | ||
380 | |||
381 | static struct event_constraint snbep_uncore_r3qpi_constraints[] = { | ||
382 | UNCORE_EVENT_CONSTRAINT(0x10, 0x3), | ||
383 | UNCORE_EVENT_CONSTRAINT(0x11, 0x3), | ||
384 | UNCORE_EVENT_CONSTRAINT(0x12, 0x3), | ||
385 | UNCORE_EVENT_CONSTRAINT(0x13, 0x1), | ||
386 | UNCORE_EVENT_CONSTRAINT(0x20, 0x3), | ||
387 | UNCORE_EVENT_CONSTRAINT(0x21, 0x3), | ||
388 | UNCORE_EVENT_CONSTRAINT(0x22, 0x3), | ||
389 | UNCORE_EVENT_CONSTRAINT(0x23, 0x3), | ||
390 | UNCORE_EVENT_CONSTRAINT(0x24, 0x3), | ||
391 | UNCORE_EVENT_CONSTRAINT(0x25, 0x3), | ||
392 | UNCORE_EVENT_CONSTRAINT(0x26, 0x3), | ||
393 | UNCORE_EVENT_CONSTRAINT(0x30, 0x3), | ||
394 | UNCORE_EVENT_CONSTRAINT(0x31, 0x3), | ||
395 | UNCORE_EVENT_CONSTRAINT(0x32, 0x3), | ||
396 | UNCORE_EVENT_CONSTRAINT(0x33, 0x3), | ||
397 | UNCORE_EVENT_CONSTRAINT(0x34, 0x3), | ||
398 | UNCORE_EVENT_CONSTRAINT(0x36, 0x3), | ||
399 | UNCORE_EVENT_CONSTRAINT(0x37, 0x3), | ||
400 | EVENT_CONSTRAINT_END | ||
401 | }; | ||
402 | |||
403 | static struct intel_uncore_type snbep_uncore_ubox = { | ||
404 | .name = "ubox", | ||
405 | .num_counters = 2, | ||
406 | .num_boxes = 1, | ||
407 | .perf_ctr_bits = 44, | ||
408 | .fixed_ctr_bits = 48, | ||
409 | .perf_ctr = SNBEP_U_MSR_PMON_CTR0, | ||
410 | .event_ctl = SNBEP_U_MSR_PMON_CTL0, | ||
411 | .event_mask = SNBEP_U_MSR_PMON_RAW_EVENT_MASK, | ||
412 | .fixed_ctr = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR, | ||
413 | .fixed_ctl = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL, | ||
414 | .ops = &snbep_uncore_msr_ops, | ||
415 | .format_group = &snbep_uncore_ubox_format_group, | ||
416 | }; | ||
417 | |||
418 | static struct intel_uncore_type snbep_uncore_cbox = { | ||
419 | .name = "cbox", | ||
420 | .num_counters = 4, | ||
421 | .num_boxes = 8, | ||
422 | .perf_ctr_bits = 44, | ||
423 | .event_ctl = SNBEP_C0_MSR_PMON_CTL0, | ||
424 | .perf_ctr = SNBEP_C0_MSR_PMON_CTR0, | ||
425 | .event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK, | ||
426 | .box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL, | ||
427 | .msr_offset = SNBEP_CBO_MSR_OFFSET, | ||
428 | .num_shared_regs = 1, | ||
429 | .constraints = snbep_uncore_cbox_constraints, | ||
430 | .ops = &snbep_uncore_msr_ops, | ||
431 | .format_group = &snbep_uncore_cbox_format_group, | ||
432 | }; | ||
433 | |||
434 | static struct intel_uncore_type snbep_uncore_pcu = { | ||
435 | .name = "pcu", | ||
436 | .num_counters = 4, | ||
437 | .num_boxes = 1, | ||
438 | .perf_ctr_bits = 48, | ||
439 | .perf_ctr = SNBEP_PCU_MSR_PMON_CTR0, | ||
440 | .event_ctl = SNBEP_PCU_MSR_PMON_CTL0, | ||
441 | .event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK, | ||
442 | .box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL, | ||
443 | .num_shared_regs = 1, | ||
444 | .ops = &snbep_uncore_msr_ops, | ||
445 | .format_group = &snbep_uncore_pcu_format_group, | ||
446 | }; | ||
447 | |||
448 | static struct intel_uncore_type *snbep_msr_uncores[] = { | ||
449 | &snbep_uncore_ubox, | ||
450 | &snbep_uncore_cbox, | ||
451 | &snbep_uncore_pcu, | ||
452 | NULL, | ||
453 | }; | ||
454 | |||
455 | #define SNBEP_UNCORE_PCI_COMMON_INIT() \ | ||
456 | .perf_ctr = SNBEP_PCI_PMON_CTR0, \ | ||
457 | .event_ctl = SNBEP_PCI_PMON_CTL0, \ | ||
458 | .event_mask = SNBEP_PMON_RAW_EVENT_MASK, \ | ||
459 | .box_ctl = SNBEP_PCI_PMON_BOX_CTL, \ | ||
460 | .ops = &snbep_uncore_pci_ops, \ | ||
461 | .format_group = &snbep_uncore_format_group | ||
462 | |||
463 | static struct intel_uncore_type snbep_uncore_ha = { | ||
464 | .name = "ha", | ||
465 | .num_counters = 4, | ||
466 | .num_boxes = 1, | ||
467 | .perf_ctr_bits = 48, | ||
468 | SNBEP_UNCORE_PCI_COMMON_INIT(), | ||
469 | }; | ||
470 | |||
471 | static struct intel_uncore_type snbep_uncore_imc = { | ||
472 | .name = "imc", | ||
473 | .num_counters = 4, | ||
474 | .num_boxes = 4, | ||
475 | .perf_ctr_bits = 48, | ||
476 | .fixed_ctr_bits = 48, | ||
477 | .fixed_ctr = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR, | ||
478 | .fixed_ctl = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL, | ||
479 | .event_descs = snbep_uncore_imc_events, | ||
480 | SNBEP_UNCORE_PCI_COMMON_INIT(), | ||
481 | }; | ||
482 | |||
483 | static struct intel_uncore_type snbep_uncore_qpi = { | ||
484 | .name = "qpi", | ||
485 | .num_counters = 4, | ||
486 | .num_boxes = 2, | ||
487 | .perf_ctr_bits = 48, | ||
488 | .event_descs = snbep_uncore_qpi_events, | ||
489 | SNBEP_UNCORE_PCI_COMMON_INIT(), | ||
490 | }; | ||
491 | |||
492 | |||
493 | static struct intel_uncore_type snbep_uncore_r2pcie = { | ||
494 | .name = "r2pcie", | ||
495 | .num_counters = 4, | ||
496 | .num_boxes = 1, | ||
497 | .perf_ctr_bits = 44, | ||
498 | .constraints = snbep_uncore_r2pcie_constraints, | ||
499 | SNBEP_UNCORE_PCI_COMMON_INIT(), | ||
500 | }; | ||
501 | |||
502 | static struct intel_uncore_type snbep_uncore_r3qpi = { | ||
503 | .name = "r3qpi", | ||
504 | .num_counters = 3, | ||
505 | .num_boxes = 2, | ||
506 | .perf_ctr_bits = 44, | ||
507 | .constraints = snbep_uncore_r3qpi_constraints, | ||
508 | SNBEP_UNCORE_PCI_COMMON_INIT(), | ||
509 | }; | ||
510 | |||
511 | static struct intel_uncore_type *snbep_pci_uncores[] = { | ||
512 | &snbep_uncore_ha, | ||
513 | &snbep_uncore_imc, | ||
514 | &snbep_uncore_qpi, | ||
515 | &snbep_uncore_r2pcie, | ||
516 | &snbep_uncore_r3qpi, | ||
517 | NULL, | ||
518 | }; | ||
519 | |||
520 | static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = { | ||
521 | { /* Home Agent */ | ||
522 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA), | ||
523 | .driver_data = (unsigned long)&snbep_uncore_ha, | ||
524 | }, | ||
525 | { /* MC Channel 0 */ | ||
526 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0), | ||
527 | .driver_data = (unsigned long)&snbep_uncore_imc, | ||
528 | }, | ||
529 | { /* MC Channel 1 */ | ||
530 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1), | ||
531 | .driver_data = (unsigned long)&snbep_uncore_imc, | ||
532 | }, | ||
533 | { /* MC Channel 2 */ | ||
534 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2), | ||
535 | .driver_data = (unsigned long)&snbep_uncore_imc, | ||
536 | }, | ||
537 | { /* MC Channel 3 */ | ||
538 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3), | ||
539 | .driver_data = (unsigned long)&snbep_uncore_imc, | ||
540 | }, | ||
541 | { /* QPI Port 0 */ | ||
542 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0), | ||
543 | .driver_data = (unsigned long)&snbep_uncore_qpi, | ||
544 | }, | ||
545 | { /* QPI Port 1 */ | ||
546 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1), | ||
547 | .driver_data = (unsigned long)&snbep_uncore_qpi, | ||
548 | }, | ||
549 | { /* P2PCIe */ | ||
550 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE), | ||
551 | .driver_data = (unsigned long)&snbep_uncore_r2pcie, | ||
552 | }, | ||
553 | { /* R3QPI Link 0 */ | ||
554 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0), | ||
555 | .driver_data = (unsigned long)&snbep_uncore_r3qpi, | ||
556 | }, | ||
557 | { /* R3QPI Link 1 */ | ||
558 | PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1), | ||
559 | .driver_data = (unsigned long)&snbep_uncore_r3qpi, | ||
560 | }, | ||
561 | { /* end: all zeroes */ } | ||
562 | }; | ||
563 | |||
564 | static struct pci_driver snbep_uncore_pci_driver = { | ||
565 | .name = "snbep_uncore", | ||
566 | .id_table = snbep_uncore_pci_ids, | ||
567 | }; | ||
568 | |||
569 | /* | ||
570 | * build pci bus to socket mapping | ||
571 | */ | ||
572 | static void snbep_pci2phy_map_init(void) | ||
573 | { | ||
574 | struct pci_dev *ubox_dev = NULL; | ||
575 | int i, bus, nodeid; | ||
576 | u32 config; | ||
577 | |||
578 | while (1) { | ||
579 | /* find the UBOX device */ | ||
580 | ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, | ||
581 | PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX, | ||
582 | ubox_dev); | ||
583 | if (!ubox_dev) | ||
584 | break; | ||
585 | bus = ubox_dev->bus->number; | ||
586 | /* get the Node ID of the local register */ | ||
587 | pci_read_config_dword(ubox_dev, 0x40, &config); | ||
588 | nodeid = config; | ||
589 | /* get the Node ID mapping */ | ||
590 | pci_read_config_dword(ubox_dev, 0x54, &config); | ||
591 | /* | ||
592 | * every three bits in the Node ID mapping register maps | ||
593 | * to a particular node. | ||
594 | */ | ||
595 | for (i = 0; i < 8; i++) { | ||
596 | if (nodeid == ((config >> (3 * i)) & 0x7)) { | ||
597 | pcibus_to_physid[bus] = i; | ||
598 | break; | ||
599 | } | ||
600 | } | ||
601 | }; | ||
602 | return; | ||
603 | } | ||
604 | /* end of Sandy Bridge-EP uncore support */ | ||
605 | |||
606 | |||
607 | /* Sandy Bridge uncore support */ | ||
608 | static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, | ||
609 | struct perf_event *event) | ||
610 | { | ||
611 | struct hw_perf_event *hwc = &event->hw; | ||
612 | |||
613 | if (hwc->idx < UNCORE_PMC_IDX_FIXED) | ||
614 | wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); | ||
615 | else | ||
616 | wrmsrl(hwc->config_base, SNB_UNC_CTL_EN); | ||
617 | } | ||
618 | |||
619 | static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, | ||
620 | struct perf_event *event) | ||
621 | { | ||
622 | wrmsrl(event->hw.config_base, 0); | ||
623 | } | ||
624 | |||
625 | static u64 snb_uncore_msr_read_counter(struct intel_uncore_box *box, | ||
626 | struct perf_event *event) | ||
627 | { | ||
628 | u64 count; | ||
629 | rdmsrl(event->hw.event_base, count); | ||
630 | return count; | ||
631 | } | ||
632 | |||
633 | static void snb_uncore_msr_init_box(struct intel_uncore_box *box) | ||
634 | { | ||
635 | if (box->pmu->pmu_idx == 0) { | ||
636 | wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, | ||
637 | SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); | ||
638 | } | ||
639 | } | ||
640 | |||
641 | static struct attribute *snb_uncore_formats_attr[] = { | ||
642 | &format_attr_event.attr, | ||
643 | &format_attr_umask.attr, | ||
644 | &format_attr_edge.attr, | ||
645 | &format_attr_inv.attr, | ||
646 | &format_attr_cmask5.attr, | ||
647 | NULL, | ||
648 | }; | ||
649 | |||
650 | static struct attribute_group snb_uncore_format_group = { | ||
651 | .name = "format", | ||
652 | .attrs = snb_uncore_formats_attr, | ||
653 | }; | ||
654 | |||
655 | static struct intel_uncore_ops snb_uncore_msr_ops = { | ||
656 | .init_box = snb_uncore_msr_init_box, | ||
657 | .disable_event = snb_uncore_msr_disable_event, | ||
658 | .enable_event = snb_uncore_msr_enable_event, | ||
659 | .read_counter = snb_uncore_msr_read_counter, | ||
660 | }; | ||
661 | |||
662 | static struct event_constraint snb_uncore_cbox_constraints[] = { | ||
663 | UNCORE_EVENT_CONSTRAINT(0x80, 0x1), | ||
664 | UNCORE_EVENT_CONSTRAINT(0x83, 0x1), | ||
665 | EVENT_CONSTRAINT_END | ||
666 | }; | ||
667 | |||
668 | static struct intel_uncore_type snb_uncore_cbox = { | ||
669 | .name = "cbox", | ||
670 | .num_counters = 2, | ||
671 | .num_boxes = 4, | ||
672 | .perf_ctr_bits = 44, | ||
673 | .fixed_ctr_bits = 48, | ||
674 | .perf_ctr = SNB_UNC_CBO_0_PER_CTR0, | ||
675 | .event_ctl = SNB_UNC_CBO_0_PERFEVTSEL0, | ||
676 | .fixed_ctr = SNB_UNC_FIXED_CTR, | ||
677 | .fixed_ctl = SNB_UNC_FIXED_CTR_CTRL, | ||
678 | .single_fixed = 1, | ||
679 | .event_mask = SNB_UNC_RAW_EVENT_MASK, | ||
680 | .msr_offset = SNB_UNC_CBO_MSR_OFFSET, | ||
681 | .constraints = snb_uncore_cbox_constraints, | ||
682 | .ops = &snb_uncore_msr_ops, | ||
683 | .format_group = &snb_uncore_format_group, | ||
684 | }; | ||
685 | |||
686 | static struct intel_uncore_type *snb_msr_uncores[] = { | ||
687 | &snb_uncore_cbox, | ||
688 | NULL, | ||
689 | }; | ||
690 | /* end of Sandy Bridge uncore support */ | ||
691 | |||
692 | /* Nehalem uncore support */ | ||
693 | static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box) | ||
694 | { | ||
695 | wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); | ||
696 | } | ||
697 | |||
698 | static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box) | ||
699 | { | ||
700 | wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, | ||
701 | NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC); | ||
702 | } | ||
703 | |||
704 | static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, | ||
705 | struct perf_event *event) | ||
706 | { | ||
707 | struct hw_perf_event *hwc = &event->hw; | ||
708 | |||
709 | if (hwc->idx < UNCORE_PMC_IDX_FIXED) | ||
710 | wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN); | ||
711 | else | ||
712 | wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN); | ||
713 | } | ||
714 | |||
715 | static struct attribute *nhm_uncore_formats_attr[] = { | ||
716 | &format_attr_event.attr, | ||
717 | &format_attr_umask.attr, | ||
718 | &format_attr_edge.attr, | ||
719 | &format_attr_inv.attr, | ||
720 | &format_attr_cmask8.attr, | ||
721 | NULL, | ||
722 | }; | ||
723 | |||
724 | static struct attribute_group nhm_uncore_format_group = { | ||
725 | .name = "format", | ||
726 | .attrs = nhm_uncore_formats_attr, | ||
727 | }; | ||
728 | |||
729 | static struct uncore_event_desc nhm_uncore_events[] = { | ||
730 | INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"), | ||
731 | INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"), | ||
732 | INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"), | ||
733 | INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"), | ||
734 | INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"), | ||
735 | INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"), | ||
736 | INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"), | ||
737 | INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"), | ||
738 | INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"), | ||
739 | { /* end: all zeroes */ }, | ||
740 | }; | ||
741 | |||
742 | static struct intel_uncore_ops nhm_uncore_msr_ops = { | ||
743 | .disable_box = nhm_uncore_msr_disable_box, | ||
744 | .enable_box = nhm_uncore_msr_enable_box, | ||
745 | .disable_event = snb_uncore_msr_disable_event, | ||
746 | .enable_event = nhm_uncore_msr_enable_event, | ||
747 | .read_counter = snb_uncore_msr_read_counter, | ||
748 | }; | ||
749 | |||
750 | static struct intel_uncore_type nhm_uncore = { | ||
751 | .name = "", | ||
752 | .num_counters = 8, | ||
753 | .num_boxes = 1, | ||
754 | .perf_ctr_bits = 48, | ||
755 | .fixed_ctr_bits = 48, | ||
756 | .event_ctl = NHM_UNC_PERFEVTSEL0, | ||
757 | .perf_ctr = NHM_UNC_UNCORE_PMC0, | ||
758 | .fixed_ctr = NHM_UNC_FIXED_CTR, | ||
759 | .fixed_ctl = NHM_UNC_FIXED_CTR_CTRL, | ||
760 | .event_mask = NHM_UNC_RAW_EVENT_MASK, | ||
761 | .event_descs = nhm_uncore_events, | ||
762 | .ops = &nhm_uncore_msr_ops, | ||
763 | .format_group = &nhm_uncore_format_group, | ||
764 | }; | ||
765 | |||
766 | static struct intel_uncore_type *nhm_msr_uncores[] = { | ||
767 | &nhm_uncore, | ||
768 | NULL, | ||
769 | }; | ||
770 | /* end of Nehalem uncore support */ | ||
771 | |||
772 | static void uncore_assign_hw_event(struct intel_uncore_box *box, | ||
773 | struct perf_event *event, int idx) | ||
774 | { | ||
775 | struct hw_perf_event *hwc = &event->hw; | ||
776 | |||
777 | hwc->idx = idx; | ||
778 | hwc->last_tag = ++box->tags[idx]; | ||
779 | |||
780 | if (hwc->idx == UNCORE_PMC_IDX_FIXED) { | ||
781 | hwc->event_base = uncore_fixed_ctr(box); | ||
782 | hwc->config_base = uncore_fixed_ctl(box); | ||
783 | return; | ||
784 | } | ||
785 | |||
786 | hwc->config_base = uncore_event_ctl(box, hwc->idx); | ||
787 | hwc->event_base = uncore_perf_ctr(box, hwc->idx); | ||
788 | } | ||
789 | |||
790 | static void uncore_perf_event_update(struct intel_uncore_box *box, | ||
791 | struct perf_event *event) | ||
792 | { | ||
793 | u64 prev_count, new_count, delta; | ||
794 | int shift; | ||
795 | |||
796 | if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) | ||
797 | shift = 64 - uncore_fixed_ctr_bits(box); | ||
798 | else | ||
799 | shift = 64 - uncore_perf_ctr_bits(box); | ||
800 | |||
801 | /* the hrtimer might modify the previous event value */ | ||
802 | again: | ||
803 | prev_count = local64_read(&event->hw.prev_count); | ||
804 | new_count = uncore_read_counter(box, event); | ||
805 | if (local64_xchg(&event->hw.prev_count, new_count) != prev_count) | ||
806 | goto again; | ||
807 | |||
808 | delta = (new_count << shift) - (prev_count << shift); | ||
809 | delta >>= shift; | ||
810 | |||
811 | local64_add(delta, &event->count); | ||
812 | } | ||
813 | |||
814 | /* | ||
815 | * The overflow interrupt is unavailable for SandyBridge-EP, is broken | ||
816 | * for SandyBridge. So we use hrtimer to periodically poll the counter | ||
817 | * to avoid overflow. | ||
818 | */ | ||
819 | static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer) | ||
820 | { | ||
821 | struct intel_uncore_box *box; | ||
822 | unsigned long flags; | ||
823 | int bit; | ||
824 | |||
825 | box = container_of(hrtimer, struct intel_uncore_box, hrtimer); | ||
826 | if (!box->n_active || box->cpu != smp_processor_id()) | ||
827 | return HRTIMER_NORESTART; | ||
828 | /* | ||
829 | * disable local interrupt to prevent uncore_pmu_event_start/stop | ||
830 | * to interrupt the update process | ||
831 | */ | ||
832 | local_irq_save(flags); | ||
833 | |||
834 | for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX) | ||
835 | uncore_perf_event_update(box, box->events[bit]); | ||
836 | |||
837 | local_irq_restore(flags); | ||
838 | |||
839 | hrtimer_forward_now(hrtimer, ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL)); | ||
840 | return HRTIMER_RESTART; | ||
841 | } | ||
842 | |||
843 | static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box) | ||
844 | { | ||
845 | __hrtimer_start_range_ns(&box->hrtimer, | ||
846 | ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL), 0, | ||
847 | HRTIMER_MODE_REL_PINNED, 0); | ||
848 | } | ||
849 | |||
850 | static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box) | ||
851 | { | ||
852 | hrtimer_cancel(&box->hrtimer); | ||
853 | } | ||
854 | |||
855 | static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box) | ||
856 | { | ||
857 | hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | ||
858 | box->hrtimer.function = uncore_pmu_hrtimer; | ||
859 | } | ||
860 | |||
861 | struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, | ||
862 | int cpu) | ||
863 | { | ||
864 | struct intel_uncore_box *box; | ||
865 | int i, size; | ||
866 | |||
867 | size = sizeof(*box) + type->num_shared_regs * | ||
868 | sizeof(struct intel_uncore_extra_reg); | ||
869 | |||
870 | box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu)); | ||
871 | if (!box) | ||
872 | return NULL; | ||
873 | |||
874 | for (i = 0; i < type->num_shared_regs; i++) | ||
875 | raw_spin_lock_init(&box->shared_regs[i].lock); | ||
876 | |||
877 | uncore_pmu_init_hrtimer(box); | ||
878 | atomic_set(&box->refcnt, 1); | ||
879 | box->cpu = -1; | ||
880 | box->phys_id = -1; | ||
881 | |||
882 | return box; | ||
883 | } | ||
884 | |||
885 | static struct intel_uncore_box * | ||
886 | uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu) | ||
887 | { | ||
888 | static struct intel_uncore_box *box; | ||
889 | |||
890 | box = *per_cpu_ptr(pmu->box, cpu); | ||
891 | if (box) | ||
892 | return box; | ||
893 | |||
894 | raw_spin_lock(&uncore_box_lock); | ||
895 | list_for_each_entry(box, &pmu->box_list, list) { | ||
896 | if (box->phys_id == topology_physical_package_id(cpu)) { | ||
897 | atomic_inc(&box->refcnt); | ||
898 | *per_cpu_ptr(pmu->box, cpu) = box; | ||
899 | break; | ||
900 | } | ||
901 | } | ||
902 | raw_spin_unlock(&uncore_box_lock); | ||
903 | |||
904 | return *per_cpu_ptr(pmu->box, cpu); | ||
905 | } | ||
906 | |||
907 | static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event) | ||
908 | { | ||
909 | return container_of(event->pmu, struct intel_uncore_pmu, pmu); | ||
910 | } | ||
911 | |||
912 | static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event) | ||
913 | { | ||
914 | /* | ||
915 | * perf core schedules event on the basis of cpu, uncore events are | ||
916 | * collected by one of the cpus inside a physical package. | ||
917 | */ | ||
918 | return uncore_pmu_to_box(uncore_event_to_pmu(event), | ||
919 | smp_processor_id()); | ||
920 | } | ||
921 | |||
922 | static int uncore_collect_events(struct intel_uncore_box *box, | ||
923 | struct perf_event *leader, bool dogrp) | ||
924 | { | ||
925 | struct perf_event *event; | ||
926 | int n, max_count; | ||
927 | |||
928 | max_count = box->pmu->type->num_counters; | ||
929 | if (box->pmu->type->fixed_ctl) | ||
930 | max_count++; | ||
931 | |||
932 | if (box->n_events >= max_count) | ||
933 | return -EINVAL; | ||
934 | |||
935 | n = box->n_events; | ||
936 | box->event_list[n] = leader; | ||
937 | n++; | ||
938 | if (!dogrp) | ||
939 | return n; | ||
940 | |||
941 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | ||
942 | if (event->state <= PERF_EVENT_STATE_OFF) | ||
943 | continue; | ||
944 | |||
945 | if (n >= max_count) | ||
946 | return -EINVAL; | ||
947 | |||
948 | box->event_list[n] = event; | ||
949 | n++; | ||
950 | } | ||
951 | return n; | ||
952 | } | ||
953 | |||
954 | static struct event_constraint * | ||
955 | uncore_get_event_constraint(struct intel_uncore_box *box, | ||
956 | struct perf_event *event) | ||
957 | { | ||
958 | struct intel_uncore_type *type = box->pmu->type; | ||
959 | struct event_constraint *c; | ||
960 | |||
961 | if (type->ops->get_constraint) { | ||
962 | c = type->ops->get_constraint(box, event); | ||
963 | if (c) | ||
964 | return c; | ||
965 | } | ||
966 | |||
967 | if (event->hw.config == ~0ULL) | ||
968 | return &constraint_fixed; | ||
969 | |||
970 | if (type->constraints) { | ||
971 | for_each_event_constraint(c, type->constraints) { | ||
972 | if ((event->hw.config & c->cmask) == c->code) | ||
973 | return c; | ||
974 | } | ||
975 | } | ||
976 | |||
977 | return &type->unconstrainted; | ||
978 | } | ||
979 | |||
980 | static void uncore_put_event_constraint(struct intel_uncore_box *box, | ||
981 | struct perf_event *event) | ||
982 | { | ||
983 | if (box->pmu->type->ops->put_constraint) | ||
984 | box->pmu->type->ops->put_constraint(box, event); | ||
985 | } | ||
986 | |||
987 | static int uncore_assign_events(struct intel_uncore_box *box, | ||
988 | int assign[], int n) | ||
989 | { | ||
990 | unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; | ||
991 | struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX]; | ||
992 | int i, wmin, wmax, ret = 0; | ||
993 | struct hw_perf_event *hwc; | ||
994 | |||
995 | bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX); | ||
996 | |||
997 | for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) { | ||
998 | c = uncore_get_event_constraint(box, box->event_list[i]); | ||
999 | constraints[i] = c; | ||
1000 | wmin = min(wmin, c->weight); | ||
1001 | wmax = max(wmax, c->weight); | ||
1002 | } | ||
1003 | |||
1004 | /* fastpath, try to reuse previous register */ | ||
1005 | for (i = 0; i < n; i++) { | ||
1006 | hwc = &box->event_list[i]->hw; | ||
1007 | c = constraints[i]; | ||
1008 | |||
1009 | /* never assigned */ | ||
1010 | if (hwc->idx == -1) | ||
1011 | break; | ||
1012 | |||
1013 | /* constraint still honored */ | ||
1014 | if (!test_bit(hwc->idx, c->idxmsk)) | ||
1015 | break; | ||
1016 | |||
1017 | /* not already used */ | ||
1018 | if (test_bit(hwc->idx, used_mask)) | ||
1019 | break; | ||
1020 | |||
1021 | __set_bit(hwc->idx, used_mask); | ||
1022 | if (assign) | ||
1023 | assign[i] = hwc->idx; | ||
1024 | } | ||
1025 | /* slow path */ | ||
1026 | if (i != n) | ||
1027 | ret = perf_assign_events(constraints, n, wmin, wmax, assign); | ||
1028 | |||
1029 | if (!assign || ret) { | ||
1030 | for (i = 0; i < n; i++) | ||
1031 | uncore_put_event_constraint(box, box->event_list[i]); | ||
1032 | } | ||
1033 | return ret ? -EINVAL : 0; | ||
1034 | } | ||
1035 | |||
1036 | static void uncore_pmu_event_start(struct perf_event *event, int flags) | ||
1037 | { | ||
1038 | struct intel_uncore_box *box = uncore_event_to_box(event); | ||
1039 | int idx = event->hw.idx; | ||
1040 | |||
1041 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | ||
1042 | return; | ||
1043 | |||
1044 | if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX)) | ||
1045 | return; | ||
1046 | |||
1047 | event->hw.state = 0; | ||
1048 | box->events[idx] = event; | ||
1049 | box->n_active++; | ||
1050 | __set_bit(idx, box->active_mask); | ||
1051 | |||
1052 | local64_set(&event->hw.prev_count, uncore_read_counter(box, event)); | ||
1053 | uncore_enable_event(box, event); | ||
1054 | |||
1055 | if (box->n_active == 1) { | ||
1056 | uncore_enable_box(box); | ||
1057 | uncore_pmu_start_hrtimer(box); | ||
1058 | } | ||
1059 | } | ||
1060 | |||
1061 | static void uncore_pmu_event_stop(struct perf_event *event, int flags) | ||
1062 | { | ||
1063 | struct intel_uncore_box *box = uncore_event_to_box(event); | ||
1064 | struct hw_perf_event *hwc = &event->hw; | ||
1065 | |||
1066 | if (__test_and_clear_bit(hwc->idx, box->active_mask)) { | ||
1067 | uncore_disable_event(box, event); | ||
1068 | box->n_active--; | ||
1069 | box->events[hwc->idx] = NULL; | ||
1070 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | ||
1071 | hwc->state |= PERF_HES_STOPPED; | ||
1072 | |||
1073 | if (box->n_active == 0) { | ||
1074 | uncore_disable_box(box); | ||
1075 | uncore_pmu_cancel_hrtimer(box); | ||
1076 | } | ||
1077 | } | ||
1078 | |||
1079 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | ||
1080 | /* | ||
1081 | * Drain the remaining delta count out of a event | ||
1082 | * that we are disabling: | ||
1083 | */ | ||
1084 | uncore_perf_event_update(box, event); | ||
1085 | hwc->state |= PERF_HES_UPTODATE; | ||
1086 | } | ||
1087 | } | ||
1088 | |||
1089 | static int uncore_pmu_event_add(struct perf_event *event, int flags) | ||
1090 | { | ||
1091 | struct intel_uncore_box *box = uncore_event_to_box(event); | ||
1092 | struct hw_perf_event *hwc = &event->hw; | ||
1093 | int assign[UNCORE_PMC_IDX_MAX]; | ||
1094 | int i, n, ret; | ||
1095 | |||
1096 | if (!box) | ||
1097 | return -ENODEV; | ||
1098 | |||
1099 | ret = n = uncore_collect_events(box, event, false); | ||
1100 | if (ret < 0) | ||
1101 | return ret; | ||
1102 | |||
1103 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | ||
1104 | if (!(flags & PERF_EF_START)) | ||
1105 | hwc->state |= PERF_HES_ARCH; | ||
1106 | |||
1107 | ret = uncore_assign_events(box, assign, n); | ||
1108 | if (ret) | ||
1109 | return ret; | ||
1110 | |||
1111 | /* save events moving to new counters */ | ||
1112 | for (i = 0; i < box->n_events; i++) { | ||
1113 | event = box->event_list[i]; | ||
1114 | hwc = &event->hw; | ||
1115 | |||
1116 | if (hwc->idx == assign[i] && | ||
1117 | hwc->last_tag == box->tags[assign[i]]) | ||
1118 | continue; | ||
1119 | /* | ||
1120 | * Ensure we don't accidentally enable a stopped | ||
1121 | * counter simply because we rescheduled. | ||
1122 | */ | ||
1123 | if (hwc->state & PERF_HES_STOPPED) | ||
1124 | hwc->state |= PERF_HES_ARCH; | ||
1125 | |||
1126 | uncore_pmu_event_stop(event, PERF_EF_UPDATE); | ||
1127 | } | ||
1128 | |||
1129 | /* reprogram moved events into new counters */ | ||
1130 | for (i = 0; i < n; i++) { | ||
1131 | event = box->event_list[i]; | ||
1132 | hwc = &event->hw; | ||
1133 | |||
1134 | if (hwc->idx != assign[i] || | ||
1135 | hwc->last_tag != box->tags[assign[i]]) | ||
1136 | uncore_assign_hw_event(box, event, assign[i]); | ||
1137 | else if (i < box->n_events) | ||
1138 | continue; | ||
1139 | |||
1140 | if (hwc->state & PERF_HES_ARCH) | ||
1141 | continue; | ||
1142 | |||
1143 | uncore_pmu_event_start(event, 0); | ||
1144 | } | ||
1145 | box->n_events = n; | ||
1146 | |||
1147 | return 0; | ||
1148 | } | ||
1149 | |||
1150 | static void uncore_pmu_event_del(struct perf_event *event, int flags) | ||
1151 | { | ||
1152 | struct intel_uncore_box *box = uncore_event_to_box(event); | ||
1153 | int i; | ||
1154 | |||
1155 | uncore_pmu_event_stop(event, PERF_EF_UPDATE); | ||
1156 | |||
1157 | for (i = 0; i < box->n_events; i++) { | ||
1158 | if (event == box->event_list[i]) { | ||
1159 | uncore_put_event_constraint(box, event); | ||
1160 | |||
1161 | while (++i < box->n_events) | ||
1162 | box->event_list[i - 1] = box->event_list[i]; | ||
1163 | |||
1164 | --box->n_events; | ||
1165 | break; | ||
1166 | } | ||
1167 | } | ||
1168 | |||
1169 | event->hw.idx = -1; | ||
1170 | event->hw.last_tag = ~0ULL; | ||
1171 | } | ||
1172 | |||
1173 | static void uncore_pmu_event_read(struct perf_event *event) | ||
1174 | { | ||
1175 | struct intel_uncore_box *box = uncore_event_to_box(event); | ||
1176 | uncore_perf_event_update(box, event); | ||
1177 | } | ||
1178 | |||
1179 | /* | ||
1180 | * validation ensures the group can be loaded onto the | ||
1181 | * PMU if it was the only group available. | ||
1182 | */ | ||
1183 | static int uncore_validate_group(struct intel_uncore_pmu *pmu, | ||
1184 | struct perf_event *event) | ||
1185 | { | ||
1186 | struct perf_event *leader = event->group_leader; | ||
1187 | struct intel_uncore_box *fake_box; | ||
1188 | int ret = -EINVAL, n; | ||
1189 | |||
1190 | fake_box = uncore_alloc_box(pmu->type, smp_processor_id()); | ||
1191 | if (!fake_box) | ||
1192 | return -ENOMEM; | ||
1193 | |||
1194 | fake_box->pmu = pmu; | ||
1195 | /* | ||
1196 | * the event is not yet connected with its | ||
1197 | * siblings therefore we must first collect | ||
1198 | * existing siblings, then add the new event | ||
1199 | * before we can simulate the scheduling | ||
1200 | */ | ||
1201 | n = uncore_collect_events(fake_box, leader, true); | ||
1202 | if (n < 0) | ||
1203 | goto out; | ||
1204 | |||
1205 | fake_box->n_events = n; | ||
1206 | n = uncore_collect_events(fake_box, event, false); | ||
1207 | if (n < 0) | ||
1208 | goto out; | ||
1209 | |||
1210 | fake_box->n_events = n; | ||
1211 | |||
1212 | ret = uncore_assign_events(fake_box, NULL, n); | ||
1213 | out: | ||
1214 | kfree(fake_box); | ||
1215 | return ret; | ||
1216 | } | ||
1217 | |||
1218 | int uncore_pmu_event_init(struct perf_event *event) | ||
1219 | { | ||
1220 | struct intel_uncore_pmu *pmu; | ||
1221 | struct intel_uncore_box *box; | ||
1222 | struct hw_perf_event *hwc = &event->hw; | ||
1223 | int ret; | ||
1224 | |||
1225 | if (event->attr.type != event->pmu->type) | ||
1226 | return -ENOENT; | ||
1227 | |||
1228 | pmu = uncore_event_to_pmu(event); | ||
1229 | /* no device found for this pmu */ | ||
1230 | if (pmu->func_id < 0) | ||
1231 | return -ENOENT; | ||
1232 | |||
1233 | /* | ||
1234 | * Uncore PMU does measure at all privilege level all the time. | ||
1235 | * So it doesn't make sense to specify any exclude bits. | ||
1236 | */ | ||
1237 | if (event->attr.exclude_user || event->attr.exclude_kernel || | ||
1238 | event->attr.exclude_hv || event->attr.exclude_idle) | ||
1239 | return -EINVAL; | ||
1240 | |||
1241 | /* Sampling not supported yet */ | ||
1242 | if (hwc->sample_period) | ||
1243 | return -EINVAL; | ||
1244 | |||
1245 | /* | ||
1246 | * Place all uncore events for a particular physical package | ||
1247 | * onto a single cpu | ||
1248 | */ | ||
1249 | if (event->cpu < 0) | ||
1250 | return -EINVAL; | ||
1251 | box = uncore_pmu_to_box(pmu, event->cpu); | ||
1252 | if (!box || box->cpu < 0) | ||
1253 | return -EINVAL; | ||
1254 | event->cpu = box->cpu; | ||
1255 | |||
1256 | event->hw.idx = -1; | ||
1257 | event->hw.last_tag = ~0ULL; | ||
1258 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | ||
1259 | |||
1260 | if (event->attr.config == UNCORE_FIXED_EVENT) { | ||
1261 | /* no fixed counter */ | ||
1262 | if (!pmu->type->fixed_ctl) | ||
1263 | return -EINVAL; | ||
1264 | /* | ||
1265 | * if there is only one fixed counter, only the first pmu | ||
1266 | * can access the fixed counter | ||
1267 | */ | ||
1268 | if (pmu->type->single_fixed && pmu->pmu_idx > 0) | ||
1269 | return -EINVAL; | ||
1270 | hwc->config = ~0ULL; | ||
1271 | } else { | ||
1272 | hwc->config = event->attr.config & pmu->type->event_mask; | ||
1273 | if (pmu->type->ops->hw_config) { | ||
1274 | ret = pmu->type->ops->hw_config(box, event); | ||
1275 | if (ret) | ||
1276 | return ret; | ||
1277 | } | ||
1278 | } | ||
1279 | |||
1280 | if (event->group_leader != event) | ||
1281 | ret = uncore_validate_group(pmu, event); | ||
1282 | else | ||
1283 | ret = 0; | ||
1284 | |||
1285 | return ret; | ||
1286 | } | ||
1287 | |||
1288 | static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu) | ||
1289 | { | ||
1290 | int ret; | ||
1291 | |||
1292 | pmu->pmu = (struct pmu) { | ||
1293 | .attr_groups = pmu->type->attr_groups, | ||
1294 | .task_ctx_nr = perf_invalid_context, | ||
1295 | .event_init = uncore_pmu_event_init, | ||
1296 | .add = uncore_pmu_event_add, | ||
1297 | .del = uncore_pmu_event_del, | ||
1298 | .start = uncore_pmu_event_start, | ||
1299 | .stop = uncore_pmu_event_stop, | ||
1300 | .read = uncore_pmu_event_read, | ||
1301 | }; | ||
1302 | |||
1303 | if (pmu->type->num_boxes == 1) { | ||
1304 | if (strlen(pmu->type->name) > 0) | ||
1305 | sprintf(pmu->name, "uncore_%s", pmu->type->name); | ||
1306 | else | ||
1307 | sprintf(pmu->name, "uncore"); | ||
1308 | } else { | ||
1309 | sprintf(pmu->name, "uncore_%s_%d", pmu->type->name, | ||
1310 | pmu->pmu_idx); | ||
1311 | } | ||
1312 | |||
1313 | ret = perf_pmu_register(&pmu->pmu, pmu->name, -1); | ||
1314 | return ret; | ||
1315 | } | ||
1316 | |||
1317 | static void __init uncore_type_exit(struct intel_uncore_type *type) | ||
1318 | { | ||
1319 | int i; | ||
1320 | |||
1321 | for (i = 0; i < type->num_boxes; i++) | ||
1322 | free_percpu(type->pmus[i].box); | ||
1323 | kfree(type->pmus); | ||
1324 | type->pmus = NULL; | ||
1325 | kfree(type->attr_groups[1]); | ||
1326 | type->attr_groups[1] = NULL; | ||
1327 | } | ||
1328 | |||
1329 | static void uncore_types_exit(struct intel_uncore_type **types) | ||
1330 | { | ||
1331 | int i; | ||
1332 | for (i = 0; types[i]; i++) | ||
1333 | uncore_type_exit(types[i]); | ||
1334 | } | ||
1335 | |||
1336 | static int __init uncore_type_init(struct intel_uncore_type *type) | ||
1337 | { | ||
1338 | struct intel_uncore_pmu *pmus; | ||
1339 | struct attribute_group *events_group; | ||
1340 | struct attribute **attrs; | ||
1341 | int i, j; | ||
1342 | |||
1343 | pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL); | ||
1344 | if (!pmus) | ||
1345 | return -ENOMEM; | ||
1346 | |||
1347 | type->unconstrainted = (struct event_constraint) | ||
1348 | __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1, | ||
1349 | 0, type->num_counters, 0); | ||
1350 | |||
1351 | for (i = 0; i < type->num_boxes; i++) { | ||
1352 | pmus[i].func_id = -1; | ||
1353 | pmus[i].pmu_idx = i; | ||
1354 | pmus[i].type = type; | ||
1355 | INIT_LIST_HEAD(&pmus[i].box_list); | ||
1356 | pmus[i].box = alloc_percpu(struct intel_uncore_box *); | ||
1357 | if (!pmus[i].box) | ||
1358 | goto fail; | ||
1359 | } | ||
1360 | |||
1361 | if (type->event_descs) { | ||
1362 | i = 0; | ||
1363 | while (type->event_descs[i].attr.attr.name) | ||
1364 | i++; | ||
1365 | |||
1366 | events_group = kzalloc(sizeof(struct attribute *) * (i + 1) + | ||
1367 | sizeof(*events_group), GFP_KERNEL); | ||
1368 | if (!events_group) | ||
1369 | goto fail; | ||
1370 | |||
1371 | attrs = (struct attribute **)(events_group + 1); | ||
1372 | events_group->name = "events"; | ||
1373 | events_group->attrs = attrs; | ||
1374 | |||
1375 | for (j = 0; j < i; j++) | ||
1376 | attrs[j] = &type->event_descs[j].attr.attr; | ||
1377 | |||
1378 | type->attr_groups[1] = events_group; | ||
1379 | } | ||
1380 | |||
1381 | type->pmus = pmus; | ||
1382 | return 0; | ||
1383 | fail: | ||
1384 | uncore_type_exit(type); | ||
1385 | return -ENOMEM; | ||
1386 | } | ||
1387 | |||
1388 | static int __init uncore_types_init(struct intel_uncore_type **types) | ||
1389 | { | ||
1390 | int i, ret; | ||
1391 | |||
1392 | for (i = 0; types[i]; i++) { | ||
1393 | ret = uncore_type_init(types[i]); | ||
1394 | if (ret) | ||
1395 | goto fail; | ||
1396 | } | ||
1397 | return 0; | ||
1398 | fail: | ||
1399 | while (--i >= 0) | ||
1400 | uncore_type_exit(types[i]); | ||
1401 | return ret; | ||
1402 | } | ||
1403 | |||
1404 | static struct pci_driver *uncore_pci_driver; | ||
1405 | static bool pcidrv_registered; | ||
1406 | |||
1407 | /* | ||
1408 | * add a pci uncore device | ||
1409 | */ | ||
1410 | static int __devinit uncore_pci_add(struct intel_uncore_type *type, | ||
1411 | struct pci_dev *pdev) | ||
1412 | { | ||
1413 | struct intel_uncore_pmu *pmu; | ||
1414 | struct intel_uncore_box *box; | ||
1415 | int i, phys_id; | ||
1416 | |||
1417 | phys_id = pcibus_to_physid[pdev->bus->number]; | ||
1418 | if (phys_id < 0) | ||
1419 | return -ENODEV; | ||
1420 | |||
1421 | box = uncore_alloc_box(type, 0); | ||
1422 | if (!box) | ||
1423 | return -ENOMEM; | ||
1424 | |||
1425 | /* | ||
1426 | * for performance monitoring unit with multiple boxes, | ||
1427 | * each box has a different function id. | ||
1428 | */ | ||
1429 | for (i = 0; i < type->num_boxes; i++) { | ||
1430 | pmu = &type->pmus[i]; | ||
1431 | if (pmu->func_id == pdev->devfn) | ||
1432 | break; | ||
1433 | if (pmu->func_id < 0) { | ||
1434 | pmu->func_id = pdev->devfn; | ||
1435 | break; | ||
1436 | } | ||
1437 | pmu = NULL; | ||
1438 | } | ||
1439 | |||
1440 | if (!pmu) { | ||
1441 | kfree(box); | ||
1442 | return -EINVAL; | ||
1443 | } | ||
1444 | |||
1445 | box->phys_id = phys_id; | ||
1446 | box->pci_dev = pdev; | ||
1447 | box->pmu = pmu; | ||
1448 | uncore_box_init(box); | ||
1449 | pci_set_drvdata(pdev, box); | ||
1450 | |||
1451 | raw_spin_lock(&uncore_box_lock); | ||
1452 | list_add_tail(&box->list, &pmu->box_list); | ||
1453 | raw_spin_unlock(&uncore_box_lock); | ||
1454 | |||
1455 | return 0; | ||
1456 | } | ||
1457 | |||
1458 | static void uncore_pci_remove(struct pci_dev *pdev) | ||
1459 | { | ||
1460 | struct intel_uncore_box *box = pci_get_drvdata(pdev); | ||
1461 | struct intel_uncore_pmu *pmu = box->pmu; | ||
1462 | int cpu, phys_id = pcibus_to_physid[pdev->bus->number]; | ||
1463 | |||
1464 | if (WARN_ON_ONCE(phys_id != box->phys_id)) | ||
1465 | return; | ||
1466 | |||
1467 | raw_spin_lock(&uncore_box_lock); | ||
1468 | list_del(&box->list); | ||
1469 | raw_spin_unlock(&uncore_box_lock); | ||
1470 | |||
1471 | for_each_possible_cpu(cpu) { | ||
1472 | if (*per_cpu_ptr(pmu->box, cpu) == box) { | ||
1473 | *per_cpu_ptr(pmu->box, cpu) = NULL; | ||
1474 | atomic_dec(&box->refcnt); | ||
1475 | } | ||
1476 | } | ||
1477 | |||
1478 | WARN_ON_ONCE(atomic_read(&box->refcnt) != 1); | ||
1479 | kfree(box); | ||
1480 | } | ||
1481 | |||
1482 | static int __devinit uncore_pci_probe(struct pci_dev *pdev, | ||
1483 | const struct pci_device_id *id) | ||
1484 | { | ||
1485 | struct intel_uncore_type *type; | ||
1486 | |||
1487 | type = (struct intel_uncore_type *)id->driver_data; | ||
1488 | return uncore_pci_add(type, pdev); | ||
1489 | } | ||
1490 | |||
1491 | static int __init uncore_pci_init(void) | ||
1492 | { | ||
1493 | int ret; | ||
1494 | |||
1495 | switch (boot_cpu_data.x86_model) { | ||
1496 | case 45: /* Sandy Bridge-EP */ | ||
1497 | pci_uncores = snbep_pci_uncores; | ||
1498 | uncore_pci_driver = &snbep_uncore_pci_driver; | ||
1499 | snbep_pci2phy_map_init(); | ||
1500 | break; | ||
1501 | default: | ||
1502 | return 0; | ||
1503 | } | ||
1504 | |||
1505 | ret = uncore_types_init(pci_uncores); | ||
1506 | if (ret) | ||
1507 | return ret; | ||
1508 | |||
1509 | uncore_pci_driver->probe = uncore_pci_probe; | ||
1510 | uncore_pci_driver->remove = uncore_pci_remove; | ||
1511 | |||
1512 | ret = pci_register_driver(uncore_pci_driver); | ||
1513 | if (ret == 0) | ||
1514 | pcidrv_registered = true; | ||
1515 | else | ||
1516 | uncore_types_exit(pci_uncores); | ||
1517 | |||
1518 | return ret; | ||
1519 | } | ||
1520 | |||
1521 | static void __init uncore_pci_exit(void) | ||
1522 | { | ||
1523 | if (pcidrv_registered) { | ||
1524 | pcidrv_registered = false; | ||
1525 | pci_unregister_driver(uncore_pci_driver); | ||
1526 | uncore_types_exit(pci_uncores); | ||
1527 | } | ||
1528 | } | ||
1529 | |||
1530 | static void __cpuinit uncore_cpu_dying(int cpu) | ||
1531 | { | ||
1532 | struct intel_uncore_type *type; | ||
1533 | struct intel_uncore_pmu *pmu; | ||
1534 | struct intel_uncore_box *box; | ||
1535 | int i, j; | ||
1536 | |||
1537 | for (i = 0; msr_uncores[i]; i++) { | ||
1538 | type = msr_uncores[i]; | ||
1539 | for (j = 0; j < type->num_boxes; j++) { | ||
1540 | pmu = &type->pmus[j]; | ||
1541 | box = *per_cpu_ptr(pmu->box, cpu); | ||
1542 | *per_cpu_ptr(pmu->box, cpu) = NULL; | ||
1543 | if (box && atomic_dec_and_test(&box->refcnt)) | ||
1544 | kfree(box); | ||
1545 | } | ||
1546 | } | ||
1547 | } | ||
1548 | |||
1549 | static int __cpuinit uncore_cpu_starting(int cpu) | ||
1550 | { | ||
1551 | struct intel_uncore_type *type; | ||
1552 | struct intel_uncore_pmu *pmu; | ||
1553 | struct intel_uncore_box *box, *exist; | ||
1554 | int i, j, k, phys_id; | ||
1555 | |||
1556 | phys_id = topology_physical_package_id(cpu); | ||
1557 | |||
1558 | for (i = 0; msr_uncores[i]; i++) { | ||
1559 | type = msr_uncores[i]; | ||
1560 | for (j = 0; j < type->num_boxes; j++) { | ||
1561 | pmu = &type->pmus[j]; | ||
1562 | box = *per_cpu_ptr(pmu->box, cpu); | ||
1563 | /* called by uncore_cpu_init? */ | ||
1564 | if (box && box->phys_id >= 0) { | ||
1565 | uncore_box_init(box); | ||
1566 | continue; | ||
1567 | } | ||
1568 | |||
1569 | for_each_online_cpu(k) { | ||
1570 | exist = *per_cpu_ptr(pmu->box, k); | ||
1571 | if (exist && exist->phys_id == phys_id) { | ||
1572 | atomic_inc(&exist->refcnt); | ||
1573 | *per_cpu_ptr(pmu->box, cpu) = exist; | ||
1574 | kfree(box); | ||
1575 | box = NULL; | ||
1576 | break; | ||
1577 | } | ||
1578 | } | ||
1579 | |||
1580 | if (box) { | ||
1581 | box->phys_id = phys_id; | ||
1582 | uncore_box_init(box); | ||
1583 | } | ||
1584 | } | ||
1585 | } | ||
1586 | return 0; | ||
1587 | } | ||
1588 | |||
1589 | static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id) | ||
1590 | { | ||
1591 | struct intel_uncore_type *type; | ||
1592 | struct intel_uncore_pmu *pmu; | ||
1593 | struct intel_uncore_box *box; | ||
1594 | int i, j; | ||
1595 | |||
1596 | for (i = 0; msr_uncores[i]; i++) { | ||
1597 | type = msr_uncores[i]; | ||
1598 | for (j = 0; j < type->num_boxes; j++) { | ||
1599 | pmu = &type->pmus[j]; | ||
1600 | if (pmu->func_id < 0) | ||
1601 | pmu->func_id = j; | ||
1602 | |||
1603 | box = uncore_alloc_box(type, cpu); | ||
1604 | if (!box) | ||
1605 | return -ENOMEM; | ||
1606 | |||
1607 | box->pmu = pmu; | ||
1608 | box->phys_id = phys_id; | ||
1609 | *per_cpu_ptr(pmu->box, cpu) = box; | ||
1610 | } | ||
1611 | } | ||
1612 | return 0; | ||
1613 | } | ||
1614 | |||
1615 | static void __cpuinit uncore_change_context(struct intel_uncore_type **uncores, | ||
1616 | int old_cpu, int new_cpu) | ||
1617 | { | ||
1618 | struct intel_uncore_type *type; | ||
1619 | struct intel_uncore_pmu *pmu; | ||
1620 | struct intel_uncore_box *box; | ||
1621 | int i, j; | ||
1622 | |||
1623 | for (i = 0; uncores[i]; i++) { | ||
1624 | type = uncores[i]; | ||
1625 | for (j = 0; j < type->num_boxes; j++) { | ||
1626 | pmu = &type->pmus[j]; | ||
1627 | if (old_cpu < 0) | ||
1628 | box = uncore_pmu_to_box(pmu, new_cpu); | ||
1629 | else | ||
1630 | box = uncore_pmu_to_box(pmu, old_cpu); | ||
1631 | if (!box) | ||
1632 | continue; | ||
1633 | |||
1634 | if (old_cpu < 0) { | ||
1635 | WARN_ON_ONCE(box->cpu != -1); | ||
1636 | box->cpu = new_cpu; | ||
1637 | continue; | ||
1638 | } | ||
1639 | |||
1640 | WARN_ON_ONCE(box->cpu != old_cpu); | ||
1641 | if (new_cpu >= 0) { | ||
1642 | uncore_pmu_cancel_hrtimer(box); | ||
1643 | perf_pmu_migrate_context(&pmu->pmu, | ||
1644 | old_cpu, new_cpu); | ||
1645 | box->cpu = new_cpu; | ||
1646 | } else { | ||
1647 | box->cpu = -1; | ||
1648 | } | ||
1649 | } | ||
1650 | } | ||
1651 | } | ||
1652 | |||
1653 | static void __cpuinit uncore_event_exit_cpu(int cpu) | ||
1654 | { | ||
1655 | int i, phys_id, target; | ||
1656 | |||
1657 | /* if exiting cpu is used for collecting uncore events */ | ||
1658 | if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask)) | ||
1659 | return; | ||
1660 | |||
1661 | /* find a new cpu to collect uncore events */ | ||
1662 | phys_id = topology_physical_package_id(cpu); | ||
1663 | target = -1; | ||
1664 | for_each_online_cpu(i) { | ||
1665 | if (i == cpu) | ||
1666 | continue; | ||
1667 | if (phys_id == topology_physical_package_id(i)) { | ||
1668 | target = i; | ||
1669 | break; | ||
1670 | } | ||
1671 | } | ||
1672 | |||
1673 | /* migrate uncore events to the new cpu */ | ||
1674 | if (target >= 0) | ||
1675 | cpumask_set_cpu(target, &uncore_cpu_mask); | ||
1676 | |||
1677 | uncore_change_context(msr_uncores, cpu, target); | ||
1678 | uncore_change_context(pci_uncores, cpu, target); | ||
1679 | } | ||
1680 | |||
1681 | static void __cpuinit uncore_event_init_cpu(int cpu) | ||
1682 | { | ||
1683 | int i, phys_id; | ||
1684 | |||
1685 | phys_id = topology_physical_package_id(cpu); | ||
1686 | for_each_cpu(i, &uncore_cpu_mask) { | ||
1687 | if (phys_id == topology_physical_package_id(i)) | ||
1688 | return; | ||
1689 | } | ||
1690 | |||
1691 | cpumask_set_cpu(cpu, &uncore_cpu_mask); | ||
1692 | |||
1693 | uncore_change_context(msr_uncores, -1, cpu); | ||
1694 | uncore_change_context(pci_uncores, -1, cpu); | ||
1695 | } | ||
1696 | |||
1697 | static int __cpuinit uncore_cpu_notifier(struct notifier_block *self, | ||
1698 | unsigned long action, void *hcpu) | ||
1699 | { | ||
1700 | unsigned int cpu = (long)hcpu; | ||
1701 | |||
1702 | /* allocate/free data structure for uncore box */ | ||
1703 | switch (action & ~CPU_TASKS_FROZEN) { | ||
1704 | case CPU_UP_PREPARE: | ||
1705 | uncore_cpu_prepare(cpu, -1); | ||
1706 | break; | ||
1707 | case CPU_STARTING: | ||
1708 | uncore_cpu_starting(cpu); | ||
1709 | break; | ||
1710 | case CPU_UP_CANCELED: | ||
1711 | case CPU_DYING: | ||
1712 | uncore_cpu_dying(cpu); | ||
1713 | break; | ||
1714 | default: | ||
1715 | break; | ||
1716 | } | ||
1717 | |||
1718 | /* select the cpu that collects uncore events */ | ||
1719 | switch (action & ~CPU_TASKS_FROZEN) { | ||
1720 | case CPU_DOWN_FAILED: | ||
1721 | case CPU_STARTING: | ||
1722 | uncore_event_init_cpu(cpu); | ||
1723 | break; | ||
1724 | case CPU_DOWN_PREPARE: | ||
1725 | uncore_event_exit_cpu(cpu); | ||
1726 | break; | ||
1727 | default: | ||
1728 | break; | ||
1729 | } | ||
1730 | |||
1731 | return NOTIFY_OK; | ||
1732 | } | ||
1733 | |||
1734 | static struct notifier_block uncore_cpu_nb __cpuinitdata = { | ||
1735 | .notifier_call = uncore_cpu_notifier, | ||
1736 | /* | ||
1737 | * to migrate uncore events, our notifier should be executed | ||
1738 | * before perf core's notifier. | ||
1739 | */ | ||
1740 | .priority = CPU_PRI_PERF + 1, | ||
1741 | }; | ||
1742 | |||
1743 | static void __init uncore_cpu_setup(void *dummy) | ||
1744 | { | ||
1745 | uncore_cpu_starting(smp_processor_id()); | ||
1746 | } | ||
1747 | |||
1748 | static int __init uncore_cpu_init(void) | ||
1749 | { | ||
1750 | int ret, cpu, max_cores; | ||
1751 | |||
1752 | max_cores = boot_cpu_data.x86_max_cores; | ||
1753 | switch (boot_cpu_data.x86_model) { | ||
1754 | case 26: /* Nehalem */ | ||
1755 | case 30: | ||
1756 | case 37: /* Westmere */ | ||
1757 | case 44: | ||
1758 | msr_uncores = nhm_msr_uncores; | ||
1759 | break; | ||
1760 | case 42: /* Sandy Bridge */ | ||
1761 | if (snb_uncore_cbox.num_boxes > max_cores) | ||
1762 | snb_uncore_cbox.num_boxes = max_cores; | ||
1763 | msr_uncores = snb_msr_uncores; | ||
1764 | break; | ||
1765 | case 45: /* Sandy Birdge-EP */ | ||
1766 | if (snbep_uncore_cbox.num_boxes > max_cores) | ||
1767 | snbep_uncore_cbox.num_boxes = max_cores; | ||
1768 | msr_uncores = snbep_msr_uncores; | ||
1769 | break; | ||
1770 | default: | ||
1771 | return 0; | ||
1772 | } | ||
1773 | |||
1774 | ret = uncore_types_init(msr_uncores); | ||
1775 | if (ret) | ||
1776 | return ret; | ||
1777 | |||
1778 | get_online_cpus(); | ||
1779 | |||
1780 | for_each_online_cpu(cpu) { | ||
1781 | int i, phys_id = topology_physical_package_id(cpu); | ||
1782 | |||
1783 | for_each_cpu(i, &uncore_cpu_mask) { | ||
1784 | if (phys_id == topology_physical_package_id(i)) { | ||
1785 | phys_id = -1; | ||
1786 | break; | ||
1787 | } | ||
1788 | } | ||
1789 | if (phys_id < 0) | ||
1790 | continue; | ||
1791 | |||
1792 | uncore_cpu_prepare(cpu, phys_id); | ||
1793 | uncore_event_init_cpu(cpu); | ||
1794 | } | ||
1795 | on_each_cpu(uncore_cpu_setup, NULL, 1); | ||
1796 | |||
1797 | register_cpu_notifier(&uncore_cpu_nb); | ||
1798 | |||
1799 | put_online_cpus(); | ||
1800 | |||
1801 | return 0; | ||
1802 | } | ||
1803 | |||
1804 | static int __init uncore_pmus_register(void) | ||
1805 | { | ||
1806 | struct intel_uncore_pmu *pmu; | ||
1807 | struct intel_uncore_type *type; | ||
1808 | int i, j; | ||
1809 | |||
1810 | for (i = 0; msr_uncores[i]; i++) { | ||
1811 | type = msr_uncores[i]; | ||
1812 | for (j = 0; j < type->num_boxes; j++) { | ||
1813 | pmu = &type->pmus[j]; | ||
1814 | uncore_pmu_register(pmu); | ||
1815 | } | ||
1816 | } | ||
1817 | |||
1818 | for (i = 0; pci_uncores[i]; i++) { | ||
1819 | type = pci_uncores[i]; | ||
1820 | for (j = 0; j < type->num_boxes; j++) { | ||
1821 | pmu = &type->pmus[j]; | ||
1822 | uncore_pmu_register(pmu); | ||
1823 | } | ||
1824 | } | ||
1825 | |||
1826 | return 0; | ||
1827 | } | ||
1828 | |||
1829 | static int __init intel_uncore_init(void) | ||
1830 | { | ||
1831 | int ret; | ||
1832 | |||
1833 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | ||
1834 | return -ENODEV; | ||
1835 | |||
1836 | ret = uncore_pci_init(); | ||
1837 | if (ret) | ||
1838 | goto fail; | ||
1839 | ret = uncore_cpu_init(); | ||
1840 | if (ret) { | ||
1841 | uncore_pci_exit(); | ||
1842 | goto fail; | ||
1843 | } | ||
1844 | |||
1845 | uncore_pmus_register(); | ||
1846 | return 0; | ||
1847 | fail: | ||
1848 | return ret; | ||
1849 | } | ||
1850 | device_initcall(intel_uncore_init); | ||
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h new file mode 100644 index 000000000000..b13e9ea81def --- /dev/null +++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h | |||
@@ -0,0 +1,424 @@ | |||
1 | #include <linux/module.h> | ||
2 | #include <linux/slab.h> | ||
3 | #include <linux/pci.h> | ||
4 | #include <linux/perf_event.h> | ||
5 | #include "perf_event.h" | ||
6 | |||
7 | #define UNCORE_PMU_NAME_LEN 32 | ||
8 | #define UNCORE_BOX_HASH_SIZE 8 | ||
9 | |||
10 | #define UNCORE_PMU_HRTIMER_INTERVAL (60 * NSEC_PER_SEC) | ||
11 | |||
12 | #define UNCORE_FIXED_EVENT 0xff | ||
13 | #define UNCORE_PMC_IDX_MAX_GENERIC 8 | ||
14 | #define UNCORE_PMC_IDX_FIXED UNCORE_PMC_IDX_MAX_GENERIC | ||
15 | #define UNCORE_PMC_IDX_MAX (UNCORE_PMC_IDX_FIXED + 1) | ||
16 | |||
17 | #define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff) | ||
18 | |||
19 | /* SNB event control */ | ||
20 | #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff | ||
21 | #define SNB_UNC_CTL_UMASK_MASK 0x0000ff00 | ||
22 | #define SNB_UNC_CTL_EDGE_DET (1 << 18) | ||
23 | #define SNB_UNC_CTL_EN (1 << 22) | ||
24 | #define SNB_UNC_CTL_INVERT (1 << 23) | ||
25 | #define SNB_UNC_CTL_CMASK_MASK 0x1f000000 | ||
26 | #define NHM_UNC_CTL_CMASK_MASK 0xff000000 | ||
27 | #define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0) | ||
28 | |||
29 | #define SNB_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ | ||
30 | SNB_UNC_CTL_UMASK_MASK | \ | ||
31 | SNB_UNC_CTL_EDGE_DET | \ | ||
32 | SNB_UNC_CTL_INVERT | \ | ||
33 | SNB_UNC_CTL_CMASK_MASK) | ||
34 | |||
35 | #define NHM_UNC_RAW_EVENT_MASK (SNB_UNC_CTL_EV_SEL_MASK | \ | ||
36 | SNB_UNC_CTL_UMASK_MASK | \ | ||
37 | SNB_UNC_CTL_EDGE_DET | \ | ||
38 | SNB_UNC_CTL_INVERT | \ | ||
39 | NHM_UNC_CTL_CMASK_MASK) | ||
40 | |||
41 | /* SNB global control register */ | ||
42 | #define SNB_UNC_PERF_GLOBAL_CTL 0x391 | ||
43 | #define SNB_UNC_FIXED_CTR_CTRL 0x394 | ||
44 | #define SNB_UNC_FIXED_CTR 0x395 | ||
45 | |||
46 | /* SNB uncore global control */ | ||
47 | #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1) | ||
48 | #define SNB_UNC_GLOBAL_CTL_EN (1 << 29) | ||
49 | |||
50 | /* SNB Cbo register */ | ||
51 | #define SNB_UNC_CBO_0_PERFEVTSEL0 0x700 | ||
52 | #define SNB_UNC_CBO_0_PER_CTR0 0x706 | ||
53 | #define SNB_UNC_CBO_MSR_OFFSET 0x10 | ||
54 | |||
55 | /* NHM global control register */ | ||
56 | #define NHM_UNC_PERF_GLOBAL_CTL 0x391 | ||
57 | #define NHM_UNC_FIXED_CTR 0x394 | ||
58 | #define NHM_UNC_FIXED_CTR_CTRL 0x395 | ||
59 | |||
60 | /* NHM uncore global control */ | ||
61 | #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1) | ||
62 | #define NHM_UNC_GLOBAL_CTL_EN_FC (1ULL << 32) | ||
63 | |||
64 | /* NHM uncore register */ | ||
65 | #define NHM_UNC_PERFEVTSEL0 0x3c0 | ||
66 | #define NHM_UNC_UNCORE_PMC0 0x3b0 | ||
67 | |||
68 | /* SNB-EP Box level control */ | ||
69 | #define SNBEP_PMON_BOX_CTL_RST_CTRL (1 << 0) | ||
70 | #define SNBEP_PMON_BOX_CTL_RST_CTRS (1 << 1) | ||
71 | #define SNBEP_PMON_BOX_CTL_FRZ (1 << 8) | ||
72 | #define SNBEP_PMON_BOX_CTL_FRZ_EN (1 << 16) | ||
73 | #define SNBEP_PMON_BOX_CTL_INT (SNBEP_PMON_BOX_CTL_RST_CTRL | \ | ||
74 | SNBEP_PMON_BOX_CTL_RST_CTRS | \ | ||
75 | SNBEP_PMON_BOX_CTL_FRZ_EN) | ||
76 | /* SNB-EP event control */ | ||
77 | #define SNBEP_PMON_CTL_EV_SEL_MASK 0x000000ff | ||
78 | #define SNBEP_PMON_CTL_UMASK_MASK 0x0000ff00 | ||
79 | #define SNBEP_PMON_CTL_RST (1 << 17) | ||
80 | #define SNBEP_PMON_CTL_EDGE_DET (1 << 18) | ||
81 | #define SNBEP_PMON_CTL_EV_SEL_EXT (1 << 21) /* only for QPI */ | ||
82 | #define SNBEP_PMON_CTL_EN (1 << 22) | ||
83 | #define SNBEP_PMON_CTL_INVERT (1 << 23) | ||
84 | #define SNBEP_PMON_CTL_TRESH_MASK 0xff000000 | ||
85 | #define SNBEP_PMON_RAW_EVENT_MASK (SNBEP_PMON_CTL_EV_SEL_MASK | \ | ||
86 | SNBEP_PMON_CTL_UMASK_MASK | \ | ||
87 | SNBEP_PMON_CTL_EDGE_DET | \ | ||
88 | SNBEP_PMON_CTL_INVERT | \ | ||
89 | SNBEP_PMON_CTL_TRESH_MASK) | ||
90 | |||
91 | /* SNB-EP Ubox event control */ | ||
92 | #define SNBEP_U_MSR_PMON_CTL_TRESH_MASK 0x1f000000 | ||
93 | #define SNBEP_U_MSR_PMON_RAW_EVENT_MASK \ | ||
94 | (SNBEP_PMON_CTL_EV_SEL_MASK | \ | ||
95 | SNBEP_PMON_CTL_UMASK_MASK | \ | ||
96 | SNBEP_PMON_CTL_EDGE_DET | \ | ||
97 | SNBEP_PMON_CTL_INVERT | \ | ||
98 | SNBEP_U_MSR_PMON_CTL_TRESH_MASK) | ||
99 | |||
100 | #define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19) | ||
101 | #define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \ | ||
102 | SNBEP_CBO_PMON_CTL_TID_EN) | ||
103 | |||
104 | /* SNB-EP PCU event control */ | ||
105 | #define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000 | ||
106 | #define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000 | ||
107 | #define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT (1 << 30) | ||
108 | #define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET (1 << 31) | ||
109 | #define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK \ | ||
110 | (SNBEP_PMON_CTL_EV_SEL_MASK | \ | ||
111 | SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \ | ||
112 | SNBEP_PMON_CTL_EDGE_DET | \ | ||
113 | SNBEP_PMON_CTL_INVERT | \ | ||
114 | SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \ | ||
115 | SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \ | ||
116 | SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET) | ||
117 | |||
118 | /* SNB-EP pci control register */ | ||
119 | #define SNBEP_PCI_PMON_BOX_CTL 0xf4 | ||
120 | #define SNBEP_PCI_PMON_CTL0 0xd8 | ||
121 | /* SNB-EP pci counter register */ | ||
122 | #define SNBEP_PCI_PMON_CTR0 0xa0 | ||
123 | |||
124 | /* SNB-EP home agent register */ | ||
125 | #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0 0x40 | ||
126 | #define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1 0x44 | ||
127 | #define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH 0x48 | ||
128 | /* SNB-EP memory controller register */ | ||
129 | #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL 0xf0 | ||
130 | #define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR 0xd0 | ||
131 | /* SNB-EP QPI register */ | ||
132 | #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0 0x228 | ||
133 | #define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1 0x22c | ||
134 | #define SNBEP_Q_Py_PCI_PMON_PKT_MASK0 0x238 | ||
135 | #define SNBEP_Q_Py_PCI_PMON_PKT_MASK1 0x23c | ||
136 | |||
137 | /* SNB-EP Ubox register */ | ||
138 | #define SNBEP_U_MSR_PMON_CTR0 0xc16 | ||
139 | #define SNBEP_U_MSR_PMON_CTL0 0xc10 | ||
140 | |||
141 | #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL 0xc08 | ||
142 | #define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR 0xc09 | ||
143 | |||
144 | /* SNB-EP Cbo register */ | ||
145 | #define SNBEP_C0_MSR_PMON_CTR0 0xd16 | ||
146 | #define SNBEP_C0_MSR_PMON_CTL0 0xd10 | ||
147 | #define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04 | ||
148 | #define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14 | ||
149 | #define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK 0xfffffc1f | ||
150 | #define SNBEP_CBO_MSR_OFFSET 0x20 | ||
151 | |||
152 | /* SNB-EP PCU register */ | ||
153 | #define SNBEP_PCU_MSR_PMON_CTR0 0xc36 | ||
154 | #define SNBEP_PCU_MSR_PMON_CTL0 0xc30 | ||
155 | #define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24 | ||
156 | #define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34 | ||
157 | #define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff | ||
158 | #define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc | ||
159 | #define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd | ||
160 | |||
161 | struct intel_uncore_ops; | ||
162 | struct intel_uncore_pmu; | ||
163 | struct intel_uncore_box; | ||
164 | struct uncore_event_desc; | ||
165 | |||
166 | struct intel_uncore_type { | ||
167 | const char *name; | ||
168 | int num_counters; | ||
169 | int num_boxes; | ||
170 | int perf_ctr_bits; | ||
171 | int fixed_ctr_bits; | ||
172 | unsigned perf_ctr; | ||
173 | unsigned event_ctl; | ||
174 | unsigned event_mask; | ||
175 | unsigned fixed_ctr; | ||
176 | unsigned fixed_ctl; | ||
177 | unsigned box_ctl; | ||
178 | unsigned msr_offset; | ||
179 | unsigned num_shared_regs:8; | ||
180 | unsigned single_fixed:1; | ||
181 | struct event_constraint unconstrainted; | ||
182 | struct event_constraint *constraints; | ||
183 | struct intel_uncore_pmu *pmus; | ||
184 | struct intel_uncore_ops *ops; | ||
185 | struct uncore_event_desc *event_descs; | ||
186 | const struct attribute_group *attr_groups[3]; | ||
187 | }; | ||
188 | |||
189 | #define format_group attr_groups[0] | ||
190 | |||
191 | struct intel_uncore_ops { | ||
192 | void (*init_box)(struct intel_uncore_box *); | ||
193 | void (*disable_box)(struct intel_uncore_box *); | ||
194 | void (*enable_box)(struct intel_uncore_box *); | ||
195 | void (*disable_event)(struct intel_uncore_box *, struct perf_event *); | ||
196 | void (*enable_event)(struct intel_uncore_box *, struct perf_event *); | ||
197 | u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *); | ||
198 | int (*hw_config)(struct intel_uncore_box *, struct perf_event *); | ||
199 | struct event_constraint *(*get_constraint)(struct intel_uncore_box *, | ||
200 | struct perf_event *); | ||
201 | void (*put_constraint)(struct intel_uncore_box *, struct perf_event *); | ||
202 | }; | ||
203 | |||
204 | struct intel_uncore_pmu { | ||
205 | struct pmu pmu; | ||
206 | char name[UNCORE_PMU_NAME_LEN]; | ||
207 | int pmu_idx; | ||
208 | int func_id; | ||
209 | struct intel_uncore_type *type; | ||
210 | struct intel_uncore_box ** __percpu box; | ||
211 | struct list_head box_list; | ||
212 | }; | ||
213 | |||
214 | struct intel_uncore_extra_reg { | ||
215 | raw_spinlock_t lock; | ||
216 | u64 config1; | ||
217 | atomic_t ref; | ||
218 | }; | ||
219 | |||
220 | struct intel_uncore_box { | ||
221 | int phys_id; | ||
222 | int n_active; /* number of active events */ | ||
223 | int n_events; | ||
224 | int cpu; /* cpu to collect events */ | ||
225 | unsigned long flags; | ||
226 | atomic_t refcnt; | ||
227 | struct perf_event *events[UNCORE_PMC_IDX_MAX]; | ||
228 | struct perf_event *event_list[UNCORE_PMC_IDX_MAX]; | ||
229 | unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; | ||
230 | u64 tags[UNCORE_PMC_IDX_MAX]; | ||
231 | struct pci_dev *pci_dev; | ||
232 | struct intel_uncore_pmu *pmu; | ||
233 | struct hrtimer hrtimer; | ||
234 | struct list_head list; | ||
235 | struct intel_uncore_extra_reg shared_regs[0]; | ||
236 | }; | ||
237 | |||
238 | #define UNCORE_BOX_FLAG_INITIATED 0 | ||
239 | |||
240 | struct uncore_event_desc { | ||
241 | struct kobj_attribute attr; | ||
242 | const char *config; | ||
243 | }; | ||
244 | |||
245 | #define INTEL_UNCORE_EVENT_DESC(_name, _config) \ | ||
246 | { \ | ||
247 | .attr = __ATTR(_name, 0444, uncore_event_show, NULL), \ | ||
248 | .config = _config, \ | ||
249 | } | ||
250 | |||
251 | #define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format) \ | ||
252 | static ssize_t __uncore_##_var##_show(struct kobject *kobj, \ | ||
253 | struct kobj_attribute *attr, \ | ||
254 | char *page) \ | ||
255 | { \ | ||
256 | BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ | ||
257 | return sprintf(page, _format "\n"); \ | ||
258 | } \ | ||
259 | static struct kobj_attribute format_attr_##_var = \ | ||
260 | __ATTR(_name, 0444, __uncore_##_var##_show, NULL) | ||
261 | |||
262 | |||
263 | static ssize_t uncore_event_show(struct kobject *kobj, | ||
264 | struct kobj_attribute *attr, char *buf) | ||
265 | { | ||
266 | struct uncore_event_desc *event = | ||
267 | container_of(attr, struct uncore_event_desc, attr); | ||
268 | return sprintf(buf, "%s", event->config); | ||
269 | } | ||
270 | |||
271 | static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box) | ||
272 | { | ||
273 | return box->pmu->type->box_ctl; | ||
274 | } | ||
275 | |||
276 | static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box) | ||
277 | { | ||
278 | return box->pmu->type->fixed_ctl; | ||
279 | } | ||
280 | |||
281 | static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box) | ||
282 | { | ||
283 | return box->pmu->type->fixed_ctr; | ||
284 | } | ||
285 | |||
286 | static inline | ||
287 | unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx) | ||
288 | { | ||
289 | return idx * 4 + box->pmu->type->event_ctl; | ||
290 | } | ||
291 | |||
292 | static inline | ||
293 | unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx) | ||
294 | { | ||
295 | return idx * 8 + box->pmu->type->perf_ctr; | ||
296 | } | ||
297 | |||
298 | static inline | ||
299 | unsigned uncore_msr_box_ctl(struct intel_uncore_box *box) | ||
300 | { | ||
301 | if (!box->pmu->type->box_ctl) | ||
302 | return 0; | ||
303 | return box->pmu->type->box_ctl + | ||
304 | box->pmu->type->msr_offset * box->pmu->pmu_idx; | ||
305 | } | ||
306 | |||
307 | static inline | ||
308 | unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box) | ||
309 | { | ||
310 | if (!box->pmu->type->fixed_ctl) | ||
311 | return 0; | ||
312 | return box->pmu->type->fixed_ctl + | ||
313 | box->pmu->type->msr_offset * box->pmu->pmu_idx; | ||
314 | } | ||
315 | |||
316 | static inline | ||
317 | unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box) | ||
318 | { | ||
319 | return box->pmu->type->fixed_ctr + | ||
320 | box->pmu->type->msr_offset * box->pmu->pmu_idx; | ||
321 | } | ||
322 | |||
323 | static inline | ||
324 | unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx) | ||
325 | { | ||
326 | return idx + box->pmu->type->event_ctl + | ||
327 | box->pmu->type->msr_offset * box->pmu->pmu_idx; | ||
328 | } | ||
329 | |||
330 | static inline | ||
331 | unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx) | ||
332 | { | ||
333 | return idx + box->pmu->type->perf_ctr + | ||
334 | box->pmu->type->msr_offset * box->pmu->pmu_idx; | ||
335 | } | ||
336 | |||
337 | static inline | ||
338 | unsigned uncore_fixed_ctl(struct intel_uncore_box *box) | ||
339 | { | ||
340 | if (box->pci_dev) | ||
341 | return uncore_pci_fixed_ctl(box); | ||
342 | else | ||
343 | return uncore_msr_fixed_ctl(box); | ||
344 | } | ||
345 | |||
346 | static inline | ||
347 | unsigned uncore_fixed_ctr(struct intel_uncore_box *box) | ||
348 | { | ||
349 | if (box->pci_dev) | ||
350 | return uncore_pci_fixed_ctr(box); | ||
351 | else | ||
352 | return uncore_msr_fixed_ctr(box); | ||
353 | } | ||
354 | |||
355 | static inline | ||
356 | unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx) | ||
357 | { | ||
358 | if (box->pci_dev) | ||
359 | return uncore_pci_event_ctl(box, idx); | ||
360 | else | ||
361 | return uncore_msr_event_ctl(box, idx); | ||
362 | } | ||
363 | |||
364 | static inline | ||
365 | unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx) | ||
366 | { | ||
367 | if (box->pci_dev) | ||
368 | return uncore_pci_perf_ctr(box, idx); | ||
369 | else | ||
370 | return uncore_msr_perf_ctr(box, idx); | ||
371 | } | ||
372 | |||
373 | static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box) | ||
374 | { | ||
375 | return box->pmu->type->perf_ctr_bits; | ||
376 | } | ||
377 | |||
378 | static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box) | ||
379 | { | ||
380 | return box->pmu->type->fixed_ctr_bits; | ||
381 | } | ||
382 | |||
383 | static inline int uncore_num_counters(struct intel_uncore_box *box) | ||
384 | { | ||
385 | return box->pmu->type->num_counters; | ||
386 | } | ||
387 | |||
388 | static inline void uncore_disable_box(struct intel_uncore_box *box) | ||
389 | { | ||
390 | if (box->pmu->type->ops->disable_box) | ||
391 | box->pmu->type->ops->disable_box(box); | ||
392 | } | ||
393 | |||
394 | static inline void uncore_enable_box(struct intel_uncore_box *box) | ||
395 | { | ||
396 | if (box->pmu->type->ops->enable_box) | ||
397 | box->pmu->type->ops->enable_box(box); | ||
398 | } | ||
399 | |||
400 | static inline void uncore_disable_event(struct intel_uncore_box *box, | ||
401 | struct perf_event *event) | ||
402 | { | ||
403 | box->pmu->type->ops->disable_event(box, event); | ||
404 | } | ||
405 | |||
406 | static inline void uncore_enable_event(struct intel_uncore_box *box, | ||
407 | struct perf_event *event) | ||
408 | { | ||
409 | box->pmu->type->ops->enable_event(box, event); | ||
410 | } | ||
411 | |||
412 | static inline u64 uncore_read_counter(struct intel_uncore_box *box, | ||
413 | struct perf_event *event) | ||
414 | { | ||
415 | return box->pmu->type->ops->read_counter(box, event); | ||
416 | } | ||
417 | |||
418 | static inline void uncore_box_init(struct intel_uncore_box *box) | ||
419 | { | ||
420 | if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { | ||
421 | if (box->pmu->type->ops->init_box) | ||
422 | box->pmu->type->ops->init_box(box); | ||
423 | } | ||
424 | } | ||
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c index 47124a73dd73..92c7e39a079f 100644 --- a/arch/x86/kernel/cpu/perf_event_p4.c +++ b/arch/x86/kernel/cpu/perf_event_p4.c | |||
@@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void) | |||
895 | * So at moment let leave metrics turned on forever -- it's | 895 | * So at moment let leave metrics turned on forever -- it's |
896 | * ok for now but need to be revisited! | 896 | * ok for now but need to be revisited! |
897 | * | 897 | * |
898 | * (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0); | 898 | * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0); |
899 | * (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0); | 899 | * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0); |
900 | */ | 900 | */ |
901 | } | 901 | } |
902 | 902 | ||
@@ -909,7 +909,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event) | |||
909 | * state we need to clear P4_CCCR_OVF, otherwise interrupt get | 909 | * state we need to clear P4_CCCR_OVF, otherwise interrupt get |
910 | * asserted again and again | 910 | * asserted again and again |
911 | */ | 911 | */ |
912 | (void)checking_wrmsrl(hwc->config_base, | 912 | (void)wrmsrl_safe(hwc->config_base, |
913 | (u64)(p4_config_unpack_cccr(hwc->config)) & | 913 | (u64)(p4_config_unpack_cccr(hwc->config)) & |
914 | ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); | 914 | ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED); |
915 | } | 915 | } |
@@ -943,8 +943,8 @@ static void p4_pmu_enable_pebs(u64 config) | |||
943 | 943 | ||
944 | bind = &p4_pebs_bind_map[idx]; | 944 | bind = &p4_pebs_bind_map[idx]; |
945 | 945 | ||
946 | (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); | 946 | (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); |
947 | (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); | 947 | (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); |
948 | } | 948 | } |
949 | 949 | ||
950 | static void p4_pmu_enable_event(struct perf_event *event) | 950 | static void p4_pmu_enable_event(struct perf_event *event) |
@@ -978,8 +978,8 @@ static void p4_pmu_enable_event(struct perf_event *event) | |||
978 | */ | 978 | */ |
979 | p4_pmu_enable_pebs(hwc->config); | 979 | p4_pmu_enable_pebs(hwc->config); |
980 | 980 | ||
981 | (void)checking_wrmsrl(escr_addr, escr_conf); | 981 | (void)wrmsrl_safe(escr_addr, escr_conf); |
982 | (void)checking_wrmsrl(hwc->config_base, | 982 | (void)wrmsrl_safe(hwc->config_base, |
983 | (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE); | 983 | (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE); |
984 | } | 984 | } |
985 | 985 | ||
@@ -1325,7 +1325,7 @@ __init int p4_pmu_init(void) | |||
1325 | unsigned int low, high; | 1325 | unsigned int low, high; |
1326 | 1326 | ||
1327 | /* If we get stripped -- indexing fails */ | 1327 | /* If we get stripped -- indexing fails */ |
1328 | BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC); | 1328 | BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC); |
1329 | 1329 | ||
1330 | rdmsr(MSR_IA32_MISC_ENABLE, low, high); | 1330 | rdmsr(MSR_IA32_MISC_ENABLE, low, high); |
1331 | if (!(low & (1 << 7))) { | 1331 | if (!(low & (1 << 7))) { |
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c index 32bcfc7dd230..e4dd0f7a0453 100644 --- a/arch/x86/kernel/cpu/perf_event_p6.c +++ b/arch/x86/kernel/cpu/perf_event_p6.c | |||
@@ -71,7 +71,7 @@ p6_pmu_disable_event(struct perf_event *event) | |||
71 | if (cpuc->enabled) | 71 | if (cpuc->enabled) |
72 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | 72 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
73 | 73 | ||
74 | (void)checking_wrmsrl(hwc->config_base, val); | 74 | (void)wrmsrl_safe(hwc->config_base, val); |
75 | } | 75 | } |
76 | 76 | ||
77 | static void p6_pmu_enable_event(struct perf_event *event) | 77 | static void p6_pmu_enable_event(struct perf_event *event) |
@@ -84,7 +84,7 @@ static void p6_pmu_enable_event(struct perf_event *event) | |||
84 | if (cpuc->enabled) | 84 | if (cpuc->enabled) |
85 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; | 85 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
86 | 86 | ||
87 | (void)checking_wrmsrl(hwc->config_base, val); | 87 | (void)wrmsrl_safe(hwc->config_base, val); |
88 | } | 88 | } |
89 | 89 | ||
90 | PMU_FORMAT_ATTR(event, "config:0-7" ); | 90 | PMU_FORMAT_ATTR(event, "config:0-7" ); |
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 571246d81edf..ae42418bc50f 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c | |||
@@ -27,8 +27,8 @@ static int die_counter; | |||
27 | 27 | ||
28 | void printk_address(unsigned long address, int reliable) | 28 | void printk_address(unsigned long address, int reliable) |
29 | { | 29 | { |
30 | printk(" [<%p>] %s%pB\n", (void *) address, | 30 | pr_cont(" [<%p>] %s%pB\n", |
31 | reliable ? "" : "? ", (void *) address); | 31 | (void *)address, reliable ? "" : "? ", (void *)address); |
32 | } | 32 | } |
33 | 33 | ||
34 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | 34 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
@@ -271,6 +271,7 @@ int __kprobes __die(const char *str, struct pt_regs *regs, long err) | |||
271 | current->thread.trap_nr, SIGSEGV) == NOTIFY_STOP) | 271 | current->thread.trap_nr, SIGSEGV) == NOTIFY_STOP) |
272 | return 1; | 272 | return 1; |
273 | 273 | ||
274 | print_modules(); | ||
274 | show_regs(regs); | 275 | show_regs(regs); |
275 | #ifdef CONFIG_X86_32 | 276 | #ifdef CONFIG_X86_32 |
276 | if (user_mode_vm(regs)) { | 277 | if (user_mode_vm(regs)) { |
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c index e0b1d783daab..1038a417ea53 100644 --- a/arch/x86/kernel/dumpstack_32.c +++ b/arch/x86/kernel/dumpstack_32.c | |||
@@ -73,11 +73,11 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, | |||
73 | if (kstack_end(stack)) | 73 | if (kstack_end(stack)) |
74 | break; | 74 | break; |
75 | if (i && ((i % STACKSLOTS_PER_LINE) == 0)) | 75 | if (i && ((i % STACKSLOTS_PER_LINE) == 0)) |
76 | printk(KERN_CONT "\n"); | 76 | pr_cont("\n"); |
77 | printk(KERN_CONT " %08lx", *stack++); | 77 | pr_cont(" %08lx", *stack++); |
78 | touch_nmi_watchdog(); | 78 | touch_nmi_watchdog(); |
79 | } | 79 | } |
80 | printk(KERN_CONT "\n"); | 80 | pr_cont("\n"); |
81 | show_trace_log_lvl(task, regs, sp, bp, log_lvl); | 81 | show_trace_log_lvl(task, regs, sp, bp, log_lvl); |
82 | } | 82 | } |
83 | 83 | ||
@@ -86,12 +86,11 @@ void show_regs(struct pt_regs *regs) | |||
86 | { | 86 | { |
87 | int i; | 87 | int i; |
88 | 88 | ||
89 | print_modules(); | ||
90 | __show_regs(regs, !user_mode_vm(regs)); | 89 | __show_regs(regs, !user_mode_vm(regs)); |
91 | 90 | ||
92 | printk(KERN_EMERG "Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n", | 91 | pr_emerg("Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n", |
93 | TASK_COMM_LEN, current->comm, task_pid_nr(current), | 92 | TASK_COMM_LEN, current->comm, task_pid_nr(current), |
94 | current_thread_info(), current, task_thread_info(current)); | 93 | current_thread_info(), current, task_thread_info(current)); |
95 | /* | 94 | /* |
96 | * When in-kernel, we also print out the stack and code at the | 95 | * When in-kernel, we also print out the stack and code at the |
97 | * time of the fault.. | 96 | * time of the fault.. |
@@ -102,10 +101,10 @@ void show_regs(struct pt_regs *regs) | |||
102 | unsigned char c; | 101 | unsigned char c; |
103 | u8 *ip; | 102 | u8 *ip; |
104 | 103 | ||
105 | printk(KERN_EMERG "Stack:\n"); | 104 | pr_emerg("Stack:\n"); |
106 | show_stack_log_lvl(NULL, regs, ®s->sp, 0, KERN_EMERG); | 105 | show_stack_log_lvl(NULL, regs, ®s->sp, 0, KERN_EMERG); |
107 | 106 | ||
108 | printk(KERN_EMERG "Code: "); | 107 | pr_emerg("Code:"); |
109 | 108 | ||
110 | ip = (u8 *)regs->ip - code_prologue; | 109 | ip = (u8 *)regs->ip - code_prologue; |
111 | if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) { | 110 | if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) { |
@@ -116,16 +115,16 @@ void show_regs(struct pt_regs *regs) | |||
116 | for (i = 0; i < code_len; i++, ip++) { | 115 | for (i = 0; i < code_len; i++, ip++) { |
117 | if (ip < (u8 *)PAGE_OFFSET || | 116 | if (ip < (u8 *)PAGE_OFFSET || |
118 | probe_kernel_address(ip, c)) { | 117 | probe_kernel_address(ip, c)) { |
119 | printk(KERN_CONT " Bad EIP value."); | 118 | pr_cont(" Bad EIP value."); |
120 | break; | 119 | break; |
121 | } | 120 | } |
122 | if (ip == (u8 *)regs->ip) | 121 | if (ip == (u8 *)regs->ip) |
123 | printk(KERN_CONT "<%02x> ", c); | 122 | pr_cont(" <%02x>", c); |
124 | else | 123 | else |
125 | printk(KERN_CONT "%02x ", c); | 124 | pr_cont(" %02x", c); |
126 | } | 125 | } |
127 | } | 126 | } |
128 | printk(KERN_CONT "\n"); | 127 | pr_cont("\n"); |
129 | } | 128 | } |
130 | 129 | ||
131 | int is_valid_bugaddr(unsigned long ip) | 130 | int is_valid_bugaddr(unsigned long ip) |
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c index 791b76122aa8..b653675d5288 100644 --- a/arch/x86/kernel/dumpstack_64.c +++ b/arch/x86/kernel/dumpstack_64.c | |||
@@ -228,20 +228,20 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs, | |||
228 | if (stack >= irq_stack && stack <= irq_stack_end) { | 228 | if (stack >= irq_stack && stack <= irq_stack_end) { |
229 | if (stack == irq_stack_end) { | 229 | if (stack == irq_stack_end) { |
230 | stack = (unsigned long *) (irq_stack_end[-1]); | 230 | stack = (unsigned long *) (irq_stack_end[-1]); |
231 | printk(KERN_CONT " <EOI> "); | 231 | pr_cont(" <EOI> "); |
232 | } | 232 | } |
233 | } else { | 233 | } else { |
234 | if (((long) stack & (THREAD_SIZE-1)) == 0) | 234 | if (((long) stack & (THREAD_SIZE-1)) == 0) |
235 | break; | 235 | break; |
236 | } | 236 | } |
237 | if (i && ((i % STACKSLOTS_PER_LINE) == 0)) | 237 | if (i && ((i % STACKSLOTS_PER_LINE) == 0)) |
238 | printk(KERN_CONT "\n"); | 238 | pr_cont("\n"); |
239 | printk(KERN_CONT " %016lx", *stack++); | 239 | pr_cont(" %016lx", *stack++); |
240 | touch_nmi_watchdog(); | 240 | touch_nmi_watchdog(); |
241 | } | 241 | } |
242 | preempt_enable(); | 242 | preempt_enable(); |
243 | 243 | ||
244 | printk(KERN_CONT "\n"); | 244 | pr_cont("\n"); |
245 | show_trace_log_lvl(task, regs, sp, bp, log_lvl); | 245 | show_trace_log_lvl(task, regs, sp, bp, log_lvl); |
246 | } | 246 | } |
247 | 247 | ||
@@ -254,10 +254,9 @@ void show_regs(struct pt_regs *regs) | |||
254 | 254 | ||
255 | sp = regs->sp; | 255 | sp = regs->sp; |
256 | printk("CPU %d ", cpu); | 256 | printk("CPU %d ", cpu); |
257 | print_modules(); | ||
258 | __show_regs(regs, 1); | 257 | __show_regs(regs, 1); |
259 | printk("Process %s (pid: %d, threadinfo %p, task %p)\n", | 258 | printk(KERN_DEFAULT "Process %s (pid: %d, threadinfo %p, task %p)\n", |
260 | cur->comm, cur->pid, task_thread_info(cur), cur); | 259 | cur->comm, cur->pid, task_thread_info(cur), cur); |
261 | 260 | ||
262 | /* | 261 | /* |
263 | * When in-kernel, we also print out the stack and code at the | 262 | * When in-kernel, we also print out the stack and code at the |
@@ -284,16 +283,16 @@ void show_regs(struct pt_regs *regs) | |||
284 | for (i = 0; i < code_len; i++, ip++) { | 283 | for (i = 0; i < code_len; i++, ip++) { |
285 | if (ip < (u8 *)PAGE_OFFSET || | 284 | if (ip < (u8 *)PAGE_OFFSET || |
286 | probe_kernel_address(ip, c)) { | 285 | probe_kernel_address(ip, c)) { |
287 | printk(KERN_CONT " Bad RIP value."); | 286 | pr_cont(" Bad RIP value."); |
288 | break; | 287 | break; |
289 | } | 288 | } |
290 | if (ip == (u8 *)regs->ip) | 289 | if (ip == (u8 *)regs->ip) |
291 | printk(KERN_CONT "<%02x> ", c); | 290 | pr_cont("<%02x> ", c); |
292 | else | 291 | else |
293 | printk(KERN_CONT "%02x ", c); | 292 | pr_cont("%02x ", c); |
294 | } | 293 | } |
295 | } | 294 | } |
296 | printk(KERN_CONT "\n"); | 295 | pr_cont("\n"); |
297 | } | 296 | } |
298 | 297 | ||
299 | int is_valid_bugaddr(unsigned long ip) | 298 | int is_valid_bugaddr(unsigned long ip) |
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S index 7d65133b51be..111f6bbd8b38 100644 --- a/arch/x86/kernel/entry_64.S +++ b/arch/x86/kernel/entry_64.S | |||
@@ -1758,10 +1758,30 @@ end_repeat_nmi: | |||
1758 | */ | 1758 | */ |
1759 | call save_paranoid | 1759 | call save_paranoid |
1760 | DEFAULT_FRAME 0 | 1760 | DEFAULT_FRAME 0 |
1761 | |||
1762 | /* | ||
1763 | * Save off the CR2 register. If we take a page fault in the NMI then | ||
1764 | * it could corrupt the CR2 value. If the NMI preempts a page fault | ||
1765 | * handler before it was able to read the CR2 register, and then the | ||
1766 | * NMI itself takes a page fault, the page fault that was preempted | ||
1767 | * will read the information from the NMI page fault and not the | ||
1768 | * origin fault. Save it off and restore it if it changes. | ||
1769 | * Use the r12 callee-saved register. | ||
1770 | */ | ||
1771 | movq %cr2, %r12 | ||
1772 | |||
1761 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ | 1773 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
1762 | movq %rsp,%rdi | 1774 | movq %rsp,%rdi |
1763 | movq $-1,%rsi | 1775 | movq $-1,%rsi |
1764 | call do_nmi | 1776 | call do_nmi |
1777 | |||
1778 | /* Did the NMI take a page fault? Restore cr2 if it did */ | ||
1779 | movq %cr2, %rcx | ||
1780 | cmpq %rcx, %r12 | ||
1781 | je 1f | ||
1782 | movq %r12, %cr2 | ||
1783 | 1: | ||
1784 | |||
1765 | testl %ebx,%ebx /* swapgs needed? */ | 1785 | testl %ebx,%ebx /* swapgs needed? */ |
1766 | jnz nmi_restore | 1786 | jnz nmi_restore |
1767 | nmi_swapgs: | 1787 | nmi_swapgs: |
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 3dafc6003b7c..1f5f1d5d2a02 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c | |||
@@ -294,9 +294,9 @@ void fixup_irqs(void) | |||
294 | raw_spin_unlock(&desc->lock); | 294 | raw_spin_unlock(&desc->lock); |
295 | 295 | ||
296 | if (break_affinity && set_affinity) | 296 | if (break_affinity && set_affinity) |
297 | printk("Broke affinity for irq %i\n", irq); | 297 | pr_notice("Broke affinity for irq %i\n", irq); |
298 | else if (!set_affinity) | 298 | else if (!set_affinity) |
299 | printk("Cannot set affinity for irq %i\n", irq); | 299 | pr_notice("Cannot set affinity for irq %i\n", irq); |
300 | } | 300 | } |
301 | 301 | ||
302 | /* | 302 | /* |
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c index fbdfc6917180..4873e62db6a1 100644 --- a/arch/x86/kernel/microcode_core.c +++ b/arch/x86/kernel/microcode_core.c | |||
@@ -87,6 +87,7 @@ | |||
87 | #include <asm/microcode.h> | 87 | #include <asm/microcode.h> |
88 | #include <asm/processor.h> | 88 | #include <asm/processor.h> |
89 | #include <asm/cpu_device_id.h> | 89 | #include <asm/cpu_device_id.h> |
90 | #include <asm/perf_event.h> | ||
90 | 91 | ||
91 | MODULE_DESCRIPTION("Microcode Update Driver"); | 92 | MODULE_DESCRIPTION("Microcode Update Driver"); |
92 | MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>"); | 93 | MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>"); |
@@ -277,7 +278,6 @@ static int reload_for_cpu(int cpu) | |||
277 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | 278 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
278 | int err = 0; | 279 | int err = 0; |
279 | 280 | ||
280 | mutex_lock(µcode_mutex); | ||
281 | if (uci->valid) { | 281 | if (uci->valid) { |
282 | enum ucode_state ustate; | 282 | enum ucode_state ustate; |
283 | 283 | ||
@@ -288,7 +288,6 @@ static int reload_for_cpu(int cpu) | |||
288 | if (ustate == UCODE_ERROR) | 288 | if (ustate == UCODE_ERROR) |
289 | err = -EINVAL; | 289 | err = -EINVAL; |
290 | } | 290 | } |
291 | mutex_unlock(µcode_mutex); | ||
292 | 291 | ||
293 | return err; | 292 | return err; |
294 | } | 293 | } |
@@ -298,19 +297,31 @@ static ssize_t reload_store(struct device *dev, | |||
298 | const char *buf, size_t size) | 297 | const char *buf, size_t size) |
299 | { | 298 | { |
300 | unsigned long val; | 299 | unsigned long val; |
301 | int cpu = dev->id; | 300 | int cpu; |
302 | ssize_t ret = 0; | 301 | ssize_t ret = 0, tmp_ret; |
303 | 302 | ||
304 | ret = kstrtoul(buf, 0, &val); | 303 | ret = kstrtoul(buf, 0, &val); |
305 | if (ret) | 304 | if (ret) |
306 | return ret; | 305 | return ret; |
307 | 306 | ||
308 | if (val == 1) { | 307 | if (val != 1) |
309 | get_online_cpus(); | 308 | return size; |
310 | if (cpu_online(cpu)) | 309 | |
311 | ret = reload_for_cpu(cpu); | 310 | get_online_cpus(); |
312 | put_online_cpus(); | 311 | mutex_lock(µcode_mutex); |
312 | for_each_online_cpu(cpu) { | ||
313 | tmp_ret = reload_for_cpu(cpu); | ||
314 | if (tmp_ret != 0) | ||
315 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | ||
316 | |||
317 | /* save retval of the first encountered reload error */ | ||
318 | if (!ret) | ||
319 | ret = tmp_ret; | ||
313 | } | 320 | } |
321 | if (!ret) | ||
322 | perf_check_microcode(); | ||
323 | mutex_unlock(µcode_mutex); | ||
324 | put_online_cpus(); | ||
314 | 325 | ||
315 | if (!ret) | 326 | if (!ret) |
316 | ret = size; | 327 | ret = size; |
@@ -339,7 +350,6 @@ static DEVICE_ATTR(version, 0400, version_show, NULL); | |||
339 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | 350 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); |
340 | 351 | ||
341 | static struct attribute *mc_default_attrs[] = { | 352 | static struct attribute *mc_default_attrs[] = { |
342 | &dev_attr_reload.attr, | ||
343 | &dev_attr_version.attr, | 353 | &dev_attr_version.attr, |
344 | &dev_attr_processor_flags.attr, | 354 | &dev_attr_processor_flags.attr, |
345 | NULL | 355 | NULL |
@@ -504,7 +514,7 @@ static struct notifier_block __refdata mc_cpu_notifier = { | |||
504 | 514 | ||
505 | #ifdef MODULE | 515 | #ifdef MODULE |
506 | /* Autoload on Intel and AMD systems */ | 516 | /* Autoload on Intel and AMD systems */ |
507 | static const struct x86_cpu_id microcode_id[] = { | 517 | static const struct x86_cpu_id __initconst microcode_id[] = { |
508 | #ifdef CONFIG_MICROCODE_INTEL | 518 | #ifdef CONFIG_MICROCODE_INTEL |
509 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, }, | 519 | { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, }, |
510 | #endif | 520 | #endif |
@@ -516,6 +526,16 @@ static const struct x86_cpu_id microcode_id[] = { | |||
516 | MODULE_DEVICE_TABLE(x86cpu, microcode_id); | 526 | MODULE_DEVICE_TABLE(x86cpu, microcode_id); |
517 | #endif | 527 | #endif |
518 | 528 | ||
529 | static struct attribute *cpu_root_microcode_attrs[] = { | ||
530 | &dev_attr_reload.attr, | ||
531 | NULL | ||
532 | }; | ||
533 | |||
534 | static struct attribute_group cpu_root_microcode_group = { | ||
535 | .name = "microcode", | ||
536 | .attrs = cpu_root_microcode_attrs, | ||
537 | }; | ||
538 | |||
519 | static int __init microcode_init(void) | 539 | static int __init microcode_init(void) |
520 | { | 540 | { |
521 | struct cpuinfo_x86 *c = &cpu_data(0); | 541 | struct cpuinfo_x86 *c = &cpu_data(0); |
@@ -540,16 +560,25 @@ static int __init microcode_init(void) | |||
540 | mutex_lock(µcode_mutex); | 560 | mutex_lock(µcode_mutex); |
541 | 561 | ||
542 | error = subsys_interface_register(&mc_cpu_interface); | 562 | error = subsys_interface_register(&mc_cpu_interface); |
543 | 563 | if (!error) | |
564 | perf_check_microcode(); | ||
544 | mutex_unlock(µcode_mutex); | 565 | mutex_unlock(µcode_mutex); |
545 | put_online_cpus(); | 566 | put_online_cpus(); |
546 | 567 | ||
547 | if (error) | 568 | if (error) |
548 | goto out_pdev; | 569 | goto out_pdev; |
549 | 570 | ||
571 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, | ||
572 | &cpu_root_microcode_group); | ||
573 | |||
574 | if (error) { | ||
575 | pr_err("Error creating microcode group!\n"); | ||
576 | goto out_driver; | ||
577 | } | ||
578 | |||
550 | error = microcode_dev_init(); | 579 | error = microcode_dev_init(); |
551 | if (error) | 580 | if (error) |
552 | goto out_driver; | 581 | goto out_ucode_group; |
553 | 582 | ||
554 | register_syscore_ops(&mc_syscore_ops); | 583 | register_syscore_ops(&mc_syscore_ops); |
555 | register_hotcpu_notifier(&mc_cpu_notifier); | 584 | register_hotcpu_notifier(&mc_cpu_notifier); |
@@ -559,7 +588,11 @@ static int __init microcode_init(void) | |||
559 | 588 | ||
560 | return 0; | 589 | return 0; |
561 | 590 | ||
562 | out_driver: | 591 | out_ucode_group: |
592 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | ||
593 | &cpu_root_microcode_group); | ||
594 | |||
595 | out_driver: | ||
563 | get_online_cpus(); | 596 | get_online_cpus(); |
564 | mutex_lock(µcode_mutex); | 597 | mutex_lock(µcode_mutex); |
565 | 598 | ||
@@ -568,7 +601,7 @@ out_driver: | |||
568 | mutex_unlock(µcode_mutex); | 601 | mutex_unlock(µcode_mutex); |
569 | put_online_cpus(); | 602 | put_online_cpus(); |
570 | 603 | ||
571 | out_pdev: | 604 | out_pdev: |
572 | platform_device_unregister(microcode_pdev); | 605 | platform_device_unregister(microcode_pdev); |
573 | return error; | 606 | return error; |
574 | 607 | ||
@@ -584,6 +617,9 @@ static void __exit microcode_exit(void) | |||
584 | unregister_hotcpu_notifier(&mc_cpu_notifier); | 617 | unregister_hotcpu_notifier(&mc_cpu_notifier); |
585 | unregister_syscore_ops(&mc_syscore_ops); | 618 | unregister_syscore_ops(&mc_syscore_ops); |
586 | 619 | ||
620 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | ||
621 | &cpu_root_microcode_group); | ||
622 | |||
587 | get_online_cpus(); | 623 | get_online_cpus(); |
588 | mutex_lock(µcode_mutex); | 624 | mutex_lock(µcode_mutex); |
589 | 625 | ||
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c index f21fd94ac897..202494d2ec6e 100644 --- a/arch/x86/kernel/module.c +++ b/arch/x86/kernel/module.c | |||
@@ -15,6 +15,9 @@ | |||
15 | along with this program; if not, write to the Free Software | 15 | along with this program; if not, write to the Free Software |
16 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 16 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
17 | */ | 17 | */ |
18 | |||
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
20 | |||
18 | #include <linux/moduleloader.h> | 21 | #include <linux/moduleloader.h> |
19 | #include <linux/elf.h> | 22 | #include <linux/elf.h> |
20 | #include <linux/vmalloc.h> | 23 | #include <linux/vmalloc.h> |
@@ -30,9 +33,14 @@ | |||
30 | #include <asm/pgtable.h> | 33 | #include <asm/pgtable.h> |
31 | 34 | ||
32 | #if 0 | 35 | #if 0 |
33 | #define DEBUGP printk | 36 | #define DEBUGP(fmt, ...) \ |
37 | printk(KERN_DEBUG fmt, ##__VA_ARGS__) | ||
34 | #else | 38 | #else |
35 | #define DEBUGP(fmt...) | 39 | #define DEBUGP(fmt, ...) \ |
40 | do { \ | ||
41 | if (0) \ | ||
42 | printk(KERN_DEBUG fmt, ##__VA_ARGS__); \ | ||
43 | } while (0) | ||
36 | #endif | 44 | #endif |
37 | 45 | ||
38 | void *module_alloc(unsigned long size) | 46 | void *module_alloc(unsigned long size) |
@@ -56,8 +64,8 @@ int apply_relocate(Elf32_Shdr *sechdrs, | |||
56 | Elf32_Sym *sym; | 64 | Elf32_Sym *sym; |
57 | uint32_t *location; | 65 | uint32_t *location; |
58 | 66 | ||
59 | DEBUGP("Applying relocate section %u to %u\n", relsec, | 67 | DEBUGP("Applying relocate section %u to %u\n", |
60 | sechdrs[relsec].sh_info); | 68 | relsec, sechdrs[relsec].sh_info); |
61 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | 69 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
62 | /* This is where to make the change */ | 70 | /* This is where to make the change */ |
63 | location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr | 71 | location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr |
@@ -77,7 +85,7 @@ int apply_relocate(Elf32_Shdr *sechdrs, | |||
77 | *location += sym->st_value - (uint32_t)location; | 85 | *location += sym->st_value - (uint32_t)location; |
78 | break; | 86 | break; |
79 | default: | 87 | default: |
80 | printk(KERN_ERR "module %s: Unknown relocation: %u\n", | 88 | pr_err("%s: Unknown relocation: %u\n", |
81 | me->name, ELF32_R_TYPE(rel[i].r_info)); | 89 | me->name, ELF32_R_TYPE(rel[i].r_info)); |
82 | return -ENOEXEC; | 90 | return -ENOEXEC; |
83 | } | 91 | } |
@@ -97,8 +105,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, | |||
97 | void *loc; | 105 | void *loc; |
98 | u64 val; | 106 | u64 val; |
99 | 107 | ||
100 | DEBUGP("Applying relocate section %u to %u\n", relsec, | 108 | DEBUGP("Applying relocate section %u to %u\n", |
101 | sechdrs[relsec].sh_info); | 109 | relsec, sechdrs[relsec].sh_info); |
102 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { | 110 | for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { |
103 | /* This is where to make the change */ | 111 | /* This is where to make the change */ |
104 | loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr | 112 | loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr |
@@ -110,8 +118,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, | |||
110 | + ELF64_R_SYM(rel[i].r_info); | 118 | + ELF64_R_SYM(rel[i].r_info); |
111 | 119 | ||
112 | DEBUGP("type %d st_value %Lx r_addend %Lx loc %Lx\n", | 120 | DEBUGP("type %d st_value %Lx r_addend %Lx loc %Lx\n", |
113 | (int)ELF64_R_TYPE(rel[i].r_info), | 121 | (int)ELF64_R_TYPE(rel[i].r_info), |
114 | sym->st_value, rel[i].r_addend, (u64)loc); | 122 | sym->st_value, rel[i].r_addend, (u64)loc); |
115 | 123 | ||
116 | val = sym->st_value + rel[i].r_addend; | 124 | val = sym->st_value + rel[i].r_addend; |
117 | 125 | ||
@@ -140,7 +148,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, | |||
140 | #endif | 148 | #endif |
141 | break; | 149 | break; |
142 | default: | 150 | default: |
143 | printk(KERN_ERR "module %s: Unknown rela relocation: %llu\n", | 151 | pr_err("%s: Unknown rela relocation: %llu\n", |
144 | me->name, ELF64_R_TYPE(rel[i].r_info)); | 152 | me->name, ELF64_R_TYPE(rel[i].r_info)); |
145 | return -ENOEXEC; | 153 | return -ENOEXEC; |
146 | } | 154 | } |
@@ -148,9 +156,9 @@ int apply_relocate_add(Elf64_Shdr *sechdrs, | |||
148 | return 0; | 156 | return 0; |
149 | 157 | ||
150 | overflow: | 158 | overflow: |
151 | printk(KERN_ERR "overflow in relocation type %d val %Lx\n", | 159 | pr_err("overflow in relocation type %d val %Lx\n", |
152 | (int)ELF64_R_TYPE(rel[i].r_info), val); | 160 | (int)ELF64_R_TYPE(rel[i].r_info), val); |
153 | printk(KERN_ERR "`%s' likely not compiled with -mcmodel=kernel\n", | 161 | pr_err("`%s' likely not compiled with -mcmodel=kernel\n", |
154 | me->name); | 162 | me->name); |
155 | return -ENOEXEC; | 163 | return -ENOEXEC; |
156 | } | 164 | } |
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index a0b2f84457be..f84f5c57de35 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c | |||
@@ -365,8 +365,9 @@ static __kprobes void default_do_nmi(struct pt_regs *regs) | |||
365 | #ifdef CONFIG_X86_32 | 365 | #ifdef CONFIG_X86_32 |
366 | /* | 366 | /* |
367 | * For i386, NMIs use the same stack as the kernel, and we can | 367 | * For i386, NMIs use the same stack as the kernel, and we can |
368 | * add a workaround to the iret problem in C. Simply have 3 states | 368 | * add a workaround to the iret problem in C (preventing nested |
369 | * the NMI can be in. | 369 | * NMIs if an NMI takes a trap). Simply have 3 states the NMI |
370 | * can be in: | ||
370 | * | 371 | * |
371 | * 1) not running | 372 | * 1) not running |
372 | * 2) executing | 373 | * 2) executing |
@@ -383,32 +384,50 @@ static __kprobes void default_do_nmi(struct pt_regs *regs) | |||
383 | * If an NMI hits a breakpoint that executes an iret, another | 384 | * If an NMI hits a breakpoint that executes an iret, another |
384 | * NMI can preempt it. We do not want to allow this new NMI | 385 | * NMI can preempt it. We do not want to allow this new NMI |
385 | * to run, but we want to execute it when the first one finishes. | 386 | * to run, but we want to execute it when the first one finishes. |
386 | * We set the state to "latched", and the first NMI will perform | 387 | * We set the state to "latched", and the exit of the first NMI will |
387 | * an cmpxchg on the state, and if it doesn't successfully | 388 | * perform a dec_return, if the result is zero (NOT_RUNNING), then |
388 | * reset the state to "not running" it will restart the next | 389 | * it will simply exit the NMI handler. If not, the dec_return |
389 | * NMI. | 390 | * would have set the state to NMI_EXECUTING (what we want it to |
391 | * be when we are running). In this case, we simply jump back | ||
392 | * to rerun the NMI handler again, and restart the 'latched' NMI. | ||
393 | * | ||
394 | * No trap (breakpoint or page fault) should be hit before nmi_restart, | ||
395 | * thus there is no race between the first check of state for NOT_RUNNING | ||
396 | * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs | ||
397 | * at this point. | ||
398 | * | ||
399 | * In case the NMI takes a page fault, we need to save off the CR2 | ||
400 | * because the NMI could have preempted another page fault and corrupt | ||
401 | * the CR2 that is about to be read. As nested NMIs must be restarted | ||
402 | * and they can not take breakpoints or page faults, the update of the | ||
403 | * CR2 must be done before converting the nmi state back to NOT_RUNNING. | ||
404 | * Otherwise, there would be a race of another nested NMI coming in | ||
405 | * after setting state to NOT_RUNNING but before updating the nmi_cr2. | ||
390 | */ | 406 | */ |
391 | enum nmi_states { | 407 | enum nmi_states { |
392 | NMI_NOT_RUNNING, | 408 | NMI_NOT_RUNNING = 0, |
393 | NMI_EXECUTING, | 409 | NMI_EXECUTING, |
394 | NMI_LATCHED, | 410 | NMI_LATCHED, |
395 | }; | 411 | }; |
396 | static DEFINE_PER_CPU(enum nmi_states, nmi_state); | 412 | static DEFINE_PER_CPU(enum nmi_states, nmi_state); |
413 | static DEFINE_PER_CPU(unsigned long, nmi_cr2); | ||
397 | 414 | ||
398 | #define nmi_nesting_preprocess(regs) \ | 415 | #define nmi_nesting_preprocess(regs) \ |
399 | do { \ | 416 | do { \ |
400 | if (__get_cpu_var(nmi_state) != NMI_NOT_RUNNING) { \ | 417 | if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { \ |
401 | __get_cpu_var(nmi_state) = NMI_LATCHED; \ | 418 | this_cpu_write(nmi_state, NMI_LATCHED); \ |
402 | return; \ | 419 | return; \ |
403 | } \ | 420 | } \ |
404 | nmi_restart: \ | 421 | this_cpu_write(nmi_state, NMI_EXECUTING); \ |
405 | __get_cpu_var(nmi_state) = NMI_EXECUTING; \ | 422 | this_cpu_write(nmi_cr2, read_cr2()); \ |
406 | } while (0) | 423 | } while (0); \ |
424 | nmi_restart: | ||
407 | 425 | ||
408 | #define nmi_nesting_postprocess() \ | 426 | #define nmi_nesting_postprocess() \ |
409 | do { \ | 427 | do { \ |
410 | if (cmpxchg(&__get_cpu_var(nmi_state), \ | 428 | if (unlikely(this_cpu_read(nmi_cr2) != read_cr2())) \ |
411 | NMI_EXECUTING, NMI_NOT_RUNNING) != NMI_EXECUTING) \ | 429 | write_cr2(this_cpu_read(nmi_cr2)); \ |
430 | if (this_cpu_dec_return(nmi_state)) \ | ||
412 | goto nmi_restart; \ | 431 | goto nmi_restart; \ |
413 | } while (0) | 432 | } while (0) |
414 | #else /* x86_64 */ | 433 | #else /* x86_64 */ |
diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c index 149b8d9c6ad4..6d9582ec0324 100644 --- a/arch/x86/kernel/nmi_selftest.c +++ b/arch/x86/kernel/nmi_selftest.c | |||
@@ -42,7 +42,8 @@ static int __init nmi_unk_cb(unsigned int val, struct pt_regs *regs) | |||
42 | static void __init init_nmi_testsuite(void) | 42 | static void __init init_nmi_testsuite(void) |
43 | { | 43 | { |
44 | /* trap all the unknown NMIs we may generate */ | 44 | /* trap all the unknown NMIs we may generate */ |
45 | register_nmi_handler_initonly(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk"); | 45 | register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk", |
46 | __initdata); | ||
46 | } | 47 | } |
47 | 48 | ||
48 | static void __init cleanup_nmi_testsuite(void) | 49 | static void __init cleanup_nmi_testsuite(void) |
@@ -64,8 +65,8 @@ static void __init test_nmi_ipi(struct cpumask *mask) | |||
64 | { | 65 | { |
65 | unsigned long timeout; | 66 | unsigned long timeout; |
66 | 67 | ||
67 | if (register_nmi_handler_initonly(NMI_LOCAL, test_nmi_ipi_callback, | 68 | if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback, |
68 | NMI_FLAG_FIRST, "nmi_selftest")) { | 69 | NMI_FLAG_FIRST, "nmi_selftest", __initdata)) { |
69 | nmi_fail = FAILURE; | 70 | nmi_fail = FAILURE; |
70 | return; | 71 | return; |
71 | } | 72 | } |
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 9ce885996fd7..17fff18a1031 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c | |||
@@ -352,9 +352,7 @@ struct pv_cpu_ops pv_cpu_ops = { | |||
352 | #endif | 352 | #endif |
353 | .wbinvd = native_wbinvd, | 353 | .wbinvd = native_wbinvd, |
354 | .read_msr = native_read_msr_safe, | 354 | .read_msr = native_read_msr_safe, |
355 | .rdmsr_regs = native_rdmsr_safe_regs, | ||
356 | .write_msr = native_write_msr_safe, | 355 | .write_msr = native_write_msr_safe, |
357 | .wrmsr_regs = native_wrmsr_safe_regs, | ||
358 | .read_tsc = native_read_tsc, | 356 | .read_tsc = native_read_tsc, |
359 | .read_pmc = native_read_pmc, | 357 | .read_pmc = native_read_pmc, |
360 | .read_tscp = native_read_tscp, | 358 | .read_tscp = native_read_tscp, |
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c index b72838bae64a..299d49302e7d 100644 --- a/arch/x86/kernel/pci-calgary_64.c +++ b/arch/x86/kernel/pci-calgary_64.c | |||
@@ -22,6 +22,8 @@ | |||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #define pr_fmt(fmt) "Calgary: " fmt | ||
26 | |||
25 | #include <linux/kernel.h> | 27 | #include <linux/kernel.h> |
26 | #include <linux/init.h> | 28 | #include <linux/init.h> |
27 | #include <linux/types.h> | 29 | #include <linux/types.h> |
@@ -245,7 +247,7 @@ static unsigned long iommu_range_alloc(struct device *dev, | |||
245 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, | 247 | offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0, |
246 | npages, 0, boundary_size, 0); | 248 | npages, 0, boundary_size, 0); |
247 | if (offset == ~0UL) { | 249 | if (offset == ~0UL) { |
248 | printk(KERN_WARNING "Calgary: IOMMU full.\n"); | 250 | pr_warn("IOMMU full\n"); |
249 | spin_unlock_irqrestore(&tbl->it_lock, flags); | 251 | spin_unlock_irqrestore(&tbl->it_lock, flags); |
250 | if (panic_on_overflow) | 252 | if (panic_on_overflow) |
251 | panic("Calgary: fix the allocator.\n"); | 253 | panic("Calgary: fix the allocator.\n"); |
@@ -271,8 +273,8 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl, | |||
271 | entry = iommu_range_alloc(dev, tbl, npages); | 273 | entry = iommu_range_alloc(dev, tbl, npages); |
272 | 274 | ||
273 | if (unlikely(entry == DMA_ERROR_CODE)) { | 275 | if (unlikely(entry == DMA_ERROR_CODE)) { |
274 | printk(KERN_WARNING "Calgary: failed to allocate %u pages in " | 276 | pr_warn("failed to allocate %u pages in iommu %p\n", |
275 | "iommu %p\n", npages, tbl); | 277 | npages, tbl); |
276 | return DMA_ERROR_CODE; | 278 | return DMA_ERROR_CODE; |
277 | } | 279 | } |
278 | 280 | ||
@@ -561,8 +563,7 @@ static void calgary_tce_cache_blast(struct iommu_table *tbl) | |||
561 | i++; | 563 | i++; |
562 | } while ((val & 0xff) != 0xff && i < 100); | 564 | } while ((val & 0xff) != 0xff && i < 100); |
563 | if (i == 100) | 565 | if (i == 100) |
564 | printk(KERN_WARNING "Calgary: PCI bus not quiesced, " | 566 | pr_warn("PCI bus not quiesced, continuing anyway\n"); |
565 | "continuing anyway\n"); | ||
566 | 567 | ||
567 | /* invalidate TCE cache */ | 568 | /* invalidate TCE cache */ |
568 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); | 569 | target = calgary_reg(bbar, tar_offset(tbl->it_busno)); |
@@ -604,8 +605,7 @@ begin: | |||
604 | i++; | 605 | i++; |
605 | } while ((val64 & 0xff) != 0xff && i < 100); | 606 | } while ((val64 & 0xff) != 0xff && i < 100); |
606 | if (i == 100) | 607 | if (i == 100) |
607 | printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, " | 608 | pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n"); |
608 | "continuing anyway\n"); | ||
609 | 609 | ||
610 | /* 3. poll Page Migration DEBUG for SoftStopFault */ | 610 | /* 3. poll Page Migration DEBUG for SoftStopFault */ |
611 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); | 611 | target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG); |
@@ -617,8 +617,7 @@ begin: | |||
617 | if (++count < 100) | 617 | if (++count < 100) |
618 | goto begin; | 618 | goto begin; |
619 | else { | 619 | else { |
620 | printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, " | 620 | pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n"); |
621 | "aborting TCE cache flush sequence!\n"); | ||
622 | return; /* pray for the best */ | 621 | return; /* pray for the best */ |
623 | } | 622 | } |
624 | } | 623 | } |
@@ -840,8 +839,8 @@ static void calgary_dump_error_regs(struct iommu_table *tbl) | |||
840 | plssr = be32_to_cpu(readl(target)); | 839 | plssr = be32_to_cpu(readl(target)); |
841 | 840 | ||
842 | /* If no error, the agent ID in the CSR is not valid */ | 841 | /* If no error, the agent ID in the CSR is not valid */ |
843 | printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, " | 842 | pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n", |
844 | "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr); | 843 | tbl->it_busno, csr, plssr); |
845 | } | 844 | } |
846 | 845 | ||
847 | static void calioc2_dump_error_regs(struct iommu_table *tbl) | 846 | static void calioc2_dump_error_regs(struct iommu_table *tbl) |
@@ -867,22 +866,21 @@ static void calioc2_dump_error_regs(struct iommu_table *tbl) | |||
867 | target = calgary_reg(bbar, phboff | 0x800); | 866 | target = calgary_reg(bbar, phboff | 0x800); |
868 | mck = be32_to_cpu(readl(target)); | 867 | mck = be32_to_cpu(readl(target)); |
869 | 868 | ||
870 | printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n", | 869 | pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno); |
871 | tbl->it_busno); | ||
872 | 870 | ||
873 | printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", | 871 | pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", |
874 | csr, plssr, csmr, mck); | 872 | csr, plssr, csmr, mck); |
875 | 873 | ||
876 | /* dump rest of error regs */ | 874 | /* dump rest of error regs */ |
877 | printk(KERN_EMERG "Calgary: "); | 875 | pr_emerg(""); |
878 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { | 876 | for (i = 0; i < ARRAY_SIZE(errregs); i++) { |
879 | /* err regs are at 0x810 - 0x870 */ | 877 | /* err regs are at 0x810 - 0x870 */ |
880 | erroff = (0x810 + (i * 0x10)); | 878 | erroff = (0x810 + (i * 0x10)); |
881 | target = calgary_reg(bbar, phboff | erroff); | 879 | target = calgary_reg(bbar, phboff | erroff); |
882 | errregs[i] = be32_to_cpu(readl(target)); | 880 | errregs[i] = be32_to_cpu(readl(target)); |
883 | printk("0x%08x@0x%lx ", errregs[i], erroff); | 881 | pr_cont("0x%08x@0x%lx ", errregs[i], erroff); |
884 | } | 882 | } |
885 | printk("\n"); | 883 | pr_cont("\n"); |
886 | 884 | ||
887 | /* root complex status */ | 885 | /* root complex status */ |
888 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); | 886 | target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS); |
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 735279e54e59..ef6a8456f719 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c | |||
@@ -1,3 +1,5 @@ | |||
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
2 | |||
1 | #include <linux/errno.h> | 3 | #include <linux/errno.h> |
2 | #include <linux/kernel.h> | 4 | #include <linux/kernel.h> |
3 | #include <linux/mm.h> | 5 | #include <linux/mm.h> |
@@ -145,16 +147,14 @@ void show_regs_common(void) | |||
145 | /* Board Name is optional */ | 147 | /* Board Name is optional */ |
146 | board = dmi_get_system_info(DMI_BOARD_NAME); | 148 | board = dmi_get_system_info(DMI_BOARD_NAME); |
147 | 149 | ||
148 | printk(KERN_CONT "\n"); | 150 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n", |
149 | printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s", | 151 | current->pid, current->comm, print_tainted(), |
150 | current->pid, current->comm, print_tainted(), | 152 | init_utsname()->release, |
151 | init_utsname()->release, | 153 | (int)strcspn(init_utsname()->version, " "), |
152 | (int)strcspn(init_utsname()->version, " "), | 154 | init_utsname()->version, |
153 | init_utsname()->version); | 155 | vendor, product, |
154 | printk(KERN_CONT " %s %s", vendor, product); | 156 | board ? "/" : "", |
155 | if (board) | 157 | board ? board : ""); |
156 | printk(KERN_CONT "/%s", board); | ||
157 | printk(KERN_CONT "\n"); | ||
158 | } | 158 | } |
159 | 159 | ||
160 | void flush_thread(void) | 160 | void flush_thread(void) |
@@ -645,7 +645,7 @@ static void amd_e400_idle(void) | |||
645 | amd_e400_c1e_detected = true; | 645 | amd_e400_c1e_detected = true; |
646 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) | 646 | if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC)) |
647 | mark_tsc_unstable("TSC halt in AMD C1E"); | 647 | mark_tsc_unstable("TSC halt in AMD C1E"); |
648 | printk(KERN_INFO "System has AMD C1E enabled\n"); | 648 | pr_info("System has AMD C1E enabled\n"); |
649 | } | 649 | } |
650 | } | 650 | } |
651 | 651 | ||
@@ -659,8 +659,7 @@ static void amd_e400_idle(void) | |||
659 | */ | 659 | */ |
660 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, | 660 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, |
661 | &cpu); | 661 | &cpu); |
662 | printk(KERN_INFO "Switch to broadcast mode on CPU%d\n", | 662 | pr_info("Switch to broadcast mode on CPU%d\n", cpu); |
663 | cpu); | ||
664 | } | 663 | } |
665 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); | 664 | clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); |
666 | 665 | ||
@@ -681,8 +680,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |||
681 | { | 680 | { |
682 | #ifdef CONFIG_SMP | 681 | #ifdef CONFIG_SMP |
683 | if (pm_idle == poll_idle && smp_num_siblings > 1) { | 682 | if (pm_idle == poll_idle && smp_num_siblings > 1) { |
684 | printk_once(KERN_WARNING "WARNING: polling idle and HT enabled," | 683 | pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n"); |
685 | " performance may degrade.\n"); | ||
686 | } | 684 | } |
687 | #endif | 685 | #endif |
688 | if (pm_idle) | 686 | if (pm_idle) |
@@ -692,11 +690,11 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |||
692 | /* | 690 | /* |
693 | * One CPU supports mwait => All CPUs supports mwait | 691 | * One CPU supports mwait => All CPUs supports mwait |
694 | */ | 692 | */ |
695 | printk(KERN_INFO "using mwait in idle threads.\n"); | 693 | pr_info("using mwait in idle threads\n"); |
696 | pm_idle = mwait_idle; | 694 | pm_idle = mwait_idle; |
697 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { | 695 | } else if (cpu_has_amd_erratum(amd_erratum_400)) { |
698 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ | 696 | /* E400: APIC timer interrupt does not wake up CPU from C1e */ |
699 | printk(KERN_INFO "using AMD E400 aware idle routine\n"); | 697 | pr_info("using AMD E400 aware idle routine\n"); |
700 | pm_idle = amd_e400_idle; | 698 | pm_idle = amd_e400_idle; |
701 | } else | 699 | } else |
702 | pm_idle = default_idle; | 700 | pm_idle = default_idle; |
@@ -715,7 +713,7 @@ static int __init idle_setup(char *str) | |||
715 | return -EINVAL; | 713 | return -EINVAL; |
716 | 714 | ||
717 | if (!strcmp(str, "poll")) { | 715 | if (!strcmp(str, "poll")) { |
718 | printk("using polling idle threads.\n"); | 716 | pr_info("using polling idle threads\n"); |
719 | pm_idle = poll_idle; | 717 | pm_idle = poll_idle; |
720 | boot_option_idle_override = IDLE_POLL; | 718 | boot_option_idle_override = IDLE_POLL; |
721 | } else if (!strcmp(str, "mwait")) { | 719 | } else if (!strcmp(str, "mwait")) { |
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 61cdf7fdf099..0a980c9d7cb8 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c | |||
@@ -117,10 +117,10 @@ void release_thread(struct task_struct *dead_task) | |||
117 | { | 117 | { |
118 | if (dead_task->mm) { | 118 | if (dead_task->mm) { |
119 | if (dead_task->mm->context.size) { | 119 | if (dead_task->mm->context.size) { |
120 | printk("WARNING: dead process %8s still has LDT? <%p/%d>\n", | 120 | pr_warn("WARNING: dead process %8s still has LDT? <%p/%d>\n", |
121 | dead_task->comm, | 121 | dead_task->comm, |
122 | dead_task->mm->context.ldt, | 122 | dead_task->mm->context.ldt, |
123 | dead_task->mm->context.size); | 123 | dead_task->mm->context.size); |
124 | BUG(); | 124 | BUG(); |
125 | } | 125 | } |
126 | } | 126 | } |
@@ -466,7 +466,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr) | |||
466 | task->thread.gs = addr; | 466 | task->thread.gs = addr; |
467 | if (doit) { | 467 | if (doit) { |
468 | load_gs_index(0); | 468 | load_gs_index(0); |
469 | ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr); | 469 | ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr); |
470 | } | 470 | } |
471 | } | 471 | } |
472 | put_cpu(); | 472 | put_cpu(); |
@@ -494,7 +494,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr) | |||
494 | /* set the selector to 0 to not confuse | 494 | /* set the selector to 0 to not confuse |
495 | __switch_to */ | 495 | __switch_to */ |
496 | loadsegment(fs, 0); | 496 | loadsegment(fs, 0); |
497 | ret = checking_wrmsrl(MSR_FS_BASE, addr); | 497 | ret = wrmsrl_safe(MSR_FS_BASE, addr); |
498 | } | 498 | } |
499 | } | 499 | } |
500 | put_cpu(); | 500 | put_cpu(); |
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 5de92f1abd76..52190a938b4a 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c | |||
@@ -1,3 +1,5 @@ | |||
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
2 | |||
1 | #include <linux/module.h> | 3 | #include <linux/module.h> |
2 | #include <linux/reboot.h> | 4 | #include <linux/reboot.h> |
3 | #include <linux/init.h> | 5 | #include <linux/init.h> |
@@ -20,14 +22,12 @@ | |||
20 | #include <asm/virtext.h> | 22 | #include <asm/virtext.h> |
21 | #include <asm/cpu.h> | 23 | #include <asm/cpu.h> |
22 | #include <asm/nmi.h> | 24 | #include <asm/nmi.h> |
25 | #include <asm/smp.h> | ||
23 | 26 | ||
24 | #ifdef CONFIG_X86_32 | 27 | #include <linux/ctype.h> |
25 | # include <linux/ctype.h> | 28 | #include <linux/mc146818rtc.h> |
26 | # include <linux/mc146818rtc.h> | 29 | #include <asm/realmode.h> |
27 | # include <asm/realmode.h> | 30 | #include <asm/x86_init.h> |
28 | #else | ||
29 | # include <asm/x86_init.h> | ||
30 | #endif | ||
31 | 31 | ||
32 | /* | 32 | /* |
33 | * Power off function, if any | 33 | * Power off function, if any |
@@ -49,7 +49,7 @@ int reboot_force; | |||
49 | */ | 49 | */ |
50 | static int reboot_default = 1; | 50 | static int reboot_default = 1; |
51 | 51 | ||
52 | #if defined(CONFIG_X86_32) && defined(CONFIG_SMP) | 52 | #ifdef CONFIG_SMP |
53 | static int reboot_cpu = -1; | 53 | static int reboot_cpu = -1; |
54 | #endif | 54 | #endif |
55 | 55 | ||
@@ -67,8 +67,8 @@ bool port_cf9_safe = false; | |||
67 | * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci] | 67 | * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci] |
68 | * warm Don't set the cold reboot flag | 68 | * warm Don't set the cold reboot flag |
69 | * cold Set the cold reboot flag | 69 | * cold Set the cold reboot flag |
70 | * bios Reboot by jumping through the BIOS (only for X86_32) | 70 | * bios Reboot by jumping through the BIOS |
71 | * smp Reboot by executing reset on BSP or other CPU (only for X86_32) | 71 | * smp Reboot by executing reset on BSP or other CPU |
72 | * triple Force a triple fault (init) | 72 | * triple Force a triple fault (init) |
73 | * kbd Use the keyboard controller. cold reset (default) | 73 | * kbd Use the keyboard controller. cold reset (default) |
74 | * acpi Use the RESET_REG in the FADT | 74 | * acpi Use the RESET_REG in the FADT |
@@ -95,7 +95,6 @@ static int __init reboot_setup(char *str) | |||
95 | reboot_mode = 0; | 95 | reboot_mode = 0; |
96 | break; | 96 | break; |
97 | 97 | ||
98 | #ifdef CONFIG_X86_32 | ||
99 | #ifdef CONFIG_SMP | 98 | #ifdef CONFIG_SMP |
100 | case 's': | 99 | case 's': |
101 | if (isdigit(*(str+1))) { | 100 | if (isdigit(*(str+1))) { |
@@ -112,7 +111,6 @@ static int __init reboot_setup(char *str) | |||
112 | #endif /* CONFIG_SMP */ | 111 | #endif /* CONFIG_SMP */ |
113 | 112 | ||
114 | case 'b': | 113 | case 'b': |
115 | #endif | ||
116 | case 'a': | 114 | case 'a': |
117 | case 'k': | 115 | case 'k': |
118 | case 't': | 116 | case 't': |
@@ -138,7 +136,6 @@ static int __init reboot_setup(char *str) | |||
138 | __setup("reboot=", reboot_setup); | 136 | __setup("reboot=", reboot_setup); |
139 | 137 | ||
140 | 138 | ||
141 | #ifdef CONFIG_X86_32 | ||
142 | /* | 139 | /* |
143 | * Reboot options and system auto-detection code provided by | 140 | * Reboot options and system auto-detection code provided by |
144 | * Dell Inc. so their systems "just work". :-) | 141 | * Dell Inc. so their systems "just work". :-) |
@@ -152,16 +149,14 @@ static int __init set_bios_reboot(const struct dmi_system_id *d) | |||
152 | { | 149 | { |
153 | if (reboot_type != BOOT_BIOS) { | 150 | if (reboot_type != BOOT_BIOS) { |
154 | reboot_type = BOOT_BIOS; | 151 | reboot_type = BOOT_BIOS; |
155 | printk(KERN_INFO "%s series board detected. Selecting BIOS-method for reboots.\n", d->ident); | 152 | pr_info("%s series board detected. Selecting %s-method for reboots.\n", |
153 | "BIOS", d->ident); | ||
156 | } | 154 | } |
157 | return 0; | 155 | return 0; |
158 | } | 156 | } |
159 | 157 | ||
160 | void machine_real_restart(unsigned int type) | 158 | void __noreturn machine_real_restart(unsigned int type) |
161 | { | 159 | { |
162 | void (*restart_lowmem)(unsigned int) = (void (*)(unsigned int)) | ||
163 | real_mode_header->machine_real_restart_asm; | ||
164 | |||
165 | local_irq_disable(); | 160 | local_irq_disable(); |
166 | 161 | ||
167 | /* | 162 | /* |
@@ -181,25 +176,28 @@ void machine_real_restart(unsigned int type) | |||
181 | /* | 176 | /* |
182 | * Switch back to the initial page table. | 177 | * Switch back to the initial page table. |
183 | */ | 178 | */ |
179 | #ifdef CONFIG_X86_32 | ||
184 | load_cr3(initial_page_table); | 180 | load_cr3(initial_page_table); |
185 | 181 | #else | |
186 | /* | 182 | write_cr3(real_mode_header->trampoline_pgd); |
187 | * Write 0x1234 to absolute memory location 0x472. The BIOS reads | 183 | #endif |
188 | * this on booting to tell it to "Bypass memory test (also warm | ||
189 | * boot)". This seems like a fairly standard thing that gets set by | ||
190 | * REBOOT.COM programs, and the previous reset routine did this | ||
191 | * too. */ | ||
192 | *((unsigned short *)0x472) = reboot_mode; | ||
193 | 184 | ||
194 | /* Jump to the identity-mapped low memory code */ | 185 | /* Jump to the identity-mapped low memory code */ |
195 | restart_lowmem(type); | 186 | #ifdef CONFIG_X86_32 |
187 | asm volatile("jmpl *%0" : : | ||
188 | "rm" (real_mode_header->machine_real_restart_asm), | ||
189 | "a" (type)); | ||
190 | #else | ||
191 | asm volatile("ljmpl *%0" : : | ||
192 | "m" (real_mode_header->machine_real_restart_asm), | ||
193 | "D" (type)); | ||
194 | #endif | ||
195 | unreachable(); | ||
196 | } | 196 | } |
197 | #ifdef CONFIG_APM_MODULE | 197 | #ifdef CONFIG_APM_MODULE |
198 | EXPORT_SYMBOL(machine_real_restart); | 198 | EXPORT_SYMBOL(machine_real_restart); |
199 | #endif | 199 | #endif |
200 | 200 | ||
201 | #endif /* CONFIG_X86_32 */ | ||
202 | |||
203 | /* | 201 | /* |
204 | * Some Apple MacBook and MacBookPro's needs reboot=p to be able to reboot | 202 | * Some Apple MacBook and MacBookPro's needs reboot=p to be able to reboot |
205 | */ | 203 | */ |
@@ -207,8 +205,8 @@ static int __init set_pci_reboot(const struct dmi_system_id *d) | |||
207 | { | 205 | { |
208 | if (reboot_type != BOOT_CF9) { | 206 | if (reboot_type != BOOT_CF9) { |
209 | reboot_type = BOOT_CF9; | 207 | reboot_type = BOOT_CF9; |
210 | printk(KERN_INFO "%s series board detected. " | 208 | pr_info("%s series board detected. Selecting %s-method for reboots.\n", |
211 | "Selecting PCI-method for reboots.\n", d->ident); | 209 | "PCI", d->ident); |
212 | } | 210 | } |
213 | return 0; | 211 | return 0; |
214 | } | 212 | } |
@@ -217,17 +215,16 @@ static int __init set_kbd_reboot(const struct dmi_system_id *d) | |||
217 | { | 215 | { |
218 | if (reboot_type != BOOT_KBD) { | 216 | if (reboot_type != BOOT_KBD) { |
219 | reboot_type = BOOT_KBD; | 217 | reboot_type = BOOT_KBD; |
220 | printk(KERN_INFO "%s series board detected. Selecting KBD-method for reboot.\n", d->ident); | 218 | pr_info("%s series board detected. Selecting %s-method for reboot.\n", |
219 | "KBD", d->ident); | ||
221 | } | 220 | } |
222 | return 0; | 221 | return 0; |
223 | } | 222 | } |
224 | 223 | ||
225 | /* | 224 | /* |
226 | * This is a single dmi_table handling all reboot quirks. Note that | 225 | * This is a single dmi_table handling all reboot quirks. |
227 | * REBOOT_BIOS is only available for 32bit | ||
228 | */ | 226 | */ |
229 | static struct dmi_system_id __initdata reboot_dmi_table[] = { | 227 | static struct dmi_system_id __initdata reboot_dmi_table[] = { |
230 | #ifdef CONFIG_X86_32 | ||
231 | { /* Handle problems with rebooting on Dell E520's */ | 228 | { /* Handle problems with rebooting on Dell E520's */ |
232 | .callback = set_bios_reboot, | 229 | .callback = set_bios_reboot, |
233 | .ident = "Dell E520", | 230 | .ident = "Dell E520", |
@@ -377,7 +374,6 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { | |||
377 | DMI_MATCH(DMI_BOARD_NAME, "P4S800"), | 374 | DMI_MATCH(DMI_BOARD_NAME, "P4S800"), |
378 | }, | 375 | }, |
379 | }, | 376 | }, |
380 | #endif /* CONFIG_X86_32 */ | ||
381 | 377 | ||
382 | { /* Handle reboot issue on Acer Aspire one */ | 378 | { /* Handle reboot issue on Acer Aspire one */ |
383 | .callback = set_kbd_reboot, | 379 | .callback = set_kbd_reboot, |
@@ -584,13 +580,11 @@ static void native_machine_emergency_restart(void) | |||
584 | reboot_type = BOOT_KBD; | 580 | reboot_type = BOOT_KBD; |
585 | break; | 581 | break; |
586 | 582 | ||
587 | #ifdef CONFIG_X86_32 | ||
588 | case BOOT_BIOS: | 583 | case BOOT_BIOS: |
589 | machine_real_restart(MRR_BIOS); | 584 | machine_real_restart(MRR_BIOS); |
590 | 585 | ||
591 | reboot_type = BOOT_KBD; | 586 | reboot_type = BOOT_KBD; |
592 | break; | 587 | break; |
593 | #endif | ||
594 | 588 | ||
595 | case BOOT_ACPI: | 589 | case BOOT_ACPI: |
596 | acpi_reboot(); | 590 | acpi_reboot(); |
@@ -632,12 +626,10 @@ void native_machine_shutdown(void) | |||
632 | /* The boot cpu is always logical cpu 0 */ | 626 | /* The boot cpu is always logical cpu 0 */ |
633 | int reboot_cpu_id = 0; | 627 | int reboot_cpu_id = 0; |
634 | 628 | ||
635 | #ifdef CONFIG_X86_32 | ||
636 | /* See if there has been given a command line override */ | 629 | /* See if there has been given a command line override */ |
637 | if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) && | 630 | if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) && |
638 | cpu_online(reboot_cpu)) | 631 | cpu_online(reboot_cpu)) |
639 | reboot_cpu_id = reboot_cpu; | 632 | reboot_cpu_id = reboot_cpu; |
640 | #endif | ||
641 | 633 | ||
642 | /* Make certain the cpu I'm about to reboot on is online */ | 634 | /* Make certain the cpu I'm about to reboot on is online */ |
643 | if (!cpu_online(reboot_cpu_id)) | 635 | if (!cpu_online(reboot_cpu_id)) |
@@ -678,7 +670,7 @@ static void __machine_emergency_restart(int emergency) | |||
678 | 670 | ||
679 | static void native_machine_restart(char *__unused) | 671 | static void native_machine_restart(char *__unused) |
680 | { | 672 | { |
681 | printk("machine restart\n"); | 673 | pr_notice("machine restart\n"); |
682 | 674 | ||
683 | if (!reboot_force) | 675 | if (!reboot_force) |
684 | machine_shutdown(); | 676 | machine_shutdown(); |
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index 16be6dc14db1..f4b9b80e1b95 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c | |||
@@ -1031,8 +1031,6 @@ void __init setup_arch(char **cmdline_p) | |||
1031 | 1031 | ||
1032 | x86_init.timers.wallclock_init(); | 1032 | x86_init.timers.wallclock_init(); |
1033 | 1033 | ||
1034 | x86_platform.wallclock_init(); | ||
1035 | |||
1036 | mcheck_init(); | 1034 | mcheck_init(); |
1037 | 1035 | ||
1038 | arch_init_ideal_nops(); | 1036 | arch_init_ideal_nops(); |
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c index 21af737053aa..b280908a376e 100644 --- a/arch/x86/kernel/signal.c +++ b/arch/x86/kernel/signal.c | |||
@@ -6,6 +6,9 @@ | |||
6 | * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes | 6 | * 2000-06-20 Pentium III FXSR, SSE support by Gareth Hughes |
7 | * 2000-2002 x86-64 support by Andi Kleen | 7 | * 2000-2002 x86-64 support by Andi Kleen |
8 | */ | 8 | */ |
9 | |||
10 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
11 | |||
9 | #include <linux/sched.h> | 12 | #include <linux/sched.h> |
10 | #include <linux/mm.h> | 13 | #include <linux/mm.h> |
11 | #include <linux/smp.h> | 14 | #include <linux/smp.h> |
@@ -814,7 +817,7 @@ void signal_fault(struct pt_regs *regs, void __user *frame, char *where) | |||
814 | me->comm, me->pid, where, frame, | 817 | me->comm, me->pid, where, frame, |
815 | regs->ip, regs->sp, regs->orig_ax); | 818 | regs->ip, regs->sp, regs->orig_ax); |
816 | print_vma_addr(" in ", regs->ip); | 819 | print_vma_addr(" in ", regs->ip); |
817 | printk(KERN_CONT "\n"); | 820 | pr_cont("\n"); |
818 | } | 821 | } |
819 | 822 | ||
820 | force_sig(SIGSEGV, me); | 823 | force_sig(SIGSEGV, me); |
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 7bd8a0823654..c1a310fb8309 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c | |||
@@ -1,4 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * x86 SMP booting functions | 2 | * x86 SMP booting functions |
3 | * | 3 | * |
4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
@@ -39,6 +39,8 @@ | |||
39 | * Glauber Costa : i386 and x86_64 integration | 39 | * Glauber Costa : i386 and x86_64 integration |
40 | */ | 40 | */ |
41 | 41 | ||
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
43 | |||
42 | #include <linux/init.h> | 44 | #include <linux/init.h> |
43 | #include <linux/smp.h> | 45 | #include <linux/smp.h> |
44 | #include <linux/module.h> | 46 | #include <linux/module.h> |
@@ -184,7 +186,7 @@ static void __cpuinit smp_callin(void) | |||
184 | * boards) | 186 | * boards) |
185 | */ | 187 | */ |
186 | 188 | ||
187 | pr_debug("CALLIN, before setup_local_APIC().\n"); | 189 | pr_debug("CALLIN, before setup_local_APIC()\n"); |
188 | if (apic->smp_callin_clear_local_apic) | 190 | if (apic->smp_callin_clear_local_apic) |
189 | apic->smp_callin_clear_local_apic(); | 191 | apic->smp_callin_clear_local_apic(); |
190 | setup_local_APIC(); | 192 | setup_local_APIC(); |
@@ -255,22 +257,13 @@ notrace static void __cpuinit start_secondary(void *unused) | |||
255 | check_tsc_sync_target(); | 257 | check_tsc_sync_target(); |
256 | 258 | ||
257 | /* | 259 | /* |
258 | * We need to hold call_lock, so there is no inconsistency | ||
259 | * between the time smp_call_function() determines number of | ||
260 | * IPI recipients, and the time when the determination is made | ||
261 | * for which cpus receive the IPI. Holding this | ||
262 | * lock helps us to not include this cpu in a currently in progress | ||
263 | * smp_call_function(). | ||
264 | * | ||
265 | * We need to hold vector_lock so there the set of online cpus | 260 | * We need to hold vector_lock so there the set of online cpus |
266 | * does not change while we are assigning vectors to cpus. Holding | 261 | * does not change while we are assigning vectors to cpus. Holding |
267 | * this lock ensures we don't half assign or remove an irq from a cpu. | 262 | * this lock ensures we don't half assign or remove an irq from a cpu. |
268 | */ | 263 | */ |
269 | ipi_call_lock(); | ||
270 | lock_vector_lock(); | 264 | lock_vector_lock(); |
271 | set_cpu_online(smp_processor_id(), true); | 265 | set_cpu_online(smp_processor_id(), true); |
272 | unlock_vector_lock(); | 266 | unlock_vector_lock(); |
273 | ipi_call_unlock(); | ||
274 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; | 267 | per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; |
275 | x86_platform.nmi_init(); | 268 | x86_platform.nmi_init(); |
276 | 269 | ||
@@ -432,17 +425,16 @@ static void impress_friends(void) | |||
432 | /* | 425 | /* |
433 | * Allow the user to impress friends. | 426 | * Allow the user to impress friends. |
434 | */ | 427 | */ |
435 | pr_debug("Before bogomips.\n"); | 428 | pr_debug("Before bogomips\n"); |
436 | for_each_possible_cpu(cpu) | 429 | for_each_possible_cpu(cpu) |
437 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) | 430 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
438 | bogosum += cpu_data(cpu).loops_per_jiffy; | 431 | bogosum += cpu_data(cpu).loops_per_jiffy; |
439 | printk(KERN_INFO | 432 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
440 | "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | ||
441 | num_online_cpus(), | 433 | num_online_cpus(), |
442 | bogosum/(500000/HZ), | 434 | bogosum/(500000/HZ), |
443 | (bogosum/(5000/HZ))%100); | 435 | (bogosum/(5000/HZ))%100); |
444 | 436 | ||
445 | pr_debug("Before bogocount - setting activated=1.\n"); | 437 | pr_debug("Before bogocount - setting activated=1\n"); |
446 | } | 438 | } |
447 | 439 | ||
448 | void __inquire_remote_apic(int apicid) | 440 | void __inquire_remote_apic(int apicid) |
@@ -452,18 +444,17 @@ void __inquire_remote_apic(int apicid) | |||
452 | int timeout; | 444 | int timeout; |
453 | u32 status; | 445 | u32 status; |
454 | 446 | ||
455 | printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); | 447 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
456 | 448 | ||
457 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | 449 | for (i = 0; i < ARRAY_SIZE(regs); i++) { |
458 | printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); | 450 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
459 | 451 | ||
460 | /* | 452 | /* |
461 | * Wait for idle. | 453 | * Wait for idle. |
462 | */ | 454 | */ |
463 | status = safe_apic_wait_icr_idle(); | 455 | status = safe_apic_wait_icr_idle(); |
464 | if (status) | 456 | if (status) |
465 | printk(KERN_CONT | 457 | pr_cont("a previous APIC delivery may have failed\n"); |
466 | "a previous APIC delivery may have failed\n"); | ||
467 | 458 | ||
468 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); | 459 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
469 | 460 | ||
@@ -476,10 +467,10 @@ void __inquire_remote_apic(int apicid) | |||
476 | switch (status) { | 467 | switch (status) { |
477 | case APIC_ICR_RR_VALID: | 468 | case APIC_ICR_RR_VALID: |
478 | status = apic_read(APIC_RRR); | 469 | status = apic_read(APIC_RRR); |
479 | printk(KERN_CONT "%08x\n", status); | 470 | pr_cont("%08x\n", status); |
480 | break; | 471 | break; |
481 | default: | 472 | default: |
482 | printk(KERN_CONT "failed\n"); | 473 | pr_cont("failed\n"); |
483 | } | 474 | } |
484 | } | 475 | } |
485 | } | 476 | } |
@@ -513,12 +504,12 @@ wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) | |||
513 | apic_write(APIC_ESR, 0); | 504 | apic_write(APIC_ESR, 0); |
514 | accept_status = (apic_read(APIC_ESR) & 0xEF); | 505 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
515 | } | 506 | } |
516 | pr_debug("NMI sent.\n"); | 507 | pr_debug("NMI sent\n"); |
517 | 508 | ||
518 | if (send_status) | 509 | if (send_status) |
519 | printk(KERN_ERR "APIC never delivered???\n"); | 510 | pr_err("APIC never delivered???\n"); |
520 | if (accept_status) | 511 | if (accept_status) |
521 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | 512 | pr_err("APIC delivery error (%lx)\n", accept_status); |
522 | 513 | ||
523 | return (send_status | accept_status); | 514 | return (send_status | accept_status); |
524 | } | 515 | } |
@@ -540,7 +531,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) | |||
540 | apic_read(APIC_ESR); | 531 | apic_read(APIC_ESR); |
541 | } | 532 | } |
542 | 533 | ||
543 | pr_debug("Asserting INIT.\n"); | 534 | pr_debug("Asserting INIT\n"); |
544 | 535 | ||
545 | /* | 536 | /* |
546 | * Turn INIT on target chip | 537 | * Turn INIT on target chip |
@@ -556,7 +547,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) | |||
556 | 547 | ||
557 | mdelay(10); | 548 | mdelay(10); |
558 | 549 | ||
559 | pr_debug("Deasserting INIT.\n"); | 550 | pr_debug("Deasserting INIT\n"); |
560 | 551 | ||
561 | /* Target chip */ | 552 | /* Target chip */ |
562 | /* Send IPI */ | 553 | /* Send IPI */ |
@@ -589,14 +580,14 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) | |||
589 | /* | 580 | /* |
590 | * Run STARTUP IPI loop. | 581 | * Run STARTUP IPI loop. |
591 | */ | 582 | */ |
592 | pr_debug("#startup loops: %d.\n", num_starts); | 583 | pr_debug("#startup loops: %d\n", num_starts); |
593 | 584 | ||
594 | for (j = 1; j <= num_starts; j++) { | 585 | for (j = 1; j <= num_starts; j++) { |
595 | pr_debug("Sending STARTUP #%d.\n", j); | 586 | pr_debug("Sending STARTUP #%d\n", j); |
596 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | 587 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
597 | apic_write(APIC_ESR, 0); | 588 | apic_write(APIC_ESR, 0); |
598 | apic_read(APIC_ESR); | 589 | apic_read(APIC_ESR); |
599 | pr_debug("After apic_write.\n"); | 590 | pr_debug("After apic_write\n"); |
600 | 591 | ||
601 | /* | 592 | /* |
602 | * STARTUP IPI | 593 | * STARTUP IPI |
@@ -613,7 +604,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) | |||
613 | */ | 604 | */ |
614 | udelay(300); | 605 | udelay(300); |
615 | 606 | ||
616 | pr_debug("Startup point 1.\n"); | 607 | pr_debug("Startup point 1\n"); |
617 | 608 | ||
618 | pr_debug("Waiting for send to finish...\n"); | 609 | pr_debug("Waiting for send to finish...\n"); |
619 | send_status = safe_apic_wait_icr_idle(); | 610 | send_status = safe_apic_wait_icr_idle(); |
@@ -628,12 +619,12 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) | |||
628 | if (send_status || accept_status) | 619 | if (send_status || accept_status) |
629 | break; | 620 | break; |
630 | } | 621 | } |
631 | pr_debug("After Startup.\n"); | 622 | pr_debug("After Startup\n"); |
632 | 623 | ||
633 | if (send_status) | 624 | if (send_status) |
634 | printk(KERN_ERR "APIC never delivered???\n"); | 625 | pr_err("APIC never delivered???\n"); |
635 | if (accept_status) | 626 | if (accept_status) |
636 | printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); | 627 | pr_err("APIC delivery error (%lx)\n", accept_status); |
637 | 628 | ||
638 | return (send_status | accept_status); | 629 | return (send_status | accept_status); |
639 | } | 630 | } |
@@ -647,11 +638,11 @@ static void __cpuinit announce_cpu(int cpu, int apicid) | |||
647 | if (system_state == SYSTEM_BOOTING) { | 638 | if (system_state == SYSTEM_BOOTING) { |
648 | if (node != current_node) { | 639 | if (node != current_node) { |
649 | if (current_node > (-1)) | 640 | if (current_node > (-1)) |
650 | pr_cont(" Ok.\n"); | 641 | pr_cont(" OK\n"); |
651 | current_node = node; | 642 | current_node = node; |
652 | pr_info("Booting Node %3d, Processors ", node); | 643 | pr_info("Booting Node %3d, Processors ", node); |
653 | } | 644 | } |
654 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); | 645 | pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); |
655 | return; | 646 | return; |
656 | } else | 647 | } else |
657 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | 648 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", |
@@ -731,9 +722,9 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) | |||
731 | /* | 722 | /* |
732 | * allow APs to start initializing. | 723 | * allow APs to start initializing. |
733 | */ | 724 | */ |
734 | pr_debug("Before Callout %d.\n", cpu); | 725 | pr_debug("Before Callout %d\n", cpu); |
735 | cpumask_set_cpu(cpu, cpu_callout_mask); | 726 | cpumask_set_cpu(cpu, cpu_callout_mask); |
736 | pr_debug("After Callout %d.\n", cpu); | 727 | pr_debug("After Callout %d\n", cpu); |
737 | 728 | ||
738 | /* | 729 | /* |
739 | * Wait 5s total for a response | 730 | * Wait 5s total for a response |
@@ -761,7 +752,7 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) | |||
761 | pr_err("CPU%d: Stuck ??\n", cpu); | 752 | pr_err("CPU%d: Stuck ??\n", cpu); |
762 | else | 753 | else |
763 | /* trampoline code not run */ | 754 | /* trampoline code not run */ |
764 | pr_err("CPU%d: Not responding.\n", cpu); | 755 | pr_err("CPU%d: Not responding\n", cpu); |
765 | if (apic->inquire_remote_apic) | 756 | if (apic->inquire_remote_apic) |
766 | apic->inquire_remote_apic(apicid); | 757 | apic->inquire_remote_apic(apicid); |
767 | } | 758 | } |
@@ -806,7 +797,7 @@ int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) | |||
806 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || | 797 | if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || |
807 | !physid_isset(apicid, phys_cpu_present_map) || | 798 | !physid_isset(apicid, phys_cpu_present_map) || |
808 | !apic->apic_id_valid(apicid)) { | 799 | !apic->apic_id_valid(apicid)) { |
809 | printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); | 800 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
810 | return -EINVAL; | 801 | return -EINVAL; |
811 | } | 802 | } |
812 | 803 | ||
@@ -887,9 +878,8 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
887 | unsigned int cpu; | 878 | unsigned int cpu; |
888 | unsigned nr; | 879 | unsigned nr; |
889 | 880 | ||
890 | printk(KERN_WARNING | 881 | pr_warn("More than 8 CPUs detected - skipping them\n" |
891 | "More than 8 CPUs detected - skipping them.\n" | 882 | "Use CONFIG_X86_BIGSMP\n"); |
892 | "Use CONFIG_X86_BIGSMP.\n"); | ||
893 | 883 | ||
894 | nr = 0; | 884 | nr = 0; |
895 | for_each_present_cpu(cpu) { | 885 | for_each_present_cpu(cpu) { |
@@ -910,8 +900,7 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
910 | #endif | 900 | #endif |
911 | 901 | ||
912 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { | 902 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
913 | printk(KERN_WARNING | 903 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
914 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | ||
915 | hard_smp_processor_id()); | 904 | hard_smp_processor_id()); |
916 | 905 | ||
917 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | 906 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
@@ -923,11 +912,10 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
923 | */ | 912 | */ |
924 | if (!smp_found_config && !acpi_lapic) { | 913 | if (!smp_found_config && !acpi_lapic) { |
925 | preempt_enable(); | 914 | preempt_enable(); |
926 | printk(KERN_NOTICE "SMP motherboard not detected.\n"); | 915 | pr_notice("SMP motherboard not detected\n"); |
927 | disable_smp(); | 916 | disable_smp(); |
928 | if (APIC_init_uniprocessor()) | 917 | if (APIC_init_uniprocessor()) |
929 | printk(KERN_NOTICE "Local APIC not detected." | 918 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); |
930 | " Using dummy APIC emulation.\n"); | ||
931 | return -1; | 919 | return -1; |
932 | } | 920 | } |
933 | 921 | ||
@@ -936,9 +924,8 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
936 | * CPU too, but we do it for the sake of robustness anyway. | 924 | * CPU too, but we do it for the sake of robustness anyway. |
937 | */ | 925 | */ |
938 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { | 926 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
939 | printk(KERN_NOTICE | 927 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
940 | "weird, boot CPU (#%d) not listed by the BIOS.\n", | 928 | boot_cpu_physical_apicid); |
941 | boot_cpu_physical_apicid); | ||
942 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); | 929 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
943 | } | 930 | } |
944 | preempt_enable(); | 931 | preempt_enable(); |
@@ -951,8 +938,7 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
951 | if (!disable_apic) { | 938 | if (!disable_apic) { |
952 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | 939 | pr_err("BIOS bug, local APIC #%d not detected!...\n", |
953 | boot_cpu_physical_apicid); | 940 | boot_cpu_physical_apicid); |
954 | pr_err("... forcing use of dummy APIC emulation." | 941 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
955 | "(tell your hw vendor)\n"); | ||
956 | } | 942 | } |
957 | smpboot_clear_io_apic(); | 943 | smpboot_clear_io_apic(); |
958 | disable_ioapic_support(); | 944 | disable_ioapic_support(); |
@@ -965,7 +951,7 @@ static int __init smp_sanity_check(unsigned max_cpus) | |||
965 | * If SMP should be disabled, then really disable it! | 951 | * If SMP should be disabled, then really disable it! |
966 | */ | 952 | */ |
967 | if (!max_cpus) { | 953 | if (!max_cpus) { |
968 | printk(KERN_INFO "SMP mode deactivated.\n"); | 954 | pr_info("SMP mode deactivated\n"); |
969 | smpboot_clear_io_apic(); | 955 | smpboot_clear_io_apic(); |
970 | 956 | ||
971 | connect_bsp_APIC(); | 957 | connect_bsp_APIC(); |
@@ -1017,7 +1003,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) | |||
1017 | 1003 | ||
1018 | 1004 | ||
1019 | if (smp_sanity_check(max_cpus) < 0) { | 1005 | if (smp_sanity_check(max_cpus) < 0) { |
1020 | printk(KERN_INFO "SMP disabled\n"); | 1006 | pr_info("SMP disabled\n"); |
1021 | disable_smp(); | 1007 | disable_smp(); |
1022 | goto out; | 1008 | goto out; |
1023 | } | 1009 | } |
@@ -1055,7 +1041,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus) | |||
1055 | * Set up local APIC timer on boot CPU. | 1041 | * Set up local APIC timer on boot CPU. |
1056 | */ | 1042 | */ |
1057 | 1043 | ||
1058 | printk(KERN_INFO "CPU%d: ", 0); | 1044 | pr_info("CPU%d: ", 0); |
1059 | print_cpu_info(&cpu_data(0)); | 1045 | print_cpu_info(&cpu_data(0)); |
1060 | x86_init.timers.setup_percpu_clockev(); | 1046 | x86_init.timers.setup_percpu_clockev(); |
1061 | 1047 | ||
@@ -1105,7 +1091,7 @@ void __init native_smp_prepare_boot_cpu(void) | |||
1105 | 1091 | ||
1106 | void __init native_smp_cpus_done(unsigned int max_cpus) | 1092 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1107 | { | 1093 | { |
1108 | pr_debug("Boot done.\n"); | 1094 | pr_debug("Boot done\n"); |
1109 | 1095 | ||
1110 | nmi_selftest(); | 1096 | nmi_selftest(); |
1111 | impress_friends(); | 1097 | impress_friends(); |
@@ -1166,8 +1152,7 @@ __init void prefill_possible_map(void) | |||
1166 | 1152 | ||
1167 | /* nr_cpu_ids could be reduced via nr_cpus= */ | 1153 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1168 | if (possible > nr_cpu_ids) { | 1154 | if (possible > nr_cpu_ids) { |
1169 | printk(KERN_WARNING | 1155 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
1170 | "%d Processors exceeds NR_CPUS limit of %d\n", | ||
1171 | possible, nr_cpu_ids); | 1156 | possible, nr_cpu_ids); |
1172 | possible = nr_cpu_ids; | 1157 | possible = nr_cpu_ids; |
1173 | } | 1158 | } |
@@ -1176,13 +1161,12 @@ __init void prefill_possible_map(void) | |||
1176 | if (!setup_max_cpus) | 1161 | if (!setup_max_cpus) |
1177 | #endif | 1162 | #endif |
1178 | if (possible > i) { | 1163 | if (possible > i) { |
1179 | printk(KERN_WARNING | 1164 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
1180 | "%d Processors exceeds max_cpus limit of %u\n", | ||
1181 | possible, setup_max_cpus); | 1165 | possible, setup_max_cpus); |
1182 | possible = i; | 1166 | possible = i; |
1183 | } | 1167 | } |
1184 | 1168 | ||
1185 | printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", | 1169 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
1186 | possible, max_t(int, possible - num_processors, 0)); | 1170 | possible, max_t(int, possible - num_processors, 0)); |
1187 | 1171 | ||
1188 | for (i = 0; i < possible; i++) | 1172 | for (i = 0; i < possible; i++) |
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c index 05b31d92f69c..b481341c9369 100644 --- a/arch/x86/kernel/traps.c +++ b/arch/x86/kernel/traps.c | |||
@@ -9,6 +9,9 @@ | |||
9 | /* | 9 | /* |
10 | * Handle hardware traps and faults. | 10 | * Handle hardware traps and faults. |
11 | */ | 11 | */ |
12 | |||
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
14 | |||
12 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
13 | #include <linux/kallsyms.h> | 16 | #include <linux/kallsyms.h> |
14 | #include <linux/spinlock.h> | 17 | #include <linux/spinlock.h> |
@@ -143,12 +146,11 @@ trap_signal: | |||
143 | #ifdef CONFIG_X86_64 | 146 | #ifdef CONFIG_X86_64 |
144 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | 147 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && |
145 | printk_ratelimit()) { | 148 | printk_ratelimit()) { |
146 | printk(KERN_INFO | 149 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
147 | "%s[%d] trap %s ip:%lx sp:%lx error:%lx", | 150 | tsk->comm, tsk->pid, str, |
148 | tsk->comm, tsk->pid, str, | 151 | regs->ip, regs->sp, error_code); |
149 | regs->ip, regs->sp, error_code); | ||
150 | print_vma_addr(" in ", regs->ip); | 152 | print_vma_addr(" in ", regs->ip); |
151 | printk("\n"); | 153 | pr_cont("\n"); |
152 | } | 154 | } |
153 | #endif | 155 | #endif |
154 | 156 | ||
@@ -269,12 +271,11 @@ do_general_protection(struct pt_regs *regs, long error_code) | |||
269 | 271 | ||
270 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && | 272 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
271 | printk_ratelimit()) { | 273 | printk_ratelimit()) { |
272 | printk(KERN_INFO | 274 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
273 | "%s[%d] general protection ip:%lx sp:%lx error:%lx", | ||
274 | tsk->comm, task_pid_nr(tsk), | 275 | tsk->comm, task_pid_nr(tsk), |
275 | regs->ip, regs->sp, error_code); | 276 | regs->ip, regs->sp, error_code); |
276 | print_vma_addr(" in ", regs->ip); | 277 | print_vma_addr(" in ", regs->ip); |
277 | printk("\n"); | 278 | pr_cont("\n"); |
278 | } | 279 | } |
279 | 280 | ||
280 | force_sig(SIGSEGV, tsk); | 281 | force_sig(SIGSEGV, tsk); |
@@ -570,7 +571,7 @@ do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |||
570 | conditional_sti(regs); | 571 | conditional_sti(regs); |
571 | #if 0 | 572 | #if 0 |
572 | /* No need to warn about this any longer. */ | 573 | /* No need to warn about this any longer. */ |
573 | printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); | 574 | pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
574 | #endif | 575 | #endif |
575 | } | 576 | } |
576 | 577 | ||
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index fc0a147e3727..cfa5d4f7ca56 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c | |||
@@ -1,3 +1,5 @@ | |||
1 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
2 | |||
1 | #include <linux/kernel.h> | 3 | #include <linux/kernel.h> |
2 | #include <linux/sched.h> | 4 | #include <linux/sched.h> |
3 | #include <linux/init.h> | 5 | #include <linux/init.h> |
@@ -84,8 +86,7 @@ EXPORT_SYMBOL_GPL(check_tsc_unstable); | |||
84 | #ifdef CONFIG_X86_TSC | 86 | #ifdef CONFIG_X86_TSC |
85 | int __init notsc_setup(char *str) | 87 | int __init notsc_setup(char *str) |
86 | { | 88 | { |
87 | printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " | 89 | pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n"); |
88 | "cannot disable TSC completely.\n"); | ||
89 | tsc_disabled = 1; | 90 | tsc_disabled = 1; |
90 | return 1; | 91 | return 1; |
91 | } | 92 | } |
@@ -373,7 +374,7 @@ static unsigned long quick_pit_calibrate(void) | |||
373 | goto success; | 374 | goto success; |
374 | } | 375 | } |
375 | } | 376 | } |
376 | printk("Fast TSC calibration failed\n"); | 377 | pr_err("Fast TSC calibration failed\n"); |
377 | return 0; | 378 | return 0; |
378 | 379 | ||
379 | success: | 380 | success: |
@@ -392,7 +393,7 @@ success: | |||
392 | */ | 393 | */ |
393 | delta *= PIT_TICK_RATE; | 394 | delta *= PIT_TICK_RATE; |
394 | do_div(delta, i*256*1000); | 395 | do_div(delta, i*256*1000); |
395 | printk("Fast TSC calibration using PIT\n"); | 396 | pr_info("Fast TSC calibration using PIT\n"); |
396 | return delta; | 397 | return delta; |
397 | } | 398 | } |
398 | 399 | ||
@@ -487,9 +488,8 @@ unsigned long native_calibrate_tsc(void) | |||
487 | * use the reference value, as it is more precise. | 488 | * use the reference value, as it is more precise. |
488 | */ | 489 | */ |
489 | if (delta >= 90 && delta <= 110) { | 490 | if (delta >= 90 && delta <= 110) { |
490 | printk(KERN_INFO | 491 | pr_info("PIT calibration matches %s. %d loops\n", |
491 | "TSC: PIT calibration matches %s. %d loops\n", | 492 | hpet ? "HPET" : "PMTIMER", i + 1); |
492 | hpet ? "HPET" : "PMTIMER", i + 1); | ||
493 | return tsc_ref_min; | 493 | return tsc_ref_min; |
494 | } | 494 | } |
495 | 495 | ||
@@ -511,38 +511,36 @@ unsigned long native_calibrate_tsc(void) | |||
511 | */ | 511 | */ |
512 | if (tsc_pit_min == ULONG_MAX) { | 512 | if (tsc_pit_min == ULONG_MAX) { |
513 | /* PIT gave no useful value */ | 513 | /* PIT gave no useful value */ |
514 | printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); | 514 | pr_warn("Unable to calibrate against PIT\n"); |
515 | 515 | ||
516 | /* We don't have an alternative source, disable TSC */ | 516 | /* We don't have an alternative source, disable TSC */ |
517 | if (!hpet && !ref1 && !ref2) { | 517 | if (!hpet && !ref1 && !ref2) { |
518 | printk("TSC: No reference (HPET/PMTIMER) available\n"); | 518 | pr_notice("No reference (HPET/PMTIMER) available\n"); |
519 | return 0; | 519 | return 0; |
520 | } | 520 | } |
521 | 521 | ||
522 | /* The alternative source failed as well, disable TSC */ | 522 | /* The alternative source failed as well, disable TSC */ |
523 | if (tsc_ref_min == ULONG_MAX) { | 523 | if (tsc_ref_min == ULONG_MAX) { |
524 | printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " | 524 | pr_warn("HPET/PMTIMER calibration failed\n"); |
525 | "failed.\n"); | ||
526 | return 0; | 525 | return 0; |
527 | } | 526 | } |
528 | 527 | ||
529 | /* Use the alternative source */ | 528 | /* Use the alternative source */ |
530 | printk(KERN_INFO "TSC: using %s reference calibration\n", | 529 | pr_info("using %s reference calibration\n", |
531 | hpet ? "HPET" : "PMTIMER"); | 530 | hpet ? "HPET" : "PMTIMER"); |
532 | 531 | ||
533 | return tsc_ref_min; | 532 | return tsc_ref_min; |
534 | } | 533 | } |
535 | 534 | ||
536 | /* We don't have an alternative source, use the PIT calibration value */ | 535 | /* We don't have an alternative source, use the PIT calibration value */ |
537 | if (!hpet && !ref1 && !ref2) { | 536 | if (!hpet && !ref1 && !ref2) { |
538 | printk(KERN_INFO "TSC: Using PIT calibration value\n"); | 537 | pr_info("Using PIT calibration value\n"); |
539 | return tsc_pit_min; | 538 | return tsc_pit_min; |
540 | } | 539 | } |
541 | 540 | ||
542 | /* The alternative source failed, use the PIT calibration value */ | 541 | /* The alternative source failed, use the PIT calibration value */ |
543 | if (tsc_ref_min == ULONG_MAX) { | 542 | if (tsc_ref_min == ULONG_MAX) { |
544 | printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " | 543 | pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n"); |
545 | "Using PIT calibration\n"); | ||
546 | return tsc_pit_min; | 544 | return tsc_pit_min; |
547 | } | 545 | } |
548 | 546 | ||
@@ -551,9 +549,9 @@ unsigned long native_calibrate_tsc(void) | |||
551 | * the PIT value as we know that there are PMTIMERs around | 549 | * the PIT value as we know that there are PMTIMERs around |
552 | * running at double speed. At least we let the user know: | 550 | * running at double speed. At least we let the user know: |
553 | */ | 551 | */ |
554 | printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", | 552 | pr_warn("PIT calibration deviates from %s: %lu %lu\n", |
555 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); | 553 | hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); |
556 | printk(KERN_INFO "TSC: Using PIT calibration value\n"); | 554 | pr_info("Using PIT calibration value\n"); |
557 | return tsc_pit_min; | 555 | return tsc_pit_min; |
558 | } | 556 | } |
559 | 557 | ||
@@ -785,7 +783,7 @@ void mark_tsc_unstable(char *reason) | |||
785 | tsc_unstable = 1; | 783 | tsc_unstable = 1; |
786 | sched_clock_stable = 0; | 784 | sched_clock_stable = 0; |
787 | disable_sched_clock_irqtime(); | 785 | disable_sched_clock_irqtime(); |
788 | printk(KERN_INFO "Marking TSC unstable due to %s\n", reason); | 786 | pr_info("Marking TSC unstable due to %s\n", reason); |
789 | /* Change only the rating, when not registered */ | 787 | /* Change only the rating, when not registered */ |
790 | if (clocksource_tsc.mult) | 788 | if (clocksource_tsc.mult) |
791 | clocksource_mark_unstable(&clocksource_tsc); | 789 | clocksource_mark_unstable(&clocksource_tsc); |
@@ -912,9 +910,9 @@ static void tsc_refine_calibration_work(struct work_struct *work) | |||
912 | goto out; | 910 | goto out; |
913 | 911 | ||
914 | tsc_khz = freq; | 912 | tsc_khz = freq; |
915 | printk(KERN_INFO "Refined TSC clocksource calibration: " | 913 | pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", |
916 | "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000, | 914 | (unsigned long)tsc_khz / 1000, |
917 | (unsigned long)tsc_khz % 1000); | 915 | (unsigned long)tsc_khz % 1000); |
918 | 916 | ||
919 | out: | 917 | out: |
920 | clocksource_register_khz(&clocksource_tsc, tsc_khz); | 918 | clocksource_register_khz(&clocksource_tsc, tsc_khz); |
@@ -970,9 +968,9 @@ void __init tsc_init(void) | |||
970 | return; | 968 | return; |
971 | } | 969 | } |
972 | 970 | ||
973 | printk("Detected %lu.%03lu MHz processor.\n", | 971 | pr_info("Detected %lu.%03lu MHz processor\n", |
974 | (unsigned long)cpu_khz / 1000, | 972 | (unsigned long)cpu_khz / 1000, |
975 | (unsigned long)cpu_khz % 1000); | 973 | (unsigned long)cpu_khz % 1000); |
976 | 974 | ||
977 | /* | 975 | /* |
978 | * Secondary CPUs do not run through tsc_init(), so set up | 976 | * Secondary CPUs do not run through tsc_init(), so set up |
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c index dc4e910a7d96..36fd42091fa7 100644 --- a/arch/x86/kernel/uprobes.c +++ b/arch/x86/kernel/uprobes.c | |||
@@ -409,9 +409,10 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm, | |||
409 | * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. | 409 | * arch_uprobe_analyze_insn - instruction analysis including validity and fixups. |
410 | * @mm: the probed address space. | 410 | * @mm: the probed address space. |
411 | * @arch_uprobe: the probepoint information. | 411 | * @arch_uprobe: the probepoint information. |
412 | * @addr: virtual address at which to install the probepoint | ||
412 | * Return 0 on success or a -ve number on error. | 413 | * Return 0 on success or a -ve number on error. |
413 | */ | 414 | */ |
414 | int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm) | 415 | int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr) |
415 | { | 416 | { |
416 | int ret; | 417 | int ret; |
417 | struct insn insn; | 418 | struct insn insn; |
diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c index 255f58ae71e8..54abcc0baf23 100644 --- a/arch/x86/kernel/vm86_32.c +++ b/arch/x86/kernel/vm86_32.c | |||
@@ -28,6 +28,8 @@ | |||
28 | * | 28 | * |
29 | */ | 29 | */ |
30 | 30 | ||
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
32 | |||
31 | #include <linux/capability.h> | 33 | #include <linux/capability.h> |
32 | #include <linux/errno.h> | 34 | #include <linux/errno.h> |
33 | #include <linux/interrupt.h> | 35 | #include <linux/interrupt.h> |
@@ -137,14 +139,14 @@ struct pt_regs *save_v86_state(struct kernel_vm86_regs *regs) | |||
137 | local_irq_enable(); | 139 | local_irq_enable(); |
138 | 140 | ||
139 | if (!current->thread.vm86_info) { | 141 | if (!current->thread.vm86_info) { |
140 | printk("no vm86_info: BAD\n"); | 142 | pr_alert("no vm86_info: BAD\n"); |
141 | do_exit(SIGSEGV); | 143 | do_exit(SIGSEGV); |
142 | } | 144 | } |
143 | set_flags(regs->pt.flags, VEFLAGS, X86_EFLAGS_VIF | current->thread.v86mask); | 145 | set_flags(regs->pt.flags, VEFLAGS, X86_EFLAGS_VIF | current->thread.v86mask); |
144 | tmp = copy_vm86_regs_to_user(¤t->thread.vm86_info->regs, regs); | 146 | tmp = copy_vm86_regs_to_user(¤t->thread.vm86_info->regs, regs); |
145 | tmp += put_user(current->thread.screen_bitmap, ¤t->thread.vm86_info->screen_bitmap); | 147 | tmp += put_user(current->thread.screen_bitmap, ¤t->thread.vm86_info->screen_bitmap); |
146 | if (tmp) { | 148 | if (tmp) { |
147 | printk("vm86: could not access userspace vm86_info\n"); | 149 | pr_alert("could not access userspace vm86_info\n"); |
148 | do_exit(SIGSEGV); | 150 | do_exit(SIGSEGV); |
149 | } | 151 | } |
150 | 152 | ||
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c index 8eeb55a551b4..992f890283e9 100644 --- a/arch/x86/kernel/vsmp_64.c +++ b/arch/x86/kernel/vsmp_64.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/pci_ids.h> | 16 | #include <linux/pci_ids.h> |
17 | #include <linux/pci_regs.h> | 17 | #include <linux/pci_regs.h> |
18 | #include <linux/smp.h> | 18 | #include <linux/smp.h> |
19 | #include <linux/irq.h> | ||
19 | 20 | ||
20 | #include <asm/apic.h> | 21 | #include <asm/apic.h> |
21 | #include <asm/pci-direct.h> | 22 | #include <asm/pci-direct.h> |
@@ -95,6 +96,18 @@ static void __init set_vsmp_pv_ops(void) | |||
95 | ctl = readl(address + 4); | 96 | ctl = readl(address + 4); |
96 | printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n", | 97 | printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n", |
97 | cap, ctl); | 98 | cap, ctl); |
99 | |||
100 | /* If possible, let the vSMP foundation route the interrupt optimally */ | ||
101 | #ifdef CONFIG_SMP | ||
102 | if (cap & ctl & BIT(8)) { | ||
103 | ctl &= ~BIT(8); | ||
104 | #ifdef CONFIG_PROC_FS | ||
105 | /* Don't let users change irq affinity via procfs */ | ||
106 | no_irq_affinity = 1; | ||
107 | #endif | ||
108 | } | ||
109 | #endif | ||
110 | |||
98 | if (cap & ctl & (1 << 4)) { | 111 | if (cap & ctl & (1 << 4)) { |
99 | /* Setup irq ops and turn on vSMP IRQ fastpath handling */ | 112 | /* Setup irq ops and turn on vSMP IRQ fastpath handling */ |
100 | pv_irq_ops.irq_disable = PV_CALLEE_SAVE(vsmp_irq_disable); | 113 | pv_irq_ops.irq_disable = PV_CALLEE_SAVE(vsmp_irq_disable); |
@@ -102,12 +115,11 @@ static void __init set_vsmp_pv_ops(void) | |||
102 | pv_irq_ops.save_fl = PV_CALLEE_SAVE(vsmp_save_fl); | 115 | pv_irq_ops.save_fl = PV_CALLEE_SAVE(vsmp_save_fl); |
103 | pv_irq_ops.restore_fl = PV_CALLEE_SAVE(vsmp_restore_fl); | 116 | pv_irq_ops.restore_fl = PV_CALLEE_SAVE(vsmp_restore_fl); |
104 | pv_init_ops.patch = vsmp_patch; | 117 | pv_init_ops.patch = vsmp_patch; |
105 | |||
106 | ctl &= ~(1 << 4); | 118 | ctl &= ~(1 << 4); |
107 | writel(ctl, address + 4); | ||
108 | ctl = readl(address + 4); | ||
109 | printk(KERN_INFO "vSMP CTL: control set to:0x%08x\n", ctl); | ||
110 | } | 119 | } |
120 | writel(ctl, address + 4); | ||
121 | ctl = readl(address + 4); | ||
122 | pr_info("vSMP CTL: control set to:0x%08x\n", ctl); | ||
111 | 123 | ||
112 | early_iounmap(address, 8); | 124 | early_iounmap(address, 8); |
113 | } | 125 | } |
@@ -187,12 +199,36 @@ static void __init vsmp_cap_cpus(void) | |||
187 | #endif | 199 | #endif |
188 | } | 200 | } |
189 | 201 | ||
202 | static int apicid_phys_pkg_id(int initial_apic_id, int index_msb) | ||
203 | { | ||
204 | return hard_smp_processor_id() >> index_msb; | ||
205 | } | ||
206 | |||
207 | /* | ||
208 | * In vSMP, all cpus should be capable of handling interrupts, regardless of | ||
209 | * the APIC used. | ||
210 | */ | ||
211 | static void fill_vector_allocation_domain(int cpu, struct cpumask *retmask, | ||
212 | const struct cpumask *mask) | ||
213 | { | ||
214 | cpumask_setall(retmask); | ||
215 | } | ||
216 | |||
217 | static void vsmp_apic_post_init(void) | ||
218 | { | ||
219 | /* need to update phys_pkg_id */ | ||
220 | apic->phys_pkg_id = apicid_phys_pkg_id; | ||
221 | apic->vector_allocation_domain = fill_vector_allocation_domain; | ||
222 | } | ||
223 | |||
190 | void __init vsmp_init(void) | 224 | void __init vsmp_init(void) |
191 | { | 225 | { |
192 | detect_vsmp_box(); | 226 | detect_vsmp_box(); |
193 | if (!is_vsmp_box()) | 227 | if (!is_vsmp_box()) |
194 | return; | 228 | return; |
195 | 229 | ||
230 | x86_platform.apic_post_init = vsmp_apic_post_init; | ||
231 | |||
196 | vsmp_cap_cpus(); | 232 | vsmp_cap_cpus(); |
197 | 233 | ||
198 | set_vsmp_pv_ops(); | 234 | set_vsmp_pv_ops(); |
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c index 7515cf0e1805..8d141b309046 100644 --- a/arch/x86/kernel/vsyscall_64.c +++ b/arch/x86/kernel/vsyscall_64.c | |||
@@ -18,6 +18,8 @@ | |||
18 | * use the vDSO. | 18 | * use the vDSO. |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
22 | |||
21 | #include <linux/time.h> | 23 | #include <linux/time.h> |
22 | #include <linux/init.h> | 24 | #include <linux/init.h> |
23 | #include <linux/kernel.h> | 25 | #include <linux/kernel.h> |
@@ -111,18 +113,13 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm, | |||
111 | static void warn_bad_vsyscall(const char *level, struct pt_regs *regs, | 113 | static void warn_bad_vsyscall(const char *level, struct pt_regs *regs, |
112 | const char *message) | 114 | const char *message) |
113 | { | 115 | { |
114 | static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); | 116 | if (!show_unhandled_signals) |
115 | struct task_struct *tsk; | ||
116 | |||
117 | if (!show_unhandled_signals || !__ratelimit(&rs)) | ||
118 | return; | 117 | return; |
119 | 118 | ||
120 | tsk = current; | 119 | pr_notice_ratelimited("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n", |
121 | 120 | level, current->comm, task_pid_nr(current), | |
122 | printk("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n", | 121 | message, regs->ip, regs->cs, |
123 | level, tsk->comm, task_pid_nr(tsk), | 122 | regs->sp, regs->ax, regs->si, regs->di); |
124 | message, regs->ip, regs->cs, | ||
125 | regs->sp, regs->ax, regs->si, regs->di); | ||
126 | } | 123 | } |
127 | 124 | ||
128 | static int addr_to_vsyscall_nr(unsigned long addr) | 125 | static int addr_to_vsyscall_nr(unsigned long addr) |
@@ -139,6 +136,19 @@ static int addr_to_vsyscall_nr(unsigned long addr) | |||
139 | return nr; | 136 | return nr; |
140 | } | 137 | } |
141 | 138 | ||
139 | #ifdef CONFIG_SECCOMP | ||
140 | static int vsyscall_seccomp(struct task_struct *tsk, int syscall_nr) | ||
141 | { | ||
142 | if (!seccomp_mode(&tsk->seccomp)) | ||
143 | return 0; | ||
144 | task_pt_regs(tsk)->orig_ax = syscall_nr; | ||
145 | task_pt_regs(tsk)->ax = syscall_nr; | ||
146 | return __secure_computing(syscall_nr); | ||
147 | } | ||
148 | #else | ||
149 | #define vsyscall_seccomp(_tsk, _nr) 0 | ||
150 | #endif | ||
151 | |||
142 | static bool write_ok_or_segv(unsigned long ptr, size_t size) | 152 | static bool write_ok_or_segv(unsigned long ptr, size_t size) |
143 | { | 153 | { |
144 | /* | 154 | /* |
@@ -174,6 +184,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
174 | int vsyscall_nr; | 184 | int vsyscall_nr; |
175 | int prev_sig_on_uaccess_error; | 185 | int prev_sig_on_uaccess_error; |
176 | long ret; | 186 | long ret; |
187 | int skip; | ||
177 | 188 | ||
178 | /* | 189 | /* |
179 | * No point in checking CS -- the only way to get here is a user mode | 190 | * No point in checking CS -- the only way to get here is a user mode |
@@ -205,9 +216,6 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
205 | } | 216 | } |
206 | 217 | ||
207 | tsk = current; | 218 | tsk = current; |
208 | if (seccomp_mode(&tsk->seccomp)) | ||
209 | do_exit(SIGKILL); | ||
210 | |||
211 | /* | 219 | /* |
212 | * With a real vsyscall, page faults cause SIGSEGV. We want to | 220 | * With a real vsyscall, page faults cause SIGSEGV. We want to |
213 | * preserve that behavior to make writing exploits harder. | 221 | * preserve that behavior to make writing exploits harder. |
@@ -222,8 +230,13 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
222 | * address 0". | 230 | * address 0". |
223 | */ | 231 | */ |
224 | ret = -EFAULT; | 232 | ret = -EFAULT; |
233 | skip = 0; | ||
225 | switch (vsyscall_nr) { | 234 | switch (vsyscall_nr) { |
226 | case 0: | 235 | case 0: |
236 | skip = vsyscall_seccomp(tsk, __NR_gettimeofday); | ||
237 | if (skip) | ||
238 | break; | ||
239 | |||
227 | if (!write_ok_or_segv(regs->di, sizeof(struct timeval)) || | 240 | if (!write_ok_or_segv(regs->di, sizeof(struct timeval)) || |
228 | !write_ok_or_segv(regs->si, sizeof(struct timezone))) | 241 | !write_ok_or_segv(regs->si, sizeof(struct timezone))) |
229 | break; | 242 | break; |
@@ -234,6 +247,10 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
234 | break; | 247 | break; |
235 | 248 | ||
236 | case 1: | 249 | case 1: |
250 | skip = vsyscall_seccomp(tsk, __NR_time); | ||
251 | if (skip) | ||
252 | break; | ||
253 | |||
237 | if (!write_ok_or_segv(regs->di, sizeof(time_t))) | 254 | if (!write_ok_or_segv(regs->di, sizeof(time_t))) |
238 | break; | 255 | break; |
239 | 256 | ||
@@ -241,6 +258,10 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
241 | break; | 258 | break; |
242 | 259 | ||
243 | case 2: | 260 | case 2: |
261 | skip = vsyscall_seccomp(tsk, __NR_getcpu); | ||
262 | if (skip) | ||
263 | break; | ||
264 | |||
244 | if (!write_ok_or_segv(regs->di, sizeof(unsigned)) || | 265 | if (!write_ok_or_segv(regs->di, sizeof(unsigned)) || |
245 | !write_ok_or_segv(regs->si, sizeof(unsigned))) | 266 | !write_ok_or_segv(regs->si, sizeof(unsigned))) |
246 | break; | 267 | break; |
@@ -253,6 +274,12 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
253 | 274 | ||
254 | current_thread_info()->sig_on_uaccess_error = prev_sig_on_uaccess_error; | 275 | current_thread_info()->sig_on_uaccess_error = prev_sig_on_uaccess_error; |
255 | 276 | ||
277 | if (skip) { | ||
278 | if ((long)regs->ax <= 0L) /* seccomp errno emulation */ | ||
279 | goto do_ret; | ||
280 | goto done; /* seccomp trace/trap */ | ||
281 | } | ||
282 | |||
256 | if (ret == -EFAULT) { | 283 | if (ret == -EFAULT) { |
257 | /* Bad news -- userspace fed a bad pointer to a vsyscall. */ | 284 | /* Bad news -- userspace fed a bad pointer to a vsyscall. */ |
258 | warn_bad_vsyscall(KERN_INFO, regs, | 285 | warn_bad_vsyscall(KERN_INFO, regs, |
@@ -271,10 +298,11 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address) | |||
271 | 298 | ||
272 | regs->ax = ret; | 299 | regs->ax = ret; |
273 | 300 | ||
301 | do_ret: | ||
274 | /* Emulate a ret instruction. */ | 302 | /* Emulate a ret instruction. */ |
275 | regs->ip = caller; | 303 | regs->ip = caller; |
276 | regs->sp += 8; | 304 | regs->sp += 8; |
277 | 305 | done: | |
278 | return true; | 306 | return true; |
279 | 307 | ||
280 | sigsegv: | 308 | sigsegv: |
diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c index 9796c2f3d074..6020f6f5927c 100644 --- a/arch/x86/kernel/x8664_ksyms_64.c +++ b/arch/x86/kernel/x8664_ksyms_64.c | |||
@@ -28,6 +28,7 @@ EXPORT_SYMBOL(__put_user_8); | |||
28 | 28 | ||
29 | EXPORT_SYMBOL(copy_user_generic_string); | 29 | EXPORT_SYMBOL(copy_user_generic_string); |
30 | EXPORT_SYMBOL(copy_user_generic_unrolled); | 30 | EXPORT_SYMBOL(copy_user_generic_unrolled); |
31 | EXPORT_SYMBOL(copy_user_enhanced_fast_string); | ||
31 | EXPORT_SYMBOL(__copy_user_nocache); | 32 | EXPORT_SYMBOL(__copy_user_nocache); |
32 | EXPORT_SYMBOL(_copy_from_user); | 33 | EXPORT_SYMBOL(_copy_from_user); |
33 | EXPORT_SYMBOL(_copy_to_user); | 34 | EXPORT_SYMBOL(_copy_to_user); |
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c index 35c5e543f550..9f3167e891ef 100644 --- a/arch/x86/kernel/x86_init.c +++ b/arch/x86/kernel/x86_init.c | |||
@@ -29,7 +29,6 @@ void __init x86_init_uint_noop(unsigned int unused) { } | |||
29 | void __init x86_init_pgd_noop(pgd_t *unused) { } | 29 | void __init x86_init_pgd_noop(pgd_t *unused) { } |
30 | int __init iommu_init_noop(void) { return 0; } | 30 | int __init iommu_init_noop(void) { return 0; } |
31 | void iommu_shutdown_noop(void) { } | 31 | void iommu_shutdown_noop(void) { } |
32 | void wallclock_init_noop(void) { } | ||
33 | 32 | ||
34 | /* | 33 | /* |
35 | * The platform setup functions are preset with the default functions | 34 | * The platform setup functions are preset with the default functions |
@@ -101,7 +100,6 @@ static int default_i8042_detect(void) { return 1; }; | |||
101 | 100 | ||
102 | struct x86_platform_ops x86_platform = { | 101 | struct x86_platform_ops x86_platform = { |
103 | .calibrate_tsc = native_calibrate_tsc, | 102 | .calibrate_tsc = native_calibrate_tsc, |
104 | .wallclock_init = wallclock_init_noop, | ||
105 | .get_wallclock = mach_get_cmos_time, | 103 | .get_wallclock = mach_get_cmos_time, |
106 | .set_wallclock = mach_set_rtc_mmss, | 104 | .set_wallclock = mach_set_rtc_mmss, |
107 | .iommu_shutdown = iommu_shutdown_noop, | 105 | .iommu_shutdown = iommu_shutdown_noop, |
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c index bd18149b2b0f..3d3e20709119 100644 --- a/arch/x86/kernel/xsave.c +++ b/arch/x86/kernel/xsave.c | |||
@@ -3,6 +3,9 @@ | |||
3 | * | 3 | * |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | 4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> |
5 | */ | 5 | */ |
6 | |||
7 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | ||
8 | |||
6 | #include <linux/bootmem.h> | 9 | #include <linux/bootmem.h> |
7 | #include <linux/compat.h> | 10 | #include <linux/compat.h> |
8 | #include <asm/i387.h> | 11 | #include <asm/i387.h> |
@@ -162,7 +165,7 @@ int save_i387_xstate(void __user *buf) | |||
162 | BUG_ON(sig_xstate_size < xstate_size); | 165 | BUG_ON(sig_xstate_size < xstate_size); |
163 | 166 | ||
164 | if ((unsigned long)buf % 64) | 167 | if ((unsigned long)buf % 64) |
165 | printk("save_i387_xstate: bad fpstate %p\n", buf); | 168 | pr_err("%s: bad fpstate %p\n", __func__, buf); |
166 | 169 | ||
167 | if (!used_math()) | 170 | if (!used_math()) |
168 | return 0; | 171 | return 0; |
@@ -422,7 +425,7 @@ static void __init xstate_enable_boot_cpu(void) | |||
422 | pcntxt_mask = eax + ((u64)edx << 32); | 425 | pcntxt_mask = eax + ((u64)edx << 32); |
423 | 426 | ||
424 | if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { | 427 | if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) { |
425 | printk(KERN_ERR "FP/SSE not shown under xsave features 0x%llx\n", | 428 | pr_err("FP/SSE not shown under xsave features 0x%llx\n", |
426 | pcntxt_mask); | 429 | pcntxt_mask); |
427 | BUG(); | 430 | BUG(); |
428 | } | 431 | } |
@@ -445,9 +448,8 @@ static void __init xstate_enable_boot_cpu(void) | |||
445 | 448 | ||
446 | setup_xstate_init(); | 449 | setup_xstate_init(); |
447 | 450 | ||
448 | printk(KERN_INFO "xsave/xrstor: enabled xstate_bv 0x%llx, " | 451 | pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n", |
449 | "cntxt size 0x%x\n", | 452 | pcntxt_mask, xstate_size); |
450 | pcntxt_mask, xstate_size); | ||
451 | } | 453 | } |
452 | 454 | ||
453 | /* | 455 | /* |
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 2e88438ffd83..9b7ec1150ab0 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c | |||
@@ -80,10 +80,10 @@ static inline struct kvm_pmc *get_fixed_pmc_idx(struct kvm_pmu *pmu, int idx) | |||
80 | 80 | ||
81 | static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx) | 81 | static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx) |
82 | { | 82 | { |
83 | if (idx < X86_PMC_IDX_FIXED) | 83 | if (idx < INTEL_PMC_IDX_FIXED) |
84 | return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0); | 84 | return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0); |
85 | else | 85 | else |
86 | return get_fixed_pmc_idx(pmu, idx - X86_PMC_IDX_FIXED); | 86 | return get_fixed_pmc_idx(pmu, idx - INTEL_PMC_IDX_FIXED); |
87 | } | 87 | } |
88 | 88 | ||
89 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu) | 89 | void kvm_deliver_pmi(struct kvm_vcpu *vcpu) |
@@ -291,7 +291,7 @@ static void reprogram_idx(struct kvm_pmu *pmu, int idx) | |||
291 | if (pmc_is_gp(pmc)) | 291 | if (pmc_is_gp(pmc)) |
292 | reprogram_gp_counter(pmc, pmc->eventsel); | 292 | reprogram_gp_counter(pmc, pmc->eventsel); |
293 | else { | 293 | else { |
294 | int fidx = idx - X86_PMC_IDX_FIXED; | 294 | int fidx = idx - INTEL_PMC_IDX_FIXED; |
295 | reprogram_fixed_counter(pmc, | 295 | reprogram_fixed_counter(pmc, |
296 | fixed_en_pmi(pmu->fixed_ctr_ctrl, fidx), fidx); | 296 | fixed_en_pmi(pmu->fixed_ctr_ctrl, fidx), fidx); |
297 | } | 297 | } |
@@ -452,7 +452,7 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu) | |||
452 | return; | 452 | return; |
453 | 453 | ||
454 | pmu->nr_arch_gp_counters = min((int)(entry->eax >> 8) & 0xff, | 454 | pmu->nr_arch_gp_counters = min((int)(entry->eax >> 8) & 0xff, |
455 | X86_PMC_MAX_GENERIC); | 455 | INTEL_PMC_MAX_GENERIC); |
456 | pmu->counter_bitmask[KVM_PMC_GP] = | 456 | pmu->counter_bitmask[KVM_PMC_GP] = |
457 | ((u64)1 << ((entry->eax >> 16) & 0xff)) - 1; | 457 | ((u64)1 << ((entry->eax >> 16) & 0xff)) - 1; |
458 | bitmap_len = (entry->eax >> 24) & 0xff; | 458 | bitmap_len = (entry->eax >> 24) & 0xff; |
@@ -462,13 +462,13 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu) | |||
462 | pmu->nr_arch_fixed_counters = 0; | 462 | pmu->nr_arch_fixed_counters = 0; |
463 | } else { | 463 | } else { |
464 | pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), | 464 | pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f), |
465 | X86_PMC_MAX_FIXED); | 465 | INTEL_PMC_MAX_FIXED); |
466 | pmu->counter_bitmask[KVM_PMC_FIXED] = | 466 | pmu->counter_bitmask[KVM_PMC_FIXED] = |
467 | ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; | 467 | ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1; |
468 | } | 468 | } |
469 | 469 | ||
470 | pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | | 470 | pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) | |
471 | (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED); | 471 | (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED); |
472 | pmu->global_ctrl_mask = ~pmu->global_ctrl; | 472 | pmu->global_ctrl_mask = ~pmu->global_ctrl; |
473 | } | 473 | } |
474 | 474 | ||
@@ -478,15 +478,15 @@ void kvm_pmu_init(struct kvm_vcpu *vcpu) | |||
478 | struct kvm_pmu *pmu = &vcpu->arch.pmu; | 478 | struct kvm_pmu *pmu = &vcpu->arch.pmu; |
479 | 479 | ||
480 | memset(pmu, 0, sizeof(*pmu)); | 480 | memset(pmu, 0, sizeof(*pmu)); |
481 | for (i = 0; i < X86_PMC_MAX_GENERIC; i++) { | 481 | for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { |
482 | pmu->gp_counters[i].type = KVM_PMC_GP; | 482 | pmu->gp_counters[i].type = KVM_PMC_GP; |
483 | pmu->gp_counters[i].vcpu = vcpu; | 483 | pmu->gp_counters[i].vcpu = vcpu; |
484 | pmu->gp_counters[i].idx = i; | 484 | pmu->gp_counters[i].idx = i; |
485 | } | 485 | } |
486 | for (i = 0; i < X86_PMC_MAX_FIXED; i++) { | 486 | for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) { |
487 | pmu->fixed_counters[i].type = KVM_PMC_FIXED; | 487 | pmu->fixed_counters[i].type = KVM_PMC_FIXED; |
488 | pmu->fixed_counters[i].vcpu = vcpu; | 488 | pmu->fixed_counters[i].vcpu = vcpu; |
489 | pmu->fixed_counters[i].idx = i + X86_PMC_IDX_FIXED; | 489 | pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED; |
490 | } | 490 | } |
491 | init_irq_work(&pmu->irq_work, trigger_pmi); | 491 | init_irq_work(&pmu->irq_work, trigger_pmi); |
492 | kvm_pmu_cpuid_update(vcpu); | 492 | kvm_pmu_cpuid_update(vcpu); |
@@ -498,13 +498,13 @@ void kvm_pmu_reset(struct kvm_vcpu *vcpu) | |||
498 | int i; | 498 | int i; |
499 | 499 | ||
500 | irq_work_sync(&pmu->irq_work); | 500 | irq_work_sync(&pmu->irq_work); |
501 | for (i = 0; i < X86_PMC_MAX_GENERIC; i++) { | 501 | for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) { |
502 | struct kvm_pmc *pmc = &pmu->gp_counters[i]; | 502 | struct kvm_pmc *pmc = &pmu->gp_counters[i]; |
503 | stop_counter(pmc); | 503 | stop_counter(pmc); |
504 | pmc->counter = pmc->eventsel = 0; | 504 | pmc->counter = pmc->eventsel = 0; |
505 | } | 505 | } |
506 | 506 | ||
507 | for (i = 0; i < X86_PMC_MAX_FIXED; i++) | 507 | for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) |
508 | stop_counter(&pmu->fixed_counters[i]); | 508 | stop_counter(&pmu->fixed_counters[i]); |
509 | 509 | ||
510 | pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = | 510 | pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = |
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index 911d2641f14c..62d02e3c3ed6 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h | |||
@@ -710,16 +710,6 @@ TRACE_EVENT(kvm_skinit, | |||
710 | __entry->rip, __entry->slb) | 710 | __entry->rip, __entry->slb) |
711 | ); | 711 | ); |
712 | 712 | ||
713 | #define __print_insn(insn, ilen) ({ \ | ||
714 | int i; \ | ||
715 | const char *ret = p->buffer + p->len; \ | ||
716 | \ | ||
717 | for (i = 0; i < ilen; ++i) \ | ||
718 | trace_seq_printf(p, " %02x", insn[i]); \ | ||
719 | trace_seq_printf(p, "%c", 0); \ | ||
720 | ret; \ | ||
721 | }) | ||
722 | |||
723 | #define KVM_EMUL_INSN_F_CR0_PE (1 << 0) | 713 | #define KVM_EMUL_INSN_F_CR0_PE (1 << 0) |
724 | #define KVM_EMUL_INSN_F_EFL_VM (1 << 1) | 714 | #define KVM_EMUL_INSN_F_EFL_VM (1 << 1) |
725 | #define KVM_EMUL_INSN_F_CS_D (1 << 2) | 715 | #define KVM_EMUL_INSN_F_CS_D (1 << 2) |
@@ -786,7 +776,7 @@ TRACE_EVENT(kvm_emulate_insn, | |||
786 | 776 | ||
787 | TP_printk("%x:%llx:%s (%s)%s", | 777 | TP_printk("%x:%llx:%s (%s)%s", |
788 | __entry->csbase, __entry->rip, | 778 | __entry->csbase, __entry->rip, |
789 | __print_insn(__entry->insn, __entry->len), | 779 | __print_hex(__entry->insn, __entry->len), |
790 | __print_symbolic(__entry->flags, | 780 | __print_symbolic(__entry->flags, |
791 | kvm_trace_symbol_emul_flags), | 781 | kvm_trace_symbol_emul_flags), |
792 | __entry->failed ? " failed" : "" | 782 | __entry->failed ? " failed" : "" |
diff --git a/arch/x86/lib/msr-reg-export.c b/arch/x86/lib/msr-reg-export.c index a311cc59b65d..8d6ef78b5d01 100644 --- a/arch/x86/lib/msr-reg-export.c +++ b/arch/x86/lib/msr-reg-export.c | |||
@@ -1,5 +1,5 @@ | |||
1 | #include <linux/module.h> | 1 | #include <linux/module.h> |
2 | #include <asm/msr.h> | 2 | #include <asm/msr.h> |
3 | 3 | ||
4 | EXPORT_SYMBOL(native_rdmsr_safe_regs); | 4 | EXPORT_SYMBOL(rdmsr_safe_regs); |
5 | EXPORT_SYMBOL(native_wrmsr_safe_regs); | 5 | EXPORT_SYMBOL(wrmsr_safe_regs); |
diff --git a/arch/x86/lib/msr-reg.S b/arch/x86/lib/msr-reg.S index 69fa10623f21..f6d13eefad10 100644 --- a/arch/x86/lib/msr-reg.S +++ b/arch/x86/lib/msr-reg.S | |||
@@ -6,13 +6,13 @@ | |||
6 | 6 | ||
7 | #ifdef CONFIG_X86_64 | 7 | #ifdef CONFIG_X86_64 |
8 | /* | 8 | /* |
9 | * int native_{rdmsr,wrmsr}_safe_regs(u32 gprs[8]); | 9 | * int {rdmsr,wrmsr}_safe_regs(u32 gprs[8]); |
10 | * | 10 | * |
11 | * reg layout: u32 gprs[eax, ecx, edx, ebx, esp, ebp, esi, edi] | 11 | * reg layout: u32 gprs[eax, ecx, edx, ebx, esp, ebp, esi, edi] |
12 | * | 12 | * |
13 | */ | 13 | */ |
14 | .macro op_safe_regs op | 14 | .macro op_safe_regs op |
15 | ENTRY(native_\op\()_safe_regs) | 15 | ENTRY(\op\()_safe_regs) |
16 | CFI_STARTPROC | 16 | CFI_STARTPROC |
17 | pushq_cfi %rbx | 17 | pushq_cfi %rbx |
18 | pushq_cfi %rbp | 18 | pushq_cfi %rbp |
@@ -45,13 +45,13 @@ ENTRY(native_\op\()_safe_regs) | |||
45 | 45 | ||
46 | _ASM_EXTABLE(1b, 3b) | 46 | _ASM_EXTABLE(1b, 3b) |
47 | CFI_ENDPROC | 47 | CFI_ENDPROC |
48 | ENDPROC(native_\op\()_safe_regs) | 48 | ENDPROC(\op\()_safe_regs) |
49 | .endm | 49 | .endm |
50 | 50 | ||
51 | #else /* X86_32 */ | 51 | #else /* X86_32 */ |
52 | 52 | ||
53 | .macro op_safe_regs op | 53 | .macro op_safe_regs op |
54 | ENTRY(native_\op\()_safe_regs) | 54 | ENTRY(\op\()_safe_regs) |
55 | CFI_STARTPROC | 55 | CFI_STARTPROC |
56 | pushl_cfi %ebx | 56 | pushl_cfi %ebx |
57 | pushl_cfi %ebp | 57 | pushl_cfi %ebp |
@@ -92,7 +92,7 @@ ENTRY(native_\op\()_safe_regs) | |||
92 | 92 | ||
93 | _ASM_EXTABLE(1b, 3b) | 93 | _ASM_EXTABLE(1b, 3b) |
94 | CFI_ENDPROC | 94 | CFI_ENDPROC |
95 | ENDPROC(native_\op\()_safe_regs) | 95 | ENDPROC(\op\()_safe_regs) |
96 | .endm | 96 | .endm |
97 | 97 | ||
98 | #endif | 98 | #endif |
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index bc4e9d84157f..e0e6990723e9 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c | |||
@@ -385,7 +385,7 @@ void free_initmem(void) | |||
385 | } | 385 | } |
386 | 386 | ||
387 | #ifdef CONFIG_BLK_DEV_INITRD | 387 | #ifdef CONFIG_BLK_DEV_INITRD |
388 | void free_initrd_mem(unsigned long start, unsigned long end) | 388 | void __init free_initrd_mem(unsigned long start, unsigned long end) |
389 | { | 389 | { |
390 | /* | 390 | /* |
391 | * end could be not aligned, and We can not align that, | 391 | * end could be not aligned, and We can not align that, |
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 303f08637826..b2b94438ff05 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -312,7 +312,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs) | |||
312 | goto fail; | 312 | goto fail; |
313 | } | 313 | } |
314 | /* both registers must be reserved */ | 314 | /* both registers must be reserved */ |
315 | if (num_counters == AMD64_NUM_COUNTERS_F15H) { | 315 | if (num_counters == AMD64_NUM_COUNTERS_CORE) { |
316 | msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1); | 316 | msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1); |
317 | msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); | 317 | msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1); |
318 | } else { | 318 | } else { |
@@ -514,7 +514,7 @@ static int op_amd_init(struct oprofile_operations *ops) | |||
514 | ops->create_files = setup_ibs_files; | 514 | ops->create_files = setup_ibs_files; |
515 | 515 | ||
516 | if (boot_cpu_data.x86 == 0x15) { | 516 | if (boot_cpu_data.x86 == 0x15) { |
517 | num_counters = AMD64_NUM_COUNTERS_F15H; | 517 | num_counters = AMD64_NUM_COUNTERS_CORE; |
518 | } else { | 518 | } else { |
519 | num_counters = AMD64_NUM_COUNTERS; | 519 | num_counters = AMD64_NUM_COUNTERS; |
520 | } | 520 | } |
diff --git a/arch/x86/platform/olpc/olpc-xo15-sci.c b/arch/x86/platform/olpc/olpc-xo15-sci.c index 23e5b9d7977b..599be499fdf7 100644 --- a/arch/x86/platform/olpc/olpc-xo15-sci.c +++ b/arch/x86/platform/olpc/olpc-xo15-sci.c | |||
@@ -203,7 +203,7 @@ static int xo15_sci_remove(struct acpi_device *device, int type) | |||
203 | return 0; | 203 | return 0; |
204 | } | 204 | } |
205 | 205 | ||
206 | static int xo15_sci_resume(struct acpi_device *device) | 206 | static int xo15_sci_resume(struct device *dev) |
207 | { | 207 | { |
208 | /* Enable all EC events */ | 208 | /* Enable all EC events */ |
209 | olpc_ec_mask_write(EC_SCI_SRC_ALL); | 209 | olpc_ec_mask_write(EC_SCI_SRC_ALL); |
@@ -215,6 +215,8 @@ static int xo15_sci_resume(struct acpi_device *device) | |||
215 | return 0; | 215 | return 0; |
216 | } | 216 | } |
217 | 217 | ||
218 | static SIMPLE_DEV_PM_OPS(xo15_sci_pm, NULL, xo15_sci_resume); | ||
219 | |||
218 | static const struct acpi_device_id xo15_sci_device_ids[] = { | 220 | static const struct acpi_device_id xo15_sci_device_ids[] = { |
219 | {"XO15EC", 0}, | 221 | {"XO15EC", 0}, |
220 | {"", 0}, | 222 | {"", 0}, |
@@ -227,8 +229,8 @@ static struct acpi_driver xo15_sci_drv = { | |||
227 | .ops = { | 229 | .ops = { |
228 | .add = xo15_sci_add, | 230 | .add = xo15_sci_add, |
229 | .remove = xo15_sci_remove, | 231 | .remove = xo15_sci_remove, |
230 | .resume = xo15_sci_resume, | ||
231 | }, | 232 | }, |
233 | .drv.pm = &xo15_sci_pm, | ||
232 | }; | 234 | }; |
233 | 235 | ||
234 | static int __init xo15_sci_init(void) | 236 | static int __init xo15_sci_init(void) |
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c index 59880afa851f..71b5d5a07d7b 100644 --- a/arch/x86/platform/uv/tlb_uv.c +++ b/arch/x86/platform/uv/tlb_uv.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * SGI UltraViolet TLB flush routines. | 2 | * SGI UltraViolet TLB flush routines. |
3 | * | 3 | * |
4 | * (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI. | 4 | * (c) 2008-2012 Cliff Wickman <cpw@sgi.com>, SGI. |
5 | * | 5 | * |
6 | * This code is released under the GNU General Public License version 2 or | 6 | * This code is released under the GNU General Public License version 2 or |
7 | * later. | 7 | * later. |
@@ -38,8 +38,7 @@ static int timeout_base_ns[] = { | |||
38 | 38 | ||
39 | static int timeout_us; | 39 | static int timeout_us; |
40 | static int nobau; | 40 | static int nobau; |
41 | static int baudisabled; | 41 | static int nobau_perm; |
42 | static spinlock_t disable_lock; | ||
43 | static cycles_t congested_cycles; | 42 | static cycles_t congested_cycles; |
44 | 43 | ||
45 | /* tunables: */ | 44 | /* tunables: */ |
@@ -47,12 +46,13 @@ static int max_concurr = MAX_BAU_CONCURRENT; | |||
47 | static int max_concurr_const = MAX_BAU_CONCURRENT; | 46 | static int max_concurr_const = MAX_BAU_CONCURRENT; |
48 | static int plugged_delay = PLUGGED_DELAY; | 47 | static int plugged_delay = PLUGGED_DELAY; |
49 | static int plugsb4reset = PLUGSB4RESET; | 48 | static int plugsb4reset = PLUGSB4RESET; |
49 | static int giveup_limit = GIVEUP_LIMIT; | ||
50 | static int timeoutsb4reset = TIMEOUTSB4RESET; | 50 | static int timeoutsb4reset = TIMEOUTSB4RESET; |
51 | static int ipi_reset_limit = IPI_RESET_LIMIT; | 51 | static int ipi_reset_limit = IPI_RESET_LIMIT; |
52 | static int complete_threshold = COMPLETE_THRESHOLD; | 52 | static int complete_threshold = COMPLETE_THRESHOLD; |
53 | static int congested_respns_us = CONGESTED_RESPONSE_US; | 53 | static int congested_respns_us = CONGESTED_RESPONSE_US; |
54 | static int congested_reps = CONGESTED_REPS; | 54 | static int congested_reps = CONGESTED_REPS; |
55 | static int congested_period = CONGESTED_PERIOD; | 55 | static int disabled_period = DISABLED_PERIOD; |
56 | 56 | ||
57 | static struct tunables tunables[] = { | 57 | static struct tunables tunables[] = { |
58 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ | 58 | {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */ |
@@ -63,7 +63,8 @@ static struct tunables tunables[] = { | |||
63 | {&complete_threshold, COMPLETE_THRESHOLD}, | 63 | {&complete_threshold, COMPLETE_THRESHOLD}, |
64 | {&congested_respns_us, CONGESTED_RESPONSE_US}, | 64 | {&congested_respns_us, CONGESTED_RESPONSE_US}, |
65 | {&congested_reps, CONGESTED_REPS}, | 65 | {&congested_reps, CONGESTED_REPS}, |
66 | {&congested_period, CONGESTED_PERIOD} | 66 | {&disabled_period, DISABLED_PERIOD}, |
67 | {&giveup_limit, GIVEUP_LIMIT} | ||
67 | }; | 68 | }; |
68 | 69 | ||
69 | static struct dentry *tunables_dir; | 70 | static struct dentry *tunables_dir; |
@@ -120,6 +121,40 @@ static DEFINE_PER_CPU(struct ptc_stats, ptcstats); | |||
120 | static DEFINE_PER_CPU(struct bau_control, bau_control); | 121 | static DEFINE_PER_CPU(struct bau_control, bau_control); |
121 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); | 122 | static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask); |
122 | 123 | ||
124 | static void | ||
125 | set_bau_on(void) | ||
126 | { | ||
127 | int cpu; | ||
128 | struct bau_control *bcp; | ||
129 | |||
130 | if (nobau_perm) { | ||
131 | pr_info("BAU not initialized; cannot be turned on\n"); | ||
132 | return; | ||
133 | } | ||
134 | nobau = 0; | ||
135 | for_each_present_cpu(cpu) { | ||
136 | bcp = &per_cpu(bau_control, cpu); | ||
137 | bcp->nobau = 0; | ||
138 | } | ||
139 | pr_info("BAU turned on\n"); | ||
140 | return; | ||
141 | } | ||
142 | |||
143 | static void | ||
144 | set_bau_off(void) | ||
145 | { | ||
146 | int cpu; | ||
147 | struct bau_control *bcp; | ||
148 | |||
149 | nobau = 1; | ||
150 | for_each_present_cpu(cpu) { | ||
151 | bcp = &per_cpu(bau_control, cpu); | ||
152 | bcp->nobau = 1; | ||
153 | } | ||
154 | pr_info("BAU turned off\n"); | ||
155 | return; | ||
156 | } | ||
157 | |||
123 | /* | 158 | /* |
124 | * Determine the first node on a uvhub. 'Nodes' are used for kernel | 159 | * Determine the first node on a uvhub. 'Nodes' are used for kernel |
125 | * memory allocation. | 160 | * memory allocation. |
@@ -278,7 +313,7 @@ static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp, | |||
278 | * Both sockets dump their completed count total into | 313 | * Both sockets dump their completed count total into |
279 | * the message's count. | 314 | * the message's count. |
280 | */ | 315 | */ |
281 | smaster->socket_acknowledge_count[mdp->msg_slot] = 0; | 316 | *sp = 0; |
282 | asp = (struct atomic_short *)&msg->acknowledge_count; | 317 | asp = (struct atomic_short *)&msg->acknowledge_count; |
283 | msg_ack_count = atom_asr(socket_ack_count, asp); | 318 | msg_ack_count = atom_asr(socket_ack_count, asp); |
284 | 319 | ||
@@ -491,16 +526,15 @@ static int uv1_wait_completion(struct bau_desc *bau_desc, | |||
491 | } | 526 | } |
492 | 527 | ||
493 | /* | 528 | /* |
494 | * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register. | 529 | * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register. |
530 | * But not currently used. | ||
495 | */ | 531 | */ |
496 | static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc) | 532 | static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc) |
497 | { | 533 | { |
498 | unsigned long descriptor_status; | 534 | unsigned long descriptor_status; |
499 | unsigned long descriptor_status2; | ||
500 | 535 | ||
501 | descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK); | 536 | descriptor_status = |
502 | descriptor_status2 = (read_mmr_uv2_status() >> desc) & 0x1UL; | 537 | ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1; |
503 | descriptor_status = (descriptor_status << 1) | descriptor_status2; | ||
504 | return descriptor_status; | 538 | return descriptor_status; |
505 | } | 539 | } |
506 | 540 | ||
@@ -531,87 +565,11 @@ int normal_busy(struct bau_control *bcp) | |||
531 | */ | 565 | */ |
532 | int handle_uv2_busy(struct bau_control *bcp) | 566 | int handle_uv2_busy(struct bau_control *bcp) |
533 | { | 567 | { |
534 | int busy_one = bcp->using_desc; | ||
535 | int normal = bcp->uvhub_cpu; | ||
536 | int selected = -1; | ||
537 | int i; | ||
538 | unsigned long descriptor_status; | ||
539 | unsigned long status; | ||
540 | int mmr_offset; | ||
541 | struct bau_desc *bau_desc_old; | ||
542 | struct bau_desc *bau_desc_new; | ||
543 | struct bau_control *hmaster = bcp->uvhub_master; | ||
544 | struct ptc_stats *stat = bcp->statp; | 568 | struct ptc_stats *stat = bcp->statp; |
545 | cycles_t ttm; | ||
546 | 569 | ||
547 | stat->s_uv2_wars++; | 570 | stat->s_uv2_wars++; |
548 | spin_lock(&hmaster->uvhub_lock); | 571 | bcp->busy = 1; |
549 | /* try for the original first */ | 572 | return FLUSH_GIVEUP; |
550 | if (busy_one != normal) { | ||
551 | if (!normal_busy(bcp)) | ||
552 | selected = normal; | ||
553 | } | ||
554 | if (selected < 0) { | ||
555 | /* can't use the normal, select an alternate */ | ||
556 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1; | ||
557 | descriptor_status = read_lmmr(mmr_offset); | ||
558 | |||
559 | /* scan available descriptors 32-63 */ | ||
560 | for (i = 0; i < UV_CPUS_PER_AS; i++) { | ||
561 | if ((hmaster->inuse_map & (1 << i)) == 0) { | ||
562 | status = ((descriptor_status >> | ||
563 | (i * UV_ACT_STATUS_SIZE)) & | ||
564 | UV_ACT_STATUS_MASK) << 1; | ||
565 | if (status != UV2H_DESC_BUSY) { | ||
566 | selected = i + UV_CPUS_PER_AS; | ||
567 | break; | ||
568 | } | ||
569 | } | ||
570 | } | ||
571 | } | ||
572 | |||
573 | if (busy_one != normal) | ||
574 | /* mark the busy alternate as not in-use */ | ||
575 | hmaster->inuse_map &= ~(1 << (busy_one - UV_CPUS_PER_AS)); | ||
576 | |||
577 | if (selected >= 0) { | ||
578 | /* switch to the selected descriptor */ | ||
579 | if (selected != normal) { | ||
580 | /* set the selected alternate as in-use */ | ||
581 | hmaster->inuse_map |= | ||
582 | (1 << (selected - UV_CPUS_PER_AS)); | ||
583 | if (selected > stat->s_uv2_wars_hw) | ||
584 | stat->s_uv2_wars_hw = selected; | ||
585 | } | ||
586 | bau_desc_old = bcp->descriptor_base; | ||
587 | bau_desc_old += (ITEMS_PER_DESC * busy_one); | ||
588 | bcp->using_desc = selected; | ||
589 | bau_desc_new = bcp->descriptor_base; | ||
590 | bau_desc_new += (ITEMS_PER_DESC * selected); | ||
591 | *bau_desc_new = *bau_desc_old; | ||
592 | } else { | ||
593 | /* | ||
594 | * All are busy. Wait for the normal one for this cpu to | ||
595 | * free up. | ||
596 | */ | ||
597 | stat->s_uv2_war_waits++; | ||
598 | spin_unlock(&hmaster->uvhub_lock); | ||
599 | ttm = get_cycles(); | ||
600 | do { | ||
601 | cpu_relax(); | ||
602 | } while (normal_busy(bcp)); | ||
603 | spin_lock(&hmaster->uvhub_lock); | ||
604 | /* switch to the original descriptor */ | ||
605 | bcp->using_desc = normal; | ||
606 | bau_desc_old = bcp->descriptor_base; | ||
607 | bau_desc_old += (ITEMS_PER_DESC * bcp->using_desc); | ||
608 | bcp->using_desc = (ITEMS_PER_DESC * normal); | ||
609 | bau_desc_new = bcp->descriptor_base; | ||
610 | bau_desc_new += (ITEMS_PER_DESC * normal); | ||
611 | *bau_desc_new = *bau_desc_old; /* copy the entire descriptor */ | ||
612 | } | ||
613 | spin_unlock(&hmaster->uvhub_lock); | ||
614 | return FLUSH_RETRY_BUSYBUG; | ||
615 | } | 573 | } |
616 | 574 | ||
617 | static int uv2_wait_completion(struct bau_desc *bau_desc, | 575 | static int uv2_wait_completion(struct bau_desc *bau_desc, |
@@ -620,7 +578,7 @@ static int uv2_wait_completion(struct bau_desc *bau_desc, | |||
620 | { | 578 | { |
621 | unsigned long descriptor_stat; | 579 | unsigned long descriptor_stat; |
622 | cycles_t ttm; | 580 | cycles_t ttm; |
623 | int desc = bcp->using_desc; | 581 | int desc = bcp->uvhub_cpu; |
624 | long busy_reps = 0; | 582 | long busy_reps = 0; |
625 | struct ptc_stats *stat = bcp->statp; | 583 | struct ptc_stats *stat = bcp->statp; |
626 | 584 | ||
@@ -628,24 +586,38 @@ static int uv2_wait_completion(struct bau_desc *bau_desc, | |||
628 | 586 | ||
629 | /* spin on the status MMR, waiting for it to go idle */ | 587 | /* spin on the status MMR, waiting for it to go idle */ |
630 | while (descriptor_stat != UV2H_DESC_IDLE) { | 588 | while (descriptor_stat != UV2H_DESC_IDLE) { |
631 | /* | 589 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) { |
632 | * Our software ack messages may be blocked because | 590 | /* |
633 | * there are no swack resources available. As long | 591 | * A h/w bug on the destination side may |
634 | * as none of them has timed out hardware will NACK | 592 | * have prevented the message being marked |
635 | * our message and its state will stay IDLE. | 593 | * pending, thus it doesn't get replied to |
636 | */ | 594 | * and gets continually nacked until it times |
637 | if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) || | 595 | * out with a SOURCE_TIMEOUT. |
638 | (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) { | 596 | */ |
639 | stat->s_stimeout++; | 597 | stat->s_stimeout++; |
640 | return FLUSH_GIVEUP; | 598 | return FLUSH_GIVEUP; |
641 | } else if (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) { | ||
642 | stat->s_strongnacks++; | ||
643 | bcp->conseccompletes = 0; | ||
644 | return FLUSH_GIVEUP; | ||
645 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { | 599 | } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) { |
600 | ttm = get_cycles(); | ||
601 | |||
602 | /* | ||
603 | * Our retries may be blocked by all destination | ||
604 | * swack resources being consumed, and a timeout | ||
605 | * pending. In that case hardware returns the | ||
606 | * ERROR that looks like a destination timeout. | ||
607 | * Without using the extended status we have to | ||
608 | * deduce from the short time that this was a | ||
609 | * strong nack. | ||
610 | */ | ||
611 | if (cycles_2_us(ttm - bcp->send_message) < timeout_us) { | ||
612 | bcp->conseccompletes = 0; | ||
613 | stat->s_plugged++; | ||
614 | /* FLUSH_RETRY_PLUGGED causes hang on boot */ | ||
615 | return FLUSH_GIVEUP; | ||
616 | } | ||
646 | stat->s_dtimeout++; | 617 | stat->s_dtimeout++; |
647 | bcp->conseccompletes = 0; | 618 | bcp->conseccompletes = 0; |
648 | return FLUSH_RETRY_TIMEOUT; | 619 | /* FLUSH_RETRY_TIMEOUT causes hang on boot */ |
620 | return FLUSH_GIVEUP; | ||
649 | } else { | 621 | } else { |
650 | busy_reps++; | 622 | busy_reps++; |
651 | if (busy_reps > 1000000) { | 623 | if (busy_reps > 1000000) { |
@@ -653,9 +625,8 @@ static int uv2_wait_completion(struct bau_desc *bau_desc, | |||
653 | busy_reps = 0; | 625 | busy_reps = 0; |
654 | ttm = get_cycles(); | 626 | ttm = get_cycles(); |
655 | if ((ttm - bcp->send_message) > | 627 | if ((ttm - bcp->send_message) > |
656 | (bcp->clocks_per_100_usec)) { | 628 | bcp->timeout_interval) |
657 | return handle_uv2_busy(bcp); | 629 | return handle_uv2_busy(bcp); |
658 | } | ||
659 | } | 630 | } |
660 | /* | 631 | /* |
661 | * descriptor_stat is still BUSY | 632 | * descriptor_stat is still BUSY |
@@ -679,7 +650,7 @@ static int wait_completion(struct bau_desc *bau_desc, | |||
679 | { | 650 | { |
680 | int right_shift; | 651 | int right_shift; |
681 | unsigned long mmr_offset; | 652 | unsigned long mmr_offset; |
682 | int desc = bcp->using_desc; | 653 | int desc = bcp->uvhub_cpu; |
683 | 654 | ||
684 | if (desc < UV_CPUS_PER_AS) { | 655 | if (desc < UV_CPUS_PER_AS) { |
685 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; | 656 | mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0; |
@@ -758,33 +729,31 @@ static void destination_timeout(struct bau_desc *bau_desc, | |||
758 | } | 729 | } |
759 | 730 | ||
760 | /* | 731 | /* |
761 | * Completions are taking a very long time due to a congested numalink | 732 | * Stop all cpus on a uvhub from using the BAU for a period of time. |
762 | * network. | 733 | * This is reversed by check_enable. |
763 | */ | 734 | */ |
764 | static void disable_for_congestion(struct bau_control *bcp, | 735 | static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat) |
765 | struct ptc_stats *stat) | ||
766 | { | 736 | { |
767 | /* let only one cpu do this disabling */ | 737 | int tcpu; |
768 | spin_lock(&disable_lock); | 738 | struct bau_control *tbcp; |
769 | 739 | struct bau_control *hmaster; | |
770 | if (!baudisabled && bcp->period_requests && | 740 | cycles_t tm1; |
771 | ((bcp->period_time / bcp->period_requests) > congested_cycles)) { | 741 | |
772 | int tcpu; | 742 | hmaster = bcp->uvhub_master; |
773 | struct bau_control *tbcp; | 743 | spin_lock(&hmaster->disable_lock); |
774 | /* it becomes this cpu's job to turn on the use of the | 744 | if (!bcp->baudisabled) { |
775 | BAU again */ | ||
776 | baudisabled = 1; | ||
777 | bcp->set_bau_off = 1; | ||
778 | bcp->set_bau_on_time = get_cycles(); | ||
779 | bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period); | ||
780 | stat->s_bau_disabled++; | 745 | stat->s_bau_disabled++; |
746 | tm1 = get_cycles(); | ||
781 | for_each_present_cpu(tcpu) { | 747 | for_each_present_cpu(tcpu) { |
782 | tbcp = &per_cpu(bau_control, tcpu); | 748 | tbcp = &per_cpu(bau_control, tcpu); |
783 | tbcp->baudisabled = 1; | 749 | if (tbcp->uvhub_master == hmaster) { |
750 | tbcp->baudisabled = 1; | ||
751 | tbcp->set_bau_on_time = | ||
752 | tm1 + bcp->disabled_period; | ||
753 | } | ||
784 | } | 754 | } |
785 | } | 755 | } |
786 | 756 | spin_unlock(&hmaster->disable_lock); | |
787 | spin_unlock(&disable_lock); | ||
788 | } | 757 | } |
789 | 758 | ||
790 | static void count_max_concurr(int stat, struct bau_control *bcp, | 759 | static void count_max_concurr(int stat, struct bau_control *bcp, |
@@ -815,16 +784,30 @@ static void record_send_stats(cycles_t time1, cycles_t time2, | |||
815 | bcp->period_requests++; | 784 | bcp->period_requests++; |
816 | bcp->period_time += elapsed; | 785 | bcp->period_time += elapsed; |
817 | if ((elapsed > congested_cycles) && | 786 | if ((elapsed > congested_cycles) && |
818 | (bcp->period_requests > bcp->cong_reps)) | 787 | (bcp->period_requests > bcp->cong_reps) && |
819 | disable_for_congestion(bcp, stat); | 788 | ((bcp->period_time / bcp->period_requests) > |
789 | congested_cycles)) { | ||
790 | stat->s_congested++; | ||
791 | disable_for_period(bcp, stat); | ||
792 | } | ||
820 | } | 793 | } |
821 | } else | 794 | } else |
822 | stat->s_requestor--; | 795 | stat->s_requestor--; |
823 | 796 | ||
824 | if (completion_status == FLUSH_COMPLETE && try > 1) | 797 | if (completion_status == FLUSH_COMPLETE && try > 1) |
825 | stat->s_retriesok++; | 798 | stat->s_retriesok++; |
826 | else if (completion_status == FLUSH_GIVEUP) | 799 | else if (completion_status == FLUSH_GIVEUP) { |
827 | stat->s_giveup++; | 800 | stat->s_giveup++; |
801 | if (get_cycles() > bcp->period_end) | ||
802 | bcp->period_giveups = 0; | ||
803 | bcp->period_giveups++; | ||
804 | if (bcp->period_giveups == 1) | ||
805 | bcp->period_end = get_cycles() + bcp->disabled_period; | ||
806 | if (bcp->period_giveups > bcp->giveup_limit) { | ||
807 | disable_for_period(bcp, stat); | ||
808 | stat->s_giveuplimit++; | ||
809 | } | ||
810 | } | ||
828 | } | 811 | } |
829 | 812 | ||
830 | /* | 813 | /* |
@@ -868,7 +851,8 @@ static void handle_cmplt(int completion_status, struct bau_desc *bau_desc, | |||
868 | * Returns 1 if it gives up entirely and the original cpu mask is to be | 851 | * Returns 1 if it gives up entirely and the original cpu mask is to be |
869 | * returned to the kernel. | 852 | * returned to the kernel. |
870 | */ | 853 | */ |
871 | int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp) | 854 | int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp, |
855 | struct bau_desc *bau_desc) | ||
872 | { | 856 | { |
873 | int seq_number = 0; | 857 | int seq_number = 0; |
874 | int completion_stat = 0; | 858 | int completion_stat = 0; |
@@ -881,24 +865,23 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp) | |||
881 | struct bau_control *hmaster = bcp->uvhub_master; | 865 | struct bau_control *hmaster = bcp->uvhub_master; |
882 | struct uv1_bau_msg_header *uv1_hdr = NULL; | 866 | struct uv1_bau_msg_header *uv1_hdr = NULL; |
883 | struct uv2_bau_msg_header *uv2_hdr = NULL; | 867 | struct uv2_bau_msg_header *uv2_hdr = NULL; |
884 | struct bau_desc *bau_desc; | ||
885 | 868 | ||
886 | if (bcp->uvhub_version == 1) | 869 | if (bcp->uvhub_version == 1) { |
870 | uv1 = 1; | ||
887 | uv1_throttle(hmaster, stat); | 871 | uv1_throttle(hmaster, stat); |
872 | } | ||
888 | 873 | ||
889 | while (hmaster->uvhub_quiesce) | 874 | while (hmaster->uvhub_quiesce) |
890 | cpu_relax(); | 875 | cpu_relax(); |
891 | 876 | ||
892 | time1 = get_cycles(); | 877 | time1 = get_cycles(); |
878 | if (uv1) | ||
879 | uv1_hdr = &bau_desc->header.uv1_hdr; | ||
880 | else | ||
881 | uv2_hdr = &bau_desc->header.uv2_hdr; | ||
882 | |||
893 | do { | 883 | do { |
894 | bau_desc = bcp->descriptor_base; | 884 | if (try == 0) { |
895 | bau_desc += (ITEMS_PER_DESC * bcp->using_desc); | ||
896 | if (bcp->uvhub_version == 1) { | ||
897 | uv1 = 1; | ||
898 | uv1_hdr = &bau_desc->header.uv1_hdr; | ||
899 | } else | ||
900 | uv2_hdr = &bau_desc->header.uv2_hdr; | ||
901 | if ((try == 0) || (completion_stat == FLUSH_RETRY_BUSYBUG)) { | ||
902 | if (uv1) | 885 | if (uv1) |
903 | uv1_hdr->msg_type = MSG_REGULAR; | 886 | uv1_hdr->msg_type = MSG_REGULAR; |
904 | else | 887 | else |
@@ -916,25 +899,24 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp) | |||
916 | uv1_hdr->sequence = seq_number; | 899 | uv1_hdr->sequence = seq_number; |
917 | else | 900 | else |
918 | uv2_hdr->sequence = seq_number; | 901 | uv2_hdr->sequence = seq_number; |
919 | index = (1UL << AS_PUSH_SHIFT) | bcp->using_desc; | 902 | index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu; |
920 | bcp->send_message = get_cycles(); | 903 | bcp->send_message = get_cycles(); |
921 | 904 | ||
922 | write_mmr_activation(index); | 905 | write_mmr_activation(index); |
923 | 906 | ||
924 | try++; | 907 | try++; |
925 | completion_stat = wait_completion(bau_desc, bcp, try); | 908 | completion_stat = wait_completion(bau_desc, bcp, try); |
926 | /* UV2: wait_completion() may change the bcp->using_desc */ | ||
927 | 909 | ||
928 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); | 910 | handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat); |
929 | 911 | ||
930 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { | 912 | if (bcp->ipi_attempts >= bcp->ipi_reset_limit) { |
931 | bcp->ipi_attempts = 0; | 913 | bcp->ipi_attempts = 0; |
914 | stat->s_overipilimit++; | ||
932 | completion_stat = FLUSH_GIVEUP; | 915 | completion_stat = FLUSH_GIVEUP; |
933 | break; | 916 | break; |
934 | } | 917 | } |
935 | cpu_relax(); | 918 | cpu_relax(); |
936 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || | 919 | } while ((completion_stat == FLUSH_RETRY_PLUGGED) || |
937 | (completion_stat == FLUSH_RETRY_BUSYBUG) || | ||
938 | (completion_stat == FLUSH_RETRY_TIMEOUT)); | 920 | (completion_stat == FLUSH_RETRY_TIMEOUT)); |
939 | 921 | ||
940 | time2 = get_cycles(); | 922 | time2 = get_cycles(); |
@@ -955,28 +937,33 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp) | |||
955 | } | 937 | } |
956 | 938 | ||
957 | /* | 939 | /* |
958 | * The BAU is disabled. When the disabled time period has expired, the cpu | 940 | * The BAU is disabled for this uvhub. When the disabled time period has |
959 | * that disabled it must re-enable it. | 941 | * expired re-enable it. |
960 | * Return 0 if it is re-enabled for all cpus. | 942 | * Return 0 if it is re-enabled for all cpus on this uvhub. |
961 | */ | 943 | */ |
962 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) | 944 | static int check_enable(struct bau_control *bcp, struct ptc_stats *stat) |
963 | { | 945 | { |
964 | int tcpu; | 946 | int tcpu; |
965 | struct bau_control *tbcp; | 947 | struct bau_control *tbcp; |
948 | struct bau_control *hmaster; | ||
966 | 949 | ||
967 | if (bcp->set_bau_off) { | 950 | hmaster = bcp->uvhub_master; |
968 | if (get_cycles() >= bcp->set_bau_on_time) { | 951 | spin_lock(&hmaster->disable_lock); |
969 | stat->s_bau_reenabled++; | 952 | if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) { |
970 | baudisabled = 0; | 953 | stat->s_bau_reenabled++; |
971 | for_each_present_cpu(tcpu) { | 954 | for_each_present_cpu(tcpu) { |
972 | tbcp = &per_cpu(bau_control, tcpu); | 955 | tbcp = &per_cpu(bau_control, tcpu); |
956 | if (tbcp->uvhub_master == hmaster) { | ||
973 | tbcp->baudisabled = 0; | 957 | tbcp->baudisabled = 0; |
974 | tbcp->period_requests = 0; | 958 | tbcp->period_requests = 0; |
975 | tbcp->period_time = 0; | 959 | tbcp->period_time = 0; |
960 | tbcp->period_giveups = 0; | ||
976 | } | 961 | } |
977 | return 0; | ||
978 | } | 962 | } |
963 | spin_unlock(&hmaster->disable_lock); | ||
964 | return 0; | ||
979 | } | 965 | } |
966 | spin_unlock(&hmaster->disable_lock); | ||
980 | return -1; | 967 | return -1; |
981 | } | 968 | } |
982 | 969 | ||
@@ -1078,18 +1065,32 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, | |||
1078 | struct cpumask *flush_mask; | 1065 | struct cpumask *flush_mask; |
1079 | struct ptc_stats *stat; | 1066 | struct ptc_stats *stat; |
1080 | struct bau_control *bcp; | 1067 | struct bau_control *bcp; |
1081 | 1068 | unsigned long descriptor_status; | |
1082 | /* kernel was booted 'nobau' */ | 1069 | unsigned long status; |
1083 | if (nobau) | ||
1084 | return cpumask; | ||
1085 | 1070 | ||
1086 | bcp = &per_cpu(bau_control, cpu); | 1071 | bcp = &per_cpu(bau_control, cpu); |
1087 | stat = bcp->statp; | 1072 | stat = bcp->statp; |
1073 | stat->s_enters++; | ||
1074 | |||
1075 | if (bcp->nobau) | ||
1076 | return cpumask; | ||
1077 | |||
1078 | if (bcp->busy) { | ||
1079 | descriptor_status = | ||
1080 | read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0); | ||
1081 | status = ((descriptor_status >> (bcp->uvhub_cpu * | ||
1082 | UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1; | ||
1083 | if (status == UV2H_DESC_BUSY) | ||
1084 | return cpumask; | ||
1085 | bcp->busy = 0; | ||
1086 | } | ||
1088 | 1087 | ||
1089 | /* bau was disabled due to slow response */ | 1088 | /* bau was disabled due to slow response */ |
1090 | if (bcp->baudisabled) { | 1089 | if (bcp->baudisabled) { |
1091 | if (check_enable(bcp, stat)) | 1090 | if (check_enable(bcp, stat)) { |
1091 | stat->s_ipifordisabled++; | ||
1092 | return cpumask; | 1092 | return cpumask; |
1093 | } | ||
1093 | } | 1094 | } |
1094 | 1095 | ||
1095 | /* | 1096 | /* |
@@ -1105,7 +1106,7 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, | |||
1105 | stat->s_ntargself++; | 1106 | stat->s_ntargself++; |
1106 | 1107 | ||
1107 | bau_desc = bcp->descriptor_base; | 1108 | bau_desc = bcp->descriptor_base; |
1108 | bau_desc += (ITEMS_PER_DESC * bcp->using_desc); | 1109 | bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu); |
1109 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); | 1110 | bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE); |
1110 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) | 1111 | if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes)) |
1111 | return NULL; | 1112 | return NULL; |
@@ -1118,25 +1119,27 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask, | |||
1118 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, | 1119 | * uv_flush_send_and_wait returns 0 if all cpu's were messaged, |
1119 | * or 1 if it gave up and the original cpumask should be returned. | 1120 | * or 1 if it gave up and the original cpumask should be returned. |
1120 | */ | 1121 | */ |
1121 | if (!uv_flush_send_and_wait(flush_mask, bcp)) | 1122 | if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc)) |
1122 | return NULL; | 1123 | return NULL; |
1123 | else | 1124 | else |
1124 | return cpumask; | 1125 | return cpumask; |
1125 | } | 1126 | } |
1126 | 1127 | ||
1127 | /* | 1128 | /* |
1128 | * Search the message queue for any 'other' message with the same software | 1129 | * Search the message queue for any 'other' unprocessed message with the |
1129 | * acknowledge resource bit vector. | 1130 | * same software acknowledge resource bit vector as the 'msg' message. |
1130 | */ | 1131 | */ |
1131 | struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg, | 1132 | struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg, |
1132 | struct bau_control *bcp, unsigned char swack_vec) | 1133 | struct bau_control *bcp) |
1133 | { | 1134 | { |
1134 | struct bau_pq_entry *msg_next = msg + 1; | 1135 | struct bau_pq_entry *msg_next = msg + 1; |
1136 | unsigned char swack_vec = msg->swack_vec; | ||
1135 | 1137 | ||
1136 | if (msg_next > bcp->queue_last) | 1138 | if (msg_next > bcp->queue_last) |
1137 | msg_next = bcp->queue_first; | 1139 | msg_next = bcp->queue_first; |
1138 | while ((msg_next->swack_vec != 0) && (msg_next != msg)) { | 1140 | while (msg_next != msg) { |
1139 | if (msg_next->swack_vec == swack_vec) | 1141 | if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) && |
1142 | (msg_next->swack_vec == swack_vec)) | ||
1140 | return msg_next; | 1143 | return msg_next; |
1141 | msg_next++; | 1144 | msg_next++; |
1142 | if (msg_next > bcp->queue_last) | 1145 | if (msg_next > bcp->queue_last) |
@@ -1165,32 +1168,30 @@ void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp) | |||
1165 | * This message was assigned a swack resource, but no | 1168 | * This message was assigned a swack resource, but no |
1166 | * reserved acknowlegment is pending. | 1169 | * reserved acknowlegment is pending. |
1167 | * The bug has prevented this message from setting the MMR. | 1170 | * The bug has prevented this message from setting the MMR. |
1168 | * And no other message has used the same sw_ack resource. | ||
1169 | * Do the requested shootdown but do not reply to the msg. | ||
1170 | * (the 0 means make no acknowledge) | ||
1171 | */ | 1171 | */ |
1172 | bau_process_message(mdp, bcp, 0); | ||
1173 | return; | ||
1174 | } | ||
1175 | |||
1176 | /* | ||
1177 | * Some message has set the MMR 'pending' bit; it might have been | ||
1178 | * another message. Look for that message. | ||
1179 | */ | ||
1180 | other_msg = find_another_by_swack(msg, bcp, msg->swack_vec); | ||
1181 | if (other_msg) { | ||
1182 | /* There is another. Do not ack the current one. */ | ||
1183 | bau_process_message(mdp, bcp, 0); | ||
1184 | /* | 1172 | /* |
1185 | * Let the natural processing of that message acknowledge | 1173 | * Some message has set the MMR 'pending' bit; it might have |
1186 | * it. Don't get the processing of sw_ack's out of order. | 1174 | * been another message. Look for that message. |
1187 | */ | 1175 | */ |
1188 | return; | 1176 | other_msg = find_another_by_swack(msg, bcp); |
1177 | if (other_msg) { | ||
1178 | /* | ||
1179 | * There is another. Process this one but do not | ||
1180 | * ack it. | ||
1181 | */ | ||
1182 | bau_process_message(mdp, bcp, 0); | ||
1183 | /* | ||
1184 | * Let the natural processing of that other message | ||
1185 | * acknowledge it. Don't get the processing of sw_ack's | ||
1186 | * out of order. | ||
1187 | */ | ||
1188 | return; | ||
1189 | } | ||
1189 | } | 1190 | } |
1190 | 1191 | ||
1191 | /* | 1192 | /* |
1192 | * There is no other message using this sw_ack, so it is safe to | 1193 | * Either the MMR shows this one pending a reply or there is no |
1193 | * acknowledge it. | 1194 | * other message using this sw_ack, so it is safe to acknowledge it. |
1194 | */ | 1195 | */ |
1195 | bau_process_message(mdp, bcp, 1); | 1196 | bau_process_message(mdp, bcp, 1); |
1196 | 1197 | ||
@@ -1295,7 +1296,8 @@ static void __init enable_timeouts(void) | |||
1295 | */ | 1296 | */ |
1296 | mmr_image |= (1L << SOFTACK_MSHIFT); | 1297 | mmr_image |= (1L << SOFTACK_MSHIFT); |
1297 | if (is_uv2_hub()) { | 1298 | if (is_uv2_hub()) { |
1298 | mmr_image |= (1L << UV2_EXT_SHFT); | 1299 | /* hw bug workaround; do not use extended status */ |
1300 | mmr_image &= ~(1L << UV2_EXT_SHFT); | ||
1299 | } | 1301 | } |
1300 | write_mmr_misc_control(pnode, mmr_image); | 1302 | write_mmr_misc_control(pnode, mmr_image); |
1301 | } | 1303 | } |
@@ -1338,29 +1340,34 @@ static inline unsigned long long usec_2_cycles(unsigned long microsec) | |||
1338 | static int ptc_seq_show(struct seq_file *file, void *data) | 1340 | static int ptc_seq_show(struct seq_file *file, void *data) |
1339 | { | 1341 | { |
1340 | struct ptc_stats *stat; | 1342 | struct ptc_stats *stat; |
1343 | struct bau_control *bcp; | ||
1341 | int cpu; | 1344 | int cpu; |
1342 | 1345 | ||
1343 | cpu = *(loff_t *)data; | 1346 | cpu = *(loff_t *)data; |
1344 | if (!cpu) { | 1347 | if (!cpu) { |
1345 | seq_printf(file, | 1348 | seq_printf(file, |
1346 | "# cpu sent stime self locals remotes ncpus localhub "); | 1349 | "# cpu bauoff sent stime self locals remotes ncpus localhub "); |
1347 | seq_printf(file, | 1350 | seq_printf(file, |
1348 | "remotehub numuvhubs numuvhubs16 numuvhubs8 "); | 1351 | "remotehub numuvhubs numuvhubs16 numuvhubs8 "); |
1349 | seq_printf(file, | 1352 | seq_printf(file, |
1350 | "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries rok "); | 1353 | "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries "); |
1354 | seq_printf(file, | ||
1355 | "rok resetp resett giveup sto bz throt disable "); | ||
1351 | seq_printf(file, | 1356 | seq_printf(file, |
1352 | "resetp resett giveup sto bz throt swack recv rtime "); | 1357 | "enable wars warshw warwaits enters ipidis plugged "); |
1353 | seq_printf(file, | 1358 | seq_printf(file, |
1354 | "all one mult none retry canc nocan reset rcan "); | 1359 | "ipiover glim cong swack recv rtime all one mult "); |
1355 | seq_printf(file, | 1360 | seq_printf(file, |
1356 | "disable enable wars warshw warwaits\n"); | 1361 | "none retry canc nocan reset rcan\n"); |
1357 | } | 1362 | } |
1358 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { | 1363 | if (cpu < num_possible_cpus() && cpu_online(cpu)) { |
1359 | stat = &per_cpu(ptcstats, cpu); | 1364 | bcp = &per_cpu(bau_control, cpu); |
1365 | stat = bcp->statp; | ||
1360 | /* source side statistics */ | 1366 | /* source side statistics */ |
1361 | seq_printf(file, | 1367 | seq_printf(file, |
1362 | "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | 1368 | "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", |
1363 | cpu, stat->s_requestor, cycles_2_us(stat->s_time), | 1369 | cpu, bcp->nobau, stat->s_requestor, |
1370 | cycles_2_us(stat->s_time), | ||
1364 | stat->s_ntargself, stat->s_ntarglocals, | 1371 | stat->s_ntargself, stat->s_ntarglocals, |
1365 | stat->s_ntargremotes, stat->s_ntargcpu, | 1372 | stat->s_ntargremotes, stat->s_ntargcpu, |
1366 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, | 1373 | stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub, |
@@ -1374,20 +1381,23 @@ static int ptc_seq_show(struct seq_file *file, void *data) | |||
1374 | stat->s_resets_plug, stat->s_resets_timeout, | 1381 | stat->s_resets_plug, stat->s_resets_timeout, |
1375 | stat->s_giveup, stat->s_stimeout, | 1382 | stat->s_giveup, stat->s_stimeout, |
1376 | stat->s_busy, stat->s_throttles); | 1383 | stat->s_busy, stat->s_throttles); |
1384 | seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | ||
1385 | stat->s_bau_disabled, stat->s_bau_reenabled, | ||
1386 | stat->s_uv2_wars, stat->s_uv2_wars_hw, | ||
1387 | stat->s_uv2_war_waits, stat->s_enters, | ||
1388 | stat->s_ipifordisabled, stat->s_plugged, | ||
1389 | stat->s_overipilimit, stat->s_giveuplimit, | ||
1390 | stat->s_congested); | ||
1377 | 1391 | ||
1378 | /* destination side statistics */ | 1392 | /* destination side statistics */ |
1379 | seq_printf(file, | 1393 | seq_printf(file, |
1380 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ", | 1394 | "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", |
1381 | read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)), | 1395 | read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)), |
1382 | stat->d_requestee, cycles_2_us(stat->d_time), | 1396 | stat->d_requestee, cycles_2_us(stat->d_time), |
1383 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, | 1397 | stat->d_alltlb, stat->d_onetlb, stat->d_multmsg, |
1384 | stat->d_nomsg, stat->d_retries, stat->d_canceled, | 1398 | stat->d_nomsg, stat->d_retries, stat->d_canceled, |
1385 | stat->d_nocanceled, stat->d_resets, | 1399 | stat->d_nocanceled, stat->d_resets, |
1386 | stat->d_rcanceled); | 1400 | stat->d_rcanceled); |
1387 | seq_printf(file, "%ld %ld %ld %ld %ld\n", | ||
1388 | stat->s_bau_disabled, stat->s_bau_reenabled, | ||
1389 | stat->s_uv2_wars, stat->s_uv2_wars_hw, | ||
1390 | stat->s_uv2_war_waits); | ||
1391 | } | 1401 | } |
1392 | return 0; | 1402 | return 0; |
1393 | } | 1403 | } |
@@ -1401,13 +1411,14 @@ static ssize_t tunables_read(struct file *file, char __user *userbuf, | |||
1401 | char *buf; | 1411 | char *buf; |
1402 | int ret; | 1412 | int ret; |
1403 | 1413 | ||
1404 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n", | 1414 | buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n", |
1405 | "max_concur plugged_delay plugsb4reset", | 1415 | "max_concur plugged_delay plugsb4reset timeoutsb4reset", |
1406 | "timeoutsb4reset ipi_reset_limit complete_threshold", | 1416 | "ipi_reset_limit complete_threshold congested_response_us", |
1407 | "congested_response_us congested_reps congested_period", | 1417 | "congested_reps disabled_period giveup_limit", |
1408 | max_concurr, plugged_delay, plugsb4reset, | 1418 | max_concurr, plugged_delay, plugsb4reset, |
1409 | timeoutsb4reset, ipi_reset_limit, complete_threshold, | 1419 | timeoutsb4reset, ipi_reset_limit, complete_threshold, |
1410 | congested_respns_us, congested_reps, congested_period); | 1420 | congested_respns_us, congested_reps, disabled_period, |
1421 | giveup_limit); | ||
1411 | 1422 | ||
1412 | if (!buf) | 1423 | if (!buf) |
1413 | return -ENOMEM; | 1424 | return -ENOMEM; |
@@ -1438,6 +1449,14 @@ static ssize_t ptc_proc_write(struct file *file, const char __user *user, | |||
1438 | return -EFAULT; | 1449 | return -EFAULT; |
1439 | optstr[count - 1] = '\0'; | 1450 | optstr[count - 1] = '\0'; |
1440 | 1451 | ||
1452 | if (!strcmp(optstr, "on")) { | ||
1453 | set_bau_on(); | ||
1454 | return count; | ||
1455 | } else if (!strcmp(optstr, "off")) { | ||
1456 | set_bau_off(); | ||
1457 | return count; | ||
1458 | } | ||
1459 | |||
1441 | if (strict_strtol(optstr, 10, &input_arg) < 0) { | 1460 | if (strict_strtol(optstr, 10, &input_arg) < 0) { |
1442 | printk(KERN_DEBUG "%s is invalid\n", optstr); | 1461 | printk(KERN_DEBUG "%s is invalid\n", optstr); |
1443 | return -EINVAL; | 1462 | return -EINVAL; |
@@ -1570,7 +1589,8 @@ static ssize_t tunables_write(struct file *file, const char __user *user, | |||
1570 | bcp->complete_threshold = complete_threshold; | 1589 | bcp->complete_threshold = complete_threshold; |
1571 | bcp->cong_response_us = congested_respns_us; | 1590 | bcp->cong_response_us = congested_respns_us; |
1572 | bcp->cong_reps = congested_reps; | 1591 | bcp->cong_reps = congested_reps; |
1573 | bcp->cong_period = congested_period; | 1592 | bcp->disabled_period = sec_2_cycles(disabled_period); |
1593 | bcp->giveup_limit = giveup_limit; | ||
1574 | } | 1594 | } |
1575 | return count; | 1595 | return count; |
1576 | } | 1596 | } |
@@ -1699,6 +1719,10 @@ static void activation_descriptor_init(int node, int pnode, int base_pnode) | |||
1699 | * fairness chaining multilevel count replied_to | 1719 | * fairness chaining multilevel count replied_to |
1700 | */ | 1720 | */ |
1701 | } else { | 1721 | } else { |
1722 | /* | ||
1723 | * BIOS uses legacy mode, but UV2 hardware always | ||
1724 | * uses native mode for selective broadcasts. | ||
1725 | */ | ||
1702 | uv2_hdr = &bd2->header.uv2_hdr; | 1726 | uv2_hdr = &bd2->header.uv2_hdr; |
1703 | uv2_hdr->swack_flag = 1; | 1727 | uv2_hdr->swack_flag = 1; |
1704 | uv2_hdr->base_dest_nasid = | 1728 | uv2_hdr->base_dest_nasid = |
@@ -1811,8 +1835,8 @@ static int calculate_destination_timeout(void) | |||
1811 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; | 1835 | index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK; |
1812 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); | 1836 | mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT); |
1813 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; | 1837 | mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK; |
1814 | base = timeout_base_ns[index]; | 1838 | ts_ns = timeout_base_ns[index]; |
1815 | ts_ns = base * mult1 * mult2; | 1839 | ts_ns *= (mult1 * mult2); |
1816 | ret = ts_ns / 1000; | 1840 | ret = ts_ns / 1000; |
1817 | } else { | 1841 | } else { |
1818 | /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ | 1842 | /* 4 bits 0/1 for 10/80us base, 3 bits of multiplier */ |
@@ -1836,6 +1860,8 @@ static void __init init_per_cpu_tunables(void) | |||
1836 | for_each_present_cpu(cpu) { | 1860 | for_each_present_cpu(cpu) { |
1837 | bcp = &per_cpu(bau_control, cpu); | 1861 | bcp = &per_cpu(bau_control, cpu); |
1838 | bcp->baudisabled = 0; | 1862 | bcp->baudisabled = 0; |
1863 | if (nobau) | ||
1864 | bcp->nobau = 1; | ||
1839 | bcp->statp = &per_cpu(ptcstats, cpu); | 1865 | bcp->statp = &per_cpu(ptcstats, cpu); |
1840 | /* time interval to catch a hardware stay-busy bug */ | 1866 | /* time interval to catch a hardware stay-busy bug */ |
1841 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); | 1867 | bcp->timeout_interval = usec_2_cycles(2*timeout_us); |
@@ -1848,10 +1874,11 @@ static void __init init_per_cpu_tunables(void) | |||
1848 | bcp->complete_threshold = complete_threshold; | 1874 | bcp->complete_threshold = complete_threshold; |
1849 | bcp->cong_response_us = congested_respns_us; | 1875 | bcp->cong_response_us = congested_respns_us; |
1850 | bcp->cong_reps = congested_reps; | 1876 | bcp->cong_reps = congested_reps; |
1851 | bcp->cong_period = congested_period; | 1877 | bcp->disabled_period = sec_2_cycles(disabled_period); |
1852 | bcp->clocks_per_100_usec = usec_2_cycles(100); | 1878 | bcp->giveup_limit = giveup_limit; |
1853 | spin_lock_init(&bcp->queue_lock); | 1879 | spin_lock_init(&bcp->queue_lock); |
1854 | spin_lock_init(&bcp->uvhub_lock); | 1880 | spin_lock_init(&bcp->uvhub_lock); |
1881 | spin_lock_init(&bcp->disable_lock); | ||
1855 | } | 1882 | } |
1856 | } | 1883 | } |
1857 | 1884 | ||
@@ -1972,7 +1999,6 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp, | |||
1972 | } | 1999 | } |
1973 | bcp->uvhub_master = *hmasterp; | 2000 | bcp->uvhub_master = *hmasterp; |
1974 | bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; | 2001 | bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; |
1975 | bcp->using_desc = bcp->uvhub_cpu; | ||
1976 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { | 2002 | if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { |
1977 | printk(KERN_EMERG "%d cpus per uvhub invalid\n", | 2003 | printk(KERN_EMERG "%d cpus per uvhub invalid\n", |
1978 | bcp->uvhub_cpu); | 2004 | bcp->uvhub_cpu); |
@@ -2069,16 +2095,12 @@ static int __init uv_bau_init(void) | |||
2069 | if (!is_uv_system()) | 2095 | if (!is_uv_system()) |
2070 | return 0; | 2096 | return 0; |
2071 | 2097 | ||
2072 | if (nobau) | ||
2073 | return 0; | ||
2074 | |||
2075 | for_each_possible_cpu(cur_cpu) { | 2098 | for_each_possible_cpu(cur_cpu) { |
2076 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); | 2099 | mask = &per_cpu(uv_flush_tlb_mask, cur_cpu); |
2077 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); | 2100 | zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu)); |
2078 | } | 2101 | } |
2079 | 2102 | ||
2080 | nuvhubs = uv_num_possible_blades(); | 2103 | nuvhubs = uv_num_possible_blades(); |
2081 | spin_lock_init(&disable_lock); | ||
2082 | congested_cycles = usec_2_cycles(congested_respns_us); | 2104 | congested_cycles = usec_2_cycles(congested_respns_us); |
2083 | 2105 | ||
2084 | uv_base_pnode = 0x7fffffff; | 2106 | uv_base_pnode = 0x7fffffff; |
@@ -2091,7 +2113,8 @@ static int __init uv_bau_init(void) | |||
2091 | enable_timeouts(); | 2113 | enable_timeouts(); |
2092 | 2114 | ||
2093 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { | 2115 | if (init_per_cpu(nuvhubs, uv_base_pnode)) { |
2094 | nobau = 1; | 2116 | set_bau_off(); |
2117 | nobau_perm = 1; | ||
2095 | return 0; | 2118 | return 0; |
2096 | } | 2119 | } |
2097 | 2120 | ||
diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c index f25c2765a5c9..acf7752da952 100644 --- a/arch/x86/platform/uv/uv_irq.c +++ b/arch/x86/platform/uv/uv_irq.c | |||
@@ -135,6 +135,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |||
135 | unsigned long mmr_value; | 135 | unsigned long mmr_value; |
136 | struct uv_IO_APIC_route_entry *entry; | 136 | struct uv_IO_APIC_route_entry *entry; |
137 | int mmr_pnode, err; | 137 | int mmr_pnode, err; |
138 | unsigned int dest; | ||
138 | 139 | ||
139 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != | 140 | BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != |
140 | sizeof(unsigned long)); | 141 | sizeof(unsigned long)); |
@@ -143,6 +144,10 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |||
143 | if (err != 0) | 144 | if (err != 0) |
144 | return err; | 145 | return err; |
145 | 146 | ||
147 | err = apic->cpu_mask_to_apicid_and(eligible_cpu, eligible_cpu, &dest); | ||
148 | if (err != 0) | ||
149 | return err; | ||
150 | |||
146 | if (limit == UV_AFFINITY_CPU) | 151 | if (limit == UV_AFFINITY_CPU) |
147 | irq_set_status_flags(irq, IRQ_NO_BALANCING); | 152 | irq_set_status_flags(irq, IRQ_NO_BALANCING); |
148 | else | 153 | else |
@@ -159,7 +164,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |||
159 | entry->polarity = 0; | 164 | entry->polarity = 0; |
160 | entry->trigger = 0; | 165 | entry->trigger = 0; |
161 | entry->mask = 0; | 166 | entry->mask = 0; |
162 | entry->dest = apic->cpu_mask_to_apicid(eligible_cpu); | 167 | entry->dest = dest; |
163 | 168 | ||
164 | mmr_pnode = uv_blade_to_pnode(mmr_blade); | 169 | mmr_pnode = uv_blade_to_pnode(mmr_blade); |
165 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); | 170 | uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value); |
@@ -222,7 +227,7 @@ uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask, | |||
222 | if (cfg->move_in_progress) | 227 | if (cfg->move_in_progress) |
223 | send_cleanup_vector(cfg); | 228 | send_cleanup_vector(cfg); |
224 | 229 | ||
225 | return 0; | 230 | return IRQ_SET_MASK_OK_NOCOPY; |
226 | } | 231 | } |
227 | 232 | ||
228 | /* | 233 | /* |
diff --git a/arch/x86/realmode/rm/Makefile b/arch/x86/realmode/rm/Makefile index 5b84a2d30888..b2d534cab25f 100644 --- a/arch/x86/realmode/rm/Makefile +++ b/arch/x86/realmode/rm/Makefile | |||
@@ -22,7 +22,7 @@ wakeup-objs += video-bios.o | |||
22 | realmode-y += header.o | 22 | realmode-y += header.o |
23 | realmode-y += trampoline_$(BITS).o | 23 | realmode-y += trampoline_$(BITS).o |
24 | realmode-y += stack.o | 24 | realmode-y += stack.o |
25 | realmode-$(CONFIG_X86_32) += reboot_32.o | 25 | realmode-y += reboot.o |
26 | realmode-$(CONFIG_ACPI_SLEEP) += $(wakeup-objs) | 26 | realmode-$(CONFIG_ACPI_SLEEP) += $(wakeup-objs) |
27 | 27 | ||
28 | targets += $(realmode-y) | 28 | targets += $(realmode-y) |
diff --git a/arch/x86/realmode/rm/header.S b/arch/x86/realmode/rm/header.S index fadf48378ada..a28221d94e69 100644 --- a/arch/x86/realmode/rm/header.S +++ b/arch/x86/realmode/rm/header.S | |||
@@ -6,6 +6,7 @@ | |||
6 | 6 | ||
7 | #include <linux/linkage.h> | 7 | #include <linux/linkage.h> |
8 | #include <asm/page_types.h> | 8 | #include <asm/page_types.h> |
9 | #include <asm/segment.h> | ||
9 | 10 | ||
10 | #include "realmode.h" | 11 | #include "realmode.h" |
11 | 12 | ||
@@ -28,8 +29,9 @@ GLOBAL(real_mode_header) | |||
28 | .long pa_wakeup_header | 29 | .long pa_wakeup_header |
29 | #endif | 30 | #endif |
30 | /* APM/BIOS reboot */ | 31 | /* APM/BIOS reboot */ |
31 | #ifdef CONFIG_X86_32 | ||
32 | .long pa_machine_real_restart_asm | 32 | .long pa_machine_real_restart_asm |
33 | #ifdef CONFIG_X86_64 | ||
34 | .long __KERNEL32_CS | ||
33 | #endif | 35 | #endif |
34 | END(real_mode_header) | 36 | END(real_mode_header) |
35 | 37 | ||
diff --git a/arch/x86/realmode/rm/reboot_32.S b/arch/x86/realmode/rm/reboot.S index 114044876b3d..f932ea61d1c8 100644 --- a/arch/x86/realmode/rm/reboot_32.S +++ b/arch/x86/realmode/rm/reboot.S | |||
@@ -2,6 +2,8 @@ | |||
2 | #include <linux/init.h> | 2 | #include <linux/init.h> |
3 | #include <asm/segment.h> | 3 | #include <asm/segment.h> |
4 | #include <asm/page_types.h> | 4 | #include <asm/page_types.h> |
5 | #include <asm/processor-flags.h> | ||
6 | #include <asm/msr-index.h> | ||
5 | #include "realmode.h" | 7 | #include "realmode.h" |
6 | 8 | ||
7 | /* | 9 | /* |
@@ -12,13 +14,35 @@ | |||
12 | * doesn't work with at least one type of 486 motherboard. It is easy | 14 | * doesn't work with at least one type of 486 motherboard. It is easy |
13 | * to stop this code working; hence the copious comments. | 15 | * to stop this code working; hence the copious comments. |
14 | * | 16 | * |
15 | * This code is called with the restart type (0 = BIOS, 1 = APM) in %eax. | 17 | * This code is called with the restart type (0 = BIOS, 1 = APM) in |
18 | * the primary argument register (%eax for 32 bit, %edi for 64 bit). | ||
16 | */ | 19 | */ |
17 | .section ".text32", "ax" | 20 | .section ".text32", "ax" |
18 | .code32 | 21 | .code32 |
19 | |||
20 | .balign 16 | ||
21 | ENTRY(machine_real_restart_asm) | 22 | ENTRY(machine_real_restart_asm) |
23 | |||
24 | #ifdef CONFIG_X86_64 | ||
25 | /* Switch to trampoline GDT as it is guaranteed < 4 GiB */ | ||
26 | movl $__KERNEL_DS, %eax | ||
27 | movl %eax, %ds | ||
28 | lgdtl pa_tr_gdt | ||
29 | |||
30 | /* Disable paging to drop us out of long mode */ | ||
31 | movl %cr0, %eax | ||
32 | andl $~X86_CR0_PG, %eax | ||
33 | movl %eax, %cr0 | ||
34 | ljmpl $__KERNEL32_CS, $pa_machine_real_restart_paging_off | ||
35 | |||
36 | GLOBAL(machine_real_restart_paging_off) | ||
37 | xorl %eax, %eax | ||
38 | xorl %edx, %edx | ||
39 | movl $MSR_EFER, %ecx | ||
40 | wrmsr | ||
41 | |||
42 | movl %edi, %eax | ||
43 | |||
44 | #endif /* CONFIG_X86_64 */ | ||
45 | |||
22 | /* Set up the IDT for real mode. */ | 46 | /* Set up the IDT for real mode. */ |
23 | lidtl pa_machine_real_restart_idt | 47 | lidtl pa_machine_real_restart_idt |
24 | 48 | ||
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c index 66e6d9359826..0faad646f5fd 100644 --- a/arch/x86/vdso/vdso32-setup.c +++ b/arch/x86/vdso/vdso32-setup.c | |||
@@ -205,9 +205,9 @@ void syscall32_cpu_init(void) | |||
205 | { | 205 | { |
206 | /* Load these always in case some future AMD CPU supports | 206 | /* Load these always in case some future AMD CPU supports |
207 | SYSENTER from compat mode too. */ | 207 | SYSENTER from compat mode too. */ |
208 | checking_wrmsrl(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | 208 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); |
209 | checking_wrmsrl(MSR_IA32_SYSENTER_ESP, 0ULL); | 209 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
210 | checking_wrmsrl(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); | 210 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target); |
211 | 211 | ||
212 | wrmsrl(MSR_CSTAR, ia32_cstar_target); | 212 | wrmsrl(MSR_CSTAR, ia32_cstar_target); |
213 | } | 213 | } |
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index ff962d4b821e..ed7d54985d0c 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c | |||
@@ -1124,9 +1124,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = { | |||
1124 | .wbinvd = native_wbinvd, | 1124 | .wbinvd = native_wbinvd, |
1125 | 1125 | ||
1126 | .read_msr = native_read_msr_safe, | 1126 | .read_msr = native_read_msr_safe, |
1127 | .rdmsr_regs = native_rdmsr_safe_regs, | ||
1128 | .write_msr = xen_write_msr_safe, | 1127 | .write_msr = xen_write_msr_safe, |
1129 | .wrmsr_regs = native_wrmsr_safe_regs, | ||
1130 | 1128 | ||
1131 | .read_tsc = native_read_tsc, | 1129 | .read_tsc = native_read_tsc, |
1132 | .read_pmc = native_read_pmc, | 1130 | .read_pmc = native_read_pmc, |
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c index afb250d22a6b..f58dca7a6e52 100644 --- a/arch/x86/xen/smp.c +++ b/arch/x86/xen/smp.c | |||
@@ -80,9 +80,7 @@ static void __cpuinit cpu_bringup(void) | |||
80 | 80 | ||
81 | notify_cpu_starting(cpu); | 81 | notify_cpu_starting(cpu); |
82 | 82 | ||
83 | ipi_call_lock(); | ||
84 | set_cpu_online(cpu, true); | 83 | set_cpu_online(cpu, true); |
85 | ipi_call_unlock(); | ||
86 | 84 | ||
87 | this_cpu_write(cpu_state, CPU_ONLINE); | 85 | this_cpu_write(cpu_state, CPU_ONLINE); |
88 | 86 | ||
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c index 9b306e550e3f..2c8d6a3d250a 100644 --- a/arch/xtensa/kernel/process.c +++ b/arch/xtensa/kernel/process.c | |||
@@ -277,7 +277,7 @@ void xtensa_elf_core_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs) | |||
277 | 277 | ||
278 | /* Don't leak any random bits. */ | 278 | /* Don't leak any random bits. */ |
279 | 279 | ||
280 | memset(elfregs, 0, sizeof (elfregs)); | 280 | memset(elfregs, 0, sizeof(*elfregs)); |
281 | 281 | ||
282 | /* Note: PS.EXCM is not set while user task is running; its | 282 | /* Note: PS.EXCM is not set while user task is running; its |
283 | * being set in regs->ps is for exception handling convenience. | 283 | * being set in regs->ps is for exception handling convenience. |